SAME54P20A Test Project
same54n19a.h
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1 
30 #ifndef _SAME54N19A_
31 #define _SAME54N19A_
32 
43 
44 #ifdef __cplusplus
45  extern "C" {
46 #endif
47 
48 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
49 #include <stdint.h>
50 #ifndef __cplusplus
51 typedef volatile const uint32_t RoReg;
52 typedef volatile const uint16_t RoReg16;
53 typedef volatile const uint8_t RoReg8;
54 #else
55 typedef volatile uint32_t RoReg;
56 typedef volatile uint16_t RoReg16;
57 typedef volatile uint8_t RoReg8;
58 #endif
59 typedef volatile uint32_t WoReg;
60 typedef volatile uint16_t WoReg16;
61 typedef volatile uint8_t WoReg8;
62 typedef volatile uint32_t RwReg;
63 typedef volatile uint16_t RwReg16;
64 typedef volatile uint8_t RwReg8;
65 #endif
66 
67 #if !defined(SKIP_INTEGER_LITERALS)
68 #if defined(_U_) || defined(_L_) || defined(_UL_)
69  #error "Integer Literals macros already defined elsewhere"
70 #endif
71 
72 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
73 /* Macros that deal with adding suffixes to integer literal constants for C/C++ */
74 #define _U_(x) x ## U
75 #define _L_(x) x ## L
76 #define _UL_(x) x ## UL
77 #else /* Assembler */
78 #define _U_(x) x
79 #define _L_(x) x
80 #define _UL_(x) x
81 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
82 #endif /* SKIP_INTEGER_LITERALS */
83 
84 /* ************************************************************************** */
86 /* ************************************************************************** */
89 
91 typedef enum IRQn
92 {
93  /****** Cortex-M4 Processor Exceptions Numbers *******************/
94  NonMaskableInt_IRQn = -14,
95  HardFault_IRQn = -13,
96  MemoryManagement_IRQn = -12,
97  BusFault_IRQn = -11,
98  UsageFault_IRQn = -10,
99  SVCall_IRQn = -5,
100  DebugMonitor_IRQn = -4,
101  PendSV_IRQn = -2,
102  SysTick_IRQn = -1,
103  /****** SAME54N19A-specific Interrupt Numbers *********************/
104  PM_IRQn = 0,
105  MCLK_IRQn = 1,
106  OSCCTRL_0_IRQn = 2,
107  OSCCTRL_1_IRQn = 3,
108  OSCCTRL_2_IRQn = 4,
109  OSCCTRL_3_IRQn = 5,
110  OSCCTRL_4_IRQn = 6,
111  OSC32KCTRL_IRQn = 7,
112  SUPC_0_IRQn = 8,
113  SUPC_1_IRQn = 9,
114  WDT_IRQn = 10,
115  RTC_IRQn = 11,
116  EIC_0_IRQn = 12,
117  EIC_1_IRQn = 13,
118  EIC_2_IRQn = 14,
119  EIC_3_IRQn = 15,
120  EIC_4_IRQn = 16,
121  EIC_5_IRQn = 17,
122  EIC_6_IRQn = 18,
123  EIC_7_IRQn = 19,
124  EIC_8_IRQn = 20,
125  EIC_9_IRQn = 21,
126  EIC_10_IRQn = 22,
127  EIC_11_IRQn = 23,
128  EIC_12_IRQn = 24,
129  EIC_13_IRQn = 25,
130  EIC_14_IRQn = 26,
131  EIC_15_IRQn = 27,
132  FREQM_IRQn = 28,
133  NVMCTRL_0_IRQn = 29,
134  NVMCTRL_1_IRQn = 30,
135  DMAC_0_IRQn = 31,
136  DMAC_1_IRQn = 32,
137  DMAC_2_IRQn = 33,
138  DMAC_3_IRQn = 34,
139  DMAC_4_IRQn = 35,
140  EVSYS_0_IRQn = 36,
141  EVSYS_1_IRQn = 37,
142  EVSYS_2_IRQn = 38,
143  EVSYS_3_IRQn = 39,
144  EVSYS_4_IRQn = 40,
145  PAC_IRQn = 41,
146  RAMECC_IRQn = 45,
147  SERCOM0_0_IRQn = 46,
148  SERCOM0_1_IRQn = 47,
149  SERCOM0_2_IRQn = 48,
150  SERCOM0_3_IRQn = 49,
151  SERCOM1_0_IRQn = 50,
152  SERCOM1_1_IRQn = 51,
153  SERCOM1_2_IRQn = 52,
154  SERCOM1_3_IRQn = 53,
155  SERCOM2_0_IRQn = 54,
156  SERCOM2_1_IRQn = 55,
157  SERCOM2_2_IRQn = 56,
158  SERCOM2_3_IRQn = 57,
159  SERCOM3_0_IRQn = 58,
160  SERCOM3_1_IRQn = 59,
161  SERCOM3_2_IRQn = 60,
162  SERCOM3_3_IRQn = 61,
163  SERCOM4_0_IRQn = 62,
164  SERCOM4_1_IRQn = 63,
165  SERCOM4_2_IRQn = 64,
166  SERCOM4_3_IRQn = 65,
167  SERCOM5_0_IRQn = 66,
168  SERCOM5_1_IRQn = 67,
169  SERCOM5_2_IRQn = 68,
170  SERCOM5_3_IRQn = 69,
171  SERCOM6_0_IRQn = 70,
172  SERCOM6_1_IRQn = 71,
173  SERCOM6_2_IRQn = 72,
174  SERCOM6_3_IRQn = 73,
175  SERCOM7_0_IRQn = 74,
176  SERCOM7_1_IRQn = 75,
177  SERCOM7_2_IRQn = 76,
178  SERCOM7_3_IRQn = 77,
179  CAN0_IRQn = 78,
180  CAN1_IRQn = 79,
181  USB_0_IRQn = 80,
182  USB_1_IRQn = 81,
183  USB_2_IRQn = 82,
184  USB_3_IRQn = 83,
185  GMAC_IRQn = 84,
186  TCC0_0_IRQn = 85,
187  TCC0_1_IRQn = 86,
188  TCC0_2_IRQn = 87,
189  TCC0_3_IRQn = 88,
190  TCC0_4_IRQn = 89,
191  TCC0_5_IRQn = 90,
192  TCC0_6_IRQn = 91,
193  TCC1_0_IRQn = 92,
194  TCC1_1_IRQn = 93,
195  TCC1_2_IRQn = 94,
196  TCC1_3_IRQn = 95,
197  TCC1_4_IRQn = 96,
198  TCC2_0_IRQn = 97,
199  TCC2_1_IRQn = 98,
200  TCC2_2_IRQn = 99,
201  TCC2_3_IRQn = 100,
202  TCC3_0_IRQn = 101,
203  TCC3_1_IRQn = 102,
204  TCC3_2_IRQn = 103,
205  TCC4_0_IRQn = 104,
206  TCC4_1_IRQn = 105,
207  TCC4_2_IRQn = 106,
208  TC0_IRQn = 107,
209  TC1_IRQn = 108,
210  TC2_IRQn = 109,
211  TC3_IRQn = 110,
212  TC4_IRQn = 111,
213  TC5_IRQn = 112,
214  TC6_IRQn = 113,
215  TC7_IRQn = 114,
216  PDEC_0_IRQn = 115,
217  PDEC_1_IRQn = 116,
218  PDEC_2_IRQn = 117,
219  ADC0_0_IRQn = 118,
220  ADC0_1_IRQn = 119,
221  ADC1_0_IRQn = 120,
222  ADC1_1_IRQn = 121,
223  AC_IRQn = 122,
224  DAC_0_IRQn = 123,
225  DAC_1_IRQn = 124,
226  DAC_2_IRQn = 125,
227  DAC_3_IRQn = 126,
228  DAC_4_IRQn = 127,
229  I2S_IRQn = 128,
230  PCC_IRQn = 129,
231  AES_IRQn = 130,
232  TRNG_IRQn = 131,
233  ICM_IRQn = 132,
234  PUKCC_IRQn = 133,
235  QSPI_IRQn = 134,
236  SDHC0_IRQn = 135,
237  SDHC1_IRQn = 136,
239  PERIPH_COUNT_IRQn = 137
240 } IRQn_Type;
241 
242 typedef struct _DeviceVectors
243 {
244  /* Stack pointer */
245  void* pvStack;
246 
247  /* Cortex-M handlers */
248  void* pfnReset_Handler;
249  void* pfnNonMaskableInt_Handler;
250  void* pfnHardFault_Handler;
251  void* pfnMemManagement_Handler;
252  void* pfnBusFault_Handler;
253  void* pfnUsageFault_Handler;
254  void* pvReservedM9;
255  void* pvReservedM8;
256  void* pvReservedM7;
257  void* pvReservedM6;
258  void* pfnSVCall_Handler;
259  void* pfnDebugMonitor_Handler;
260  void* pvReservedM3;
261  void* pfnPendSV_Handler;
262  void* pfnSysTick_Handler;
263 
264  /* Peripheral handlers */
265  void* pfnPM_Handler; /* 0 Power Manager */
266  void* pfnMCLK_Handler; /* 1 Main Clock */
267  void* pfnOSCCTRL_0_Handler; /* 2 Oscillators Control IRQ 0 */
268  void* pfnOSCCTRL_1_Handler; /* 3 Oscillators Control IRQ 1 */
269  void* pfnOSCCTRL_2_Handler; /* 4 Oscillators Control IRQ 2 */
270  void* pfnOSCCTRL_3_Handler; /* 5 Oscillators Control IRQ 3 */
271  void* pfnOSCCTRL_4_Handler; /* 6 Oscillators Control IRQ 4 */
272  void* pfnOSC32KCTRL_Handler; /* 7 32kHz Oscillators Control */
273  void* pfnSUPC_0_Handler; /* 8 Supply Controller IRQ 0 */
274  void* pfnSUPC_1_Handler; /* 9 Supply Controller IRQ 1 */
275  void* pfnWDT_Handler; /* 10 Watchdog Timer */
276  void* pfnRTC_Handler; /* 11 Real-Time Counter */
277  void* pfnEIC_0_Handler; /* 12 External Interrupt Controller IRQ 0 */
278  void* pfnEIC_1_Handler; /* 13 External Interrupt Controller IRQ 1 */
279  void* pfnEIC_2_Handler; /* 14 External Interrupt Controller IRQ 2 */
280  void* pfnEIC_3_Handler; /* 15 External Interrupt Controller IRQ 3 */
281  void* pfnEIC_4_Handler; /* 16 External Interrupt Controller IRQ 4 */
282  void* pfnEIC_5_Handler; /* 17 External Interrupt Controller IRQ 5 */
283  void* pfnEIC_6_Handler; /* 18 External Interrupt Controller IRQ 6 */
284  void* pfnEIC_7_Handler; /* 19 External Interrupt Controller IRQ 7 */
285  void* pfnEIC_8_Handler; /* 20 External Interrupt Controller IRQ 8 */
286  void* pfnEIC_9_Handler; /* 21 External Interrupt Controller IRQ 9 */
287  void* pfnEIC_10_Handler; /* 22 External Interrupt Controller IRQ 10 */
288  void* pfnEIC_11_Handler; /* 23 External Interrupt Controller IRQ 11 */
289  void* pfnEIC_12_Handler; /* 24 External Interrupt Controller IRQ 12 */
290  void* pfnEIC_13_Handler; /* 25 External Interrupt Controller IRQ 13 */
291  void* pfnEIC_14_Handler; /* 26 External Interrupt Controller IRQ 14 */
292  void* pfnEIC_15_Handler; /* 27 External Interrupt Controller IRQ 15 */
293  void* pfnFREQM_Handler; /* 28 Frequency Meter */
294  void* pfnNVMCTRL_0_Handler; /* 29 Non-Volatile Memory Controller IRQ 0 */
295  void* pfnNVMCTRL_1_Handler; /* 30 Non-Volatile Memory Controller IRQ 1 */
296  void* pfnDMAC_0_Handler; /* 31 Direct Memory Access Controller IRQ 0 */
297  void* pfnDMAC_1_Handler; /* 32 Direct Memory Access Controller IRQ 1 */
298  void* pfnDMAC_2_Handler; /* 33 Direct Memory Access Controller IRQ 2 */
299  void* pfnDMAC_3_Handler; /* 34 Direct Memory Access Controller IRQ 3 */
300  void* pfnDMAC_4_Handler; /* 35 Direct Memory Access Controller IRQ 4 */
301  void* pfnEVSYS_0_Handler; /* 36 Event System Interface IRQ 0 */
302  void* pfnEVSYS_1_Handler; /* 37 Event System Interface IRQ 1 */
303  void* pfnEVSYS_2_Handler; /* 38 Event System Interface IRQ 2 */
304  void* pfnEVSYS_3_Handler; /* 39 Event System Interface IRQ 3 */
305  void* pfnEVSYS_4_Handler; /* 40 Event System Interface IRQ 4 */
306  void* pfnPAC_Handler; /* 41 Peripheral Access Controller */
307  void* pvReserved42;
308  void* pvReserved43;
309  void* pvReserved44;
310  void* pfnRAMECC_Handler; /* 45 RAM ECC */
311  void* pfnSERCOM0_0_Handler; /* 46 Serial Communication Interface 0 IRQ 0 */
312  void* pfnSERCOM0_1_Handler; /* 47 Serial Communication Interface 0 IRQ 1 */
313  void* pfnSERCOM0_2_Handler; /* 48 Serial Communication Interface 0 IRQ 2 */
314  void* pfnSERCOM0_3_Handler; /* 49 Serial Communication Interface 0 IRQ 3 */
315  void* pfnSERCOM1_0_Handler; /* 50 Serial Communication Interface 1 IRQ 0 */
316  void* pfnSERCOM1_1_Handler; /* 51 Serial Communication Interface 1 IRQ 1 */
317  void* pfnSERCOM1_2_Handler; /* 52 Serial Communication Interface 1 IRQ 2 */
318  void* pfnSERCOM1_3_Handler; /* 53 Serial Communication Interface 1 IRQ 3 */
319  void* pfnSERCOM2_0_Handler; /* 54 Serial Communication Interface 2 IRQ 0 */
320  void* pfnSERCOM2_1_Handler; /* 55 Serial Communication Interface 2 IRQ 1 */
321  void* pfnSERCOM2_2_Handler; /* 56 Serial Communication Interface 2 IRQ 2 */
322  void* pfnSERCOM2_3_Handler; /* 57 Serial Communication Interface 2 IRQ 3 */
323  void* pfnSERCOM3_0_Handler; /* 58 Serial Communication Interface 3 IRQ 0 */
324  void* pfnSERCOM3_1_Handler; /* 59 Serial Communication Interface 3 IRQ 1 */
325  void* pfnSERCOM3_2_Handler; /* 60 Serial Communication Interface 3 IRQ 2 */
326  void* pfnSERCOM3_3_Handler; /* 61 Serial Communication Interface 3 IRQ 3 */
327  void* pfnSERCOM4_0_Handler; /* 62 Serial Communication Interface 4 IRQ 0 */
328  void* pfnSERCOM4_1_Handler; /* 63 Serial Communication Interface 4 IRQ 1 */
329  void* pfnSERCOM4_2_Handler; /* 64 Serial Communication Interface 4 IRQ 2 */
330  void* pfnSERCOM4_3_Handler; /* 65 Serial Communication Interface 4 IRQ 3 */
331  void* pfnSERCOM5_0_Handler; /* 66 Serial Communication Interface 5 IRQ 0 */
332  void* pfnSERCOM5_1_Handler; /* 67 Serial Communication Interface 5 IRQ 1 */
333  void* pfnSERCOM5_2_Handler; /* 68 Serial Communication Interface 5 IRQ 2 */
334  void* pfnSERCOM5_3_Handler; /* 69 Serial Communication Interface 5 IRQ 3 */
335  void* pfnSERCOM6_0_Handler; /* 70 Serial Communication Interface 6 IRQ 0 */
336  void* pfnSERCOM6_1_Handler; /* 71 Serial Communication Interface 6 IRQ 1 */
337  void* pfnSERCOM6_2_Handler; /* 72 Serial Communication Interface 6 IRQ 2 */
338  void* pfnSERCOM6_3_Handler; /* 73 Serial Communication Interface 6 IRQ 3 */
339  void* pfnSERCOM7_0_Handler; /* 74 Serial Communication Interface 7 IRQ 0 */
340  void* pfnSERCOM7_1_Handler; /* 75 Serial Communication Interface 7 IRQ 1 */
341  void* pfnSERCOM7_2_Handler; /* 76 Serial Communication Interface 7 IRQ 2 */
342  void* pfnSERCOM7_3_Handler; /* 77 Serial Communication Interface 7 IRQ 3 */
343  void* pfnCAN0_Handler; /* 78 Control Area Network 0 */
344  void* pfnCAN1_Handler; /* 79 Control Area Network 1 */
345  void* pfnUSB_0_Handler; /* 80 Universal Serial Bus IRQ 0 */
346  void* pfnUSB_1_Handler; /* 81 Universal Serial Bus IRQ 1 */
347  void* pfnUSB_2_Handler; /* 82 Universal Serial Bus IRQ 2 */
348  void* pfnUSB_3_Handler; /* 83 Universal Serial Bus IRQ 3 */
349  void* pfnGMAC_Handler; /* 84 Ethernet MAC */
350  void* pfnTCC0_0_Handler; /* 85 Timer Counter Control 0 IRQ 0 */
351  void* pfnTCC0_1_Handler; /* 86 Timer Counter Control 0 IRQ 1 */
352  void* pfnTCC0_2_Handler; /* 87 Timer Counter Control 0 IRQ 2 */
353  void* pfnTCC0_3_Handler; /* 88 Timer Counter Control 0 IRQ 3 */
354  void* pfnTCC0_4_Handler; /* 89 Timer Counter Control 0 IRQ 4 */
355  void* pfnTCC0_5_Handler; /* 90 Timer Counter Control 0 IRQ 5 */
356  void* pfnTCC0_6_Handler; /* 91 Timer Counter Control 0 IRQ 6 */
357  void* pfnTCC1_0_Handler; /* 92 Timer Counter Control 1 IRQ 0 */
358  void* pfnTCC1_1_Handler; /* 93 Timer Counter Control 1 IRQ 1 */
359  void* pfnTCC1_2_Handler; /* 94 Timer Counter Control 1 IRQ 2 */
360  void* pfnTCC1_3_Handler; /* 95 Timer Counter Control 1 IRQ 3 */
361  void* pfnTCC1_4_Handler; /* 96 Timer Counter Control 1 IRQ 4 */
362  void* pfnTCC2_0_Handler; /* 97 Timer Counter Control 2 IRQ 0 */
363  void* pfnTCC2_1_Handler; /* 98 Timer Counter Control 2 IRQ 1 */
364  void* pfnTCC2_2_Handler; /* 99 Timer Counter Control 2 IRQ 2 */
365  void* pfnTCC2_3_Handler; /* 100 Timer Counter Control 2 IRQ 3 */
366  void* pfnTCC3_0_Handler; /* 101 Timer Counter Control 3 IRQ 0 */
367  void* pfnTCC3_1_Handler; /* 102 Timer Counter Control 3 IRQ 1 */
368  void* pfnTCC3_2_Handler; /* 103 Timer Counter Control 3 IRQ 2 */
369  void* pfnTCC4_0_Handler; /* 104 Timer Counter Control 4 IRQ 0 */
370  void* pfnTCC4_1_Handler; /* 105 Timer Counter Control 4 IRQ 1 */
371  void* pfnTCC4_2_Handler; /* 106 Timer Counter Control 4 IRQ 2 */
372  void* pfnTC0_Handler; /* 107 Basic Timer Counter 0 */
373  void* pfnTC1_Handler; /* 108 Basic Timer Counter 1 */
374  void* pfnTC2_Handler; /* 109 Basic Timer Counter 2 */
375  void* pfnTC3_Handler; /* 110 Basic Timer Counter 3 */
376  void* pfnTC4_Handler; /* 111 Basic Timer Counter 4 */
377  void* pfnTC5_Handler; /* 112 Basic Timer Counter 5 */
378  void* pfnTC6_Handler; /* 113 Basic Timer Counter 6 */
379  void* pfnTC7_Handler; /* 114 Basic Timer Counter 7 */
380  void* pfnPDEC_0_Handler; /* 115 Quadrature Decodeur IRQ 0 */
381  void* pfnPDEC_1_Handler; /* 116 Quadrature Decodeur IRQ 1 */
382  void* pfnPDEC_2_Handler; /* 117 Quadrature Decodeur IRQ 2 */
383  void* pfnADC0_0_Handler; /* 118 Analog Digital Converter 0 IRQ 0 */
384  void* pfnADC0_1_Handler; /* 119 Analog Digital Converter 0 IRQ 1 */
385  void* pfnADC1_0_Handler; /* 120 Analog Digital Converter 1 IRQ 0 */
386  void* pfnADC1_1_Handler; /* 121 Analog Digital Converter 1 IRQ 1 */
387  void* pfnAC_Handler; /* 122 Analog Comparators */
388  void* pfnDAC_0_Handler; /* 123 Digital-to-Analog Converter IRQ 0 */
389  void* pfnDAC_1_Handler; /* 124 Digital-to-Analog Converter IRQ 1 */
390  void* pfnDAC_2_Handler; /* 125 Digital-to-Analog Converter IRQ 2 */
391  void* pfnDAC_3_Handler; /* 126 Digital-to-Analog Converter IRQ 3 */
392  void* pfnDAC_4_Handler; /* 127 Digital-to-Analog Converter IRQ 4 */
393  void* pfnI2S_Handler; /* 128 Inter-IC Sound Interface */
394  void* pfnPCC_Handler; /* 129 Parallel Capture Controller */
395  void* pfnAES_Handler; /* 130 Advanced Encryption Standard */
396  void* pfnTRNG_Handler; /* 131 True Random Generator */
397  void* pfnICM_Handler; /* 132 Integrity Check Monitor */
398  void* pfnPUKCC_Handler; /* 133 PUblic-Key Cryptography Controller */
399  void* pfnQSPI_Handler; /* 134 Quad SPI interface */
400  void* pfnSDHC0_Handler; /* 135 SD/MMC Host Controller 0 */
401  void* pfnSDHC1_Handler; /* 136 SD/MMC Host Controller 1 */
402 } DeviceVectors;
403 
404 /* Cortex-M4 processor handlers */
405 void Reset_Handler ( void );
406 void NonMaskableInt_Handler ( void );
407 void HardFault_Handler ( void );
408 void MemManagement_Handler ( void );
409 void BusFault_Handler ( void );
410 void UsageFault_Handler ( void );
411 void SVCall_Handler ( void );
412 void DebugMonitor_Handler ( void );
413 void PendSV_Handler ( void );
414 void SysTick_Handler ( void );
415 
416 /* Peripherals handlers */
417 void PM_Handler ( void );
418 void MCLK_Handler ( void );
419 void OSCCTRL_0_Handler ( void );
420 void OSCCTRL_1_Handler ( void );
421 void OSCCTRL_2_Handler ( void );
422 void OSCCTRL_3_Handler ( void );
423 void OSCCTRL_4_Handler ( void );
424 void OSC32KCTRL_Handler ( void );
425 void SUPC_0_Handler ( void );
426 void SUPC_1_Handler ( void );
427 void WDT_Handler ( void );
428 void RTC_Handler ( void );
429 void EIC_0_Handler ( void );
430 void EIC_1_Handler ( void );
431 void EIC_2_Handler ( void );
432 void EIC_3_Handler ( void );
433 void EIC_4_Handler ( void );
434 void EIC_5_Handler ( void );
435 void EIC_6_Handler ( void );
436 void EIC_7_Handler ( void );
437 void EIC_8_Handler ( void );
438 void EIC_9_Handler ( void );
439 void EIC_10_Handler ( void );
440 void EIC_11_Handler ( void );
441 void EIC_12_Handler ( void );
442 void EIC_13_Handler ( void );
443 void EIC_14_Handler ( void );
444 void EIC_15_Handler ( void );
445 void FREQM_Handler ( void );
446 void NVMCTRL_0_Handler ( void );
447 void NVMCTRL_1_Handler ( void );
448 void DMAC_0_Handler ( void );
449 void DMAC_1_Handler ( void );
450 void DMAC_2_Handler ( void );
451 void DMAC_3_Handler ( void );
452 void DMAC_4_Handler ( void );
453 void EVSYS_0_Handler ( void );
454 void EVSYS_1_Handler ( void );
455 void EVSYS_2_Handler ( void );
456 void EVSYS_3_Handler ( void );
457 void EVSYS_4_Handler ( void );
458 void PAC_Handler ( void );
459 void RAMECC_Handler ( void );
460 void SERCOM0_0_Handler ( void );
461 void SERCOM0_1_Handler ( void );
462 void SERCOM0_2_Handler ( void );
463 void SERCOM0_3_Handler ( void );
464 void SERCOM1_0_Handler ( void );
465 void SERCOM1_1_Handler ( void );
466 void SERCOM1_2_Handler ( void );
467 void SERCOM1_3_Handler ( void );
468 void SERCOM2_0_Handler ( void );
469 void SERCOM2_1_Handler ( void );
470 void SERCOM2_2_Handler ( void );
471 void SERCOM2_3_Handler ( void );
472 void SERCOM3_0_Handler ( void );
473 void SERCOM3_1_Handler ( void );
474 void SERCOM3_2_Handler ( void );
475 void SERCOM3_3_Handler ( void );
476 void SERCOM4_0_Handler ( void );
477 void SERCOM4_1_Handler ( void );
478 void SERCOM4_2_Handler ( void );
479 void SERCOM4_3_Handler ( void );
480 void SERCOM5_0_Handler ( void );
481 void SERCOM5_1_Handler ( void );
482 void SERCOM5_2_Handler ( void );
483 void SERCOM5_3_Handler ( void );
484 void SERCOM6_0_Handler ( void );
485 void SERCOM6_1_Handler ( void );
486 void SERCOM6_2_Handler ( void );
487 void SERCOM6_3_Handler ( void );
488 void SERCOM7_0_Handler ( void );
489 void SERCOM7_1_Handler ( void );
490 void SERCOM7_2_Handler ( void );
491 void SERCOM7_3_Handler ( void );
492 void CAN0_Handler ( void );
493 void CAN1_Handler ( void );
494 void USB_0_Handler ( void );
495 void USB_1_Handler ( void );
496 void USB_2_Handler ( void );
497 void USB_3_Handler ( void );
498 void GMAC_Handler ( void );
499 void TCC0_0_Handler ( void );
500 void TCC0_1_Handler ( void );
501 void TCC0_2_Handler ( void );
502 void TCC0_3_Handler ( void );
503 void TCC0_4_Handler ( void );
504 void TCC0_5_Handler ( void );
505 void TCC0_6_Handler ( void );
506 void TCC1_0_Handler ( void );
507 void TCC1_1_Handler ( void );
508 void TCC1_2_Handler ( void );
509 void TCC1_3_Handler ( void );
510 void TCC1_4_Handler ( void );
511 void TCC2_0_Handler ( void );
512 void TCC2_1_Handler ( void );
513 void TCC2_2_Handler ( void );
514 void TCC2_3_Handler ( void );
515 void TCC3_0_Handler ( void );
516 void TCC3_1_Handler ( void );
517 void TCC3_2_Handler ( void );
518 void TCC4_0_Handler ( void );
519 void TCC4_1_Handler ( void );
520 void TCC4_2_Handler ( void );
521 void TC0_Handler ( void );
522 void TC1_Handler ( void );
523 void TC2_Handler ( void );
524 void TC3_Handler ( void );
525 void TC4_Handler ( void );
526 void TC5_Handler ( void );
527 void TC6_Handler ( void );
528 void TC7_Handler ( void );
529 void PDEC_0_Handler ( void );
530 void PDEC_1_Handler ( void );
531 void PDEC_2_Handler ( void );
532 void ADC0_0_Handler ( void );
533 void ADC0_1_Handler ( void );
534 void ADC1_0_Handler ( void );
535 void ADC1_1_Handler ( void );
536 void AC_Handler ( void );
537 void DAC_0_Handler ( void );
538 void DAC_1_Handler ( void );
539 void DAC_2_Handler ( void );
540 void DAC_3_Handler ( void );
541 void DAC_4_Handler ( void );
542 void I2S_Handler ( void );
543 void PCC_Handler ( void );
544 void AES_Handler ( void );
545 void TRNG_Handler ( void );
546 void ICM_Handler ( void );
547 void PUKCC_Handler ( void );
548 void QSPI_Handler ( void );
549 void SDHC0_Handler ( void );
550 void SDHC1_Handler ( void );
551 
552 /*
553  * \brief Configuration of the Cortex-M4 Processor and Core Peripherals
554  */
555 
556 #define __CM4_REV 1
557 #define __DEBUG_LVL 3
558 #define __FPU_PRESENT 1
559 #define __MPU_PRESENT 1
560 #define __NVIC_PRIO_BITS 3
561 #define __TRACE_LVL 2
562 #define __VTOR_PRESENT 1
563 #define __Vendor_SysTickConfig 0
569 #include <core_cm4.h>
570 #if !defined DONT_USE_CMSIS_INIT
571 #include "system_same54.h"
572 #endif /* DONT_USE_CMSIS_INIT */
573 
576 /* ************************************************************************** */
578 /* ************************************************************************** */
581 
582 #include "component/ac.h"
583 #include "component/adc.h"
584 #include "component/aes.h"
585 #include "component/can.h"
586 #include "component/ccl.h"
587 #include "component/cmcc.h"
588 #include "component/dac.h"
589 #include "component/dmac.h"
590 #include "component/dsu.h"
591 #include "component/eic.h"
592 #include "component/evsys.h"
593 #include "component/freqm.h"
594 #include "component/gclk.h"
595 #include "component/gmac.h"
596 #include "component/hmatrixb.h"
597 #include "component/icm.h"
598 #include "component/i2s.h"
599 #include "component/mclk.h"
600 #include "component/nvmctrl.h"
601 #include "component/oscctrl.h"
602 #include "component/osc32kctrl.h"
603 #include "component/pac.h"
604 #include "component/pcc.h"
605 #include "component/pdec.h"
606 #include "component/pm.h"
607 #include "component/port.h"
608 #include "component/qspi.h"
609 #include "component/ramecc.h"
610 #include "component/rstc.h"
611 #include "component/rtc.h"
612 #include "component/sdhc.h"
613 #include "component/sercom.h"
614 #include "component/supc.h"
615 #include "component/tc.h"
616 #include "component/tcc.h"
617 #include "component/trng.h"
618 #include "component/usb.h"
619 #include "component/wdt.h"
622 /* ************************************************************************** */
624 /* ************************************************************************** */
627 
628 #include "instance/ac.h"
629 #include "instance/adc0.h"
630 #include "instance/adc1.h"
631 #include "instance/aes.h"
632 #include "instance/can0.h"
633 #include "instance/can1.h"
634 #include "instance/ccl.h"
635 #include "instance/cmcc.h"
636 #include "instance/dac.h"
637 #include "instance/dmac.h"
638 #include "instance/dsu.h"
639 #include "instance/eic.h"
640 #include "instance/evsys.h"
641 #include "instance/freqm.h"
642 #include "instance/gclk.h"
643 #include "instance/gmac.h"
644 #include "instance/hmatrix.h"
645 #include "instance/icm.h"
646 #include "instance/i2s.h"
647 #include "instance/mclk.h"
648 #include "instance/nvmctrl.h"
649 #include "instance/oscctrl.h"
650 #include "instance/osc32kctrl.h"
651 #include "instance/pac.h"
652 #include "instance/pcc.h"
653 #include "instance/pdec.h"
654 #include "instance/pm.h"
655 #include "instance/port.h"
656 #include "instance/pukcc.h"
657 #include "instance/qspi.h"
658 #include "instance/ramecc.h"
659 #include "instance/rstc.h"
660 #include "instance/rtc.h"
661 #include "instance/sdhc0.h"
662 #include "instance/sdhc1.h"
663 #include "instance/sercom0.h"
664 #include "instance/sercom1.h"
665 #include "instance/sercom2.h"
666 #include "instance/sercom3.h"
667 #include "instance/sercom4.h"
668 #include "instance/sercom5.h"
669 #include "instance/sercom6.h"
670 #include "instance/sercom7.h"
671 #include "instance/supc.h"
672 #include "instance/tc0.h"
673 #include "instance/tc1.h"
674 #include "instance/tc2.h"
675 #include "instance/tc3.h"
676 #include "instance/tc4.h"
677 #include "instance/tc5.h"
678 #include "instance/tc6.h"
679 #include "instance/tc7.h"
680 #include "instance/tcc0.h"
681 #include "instance/tcc1.h"
682 #include "instance/tcc2.h"
683 #include "instance/tcc3.h"
684 #include "instance/tcc4.h"
685 #include "instance/trng.h"
686 #include "instance/usb.h"
687 #include "instance/wdt.h"
690 /* ************************************************************************** */
692 /* ************************************************************************** */
695 
696 // Peripheral instances on HPB0 bridge
697 #define ID_PAC 0
698 #define ID_PM 1
699 #define ID_MCLK 2
700 #define ID_RSTC 3
701 #define ID_OSCCTRL 4
702 #define ID_OSC32KCTRL 5
703 #define ID_SUPC 6
704 #define ID_GCLK 7
705 #define ID_WDT 8
706 #define ID_RTC 9
707 #define ID_EIC 10
708 #define ID_FREQM 11
709 #define ID_SERCOM0 12
710 #define ID_SERCOM1 13
711 #define ID_TC0 14
712 #define ID_TC1 15
714 // Peripheral instances on HPB1 bridge
715 #define ID_USB 32
716 #define ID_DSU 33
717 #define ID_NVMCTRL 34
718 #define ID_CMCC 35
719 #define ID_PORT 36
720 #define ID_DMAC 37
721 #define ID_HMATRIX 38
722 #define ID_EVSYS 39
723 #define ID_SERCOM2 41
724 #define ID_SERCOM3 42
725 #define ID_TCC0 43
726 #define ID_TCC1 44
727 #define ID_TC2 45
728 #define ID_TC3 46
729 #define ID_RAMECC 48
731 // Peripheral instances on HPB2 bridge
732 #define ID_CAN0 64
733 #define ID_CAN1 65
734 #define ID_GMAC 66
735 #define ID_TCC2 67
736 #define ID_TCC3 68
737 #define ID_TC4 69
738 #define ID_TC5 70
739 #define ID_PDEC 71
740 #define ID_AC 72
741 #define ID_AES 73
742 #define ID_TRNG 74
743 #define ID_ICM 75
744 #define ID_PUKCC 76
745 #define ID_QSPI 77
746 #define ID_CCL 78
748 // Peripheral instances on HPB3 bridge
749 #define ID_SERCOM4 96
750 #define ID_SERCOM5 97
751 #define ID_SERCOM6 98
752 #define ID_SERCOM7 99
753 #define ID_TCC4 100
754 #define ID_TC6 101
755 #define ID_TC7 102
756 #define ID_ADC0 103
757 #define ID_ADC1 104
758 #define ID_DAC 105
759 #define ID_I2S 106
760 #define ID_PCC 107
762 // Peripheral instances on AHB (as if on bridge 4)
763 #define ID_SDHC0 128
764 #define ID_SDHC1 129
766 #define ID_PERIPH_COUNT 130
768 
769 /* ************************************************************************** */
771 /* ************************************************************************** */
774 
775 #if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)
776 #define AC (0x42002000)
777 #define ADC0 (0x43001C00)
778 #define ADC1 (0x43002000)
779 #define AES (0x42002400)
780 #define CAN0 (0x42000000)
781 #define CAN1 (0x42000400)
782 #define CCL (0x42003800)
783 #define CMCC (0x41006000)
784 #define CMCC_AHB (0x03000000)
785 #define DAC (0x43002400)
786 #define DMAC (0x4100A000)
787 #define DSU (0x41002000)
788 #define EIC (0x40002800)
789 #define EVSYS (0x4100E000)
790 #define FREQM (0x40002C00)
791 #define GCLK (0x40001C00)
792 #define GMAC (0x42000800)
793 #define HMATRIX (0x4100C000)
794 #define ICM (0x42002C00)
795 #define I2S (0x43002800)
796 #define MCLK (0x40000800)
797 #define NVMCTRL (0x41004000)
798 #define NVMCTRL_SW0 (0x00800080)
799 #define NVMCTRL_TEMP_LOG (0x00800100)
800 #define NVMCTRL_USER (0x00804000)
801 #define OSCCTRL (0x40001000)
802 #define OSC32KCTRL (0x40001400)
803 #define PAC (0x40000000)
804 #define PCC (0x43002C00)
805 #define PDEC (0x42001C00)
806 #define PM (0x40000400)
807 #define PORT (0x41008000)
808 #define PUKCC (0x42003000)
809 #define PUKCC_AHB (0x02000000)
810 #define QSPI (0x42003400)
811 #define QSPI_AHB (0x04000000)
812 #define RAMECC (0x41020000)
813 #define RSTC (0x40000C00)
814 #define RTC (0x40002400)
815 #define SDHC0 (0x45000000)
816 #define SDHC1 (0x46000000)
817 #define SERCOM0 (0x40003000)
818 #define SERCOM1 (0x40003400)
819 #define SERCOM2 (0x41012000)
820 #define SERCOM3 (0x41014000)
821 #define SERCOM4 (0x43000000)
822 #define SERCOM5 (0x43000400)
823 #define SERCOM6 (0x43000800)
824 #define SERCOM7 (0x43000C00)
825 #define SUPC (0x40001800)
826 #define TC0 (0x40003800)
827 #define TC1 (0x40003C00)
828 #define TC2 (0x4101A000)
829 #define TC3 (0x4101C000)
830 #define TC4 (0x42001400)
831 #define TC5 (0x42001800)
832 #define TC6 (0x43001400)
833 #define TC7 (0x43001800)
834 #define TCC0 (0x41016000)
835 #define TCC1 (0x41018000)
836 #define TCC2 (0x42000C00)
837 #define TCC3 (0x42001000)
838 #define TCC4 (0x43001000)
839 #define TRNG (0x42002800)
840 #define USB (0x41000000)
841 #define WDT (0x40002000)
842 #else
843 #define AC ((Ac *)0x42002000UL)
844 #define AC_INST_NUM 1
845 #define AC_INSTS { AC }
847 #define ADC0 ((Adc *)0x43001C00UL)
848 #define ADC1 ((Adc *)0x43002000UL)
849 #define ADC_INST_NUM 2
850 #define ADC_INSTS { ADC0, ADC1 }
852 #define AES ((Aes *)0x42002400UL)
853 #define AES_INST_NUM 1
854 #define AES_INSTS { AES }
856 #define CAN0 ((Can *)0x42000000UL)
857 #define CAN1 ((Can *)0x42000400UL)
858 #define CAN_INST_NUM 2
859 #define CAN_INSTS { CAN0, CAN1 }
861 #define CCL ((Ccl *)0x42003800UL)
862 #define CCL_INST_NUM 1
863 #define CCL_INSTS { CCL }
865 #define CMCC ((Cmcc *)0x41006000UL)
866 #define CMCC_AHB (0x03000000UL)
867 #define CMCC_INST_NUM 1
868 #define CMCC_INSTS { CMCC }
870 #define DAC ((Dac *)0x43002400UL)
871 #define DAC_INST_NUM 1
872 #define DAC_INSTS { DAC }
874 #define DMAC ((Dmac *)0x4100A000UL)
875 #define DMAC_INST_NUM 1
876 #define DMAC_INSTS { DMAC }
878 #define DSU ((Dsu *)0x41002000UL)
879 #define DSU_INST_NUM 1
880 #define DSU_INSTS { DSU }
882 #define EIC ((Eic *)0x40002800UL)
883 #define EIC_INST_NUM 1
884 #define EIC_INSTS { EIC }
886 #define EVSYS ((Evsys *)0x4100E000UL)
887 #define EVSYS_INST_NUM 1
888 #define EVSYS_INSTS { EVSYS }
890 #define FREQM ((Freqm *)0x40002C00UL)
891 #define FREQM_INST_NUM 1
892 #define FREQM_INSTS { FREQM }
894 #define GCLK ((Gclk *)0x40001C00UL)
895 #define GCLK_INST_NUM 1
896 #define GCLK_INSTS { GCLK }
898 #define GMAC ((Gmac *)0x42000800UL)
899 #define GMAC_INST_NUM 1
900 #define GMAC_INSTS { GMAC }
902 #define HMATRIX ((Hmatrixb *)0x4100C000UL)
903 #define HMATRIXB_INST_NUM 1
904 #define HMATRIXB_INSTS { HMATRIX }
906 #define ICM ((Icm *)0x42002C00UL)
907 #define ICM_INST_NUM 1
908 #define ICM_INSTS { ICM }
910 #define I2S ((I2s *)0x43002800UL)
911 #define I2S_INST_NUM 1
912 #define I2S_INSTS { I2S }
914 #define MCLK ((Mclk *)0x40000800UL)
915 #define MCLK_INST_NUM 1
916 #define MCLK_INSTS { MCLK }
918 #define NVMCTRL ((Nvmctrl *)0x41004000UL)
919 #define NVMCTRL_SW0 (0x00800080UL)
920 #define NVMCTRL_TEMP_LOG (0x00800100UL)
921 #define NVMCTRL_USER (0x00804000UL)
922 #define NVMCTRL_INST_NUM 1
923 #define NVMCTRL_INSTS { NVMCTRL }
925 #define OSCCTRL ((Oscctrl *)0x40001000UL)
926 #define OSCCTRL_INST_NUM 1
927 #define OSCCTRL_INSTS { OSCCTRL }
929 #define OSC32KCTRL ((Osc32kctrl *)0x40001400UL)
930 #define OSC32KCTRL_INST_NUM 1
931 #define OSC32KCTRL_INSTS { OSC32KCTRL }
933 #define PAC ((Pac *)0x40000000UL)
934 #define PAC_INST_NUM 1
935 #define PAC_INSTS { PAC }
937 #define PCC ((Pcc *)0x43002C00UL)
938 #define PCC_INST_NUM 1
939 #define PCC_INSTS { PCC }
941 #define PDEC ((Pdec *)0x42001C00UL)
942 #define PDEC_INST_NUM 1
943 #define PDEC_INSTS { PDEC }
945 #define PM ((Pm *)0x40000400UL)
946 #define PM_INST_NUM 1
947 #define PM_INSTS { PM }
949 #define PORT ((Port *)0x41008000UL)
950 #define PORT_INST_NUM 1
951 #define PORT_INSTS { PORT }
953 #define PUKCC ((void *)0x42003000UL)
954 #define PUKCC_AHB ((void *)0x02000000UL)
955 #define PUKCC_INST_NUM 1
956 #define PUKCC_INSTS { PUKCC }
958 #define QSPI ((Qspi *)0x42003400UL)
959 #define QSPI_AHB (0x04000000UL)
960 #define QSPI_INST_NUM 1
961 #define QSPI_INSTS { QSPI }
963 #define RAMECC ((Ramecc *)0x41020000UL)
964 #define RAMECC_INST_NUM 1
965 #define RAMECC_INSTS { RAMECC }
967 #define RSTC ((Rstc *)0x40000C00UL)
968 #define RSTC_INST_NUM 1
969 #define RSTC_INSTS { RSTC }
971 #define RTC ((Rtc *)0x40002400UL)
972 #define RTC_INST_NUM 1
973 #define RTC_INSTS { RTC }
975 #define SDHC0 ((Sdhc *)0x45000000UL)
976 #define SDHC1 ((Sdhc *)0x46000000UL)
977 #define SDHC_INST_NUM 2
978 #define SDHC_INSTS { SDHC0, SDHC1 }
980 #define SERCOM0 ((Sercom *)0x40003000UL)
981 #define SERCOM1 ((Sercom *)0x40003400UL)
982 #define SERCOM2 ((Sercom *)0x41012000UL)
983 #define SERCOM3 ((Sercom *)0x41014000UL)
984 #define SERCOM4 ((Sercom *)0x43000000UL)
985 #define SERCOM5 ((Sercom *)0x43000400UL)
986 #define SERCOM6 ((Sercom *)0x43000800UL)
987 #define SERCOM7 ((Sercom *)0x43000C00UL)
988 #define SERCOM_INST_NUM 8
989 #define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5, SERCOM6, SERCOM7 }
991 #define SUPC ((Supc *)0x40001800UL)
992 #define SUPC_INST_NUM 1
993 #define SUPC_INSTS { SUPC }
995 #define TC0 ((Tc *)0x40003800UL)
996 #define TC1 ((Tc *)0x40003C00UL)
997 #define TC2 ((Tc *)0x4101A000UL)
998 #define TC3 ((Tc *)0x4101C000UL)
999 #define TC4 ((Tc *)0x42001400UL)
1000 #define TC5 ((Tc *)0x42001800UL)
1001 #define TC6 ((Tc *)0x43001400UL)
1002 #define TC7 ((Tc *)0x43001800UL)
1003 #define TC_INST_NUM 8
1004 #define TC_INSTS { TC0, TC1, TC2, TC3, TC4, TC5, TC6, TC7 }
1006 #define TCC0 ((Tcc *)0x41016000UL)
1007 #define TCC1 ((Tcc *)0x41018000UL)
1008 #define TCC2 ((Tcc *)0x42000C00UL)
1009 #define TCC3 ((Tcc *)0x42001000UL)
1010 #define TCC4 ((Tcc *)0x43001000UL)
1011 #define TCC_INST_NUM 5
1012 #define TCC_INSTS { TCC0, TCC1, TCC2, TCC3, TCC4 }
1014 #define TRNG ((Trng *)0x42002800UL)
1015 #define TRNG_INST_NUM 1
1016 #define TRNG_INSTS { TRNG }
1018 #define USB ((Usb *)0x41000000UL)
1019 #define USB_INST_NUM 1
1020 #define USB_INSTS { USB }
1022 #define WDT ((Wdt *)0x40002000UL)
1023 #define WDT_INST_NUM 1
1024 #define WDT_INSTS { WDT }
1026 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
1027 
1029 /* ************************************************************************** */
1031 /* ************************************************************************** */
1034 
1035 #include "pio/same54n19a.h"
1038 /* ************************************************************************** */
1040 /* ************************************************************************** */
1041 
1042 #define HSRAM_SIZE _UL_(0x00030000) /* 192 kB */
1043 #define FLASH_SIZE _UL_(0x00080000) /* 512 kB */
1044 #define FLASH_PAGE_SIZE 512
1045 #define FLASH_NB_OF_PAGES 1024
1046 #define FLASH_USER_PAGE_SIZE 512
1047 #define BKUPRAM_SIZE _UL_(0x00002000) /* 8 kB */
1048 #define QSPI_SIZE _UL_(0x01000000) /* 16384 kB */
1049 
1050 #define FLASH_ADDR _UL_(0x00000000)
1051 #define CMCC_DATARAM_ADDR _UL_(0x03000000)
1052 #define CMCC_DATARAM_SIZE _UL_(0x00001000)
1053 #define CMCC_TAGRAM_ADDR _UL_(0x03001000)
1054 #define CMCC_TAGRAM_SIZE _UL_(0x00000400)
1055 #define CMCC_VALIDRAM_ADDR _UL_(0x03002000)
1056 #define CMCC_VALIDRAM_SIZE _UL_(0x00000040)
1057 #define HSRAM_ADDR _UL_(0x20000000)
1058 #define HSRAM_ETB_ADDR _UL_(0x20000000)
1059 #define HSRAM_ETB_SIZE _UL_(0x00008000)
1060 #define HSRAM_RET1_ADDR _UL_(0x20000000)
1061 #define HSRAM_RET1_SIZE _UL_(0x00008000)
1062 #define HPB0_ADDR _UL_(0x40000000)
1063 #define HPB1_ADDR _UL_(0x41000000)
1064 #define HPB2_ADDR _UL_(0x42000000)
1065 #define HPB3_ADDR _UL_(0x43000000)
1066 #define SEEPROM_ADDR _UL_(0x44000000)
1067 #define BKUPRAM_ADDR _UL_(0x47000000)
1068 #define PPB_ADDR _UL_(0xE0000000)
1070 #define DSU_DID_RESETVALUE _UL_(0x61840303)
1071 #define ADC0_TOUCH_LINES_NUM 32
1072 #define PORT_GROUPS 3
1073 
1074 /* ************************************************************************** */
1076 /* ************************************************************************** */
1077 
1078 
1079 #ifdef __cplusplus
1080 }
1081 #endif
1082 
1085 #endif /* SAME54N19A_H */
SERCOM2_0_IRQn
@ SERCOM2_0_IRQn
Definition: same54n19a.h:155
RoReg
volatile const uint32_t RoReg
Definition: same54n19a.h:51
icm.h
Instance description for ICM.
icm.h
Component description for ICM.
Reset_Handler
void Reset_Handler(void)
This is the code that gets called on processor reset. To initialize the device, and call the main() r...
Definition: startup_same54.c:499
SERCOM3_3_IRQn
@ SERCOM3_3_IRQn
Definition: same54n19a.h:162
PendSV_IRQn
@ PendSV_IRQn
Definition: same54n19a.h:101
tc4.h
Instance description for TC4.
SERCOM7_3_IRQn
@ SERCOM7_3_IRQn
Definition: same54n19a.h:178
SDHC0_IRQn
@ SDHC0_IRQn
Definition: same54n19a.h:236
AC_IRQn
@ AC_IRQn
Definition: same54n19a.h:223
mclk.h
Component description for MCLK.
RwReg8
volatile uint8_t RwReg8
Definition: same54n19a.h:64
tc5.h
Instance description for TC5.
supc.h
Component description for SUPC.
DAC_3_IRQn
@ DAC_3_IRQn
Definition: same54n19a.h:227
can0.h
Instance description for CAN0.
pdec.h
Component description for PDEC.
EIC_12_IRQn
@ EIC_12_IRQn
Definition: same54n19a.h:128
RoReg16
volatile const uint16_t RoReg16
Definition: same54n19a.h:52
system_same54.h
Low-level initialization functions called upon chip startup.
SERCOM5_3_IRQn
@ SERCOM5_3_IRQn
Definition: same54n19a.h:170
SERCOM6_3_IRQn
@ SERCOM6_3_IRQn
Definition: same54n19a.h:174
PDEC_0_IRQn
@ PDEC_0_IRQn
Definition: same54n19a.h:216
tc2.h
Instance description for TC2.
can1.h
Instance description for CAN1.
EIC_4_IRQn
@ EIC_4_IRQn
Definition: same54n19a.h:120
SERCOM5_1_IRQn
@ SERCOM5_1_IRQn
Definition: same54n19a.h:168
NVMCTRL_0_IRQn
@ NVMCTRL_0_IRQn
Definition: same54n19a.h:133
TC3_IRQn
@ TC3_IRQn
Definition: same54n19a.h:211
SERCOM3_2_IRQn
@ SERCOM3_2_IRQn
Definition: same54n19a.h:161
pac.h
Component description for PAC.
tc3.h
Instance description for TC3.
rtc.h
Component description for RTC.
EIC_0_IRQn
@ EIC_0_IRQn
Definition: same54n19a.h:116
IRQn_Type
enum IRQn IRQn_Type
USB_3_IRQn
@ USB_3_IRQn
Definition: same54n19a.h:184
PCC_IRQn
@ PCC_IRQn
Definition: same54n19a.h:230
TCC3_1_IRQn
@ TCC3_1_IRQn
Definition: same54n19a.h:203
DAC_1_IRQn
@ DAC_1_IRQn
Definition: same54n19a.h:225
OSCCTRL_4_IRQn
@ OSCCTRL_4_IRQn
Definition: same54n19a.h:110
sercom2.h
Instance description for SERCOM2.
sdhc1.h
Instance description for SDHC1.
EIC_14_IRQn
@ EIC_14_IRQn
Definition: same54n19a.h:130
OSCCTRL_3_IRQn
@ OSCCTRL_3_IRQn
Definition: same54n19a.h:109
SERCOM5_2_IRQn
@ SERCOM5_2_IRQn
Definition: same54n19a.h:169
tcc0.h
Instance description for TCC0.
EIC_11_IRQn
@ EIC_11_IRQn
Definition: same54n19a.h:127
EVSYS_0_IRQn
@ EVSYS_0_IRQn
Definition: same54n19a.h:140
oscctrl.h
Component description for OSCCTRL.
tc6.h
Instance description for TC6.
WoReg
volatile uint32_t WoReg
Definition: same54n19a.h:59
RwReg16
volatile uint16_t RwReg16
Definition: same54n19a.h:63
cmcc.h
Component description for CMCC.
ADC0_0_IRQn
@ ADC0_0_IRQn
Definition: same54n19a.h:219
sercom0.h
Instance description for SERCOM0.
wdt.h
Instance description for WDT.
SDHC1_IRQn
@ SDHC1_IRQn
Definition: same54n19a.h:237
EIC_9_IRQn
@ EIC_9_IRQn
Definition: same54n19a.h:125
tcc1.h
Instance description for TCC1.
EIC_6_IRQn
@ EIC_6_IRQn
Definition: same54n19a.h:122
tc7.h
Instance description for TC7.
i2s.h
Instance description for I2S.
sercom3.h
Instance description for SERCOM3.
sdhc0.h
Instance description for SDHC0.
aes.h
Instance description for AES.
IRQn
IRQn
Definition: same54n19a.h:92
TCC4_1_IRQn
@ TCC4_1_IRQn
Definition: same54n19a.h:206
SERCOM3_0_IRQn
@ SERCOM3_0_IRQn
Definition: same54n19a.h:159
sercom6.h
Instance description for SERCOM6.
oscctrl.h
Instance description for OSCCTRL.
adc.h
Component description for ADC.
OSCCTRL_2_IRQn
@ OSCCTRL_2_IRQn
Definition: same54n19a.h:108
PDEC_2_IRQn
@ PDEC_2_IRQn
Definition: same54n19a.h:218
PDEC_1_IRQn
@ PDEC_1_IRQn
Definition: same54n19a.h:217
SERCOM7_1_IRQn
@ SERCOM7_1_IRQn
Definition: same54n19a.h:176
ICM_IRQn
@ ICM_IRQn
Definition: same54n19a.h:233
TCC1_3_IRQn
@ TCC1_3_IRQn
Definition: same54n19a.h:196
sercom4.h
Instance description for SERCOM4.
SERCOM0_3_IRQn
@ SERCOM0_3_IRQn
Definition: same54n19a.h:150
usb.h
Instance description for USB.
WoReg8
volatile uint8_t WoReg8
Definition: same54n19a.h:61
pukcc.h
Instance description for PUKCC.
TCC2_1_IRQn
@ TCC2_1_IRQn
Definition: same54n19a.h:199
PAC_IRQn
@ PAC_IRQn
Definition: same54n19a.h:145
sercom7.h
Instance description for SERCOM7.
EVSYS_1_IRQn
@ EVSYS_1_IRQn
Definition: same54n19a.h:141
nvmctrl.h
Component description for NVMCTRL.
ccl.h
Component description for CCL.
CAN1_IRQn
@ CAN1_IRQn
Definition: same54n19a.h:180
tc0.h
Instance description for TC0.
hmatrixb.h
Component description for HMATRIXB.
EVSYS_3_IRQn
@ EVSYS_3_IRQn
Definition: same54n19a.h:143
gclk.h
Instance description for GCLK.
GMAC_IRQn
@ GMAC_IRQn
Definition: same54n19a.h:185
CAN0_IRQn
@ CAN0_IRQn
Definition: same54n19a.h:179
SERCOM5_0_IRQn
@ SERCOM5_0_IRQn
Definition: same54n19a.h:167
tc1.h
Instance description for TC1.
SERCOM1_3_IRQn
@ SERCOM1_3_IRQn
Definition: same54n19a.h:154
port.h
Instance description for PORT.
tc.h
Component description for TC.
_DeviceVectors
Definition: same54n19a.h:243
usb.h
Component description for USB.
PERIPH_COUNT_IRQn
@ PERIPH_COUNT_IRQn
Definition: same54n19a.h:239
TCC2_0_IRQn
@ TCC2_0_IRQn
Definition: same54n19a.h:198
EIC_8_IRQn
@ EIC_8_IRQn
Definition: same54n19a.h:124
sercom5.h
Instance description for SERCOM5.
SUPC_1_IRQn
@ SUPC_1_IRQn
Definition: same54n19a.h:113
wdt.h
Component description for WDT.
TCC1_1_IRQn
@ TCC1_1_IRQn
Definition: same54n19a.h:194
DMAC_4_IRQn
@ DMAC_4_IRQn
Definition: same54n19a.h:139
ccl.h
Instance description for CCL.
HardFault_IRQn
@ HardFault_IRQn
Definition: same54n19a.h:95
DMAC_0_IRQn
@ DMAC_0_IRQn
Definition: same54n19a.h:135
SERCOM7_0_IRQn
@ SERCOM7_0_IRQn
Definition: same54n19a.h:175
TC5_IRQn
@ TC5_IRQn
Definition: same54n19a.h:213
UsageFault_IRQn
@ UsageFault_IRQn
Definition: same54n19a.h:98
dsu.h
Instance description for DSU.
WDT_IRQn
@ WDT_IRQn
Definition: same54n19a.h:114
EVSYS_2_IRQn
@ EVSYS_2_IRQn
Definition: same54n19a.h:142
TCC0_0_IRQn
@ TCC0_0_IRQn
Definition: same54n19a.h:186
TCC1_2_IRQn
@ TCC1_2_IRQn
Definition: same54n19a.h:195
dmac.h
Component description for DMAC.
qspi.h
Instance description for QSPI.
SERCOM6_0_IRQn
@ SERCOM6_0_IRQn
Definition: same54n19a.h:171
pm.h
Component description for PM.
EIC_3_IRQn
@ EIC_3_IRQn
Definition: same54n19a.h:119
EIC_2_IRQn
@ EIC_2_IRQn
Definition: same54n19a.h:118
SERCOM6_2_IRQn
@ SERCOM6_2_IRQn
Definition: same54n19a.h:173
pdec.h
Instance description for PDEC.
SERCOM7_2_IRQn
@ SERCOM7_2_IRQn
Definition: same54n19a.h:177
dac.h
Component description for DAC.
DAC_0_IRQn
@ DAC_0_IRQn
Definition: same54n19a.h:224
QSPI_IRQn
@ QSPI_IRQn
Definition: same54n19a.h:235
ADC1_0_IRQn
@ ADC1_0_IRQn
Definition: same54n19a.h:221
pac.h
Instance description for PAC.
TCC0_3_IRQn
@ TCC0_3_IRQn
Definition: same54n19a.h:189
gmac.h
Component description for GMAC.
rstc.h
Instance description for RSTC.
gmac.h
Instance description for GMAC.
TCC0_4_IRQn
@ TCC0_4_IRQn
Definition: same54n19a.h:190
SERCOM2_1_IRQn
@ SERCOM2_1_IRQn
Definition: same54n19a.h:156
TCC0_2_IRQn
@ TCC0_2_IRQn
Definition: same54n19a.h:188
OSCCTRL_1_IRQn
@ OSCCTRL_1_IRQn
Definition: same54n19a.h:107
TCC0_5_IRQn
@ TCC0_5_IRQn
Definition: same54n19a.h:191
ac.h
Component description for AC.
TRNG_IRQn
@ TRNG_IRQn
Definition: same54n19a.h:232
SERCOM4_0_IRQn
@ SERCOM4_0_IRQn
Definition: same54n19a.h:163
FREQM_IRQn
@ FREQM_IRQn
Definition: same54n19a.h:132
TCC4_2_IRQn
@ TCC4_2_IRQn
Definition: same54n19a.h:207
TCC1_0_IRQn
@ TCC1_0_IRQn
Definition: same54n19a.h:193
trng.h
Component description for TRNG.
TC4_IRQn
@ TC4_IRQn
Definition: same54n19a.h:212
USB_0_IRQn
@ USB_0_IRQn
Definition: same54n19a.h:181
eic.h
Instance description for EIC.
SERCOM4_2_IRQn
@ SERCOM4_2_IRQn
Definition: same54n19a.h:165
sercom.h
Component description for SERCOM.
EIC_13_IRQn
@ EIC_13_IRQn
Definition: same54n19a.h:129
ADC1_1_IRQn
@ ADC1_1_IRQn
Definition: same54n19a.h:222
EVSYS_4_IRQn
@ EVSYS_4_IRQn
Definition: same54n19a.h:144
TCC3_0_IRQn
@ TCC3_0_IRQn
Definition: same54n19a.h:202
TCC1_4_IRQn
@ TCC1_4_IRQn
Definition: same54n19a.h:197
ramecc.h
Instance description for RAMECC.
EIC_7_IRQn
@ EIC_7_IRQn
Definition: same54n19a.h:123
EIC_5_IRQn
@ EIC_5_IRQn
Definition: same54n19a.h:121
TC6_IRQn
@ TC6_IRQn
Definition: same54n19a.h:214
USB_2_IRQn
@ USB_2_IRQn
Definition: same54n19a.h:183
dsu.h
Component description for DSU.
pcc.h
Component description for PCC.
osc32kctrl.h
Component description for OSC32KCTRL.
gclk.h
Component description for GCLK.
SERCOM3_1_IRQn
@ SERCOM3_1_IRQn
Definition: same54n19a.h:160
cmcc.h
Instance description for CMCC.
SERCOM2_2_IRQn
@ SERCOM2_2_IRQn
Definition: same54n19a.h:157
trng.h
Instance description for TRNG.
qspi.h
Component description for QSPI.
rtc.h
Instance description for RTC.
TCC0_1_IRQn
@ TCC0_1_IRQn
Definition: same54n19a.h:187
SERCOM4_1_IRQn
@ SERCOM4_1_IRQn
Definition: same54n19a.h:164
evsys.h
Component description for EVSYS.
RwReg
volatile uint32_t RwReg
Definition: same54n19a.h:62
TCC4_0_IRQn
@ TCC4_0_IRQn
Definition: same54n19a.h:205
DebugMonitor_IRQn
@ DebugMonitor_IRQn
Definition: same54n19a.h:100
OSC32KCTRL_IRQn
@ OSC32KCTRL_IRQn
Definition: same54n19a.h:111
NVMCTRL_1_IRQn
@ NVMCTRL_1_IRQn
Definition: same54n19a.h:134
EIC_10_IRQn
@ EIC_10_IRQn
Definition: same54n19a.h:126
port.h
Component description for PORT.
ac.h
Instance description for AC.
SERCOM0_0_IRQn
@ SERCOM0_0_IRQn
Definition: same54n19a.h:147
mclk.h
Instance description for MCLK.
I2S_IRQn
@ I2S_IRQn
Definition: same54n19a.h:229
DAC_2_IRQn
@ DAC_2_IRQn
Definition: same54n19a.h:226
TCC0_6_IRQn
@ TCC0_6_IRQn
Definition: same54n19a.h:192
eic.h
Component description for EIC.
DMAC_2_IRQn
@ DMAC_2_IRQn
Definition: same54n19a.h:137
aes.h
Component description for AES.
SERCOM4_3_IRQn
@ SERCOM4_3_IRQn
Definition: same54n19a.h:166
NonMaskableInt_IRQn
@ NonMaskableInt_IRQn
Definition: same54n19a.h:94
TC2_IRQn
@ TC2_IRQn
Definition: same54n19a.h:210
SERCOM1_0_IRQn
@ SERCOM1_0_IRQn
Definition: same54n19a.h:151
RTC_IRQn
@ RTC_IRQn
Definition: same54n19a.h:115
SERCOM1_1_IRQn
@ SERCOM1_1_IRQn
Definition: same54n19a.h:152
same54n19a.h
Peripheral I/O description for SAME54N19A.
MemoryManagement_IRQn
@ MemoryManagement_IRQn
Definition: same54n19a.h:96
hmatrix.h
Instance description for HMATRIX.
DMAC_1_IRQn
@ DMAC_1_IRQn
Definition: same54n19a.h:136
BusFault_IRQn
@ BusFault_IRQn
Definition: same54n19a.h:97
SysTick_IRQn
@ SysTick_IRQn
Definition: same54n19a.h:102
USB_1_IRQn
@ USB_1_IRQn
Definition: same54n19a.h:182
adc0.h
Instance description for ADC0.
PM_IRQn
@ PM_IRQn
Definition: same54n19a.h:104
PUKCC_IRQn
@ PUKCC_IRQn
Definition: same54n19a.h:234
RoReg8
volatile const uint8_t RoReg8
Definition: same54n19a.h:53
evsys.h
Instance description for EVSYS.
adc1.h
Instance description for ADC1.
can.h
Component description for CAN.
DMAC_3_IRQn
@ DMAC_3_IRQn
Definition: same54n19a.h:138
TC0_IRQn
@ TC0_IRQn
Definition: same54n19a.h:208
TC7_IRQn
@ TC7_IRQn
Definition: same54n19a.h:215
SUPC_0_IRQn
@ SUPC_0_IRQn
Definition: same54n19a.h:112
SERCOM1_2_IRQn
@ SERCOM1_2_IRQn
Definition: same54n19a.h:153
dac.h
Instance description for DAC.
SERCOM0_1_IRQn
@ SERCOM0_1_IRQn
Definition: same54n19a.h:148
sercom1.h
Instance description for SERCOM1.
AES_IRQn
@ AES_IRQn
Definition: same54n19a.h:231
tcc4.h
Instance description for TCC4.
rstc.h
Component description for RSTC.
TCC2_2_IRQn
@ TCC2_2_IRQn
Definition: same54n19a.h:200
SVCall_IRQn
@ SVCall_IRQn
Definition: same54n19a.h:99
EIC_15_IRQn
@ EIC_15_IRQn
Definition: same54n19a.h:131
MCLK_IRQn
@ MCLK_IRQn
Definition: same54n19a.h:105
tcc.h
Component description for TCC.
freqm.h
Component description for FREQM.
DAC_4_IRQn
@ DAC_4_IRQn
Definition: same54n19a.h:228
supc.h
Instance description for SUPC.
tcc2.h
Instance description for TCC2.
osc32kctrl.h
Instance description for OSC32KCTRL.
dmac.h
Instance description for DMAC.
i2s.h
Component description for I2S.
EIC_1_IRQn
@ EIC_1_IRQn
Definition: same54n19a.h:117
TC1_IRQn
@ TC1_IRQn
Definition: same54n19a.h:209
pm.h
Instance description for PM.
SERCOM6_1_IRQn
@ SERCOM6_1_IRQn
Definition: same54n19a.h:172
TCC3_2_IRQn
@ TCC3_2_IRQn
Definition: same54n19a.h:204
ramecc.h
Component description for RAMECC.
tcc3.h
Instance description for TCC3.
TCC2_3_IRQn
@ TCC2_3_IRQn
Definition: same54n19a.h:201
pcc.h
Instance description for PCC.
freqm.h
Instance description for FREQM.
SERCOM2_3_IRQn
@ SERCOM2_3_IRQn
Definition: same54n19a.h:158
sdhc.h
Component description for SDHC.
WoReg16
volatile uint16_t WoReg16
Definition: same54n19a.h:60
ADC0_1_IRQn
@ ADC0_1_IRQn
Definition: same54n19a.h:220
OSCCTRL_0_IRQn
@ OSCCTRL_0_IRQn
Definition: same54n19a.h:106
SERCOM0_2_IRQn
@ SERCOM0_2_IRQn
Definition: same54n19a.h:149
nvmctrl.h
Instance description for NVMCTRL.
RAMECC_IRQn
@ RAMECC_IRQn
Definition: same54n19a.h:146
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