Instance description for CAN1. More...

Macros
#define	REG_CAN1_CREL ((RoReg )0x42000400UL)
	(CAN1) Core Release

#define	REG_CAN1_ENDN ((RoReg )0x42000404UL)
	(CAN1) Endian

#define	REG_CAN1_MRCFG ((RwReg )0x42000408UL)
	(CAN1) Message RAM Configuration

#define	REG_CAN1_DBTP ((RwReg )0x4200040CUL)
	(CAN1) Fast Bit Timing and Prescaler

#define	REG_CAN1_TEST ((RwReg )0x42000410UL)
	(CAN1) Test

#define	REG_CAN1_RWD ((RwReg )0x42000414UL)
	(CAN1) RAM Watchdog

#define	REG_CAN1_CCCR ((RwReg )0x42000418UL)
	(CAN1) CC Control

#define	REG_CAN1_NBTP ((RwReg )0x4200041CUL)
	(CAN1) Nominal Bit Timing and Prescaler

#define	REG_CAN1_TSCC ((RwReg )0x42000420UL)
	(CAN1) Timestamp Counter Configuration

#define	REG_CAN1_TSCV ((RoReg )0x42000424UL)
	(CAN1) Timestamp Counter Value

#define	REG_CAN1_TOCC ((RwReg )0x42000428UL)
	(CAN1) Timeout Counter Configuration

#define	REG_CAN1_TOCV ((RwReg )0x4200042CUL)
	(CAN1) Timeout Counter Value

#define	REG_CAN1_ECR ((RoReg )0x42000440UL)
	(CAN1) Error Counter

#define	REG_CAN1_PSR ((RoReg )0x42000444UL)
	(CAN1) Protocol Status

#define	REG_CAN1_TDCR ((RwReg )0x42000448UL)
	(CAN1) Extended ID Filter Configuration

#define	REG_CAN1_IR ((RwReg )0x42000450UL)
	(CAN1) Interrupt

#define	REG_CAN1_IE ((RwReg )0x42000454UL)
	(CAN1) Interrupt Enable

#define	REG_CAN1_ILS ((RwReg )0x42000458UL)
	(CAN1) Interrupt Line Select

#define	REG_CAN1_ILE ((RwReg )0x4200045CUL)
	(CAN1) Interrupt Line Enable

#define	REG_CAN1_GFC ((RwReg )0x42000480UL)
	(CAN1) Global Filter Configuration

#define	REG_CAN1_SIDFC ((RwReg )0x42000484UL)
	(CAN1) Standard ID Filter Configuration

#define	REG_CAN1_XIDFC ((RwReg )0x42000488UL)
	(CAN1) Extended ID Filter Configuration

#define	REG_CAN1_XIDAM ((RwReg )0x42000490UL)
	(CAN1) Extended ID AND Mask

#define	REG_CAN1_HPMS ((RoReg )0x42000494UL)
	(CAN1) High Priority Message Status

#define	REG_CAN1_NDAT1 ((RwReg )0x42000498UL)
	(CAN1) New Data 1

#define	REG_CAN1_NDAT2 ((RwReg )0x4200049CUL)
	(CAN1) New Data 2

#define	REG_CAN1_RXF0C ((RwReg )0x420004A0UL)
	(CAN1) Rx FIFO 0 Configuration

#define	REG_CAN1_RXF0S ((RoReg )0x420004A4UL)
	(CAN1) Rx FIFO 0 Status

#define	REG_CAN1_RXF0A ((RwReg )0x420004A8UL)
	(CAN1) Rx FIFO 0 Acknowledge

#define	REG_CAN1_RXBC ((RwReg )0x420004ACUL)
	(CAN1) Rx Buffer Configuration

#define	REG_CAN1_RXF1C ((RwReg )0x420004B0UL)
	(CAN1) Rx FIFO 1 Configuration

#define	REG_CAN1_RXF1S ((RoReg )0x420004B4UL)
	(CAN1) Rx FIFO 1 Status

#define	REG_CAN1_RXF1A ((RwReg )0x420004B8UL)
	(CAN1) Rx FIFO 1 Acknowledge

#define	REG_CAN1_RXESC ((RwReg )0x420004BCUL)
	(CAN1) Rx Buffer / FIFO Element Size Configuration

#define	REG_CAN1_TXBC ((RwReg )0x420004C0UL)
	(CAN1) Tx Buffer Configuration

#define	REG_CAN1_TXFQS ((RoReg )0x420004C4UL)
	(CAN1) Tx FIFO / Queue Status

#define	REG_CAN1_TXESC ((RwReg )0x420004C8UL)
	(CAN1) Tx Buffer Element Size Configuration

#define	REG_CAN1_TXBRP ((RoReg )0x420004CCUL)
	(CAN1) Tx Buffer Request Pending

#define	REG_CAN1_TXBAR ((RwReg )0x420004D0UL)
	(CAN1) Tx Buffer Add Request

#define	REG_CAN1_TXBCR ((RwReg )0x420004D4UL)
	(CAN1) Tx Buffer Cancellation Request

#define	REG_CAN1_TXBTO ((RoReg )0x420004D8UL)
	(CAN1) Tx Buffer Transmission Occurred

#define	REG_CAN1_TXBCF ((RoReg )0x420004DCUL)
	(CAN1) Tx Buffer Cancellation Finished

#define	REG_CAN1_TXBTIE ((RwReg )0x420004E0UL)
	(CAN1) Tx Buffer Transmission Interrupt Enable

#define	REG_CAN1_TXBCIE ((RwReg )0x420004E4UL)
	(CAN1) Tx Buffer Cancellation Finished Interrupt Enable

#define	REG_CAN1_TXEFC ((RwReg )0x420004F0UL)
	(CAN1) Tx Event FIFO Configuration

#define	REG_CAN1_TXEFS ((RoReg )0x420004F4UL)
	(CAN1) Tx Event FIFO Status

#define	REG_CAN1_TXEFA ((RwReg )0x420004F8UL)
	(CAN1) Tx Event FIFO Acknowledge

#define	CAN1_CLK_AHB_ID 18

#define	CAN1_DMAC_ID_DEBUG 21

#define	CAN1_GCLK_ID 28

#define	CAN1_MSG_RAM_ADDR 0x20000000

#define	CAN1_QOS_RESET_VAL 1

Detailed Description

Instance description for CAN1.

\asf_license_start

Definition in file can1.h.

Macros

Detailed Description