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SAME54P20A Test Project
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Instance description for EVSYS. More...
Go to the source code of this file.
Macros | |
| #define | REG_EVSYS_CTRLA (*(RwReg8 *)0x4100E000UL) |
| (EVSYS) Control | |
| #define | REG_EVSYS_SWEVT (*(WoReg *)0x4100E004UL) |
| (EVSYS) Software Event | |
| #define | REG_EVSYS_PRICTRL (*(RwReg8 *)0x4100E008UL) |
| (EVSYS) Priority Control | |
| #define | REG_EVSYS_INTPEND (*(RwReg16*)0x4100E010UL) |
| (EVSYS) Channel Pending Interrupt | |
| #define | REG_EVSYS_INTSTATUS (*(RoReg *)0x4100E014UL) |
| (EVSYS) Interrupt Status | |
| #define | REG_EVSYS_BUSYCH (*(RoReg *)0x4100E018UL) |
| (EVSYS) Busy Channels | |
| #define | REG_EVSYS_READYUSR (*(RoReg *)0x4100E01CUL) |
| (EVSYS) Ready Users | |
| #define | REG_EVSYS_CHANNEL0 (*(RwReg *)0x4100E020UL) |
| (EVSYS) Channel 0 Control | |
| #define | REG_EVSYS_CHINTENCLR0 (*(RwReg8 *)0x4100E024UL) |
| (EVSYS) Channel 0 Interrupt Enable Clear | |
| #define | REG_EVSYS_CHINTENSET0 (*(RwReg8 *)0x4100E025UL) |
| (EVSYS) Channel 0 Interrupt Enable Set | |
| #define | REG_EVSYS_CHINTFLAG0 (*(RwReg8 *)0x4100E026UL) |
| (EVSYS) Channel 0 Interrupt Flag Status and Clear | |
| #define | REG_EVSYS_CHSTATUS0 (*(RoReg8 *)0x4100E027UL) |
| (EVSYS) Channel 0 Status | |
| #define | REG_EVSYS_CHANNEL1 (*(RwReg *)0x4100E028UL) |
| (EVSYS) Channel 1 Control | |
| #define | REG_EVSYS_CHINTENCLR1 (*(RwReg8 *)0x4100E02CUL) |
| (EVSYS) Channel 1 Interrupt Enable Clear | |
| #define | REG_EVSYS_CHINTENSET1 (*(RwReg8 *)0x4100E02DUL) |
| (EVSYS) Channel 1 Interrupt Enable Set | |
| #define | REG_EVSYS_CHINTFLAG1 (*(RwReg8 *)0x4100E02EUL) |
| (EVSYS) Channel 1 Interrupt Flag Status and Clear | |
| #define | REG_EVSYS_CHSTATUS1 (*(RoReg8 *)0x4100E02FUL) |
| (EVSYS) Channel 1 Status | |
| #define | REG_EVSYS_CHANNEL2 (*(RwReg *)0x4100E030UL) |
| (EVSYS) Channel 2 Control | |
| #define | REG_EVSYS_CHINTENCLR2 (*(RwReg8 *)0x4100E034UL) |
| (EVSYS) Channel 2 Interrupt Enable Clear | |
| #define | REG_EVSYS_CHINTENSET2 (*(RwReg8 *)0x4100E035UL) |
| (EVSYS) Channel 2 Interrupt Enable Set | |
| #define | REG_EVSYS_CHINTFLAG2 (*(RwReg8 *)0x4100E036UL) |
| (EVSYS) Channel 2 Interrupt Flag Status and Clear | |
| #define | REG_EVSYS_CHSTATUS2 (*(RoReg8 *)0x4100E037UL) |
| (EVSYS) Channel 2 Status | |
| #define | REG_EVSYS_CHANNEL3 (*(RwReg *)0x4100E038UL) |
| (EVSYS) Channel 3 Control | |
| #define | REG_EVSYS_CHINTENCLR3 (*(RwReg8 *)0x4100E03CUL) |
| (EVSYS) Channel 3 Interrupt Enable Clear | |
| #define | REG_EVSYS_CHINTENSET3 (*(RwReg8 *)0x4100E03DUL) |
| (EVSYS) Channel 3 Interrupt Enable Set | |
| #define | REG_EVSYS_CHINTFLAG3 (*(RwReg8 *)0x4100E03EUL) |
| (EVSYS) Channel 3 Interrupt Flag Status and Clear | |
| #define | REG_EVSYS_CHSTATUS3 (*(RoReg8 *)0x4100E03FUL) |
| (EVSYS) Channel 3 Status | |
| #define | REG_EVSYS_CHANNEL4 (*(RwReg *)0x4100E040UL) |
| (EVSYS) Channel 4 Control | |
| #define | REG_EVSYS_CHINTENCLR4 (*(RwReg8 *)0x4100E044UL) |
| (EVSYS) Channel 4 Interrupt Enable Clear | |
| #define | REG_EVSYS_CHINTENSET4 (*(RwReg8 *)0x4100E045UL) |
| (EVSYS) Channel 4 Interrupt Enable Set | |
| #define | REG_EVSYS_CHINTFLAG4 (*(RwReg8 *)0x4100E046UL) |
| (EVSYS) Channel 4 Interrupt Flag Status and Clear | |
| #define | REG_EVSYS_CHSTATUS4 (*(RoReg8 *)0x4100E047UL) |
| (EVSYS) Channel 4 Status | |
| #define | REG_EVSYS_CHANNEL5 (*(RwReg *)0x4100E048UL) |
| (EVSYS) Channel 5 Control | |
| #define | REG_EVSYS_CHINTENCLR5 (*(RwReg8 *)0x4100E04CUL) |
| (EVSYS) Channel 5 Interrupt Enable Clear | |
| #define | REG_EVSYS_CHINTENSET5 (*(RwReg8 *)0x4100E04DUL) |
| (EVSYS) Channel 5 Interrupt Enable Set | |
| #define | REG_EVSYS_CHINTFLAG5 (*(RwReg8 *)0x4100E04EUL) |
| (EVSYS) Channel 5 Interrupt Flag Status and Clear | |
| #define | REG_EVSYS_CHSTATUS5 (*(RoReg8 *)0x4100E04FUL) |
| (EVSYS) Channel 5 Status | |
| #define | REG_EVSYS_CHANNEL6 (*(RwReg *)0x4100E050UL) |
| (EVSYS) Channel 6 Control | |
| #define | REG_EVSYS_CHINTENCLR6 (*(RwReg8 *)0x4100E054UL) |
| (EVSYS) Channel 6 Interrupt Enable Clear | |
| #define | REG_EVSYS_CHINTENSET6 (*(RwReg8 *)0x4100E055UL) |
| (EVSYS) Channel 6 Interrupt Enable Set | |
| #define | REG_EVSYS_CHINTFLAG6 (*(RwReg8 *)0x4100E056UL) |
| (EVSYS) Channel 6 Interrupt Flag Status and Clear | |
| #define | REG_EVSYS_CHSTATUS6 (*(RoReg8 *)0x4100E057UL) |
| (EVSYS) Channel 6 Status | |
| #define | REG_EVSYS_CHANNEL7 (*(RwReg *)0x4100E058UL) |
| (EVSYS) Channel 7 Control | |
| #define | REG_EVSYS_CHINTENCLR7 (*(RwReg8 *)0x4100E05CUL) |
| (EVSYS) Channel 7 Interrupt Enable Clear | |
| #define | REG_EVSYS_CHINTENSET7 (*(RwReg8 *)0x4100E05DUL) |
| (EVSYS) Channel 7 Interrupt Enable Set | |
| #define | REG_EVSYS_CHINTFLAG7 (*(RwReg8 *)0x4100E05EUL) |
| (EVSYS) Channel 7 Interrupt Flag Status and Clear | |
| #define | REG_EVSYS_CHSTATUS7 (*(RoReg8 *)0x4100E05FUL) |
| (EVSYS) Channel 7 Status | |
| #define | REG_EVSYS_CHANNEL8 (*(RwReg *)0x4100E060UL) |
| (EVSYS) Channel 8 Control | |
| #define | REG_EVSYS_CHINTENCLR8 (*(RwReg8 *)0x4100E064UL) |
| (EVSYS) Channel 8 Interrupt Enable Clear | |
| #define | REG_EVSYS_CHINTENSET8 (*(RwReg8 *)0x4100E065UL) |
| (EVSYS) Channel 8 Interrupt Enable Set | |
| #define | REG_EVSYS_CHINTFLAG8 (*(RwReg8 *)0x4100E066UL) |
| (EVSYS) Channel 8 Interrupt Flag Status and Clear | |
| #define | REG_EVSYS_CHSTATUS8 (*(RoReg8 *)0x4100E067UL) |
| (EVSYS) Channel 8 Status | |
| #define | REG_EVSYS_CHANNEL9 (*(RwReg *)0x4100E068UL) |
| (EVSYS) Channel 9 Control | |
| #define | REG_EVSYS_CHINTENCLR9 (*(RwReg8 *)0x4100E06CUL) |
| (EVSYS) Channel 9 Interrupt Enable Clear | |
| #define | REG_EVSYS_CHINTENSET9 (*(RwReg8 *)0x4100E06DUL) |
| (EVSYS) Channel 9 Interrupt Enable Set | |
| #define | REG_EVSYS_CHINTFLAG9 (*(RwReg8 *)0x4100E06EUL) |
| (EVSYS) Channel 9 Interrupt Flag Status and Clear | |
| #define | REG_EVSYS_CHSTATUS9 (*(RoReg8 *)0x4100E06FUL) |
| (EVSYS) Channel 9 Status | |
| #define | REG_EVSYS_CHANNEL10 (*(RwReg *)0x4100E070UL) |
| (EVSYS) Channel 10 Control | |
| #define | REG_EVSYS_CHINTENCLR10 (*(RwReg8 *)0x4100E074UL) |
| (EVSYS) Channel 10 Interrupt Enable Clear | |
| #define | REG_EVSYS_CHINTENSET10 (*(RwReg8 *)0x4100E075UL) |
| (EVSYS) Channel 10 Interrupt Enable Set | |
| #define | REG_EVSYS_CHINTFLAG10 (*(RwReg8 *)0x4100E076UL) |
| (EVSYS) Channel 10 Interrupt Flag Status and Clear | |
| #define | REG_EVSYS_CHSTATUS10 (*(RoReg8 *)0x4100E077UL) |
| (EVSYS) Channel 10 Status | |
| #define | REG_EVSYS_CHANNEL11 (*(RwReg *)0x4100E078UL) |
| (EVSYS) Channel 11 Control | |
| #define | REG_EVSYS_CHINTENCLR11 (*(RwReg8 *)0x4100E07CUL) |
| (EVSYS) Channel 11 Interrupt Enable Clear | |
| #define | REG_EVSYS_CHINTENSET11 (*(RwReg8 *)0x4100E07DUL) |
| (EVSYS) Channel 11 Interrupt Enable Set | |
| #define | REG_EVSYS_CHINTFLAG11 (*(RwReg8 *)0x4100E07EUL) |
| (EVSYS) Channel 11 Interrupt Flag Status and Clear | |
| #define | REG_EVSYS_CHSTATUS11 (*(RoReg8 *)0x4100E07FUL) |
| (EVSYS) Channel 11 Status | |
| #define | REG_EVSYS_CHANNEL12 (*(RwReg *)0x4100E080UL) |
| (EVSYS) Channel 12 Control | |
| #define | REG_EVSYS_CHINTENCLR12 (*(RwReg8 *)0x4100E084UL) |
| (EVSYS) Channel 12 Interrupt Enable Clear | |
| #define | REG_EVSYS_CHINTENSET12 (*(RwReg8 *)0x4100E085UL) |
| (EVSYS) Channel 12 Interrupt Enable Set | |
| #define | REG_EVSYS_CHINTFLAG12 (*(RwReg8 *)0x4100E086UL) |
| (EVSYS) Channel 12 Interrupt Flag Status and Clear | |
| #define | REG_EVSYS_CHSTATUS12 (*(RoReg8 *)0x4100E087UL) |
| (EVSYS) Channel 12 Status | |
| #define | REG_EVSYS_CHANNEL13 (*(RwReg *)0x4100E088UL) |
| (EVSYS) Channel 13 Control | |
| #define | REG_EVSYS_CHINTENCLR13 (*(RwReg8 *)0x4100E08CUL) |
| (EVSYS) Channel 13 Interrupt Enable Clear | |
| #define | REG_EVSYS_CHINTENSET13 (*(RwReg8 *)0x4100E08DUL) |
| (EVSYS) Channel 13 Interrupt Enable Set | |
| #define | REG_EVSYS_CHINTFLAG13 (*(RwReg8 *)0x4100E08EUL) |
| (EVSYS) Channel 13 Interrupt Flag Status and Clear | |
| #define | REG_EVSYS_CHSTATUS13 (*(RoReg8 *)0x4100E08FUL) |
| (EVSYS) Channel 13 Status | |
| #define | REG_EVSYS_CHANNEL14 (*(RwReg *)0x4100E090UL) |
| (EVSYS) Channel 14 Control | |
| #define | REG_EVSYS_CHINTENCLR14 (*(RwReg8 *)0x4100E094UL) |
| (EVSYS) Channel 14 Interrupt Enable Clear | |
| #define | REG_EVSYS_CHINTENSET14 (*(RwReg8 *)0x4100E095UL) |
| (EVSYS) Channel 14 Interrupt Enable Set | |
| #define | REG_EVSYS_CHINTFLAG14 (*(RwReg8 *)0x4100E096UL) |
| (EVSYS) Channel 14 Interrupt Flag Status and Clear | |
| #define | REG_EVSYS_CHSTATUS14 (*(RoReg8 *)0x4100E097UL) |
| (EVSYS) Channel 14 Status | |
| #define | REG_EVSYS_CHANNEL15 (*(RwReg *)0x4100E098UL) |
| (EVSYS) Channel 15 Control | |
| #define | REG_EVSYS_CHINTENCLR15 (*(RwReg8 *)0x4100E09CUL) |
| (EVSYS) Channel 15 Interrupt Enable Clear | |
| #define | REG_EVSYS_CHINTENSET15 (*(RwReg8 *)0x4100E09DUL) |
| (EVSYS) Channel 15 Interrupt Enable Set | |
| #define | REG_EVSYS_CHINTFLAG15 (*(RwReg8 *)0x4100E09EUL) |
| (EVSYS) Channel 15 Interrupt Flag Status and Clear | |
| #define | REG_EVSYS_CHSTATUS15 (*(RoReg8 *)0x4100E09FUL) |
| (EVSYS) Channel 15 Status | |
| #define | REG_EVSYS_CHANNEL16 (*(RwReg *)0x4100E0A0UL) |
| (EVSYS) Channel 16 Control | |
| #define | REG_EVSYS_CHINTENCLR16 (*(RwReg8 *)0x4100E0A4UL) |
| (EVSYS) Channel 16 Interrupt Enable Clear | |
| #define | REG_EVSYS_CHINTENSET16 (*(RwReg8 *)0x4100E0A5UL) |
| (EVSYS) Channel 16 Interrupt Enable Set | |
| #define | REG_EVSYS_CHINTFLAG16 (*(RwReg8 *)0x4100E0A6UL) |
| (EVSYS) Channel 16 Interrupt Flag Status and Clear | |
| #define | REG_EVSYS_CHSTATUS16 (*(RoReg8 *)0x4100E0A7UL) |
| (EVSYS) Channel 16 Status | |
| #define | REG_EVSYS_CHANNEL17 (*(RwReg *)0x4100E0A8UL) |
| (EVSYS) Channel 17 Control | |
| #define | REG_EVSYS_CHINTENCLR17 (*(RwReg8 *)0x4100E0ACUL) |
| (EVSYS) Channel 17 Interrupt Enable Clear | |
| #define | REG_EVSYS_CHINTENSET17 (*(RwReg8 *)0x4100E0ADUL) |
| (EVSYS) Channel 17 Interrupt Enable Set | |
| #define | REG_EVSYS_CHINTFLAG17 (*(RwReg8 *)0x4100E0AEUL) |
| (EVSYS) Channel 17 Interrupt Flag Status and Clear | |
| #define | REG_EVSYS_CHSTATUS17 (*(RoReg8 *)0x4100E0AFUL) |
| (EVSYS) Channel 17 Status | |
| #define | REG_EVSYS_CHANNEL18 (*(RwReg *)0x4100E0B0UL) |
| (EVSYS) Channel 18 Control | |
| #define | REG_EVSYS_CHINTENCLR18 (*(RwReg8 *)0x4100E0B4UL) |
| (EVSYS) Channel 18 Interrupt Enable Clear | |
| #define | REG_EVSYS_CHINTENSET18 (*(RwReg8 *)0x4100E0B5UL) |
| (EVSYS) Channel 18 Interrupt Enable Set | |
| #define | REG_EVSYS_CHINTFLAG18 (*(RwReg8 *)0x4100E0B6UL) |
| (EVSYS) Channel 18 Interrupt Flag Status and Clear | |
| #define | REG_EVSYS_CHSTATUS18 (*(RoReg8 *)0x4100E0B7UL) |
| (EVSYS) Channel 18 Status | |
| #define | REG_EVSYS_CHANNEL19 (*(RwReg *)0x4100E0B8UL) |
| (EVSYS) Channel 19 Control | |
| #define | REG_EVSYS_CHINTENCLR19 (*(RwReg8 *)0x4100E0BCUL) |
| (EVSYS) Channel 19 Interrupt Enable Clear | |
| #define | REG_EVSYS_CHINTENSET19 (*(RwReg8 *)0x4100E0BDUL) |
| (EVSYS) Channel 19 Interrupt Enable Set | |
| #define | REG_EVSYS_CHINTFLAG19 (*(RwReg8 *)0x4100E0BEUL) |
| (EVSYS) Channel 19 Interrupt Flag Status and Clear | |
| #define | REG_EVSYS_CHSTATUS19 (*(RoReg8 *)0x4100E0BFUL) |
| (EVSYS) Channel 19 Status | |
| #define | REG_EVSYS_CHANNEL20 (*(RwReg *)0x4100E0C0UL) |
| (EVSYS) Channel 20 Control | |
| #define | REG_EVSYS_CHINTENCLR20 (*(RwReg8 *)0x4100E0C4UL) |
| (EVSYS) Channel 20 Interrupt Enable Clear | |
| #define | REG_EVSYS_CHINTENSET20 (*(RwReg8 *)0x4100E0C5UL) |
| (EVSYS) Channel 20 Interrupt Enable Set | |
| #define | REG_EVSYS_CHINTFLAG20 (*(RwReg8 *)0x4100E0C6UL) |
| (EVSYS) Channel 20 Interrupt Flag Status and Clear | |
| #define | REG_EVSYS_CHSTATUS20 (*(RoReg8 *)0x4100E0C7UL) |
| (EVSYS) Channel 20 Status | |
| #define | REG_EVSYS_CHANNEL21 (*(RwReg *)0x4100E0C8UL) |
| (EVSYS) Channel 21 Control | |
| #define | REG_EVSYS_CHINTENCLR21 (*(RwReg8 *)0x4100E0CCUL) |
| (EVSYS) Channel 21 Interrupt Enable Clear | |
| #define | REG_EVSYS_CHINTENSET21 (*(RwReg8 *)0x4100E0CDUL) |
| (EVSYS) Channel 21 Interrupt Enable Set | |
| #define | REG_EVSYS_CHINTFLAG21 (*(RwReg8 *)0x4100E0CEUL) |
| (EVSYS) Channel 21 Interrupt Flag Status and Clear | |
| #define | REG_EVSYS_CHSTATUS21 (*(RoReg8 *)0x4100E0CFUL) |
| (EVSYS) Channel 21 Status | |
| #define | REG_EVSYS_CHANNEL22 (*(RwReg *)0x4100E0D0UL) |
| (EVSYS) Channel 22 Control | |
| #define | REG_EVSYS_CHINTENCLR22 (*(RwReg8 *)0x4100E0D4UL) |
| (EVSYS) Channel 22 Interrupt Enable Clear | |
| #define | REG_EVSYS_CHINTENSET22 (*(RwReg8 *)0x4100E0D5UL) |
| (EVSYS) Channel 22 Interrupt Enable Set | |
| #define | REG_EVSYS_CHINTFLAG22 (*(RwReg8 *)0x4100E0D6UL) |
| (EVSYS) Channel 22 Interrupt Flag Status and Clear | |
| #define | REG_EVSYS_CHSTATUS22 (*(RoReg8 *)0x4100E0D7UL) |
| (EVSYS) Channel 22 Status | |
| #define | REG_EVSYS_CHANNEL23 (*(RwReg *)0x4100E0D8UL) |
| (EVSYS) Channel 23 Control | |
| #define | REG_EVSYS_CHINTENCLR23 (*(RwReg8 *)0x4100E0DCUL) |
| (EVSYS) Channel 23 Interrupt Enable Clear | |
| #define | REG_EVSYS_CHINTENSET23 (*(RwReg8 *)0x4100E0DDUL) |
| (EVSYS) Channel 23 Interrupt Enable Set | |
| #define | REG_EVSYS_CHINTFLAG23 (*(RwReg8 *)0x4100E0DEUL) |
| (EVSYS) Channel 23 Interrupt Flag Status and Clear | |
| #define | REG_EVSYS_CHSTATUS23 (*(RoReg8 *)0x4100E0DFUL) |
| (EVSYS) Channel 23 Status | |
| #define | REG_EVSYS_CHANNEL24 (*(RwReg *)0x4100E0E0UL) |
| (EVSYS) Channel 24 Control | |
| #define | REG_EVSYS_CHINTENCLR24 (*(RwReg8 *)0x4100E0E4UL) |
| (EVSYS) Channel 24 Interrupt Enable Clear | |
| #define | REG_EVSYS_CHINTENSET24 (*(RwReg8 *)0x4100E0E5UL) |
| (EVSYS) Channel 24 Interrupt Enable Set | |
| #define | REG_EVSYS_CHINTFLAG24 (*(RwReg8 *)0x4100E0E6UL) |
| (EVSYS) Channel 24 Interrupt Flag Status and Clear | |
| #define | REG_EVSYS_CHSTATUS24 (*(RoReg8 *)0x4100E0E7UL) |
| (EVSYS) Channel 24 Status | |
| #define | REG_EVSYS_CHANNEL25 (*(RwReg *)0x4100E0E8UL) |
| (EVSYS) Channel 25 Control | |
| #define | REG_EVSYS_CHINTENCLR25 (*(RwReg8 *)0x4100E0ECUL) |
| (EVSYS) Channel 25 Interrupt Enable Clear | |
| #define | REG_EVSYS_CHINTENSET25 (*(RwReg8 *)0x4100E0EDUL) |
| (EVSYS) Channel 25 Interrupt Enable Set | |
| #define | REG_EVSYS_CHINTFLAG25 (*(RwReg8 *)0x4100E0EEUL) |
| (EVSYS) Channel 25 Interrupt Flag Status and Clear | |
| #define | REG_EVSYS_CHSTATUS25 (*(RoReg8 *)0x4100E0EFUL) |
| (EVSYS) Channel 25 Status | |
| #define | REG_EVSYS_CHANNEL26 (*(RwReg *)0x4100E0F0UL) |
| (EVSYS) Channel 26 Control | |
| #define | REG_EVSYS_CHINTENCLR26 (*(RwReg8 *)0x4100E0F4UL) |
| (EVSYS) Channel 26 Interrupt Enable Clear | |
| #define | REG_EVSYS_CHINTENSET26 (*(RwReg8 *)0x4100E0F5UL) |
| (EVSYS) Channel 26 Interrupt Enable Set | |
| #define | REG_EVSYS_CHINTFLAG26 (*(RwReg8 *)0x4100E0F6UL) |
| (EVSYS) Channel 26 Interrupt Flag Status and Clear | |
| #define | REG_EVSYS_CHSTATUS26 (*(RoReg8 *)0x4100E0F7UL) |
| (EVSYS) Channel 26 Status | |
| #define | REG_EVSYS_CHANNEL27 (*(RwReg *)0x4100E0F8UL) |
| (EVSYS) Channel 27 Control | |
| #define | REG_EVSYS_CHINTENCLR27 (*(RwReg8 *)0x4100E0FCUL) |
| (EVSYS) Channel 27 Interrupt Enable Clear | |
| #define | REG_EVSYS_CHINTENSET27 (*(RwReg8 *)0x4100E0FDUL) |
| (EVSYS) Channel 27 Interrupt Enable Set | |
| #define | REG_EVSYS_CHINTFLAG27 (*(RwReg8 *)0x4100E0FEUL) |
| (EVSYS) Channel 27 Interrupt Flag Status and Clear | |
| #define | REG_EVSYS_CHSTATUS27 (*(RoReg8 *)0x4100E0FFUL) |
| (EVSYS) Channel 27 Status | |
| #define | REG_EVSYS_CHANNEL28 (*(RwReg *)0x4100E100UL) |
| (EVSYS) Channel 28 Control | |
| #define | REG_EVSYS_CHINTENCLR28 (*(RwReg8 *)0x4100E104UL) |
| (EVSYS) Channel 28 Interrupt Enable Clear | |
| #define | REG_EVSYS_CHINTENSET28 (*(RwReg8 *)0x4100E105UL) |
| (EVSYS) Channel 28 Interrupt Enable Set | |
| #define | REG_EVSYS_CHINTFLAG28 (*(RwReg8 *)0x4100E106UL) |
| (EVSYS) Channel 28 Interrupt Flag Status and Clear | |
| #define | REG_EVSYS_CHSTATUS28 (*(RoReg8 *)0x4100E107UL) |
| (EVSYS) Channel 28 Status | |
| #define | REG_EVSYS_CHANNEL29 (*(RwReg *)0x4100E108UL) |
| (EVSYS) Channel 29 Control | |
| #define | REG_EVSYS_CHINTENCLR29 (*(RwReg8 *)0x4100E10CUL) |
| (EVSYS) Channel 29 Interrupt Enable Clear | |
| #define | REG_EVSYS_CHINTENSET29 (*(RwReg8 *)0x4100E10DUL) |
| (EVSYS) Channel 29 Interrupt Enable Set | |
| #define | REG_EVSYS_CHINTFLAG29 (*(RwReg8 *)0x4100E10EUL) |
| (EVSYS) Channel 29 Interrupt Flag Status and Clear | |
| #define | REG_EVSYS_CHSTATUS29 (*(RoReg8 *)0x4100E10FUL) |
| (EVSYS) Channel 29 Status | |
| #define | REG_EVSYS_CHANNEL30 (*(RwReg *)0x4100E110UL) |
| (EVSYS) Channel 30 Control | |
| #define | REG_EVSYS_CHINTENCLR30 (*(RwReg8 *)0x4100E114UL) |
| (EVSYS) Channel 30 Interrupt Enable Clear | |
| #define | REG_EVSYS_CHINTENSET30 (*(RwReg8 *)0x4100E115UL) |
| (EVSYS) Channel 30 Interrupt Enable Set | |
| #define | REG_EVSYS_CHINTFLAG30 (*(RwReg8 *)0x4100E116UL) |
| (EVSYS) Channel 30 Interrupt Flag Status and Clear | |
| #define | REG_EVSYS_CHSTATUS30 (*(RoReg8 *)0x4100E117UL) |
| (EVSYS) Channel 30 Status | |
| #define | REG_EVSYS_CHANNEL31 (*(RwReg *)0x4100E118UL) |
| (EVSYS) Channel 31 Control | |
| #define | REG_EVSYS_CHINTENCLR31 (*(RwReg8 *)0x4100E11CUL) |
| (EVSYS) Channel 31 Interrupt Enable Clear | |
| #define | REG_EVSYS_CHINTENSET31 (*(RwReg8 *)0x4100E11DUL) |
| (EVSYS) Channel 31 Interrupt Enable Set | |
| #define | REG_EVSYS_CHINTFLAG31 (*(RwReg8 *)0x4100E11EUL) |
| (EVSYS) Channel 31 Interrupt Flag Status and Clear | |
| #define | REG_EVSYS_CHSTATUS31 (*(RoReg8 *)0x4100E11FUL) |
| (EVSYS) Channel 31 Status | |
| #define | REG_EVSYS_USER0 (*(RwReg *)0x4100E120UL) |
| (EVSYS) User Multiplexer 0 | |
| #define | REG_EVSYS_USER1 (*(RwReg *)0x4100E124UL) |
| (EVSYS) User Multiplexer 1 | |
| #define | REG_EVSYS_USER2 (*(RwReg *)0x4100E128UL) |
| (EVSYS) User Multiplexer 2 | |
| #define | REG_EVSYS_USER3 (*(RwReg *)0x4100E12CUL) |
| (EVSYS) User Multiplexer 3 | |
| #define | REG_EVSYS_USER4 (*(RwReg *)0x4100E130UL) |
| (EVSYS) User Multiplexer 4 | |
| #define | REG_EVSYS_USER5 (*(RwReg *)0x4100E134UL) |
| (EVSYS) User Multiplexer 5 | |
| #define | REG_EVSYS_USER6 (*(RwReg *)0x4100E138UL) |
| (EVSYS) User Multiplexer 6 | |
| #define | REG_EVSYS_USER7 (*(RwReg *)0x4100E13CUL) |
| (EVSYS) User Multiplexer 7 | |
| #define | REG_EVSYS_USER8 (*(RwReg *)0x4100E140UL) |
| (EVSYS) User Multiplexer 8 | |
| #define | REG_EVSYS_USER9 (*(RwReg *)0x4100E144UL) |
| (EVSYS) User Multiplexer 9 | |
| #define | REG_EVSYS_USER10 (*(RwReg *)0x4100E148UL) |
| (EVSYS) User Multiplexer 10 | |
| #define | REG_EVSYS_USER11 (*(RwReg *)0x4100E14CUL) |
| (EVSYS) User Multiplexer 11 | |
| #define | REG_EVSYS_USER12 (*(RwReg *)0x4100E150UL) |
| (EVSYS) User Multiplexer 12 | |
| #define | REG_EVSYS_USER13 (*(RwReg *)0x4100E154UL) |
| (EVSYS) User Multiplexer 13 | |
| #define | REG_EVSYS_USER14 (*(RwReg *)0x4100E158UL) |
| (EVSYS) User Multiplexer 14 | |
| #define | REG_EVSYS_USER15 (*(RwReg *)0x4100E15CUL) |
| (EVSYS) User Multiplexer 15 | |
| #define | REG_EVSYS_USER16 (*(RwReg *)0x4100E160UL) |
| (EVSYS) User Multiplexer 16 | |
| #define | REG_EVSYS_USER17 (*(RwReg *)0x4100E164UL) |
| (EVSYS) User Multiplexer 17 | |
| #define | REG_EVSYS_USER18 (*(RwReg *)0x4100E168UL) |
| (EVSYS) User Multiplexer 18 | |
| #define | REG_EVSYS_USER19 (*(RwReg *)0x4100E16CUL) |
| (EVSYS) User Multiplexer 19 | |
| #define | REG_EVSYS_USER20 (*(RwReg *)0x4100E170UL) |
| (EVSYS) User Multiplexer 20 | |
| #define | REG_EVSYS_USER21 (*(RwReg *)0x4100E174UL) |
| (EVSYS) User Multiplexer 21 | |
| #define | REG_EVSYS_USER22 (*(RwReg *)0x4100E178UL) |
| (EVSYS) User Multiplexer 22 | |
| #define | REG_EVSYS_USER23 (*(RwReg *)0x4100E17CUL) |
| (EVSYS) User Multiplexer 23 | |
| #define | REG_EVSYS_USER24 (*(RwReg *)0x4100E180UL) |
| (EVSYS) User Multiplexer 24 | |
| #define | REG_EVSYS_USER25 (*(RwReg *)0x4100E184UL) |
| (EVSYS) User Multiplexer 25 | |
| #define | REG_EVSYS_USER26 (*(RwReg *)0x4100E188UL) |
| (EVSYS) User Multiplexer 26 | |
| #define | REG_EVSYS_USER27 (*(RwReg *)0x4100E18CUL) |
| (EVSYS) User Multiplexer 27 | |
| #define | REG_EVSYS_USER28 (*(RwReg *)0x4100E190UL) |
| (EVSYS) User Multiplexer 28 | |
| #define | REG_EVSYS_USER29 (*(RwReg *)0x4100E194UL) |
| (EVSYS) User Multiplexer 29 | |
| #define | REG_EVSYS_USER30 (*(RwReg *)0x4100E198UL) |
| (EVSYS) User Multiplexer 30 | |
| #define | REG_EVSYS_USER31 (*(RwReg *)0x4100E19CUL) |
| (EVSYS) User Multiplexer 31 | |
| #define | REG_EVSYS_USER32 (*(RwReg *)0x4100E1A0UL) |
| (EVSYS) User Multiplexer 32 | |
| #define | REG_EVSYS_USER33 (*(RwReg *)0x4100E1A4UL) |
| (EVSYS) User Multiplexer 33 | |
| #define | REG_EVSYS_USER34 (*(RwReg *)0x4100E1A8UL) |
| (EVSYS) User Multiplexer 34 | |
| #define | REG_EVSYS_USER35 (*(RwReg *)0x4100E1ACUL) |
| (EVSYS) User Multiplexer 35 | |
| #define | REG_EVSYS_USER36 (*(RwReg *)0x4100E1B0UL) |
| (EVSYS) User Multiplexer 36 | |
| #define | REG_EVSYS_USER37 (*(RwReg *)0x4100E1B4UL) |
| (EVSYS) User Multiplexer 37 | |
| #define | REG_EVSYS_USER38 (*(RwReg *)0x4100E1B8UL) |
| (EVSYS) User Multiplexer 38 | |
| #define | REG_EVSYS_USER39 (*(RwReg *)0x4100E1BCUL) |
| (EVSYS) User Multiplexer 39 | |
| #define | REG_EVSYS_USER40 (*(RwReg *)0x4100E1C0UL) |
| (EVSYS) User Multiplexer 40 | |
| #define | REG_EVSYS_USER41 (*(RwReg *)0x4100E1C4UL) |
| (EVSYS) User Multiplexer 41 | |
| #define | REG_EVSYS_USER42 (*(RwReg *)0x4100E1C8UL) |
| (EVSYS) User Multiplexer 42 | |
| #define | REG_EVSYS_USER43 (*(RwReg *)0x4100E1CCUL) |
| (EVSYS) User Multiplexer 43 | |
| #define | REG_EVSYS_USER44 (*(RwReg *)0x4100E1D0UL) |
| (EVSYS) User Multiplexer 44 | |
| #define | REG_EVSYS_USER45 (*(RwReg *)0x4100E1D4UL) |
| (EVSYS) User Multiplexer 45 | |
| #define | REG_EVSYS_USER46 (*(RwReg *)0x4100E1D8UL) |
| (EVSYS) User Multiplexer 46 | |
| #define | REG_EVSYS_USER47 (*(RwReg *)0x4100E1DCUL) |
| (EVSYS) User Multiplexer 47 | |
| #define | REG_EVSYS_USER48 (*(RwReg *)0x4100E1E0UL) |
| (EVSYS) User Multiplexer 48 | |
| #define | REG_EVSYS_USER49 (*(RwReg *)0x4100E1E4UL) |
| (EVSYS) User Multiplexer 49 | |
| #define | REG_EVSYS_USER50 (*(RwReg *)0x4100E1E8UL) |
| (EVSYS) User Multiplexer 50 | |
| #define | REG_EVSYS_USER51 (*(RwReg *)0x4100E1ECUL) |
| (EVSYS) User Multiplexer 51 | |
| #define | REG_EVSYS_USER52 (*(RwReg *)0x4100E1F0UL) |
| (EVSYS) User Multiplexer 52 | |
| #define | REG_EVSYS_USER53 (*(RwReg *)0x4100E1F4UL) |
| (EVSYS) User Multiplexer 53 | |
| #define | REG_EVSYS_USER54 (*(RwReg *)0x4100E1F8UL) |
| (EVSYS) User Multiplexer 54 | |
| #define | REG_EVSYS_USER55 (*(RwReg *)0x4100E1FCUL) |
| (EVSYS) User Multiplexer 55 | |
| #define | REG_EVSYS_USER56 (*(RwReg *)0x4100E200UL) |
| (EVSYS) User Multiplexer 56 | |
| #define | REG_EVSYS_USER57 (*(RwReg *)0x4100E204UL) |
| (EVSYS) User Multiplexer 57 | |
| #define | REG_EVSYS_USER58 (*(RwReg *)0x4100E208UL) |
| (EVSYS) User Multiplexer 58 | |
| #define | REG_EVSYS_USER59 (*(RwReg *)0x4100E20CUL) |
| (EVSYS) User Multiplexer 59 | |
| #define | REG_EVSYS_USER60 (*(RwReg *)0x4100E210UL) |
| (EVSYS) User Multiplexer 60 | |
| #define | REG_EVSYS_USER61 (*(RwReg *)0x4100E214UL) |
| (EVSYS) User Multiplexer 61 | |
| #define | REG_EVSYS_USER62 (*(RwReg *)0x4100E218UL) |
| (EVSYS) User Multiplexer 62 | |
| #define | REG_EVSYS_USER63 (*(RwReg *)0x4100E21CUL) |
| (EVSYS) User Multiplexer 63 | |
| #define | REG_EVSYS_USER64 (*(RwReg *)0x4100E220UL) |
| (EVSYS) User Multiplexer 64 | |
| #define | REG_EVSYS_USER65 (*(RwReg *)0x4100E224UL) |
| (EVSYS) User Multiplexer 65 | |
| #define | REG_EVSYS_USER66 (*(RwReg *)0x4100E228UL) |
| (EVSYS) User Multiplexer 66 | |
| #define | EVSYS_ASYNCHRONOUS_CHANNELS 0xFFFFF000 |
| #define | EVSYS_CHANNELS 32 |
| #define | EVSYS_CHANNELS_BITS 5 |
| #define | EVSYS_EXTEVT_NUM 0 |
| #define | EVSYS_GCLK_ID_0 11 |
| #define | EVSYS_GCLK_ID_1 12 |
| #define | EVSYS_GCLK_ID_2 13 |
| #define | EVSYS_GCLK_ID_3 14 |
| #define | EVSYS_GCLK_ID_4 15 |
| #define | EVSYS_GCLK_ID_5 16 |
| #define | EVSYS_GCLK_ID_6 17 |
| #define | EVSYS_GCLK_ID_7 18 |
| #define | EVSYS_GCLK_ID_8 19 |
| #define | EVSYS_GCLK_ID_9 20 |
| #define | EVSYS_GCLK_ID_10 21 |
| #define | EVSYS_GCLK_ID_11 22 |
| #define | EVSYS_GCLK_ID_LSB 11 |
| #define | EVSYS_GCLK_ID_MSB 22 |
| #define | EVSYS_GCLK_ID_SIZE 12 |
| #define | EVSYS_GENERATORS 119 |
| #define | EVSYS_GENERATORS_BITS 7 |
| #define | EVSYS_SYNCH_NUM 12 |
| #define | EVSYS_SYNCH_NUM_BITS 4 |
| #define | EVSYS_USERS 67 |
| #define | EVSYS_USERS_BITS 7 |
| #define | EVSYS_ID_GEN_OSCCTRL_XOSC_FAIL_0 1 |
| #define | EVSYS_ID_GEN_OSCCTRL_XOSC_FAIL_1 2 |
| #define | EVSYS_ID_GEN_OSC32KCTRL_XOSC32K_FAIL 3 |
| #define | EVSYS_ID_GEN_RTC_PER_0 4 |
| #define | EVSYS_ID_GEN_RTC_PER_1 5 |
| #define | EVSYS_ID_GEN_RTC_PER_2 6 |
| #define | EVSYS_ID_GEN_RTC_PER_3 7 |
| #define | EVSYS_ID_GEN_RTC_PER_4 8 |
| #define | EVSYS_ID_GEN_RTC_PER_5 9 |
| #define | EVSYS_ID_GEN_RTC_PER_6 10 |
| #define | EVSYS_ID_GEN_RTC_PER_7 11 |
| #define | EVSYS_ID_GEN_RTC_CMP_0 12 |
| #define | EVSYS_ID_GEN_RTC_CMP_1 13 |
| #define | EVSYS_ID_GEN_RTC_CMP_2 14 |
| #define | EVSYS_ID_GEN_RTC_CMP_3 15 |
| #define | EVSYS_ID_GEN_RTC_TAMPER 16 |
| #define | EVSYS_ID_GEN_RTC_OVF 17 |
| #define | EVSYS_ID_GEN_EIC_EXTINT_0 18 |
| #define | EVSYS_ID_GEN_EIC_EXTINT_1 19 |
| #define | EVSYS_ID_GEN_EIC_EXTINT_2 20 |
| #define | EVSYS_ID_GEN_EIC_EXTINT_3 21 |
| #define | EVSYS_ID_GEN_EIC_EXTINT_4 22 |
| #define | EVSYS_ID_GEN_EIC_EXTINT_5 23 |
| #define | EVSYS_ID_GEN_EIC_EXTINT_6 24 |
| #define | EVSYS_ID_GEN_EIC_EXTINT_7 25 |
| #define | EVSYS_ID_GEN_EIC_EXTINT_8 26 |
| #define | EVSYS_ID_GEN_EIC_EXTINT_9 27 |
| #define | EVSYS_ID_GEN_EIC_EXTINT_10 28 |
| #define | EVSYS_ID_GEN_EIC_EXTINT_11 29 |
| #define | EVSYS_ID_GEN_EIC_EXTINT_12 30 |
| #define | EVSYS_ID_GEN_EIC_EXTINT_13 31 |
| #define | EVSYS_ID_GEN_EIC_EXTINT_14 32 |
| #define | EVSYS_ID_GEN_EIC_EXTINT_15 33 |
| #define | EVSYS_ID_GEN_DMAC_CH_0 34 |
| #define | EVSYS_ID_GEN_DMAC_CH_1 35 |
| #define | EVSYS_ID_GEN_DMAC_CH_2 36 |
| #define | EVSYS_ID_GEN_DMAC_CH_3 37 |
| #define | EVSYS_ID_GEN_PAC_ACCERR 38 |
| #define | EVSYS_ID_GEN_TCC0_OVF 41 |
| #define | EVSYS_ID_GEN_TCC0_TRG 42 |
| #define | EVSYS_ID_GEN_TCC0_CNT 43 |
| #define | EVSYS_ID_GEN_TCC0_MC_0 44 |
| #define | EVSYS_ID_GEN_TCC0_MC_1 45 |
| #define | EVSYS_ID_GEN_TCC0_MC_2 46 |
| #define | EVSYS_ID_GEN_TCC0_MC_3 47 |
| #define | EVSYS_ID_GEN_TCC0_MC_4 48 |
| #define | EVSYS_ID_GEN_TCC0_MC_5 49 |
| #define | EVSYS_ID_GEN_TCC1_OVF 50 |
| #define | EVSYS_ID_GEN_TCC1_TRG 51 |
| #define | EVSYS_ID_GEN_TCC1_CNT 52 |
| #define | EVSYS_ID_GEN_TCC1_MC_0 53 |
| #define | EVSYS_ID_GEN_TCC1_MC_1 54 |
| #define | EVSYS_ID_GEN_TCC1_MC_2 55 |
| #define | EVSYS_ID_GEN_TCC1_MC_3 56 |
| #define | EVSYS_ID_GEN_TCC2_OVF 57 |
| #define | EVSYS_ID_GEN_TCC2_TRG 58 |
| #define | EVSYS_ID_GEN_TCC2_CNT 59 |
| #define | EVSYS_ID_GEN_TCC2_MC_0 60 |
| #define | EVSYS_ID_GEN_TCC2_MC_1 61 |
| #define | EVSYS_ID_GEN_TCC2_MC_2 62 |
| #define | EVSYS_ID_GEN_TCC3_OVF 63 |
| #define | EVSYS_ID_GEN_TCC3_TRG 64 |
| #define | EVSYS_ID_GEN_TCC3_CNT 65 |
| #define | EVSYS_ID_GEN_TCC3_MC_0 66 |
| #define | EVSYS_ID_GEN_TCC3_MC_1 67 |
| #define | EVSYS_ID_GEN_TCC4_OVF 68 |
| #define | EVSYS_ID_GEN_TCC4_TRG 69 |
| #define | EVSYS_ID_GEN_TCC4_CNT 70 |
| #define | EVSYS_ID_GEN_TCC4_MC_0 71 |
| #define | EVSYS_ID_GEN_TCC4_MC_1 72 |
| #define | EVSYS_ID_GEN_TC0_OVF 73 |
| #define | EVSYS_ID_GEN_TC0_MC_0 74 |
| #define | EVSYS_ID_GEN_TC0_MC_1 75 |
| #define | EVSYS_ID_GEN_TC1_OVF 76 |
| #define | EVSYS_ID_GEN_TC1_MC_0 77 |
| #define | EVSYS_ID_GEN_TC1_MC_1 78 |
| #define | EVSYS_ID_GEN_TC2_OVF 79 |
| #define | EVSYS_ID_GEN_TC2_MC_0 80 |
| #define | EVSYS_ID_GEN_TC2_MC_1 81 |
| #define | EVSYS_ID_GEN_TC3_OVF 82 |
| #define | EVSYS_ID_GEN_TC3_MC_0 83 |
| #define | EVSYS_ID_GEN_TC3_MC_1 84 |
| #define | EVSYS_ID_GEN_TC4_OVF 85 |
| #define | EVSYS_ID_GEN_TC4_MC_0 86 |
| #define | EVSYS_ID_GEN_TC4_MC_1 87 |
| #define | EVSYS_ID_GEN_TC5_OVF 88 |
| #define | EVSYS_ID_GEN_TC5_MC_0 89 |
| #define | EVSYS_ID_GEN_TC5_MC_1 90 |
| #define | EVSYS_ID_GEN_TC6_OVF 91 |
| #define | EVSYS_ID_GEN_TC6_MC_0 92 |
| #define | EVSYS_ID_GEN_TC6_MC_1 93 |
| #define | EVSYS_ID_GEN_TC7_OVF 94 |
| #define | EVSYS_ID_GEN_TC7_MC_0 95 |
| #define | EVSYS_ID_GEN_TC7_MC_1 96 |
| #define | EVSYS_ID_GEN_PDEC_OVF 97 |
| #define | EVSYS_ID_GEN_PDEC_ERR 98 |
| #define | EVSYS_ID_GEN_PDEC_DIR 99 |
| #define | EVSYS_ID_GEN_PDEC_VLC 100 |
| #define | EVSYS_ID_GEN_PDEC_MC_0 101 |
| #define | EVSYS_ID_GEN_PDEC_MC_1 102 |
| #define | EVSYS_ID_GEN_ADC0_RESRDY 103 |
| #define | EVSYS_ID_GEN_ADC0_WINMON 104 |
| #define | EVSYS_ID_GEN_ADC1_RESRDY 105 |
| #define | EVSYS_ID_GEN_ADC1_WINMON 106 |
| #define | EVSYS_ID_GEN_AC_COMP_0 107 |
| #define | EVSYS_ID_GEN_AC_COMP_1 108 |
| #define | EVSYS_ID_GEN_AC_WIN_0 109 |
| #define | EVSYS_ID_GEN_DAC_EMPTY_0 110 |
| #define | EVSYS_ID_GEN_DAC_EMPTY_1 111 |
| #define | EVSYS_ID_GEN_DAC_RESRDY_0 112 |
| #define | EVSYS_ID_GEN_DAC_RESRDY_1 113 |
| #define | EVSYS_ID_GEN_GMAC_TSU_CMP 114 |
| #define | EVSYS_ID_GEN_TRNG_READY 115 |
| #define | EVSYS_ID_GEN_CCL_LUTOUT_0 116 |
| #define | EVSYS_ID_GEN_CCL_LUTOUT_1 117 |
| #define | EVSYS_ID_GEN_CCL_LUTOUT_2 118 |
| #define | EVSYS_ID_GEN_CCL_LUTOUT_3 119 |
| #define | EVSYS_ID_USER_RTC_TAMPER 0 |
| #define | EVSYS_ID_USER_PORT_EV_0 1 |
| #define | EVSYS_ID_USER_PORT_EV_1 2 |
| #define | EVSYS_ID_USER_PORT_EV_2 3 |
| #define | EVSYS_ID_USER_PORT_EV_3 4 |
| #define | EVSYS_ID_USER_DMAC_CH_0 5 |
| #define | EVSYS_ID_USER_DMAC_CH_1 6 |
| #define | EVSYS_ID_USER_DMAC_CH_2 7 |
| #define | EVSYS_ID_USER_DMAC_CH_3 8 |
| #define | EVSYS_ID_USER_DMAC_CH_4 9 |
| #define | EVSYS_ID_USER_DMAC_CH_5 10 |
| #define | EVSYS_ID_USER_DMAC_CH_6 11 |
| #define | EVSYS_ID_USER_DMAC_CH_7 12 |
| #define | EVSYS_ID_USER_CM4_TRACE_START 14 |
| #define | EVSYS_ID_USER_CM4_TRACE_STOP 15 |
| #define | EVSYS_ID_USER_CM4_TRACE_TRIG 16 |
| #define | EVSYS_ID_USER_TCC0_EV_0 17 |
| #define | EVSYS_ID_USER_TCC0_EV_1 18 |
| #define | EVSYS_ID_USER_TCC0_MC_0 19 |
| #define | EVSYS_ID_USER_TCC0_MC_1 20 |
| #define | EVSYS_ID_USER_TCC0_MC_2 21 |
| #define | EVSYS_ID_USER_TCC0_MC_3 22 |
| #define | EVSYS_ID_USER_TCC0_MC_4 23 |
| #define | EVSYS_ID_USER_TCC0_MC_5 24 |
| #define | EVSYS_ID_USER_TCC1_EV_0 25 |
| #define | EVSYS_ID_USER_TCC1_EV_1 26 |
| #define | EVSYS_ID_USER_TCC1_MC_0 27 |
| #define | EVSYS_ID_USER_TCC1_MC_1 28 |
| #define | EVSYS_ID_USER_TCC1_MC_2 29 |
| #define | EVSYS_ID_USER_TCC1_MC_3 30 |
| #define | EVSYS_ID_USER_TCC2_EV_0 31 |
| #define | EVSYS_ID_USER_TCC2_EV_1 32 |
| #define | EVSYS_ID_USER_TCC2_MC_0 33 |
| #define | EVSYS_ID_USER_TCC2_MC_1 34 |
| #define | EVSYS_ID_USER_TCC2_MC_2 35 |
| #define | EVSYS_ID_USER_TCC3_EV_0 36 |
| #define | EVSYS_ID_USER_TCC3_EV_1 37 |
| #define | EVSYS_ID_USER_TCC3_MC_0 38 |
| #define | EVSYS_ID_USER_TCC3_MC_1 39 |
| #define | EVSYS_ID_USER_TCC4_EV_0 40 |
| #define | EVSYS_ID_USER_TCC4_EV_1 41 |
| #define | EVSYS_ID_USER_TCC4_MC_0 42 |
| #define | EVSYS_ID_USER_TCC4_MC_1 43 |
| #define | EVSYS_ID_USER_TC0_EVU 44 |
| #define | EVSYS_ID_USER_TC1_EVU 45 |
| #define | EVSYS_ID_USER_TC2_EVU 46 |
| #define | EVSYS_ID_USER_TC3_EVU 47 |
| #define | EVSYS_ID_USER_TC4_EVU 48 |
| #define | EVSYS_ID_USER_TC5_EVU 49 |
| #define | EVSYS_ID_USER_TC6_EVU 50 |
| #define | EVSYS_ID_USER_TC7_EVU 51 |
| #define | EVSYS_ID_USER_PDEC_EVU_0 52 |
| #define | EVSYS_ID_USER_PDEC_EVU_1 53 |
| #define | EVSYS_ID_USER_PDEC_EVU_2 54 |
| #define | EVSYS_ID_USER_ADC0_START 55 |
| #define | EVSYS_ID_USER_ADC0_SYNC 56 |
| #define | EVSYS_ID_USER_ADC1_START 57 |
| #define | EVSYS_ID_USER_ADC1_SYNC 58 |
| #define | EVSYS_ID_USER_AC_SOC_0 59 |
| #define | EVSYS_ID_USER_AC_SOC_1 60 |
| #define | EVSYS_ID_USER_DAC_START_0 61 |
| #define | EVSYS_ID_USER_DAC_START_1 62 |
| #define | EVSYS_ID_USER_CCL_LUTIN_0 63 |
| #define | EVSYS_ID_USER_CCL_LUTIN_1 64 |
| #define | EVSYS_ID_USER_CCL_LUTIN_2 65 |
| #define | EVSYS_ID_USER_CCL_LUTIN_3 66 |
Instance description for EVSYS.
Copyright (c) 2019 Microchip Technology Inc.
\asf_license_start
Definition in file evsys.h.
1.8.20