Instance description for PORT. More...

Macros
#define	REG_PORT_DIR0 ((RwReg )0x41008000UL)
	(PORT) Data Direction 0

#define	REG_PORT_DIRCLR0 ((RwReg )0x41008004UL)
	(PORT) Data Direction Clear 0

#define	REG_PORT_DIRSET0 ((RwReg )0x41008008UL)
	(PORT) Data Direction Set 0

#define	REG_PORT_DIRTGL0 ((RwReg )0x4100800CUL)
	(PORT) Data Direction Toggle 0

#define	REG_PORT_OUT0 ((RwReg )0x41008010UL)
	(PORT) Data Output Value 0

#define	REG_PORT_OUTCLR0 ((RwReg )0x41008014UL)
	(PORT) Data Output Value Clear 0

#define	REG_PORT_OUTSET0 ((RwReg )0x41008018UL)
	(PORT) Data Output Value Set 0

#define	REG_PORT_OUTTGL0 ((RwReg )0x4100801CUL)
	(PORT) Data Output Value Toggle 0

#define	REG_PORT_IN0 ((RoReg )0x41008020UL)
	(PORT) Data Input Value 0

#define	REG_PORT_CTRL0 ((RwReg )0x41008024UL)
	(PORT) Control 0

#define	REG_PORT_WRCONFIG0 ((WoReg )0x41008028UL)
	(PORT) Write Configuration 0

#define	REG_PORT_EVCTRL0 ((RwReg )0x4100802CUL)
	(PORT) Event Input Control 0

#define	REG_PORT_PMUX0 ((RwReg8 )0x41008030UL)
	(PORT) Peripheral Multiplexing 0

#define	REG_PORT_PINCFG0 ((RwReg8 )0x41008040UL)
	(PORT) Pin Configuration 0

#define	REG_PORT_DIR1 ((RwReg )0x41008080UL)
	(PORT) Data Direction 1

#define	REG_PORT_DIRCLR1 ((RwReg )0x41008084UL)
	(PORT) Data Direction Clear 1

#define	REG_PORT_DIRSET1 ((RwReg )0x41008088UL)
	(PORT) Data Direction Set 1

#define	REG_PORT_DIRTGL1 ((RwReg )0x4100808CUL)
	(PORT) Data Direction Toggle 1

#define	REG_PORT_OUT1 ((RwReg )0x41008090UL)
	(PORT) Data Output Value 1

#define	REG_PORT_OUTCLR1 ((RwReg )0x41008094UL)
	(PORT) Data Output Value Clear 1

#define	REG_PORT_OUTSET1 ((RwReg )0x41008098UL)
	(PORT) Data Output Value Set 1

#define	REG_PORT_OUTTGL1 ((RwReg )0x4100809CUL)
	(PORT) Data Output Value Toggle 1

#define	REG_PORT_IN1 ((RoReg )0x410080A0UL)
	(PORT) Data Input Value 1

#define	REG_PORT_CTRL1 ((RwReg )0x410080A4UL)
	(PORT) Control 1

#define	REG_PORT_WRCONFIG1 ((WoReg )0x410080A8UL)
	(PORT) Write Configuration 1

#define	REG_PORT_EVCTRL1 ((RwReg )0x410080ACUL)
	(PORT) Event Input Control 1

#define	REG_PORT_PMUX1 ((RwReg8 )0x410080B0UL)
	(PORT) Peripheral Multiplexing 1

#define	REG_PORT_PINCFG1 ((RwReg8 )0x410080C0UL)
	(PORT) Pin Configuration 1

#define	REG_PORT_DIR2 ((RwReg )0x41008100UL)
	(PORT) Data Direction 2

#define	REG_PORT_DIRCLR2 ((RwReg )0x41008104UL)
	(PORT) Data Direction Clear 2

#define	REG_PORT_DIRSET2 ((RwReg )0x41008108UL)
	(PORT) Data Direction Set 2

#define	REG_PORT_DIRTGL2 ((RwReg )0x4100810CUL)
	(PORT) Data Direction Toggle 2

#define	REG_PORT_OUT2 ((RwReg )0x41008110UL)
	(PORT) Data Output Value 2

#define	REG_PORT_OUTCLR2 ((RwReg )0x41008114UL)
	(PORT) Data Output Value Clear 2

#define	REG_PORT_OUTSET2 ((RwReg )0x41008118UL)
	(PORT) Data Output Value Set 2

#define	REG_PORT_OUTTGL2 ((RwReg )0x4100811CUL)
	(PORT) Data Output Value Toggle 2

#define	REG_PORT_IN2 ((RoReg )0x41008120UL)
	(PORT) Data Input Value 2

#define	REG_PORT_CTRL2 ((RwReg )0x41008124UL)
	(PORT) Control 2

#define	REG_PORT_WRCONFIG2 ((WoReg )0x41008128UL)
	(PORT) Write Configuration 2

#define	REG_PORT_EVCTRL2 ((RwReg )0x4100812CUL)
	(PORT) Event Input Control 2

#define	REG_PORT_PMUX2 ((RwReg8 )0x41008130UL)
	(PORT) Peripheral Multiplexing 2

#define	REG_PORT_PINCFG2 ((RwReg8 )0x41008140UL)
	(PORT) Pin Configuration 2

#define	REG_PORT_DIR3 ((RwReg )0x41008180UL)
	(PORT) Data Direction 3

#define	REG_PORT_DIRCLR3 ((RwReg )0x41008184UL)
	(PORT) Data Direction Clear 3

#define	REG_PORT_DIRSET3 ((RwReg )0x41008188UL)
	(PORT) Data Direction Set 3

#define	REG_PORT_DIRTGL3 ((RwReg )0x4100818CUL)
	(PORT) Data Direction Toggle 3

#define	REG_PORT_OUT3 ((RwReg )0x41008190UL)
	(PORT) Data Output Value 3

#define	REG_PORT_OUTCLR3 ((RwReg )0x41008194UL)
	(PORT) Data Output Value Clear 3

#define	REG_PORT_OUTSET3 ((RwReg )0x41008198UL)
	(PORT) Data Output Value Set 3

#define	REG_PORT_OUTTGL3 ((RwReg )0x4100819CUL)
	(PORT) Data Output Value Toggle 3

#define	REG_PORT_IN3 ((RoReg )0x410081A0UL)
	(PORT) Data Input Value 3

#define	REG_PORT_CTRL3 ((RwReg )0x410081A4UL)
	(PORT) Control 3

#define	REG_PORT_WRCONFIG3 ((WoReg )0x410081A8UL)
	(PORT) Write Configuration 3

#define	REG_PORT_EVCTRL3 ((RwReg )0x410081ACUL)
	(PORT) Event Input Control 3

#define	REG_PORT_PMUX3 ((RwReg8 )0x410081B0UL)
	(PORT) Peripheral Multiplexing 3

#define	REG_PORT_PINCFG3 ((RwReg8 )0x410081C0UL)
	(PORT) Pin Configuration 3

#define	PORT_BITS 118

#define	PORT_DIR_DEFAULT_VAL { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }

#define	PORT_DIR_IMPLEMENTED { 0xCBFFFFFF, 0xFFFFFFFF, 0xDFFFFCFF, 0x00301F03 }

#define	PORT_DRVSTR 1

#define	PORT_DRVSTR_DEFAULT_VAL { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }

#define	PORT_DRVSTR_IMPLEMENTED { 0xC8FFFFFF, 0xFFFFFFFF, 0xDFFFFCFF, 0x00301F03 }

#define	PORT_EVENT_IMPLEMENTED { 0xCBFFFFFF, 0xFFFFFFFF, 0xDFFFFCFF, 0x00301F03 }

#define	PORT_EV_NUM 4

#define	PORT_INEN_DEFAULT_VAL { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }

#define	PORT_INEN_IMPLEMENTED { 0xCBFFFFFF, 0xFFFFFFFF, 0xDFFFFCFF, 0x00301F03 }

#define	PORT_ODRAIN 0

#define	PORT_ODRAIN_DEFAULT_VAL { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }

#define	PORT_ODRAIN_IMPLEMENTED { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }

#define	PORT_OUT_DEFAULT_VAL { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }

#define	PORT_OUT_IMPLEMENTED { 0xCBFFFFFF, 0xFFFFFFFF, 0xDFFFFCFF, 0x00301F03 }

#define	PORT_PIN_IMPLEMENTED { 0xCBFFFFFF, 0xFFFFFFFF, 0xDFFFFCFF, 0x00301F03 }

#define	PORT_PMUXBIT0_DEFAULT_VAL { 0x40000000, 0x00000000, 0x00000000, 0x00000000 }

#define	PORT_PMUXBIT0_IMPLEMENTED { 0xCBFFFFFF, 0xFFFFFFFF, 0xDFFFFC1F, 0x00301F03 }

#define	PORT_PMUXBIT1_DEFAULT_VAL { 0x40000000, 0x00000000, 0x00000000, 0x00000000 }

#define	PORT_PMUXBIT1_IMPLEMENTED { 0xCBFFFFFB, 0xFFFFFFFF, 0x1FFFFCF0, 0x00300F00 }

#define	PORT_PMUXBIT2_DEFAULT_VAL { 0x40000000, 0x00000000, 0x00000000, 0x00000000 }

#define	PORT_PMUXBIT2_IMPLEMENTED { 0xCBFFFFFB, 0xFFFFFFFF, 0x1FFFFC10, 0x00301F00 }

#define	PORT_PMUXBIT3_DEFAULT_VAL { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }

#define	PORT_PMUXBIT3_IMPLEMENTED { 0xCBFFFFF8, 0x33FFFFFF, 0x18FFF8C0, 0x00300000 }

#define	PORT_PMUXEN_DEFAULT_VAL { 0x40000000, 0x00000000, 0x00000000, 0x00000000 }

#define	PORT_PMUXEN_IMPLEMENTED { 0xCBFFFFFF, 0xFFFFFFFF, 0xDFFFFCFF, 0x00301F03 }

#define	PORT_PPP_IMPLEMENTED { 0x00000001 }

#define	PORT_PULLEN_DEFAULT_VAL { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }

#define	PORT_PULLEN_IMPLEMENTED { 0xCBFFFFFF, 0xFFFFFFFF, 0xDFFFFCFF, 0x00301F03 }

#define	PORT_SLEWLIM 0

#define	PORT_SLEWLIM_DEFAULT_VAL { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }

#define	PORT_SLEWLIM_IMPLEMENTED { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }

Detailed Description

Instance description for PORT.

\asf_license_start

Definition in file port.h.

Macros

Detailed Description