Component description for PM. More...

Data Structures
union	PM_CTRLA_Type

union	PM_SLEEPCFG_Type

union	PM_INTENCLR_Type

union	PM_INTENSET_Type

union	PM_INTFLAG_Type

union	PM_STDBYCFG_Type

union	PM_HIBCFG_Type

union	PM_BKUPCFG_Type

union	PM_PWSAKDLY_Type

struct	Pm
	PM hardware registers. More...

Macros
#define	PM_U2406

#define	REV_PM 0x100

#define	PM_CTRLA_OFFSET 0x00
	(PM_CTRLA offset) Control A

#define	PM_CTRLA_RESETVALUE _U_(0x00)
	(PM_CTRLA reset_value) Control A

#define	PM_CTRLA_IORET_Pos 2
	(PM_CTRLA) I/O Retention

#define	PM_CTRLA_IORET (_U_(0x1) << PM_CTRLA_IORET_Pos)

#define	PM_CTRLA_MASK _U_(0x04)
	(PM_CTRLA) MASK Register

#define	PM_SLEEPCFG_OFFSET 0x01
	(PM_SLEEPCFG offset) Sleep Configuration

#define	PM_SLEEPCFG_RESETVALUE _U_(0x02)
	(PM_SLEEPCFG reset_value) Sleep Configuration

#define	PM_SLEEPCFG_SLEEPMODE_Pos 0
	(PM_SLEEPCFG) Sleep Mode

#define	PM_SLEEPCFG_SLEEPMODE_Msk (_U_(0x7) << PM_SLEEPCFG_SLEEPMODE_Pos)

#define	PM_SLEEPCFG_SLEEPMODE(value) (PM_SLEEPCFG_SLEEPMODE_Msk & ((value) << PM_SLEEPCFG_SLEEPMODE_Pos))

#define	PM_SLEEPCFG_SLEEPMODE_IDLE0_Val _U_(0x0)
	(PM_SLEEPCFG) CPU clock is OFF

#define	PM_SLEEPCFG_SLEEPMODE_IDLE1_Val _U_(0x1)
	(PM_SLEEPCFG) AHB clock is OFF

#define	PM_SLEEPCFG_SLEEPMODE_IDLE2_Val _U_(0x2)
	(PM_SLEEPCFG) APB clock are OFF

#define	PM_SLEEPCFG_SLEEPMODE_STANDBY_Val _U_(0x4)
	(PM_SLEEPCFG) All Clocks are OFF

#define	PM_SLEEPCFG_SLEEPMODE_HIBERNATE_Val _U_(0x5)
	(PM_SLEEPCFG) Backup domain is ON as well as some PDRAMs

#define	PM_SLEEPCFG_SLEEPMODE_BACKUP_Val _U_(0x6)
	(PM_SLEEPCFG) Only Backup domain is powered ON

#define	PM_SLEEPCFG_SLEEPMODE_OFF_Val _U_(0x7)
	(PM_SLEEPCFG) All power domains are powered OFF

#define	PM_SLEEPCFG_SLEEPMODE_IDLE0 (PM_SLEEPCFG_SLEEPMODE_IDLE0_Val << PM_SLEEPCFG_SLEEPMODE_Pos)

#define	PM_SLEEPCFG_SLEEPMODE_IDLE1 (PM_SLEEPCFG_SLEEPMODE_IDLE1_Val << PM_SLEEPCFG_SLEEPMODE_Pos)

#define	PM_SLEEPCFG_SLEEPMODE_IDLE2 (PM_SLEEPCFG_SLEEPMODE_IDLE2_Val << PM_SLEEPCFG_SLEEPMODE_Pos)

#define	PM_SLEEPCFG_SLEEPMODE_STANDBY (PM_SLEEPCFG_SLEEPMODE_STANDBY_Val << PM_SLEEPCFG_SLEEPMODE_Pos)

#define	PM_SLEEPCFG_SLEEPMODE_HIBERNATE (PM_SLEEPCFG_SLEEPMODE_HIBERNATE_Val << PM_SLEEPCFG_SLEEPMODE_Pos)

#define	PM_SLEEPCFG_SLEEPMODE_BACKUP (PM_SLEEPCFG_SLEEPMODE_BACKUP_Val << PM_SLEEPCFG_SLEEPMODE_Pos)

#define	PM_SLEEPCFG_SLEEPMODE_OFF (PM_SLEEPCFG_SLEEPMODE_OFF_Val << PM_SLEEPCFG_SLEEPMODE_Pos)

#define	PM_SLEEPCFG_MASK _U_(0x07)
	(PM_SLEEPCFG) MASK Register

#define	PM_INTENCLR_OFFSET 0x04
	(PM_INTENCLR offset) Interrupt Enable Clear

#define	PM_INTENCLR_RESETVALUE _U_(0x00)
	(PM_INTENCLR reset_value) Interrupt Enable Clear

#define	PM_INTENCLR_SLEEPRDY_Pos 0
	(PM_INTENCLR) Sleep Mode Entry Ready Enable

#define	PM_INTENCLR_SLEEPRDY (_U_(0x1) << PM_INTENCLR_SLEEPRDY_Pos)

#define	PM_INTENCLR_MASK _U_(0x01)
	(PM_INTENCLR) MASK Register

#define	PM_INTENSET_OFFSET 0x05
	(PM_INTENSET offset) Interrupt Enable Set

#define	PM_INTENSET_RESETVALUE _U_(0x00)
	(PM_INTENSET reset_value) Interrupt Enable Set

#define	PM_INTENSET_SLEEPRDY_Pos 0
	(PM_INTENSET) Sleep Mode Entry Ready Enable

#define	PM_INTENSET_SLEEPRDY (_U_(0x1) << PM_INTENSET_SLEEPRDY_Pos)

#define	PM_INTENSET_MASK _U_(0x01)
	(PM_INTENSET) MASK Register

#define	PM_INTFLAG_OFFSET 0x06
	(PM_INTFLAG offset) Interrupt Flag Status and Clear

#define	PM_INTFLAG_RESETVALUE _U_(0x00)
	(PM_INTFLAG reset_value) Interrupt Flag Status and Clear

#define	PM_INTFLAG_SLEEPRDY_Pos 0
	(PM_INTFLAG) Sleep Mode Entry Ready

#define	PM_INTFLAG_SLEEPRDY (_U_(0x1) << PM_INTFLAG_SLEEPRDY_Pos)

#define	PM_INTFLAG_MASK _U_(0x01)
	(PM_INTFLAG) MASK Register

#define	PM_STDBYCFG_OFFSET 0x08
	(PM_STDBYCFG offset) Standby Configuration

#define	PM_STDBYCFG_RESETVALUE _U_(0x00)
	(PM_STDBYCFG reset_value) Standby Configuration

#define	PM_STDBYCFG_RAMCFG_Pos 0
	(PM_STDBYCFG) Ram Configuration

#define	PM_STDBYCFG_RAMCFG_Msk (_U_(0x3) << PM_STDBYCFG_RAMCFG_Pos)

#define	PM_STDBYCFG_RAMCFG(value) (PM_STDBYCFG_RAMCFG_Msk & ((value) << PM_STDBYCFG_RAMCFG_Pos))

#define	PM_STDBYCFG_RAMCFG_RET_Val _U_(0x0)
	(PM_STDBYCFG) All the RAMs are retained

#define	PM_STDBYCFG_RAMCFG_PARTIAL_Val _U_(0x1)
	(PM_STDBYCFG) Only the first 32K bytes are retained

#define	PM_STDBYCFG_RAMCFG_OFF_Val _U_(0x2)
	(PM_STDBYCFG) All the RAMs are OFF

#define	PM_STDBYCFG_RAMCFG_RET (PM_STDBYCFG_RAMCFG_RET_Val << PM_STDBYCFG_RAMCFG_Pos)

#define	PM_STDBYCFG_RAMCFG_PARTIAL (PM_STDBYCFG_RAMCFG_PARTIAL_Val << PM_STDBYCFG_RAMCFG_Pos)

#define	PM_STDBYCFG_RAMCFG_OFF (PM_STDBYCFG_RAMCFG_OFF_Val << PM_STDBYCFG_RAMCFG_Pos)

#define	PM_STDBYCFG_FASTWKUP_Pos 4
	(PM_STDBYCFG) Fast Wakeup

#define	PM_STDBYCFG_FASTWKUP_Msk (_U_(0x3) << PM_STDBYCFG_FASTWKUP_Pos)

#define	PM_STDBYCFG_FASTWKUP(value) (PM_STDBYCFG_FASTWKUP_Msk & ((value) << PM_STDBYCFG_FASTWKUP_Pos))

#define	PM_STDBYCFG_MASK _U_(0x33)
	(PM_STDBYCFG) MASK Register

#define	PM_HIBCFG_OFFSET 0x09
	(PM_HIBCFG offset) Hibernate Configuration

#define	PM_HIBCFG_RESETVALUE _U_(0x00)
	(PM_HIBCFG reset_value) Hibernate Configuration

#define	PM_HIBCFG_RAMCFG_Pos 0
	(PM_HIBCFG) Ram Configuration

#define	PM_HIBCFG_RAMCFG_Msk (_U_(0x3) << PM_HIBCFG_RAMCFG_Pos)

#define	PM_HIBCFG_RAMCFG(value) (PM_HIBCFG_RAMCFG_Msk & ((value) << PM_HIBCFG_RAMCFG_Pos))

#define	PM_HIBCFG_BRAMCFG_Pos 2
	(PM_HIBCFG) Backup Ram Configuration

#define	PM_HIBCFG_BRAMCFG_Msk (_U_(0x3) << PM_HIBCFG_BRAMCFG_Pos)

#define	PM_HIBCFG_BRAMCFG(value) (PM_HIBCFG_BRAMCFG_Msk & ((value) << PM_HIBCFG_BRAMCFG_Pos))

#define	PM_HIBCFG_MASK _U_(0x0F)
	(PM_HIBCFG) MASK Register

#define	PM_BKUPCFG_OFFSET 0x0A
	(PM_BKUPCFG offset) Backup Configuration

#define	PM_BKUPCFG_RESETVALUE _U_(0x00)
	(PM_BKUPCFG reset_value) Backup Configuration

#define	PM_BKUPCFG_BRAMCFG_Pos 0
	(PM_BKUPCFG) Ram Configuration

#define	PM_BKUPCFG_BRAMCFG_Msk (_U_(0x3) << PM_BKUPCFG_BRAMCFG_Pos)

#define	PM_BKUPCFG_BRAMCFG(value) (PM_BKUPCFG_BRAMCFG_Msk & ((value) << PM_BKUPCFG_BRAMCFG_Pos))

#define	PM_BKUPCFG_MASK _U_(0x03)
	(PM_BKUPCFG) MASK Register

#define	PM_PWSAKDLY_OFFSET 0x12
	(PM_PWSAKDLY offset) Power Switch Acknowledge Delay

#define	PM_PWSAKDLY_RESETVALUE _U_(0x00)
	(PM_PWSAKDLY reset_value) Power Switch Acknowledge Delay

#define	PM_PWSAKDLY_DLYVAL_Pos 0
	(PM_PWSAKDLY) Delay Value

#define	PM_PWSAKDLY_DLYVAL_Msk (_U_(0x7F) << PM_PWSAKDLY_DLYVAL_Pos)

#define	PM_PWSAKDLY_DLYVAL(value) (PM_PWSAKDLY_DLYVAL_Msk & ((value) << PM_PWSAKDLY_DLYVAL_Pos))

#define	PM_PWSAKDLY_IGNACK_Pos 7
	(PM_PWSAKDLY) Ignore Acknowledge

#define	PM_PWSAKDLY_IGNACK (_U_(0x1) << PM_PWSAKDLY_IGNACK_Pos)

#define	PM_PWSAKDLY_MASK _U_(0xFF)
	(PM_PWSAKDLY) MASK Register

Detailed Description

Component description for PM.

\asf_license_start

Definition in file pm.h.

Data Structures

Macros

Detailed Description