Instance description for GCLK. More...

Macros
#define	REG_GCLK_CTRLA ((RwReg8 )0x40001C00UL)
	(GCLK) Control

#define	REG_GCLK_SYNCBUSY ((RoReg )0x40001C04UL)
	(GCLK) Synchronization Busy

#define	REG_GCLK_GENCTRL0 ((RwReg )0x40001C20UL)
	(GCLK) Generic Clock Generator Control 0

#define	REG_GCLK_GENCTRL1 ((RwReg )0x40001C24UL)
	(GCLK) Generic Clock Generator Control 1

#define	REG_GCLK_GENCTRL2 ((RwReg )0x40001C28UL)
	(GCLK) Generic Clock Generator Control 2

#define	REG_GCLK_GENCTRL3 ((RwReg )0x40001C2CUL)
	(GCLK) Generic Clock Generator Control 3

#define	REG_GCLK_GENCTRL4 ((RwReg )0x40001C30UL)
	(GCLK) Generic Clock Generator Control 4

#define	REG_GCLK_GENCTRL5 ((RwReg )0x40001C34UL)
	(GCLK) Generic Clock Generator Control 5

#define	REG_GCLK_GENCTRL6 ((RwReg )0x40001C38UL)
	(GCLK) Generic Clock Generator Control 6

#define	REG_GCLK_GENCTRL7 ((RwReg )0x40001C3CUL)
	(GCLK) Generic Clock Generator Control 7

#define	REG_GCLK_GENCTRL8 ((RwReg )0x40001C40UL)
	(GCLK) Generic Clock Generator Control 8

#define	REG_GCLK_GENCTRL9 ((RwReg )0x40001C44UL)
	(GCLK) Generic Clock Generator Control 9

#define	REG_GCLK_GENCTRL10 ((RwReg )0x40001C48UL)
	(GCLK) Generic Clock Generator Control 10

#define	REG_GCLK_GENCTRL11 ((RwReg )0x40001C4CUL)
	(GCLK) Generic Clock Generator Control 11

#define	REG_GCLK_PCHCTRL0 ((RwReg )0x40001C80UL)
	(GCLK) Peripheral Clock Control 0

#define	REG_GCLK_PCHCTRL1 ((RwReg )0x40001C84UL)
	(GCLK) Peripheral Clock Control 1

#define	REG_GCLK_PCHCTRL2 ((RwReg )0x40001C88UL)
	(GCLK) Peripheral Clock Control 2

#define	REG_GCLK_PCHCTRL3 ((RwReg )0x40001C8CUL)
	(GCLK) Peripheral Clock Control 3

#define	REG_GCLK_PCHCTRL4 ((RwReg )0x40001C90UL)
	(GCLK) Peripheral Clock Control 4

#define	REG_GCLK_PCHCTRL5 ((RwReg )0x40001C94UL)
	(GCLK) Peripheral Clock Control 5

#define	REG_GCLK_PCHCTRL6 ((RwReg )0x40001C98UL)
	(GCLK) Peripheral Clock Control 6

#define	REG_GCLK_PCHCTRL7 ((RwReg )0x40001C9CUL)
	(GCLK) Peripheral Clock Control 7

#define	REG_GCLK_PCHCTRL8 ((RwReg )0x40001CA0UL)
	(GCLK) Peripheral Clock Control 8

#define	REG_GCLK_PCHCTRL9 ((RwReg )0x40001CA4UL)
	(GCLK) Peripheral Clock Control 9

#define	REG_GCLK_PCHCTRL10 ((RwReg )0x40001CA8UL)
	(GCLK) Peripheral Clock Control 10

#define	REG_GCLK_PCHCTRL11 ((RwReg )0x40001CACUL)
	(GCLK) Peripheral Clock Control 11

#define	REG_GCLK_PCHCTRL12 ((RwReg )0x40001CB0UL)
	(GCLK) Peripheral Clock Control 12

#define	REG_GCLK_PCHCTRL13 ((RwReg )0x40001CB4UL)
	(GCLK) Peripheral Clock Control 13

#define	REG_GCLK_PCHCTRL14 ((RwReg )0x40001CB8UL)
	(GCLK) Peripheral Clock Control 14

#define	REG_GCLK_PCHCTRL15 ((RwReg )0x40001CBCUL)
	(GCLK) Peripheral Clock Control 15

#define	REG_GCLK_PCHCTRL16 ((RwReg )0x40001CC0UL)
	(GCLK) Peripheral Clock Control 16

#define	REG_GCLK_PCHCTRL17 ((RwReg )0x40001CC4UL)
	(GCLK) Peripheral Clock Control 17

#define	REG_GCLK_PCHCTRL18 ((RwReg )0x40001CC8UL)
	(GCLK) Peripheral Clock Control 18

#define	REG_GCLK_PCHCTRL19 ((RwReg )0x40001CCCUL)
	(GCLK) Peripheral Clock Control 19

#define	REG_GCLK_PCHCTRL20 ((RwReg )0x40001CD0UL)
	(GCLK) Peripheral Clock Control 20

#define	REG_GCLK_PCHCTRL21 ((RwReg )0x40001CD4UL)
	(GCLK) Peripheral Clock Control 21

#define	REG_GCLK_PCHCTRL22 ((RwReg )0x40001CD8UL)
	(GCLK) Peripheral Clock Control 22

#define	REG_GCLK_PCHCTRL23 ((RwReg )0x40001CDCUL)
	(GCLK) Peripheral Clock Control 23

#define	REG_GCLK_PCHCTRL24 ((RwReg )0x40001CE0UL)
	(GCLK) Peripheral Clock Control 24

#define	REG_GCLK_PCHCTRL25 ((RwReg )0x40001CE4UL)
	(GCLK) Peripheral Clock Control 25

#define	REG_GCLK_PCHCTRL26 ((RwReg )0x40001CE8UL)
	(GCLK) Peripheral Clock Control 26

#define	REG_GCLK_PCHCTRL27 ((RwReg )0x40001CECUL)
	(GCLK) Peripheral Clock Control 27

#define	REG_GCLK_PCHCTRL28 ((RwReg )0x40001CF0UL)
	(GCLK) Peripheral Clock Control 28

#define	REG_GCLK_PCHCTRL29 ((RwReg )0x40001CF4UL)
	(GCLK) Peripheral Clock Control 29

#define	REG_GCLK_PCHCTRL30 ((RwReg )0x40001CF8UL)
	(GCLK) Peripheral Clock Control 30

#define	REG_GCLK_PCHCTRL31 ((RwReg )0x40001CFCUL)
	(GCLK) Peripheral Clock Control 31

#define	REG_GCLK_PCHCTRL32 ((RwReg )0x40001D00UL)
	(GCLK) Peripheral Clock Control 32

#define	REG_GCLK_PCHCTRL33 ((RwReg )0x40001D04UL)
	(GCLK) Peripheral Clock Control 33

#define	REG_GCLK_PCHCTRL34 ((RwReg )0x40001D08UL)
	(GCLK) Peripheral Clock Control 34

#define	REG_GCLK_PCHCTRL35 ((RwReg )0x40001D0CUL)
	(GCLK) Peripheral Clock Control 35

#define	REG_GCLK_PCHCTRL36 ((RwReg )0x40001D10UL)
	(GCLK) Peripheral Clock Control 36

#define	REG_GCLK_PCHCTRL37 ((RwReg )0x40001D14UL)
	(GCLK) Peripheral Clock Control 37

#define	REG_GCLK_PCHCTRL38 ((RwReg )0x40001D18UL)
	(GCLK) Peripheral Clock Control 38

#define	REG_GCLK_PCHCTRL39 ((RwReg )0x40001D1CUL)
	(GCLK) Peripheral Clock Control 39

#define	REG_GCLK_PCHCTRL40 ((RwReg )0x40001D20UL)
	(GCLK) Peripheral Clock Control 40

#define	REG_GCLK_PCHCTRL41 ((RwReg )0x40001D24UL)
	(GCLK) Peripheral Clock Control 41

#define	REG_GCLK_PCHCTRL42 ((RwReg )0x40001D28UL)
	(GCLK) Peripheral Clock Control 42

#define	REG_GCLK_PCHCTRL43 ((RwReg )0x40001D2CUL)
	(GCLK) Peripheral Clock Control 43

#define	REG_GCLK_PCHCTRL44 ((RwReg )0x40001D30UL)
	(GCLK) Peripheral Clock Control 44

#define	REG_GCLK_PCHCTRL45 ((RwReg )0x40001D34UL)
	(GCLK) Peripheral Clock Control 45

#define	REG_GCLK_PCHCTRL46 ((RwReg )0x40001D38UL)
	(GCLK) Peripheral Clock Control 46

#define	REG_GCLK_PCHCTRL47 ((RwReg )0x40001D3CUL)
	(GCLK) Peripheral Clock Control 47

#define	GCLK_GENCTRL0_RESETVALUE 106

#define	GCLK_GENDIV_BITS 16

#define	GCLK_GEN_BITS 4

#define	GCLK_GEN_NUM 12

#define	GCLK_GEN_NUM_MSB 11

#define	GCLK_GEN_SOURCE_NUM_MSB 8

#define	GCLK_IO_NUM 8

#define	GCLK_NUM 48

#define	GCLK_SOURCE_BITS 4

#define	GCLK_SOURCE_NUM 9

#define	GCLK_SOURCE_XOSC0 0

#define	GCLK_SOURCE_XOSC 0

#define	GCLK_SOURCE_XOSC1 1

#define	GCLK_SOURCE_GCLKIN 2

#define	GCLK_SOURCE_GCLKGEN1 3

#define	GCLK_SOURCE_OSCULP32K 4

#define	GCLK_SOURCE_XOSC32K 5

#define	GCLK_SOURCE_DFLL 6

#define	GCLK_SOURCE_DFLL48M 6

#define	GCLK_SOURCE_OSC16M 6

#define	GCLK_SOURCE_OSC48M 6

#define	GCLK_SOURCE_DPLL0 7

#define	GCLK_SOURCE_FDPLL 7

#define	GCLK_SOURCE_FDPLL0 7

#define	GCLK_SOURCE_DPLL1 8

#define	GCLK_SOURCE_FDPLL1 8

#define	GCLK_GEN_DIV_BITS { 8, 16, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8 }

Detailed Description

Instance description for GCLK.

\asf_license_start

Definition in file gclk.h.

Macros

Detailed Description