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updating docs again

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penguin 3 years ago
parent 32114c85ab
commit b9d5e38cce
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1
test/same54p20a_test/ESF/modules/core/.#clocks.h
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penguin@penguin-arch-home.19167:1609094009

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test/same54p20a_test/ESF/modules/core/clocks.h
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#define CONF_CORE_CLK_XOSC32KCTRL_STARTUP_4000009200ns (0x5)
#define CONF_CORE_CLK_XOSC32KCTRL_STARTUP_8000009200ns (0x6)
#define CONF_CORE_CLK_XOSCCTRL_STARTUP_31us 0x0
#define CONF_CORE_CLK_XOSCCTRL_STARTUP_61us 0x1
#define CONF_CORE_CLK_XOSCCTRL_STARTUP_122us 0x2
#define CONF_CORE_CLK_XOSCCTRL_STARTUP_244us 0x3
#define CONF_CORE_CLK_XOSCCTRL_STARTUP_488us 0x4
#define CONF_CORE_CLK_XOSCCTRL_STARTUP_977us 0x5
#define CONF_CORE_CLK_XOSCCTRL_STARTUP_1953us 0x6
#define CONF_CORE_CLK_XOSCCTRL_STARTUP_3906us 0x7
#define CONF_CORE_CLK_XOSCCTRL_STARTUP_7813us 0x8
#define CONF_CORE_CLK_XOSCCTRL_STARTUP_15625us 0x9
#define CONF_CORE_CLK_XOSCCTRL_STARTUP_31250us 0xA
#define CONF_CORE_CLK_XOSCCTRL_STARTUP_62500us 0xB
#define CONF_CORE_CLK_XOSCCTRL_STARTUP_125000us 0xC
#define CONF_CORE_CLK_XOSCCTRL_STARTUP_250000us 0xD
#define CONF_CORE_CLK_XOSCCTRL_STARTUP_500000us 0xE
#define CONF_CORE_CLK_XOSCCTRL_STARTUP_1000000us 0xF
// Oscillator Current Multiplier
#define CONF_CORE_CLK_XOSCCTRL_IMULT_24MHZ_TO_48MHZ (6)
#define CONF_CORE_CLK_XOSCCTRL_IMULT_16MHZ_TO_24MHZ (5)

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test/same54p20a_test/cfg/conf_core.h
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*/
/**
* Define the number of wait states for the master clock.
* Can be [0-15].
* @brief Define the number of wait states for the master clock.
* <br>Can be [0-15].
* <br>See <a href="https://ww1.microchip.com/downloads/en/DeviceDoc/SAM_D5xE5x_Family_Data_Sheet_DS60001507F.pdf#page=605">Datasheet Reference</a>
*/
#define CONF_CORE_MCLK_NVM_WAIT_STATE 0x5
/**
* Define the master clock divisor.
* @brief Define the master clock divisor.
* - 0x1 => Clock Divide by 1
* - 0x2 => Clock Divide by 2
* - 0x4 => Clock Divide by 4
@ -32,16 +33,18 @@
* - 0x20 => Clock Divide by 32
* - 0x40 => Clock Divide by 64
* - 0x80 => Clock Divide by 128
* <br>See <a href="https://ww1.microchip.com/downloads/en/DeviceDoc/SAM_D5xE5x_Family_Data_Sheet_DS60001507F.pdf#page=170">Datasheet Reference</a>
*/
#define CONF_CORE_MCLK_CPUDIV 0x1
/** @} */
/**
* Define whether the DMAC is enabled or not.
* - 0 => Disabled
* - 1 => Enabled
* <br>See <a href="https://ww1.microchip.com/downloads/en/DeviceDoc/SAM_D5xE5x_Family_Data_Sheet_DS60001507F.pdf#page=172">Datasheet Reference</a>
*/
/** @} */
#define CONF_CORE_DMA_ENABLE (0)
/**
@ -51,63 +54,326 @@
*/
#define CONF_CORE_CMCC_ENABLE (0)
/** Currently Unused */
#define CONF_CORE_PORT_EVCTRL_0_ENABLE (0)
/** Currently Unused */
#define CONF_CORE_PORT_EVCTRL_1_ENABLE (0)
/** Currently Unused */
#define CONF_CORE_PORT_EVCTRL_2_ENABLE (0)
/** @name Core-XOSC0-Configuration
* Configuration options for XOSC0.
* <br>See <a href="https://ww1.microchip.com/downloads/en/DeviceDoc/SAM_D5xE5x_Family_Data_Sheet_DS60001507F.pdf#page=693">Datasheet Reference</a>
* @{
*/
/**
* XOSC0 Enable
* @brief Enables or Disables the XOSC0 Clock
* - 0 => Disables XOSC0
* - 1 => Enables XOSC0
* <br>See <a href="https://ww1.microchip.com/downloads/en/DeviceDoc/SAM_D5xE5x_Family_Data_Sheet_DS60001507F.pdf#page=723">Datasheet Reference</a>
*/
#define CONF_CORE_CLK_XOSC0_ENABLE (1)
/**
* XOSC0 XTALEN
* @brief This bit controls the connections between the I/O pads and the external clock or crystal oscillator XOSC0:
* - 0 => External clock connected on XIN. XOUT can be used as general purpose I/O.
* - 1 => Crystal connected to XIN/XOUT.
* <br>See <a href="https://ww1.microchip.com/downloads/en/DeviceDoc/SAM_D5xE5x_Family_Data_Sheet_DS60001507F.pdf#page=723">Datasheet Reference</a>
*/
#define CONF_CORE_CLK_XOSC0_XTALEN (1)
/**
* XOSC0 Run in Standby
* @brief This bit controls how the XOSC0 behaves during standby sleep mode:
* - 0 => XOSC0 is not running in standby sleep mode if no peripheral requests the clock.
* - 1 => XOSC0 is running in standby sleep mode.
* If ONDEMAND is 1, XOSC0 will be running when a peripheral is requesting the clock.
* If ONDEMAND is 0, the clock source will always be running in standby sleep mode.
* <br>See <a href="https://ww1.microchip.com/downloads/en/DeviceDoc/SAM_D5xE5x_Family_Data_Sheet_DS60001507F.pdf#page=723">Datasheet Reference</a>
*/
#define CONF_CORE_CLK_XOSC0_RUNSTDBY (0)
/**
* XOSC0 On Demand Control
* @brief The On Demand operation mode allows the oscillator XOSC0 to be enabled or disabled, depending on peripheral clock requests.
* - 0 => Oscillator is always on.
* - 1 => The oscillator is running when a peripheral is requesting the oscillator to be used as a clock source.
* The oscillator is not running if no peripheral is requesting the clock source.
* <br>See <a href="https://ww1.microchip.com/downloads/en/DeviceDoc/SAM_D5xE5x_Family_Data_Sheet_DS60001507F.pdf#page=722">Datasheet Reference</a>
*/
#define CONF_CORE_CLK_XOSC0_ONDEMAND (0)
/**
* XOSC0 Low Buffer Gain Control Bit
* @brief The default value of LOWBUFGAIN=0 should be used to allow operating with a low amplitude oscillator.
* Don't use this setting except to solve stability issues.
* - 0 => The low buffer gain of XOSC0 is disabled.
* - 1 => The low buffer gain of XOSC0 is enabled.
* <br>See <a href="https://ww1.microchip.com/downloads/en/DeviceDoc/SAM_D5xE5x_Family_Data_Sheet_DS60001507F.pdf#page=722">Datasheet Reference</a>
*/
#define CONF_CORE_CLK_XOSC0_LOWBUFGAIN (0)
/**
* XOSC0 Automatic Loop Control
* @brief This bit controls the XOSC0 automatic loop control:
* - 0 => The automatic loop control is disabled.
* - 1 => The automatic loop control is enabled. Oscillator's amplitude will be automatically adjusted during Crystal Oscillator operation.
* <br>See <a href="https://ww1.microchip.com/downloads/en/DeviceDoc/SAM_D5xE5x_Family_Data_Sheet_DS60001507F.pdf#page=722">Datasheet Reference</a>
*/
#define CONF_CORE_CLK_XOSC0_ENALC (1)
/**
* XOSC0 Clock Failure Detector Control
* @brief This bit controls the XOSC0 clock failure detector:
* - 0 => Clock Failure Detector is disabled.
* - 1 => Clock Failure Detector is enabled.
* <br>See <a href="https://ww1.microchip.com/downloads/en/DeviceDoc/SAM_D5xE5x_Family_Data_Sheet_DS60001507F.pdf#page=722">Datasheet Reference</a>
*/
#define CONF_CORE_CLK_XOSC0_CFDEN (1)
/**
* XOSC0 Clock Switch Enable
* @brief This bit controls the XOSC0 output clock switch back to the external clock or crystal oscillator in case of clock recovery:
* - 0 => The clock switch back is disabled.
* - 1 => The clock switch back is enabled.
* This bit is reset once the XOSC0 output clock is switched back to the external clock or crystal oscillator.
* <br>See <a href="https://ww1.microchip.com/downloads/en/DeviceDoc/SAM_D5xE5x_Family_Data_Sheet_DS60001507F.pdf#page=722">Datasheet Reference</a>
*/
#define CONF_CORE_CLK_XOSC0_SWBEN (0)
#define CONF_CORE_CLK_XOSC0_STARTUP_TIME CONF_CORE_CLK_XOSCCTRL_STARTUP_31us
/**
* XOSC0 Startup Time
* @brief These bits select start-up time for XOSC0 according to the table below:
* - 0x00 => 31us
* - 0x01 => 61us
* - 0x02 => 122us
* - 0x03 => 244us
* - 0x04 => 488us
* - 0x05 => 977us
* - 0x06 => 1953us
* - 0x07 => 3906us
* - 0x08 => 7813us
* - 0x09 => 15625us
* - 0x0A => 31250us
* - 0x0B => 62500us
* - 0x0C => 125000us
* - 0x0D => 250000us
* - 0x0E => 500000us
* - 0x0F => 1000000us
* <br>See <a href="https://ww1.microchip.com/downloads/en/DeviceDoc/SAM_D5xE5x_Family_Data_Sheet_DS60001507F.pdf#page=721">Datasheet Reference</a>
*/
#define CONF_CORE_CLK_XOSC0_STARTUP_TIME (0x00)
/**
* XOSC0 Frequency
* @brief This is the frequency of the external clock you're using for XOSC0.
* This can be anything from 8MHz to 48MHz.
*/
#define CONF_CORE_CLK_XOSC0_FREQUENCY 12000000
/** @} */
/** @name Core-XOSC1-Configuration
* Configuration options for XOSC1.
* <br>See <a href="https://ww1.microchip.com/downloads/en/DeviceDoc/SAM_D5xE5x_Family_Data_Sheet_DS60001507F.pdf#page=693">Datasheet Reference</a>
* @{
*/
/**
* XOSC1 Enable
* @brief Enables or Disables the XOSC1 Clock
* - 0 => Disables XOSC1
* - 1 => Enables XOSC1
* <br>See <a href="https://ww1.microchip.com/downloads/en/DeviceDoc/SAM_D5xE5x_Family_Data_Sheet_DS60001507F.pdf#page=723">Datasheet Reference</a>
*/
#define CONF_CORE_CLK_XOSC1_ENABLE (0)
/**
* XOSC1 XTALEN
* @brief This bit controls the connections between the I/O pads and the external clock or crystal oscillator XOSC1:
* - 0 => External clock connected on XIN. XOUT can be used as general purpose I/O.
* - 1 => Crystal connected to XIN/XOUT.
* <br>See <a href="https://ww1.microchip.com/downloads/en/DeviceDoc/SAM_D5xE5x_Family_Data_Sheet_DS60001507F.pdf#page=723">Datasheet Reference</a>
*/
#define CONF_CORE_CLK_XOSC1_XTALEN (0)
/**
* XOSC1 Run in Standby
* @brief This bit controls how the XOSC1 behaves during standby sleep mode:
* - 0 => XOSC1 is not running in standby sleep mode if no peripheral requests the clock.
* - 1 => XOSC1 is running in standby sleep mode.
* If ONDEMAND is 1, XOSC1 will be running when a peripheral is requesting the clock.
* If ONDEMAND is 0, the clock source will always be running in standby sleep mode.
* <br>See <a href="https://ww1.microchip.com/downloads/en/DeviceDoc/SAM_D5xE5x_Family_Data_Sheet_DS60001507F.pdf#page=723">Datasheet Reference</a>
*/
#define CONF_CORE_CLK_XOSC1_RUNSTDBY (0)
/**
* XOSC1 On Demand Control
* @brief The On Demand operation mode allows the oscillator XOSC1 to be enabled or disabled, depending on peripheral clock requests.
* - 0 => Oscillator is always on.
* - 1 => The oscillator is running when a peripheral is requesting the oscillator to be used as a clock source.
* The oscillator is not running if no peripheral is requesting the clock source.
* <br>See <a href="https://ww1.microchip.com/downloads/en/DeviceDoc/SAM_D5xE5x_Family_Data_Sheet_DS60001507F.pdf#page=722">Datasheet Reference</a>
*/
#define CONF_CORE_CLK_XOSC1_ONDEMAND (0)
/**
* XOSC1 Low Buffer Gain Control Bit
* @brief The default value of LOWBUFGAIN=0 should be used to allow operating with a low amplitude oscillator.
* Don't use this setting except to solve stability issues.
* - 0 => The low buffer gain of XOSC1 is disabled.
* - 1 => The low buffer gain of XOSC1 is enabled.
* <br>See <a href="https://ww1.microchip.com/downloads/en/DeviceDoc/SAM_D5xE5x_Family_Data_Sheet_DS60001507F.pdf#page=722">Datasheet Reference</a>
*/
#define CONF_CORE_CLK_XOSC1_LOWBUFGAIN (0)
/**
* XOSC1 Automatic Loop Control
* @brief This bit controls the XOSC1 automatic loop control:
* - 0 => The automatic loop control is disabled.
* - 1 => The automatic loop control is enabled. Oscillator's amplitude will be automatically adjusted during Crystal Oscillator operation.
* <br>See <a href="https://ww1.microchip.com/downloads/en/DeviceDoc/SAM_D5xE5x_Family_Data_Sheet_DS60001507F.pdf#page=722">Datasheet Reference</a>
*/
#define CONF_CORE_CLK_XOSC1_ENALC (0)
/**
* XOSC1 Clock Failure Detector Control
* @brief This bit controls the XOSC1 clock failure detector:
* - 0 => Clock Failure Detector is disabled.
* - 1 => Clock Failure Detector is enabled.
* <br>See <a href="https://ww1.microchip.com/downloads/en/DeviceDoc/SAM_D5xE5x_Family_Data_Sheet_DS60001507F.pdf#page=722">Datasheet Reference</a>
*/
#define CONF_CORE_CLK_XOSC1_CFDEN (0)
/**
* XOSC1 Clock Switch Enable
* @brief This bit controls the XOSC1 output clock switch back to the external clock or crystal oscillator in case of clock recovery:
* - 0 => The clock switch back is disabled.
* - 1 => The clock switch back is enabled.
* This bit is reset once the XOSC1 output clock is switched back to the external clock or crystal oscillator.
* <br>See <a href="https://ww1.microchip.com/downloads/en/DeviceDoc/SAM_D5xE5x_Family_Data_Sheet_DS60001507F.pdf#page=722">Datasheet Reference</a>
*/
#define CONF_CORE_CLK_XOSC1_SWBEN (0)
#define CONF_CORE_CLK_XOSC1_STARTUP_TIME CONF_CORE_CLK_XOSCCTRL_STARTUP_31us
/**
* XOSC1 Startup Time
* @brief These bits select start-up time for XOSC1 according to the table below:
* - 0x00 => 31us
* - 0x01 => 61us
* - 0x02 => 122us
* - 0x03 => 244us
* - 0x04 => 488us
* - 0x05 => 977us
* - 0x06 => 1953us
* - 0x07 => 3906us
* - 0x08 => 7813us
* - 0x09 => 15625us
* - 0x0A => 31250us
* - 0x0B => 62500us
* - 0x0C => 125000us
* - 0x0D => 250000us
* - 0x0E => 500000us
* - 0x0F => 1000000us
* <br>See <a href="https://ww1.microchip.com/downloads/en/DeviceDoc/SAM_D5xE5x_Family_Data_Sheet_DS60001507F.pdf#page=721">Datasheet Reference</a>
*/
#define CONF_CORE_CLK_XOSC1_STARTUP_TIME (0x00)
/**
* XOSC1 Frequency
* @brief This is the frequency of the external clock you're using for XOSC1.
* This can be anything from 8MHz to 48MHz.
*/
#define CONF_CORE_CLK_XOSC1_FREQUENCY 12000000
/** @} */
/** @name Core-XOSC32K-Configuration
* Configuration options for the external 32khz oscillator.
* <br>See <a href="https://ww1.microchip.com/downloads/en/DeviceDoc/SAM_D5xE5x_Family_Data_Sheet_DS60001507F.pdf#page=735">Datasheet Reference</a>
* @{
*/
/**
* XOSC32K Enable
* @brief Enables or Disables XOSC32K.
* - 0 => The oscillator is disabled.
* - 1 => The oscillator is enabled.
* <br>See <a href="https://ww1.microchip.com/downloads/en/DeviceDoc/SAM_D5xE5x_Family_Data_Sheet_DS60001507F.pdf#page=749">Datasheet Reference</a>
*/
#define CONF_CORE_CLK_XOSC32K_ENABLE (1)
#define CONF_CORE_CLK_XOSC32K_CGM CONF_CORE_CLK_XOSC32KCTRL_CGM_STD_MODE
/**
* XOSC32K Control Gain Mode
* @brief These bits control the gain of the external crstal oscillator.
* - 0x00 => Low Power Mode
* - 0x01 => Standard Mode (Default)
* - 0x02 => High Speed Mode
* <br>See <a href="https://ww1.microchip.com/downloads/en/DeviceDoc/SAM_D5xE5x_Family_Data_Sheet_DS60001507F.pdf#page=748">Datasheet Reference</a>
*/
#define CONF_CORE_CLK_XOSC32K_CGM (0x01)
/**
* XOSC32K Startup Time
* @brief These bits select the startup time for the oscillator.
* - 0x00 => 62.592ms
* - 0x01 => 125.092ms
* - 0x02 => 500.092ms
* - 0x03 => 1000.0092ms
* - 0x04 => 2000.0092ms
* - 0x05 => 4000.0092ms
* - 0x06 => 8000.0092ms
* <br>See <a href="https://ww1.microchip.com/downloads/en/DeviceDoc/SAM_D5xE5x_Family_Data_Sheet_DS60001507F.pdf#page=748">Datasheet Reference</a>
*/
#define CONF_CORE_CLK_XOSC32K_STARTUP_TIME CONF_CORE_CLK_XOSC32KCTRL_STARTUP_62592us
/**
* XOSC32K On Demand Control
* @brief This bit controls how XOSC32K behaves when a peripheral clock request is detected.
* - 0 => On Demand Control disabled
* - 1 => On Demand Control enabled
* <br>See <a href="https://ww1.microchip.com/downloads/en/DeviceDoc/SAM_D5xE5x_Family_Data_Sheet_DS60001507F.pdf#page=748">Datasheet Reference</a>
*/
#define CONF_CORE_CLK_XOSC32K_ONDEMAND (1)
/**
* XOSC32K Run in Standby
* @brief This bit controls how XOSC32K behaves during standby sleep mode.
* - 0 => Run if requested by peripheral.
* - 1 => Run if requested by peripheral OR always run depending ONDEMAND value.
* <br>See <a href="https://ww1.microchip.com/downloads/en/DeviceDoc/SAM_D5xE5x_Family_Data_Sheet_DS60001507F.pdf#page=748">Datasheet Reference</a>
*/
#define CONF_CORE_CLK_XOSC32K_RUNSTDBY (0)
/**
* XOSC32K 1KHz Output Control
* - 0 => 1KHz output is disabled.
* - 1 => 1KHz output is enabled.
* <br>See <a href="https://ww1.microchip.com/downloads/en/DeviceDoc/SAM_D5xE5x_Family_Data_Sheet_DS60001507F.pdf#page=749">Datasheet Reference</a>
*/
#define CONF_CORE_CLK_XOSC32K_EN1K (0)
/**
* XOSC32K 32KHz Output Control
* - 0 => 32KHz output is disabled.
* - 1 => 32KHz output is enabled.
* <br>See <a href="https://ww1.microchip.com/downloads/en/DeviceDoc/SAM_D5xE5x_Family_Data_Sheet_DS60001507F.pdf#page=749">Datasheet Reference</a>
*/
#define CONF_CORE_CLK_XOSC32K_EN32K (1)
/**
* XOSC32K Crystal Oscillator Enable
* @brief This bit controls the connections between the I/O pads and the external clock or crystal oscillator.
* - 0 => External clock is connected on XIN32. XOUT32 can be used as general-purpose I/O.
* - 1 => Crystal connected to XIN32/XOUT32.
* <br>See <a href="https://ww1.microchip.com/downloads/en/DeviceDoc/SAM_D5xE5x_Family_Data_Sheet_DS60001507F.pdf#page=749">Datasheet Reference</a>
*/
#define CONF_CORE_CLK_XOSC32K_XTALEN (1)
/**
* XOSC32K Clock Failure Detector Prescaler
* @brief This bit selects the prescaler for the CLock Failure Detector:
* - 0 => The CFD safe clock frequency is the OSCULP32K frequency.
* - 1 => The CFD safe clock frequency is the OSCULP32K frequency divided by 2.
* <br>See <a href="https://ww1.microchip.com/downloads/en/DeviceDoc/SAM_D5xE5x_Family_Data_Sheet_DS60001507F.pdf#page=750">Datasheet Reference</a>
*/
#define CONF_CORE_CLK_XOSC32K_CFDPRESC (0)
/**
* XOSC32K Clock Failure Detector Control
* @brief This bit selects the Clock Failulre Detector state.
* - 0 => The CFD is disabled.
* - 1 => The CFD is enabled.
* <br>See <a href="https://ww1.microchip.com/downloads/en/DeviceDoc/SAM_D5xE5x_Family_Data_Sheet_DS60001507F.pdf#page=750">Datasheet Reference</a>
*/
#define CONF_CORE_CLK_XOSC32K_CFDEN (0)
/**
* XOSC32K Clock Switch Back
* @brief This bit controls the XOSC32K output switch back to the external clock or crystal oscillator in case of clock recovery.
* - 0 => The clock switch is disabled.
* - 1 => The clock switch is enabled. This bit is reset when XOSC32K output is switched back to the external clock or crystal oscillator.
* <br>See <a href="https://ww1.microchip.com/downloads/en/DeviceDoc/SAM_D5xE5x_Family_Data_Sheet_DS60001507F.pdf#page=750">Datasheet Reference</a>
*/
#define CONF_CORE_CLK_XOSC32K_SWBACK (0)
/**
* XOSC32K Write Lock
* @brief This bit locks the XOSC32K register for future writes, effectively freezing the XOSC32K configuration.
* - 0 => XOSC32K configuration is not locked.
* - 1 => XOSC32K configuration is locked.
* <br>See <a href="https://ww1.microchip.com/downloads/en/DeviceDoc/SAM_D5xE5x_Family_Data_Sheet_DS60001507F.pdf#page=748">Datasheet Reference</a>
*/
#define CONF_CORE_CLK_XOSC32K_WRTLOCK (0)
/** @} */
/** @name Core-DFLL48M-Configuration
@ -199,6 +465,7 @@
#define CONF_CORE_CLK_DPLL0_REFCLK CONF_CORE_CLK_DPLLCTRL_REFCLK_XOSC0
/**
* pg. 732 of the datasheet
* ~~~
* FILTER[3:0] | PLL Bandwidth (fn) | Damping Factor
* 0x0 | 92.7 kHz | 0.76
* 0x1 | 131 kHz | 1.08
@ -216,7 +483,8 @@
* 0xD | 92.7 kHz | 1.51
* 0xE | 32.8 kHz | 0.53
* 0xF | 46.4 kHz | 0.75
*
* ~~~
*
* When in doubt, leave this at its default.
*/
#define CONF_CORE_CLK_DPLL0_FILTER 0x0

107
test/same54p20a_test/doc/html/clocks_8c_source.html
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@ -111,17 +111,17 @@ $(function() {
<div class="line"><a name="l00040"></a><span class="lineno"> 40</span>&#160;<span class="keywordtype">void</span> clock_osc32k_init(<span class="keywordtype">void</span>)</div>
<div class="line"><a name="l00041"></a><span class="lineno"> 41</span>&#160;{</div>
<div class="line"><a name="l00042"></a><span class="lineno"> 42</span>&#160;<span class="preprocessor">#if CONF_CORE_CLK_XOSC32K_ENABLE == 1</span></div>
<div class="line"><a name="l00043"></a><span class="lineno"> 43</span>&#160; <a class="code" href="same54n19a_8h.html#af1a4b8f1d1a2265b93f22621f7903f88">OSC32KCTRL</a>-&gt;XOSC32K.bit.CGM = CONF_CORE_CLK_XOSC32K_CGM;</div>
<div class="line"><a name="l00044"></a><span class="lineno"> 44</span>&#160; <a class="code" href="same54n19a_8h.html#af1a4b8f1d1a2265b93f22621f7903f88">OSC32KCTRL</a>-&gt;XOSC32K.bit.WRTLOCK = CONF_CORE_CLK_XOSC32K_WRTLOCK;</div>
<div class="line"><a name="l00045"></a><span class="lineno"> 45</span>&#160; <a class="code" href="same54n19a_8h.html#af1a4b8f1d1a2265b93f22621f7903f88">OSC32KCTRL</a>-&gt;XOSC32K.bit.STARTUP = CONF_CORE_CLK_XOSC32K_STARTUP_TIME;</div>
<div class="line"><a name="l00046"></a><span class="lineno"> 46</span>&#160; <a class="code" href="same54n19a_8h.html#af1a4b8f1d1a2265b93f22621f7903f88">OSC32KCTRL</a>-&gt;XOSC32K.bit.RUNSTDBY = CONF_CORE_CLK_XOSC32K_RUNSTDBY;</div>
<div class="line"><a name="l00047"></a><span class="lineno"> 47</span>&#160; <a class="code" href="same54n19a_8h.html#af1a4b8f1d1a2265b93f22621f7903f88">OSC32KCTRL</a>-&gt;XOSC32K.bit.ONDEMAND = CONF_CORE_CLK_XOSC32K_ONDEMAND;</div>
<div class="line"><a name="l00048"></a><span class="lineno"> 48</span>&#160; <a class="code" href="same54n19a_8h.html#af1a4b8f1d1a2265b93f22621f7903f88">OSC32KCTRL</a>-&gt;XOSC32K.bit.EN1K = CONF_CORE_CLK_XOSC32K_EN1K;</div>
<div class="line"><a name="l00049"></a><span class="lineno"> 49</span>&#160; <a class="code" href="same54n19a_8h.html#af1a4b8f1d1a2265b93f22621f7903f88">OSC32KCTRL</a>-&gt;XOSC32K.bit.EN32K = CONF_CORE_CLK_XOSC32K_EN32K;</div>
<div class="line"><a name="l00050"></a><span class="lineno"> 50</span>&#160; <a class="code" href="same54n19a_8h.html#af1a4b8f1d1a2265b93f22621f7903f88">OSC32KCTRL</a>-&gt;XOSC32K.bit.XTALEN = CONF_CORE_CLK_XOSC32K_XTALEN;</div>
<div class="line"><a name="l00051"></a><span class="lineno"> 51</span>&#160; <a class="code" href="same54n19a_8h.html#af1a4b8f1d1a2265b93f22621f7903f88">OSC32KCTRL</a>-&gt;CFDCTRL.bit.CFDPRESC = CONF_CORE_CLK_XOSC32K_CFDPRESC;</div>
<div class="line"><a name="l00052"></a><span class="lineno"> 52</span>&#160; <a class="code" href="same54n19a_8h.html#af1a4b8f1d1a2265b93f22621f7903f88">OSC32KCTRL</a>-&gt;CFDCTRL.bit.SWBACK = CONF_CORE_CLK_XOSC32K_SWBACK;</div>
<div class="line"><a name="l00053"></a><span class="lineno"> 53</span>&#160; <a class="code" href="same54n19a_8h.html#af1a4b8f1d1a2265b93f22621f7903f88">OSC32KCTRL</a>-&gt;CFDCTRL.bit.CFDEN = CONF_CORE_CLK_XOSC32K_CFDEN;</div>
<div class="line"><a name="l00043"></a><span class="lineno"> 43</span>&#160; <a class="code" href="same54n19a_8h.html#af1a4b8f1d1a2265b93f22621f7903f88">OSC32KCTRL</a>-&gt;XOSC32K.bit.CGM = <a class="code" href="conf__core_8h.html#a031a77340c697036538d218724837de1">CONF_CORE_CLK_XOSC32K_CGM</a>;</div>
<div class="line"><a name="l00044"></a><span class="lineno"> 44</span>&#160; <a class="code" href="same54n19a_8h.html#af1a4b8f1d1a2265b93f22621f7903f88">OSC32KCTRL</a>-&gt;XOSC32K.bit.WRTLOCK = <a class="code" href="conf__core_8h.html#a42b0270d2f3c0f51c4b3d2b8ac397fda">CONF_CORE_CLK_XOSC32K_WRTLOCK</a>;</div>
<div class="line"><a name="l00045"></a><span class="lineno"> 45</span>&#160; <a class="code" href="same54n19a_8h.html#af1a4b8f1d1a2265b93f22621f7903f88">OSC32KCTRL</a>-&gt;XOSC32K.bit.STARTUP = <a class="code" href="conf__core_8h.html#a314b78ee48f1ecf6c40f4bad7ef63d9d">CONF_CORE_CLK_XOSC32K_STARTUP_TIME</a>;</div>
<div class="line"><a name="l00046"></a><span class="lineno"> 46</span>&#160; <a class="code" href="same54n19a_8h.html#af1a4b8f1d1a2265b93f22621f7903f88">OSC32KCTRL</a>-&gt;XOSC32K.bit.RUNSTDBY = <a class="code" href="conf__core_8h.html#adc7a2f161e9e8e54388b1f290066247e">CONF_CORE_CLK_XOSC32K_RUNSTDBY</a>;</div>
<div class="line"><a name="l00047"></a><span class="lineno"> 47</span>&#160; <a class="code" href="same54n19a_8h.html#af1a4b8f1d1a2265b93f22621f7903f88">OSC32KCTRL</a>-&gt;XOSC32K.bit.ONDEMAND = <a class="code" href="conf__core_8h.html#a8d70a30b50febec035af6b982daac395">CONF_CORE_CLK_XOSC32K_ONDEMAND</a>;</div>
<div class="line"><a name="l00048"></a><span class="lineno"> 48</span>&#160; <a class="code" href="same54n19a_8h.html#af1a4b8f1d1a2265b93f22621f7903f88">OSC32KCTRL</a>-&gt;XOSC32K.bit.EN1K = <a class="code" href="conf__core_8h.html#a033f3571fb50a6ed02278d65ea84b45e">CONF_CORE_CLK_XOSC32K_EN1K</a>;</div>
<div class="line"><a name="l00049"></a><span class="lineno"> 49</span>&#160; <a class="code" href="same54n19a_8h.html#af1a4b8f1d1a2265b93f22621f7903f88">OSC32KCTRL</a>-&gt;XOSC32K.bit.EN32K = <a class="code" href="conf__core_8h.html#ae9fbb8d05dc5808f510eae4e8a629826">CONF_CORE_CLK_XOSC32K_EN32K</a>;</div>
<div class="line"><a name="l00050"></a><span class="lineno"> 50</span>&#160; <a class="code" href="same54n19a_8h.html#af1a4b8f1d1a2265b93f22621f7903f88">OSC32KCTRL</a>-&gt;XOSC32K.bit.XTALEN = <a class="code" href="conf__core_8h.html#a6a65a6f4bf7e21dc2003b61a7045e24a">CONF_CORE_CLK_XOSC32K_XTALEN</a>;</div>
<div class="line"><a name="l00051"></a><span class="lineno"> 51</span>&#160; <a class="code" href="same54n19a_8h.html#af1a4b8f1d1a2265b93f22621f7903f88">OSC32KCTRL</a>-&gt;CFDCTRL.bit.CFDPRESC = <a class="code" href="conf__core_8h.html#a79567f94a0f3ad2d628bcf5e1cff62d1">CONF_CORE_CLK_XOSC32K_CFDPRESC</a>;</div>
<div class="line"><a name="l00052"></a><span class="lineno"> 52</span>&#160; <a class="code" href="same54n19a_8h.html#af1a4b8f1d1a2265b93f22621f7903f88">OSC32KCTRL</a>-&gt;CFDCTRL.bit.SWBACK = <a class="code" href="conf__core_8h.html#ac6e671eee4ca4aeb9fcbb87d52b457b5">CONF_CORE_CLK_XOSC32K_SWBACK</a>;</div>
<div class="line"><a name="l00053"></a><span class="lineno"> 53</span>&#160; <a class="code" href="same54n19a_8h.html#af1a4b8f1d1a2265b93f22621f7903f88">OSC32KCTRL</a>-&gt;CFDCTRL.bit.CFDEN = <a class="code" href="conf__core_8h.html#a668d68edf9a7ac05be5b9cda247225ad">CONF_CORE_CLK_XOSC32K_CFDEN</a>;</div>
<div class="line"><a name="l00054"></a><span class="lineno"> 54</span>&#160; </div>
<div class="line"><a name="l00055"></a><span class="lineno"> 55</span>&#160;<span class="preprocessor">#if CONF_CORE_CLK_XOSC32K_ENABLE == 1 &amp;&amp; CONF_CORE_CLK_XOSC32K_ONDEMAND == 0</span></div>
<div class="line"><a name="l00056"></a><span class="lineno"> 56</span>&#160; <span class="keywordflow">while</span>(<a class="code" href="same54n19a_8h.html#af1a4b8f1d1a2265b93f22621f7903f88">OSC32KCTRL</a>-&gt;STATUS.bit.XOSC32KRDY == 0);</div>
@ -133,34 +133,34 @@ $(function() {
<div class="line"><a name="l00062"></a><span class="lineno"> 62</span>&#160;{</div>
<div class="line"><a name="l00063"></a><span class="lineno"> 63</span>&#160;<span class="preprocessor">#if CONF_CORE_CLK_XOSC0_ENABLE == 1</span></div>
<div class="line"><a name="l00064"></a><span class="lineno"> 64</span>&#160; CRITICAL_SECTION_ENTER();</div>
<div class="line"><a name="l00065"></a><span class="lineno"> 65</span>&#160; <a class="code" href="same54n19a_8h.html#a49136ad5bf1adc9e9a0232349bcdce57">OSCCTRL</a>-&gt;XOSCCTRL[0].bit.XTALEN = CONF_CORE_CLK_XOSC0_XTALEN;</div>
<div class="line"><a name="l00066"></a><span class="lineno"> 66</span>&#160; <a class="code" href="same54n19a_8h.html#a49136ad5bf1adc9e9a0232349bcdce57">OSCCTRL</a>-&gt;XOSCCTRL[0].bit.RUNSTDBY = CONF_CORE_CLK_XOSC0_RUNSTDBY;</div>
<div class="line"><a name="l00067"></a><span class="lineno"> 67</span>&#160; <a class="code" href="same54n19a_8h.html#a49136ad5bf1adc9e9a0232349bcdce57">OSCCTRL</a>-&gt;XOSCCTRL[0].bit.ONDEMAND = CONF_CORE_CLK_XOSC0_ONDEMAND;</div>
<div class="line"><a name="l00068"></a><span class="lineno"> 68</span>&#160; <a class="code" href="same54n19a_8h.html#a49136ad5bf1adc9e9a0232349bcdce57">OSCCTRL</a>-&gt;XOSCCTRL[0].bit.LOWBUFGAIN = CONF_CORE_CLK_XOSC0_LOWBUFGAIN;</div>
<div class="line"><a name="l00065"></a><span class="lineno"> 65</span>&#160; <a class="code" href="same54n19a_8h.html#a49136ad5bf1adc9e9a0232349bcdce57">OSCCTRL</a>-&gt;XOSCCTRL[0].bit.XTALEN = <a class="code" href="conf__core_8h.html#ac2ca0e9037347eb69d53a0011f989910">CONF_CORE_CLK_XOSC0_XTALEN</a>;</div>
<div class="line"><a name="l00066"></a><span class="lineno"> 66</span>&#160; <a class="code" href="same54n19a_8h.html#a49136ad5bf1adc9e9a0232349bcdce57">OSCCTRL</a>-&gt;XOSCCTRL[0].bit.RUNSTDBY = <a class="code" href="conf__core_8h.html#afac0686157854cc021424410ded071f1">CONF_CORE_CLK_XOSC0_RUNSTDBY</a>;</div>
<div class="line"><a name="l00067"></a><span class="lineno"> 67</span>&#160; <a class="code" href="same54n19a_8h.html#a49136ad5bf1adc9e9a0232349bcdce57">OSCCTRL</a>-&gt;XOSCCTRL[0].bit.ONDEMAND = <a class="code" href="conf__core_8h.html#a5ffaa1551b7ffb8a342b2cc5fbc5950c">CONF_CORE_CLK_XOSC0_ONDEMAND</a>;</div>
<div class="line"><a name="l00068"></a><span class="lineno"> 68</span>&#160; <a class="code" href="same54n19a_8h.html#a49136ad5bf1adc9e9a0232349bcdce57">OSCCTRL</a>-&gt;XOSCCTRL[0].bit.LOWBUFGAIN = <a class="code" href="conf__core_8h.html#aeea7b0d3663bb6d5ccc3218017f9a05b">CONF_CORE_CLK_XOSC0_LOWBUFGAIN</a>;</div>
<div class="line"><a name="l00069"></a><span class="lineno"> 69</span>&#160; <a class="code" href="same54n19a_8h.html#a49136ad5bf1adc9e9a0232349bcdce57">OSCCTRL</a>-&gt;XOSCCTRL[0].bit.IPTAT = CONF_CORE_CLK_XOSC0_IPTAT;</div>
<div class="line"><a name="l00070"></a><span class="lineno"> 70</span>&#160; <a class="code" href="same54n19a_8h.html#a49136ad5bf1adc9e9a0232349bcdce57">OSCCTRL</a>-&gt;XOSCCTRL[0].bit.IMULT = CONF_CORE_CLK_XOSC0_IMULT;</div>
<div class="line"><a name="l00071"></a><span class="lineno"> 71</span>&#160; <a class="code" href="same54n19a_8h.html#a49136ad5bf1adc9e9a0232349bcdce57">OSCCTRL</a>-&gt;XOSCCTRL[0].bit.ENALC = CONF_CORE_CLK_XOSC0_ENALC;</div>
<div class="line"><a name="l00072"></a><span class="lineno"> 72</span>&#160; <a class="code" href="same54n19a_8h.html#a49136ad5bf1adc9e9a0232349bcdce57">OSCCTRL</a>-&gt;XOSCCTRL[0].bit.CFDEN = CONF_CORE_CLK_XOSC0_CFDEN;</div>
<div class="line"><a name="l00071"></a><span class="lineno"> 71</span>&#160; <a class="code" href="same54n19a_8h.html#a49136ad5bf1adc9e9a0232349bcdce57">OSCCTRL</a>-&gt;XOSCCTRL[0].bit.ENALC = <a class="code" href="conf__core_8h.html#a2683d3721ab44a85e60cfff0d0cbf96e">CONF_CORE_CLK_XOSC0_ENALC</a>;</div>
<div class="line"><a name="l00072"></a><span class="lineno"> 72</span>&#160; <a class="code" href="same54n19a_8h.html#a49136ad5bf1adc9e9a0232349bcdce57">OSCCTRL</a>-&gt;XOSCCTRL[0].bit.CFDEN = <a class="code" href="conf__core_8h.html#a17cd20bb954bc137251cf7fb63889151">CONF_CORE_CLK_XOSC0_CFDEN</a>;</div>
<div class="line"><a name="l00073"></a><span class="lineno"> 73</span>&#160; <a class="code" href="same54n19a_8h.html#a49136ad5bf1adc9e9a0232349bcdce57">OSCCTRL</a>-&gt;XOSCCTRL[0].bit.CFDPRESC = CONF_CORE_CLK_XOSC0_CFDPRESC;</div>
<div class="line"><a name="l00074"></a><span class="lineno"> 74</span>&#160; <a class="code" href="same54n19a_8h.html#a49136ad5bf1adc9e9a0232349bcdce57">OSCCTRL</a>-&gt;XOSCCTRL[0].bit.SWBEN = CONF_CORE_CLK_XOSC0_SWBEN;</div>
<div class="line"><a name="l00075"></a><span class="lineno"> 75</span>&#160; <a class="code" href="same54n19a_8h.html#a49136ad5bf1adc9e9a0232349bcdce57">OSCCTRL</a>-&gt;XOSCCTRL[0].bit.STARTUP = CONF_CORE_CLK_XOSC0_STARTUP_TIME;</div>
<div class="line"><a name="l00076"></a><span class="lineno"> 76</span>&#160; <a class="code" href="same54n19a_8h.html#a49136ad5bf1adc9e9a0232349bcdce57">OSCCTRL</a>-&gt;XOSCCTRL[0].bit.ENABLE = CONF_CORE_CLK_XOSC0_ENABLE;</div>
<div class="line"><a name="l00074"></a><span class="lineno"> 74</span>&#160; <a class="code" href="same54n19a_8h.html#a49136ad5bf1adc9e9a0232349bcdce57">OSCCTRL</a>-&gt;XOSCCTRL[0].bit.SWBEN = <a class="code" href="conf__core_8h.html#abe235b3b13f253acb855d15c8f33c95a">CONF_CORE_CLK_XOSC0_SWBEN</a>;</div>
<div class="line"><a name="l00075"></a><span class="lineno"> 75</span>&#160; <a class="code" href="same54n19a_8h.html#a49136ad5bf1adc9e9a0232349bcdce57">OSCCTRL</a>-&gt;XOSCCTRL[0].bit.STARTUP = <a class="code" href="conf__core_8h.html#affc8201cf2340d2236ba9ca44a1e657c">CONF_CORE_CLK_XOSC0_STARTUP_TIME</a>;</div>
<div class="line"><a name="l00076"></a><span class="lineno"> 76</span>&#160; <a class="code" href="same54n19a_8h.html#a49136ad5bf1adc9e9a0232349bcdce57">OSCCTRL</a>-&gt;XOSCCTRL[0].bit.ENABLE = <a class="code" href="conf__core_8h.html#a61559adc856ce1dcfa046e749af63bc3">CONF_CORE_CLK_XOSC0_ENABLE</a>;</div>
<div class="line"><a name="l00077"></a><span class="lineno"> 77</span>&#160; CRITICAL_SECTION_LEAVE();</div>
<div class="line"><a name="l00078"></a><span class="lineno"> 78</span>&#160; <span class="keywordflow">while</span>(0 == <a class="code" href="same54n19a_8h.html#a49136ad5bf1adc9e9a0232349bcdce57">OSCCTRL</a>-&gt;STATUS.bit.XOSCRDY0);</div>
<div class="line"><a name="l00079"></a><span class="lineno"> 79</span>&#160;<span class="preprocessor">#endif</span></div>
<div class="line"><a name="l00080"></a><span class="lineno"> 80</span>&#160; </div>
<div class="line"><a name="l00081"></a><span class="lineno"> 81</span>&#160;<span class="preprocessor">#if CONF_CORE_CLK_XOSC1_ENABLE == 1</span></div>
<div class="line"><a name="l00082"></a><span class="lineno"> 82</span>&#160; CRITICAL_SECTION_ENTER();</div>
<div class="line"><a name="l00083"></a><span class="lineno"> 83</span>&#160; <a class="code" href="same54n19a_8h.html#a49136ad5bf1adc9e9a0232349bcdce57">OSCCTRL</a>-&gt;XOSCCTRL[1].bit.XTALEN = CONF_CORE_CLK_XOSC1_XTALEN;</div>
<div class="line"><a name="l00084"></a><span class="lineno"> 84</span>&#160; <a class="code" href="same54n19a_8h.html#a49136ad5bf1adc9e9a0232349bcdce57">OSCCTRL</a>-&gt;XOSCCTRL[1].bit.RUNSTDBY = CONF_CORE_CLK_XOSC1_RUNSTDBY;</div>
<div class="line"><a name="l00085"></a><span class="lineno"> 85</span>&#160; <a class="code" href="same54n19a_8h.html#a49136ad5bf1adc9e9a0232349bcdce57">OSCCTRL</a>-&gt;XOSCCTRL[1].bit.LOWBUFGAIN = CONF_CORE_CLK_XOSC1_LOWBUFGAIN;</div>
<div class="line"><a name="l00083"></a><span class="lineno"> 83</span>&#160; <a class="code" href="same54n19a_8h.html#a49136ad5bf1adc9e9a0232349bcdce57">OSCCTRL</a>-&gt;XOSCCTRL[1].bit.XTALEN = <a class="code" href="conf__core_8h.html#ae3f8741e2be4b37a46dfb49af2c2a09d">CONF_CORE_CLK_XOSC1_XTALEN</a>;</div>
<div class="line"><a name="l00084"></a><span class="lineno"> 84</span>&#160; <a class="code" href="same54n19a_8h.html#a49136ad5bf1adc9e9a0232349bcdce57">OSCCTRL</a>-&gt;XOSCCTRL[1].bit.RUNSTDBY = <a class="code" href="conf__core_8h.html#a8bec34fdc01ac38ec0c2d13112f28aa0">CONF_CORE_CLK_XOSC1_RUNSTDBY</a>;</div>
<div class="line"><a name="l00085"></a><span class="lineno"> 85</span>&#160; <a class="code" href="same54n19a_8h.html#a49136ad5bf1adc9e9a0232349bcdce57">OSCCTRL</a>-&gt;XOSCCTRL[1].bit.LOWBUFGAIN = <a class="code" href="conf__core_8h.html#a985ebd23986d9411d3602040e33bb405">CONF_CORE_CLK_XOSC1_LOWBUFGAIN</a>;</div>
<div class="line"><a name="l00086"></a><span class="lineno"> 86</span>&#160; <a class="code" href="same54n19a_8h.html#a49136ad5bf1adc9e9a0232349bcdce57">OSCCTRL</a>-&gt;XOSCCTRL[1].bit.IPTAT = CONF_CORE_CLK_XOSC1_IPTAT;</div>
<div class="line"><a name="l00087"></a><span class="lineno"> 87</span>&#160; <a class="code" href="same54n19a_8h.html#a49136ad5bf1adc9e9a0232349bcdce57">OSCCTRL</a>-&gt;XOSCCTRL[1].bit.IMULT = CONF_CORE_CLK_XOSC1_IMULT;</div>
<div class="line"><a name="l00088"></a><span class="lineno"> 88</span>&#160; <a class="code" href="same54n19a_8h.html#a49136ad5bf1adc9e9a0232349bcdce57">OSCCTRL</a>-&gt;XOSCCTRL[1].bit.CFDEN = CONF_CORE_CLK_XOSC1_CFDEN;</div>
<div class="line"><a name="l00088"></a><span class="lineno"> 88</span>&#160; <a class="code" href="same54n19a_8h.html#a49136ad5bf1adc9e9a0232349bcdce57">OSCCTRL</a>-&gt;XOSCCTRL[1].bit.CFDEN = <a class="code" href="conf__core_8h.html#a924214b0f469bde71ff28fe5544466db">CONF_CORE_CLK_XOSC1_CFDEN</a>;</div>
<div class="line"><a name="l00089"></a><span class="lineno"> 89</span>&#160; <a class="code" href="same54n19a_8h.html#a49136ad5bf1adc9e9a0232349bcdce57">OSCCTRL</a>-&gt;XOSCCTRL[1].bit.CFDPRESC = CONF_CORE_CLK_XOSC1_CFDPRESC;</div>
<div class="line"><a name="l00090"></a><span class="lineno"> 90</span>&#160; <a class="code" href="same54n19a_8h.html#a49136ad5bf1adc9e9a0232349bcdce57">OSCCTRL</a>-&gt;XOSCCTRL[1].bit.SWBEN = CONF_CORE_CLK_XOSC1_SWBEN;</div>
<div class="line"><a name="l00091"></a><span class="lineno"> 91</span>&#160; <a class="code" href="same54n19a_8h.html#a49136ad5bf1adc9e9a0232349bcdce57">OSCCTRL</a>-&gt;XOSCCTRL[1].bit.STARTUP = CONF_CORE_CLK_XOSC1_STARTUP_TIME;</div>
<div class="line"><a name="l00092"></a><span class="lineno"> 92</span>&#160; <a class="code" href="same54n19a_8h.html#a49136ad5bf1adc9e9a0232349bcdce57">OSCCTRL</a>-&gt;XOSCCTRL[1].bit.ENABLE = CONF_CORE_CLK_XOSC1_ENABLE;</div>
<div class="line"><a name="l00090"></a><span class="lineno"> 90</span>&#160; <a class="code" href="same54n19a_8h.html#a49136ad5bf1adc9e9a0232349bcdce57">OSCCTRL</a>-&gt;XOSCCTRL[1].bit.SWBEN = <a class="code" href="conf__core_8h.html#a590b1e68a3f666bdea576a32f4e74ba0">CONF_CORE_CLK_XOSC1_SWBEN</a>;</div>
<div class="line"><a name="l00091"></a><span class="lineno"> 91</span>&#160; <a class="code" href="same54n19a_8h.html#a49136ad5bf1adc9e9a0232349bcdce57">OSCCTRL</a>-&gt;XOSCCTRL[1].bit.STARTUP = <a class="code" href="conf__core_8h.html#ae8d2fdac3b52964174863149986db625">CONF_CORE_CLK_XOSC1_STARTUP_TIME</a>;</div>
<div class="line"><a name="l00092"></a><span class="lineno"> 92</span>&#160; <a class="code" href="same54n19a_8h.html#a49136ad5bf1adc9e9a0232349bcdce57">OSCCTRL</a>-&gt;XOSCCTRL[1].bit.ENABLE = <a class="code" href="conf__core_8h.html#aa54465cc56631333a22ae84ab66d5f3a">CONF_CORE_CLK_XOSC1_ENABLE</a>;</div>
<div class="line"><a name="l00093"></a><span class="lineno"> 93</span>&#160; CRITICAL_SECTION_LEAVE();</div>
<div class="line"><a name="l00094"></a><span class="lineno"> 94</span>&#160; <span class="keywordflow">while</span>(0 == <a class="code" href="same54n19a_8h.html#a49136ad5bf1adc9e9a0232349bcdce57">OSCCTRL</a>-&gt;STATUS.bit.XOSCRDY1);</div>
<div class="line"><a name="l00095"></a><span class="lineno"> 95</span>&#160;<span class="preprocessor">#endif</span></div>
@ -168,11 +168,11 @@ $(function() {
<div class="line"><a name="l00097"></a><span class="lineno"> 97</span>&#160;<span class="preprocessor">#if CONF_CORE_CLK_XOSC0_ENABLE == 1</span></div>
<div class="line"><a name="l00098"></a><span class="lineno"> 98</span>&#160; CRITICAL_SECTION_ENTER();</div>
<div class="line"><a name="l00099"></a><span class="lineno"> 99</span>&#160;<span class="preprocessor">#if CONF_CORE_CLK_XOSC0_ENALC == 1</span></div>
<div class="line"><a name="l00100"></a><span class="lineno"> 100</span>&#160; <a class="code" href="same54n19a_8h.html#a49136ad5bf1adc9e9a0232349bcdce57">OSCCTRL</a>-&gt;XOSCCTRL[0].bit.ENALC = CONF_CORE_CLK_XOSC0_ENALC;</div>
<div class="line"><a name="l00100"></a><span class="lineno"> 100</span>&#160; <a class="code" href="same54n19a_8h.html#a49136ad5bf1adc9e9a0232349bcdce57">OSCCTRL</a>-&gt;XOSCCTRL[0].bit.ENALC = <a class="code" href="conf__core_8h.html#a2683d3721ab44a85e60cfff0d0cbf96e">CONF_CORE_CLK_XOSC0_ENALC</a>;</div>
<div class="line"><a name="l00101"></a><span class="lineno"> 101</span>&#160;<span class="preprocessor">#endif</span></div>
<div class="line"><a name="l00102"></a><span class="lineno"> 102</span>&#160; </div>
<div class="line"><a name="l00103"></a><span class="lineno"> 103</span>&#160;<span class="preprocessor">#if CONF_CORE_CLK_XOSC0_ONDEMAND == 1</span></div>
<div class="line"><a name="l00104"></a><span class="lineno"> 104</span>&#160; <a class="code" href="same54n19a_8h.html#a49136ad5bf1adc9e9a0232349bcdce57">OSCCTRL</a>-&gt;XOSCCTRL[0].bit.ONDEMAND = CONF_CORE_CLK_XOSC0_ONDEMAND;</div>
<div class="line"><a name="l00104"></a><span class="lineno"> 104</span>&#160; <a class="code" href="same54n19a_8h.html#a49136ad5bf1adc9e9a0232349bcdce57">OSCCTRL</a>-&gt;XOSCCTRL[0].bit.ONDEMAND = <a class="code" href="conf__core_8h.html#a5ffaa1551b7ffb8a342b2cc5fbc5950c">CONF_CORE_CLK_XOSC0_ONDEMAND</a>;</div>
<div class="line"><a name="l00105"></a><span class="lineno"> 105</span>&#160;<span class="preprocessor">#endif</span></div>
<div class="line"><a name="l00106"></a><span class="lineno"> 106</span>&#160; CRITICAL_SECTION_LEAVE();</div>
<div class="line"><a name="l00107"></a><span class="lineno"> 107</span>&#160;<span class="preprocessor">#endif</span></div>
@ -180,11 +180,11 @@ $(function() {
<div class="line"><a name="l00109"></a><span class="lineno"> 109</span>&#160;<span class="preprocessor">#if CONF_CORE_CLK_XOSC1_ENABLE == 1</span></div>
<div class="line"><a name="l00110"></a><span class="lineno"> 110</span>&#160; CRITICAL_SECTION_ENTER();</div>
<div class="line"><a name="l00111"></a><span class="lineno"> 111</span>&#160;<span class="preprocessor">#if CONF_CORE_CLK_XOSC1_ENALC == 1</span></div>
<div class="line"><a name="l00112"></a><span class="lineno"> 112</span>&#160; <a class="code" href="same54n19a_8h.html#a49136ad5bf1adc9e9a0232349bcdce57">OSCCTRL</a>-&gt;XOSCCTRL[1].bit.ENALC = CONF_CORE_CLK_XOSC1_ENALC;</div>
<div class="line"><a name="l00112"></a><span class="lineno"> 112</span>&#160; <a class="code" href="same54n19a_8h.html#a49136ad5bf1adc9e9a0232349bcdce57">OSCCTRL</a>-&gt;XOSCCTRL[1].bit.ENALC = <a class="code" href="conf__core_8h.html#a3a42de5c6251540e7b8c000974acfc62">CONF_CORE_CLK_XOSC1_ENALC</a>;</div>
<div class="line"><a name="l00113"></a><span class="lineno"> 113</span>&#160;<span class="preprocessor">#endif</span></div>
<div class="line"><a name="l00114"></a><span class="lineno"> 114</span>&#160; </div>
<div class="line"><a name="l00115"></a><span class="lineno"> 115</span>&#160;<span class="preprocessor">#if CONF_CORE_CLK_XOSC1_ONDEMAND == 1</span></div>
<div class="line"><a name="l00116"></a><span class="lineno"> 116</span>&#160; <a class="code" href="same54n19a_8h.html#a49136ad5bf1adc9e9a0232349bcdce57">OSCCTRL</a>-&gt;XOSCCTRL[1].bit.ONDEMAND = CONF_CORE_CLK_XOSC1_ONDEMAND;</div>
<div class="line"><a name="l00116"></a><span class="lineno"> 116</span>&#160; <a class="code" href="same54n19a_8h.html#a49136ad5bf1adc9e9a0232349bcdce57">OSCCTRL</a>-&gt;XOSCCTRL[1].bit.ONDEMAND = <a class="code" href="conf__core_8h.html#aaf561ace0fee1e373536a251ce8a9726">CONF_CORE_CLK_XOSC1_ONDEMAND</a>;</div>
<div class="line"><a name="l00117"></a><span class="lineno"> 117</span>&#160;<span class="preprocessor">#endif</span></div>
<div class="line"><a name="l00118"></a><span class="lineno"> 118</span>&#160; CRITICAL_SECTION_LEAVE();</div>
<div class="line"><a name="l00119"></a><span class="lineno"> 119</span>&#160;<span class="preprocessor">#endif</span></div>
@ -526,19 +526,48 @@ $(function() {
<div class="line"><a name="l00455"></a><span class="lineno"> 455</span>&#160;<span class="preprocessor">#endif</span></div>
<div class="line"><a name="l00456"></a><span class="lineno"> 456</span>&#160;}</div>
</div><!-- fragment --></div><!-- contents -->
<div class="ttc" id="aconf__core_8h_html_a1f088d6654bb907ff388ced455b2dbb2"><div class="ttname"><a href="conf__core_8h.html#a1f088d6654bb907ff388ced455b2dbb2">CONF_CORE_CLK_DFLL_WAITLOCK</a></div><div class="ttdeci">#define CONF_CORE_CLK_DFLL_WAITLOCK</div><div class="ttdoc">This bit controls the DFLL output clock, depending on the lock status:</div><div class="ttdef"><b>Definition:</b> <a href="conf__core_8h_source.html#l00148">conf_core.h:148</a></div></div>
<div class="ttc" id="aconf__core_8h_html_a9de3ab7eb7e3c001d6aa7040f6311f10"><div class="ttname"><a href="conf__core_8h.html#a9de3ab7eb7e3c001d6aa7040f6311f10">CONF_CORE_CLK_DPLL1_FILTER</a></div><div class="ttdeci">#define CONF_CORE_CLK_DPLL1_FILTER</div><div class="ttdef"><b>Definition:</b> <a href="conf__core_8h_source.html#l00267">conf_core.h:267</a></div></div>
<div class="ttc" id="aconf__core_8h_html_a5cd9abca6f486eaebb6ddd236960b01a"><div class="ttname"><a href="conf__core_8h.html#a5cd9abca6f486eaebb6ddd236960b01a">CONF_CORE_CLK_DPLL0_FILTER</a></div><div class="ttdeci">#define CONF_CORE_CLK_DPLL0_FILTER</div><div class="ttdef"><b>Definition:</b> <a href="conf__core_8h_source.html#l00222">conf_core.h:222</a></div></div>
<div class="ttc" id="aconf__core_8h_html_aa9643e96439d0d47e0684a4b11c1f529"><div class="ttname"><a href="conf__core_8h.html#aa9643e96439d0d47e0684a4b11c1f529">CONF_CORE_MCLK_CPUDIV</a></div><div class="ttdeci">#define CONF_CORE_MCLK_CPUDIV</div><div class="ttdef"><b>Definition:</b> <a href="conf__core_8h_source.html#l00036">conf_core.h:36</a></div></div>
<div class="ttc" id="aconf__core_8h_html_a1f088d6654bb907ff388ced455b2dbb2"><div class="ttname"><a href="conf__core_8h.html#a1f088d6654bb907ff388ced455b2dbb2">CONF_CORE_CLK_DFLL_WAITLOCK</a></div><div class="ttdeci">#define CONF_CORE_CLK_DFLL_WAITLOCK</div><div class="ttdoc">This bit controls the DFLL output clock, depending on the lock status:</div><div class="ttdef"><b>Definition:</b> <a href="conf__core_8h_source.html#l00414">conf_core.h:414</a></div></div>
<div class="ttc" id="aconf__core_8h_html_aaf561ace0fee1e373536a251ce8a9726"><div class="ttname"><a href="conf__core_8h.html#aaf561ace0fee1e373536a251ce8a9726">CONF_CORE_CLK_XOSC1_ONDEMAND</a></div><div class="ttdeci">#define CONF_CORE_CLK_XOSC1_ONDEMAND</div><div class="ttdoc">The On Demand operation mode allows the oscillator XOSC1 to be enabled or disabled,...</div><div class="ttdef"><b>Definition:</b> <a href="conf__core_8h_source.html#l00207">conf_core.h:207</a></div></div>
<div class="ttc" id="aconf__core_8h_html_a17cd20bb954bc137251cf7fb63889151"><div class="ttname"><a href="conf__core_8h.html#a17cd20bb954bc137251cf7fb63889151">CONF_CORE_CLK_XOSC0_CFDEN</a></div><div class="ttdeci">#define CONF_CORE_CLK_XOSC0_CFDEN</div><div class="ttdoc">This bit controls the XOSC0 clock failure detector:</div><div class="ttdef"><b>Definition:</b> <a href="conf__core_8h_source.html#l00128">conf_core.h:128</a></div></div>
<div class="ttc" id="aconf__core_8h_html_a9de3ab7eb7e3c001d6aa7040f6311f10"><div class="ttname"><a href="conf__core_8h.html#a9de3ab7eb7e3c001d6aa7040f6311f10">CONF_CORE_CLK_DPLL1_FILTER</a></div><div class="ttdeci">#define CONF_CORE_CLK_DPLL1_FILTER</div><div class="ttdef"><b>Definition:</b> <a href="conf__core_8h_source.html#l00535">conf_core.h:535</a></div></div>
<div class="ttc" id="aconf__core_8h_html_a590b1e68a3f666bdea576a32f4e74ba0"><div class="ttname"><a href="conf__core_8h.html#a590b1e68a3f666bdea576a32f4e74ba0">CONF_CORE_CLK_XOSC1_SWBEN</a></div><div class="ttdeci">#define CONF_CORE_CLK_XOSC1_SWBEN</div><div class="ttdoc">This bit controls the XOSC1 output clock switch back to the external clock or crystal oscillator in c...</div><div class="ttdef"><b>Definition:</b> <a href="conf__core_8h_source.html#l00241">conf_core.h:241</a></div></div>
<div class="ttc" id="aconf__core_8h_html_a2683d3721ab44a85e60cfff0d0cbf96e"><div class="ttname"><a href="conf__core_8h.html#a2683d3721ab44a85e60cfff0d0cbf96e">CONF_CORE_CLK_XOSC0_ENALC</a></div><div class="ttdeci">#define CONF_CORE_CLK_XOSC0_ENALC</div><div class="ttdoc">This bit controls the XOSC0 automatic loop control:</div><div class="ttdef"><b>Definition:</b> <a href="conf__core_8h_source.html#l00120">conf_core.h:120</a></div></div>
<div class="ttc" id="aconf__core_8h_html_ae9fbb8d05dc5808f510eae4e8a629826"><div class="ttname"><a href="conf__core_8h.html#ae9fbb8d05dc5808f510eae4e8a629826">CONF_CORE_CLK_XOSC32K_EN32K</a></div><div class="ttdeci">#define CONF_CORE_CLK_XOSC32K_EN32K</div><div class="ttdef"><b>Definition:</b> <a href="conf__core_8h_source.html#l00336">conf_core.h:336</a></div></div>
<div class="ttc" id="aconf__core_8h_html_a5cd9abca6f486eaebb6ddd236960b01a"><div class="ttname"><a href="conf__core_8h.html#a5cd9abca6f486eaebb6ddd236960b01a">CONF_CORE_CLK_DPLL0_FILTER</a></div><div class="ttdeci">#define CONF_CORE_CLK_DPLL0_FILTER</div><div class="ttdef"><b>Definition:</b> <a href="conf__core_8h_source.html#l00490">conf_core.h:490</a></div></div>
<div class="ttc" id="aconf__core_8h_html_a031a77340c697036538d218724837de1"><div class="ttname"><a href="conf__core_8h.html#a031a77340c697036538d218724837de1">CONF_CORE_CLK_XOSC32K_CGM</a></div><div class="ttdeci">#define CONF_CORE_CLK_XOSC32K_CGM</div><div class="ttdoc">These bits control the gain of the external crstal oscillator.</div><div class="ttdef"><b>Definition:</b> <a href="conf__core_8h_source.html#l00293">conf_core.h:293</a></div></div>
<div class="ttc" id="aconf__core_8h_html_aa9643e96439d0d47e0684a4b11c1f529"><div class="ttname"><a href="conf__core_8h.html#aa9643e96439d0d47e0684a4b11c1f529">CONF_CORE_MCLK_CPUDIV</a></div><div class="ttdeci">#define CONF_CORE_MCLK_CPUDIV</div><div class="ttdoc">Define the master clock divisor.</div><div class="ttdef"><b>Definition:</b> <a href="conf__core_8h_source.html#l00038">conf_core.h:38</a></div></div>
<div class="ttc" id="aconf__core_8h_html_ac2ca0e9037347eb69d53a0011f989910"><div class="ttname"><a href="conf__core_8h.html#ac2ca0e9037347eb69d53a0011f989910">CONF_CORE_CLK_XOSC0_XTALEN</a></div><div class="ttdeci">#define CONF_CORE_CLK_XOSC0_XTALEN</div><div class="ttdoc">This bit controls the connections between the I/O pads and the external clock or crystal oscillator X...</div><div class="ttdef"><b>Definition:</b> <a href="conf__core_8h_source.html#l00084">conf_core.h:84</a></div></div>
<div class="ttc" id="aconf__core_8h_html_a8bec34fdc01ac38ec0c2d13112f28aa0"><div class="ttname"><a href="conf__core_8h.html#a8bec34fdc01ac38ec0c2d13112f28aa0">CONF_CORE_CLK_XOSC1_RUNSTDBY</a></div><div class="ttdeci">#define CONF_CORE_CLK_XOSC1_RUNSTDBY</div><div class="ttdoc">This bit controls how the XOSC1 behaves during standby sleep mode:</div><div class="ttdef"><b>Definition:</b> <a href="conf__core_8h_source.html#l00198">conf_core.h:198</a></div></div>
<div class="ttc" id="aconf__core_8h_html_a924214b0f469bde71ff28fe5544466db"><div class="ttname"><a href="conf__core_8h.html#a924214b0f469bde71ff28fe5544466db">CONF_CORE_CLK_XOSC1_CFDEN</a></div><div class="ttdeci">#define CONF_CORE_CLK_XOSC1_CFDEN</div><div class="ttdoc">This bit controls the XOSC1 clock failure detector:</div><div class="ttdef"><b>Definition:</b> <a href="conf__core_8h_source.html#l00232">conf_core.h:232</a></div></div>
<div class="ttc" id="aconf__core_8h_html_a668d68edf9a7ac05be5b9cda247225ad"><div class="ttname"><a href="conf__core_8h.html#a668d68edf9a7ac05be5b9cda247225ad">CONF_CORE_CLK_XOSC32K_CFDEN</a></div><div class="ttdeci">#define CONF_CORE_CLK_XOSC32K_CFDEN</div><div class="ttdoc">This bit selects the Clock Failulre Detector state.</div><div class="ttdef"><b>Definition:</b> <a href="conf__core_8h_source.html#l00360">conf_core.h:360</a></div></div>
<div class="ttc" id="asame54n19a_8h_html_a625e6fdb4c2120fc163e1b04178af3dd"><div class="ttname"><a href="same54n19a_8h.html#a625e6fdb4c2120fc163e1b04178af3dd">MCLK</a></div><div class="ttdeci">#define MCLK</div><div class="ttdoc">(MCLK) APB Base Address</div><div class="ttdef"><b>Definition:</b> <a href="same54n19a_8h_source.html#l00914">same54n19a.h:914</a></div></div>
<div class="ttc" id="aconf__core_8h_html_aa54465cc56631333a22ae84ab66d5f3a"><div class="ttname"><a href="conf__core_8h.html#aa54465cc56631333a22ae84ab66d5f3a">CONF_CORE_CLK_XOSC1_ENABLE</a></div><div class="ttdeci">#define CONF_CORE_CLK_XOSC1_ENABLE</div><div class="ttdoc">Enables or Disables the XOSC1 Clock.</div><div class="ttdef"><b>Definition:</b> <a href="conf__core_8h_source.html#l00180">conf_core.h:180</a></div></div>
<div class="ttc" id="aconf__core_8h_html_a3a42de5c6251540e7b8c000974acfc62"><div class="ttname"><a href="conf__core_8h.html#a3a42de5c6251540e7b8c000974acfc62">CONF_CORE_CLK_XOSC1_ENALC</a></div><div class="ttdeci">#define CONF_CORE_CLK_XOSC1_ENALC</div><div class="ttdoc">This bit controls the XOSC1 automatic loop control:</div><div class="ttdef"><b>Definition:</b> <a href="conf__core_8h_source.html#l00224">conf_core.h:224</a></div></div>
<div class="ttc" id="aconf__core_8h_html_abe235b3b13f253acb855d15c8f33c95a"><div class="ttname"><a href="conf__core_8h.html#abe235b3b13f253acb855d15c8f33c95a">CONF_CORE_CLK_XOSC0_SWBEN</a></div><div class="ttdeci">#define CONF_CORE_CLK_XOSC0_SWBEN</div><div class="ttdoc">This bit controls the XOSC0 output clock switch back to the external clock or crystal oscillator in c...</div><div class="ttdef"><b>Definition:</b> <a href="conf__core_8h_source.html#l00137">conf_core.h:137</a></div></div>
<div class="ttc" id="aconf__core_8h_html_a61559adc856ce1dcfa046e749af63bc3"><div class="ttname"><a href="conf__core_8h.html#a61559adc856ce1dcfa046e749af63bc3">CONF_CORE_CLK_XOSC0_ENABLE</a></div><div class="ttdeci">#define CONF_CORE_CLK_XOSC0_ENABLE</div><div class="ttdoc">Enables or Disables the XOSC0 Clock.</div><div class="ttdef"><b>Definition:</b> <a href="conf__core_8h_source.html#l00076">conf_core.h:76</a></div></div>
<div class="ttc" id="aconf__core_8h_html_ae3f8741e2be4b37a46dfb49af2c2a09d"><div class="ttname"><a href="conf__core_8h.html#ae3f8741e2be4b37a46dfb49af2c2a09d">CONF_CORE_CLK_XOSC1_XTALEN</a></div><div class="ttdeci">#define CONF_CORE_CLK_XOSC1_XTALEN</div><div class="ttdoc">This bit controls the connections between the I/O pads and the external clock or crystal oscillator X...</div><div class="ttdef"><b>Definition:</b> <a href="conf__core_8h_source.html#l00188">conf_core.h:188</a></div></div>
<div class="ttc" id="aconf__core_8h_html_a6a65a6f4bf7e21dc2003b61a7045e24a"><div class="ttname"><a href="conf__core_8h.html#a6a65a6f4bf7e21dc2003b61a7045e24a">CONF_CORE_CLK_XOSC32K_XTALEN</a></div><div class="ttdeci">#define CONF_CORE_CLK_XOSC32K_XTALEN</div><div class="ttdoc">This bit controls the connections between the I/O pads and the external clock or crystal oscillator.</div><div class="ttdef"><b>Definition:</b> <a href="conf__core_8h_source.html#l00344">conf_core.h:344</a></div></div>
<div class="ttc" id="asame54n19a_8h_html_af1a4b8f1d1a2265b93f22621f7903f88"><div class="ttname"><a href="same54n19a_8h.html#af1a4b8f1d1a2265b93f22621f7903f88">OSC32KCTRL</a></div><div class="ttdeci">#define OSC32KCTRL</div><div class="ttdoc">(OSC32KCTRL) APB Base Address</div><div class="ttdef"><b>Definition:</b> <a href="same54n19a_8h_source.html#l00929">same54n19a.h:929</a></div></div>
<div class="ttc" id="aconf__core_8h_html_a55515b150245a993779a0d5f417cc828"><div class="ttname"><a href="conf__core_8h.html#a55515b150245a993779a0d5f417cc828">CONF_CORE_CLK_DFLL_ONDEMAND</a></div><div class="ttdeci">#define CONF_CORE_CLK_DFLL_ONDEMAND</div><div class="ttdoc">Enables or Disables on-demand operation.</div><div class="ttdef"><b>Definition:</b> <a href="conf__core_8h_source.html#l00132">conf_core.h:132</a></div></div>
<div class="ttc" id="aconf__core_8h_html_a314b78ee48f1ecf6c40f4bad7ef63d9d"><div class="ttname"><a href="conf__core_8h.html#a314b78ee48f1ecf6c40f4bad7ef63d9d">CONF_CORE_CLK_XOSC32K_STARTUP_TIME</a></div><div class="ttdeci">#define CONF_CORE_CLK_XOSC32K_STARTUP_TIME</div><div class="ttdoc">These bits select the startup time for the oscillator.</div><div class="ttdef"><b>Definition:</b> <a href="conf__core_8h_source.html#l00306">conf_core.h:306</a></div></div>
<div class="ttc" id="aconf__core_8h_html_a55515b150245a993779a0d5f417cc828"><div class="ttname"><a href="conf__core_8h.html#a55515b150245a993779a0d5f417cc828">CONF_CORE_CLK_DFLL_ONDEMAND</a></div><div class="ttdeci">#define CONF_CORE_CLK_DFLL_ONDEMAND</div><div class="ttdoc">Enables or Disables on-demand operation.</div><div class="ttdef"><b>Definition:</b> <a href="conf__core_8h_source.html#l00398">conf_core.h:398</a></div></div>
<div class="ttc" id="aconf__core_8h_html_adc7a2f161e9e8e54388b1f290066247e"><div class="ttname"><a href="conf__core_8h.html#adc7a2f161e9e8e54388b1f290066247e">CONF_CORE_CLK_XOSC32K_RUNSTDBY</a></div><div class="ttdeci">#define CONF_CORE_CLK_XOSC32K_RUNSTDBY</div><div class="ttdoc">This bit controls how XOSC32K behaves during standby sleep mode.</div><div class="ttdef"><b>Definition:</b> <a href="conf__core_8h_source.html#l00322">conf_core.h:322</a></div></div>
<div class="ttc" id="aconf__core_8h_html_affc8201cf2340d2236ba9ca44a1e657c"><div class="ttname"><a href="conf__core_8h.html#affc8201cf2340d2236ba9ca44a1e657c">CONF_CORE_CLK_XOSC0_STARTUP_TIME</a></div><div class="ttdeci">#define CONF_CORE_CLK_XOSC0_STARTUP_TIME</div><div class="ttdoc">These bits select start-up time for XOSC0 according to the table below:</div><div class="ttdef"><b>Definition:</b> <a href="conf__core_8h_source.html#l00159">conf_core.h:159</a></div></div>
<div class="ttc" id="aconf__core_8h_html_a8d70a30b50febec035af6b982daac395"><div class="ttname"><a href="conf__core_8h.html#a8d70a30b50febec035af6b982daac395">CONF_CORE_CLK_XOSC32K_ONDEMAND</a></div><div class="ttdeci">#define CONF_CORE_CLK_XOSC32K_ONDEMAND</div><div class="ttdoc">This bit controls how XOSC32K behaves when a peripheral clock request is detected.</div><div class="ttdef"><b>Definition:</b> <a href="conf__core_8h_source.html#l00314">conf_core.h:314</a></div></div>
<div class="ttc" id="asame54n19a_8h_html_a49136ad5bf1adc9e9a0232349bcdce57"><div class="ttname"><a href="same54n19a_8h.html#a49136ad5bf1adc9e9a0232349bcdce57">OSCCTRL</a></div><div class="ttdeci">#define OSCCTRL</div><div class="ttdoc">(OSCCTRL) APB Base Address</div><div class="ttdef"><b>Definition:</b> <a href="same54n19a_8h_source.html#l00925">same54n19a.h:925</a></div></div>
<div class="ttc" id="aconf__core_8h_html_ab6b320dcf67ec88f534adcbf77e2ce7b"><div class="ttname"><a href="conf__core_8h.html#ab6b320dcf67ec88f534adcbf77e2ce7b">CONF_CORE_CLK_DFLL_RUNSTDBY</a></div><div class="ttdeci">#define CONF_CORE_CLK_DFLL_RUNSTDBY</div><div class="ttdoc">Enables or Disables run-in-standby operation.</div><div class="ttdef"><b>Definition:</b> <a href="conf__core_8h_source.html#l00140">conf_core.h:140</a></div></div>
<div class="ttc" id="aconf__core_8h_html_a42b0270d2f3c0f51c4b3d2b8ac397fda"><div class="ttname"><a href="conf__core_8h.html#a42b0270d2f3c0f51c4b3d2b8ac397fda">CONF_CORE_CLK_XOSC32K_WRTLOCK</a></div><div class="ttdeci">#define CONF_CORE_CLK_XOSC32K_WRTLOCK</div><div class="ttdoc">This bit locks the XOSC32K register for future writes, effectively freezing the XOSC32K configuration...</div><div class="ttdef"><b>Definition:</b> <a href="conf__core_8h_source.html#l00376">conf_core.h:376</a></div></div>
<div class="ttc" id="aconf__core_8h_html_a79567f94a0f3ad2d628bcf5e1cff62d1"><div class="ttname"><a href="conf__core_8h.html#a79567f94a0f3ad2d628bcf5e1cff62d1">CONF_CORE_CLK_XOSC32K_CFDPRESC</a></div><div class="ttdeci">#define CONF_CORE_CLK_XOSC32K_CFDPRESC</div><div class="ttdoc">This bit selects the prescaler for the CLock Failure Detector:</div><div class="ttdef"><b>Definition:</b> <a href="conf__core_8h_source.html#l00352">conf_core.h:352</a></div></div>
<div class="ttc" id="aconf__core_8h_html_afac0686157854cc021424410ded071f1"><div class="ttname"><a href="conf__core_8h.html#afac0686157854cc021424410ded071f1">CONF_CORE_CLK_XOSC0_RUNSTDBY</a></div><div class="ttdeci">#define CONF_CORE_CLK_XOSC0_RUNSTDBY</div><div class="ttdoc">This bit controls how the XOSC0 behaves during standby sleep mode:</div><div class="ttdef"><b>Definition:</b> <a href="conf__core_8h_source.html#l00094">conf_core.h:94</a></div></div>
<div class="ttc" id="aconf__core_8h_html_ae8d2fdac3b52964174863149986db625"><div class="ttname"><a href="conf__core_8h.html#ae8d2fdac3b52964174863149986db625">CONF_CORE_CLK_XOSC1_STARTUP_TIME</a></div><div class="ttdeci">#define CONF_CORE_CLK_XOSC1_STARTUP_TIME</div><div class="ttdoc">These bits select start-up time for XOSC1 according to the table below:</div><div class="ttdef"><b>Definition:</b> <a href="conf__core_8h_source.html#l00263">conf_core.h:263</a></div></div>
<div class="ttc" id="aconf__core_8h_html_a033f3571fb50a6ed02278d65ea84b45e"><div class="ttname"><a href="conf__core_8h.html#a033f3571fb50a6ed02278d65ea84b45e">CONF_CORE_CLK_XOSC32K_EN1K</a></div><div class="ttdeci">#define CONF_CORE_CLK_XOSC32K_EN1K</div><div class="ttdef"><b>Definition:</b> <a href="conf__core_8h_source.html#l00329">conf_core.h:329</a></div></div>
<div class="ttc" id="aconf__core_8h_html_ab6b320dcf67ec88f534adcbf77e2ce7b"><div class="ttname"><a href="conf__core_8h.html#ab6b320dcf67ec88f534adcbf77e2ce7b">CONF_CORE_CLK_DFLL_RUNSTDBY</a></div><div class="ttdeci">#define CONF_CORE_CLK_DFLL_RUNSTDBY</div><div class="ttdoc">Enables or Disables run-in-standby operation.</div><div class="ttdef"><b>Definition:</b> <a href="conf__core_8h_source.html#l00406">conf_core.h:406</a></div></div>
<div class="ttc" id="aconf__core_8h_html"><div class="ttname"><a href="conf__core_8h.html">conf_core.h</a></div></div>
<div class="ttc" id="aconf__core_8h_html_a03160c4c7871685bbde0e96f02825842"><div class="ttname"><a href="conf__core_8h.html#a03160c4c7871685bbde0e96f02825842">CONF_CORE_CLK_DFLL_ENABLE</a></div><div class="ttdeci">#define CONF_CORE_CLK_DFLL_ENABLE</div><div class="ttdoc">Enables or Disables the DFLL48M Clock.</div><div class="ttdef"><b>Definition:</b> <a href="conf__core_8h_source.html#l00124">conf_core.h:124</a></div></div>
<div class="ttc" id="aconf__core_8h_html_a5ffaa1551b7ffb8a342b2cc5fbc5950c"><div class="ttname"><a href="conf__core_8h.html#a5ffaa1551b7ffb8a342b2cc5fbc5950c">CONF_CORE_CLK_XOSC0_ONDEMAND</a></div><div class="ttdeci">#define CONF_CORE_CLK_XOSC0_ONDEMAND</div><div class="ttdoc">The On Demand operation mode allows the oscillator XOSC0 to be enabled or disabled,...</div><div class="ttdef"><b>Definition:</b> <a href="conf__core_8h_source.html#l00103">conf_core.h:103</a></div></div>
<div class="ttc" id="aconf__core_8h_html_ac6e671eee4ca4aeb9fcbb87d52b457b5"><div class="ttname"><a href="conf__core_8h.html#ac6e671eee4ca4aeb9fcbb87d52b457b5">CONF_CORE_CLK_XOSC32K_SWBACK</a></div><div class="ttdeci">#define CONF_CORE_CLK_XOSC32K_SWBACK</div><div class="ttdoc">This bit controls the XOSC32K output switch back to the external clock or crystal oscillator in case ...</div><div class="ttdef"><b>Definition:</b> <a href="conf__core_8h_source.html#l00368">conf_core.h:368</a></div></div>
<div class="ttc" id="aconf__core_8h_html_aeea7b0d3663bb6d5ccc3218017f9a05b"><div class="ttname"><a href="conf__core_8h.html#aeea7b0d3663bb6d5ccc3218017f9a05b">CONF_CORE_CLK_XOSC0_LOWBUFGAIN</a></div><div class="ttdeci">#define CONF_CORE_CLK_XOSC0_LOWBUFGAIN</div><div class="ttdoc">The default value of LOWBUFGAIN=0 should be used to allow operating with a low amplitude oscillator....</div><div class="ttdef"><b>Definition:</b> <a href="conf__core_8h_source.html#l00112">conf_core.h:112</a></div></div>
<div class="ttc" id="aconf__core_8h_html_a03160c4c7871685bbde0e96f02825842"><div class="ttname"><a href="conf__core_8h.html#a03160c4c7871685bbde0e96f02825842">CONF_CORE_CLK_DFLL_ENABLE</a></div><div class="ttdeci">#define CONF_CORE_CLK_DFLL_ENABLE</div><div class="ttdoc">Enables or Disables the DFLL48M Clock.</div><div class="ttdef"><b>Definition:</b> <a href="conf__core_8h_source.html#l00390">conf_core.h:390</a></div></div>
<div class="ttc" id="asame54n19a_8h_html_a23f9186cfd6ee5e60c8485315183271f"><div class="ttname"><a href="same54n19a_8h.html#a23f9186cfd6ee5e60c8485315183271f">GCLK</a></div><div class="ttdeci">#define GCLK</div><div class="ttdoc">(GCLK) APB Base Address</div><div class="ttdef"><b>Definition:</b> <a href="same54n19a_8h_source.html#l00894">same54n19a.h:894</a></div></div>
<div class="ttc" id="aconf__core_8h_html_a0d8e56832f3d1f24b98173e3a3aa0046"><div class="ttname"><a href="conf__core_8h.html#a0d8e56832f3d1f24b98173e3a3aa0046">CONF_CORE_CLK_DFLL_GCLK_SRC</a></div><div class="ttdeci">#define CONF_CORE_CLK_DFLL_GCLK_SRC</div><div class="ttdoc">GCLK Source used to generate DFLL48M.</div><div class="ttdef"><b>Definition:</b> <a href="conf__core_8h_source.html#l00178">conf_core.h:178</a></div></div>
<div class="ttc" id="aconf__core_8h_html_a0d8e56832f3d1f24b98173e3a3aa0046"><div class="ttname"><a href="conf__core_8h.html#a0d8e56832f3d1f24b98173e3a3aa0046">CONF_CORE_CLK_DFLL_GCLK_SRC</a></div><div class="ttdeci">#define CONF_CORE_CLK_DFLL_GCLK_SRC</div><div class="ttdoc">GCLK Source used to generate DFLL48M.</div><div class="ttdef"><b>Definition:</b> <a href="conf__core_8h_source.html#l00444">conf_core.h:444</a></div></div>
<div class="ttc" id="aconf__core_8h_html_a985ebd23986d9411d3602040e33bb405"><div class="ttname"><a href="conf__core_8h.html#a985ebd23986d9411d3602040e33bb405">CONF_CORE_CLK_XOSC1_LOWBUFGAIN</a></div><div class="ttdeci">#define CONF_CORE_CLK_XOSC1_LOWBUFGAIN</div><div class="ttdoc">The default value of LOWBUFGAIN=0 should be used to allow operating with a low amplitude oscillator....</div><div class="ttdef"><b>Definition:</b> <a href="conf__core_8h_source.html#l00216">conf_core.h:216</a></div></div>
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@ -87,67 +87,50 @@ $(function() {
<div class="line"><a name="l00016"></a><span class="lineno"> 16</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_XOSC32KCTRL_STARTUP_4000009200ns (0x5)</span></div>
<div class="line"><a name="l00017"></a><span class="lineno"> 17</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_XOSC32KCTRL_STARTUP_8000009200ns (0x6)</span></div>
<div class="line"><a name="l00018"></a><span class="lineno"> 18</span>&#160; </div>
<div class="line"><a name="l00019"></a><span class="lineno"> 19</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_XOSCCTRL_STARTUP_31us 0x0</span></div>
<div class="line"><a name="l00020"></a><span class="lineno"> 20</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_XOSCCTRL_STARTUP_61us 0x1</span></div>
<div class="line"><a name="l00021"></a><span class="lineno"> 21</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_XOSCCTRL_STARTUP_122us 0x2</span></div>
<div class="line"><a name="l00022"></a><span class="lineno"> 22</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_XOSCCTRL_STARTUP_244us 0x3</span></div>
<div class="line"><a name="l00023"></a><span class="lineno"> 23</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_XOSCCTRL_STARTUP_488us 0x4</span></div>
<div class="line"><a name="l00024"></a><span class="lineno"> 24</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_XOSCCTRL_STARTUP_977us 0x5</span></div>
<div class="line"><a name="l00025"></a><span class="lineno"> 25</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_XOSCCTRL_STARTUP_1953us 0x6</span></div>
<div class="line"><a name="l00026"></a><span class="lineno"> 26</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_XOSCCTRL_STARTUP_3906us 0x7</span></div>
<div class="line"><a name="l00027"></a><span class="lineno"> 27</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_XOSCCTRL_STARTUP_7813us 0x8</span></div>
<div class="line"><a name="l00028"></a><span class="lineno"> 28</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_XOSCCTRL_STARTUP_15625us 0x9</span></div>
<div class="line"><a name="l00029"></a><span class="lineno"> 29</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_XOSCCTRL_STARTUP_31250us 0xA</span></div>
<div class="line"><a name="l00030"></a><span class="lineno"> 30</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_XOSCCTRL_STARTUP_62500us 0xB</span></div>
<div class="line"><a name="l00031"></a><span class="lineno"> 31</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_XOSCCTRL_STARTUP_125000us 0xC</span></div>
<div class="line"><a name="l00032"></a><span class="lineno"> 32</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_XOSCCTRL_STARTUP_250000us 0xD</span></div>
<div class="line"><a name="l00033"></a><span class="lineno"> 33</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_XOSCCTRL_STARTUP_500000us 0xE</span></div>
<div class="line"><a name="l00034"></a><span class="lineno"> 34</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_XOSCCTRL_STARTUP_1000000us 0xF</span></div>
<div class="line"><a name="l00035"></a><span class="lineno"> 35</span>&#160; </div>
<div class="line"><a name="l00036"></a><span class="lineno"> 36</span>&#160;<span class="comment">// Oscillator Current Multiplier</span></div>
<div class="line"><a name="l00037"></a><span class="lineno"> 37</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_XOSCCTRL_IMULT_24MHZ_TO_48MHZ (6)</span></div>
<div class="line"><a name="l00038"></a><span class="lineno"> 38</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_XOSCCTRL_IMULT_16MHZ_TO_24MHZ (5)</span></div>
<div class="line"><a name="l00039"></a><span class="lineno"> 39</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_XOSCCTRL_IMULT_8MHZ_TO_16MHZ (4)</span></div>
<div class="line"><a name="l00040"></a><span class="lineno"> 40</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_XOSCCTRL_IMULT_8MHZ (3)</span></div>
<div class="line"><a name="l00041"></a><span class="lineno"> 41</span>&#160; </div>
<div class="line"><a name="l00042"></a><span class="lineno"> 42</span>&#160;<span class="comment">// Oscillator Current Reference</span></div>
<div class="line"><a name="l00043"></a><span class="lineno"> 43</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_XOSCCTRL_IPTAT_24MHZ_TO_48MHZ (3)</span></div>
<div class="line"><a name="l00044"></a><span class="lineno"> 44</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_XOSCCTRL_IPTAT_16MHZ_TO_24MHZ (3)</span></div>
<div class="line"><a name="l00045"></a><span class="lineno"> 45</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_XOSCCTRL_IPTAT_8MHZ_TO_16MHZ (3)</span></div>
<div class="line"><a name="l00046"></a><span class="lineno"> 46</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_XOSCCTRL_IPTAT_8MHZ (2)</span></div>
<div class="line"><a name="l00047"></a><span class="lineno"> 47</span>&#160; </div>
<div class="line"><a name="l00048"></a><span class="lineno"> 48</span>&#160;<span class="comment">// DFLL Definitions</span></div>
<div class="line"><a name="l00049"></a><span class="lineno"> 49</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_DFLLCTRL_STABLE_FCALIB_NOT_FIXED (0)</span></div>
<div class="line"><a name="l00050"></a><span class="lineno"> 50</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_DFLLCTRL_STABLE_FCALIB_FIXED (1)</span></div>
<div class="line"><a name="l00051"></a><span class="lineno"> 51</span>&#160; </div>
<div class="line"><a name="l00052"></a><span class="lineno"> 52</span>&#160;<span class="comment">// DPLL Definitions</span></div>
<div class="line"><a name="l00053"></a><span class="lineno"> 53</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_DPLLCTRL_DCOFILTER_3210KHZ (0x0)</span></div>
<div class="line"><a name="l00054"></a><span class="lineno"> 54</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_DPLLCTRL_DCOFILTER_1600KHZ (0x1)</span></div>
<div class="line"><a name="l00055"></a><span class="lineno"> 55</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_DPLLCTRL_DCOFILTER_1100KHZ (0x2)</span></div>
<div class="line"><a name="l00056"></a><span class="lineno"> 56</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_DPLLCTRL_DCOFILTER_800KHZ (0x3)</span></div>
<div class="line"><a name="l00057"></a><span class="lineno"> 57</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_DPLLCTRL_DCOFILTER_640KHZ (0x4)</span></div>
<div class="line"><a name="l00058"></a><span class="lineno"> 58</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_DPLLCTRL_DCOFILTER_550KHZ (0x5)</span></div>
<div class="line"><a name="l00059"></a><span class="lineno"> 59</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_DPLLCTRL_DCOFILTER_450KHZ (0x6)</span></div>
<div class="line"><a name="l00060"></a><span class="lineno"> 60</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_DPLLCTRL_DCOFILTER_400KHZ (0x7)</span></div>
<div class="line"><a name="l00061"></a><span class="lineno"> 61</span>&#160; </div>
<div class="line"><a name="l00062"></a><span class="lineno"> 62</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_DPLLCTRL_LTIME_TIMEOUT_NONE (0x0)</span></div>
<div class="line"><a name="l00063"></a><span class="lineno"> 63</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_DPLLCTRL_LTIME_TIMEOUT_800us (0x4)</span></div>
<div class="line"><a name="l00064"></a><span class="lineno"> 64</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_DPLLCTRL_LTIME_TIMEOUT_900us (0x5)</span></div>
<div class="line"><a name="l00065"></a><span class="lineno"> 65</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_DPLLCTRL_LTIME_TIMEOUT_1000us (0x6)</span></div>
<div class="line"><a name="l00066"></a><span class="lineno"> 66</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_DPLLCTRL_LTIME_TIMEOUT_1100us (0x7)</span></div>
<div class="line"><a name="l00067"></a><span class="lineno"> 67</span>&#160; </div>
<div class="line"><a name="l00068"></a><span class="lineno"> 68</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_DPLLCTRL_REFCLK_GCLK (0x0)</span></div>
<div class="line"><a name="l00069"></a><span class="lineno"> 69</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_DPLLCTRL_REFCLK_XOSC32 (0x1)</span></div>
<div class="line"><a name="l00070"></a><span class="lineno"> 70</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_DPLLCTRL_REFCLK_XOSC0 (0x2)</span></div>
<div class="line"><a name="l00071"></a><span class="lineno"> 71</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_DPLLCTRL_REFCLK_XOSC1 (0x3)</span></div>
<div class="line"><a name="l00072"></a><span class="lineno"> 72</span>&#160; </div>
<div class="line"><a name="l00073"></a><span class="lineno"> 73</span>&#160;<span class="keywordtype">void</span> clock_osc32k_init(<span class="keywordtype">void</span>);</div>
<div class="line"><a name="l00074"></a><span class="lineno"> 74</span>&#160;<span class="keywordtype">void</span> clock_osc_init(<span class="keywordtype">void</span>);</div>
<div class="line"><a name="l00075"></a><span class="lineno"> 75</span>&#160;<span class="keywordtype">void</span> clock_mclk_init(<span class="keywordtype">void</span>);</div>
<div class="line"><a name="l00076"></a><span class="lineno"> 76</span>&#160;<span class="keywordtype">void</span> clock_gclk_init(<span class="keywordtype">void</span>);</div>
<div class="line"><a name="l00077"></a><span class="lineno"> 77</span>&#160;<span class="keywordtype">void</span> clock_dpll_init(<span class="keywordtype">void</span>);</div>
<div class="line"><a name="l00078"></a><span class="lineno"> 78</span>&#160;<span class="keywordtype">void</span> clock_dfll_init(<span class="keywordtype">void</span>);</div>
<div class="line"><a name="l00079"></a><span class="lineno"> 79</span>&#160;<span class="preprocessor">#endif</span></div>
<div class="line"><a name="l00019"></a><span class="lineno"> 19</span>&#160;<span class="comment">// Oscillator Current Multiplier</span></div>
<div class="line"><a name="l00020"></a><span class="lineno"> 20</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_XOSCCTRL_IMULT_24MHZ_TO_48MHZ (6)</span></div>
<div class="line"><a name="l00021"></a><span class="lineno"> 21</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_XOSCCTRL_IMULT_16MHZ_TO_24MHZ (5)</span></div>
<div class="line"><a name="l00022"></a><span class="lineno"> 22</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_XOSCCTRL_IMULT_8MHZ_TO_16MHZ (4)</span></div>
<div class="line"><a name="l00023"></a><span class="lineno"> 23</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_XOSCCTRL_IMULT_8MHZ (3)</span></div>
<div class="line"><a name="l00024"></a><span class="lineno"> 24</span>&#160; </div>
<div class="line"><a name="l00025"></a><span class="lineno"> 25</span>&#160;<span class="comment">// Oscillator Current Reference</span></div>
<div class="line"><a name="l00026"></a><span class="lineno"> 26</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_XOSCCTRL_IPTAT_24MHZ_TO_48MHZ (3)</span></div>
<div class="line"><a name="l00027"></a><span class="lineno"> 27</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_XOSCCTRL_IPTAT_16MHZ_TO_24MHZ (3)</span></div>
<div class="line"><a name="l00028"></a><span class="lineno"> 28</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_XOSCCTRL_IPTAT_8MHZ_TO_16MHZ (3)</span></div>
<div class="line"><a name="l00029"></a><span class="lineno"> 29</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_XOSCCTRL_IPTAT_8MHZ (2)</span></div>
<div class="line"><a name="l00030"></a><span class="lineno"> 30</span>&#160; </div>
<div class="line"><a name="l00031"></a><span class="lineno"> 31</span>&#160;<span class="comment">// DFLL Definitions</span></div>
<div class="line"><a name="l00032"></a><span class="lineno"> 32</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_DFLLCTRL_STABLE_FCALIB_NOT_FIXED (0)</span></div>
<div class="line"><a name="l00033"></a><span class="lineno"> 33</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_DFLLCTRL_STABLE_FCALIB_FIXED (1)</span></div>
<div class="line"><a name="l00034"></a><span class="lineno"> 34</span>&#160; </div>
<div class="line"><a name="l00035"></a><span class="lineno"> 35</span>&#160;<span class="comment">// DPLL Definitions</span></div>
<div class="line"><a name="l00036"></a><span class="lineno"> 36</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_DPLLCTRL_DCOFILTER_3210KHZ (0x0)</span></div>
<div class="line"><a name="l00037"></a><span class="lineno"> 37</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_DPLLCTRL_DCOFILTER_1600KHZ (0x1)</span></div>
<div class="line"><a name="l00038"></a><span class="lineno"> 38</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_DPLLCTRL_DCOFILTER_1100KHZ (0x2)</span></div>
<div class="line"><a name="l00039"></a><span class="lineno"> 39</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_DPLLCTRL_DCOFILTER_800KHZ (0x3)</span></div>
<div class="line"><a name="l00040"></a><span class="lineno"> 40</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_DPLLCTRL_DCOFILTER_640KHZ (0x4)</span></div>
<div class="line"><a name="l00041"></a><span class="lineno"> 41</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_DPLLCTRL_DCOFILTER_550KHZ (0x5)</span></div>
<div class="line"><a name="l00042"></a><span class="lineno"> 42</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_DPLLCTRL_DCOFILTER_450KHZ (0x6)</span></div>
<div class="line"><a name="l00043"></a><span class="lineno"> 43</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_DPLLCTRL_DCOFILTER_400KHZ (0x7)</span></div>
<div class="line"><a name="l00044"></a><span class="lineno"> 44</span>&#160; </div>
<div class="line"><a name="l00045"></a><span class="lineno"> 45</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_DPLLCTRL_LTIME_TIMEOUT_NONE (0x0)</span></div>
<div class="line"><a name="l00046"></a><span class="lineno"> 46</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_DPLLCTRL_LTIME_TIMEOUT_800us (0x4)</span></div>
<div class="line"><a name="l00047"></a><span class="lineno"> 47</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_DPLLCTRL_LTIME_TIMEOUT_900us (0x5)</span></div>
<div class="line"><a name="l00048"></a><span class="lineno"> 48</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_DPLLCTRL_LTIME_TIMEOUT_1000us (0x6)</span></div>
<div class="line"><a name="l00049"></a><span class="lineno"> 49</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_DPLLCTRL_LTIME_TIMEOUT_1100us (0x7)</span></div>
<div class="line"><a name="l00050"></a><span class="lineno"> 50</span>&#160; </div>
<div class="line"><a name="l00051"></a><span class="lineno"> 51</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_DPLLCTRL_REFCLK_GCLK (0x0)</span></div>
<div class="line"><a name="l00052"></a><span class="lineno"> 52</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_DPLLCTRL_REFCLK_XOSC32 (0x1)</span></div>
<div class="line"><a name="l00053"></a><span class="lineno"> 53</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_DPLLCTRL_REFCLK_XOSC0 (0x2)</span></div>
<div class="line"><a name="l00054"></a><span class="lineno"> 54</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_DPLLCTRL_REFCLK_XOSC1 (0x3)</span></div>
<div class="line"><a name="l00055"></a><span class="lineno"> 55</span>&#160; </div>
<div class="line"><a name="l00056"></a><span class="lineno"> 56</span>&#160;<span class="keywordtype">void</span> clock_osc32k_init(<span class="keywordtype">void</span>);</div>
<div class="line"><a name="l00057"></a><span class="lineno"> 57</span>&#160;<span class="keywordtype">void</span> clock_osc_init(<span class="keywordtype">void</span>);</div>
<div class="line"><a name="l00058"></a><span class="lineno"> 58</span>&#160;<span class="keywordtype">void</span> clock_mclk_init(<span class="keywordtype">void</span>);</div>
<div class="line"><a name="l00059"></a><span class="lineno"> 59</span>&#160;<span class="keywordtype">void</span> clock_gclk_init(<span class="keywordtype">void</span>);</div>
<div class="line"><a name="l00060"></a><span class="lineno"> 60</span>&#160;<span class="keywordtype">void</span> clock_dpll_init(<span class="keywordtype">void</span>);</div>
<div class="line"><a name="l00061"></a><span class="lineno"> 61</span>&#160;<span class="keywordtype">void</span> clock_dfll_init(<span class="keywordtype">void</span>);</div>
<div class="line"><a name="l00062"></a><span class="lineno"> 62</span>&#160;<span class="preprocessor">#endif</span></div>
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@ -74,221 +74,252 @@ $(function() {
<div class="line"><a name="l00011"></a><span class="lineno"> 11</span>&#160;<span class="preprocessor">#define _CONF_CLOCKS_H_</span></div>
<div class="line"><a name="l00012"></a><span class="lineno"> 12</span>&#160;<span class="preprocessor">#include &quot;clocks.h&quot;</span></div>
<div class="line"><a name="l00013"></a><span class="lineno"> 13</span>&#160; </div>
<div class="line"><a name="l00023"></a><span class="lineno"><a class="line" href="conf__core_8h.html#ab46aa120e454ecf957efa4bd97be5bdf"> 23</a></span>&#160;<span class="preprocessor">#define CONF_CORE_MCLK_NVM_WAIT_STATE 0x5</span></div>
<div class="line"><a name="l00024"></a><span class="lineno"> 24</span>&#160; </div>
<div class="line"><a name="l00036"></a><span class="lineno"><a class="line" href="conf__core_8h.html#aa9643e96439d0d47e0684a4b11c1f529"> 36</a></span>&#160;<span class="preprocessor">#define CONF_CORE_MCLK_CPUDIV 0x1</span></div>
<div class="line"><a name="l00037"></a><span class="lineno"> 37</span>&#160; </div>
<div class="line"><a name="l00045"></a><span class="lineno"><a class="line" href="conf__core_8h.html#a16a34b830edda5b571c41a0f865f7051"> 45</a></span>&#160;<span class="preprocessor">#define CONF_CORE_DMA_ENABLE (0)</span></div>
<div class="line"><a name="l00046"></a><span class="lineno"> 46</span>&#160; </div>
<div class="line"><a name="l00052"></a><span class="lineno"><a class="line" href="conf__core_8h.html#a81edcdaa3908cc3d99a95047e4431405"> 52</a></span>&#160;<span class="preprocessor">#define CONF_CORE_CMCC_ENABLE (0)</span></div>
<div class="line"><a name="l00053"></a><span class="lineno"> 53</span>&#160; </div>
<div class="line"><a name="l00054"></a><span class="lineno"> 54</span>&#160;<span class="preprocessor">#define CONF_CORE_PORT_EVCTRL_0_ENABLE (0)</span></div>
<div class="line"><a name="l00055"></a><span class="lineno"> 55</span>&#160;<span class="preprocessor">#define CONF_CORE_PORT_EVCTRL_1_ENABLE (0)</span></div>
<div class="line"><a name="l00056"></a><span class="lineno"> 56</span>&#160;<span class="preprocessor">#define CONF_CORE_PORT_EVCTRL_2_ENABLE (0)</span></div>
<div class="line"><a name="l00057"></a><span class="lineno"> 57</span>&#160; </div>
<div class="line"><a name="l00062"></a><span class="lineno"> 62</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_XOSC0_ENABLE (1)</span></div>
<div class="line"><a name="l00063"></a><span class="lineno"> 63</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_XOSC0_XTALEN (1)</span></div>
<div class="line"><a name="l00064"></a><span class="lineno"> 64</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_XOSC0_RUNSTDBY (0)</span></div>
<div class="line"><a name="l00065"></a><span class="lineno"> 65</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_XOSC0_ONDEMAND (0)</span></div>
<div class="line"><a name="l00066"></a><span class="lineno"> 66</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_XOSC0_LOWBUFGAIN (0)</span></div>
<div class="line"><a name="l00067"></a><span class="lineno"> 67</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_XOSC0_ENALC (1)</span></div>
<div class="line"><a name="l00068"></a><span class="lineno"> 68</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_XOSC0_CFDEN (1)</span></div>
<div class="line"><a name="l00069"></a><span class="lineno"> 69</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_XOSC0_SWBEN (0)</span></div>
<div class="line"><a name="l00070"></a><span class="lineno"> 70</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_XOSC0_STARTUP_TIME CONF_CORE_CLK_XOSCCTRL_STARTUP_31us</span></div>
<div class="line"><a name="l00071"></a><span class="lineno"> 71</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_XOSC0_FREQUENCY 12000000</span></div>
<div class="line"><a name="l00072"></a><span class="lineno"> 72</span>&#160; </div>
<div class="line"><a name="l00080"></a><span class="lineno"> 80</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_XOSC1_ENABLE (0)</span></div>
<div class="line"><a name="l00081"></a><span class="lineno"> 81</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_XOSC1_XTALEN (0)</span></div>
<div class="line"><a name="l00082"></a><span class="lineno"> 82</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_XOSC1_RUNSTDBY (0)</span></div>
<div class="line"><a name="l00083"></a><span class="lineno"> 83</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_XOSC1_ONDEMAND (0)</span></div>
<div class="line"><a name="l00084"></a><span class="lineno"> 84</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_XOSC1_LOWBUFGAIN (0)</span></div>
<div class="line"><a name="l00085"></a><span class="lineno"> 85</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_XOSC1_ENALC (0)</span></div>
<div class="line"><a name="l00086"></a><span class="lineno"> 86</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_XOSC1_CFDEN (0)</span></div>
<div class="line"><a name="l00087"></a><span class="lineno"> 87</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_XOSC1_SWBEN (0)</span></div>
<div class="line"><a name="l00088"></a><span class="lineno"> 88</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_XOSC1_STARTUP_TIME CONF_CORE_CLK_XOSCCTRL_STARTUP_31us</span></div>
<div class="line"><a name="l00089"></a><span class="lineno"> 89</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_XOSC1_FREQUENCY 12000000</span></div>
<div class="line"><a name="l00090"></a><span class="lineno"> 90</span>&#160; </div>
<div class="line"><a name="l00098"></a><span class="lineno"> 98</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_XOSC32K_ENABLE (1)</span></div>
<div class="line"><a name="l00099"></a><span class="lineno"> 99</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_XOSC32K_CGM CONF_CORE_CLK_XOSC32KCTRL_CGM_STD_MODE</span></div>
<div class="line"><a name="l00100"></a><span class="lineno"> 100</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_XOSC32K_STARTUP_TIME CONF_CORE_CLK_XOSC32KCTRL_STARTUP_62592us</span></div>
<div class="line"><a name="l00101"></a><span class="lineno"> 101</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_XOSC32K_ONDEMAND (1)</span></div>
<div class="line"><a name="l00102"></a><span class="lineno"> 102</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_XOSC32K_RUNSTDBY (0)</span></div>
<div class="line"><a name="l00103"></a><span class="lineno"> 103</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_XOSC32K_EN1K (0)</span></div>
<div class="line"><a name="l00104"></a><span class="lineno"> 104</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_XOSC32K_EN32K (1)</span></div>
<div class="line"><a name="l00105"></a><span class="lineno"> 105</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_XOSC32K_XTALEN (1)</span></div>
<div class="line"><a name="l00106"></a><span class="lineno"> 106</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_XOSC32K_CFDPRESC (0)</span></div>
<div class="line"><a name="l00107"></a><span class="lineno"> 107</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_XOSC32K_CFDEN (0)</span></div>
<div class="line"><a name="l00108"></a><span class="lineno"> 108</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_XOSC32K_SWBACK (0)</span></div>
<div class="line"><a name="l00109"></a><span class="lineno"> 109</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_XOSC32K_WRTLOCK (0)</span></div>
<div class="line"><a name="l00110"></a><span class="lineno"> 110</span>&#160; </div>
<div class="line"><a name="l00124"></a><span class="lineno"><a class="line" href="conf__core_8h.html#a03160c4c7871685bbde0e96f02825842"> 124</a></span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_DFLL_ENABLE (1)</span></div>
<div class="line"><a name="l00125"></a><span class="lineno"> 125</span>&#160; </div>
<div class="line"><a name="l00132"></a><span class="lineno"><a class="line" href="conf__core_8h.html#a55515b150245a993779a0d5f417cc828"> 132</a></span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_DFLL_ONDEMAND (0)</span></div>
<div class="line"><a name="l00133"></a><span class="lineno"> 133</span>&#160; </div>
<div class="line"><a name="l00140"></a><span class="lineno"><a class="line" href="conf__core_8h.html#ab6b320dcf67ec88f534adcbf77e2ce7b"> 140</a></span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_DFLL_RUNSTDBY (0)</span></div>
<div class="line"><a name="l00141"></a><span class="lineno"> 141</span>&#160; </div>
<div class="line"><a name="l00148"></a><span class="lineno"><a class="line" href="conf__core_8h.html#a1f088d6654bb907ff388ced455b2dbb2"> 148</a></span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_DFLL_WAITLOCK (0)</span></div>
<div class="line"><a name="l00149"></a><span class="lineno"> 149</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_DFLL_BPLKC (0)</span></div>
<div class="line"><a name="l00150"></a><span class="lineno"> 150</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_DFLL_QLDIS (0)</span></div>
<div class="line"><a name="l00151"></a><span class="lineno"> 151</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_DFLL_CCDIS (1)</span></div>
<div class="line"><a name="l00152"></a><span class="lineno"> 152</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_DFLL_USBCRM (1)</span></div>
<div class="line"><a name="l00153"></a><span class="lineno"> 153</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_DFLL_LLAW (0)</span></div>
<div class="line"><a name="l00154"></a><span class="lineno"> 154</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_DFLL_STABLE_FCALIB CONF_CORE_CLK_DFLLCTRL_STABLE_FCALIB_NOT_FIXED</span></div>
<div class="line"><a name="l00155"></a><span class="lineno"> 155</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_DFLL_MODE 0x01</span></div>
<div class="line"><a name="l00156"></a><span class="lineno"> 156</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_DFLL_DIFF_VAL 0</span></div>
<div class="line"><a name="l00157"></a><span class="lineno"> 157</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_DFLL_COARSE_VAL (0x1f / 4)</span></div>
<div class="line"><a name="l00158"></a><span class="lineno"> 158</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_DFLL_FINE_VAL 128</span></div>
<div class="line"><a name="l00159"></a><span class="lineno"> 159</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_DFLL_CSTEP_VAL 1</span></div>
<div class="line"><a name="l00160"></a><span class="lineno"> 160</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_DFLL_FSTEP_VAL 1</span></div>
<div class="line"><a name="l00161"></a><span class="lineno"> 161</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_DFLL_MUL_VAL (48000000)</span></div>
<div class="line"><a name="l00162"></a><span class="lineno"> 162</span>&#160; </div>
<div class="line"><a name="l00178"></a><span class="lineno"><a class="line" href="conf__core_8h.html#a0d8e56832f3d1f24b98173e3a3aa0046"> 178</a></span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_DFLL_GCLK_SRC 3</span></div>
<div class="line"><a name="l00179"></a><span class="lineno"> 179</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_DFLL_OVERWRITE_CAL 0</span></div>
<div class="line"><a name="l00180"></a><span class="lineno"> 180</span>&#160; </div>
<div class="line"><a name="l00187"></a><span class="lineno"> 187</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_DPLL0_ENABLE (1)</span></div>
<div class="line"><a name="l00188"></a><span class="lineno"> 188</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_DPLL0_ONDEMAND (0)</span></div>
<div class="line"><a name="l00189"></a><span class="lineno"> 189</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_DPLL0_RUNSTDBY (0)</span></div>
<div class="line"><a name="l00190"></a><span class="lineno"> 190</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_DPLL0_LDRFRAC_VAL 0</span></div>
<div class="line"><a name="l00191"></a><span class="lineno"> 191</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_DPLL0_LDR_VAL (119)</span></div>
<div class="line"><a name="l00192"></a><span class="lineno"> 192</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_DPLL0_DIV_VAL (5)</span></div>
<div class="line"><a name="l00193"></a><span class="lineno"> 193</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_DPLL0_DCOEN 0</span></div>
<div class="line"><a name="l00194"></a><span class="lineno"> 194</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_DPLL0_DCOFILTER CONF_CORE_CLK_DPLLCTRL_DCOFILTER_3210KHZ</span></div>
<div class="line"><a name="l00195"></a><span class="lineno"> 195</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_DPLL0_LBYPASS 1</span></div>
<div class="line"><a name="l00196"></a><span class="lineno"> 196</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_DPLL0_LTIME 0</span></div>
<div class="line"><a name="l00197"></a><span class="lineno"> 197</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_DPLL0_WUF 0</span></div>
<div class="line"><a name="l00198"></a><span class="lineno"> 198</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_DPLL0_GCLK_SRC GCLK_GENCTRL_SRC_XOSC0</span></div>
<div class="line"><a name="l00199"></a><span class="lineno"> 199</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_DPLL0_REFCLK CONF_CORE_CLK_DPLLCTRL_REFCLK_XOSC0</span></div>
<div class="line"><a name="l00200"></a><span class="lineno"> 200</span>&#160; </div>
<div class="line"><a name="l00222"></a><span class="lineno"><a class="line" href="conf__core_8h.html#a5cd9abca6f486eaebb6ddd236960b01a"> 222</a></span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_DPLL0_FILTER 0x0</span></div>
<div class="line"><a name="l00223"></a><span class="lineno"> 223</span>&#160; </div>
<div class="line"><a name="l00230"></a><span class="lineno"> 230</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_DPLL1_ENABLE (0)</span></div>
<div class="line"><a name="l00231"></a><span class="lineno"> 231</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_DPLL1_ONDEMAND (0)</span></div>
<div class="line"><a name="l00232"></a><span class="lineno"> 232</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_DPLL1_RUNSTDBY (0)</span></div>
<div class="line"><a name="l00233"></a><span class="lineno"> 233</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_DPLL1_LDRFRAC_VAL 0</span></div>
<div class="line"><a name="l00234"></a><span class="lineno"> 234</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_DPLL1_LDR_VAL (0)</span></div>
<div class="line"><a name="l00235"></a><span class="lineno"> 235</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_DPLL1_DIV_VAL (0)</span></div>
<div class="line"><a name="l00236"></a><span class="lineno"> 236</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_DPLL1_DCOEN 0</span></div>
<div class="line"><a name="l00237"></a><span class="lineno"> 237</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_DPLL1_DCOFILTER CONF_CORE_CLK_DPLLCTRL_DCOFILTER_3210KHZ</span></div>
<div class="line"><a name="l00238"></a><span class="lineno"> 238</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_DPLL1_LBYPASS 0</span></div>
<div class="line"><a name="l00239"></a><span class="lineno"> 239</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_DPLL1_LTIME 0</span></div>
<div class="line"><a name="l00240"></a><span class="lineno"> 240</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_DPLL1_WUF 0</span></div>
<div class="line"><a name="l00241"></a><span class="lineno"> 241</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_DPLL1_GCLK_SRC GCLK_GENCTRL_SRC_XOSC0</span></div>
<div class="line"><a name="l00242"></a><span class="lineno"> 242</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_DPLL1_REFCLK CONF_CORE_CLK_DPLLCTRL_REFCLK_XOSC0</span></div>
<div class="line"><a name="l00243"></a><span class="lineno"> 243</span>&#160; </div>
<div class="line"><a name="l00267"></a><span class="lineno"><a class="line" href="conf__core_8h.html#a9de3ab7eb7e3c001d6aa7040f6311f10"> 267</a></span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_DPLL1_FILTER 0x0</span></div>
<div class="line"><a name="l00268"></a><span class="lineno"> 268</span>&#160; </div>
<div class="line"><a name="l00271"></a><span class="lineno"> 271</span>&#160;<span class="comment">// GCLK Generators Config</span></div>
<div class="line"><a name="l00272"></a><span class="lineno"> 272</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_0_ENABLE 1</span></div>
<div class="line"><a name="l00273"></a><span class="lineno"> 273</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_0_RUN_IN_STANDBY 1</span></div>
<div class="line"><a name="l00274"></a><span class="lineno"> 274</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_0_CLOCK_SOURCE GCLK_GENCTRL_SRC_XOSC0</span></div>
<div class="line"><a name="l00275"></a><span class="lineno"> 275</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_0_DIV_VAL 1</span></div>
<div class="line"><a name="l00276"></a><span class="lineno"> 276</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_0_DIVSEL 0</span></div>
<div class="line"><a name="l00277"></a><span class="lineno"> 277</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_0_OUTPUT_ENABLE 1</span></div>
<div class="line"><a name="l00278"></a><span class="lineno"> 278</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_0_OUTPUT_OFF_VALUE 1</span></div>
<div class="line"><a name="l00279"></a><span class="lineno"> 279</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_0_IDC 1</span></div>
<div class="line"><a name="l00280"></a><span class="lineno"> 280</span>&#160; </div>
<div class="line"><a name="l00281"></a><span class="lineno"> 281</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_1_ENABLE 0</span></div>
<div class="line"><a name="l00282"></a><span class="lineno"> 282</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_1_RUN_IN_STANDBY 0</span></div>
<div class="line"><a name="l00283"></a><span class="lineno"> 283</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_1_CLOCK_SOURCE GCLK_GENCTRL_SRC_XOSC0</span></div>
<div class="line"><a name="l00284"></a><span class="lineno"> 284</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_1_DIV_VAL 1</span></div>
<div class="line"><a name="l00285"></a><span class="lineno"> 285</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_1_DIVSEL 0</span></div>
<div class="line"><a name="l00286"></a><span class="lineno"> 286</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_1_OUTPUT_ENABLE 0</span></div>
<div class="line"><a name="l00287"></a><span class="lineno"> 287</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_1_OUTPUT_OFF_VALUE 0</span></div>
<div class="line"><a name="l00288"></a><span class="lineno"> 288</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_1_IDC 0</span></div>
<div class="line"><a name="l00289"></a><span class="lineno"> 289</span>&#160; </div>
<div class="line"><a name="l00290"></a><span class="lineno"> 290</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_2_ENABLE 0</span></div>
<div class="line"><a name="l00291"></a><span class="lineno"> 291</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_2_RUN_IN_STANDBY 0</span></div>
<div class="line"><a name="l00292"></a><span class="lineno"> 292</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_2_CLOCK_SOURCE GCLK_GENCTRL_SRC_XOSC0</span></div>
<div class="line"><a name="l00293"></a><span class="lineno"> 293</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_2_DIV_VAL 1</span></div>
<div class="line"><a name="l00294"></a><span class="lineno"> 294</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_2_DIVSEL 0</span></div>
<div class="line"><a name="l00295"></a><span class="lineno"> 295</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_2_OUTPUT_ENABLE 0</span></div>
<div class="line"><a name="l00296"></a><span class="lineno"> 296</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_2_OUTPUT_OFF_VALUE 0</span></div>
<div class="line"><a name="l00297"></a><span class="lineno"> 297</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_2_IDC 0</span></div>
<div class="line"><a name="l00298"></a><span class="lineno"> 298</span>&#160; </div>
<div class="line"><a name="l00299"></a><span class="lineno"> 299</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_3_ENABLE 1</span></div>
<div class="line"><a name="l00300"></a><span class="lineno"> 300</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_3_RUN_IN_STANDBY 0</span></div>
<div class="line"><a name="l00301"></a><span class="lineno"> 301</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_3_CLOCK_SOURCE GCLK_GENCTRL_SRC_XOSC32K</span></div>
<div class="line"><a name="l00302"></a><span class="lineno"> 302</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_3_DIV_VAL 1</span></div>
<div class="line"><a name="l00303"></a><span class="lineno"> 303</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_3_DIVSEL 0</span></div>
<div class="line"><a name="l00304"></a><span class="lineno"> 304</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_3_OUTPUT_ENABLE 0</span></div>
<div class="line"><a name="l00305"></a><span class="lineno"> 305</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_3_OUTPUT_OFF_VALUE 0</span></div>
<div class="line"><a name="l00306"></a><span class="lineno"> 306</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_3_IDC 0</span></div>
<div class="line"><a name="l00024"></a><span class="lineno"><a class="line" href="conf__core_8h.html#ab46aa120e454ecf957efa4bd97be5bdf"> 24</a></span>&#160;<span class="preprocessor">#define CONF_CORE_MCLK_NVM_WAIT_STATE 0x5</span></div>
<div class="line"><a name="l00025"></a><span class="lineno"> 25</span>&#160; </div>
<div class="line"><a name="l00038"></a><span class="lineno"><a class="line" href="conf__core_8h.html#aa9643e96439d0d47e0684a4b11c1f529"> 38</a></span>&#160;<span class="preprocessor">#define CONF_CORE_MCLK_CPUDIV 0x1</span></div>
<div class="line"><a name="l00039"></a><span class="lineno"> 39</span>&#160; </div>
<div class="line"><a name="l00048"></a><span class="lineno"><a class="line" href="conf__core_8h.html#a16a34b830edda5b571c41a0f865f7051"> 48</a></span>&#160;<span class="preprocessor">#define CONF_CORE_DMA_ENABLE (0)</span></div>
<div class="line"><a name="l00049"></a><span class="lineno"> 49</span>&#160; </div>
<div class="line"><a name="l00055"></a><span class="lineno"><a class="line" href="conf__core_8h.html#a81edcdaa3908cc3d99a95047e4431405"> 55</a></span>&#160;<span class="preprocessor">#define CONF_CORE_CMCC_ENABLE (0)</span></div>
<div class="line"><a name="l00056"></a><span class="lineno"> 56</span>&#160; </div>
<div class="line"><a name="l00058"></a><span class="lineno"><a class="line" href="conf__core_8h.html#a4e846249cdbec567989afa93b6653671"> 58</a></span>&#160;<span class="preprocessor">#define CONF_CORE_PORT_EVCTRL_0_ENABLE (0)</span></div>
<div class="line"><a name="l00059"></a><span class="lineno"> 59</span>&#160; </div>
<div class="line"><a name="l00060"></a><span class="lineno"><a class="line" href="conf__core_8h.html#ab1c71bf1f1249ce9046aca27329ae588"> 60</a></span>&#160;<span class="preprocessor">#define CONF_CORE_PORT_EVCTRL_1_ENABLE (0)</span></div>
<div class="line"><a name="l00061"></a><span class="lineno"> 61</span>&#160; </div>
<div class="line"><a name="l00062"></a><span class="lineno"><a class="line" href="conf__core_8h.html#a7971c1d952e35ecc50ae18de2b2c48ed"> 62</a></span>&#160;<span class="preprocessor">#define CONF_CORE_PORT_EVCTRL_2_ENABLE (0)</span></div>
<div class="line"><a name="l00063"></a><span class="lineno"> 63</span>&#160; </div>
<div class="line"><a name="l00076"></a><span class="lineno"><a class="line" href="conf__core_8h.html#a61559adc856ce1dcfa046e749af63bc3"> 76</a></span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_XOSC0_ENABLE (1)</span></div>
<div class="line"><a name="l00077"></a><span class="lineno"> 77</span>&#160; </div>
<div class="line"><a name="l00084"></a><span class="lineno"><a class="line" href="conf__core_8h.html#ac2ca0e9037347eb69d53a0011f989910"> 84</a></span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_XOSC0_XTALEN (1)</span></div>
<div class="line"><a name="l00085"></a><span class="lineno"> 85</span>&#160; </div>
<div class="line"><a name="l00094"></a><span class="lineno"><a class="line" href="conf__core_8h.html#afac0686157854cc021424410ded071f1"> 94</a></span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_XOSC0_RUNSTDBY (0)</span></div>
<div class="line"><a name="l00095"></a><span class="lineno"> 95</span>&#160; </div>
<div class="line"><a name="l00103"></a><span class="lineno"><a class="line" href="conf__core_8h.html#a5ffaa1551b7ffb8a342b2cc5fbc5950c"> 103</a></span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_XOSC0_ONDEMAND (0)</span></div>
<div class="line"><a name="l00104"></a><span class="lineno"> 104</span>&#160; </div>
<div class="line"><a name="l00112"></a><span class="lineno"><a class="line" href="conf__core_8h.html#aeea7b0d3663bb6d5ccc3218017f9a05b"> 112</a></span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_XOSC0_LOWBUFGAIN (0)</span></div>
<div class="line"><a name="l00113"></a><span class="lineno"> 113</span>&#160; </div>
<div class="line"><a name="l00120"></a><span class="lineno"><a class="line" href="conf__core_8h.html#a2683d3721ab44a85e60cfff0d0cbf96e"> 120</a></span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_XOSC0_ENALC (1)</span></div>
<div class="line"><a name="l00121"></a><span class="lineno"> 121</span>&#160; </div>
<div class="line"><a name="l00128"></a><span class="lineno"><a class="line" href="conf__core_8h.html#a17cd20bb954bc137251cf7fb63889151"> 128</a></span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_XOSC0_CFDEN (1)</span></div>
<div class="line"><a name="l00129"></a><span class="lineno"> 129</span>&#160; </div>
<div class="line"><a name="l00137"></a><span class="lineno"><a class="line" href="conf__core_8h.html#abe235b3b13f253acb855d15c8f33c95a"> 137</a></span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_XOSC0_SWBEN (0)</span></div>
<div class="line"><a name="l00138"></a><span class="lineno"> 138</span>&#160; </div>
<div class="line"><a name="l00159"></a><span class="lineno"><a class="line" href="conf__core_8h.html#affc8201cf2340d2236ba9ca44a1e657c"> 159</a></span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_XOSC0_STARTUP_TIME (0x00)</span></div>
<div class="line"><a name="l00160"></a><span class="lineno"> 160</span>&#160; </div>
<div class="line"><a name="l00165"></a><span class="lineno"><a class="line" href="conf__core_8h.html#af6ec0afa1da472db5f1def1d1923faad"> 165</a></span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_XOSC0_FREQUENCY 12000000</span></div>
<div class="line"><a name="l00166"></a><span class="lineno"> 166</span>&#160; </div>
<div class="line"><a name="l00180"></a><span class="lineno"><a class="line" href="conf__core_8h.html#aa54465cc56631333a22ae84ab66d5f3a"> 180</a></span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_XOSC1_ENABLE (0)</span></div>
<div class="line"><a name="l00181"></a><span class="lineno"> 181</span>&#160; </div>
<div class="line"><a name="l00188"></a><span class="lineno"><a class="line" href="conf__core_8h.html#ae3f8741e2be4b37a46dfb49af2c2a09d"> 188</a></span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_XOSC1_XTALEN (0)</span></div>
<div class="line"><a name="l00189"></a><span class="lineno"> 189</span>&#160; </div>
<div class="line"><a name="l00198"></a><span class="lineno"><a class="line" href="conf__core_8h.html#a8bec34fdc01ac38ec0c2d13112f28aa0"> 198</a></span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_XOSC1_RUNSTDBY (0)</span></div>
<div class="line"><a name="l00199"></a><span class="lineno"> 199</span>&#160; </div>
<div class="line"><a name="l00207"></a><span class="lineno"><a class="line" href="conf__core_8h.html#aaf561ace0fee1e373536a251ce8a9726"> 207</a></span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_XOSC1_ONDEMAND (0)</span></div>
<div class="line"><a name="l00208"></a><span class="lineno"> 208</span>&#160; </div>
<div class="line"><a name="l00216"></a><span class="lineno"><a class="line" href="conf__core_8h.html#a985ebd23986d9411d3602040e33bb405"> 216</a></span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_XOSC1_LOWBUFGAIN (0)</span></div>
<div class="line"><a name="l00217"></a><span class="lineno"> 217</span>&#160; </div>
<div class="line"><a name="l00224"></a><span class="lineno"><a class="line" href="conf__core_8h.html#a3a42de5c6251540e7b8c000974acfc62"> 224</a></span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_XOSC1_ENALC (0)</span></div>
<div class="line"><a name="l00225"></a><span class="lineno"> 225</span>&#160; </div>
<div class="line"><a name="l00232"></a><span class="lineno"><a class="line" href="conf__core_8h.html#a924214b0f469bde71ff28fe5544466db"> 232</a></span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_XOSC1_CFDEN (0)</span></div>
<div class="line"><a name="l00233"></a><span class="lineno"> 233</span>&#160; </div>
<div class="line"><a name="l00241"></a><span class="lineno"><a class="line" href="conf__core_8h.html#a590b1e68a3f666bdea576a32f4e74ba0"> 241</a></span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_XOSC1_SWBEN (0)</span></div>
<div class="line"><a name="l00242"></a><span class="lineno"> 242</span>&#160; </div>
<div class="line"><a name="l00263"></a><span class="lineno"><a class="line" href="conf__core_8h.html#ae8d2fdac3b52964174863149986db625"> 263</a></span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_XOSC1_STARTUP_TIME (0x00)</span></div>
<div class="line"><a name="l00264"></a><span class="lineno"> 264</span>&#160; </div>
<div class="line"><a name="l00269"></a><span class="lineno"><a class="line" href="conf__core_8h.html#a3fc3ea49b9d78438e5a8c19a22849469"> 269</a></span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_XOSC1_FREQUENCY 12000000</span></div>
<div class="line"><a name="l00270"></a><span class="lineno"> 270</span>&#160; </div>
<div class="line"><a name="l00284"></a><span class="lineno"><a class="line" href="conf__core_8h.html#accf341cf268c0883a3d862b98667bc9c"> 284</a></span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_XOSC32K_ENABLE (1)</span></div>
<div class="line"><a name="l00285"></a><span class="lineno"> 285</span>&#160; </div>
<div class="line"><a name="l00293"></a><span class="lineno"><a class="line" href="conf__core_8h.html#a031a77340c697036538d218724837de1"> 293</a></span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_XOSC32K_CGM (0x01)</span></div>
<div class="line"><a name="l00294"></a><span class="lineno"> 294</span>&#160; </div>
<div class="line"><a name="l00306"></a><span class="lineno"><a class="line" href="conf__core_8h.html#a314b78ee48f1ecf6c40f4bad7ef63d9d"> 306</a></span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_XOSC32K_STARTUP_TIME CONF_CORE_CLK_XOSC32KCTRL_STARTUP_62592us</span></div>
<div class="line"><a name="l00307"></a><span class="lineno"> 307</span>&#160; </div>
<div class="line"><a name="l00308"></a><span class="lineno"> 308</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_4_ENABLE 0</span></div>
<div class="line"><a name="l00309"></a><span class="lineno"> 309</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_4_RUN_IN_STANDBY 0</span></div>
<div class="line"><a name="l00310"></a><span class="lineno"> 310</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_4_CLOCK_SOURCE GCLK_GENCTRL_SRC_XOSC0</span></div>
<div class="line"><a name="l00311"></a><span class="lineno"> 311</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_4_DIV_VAL 1</span></div>
<div class="line"><a name="l00312"></a><span class="lineno"> 312</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_4_DIVSEL 1</span></div>
<div class="line"><a name="l00313"></a><span class="lineno"> 313</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_4_OUTPUT_ENABLE 0</span></div>
<div class="line"><a name="l00314"></a><span class="lineno"> 314</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_4_OUTPUT_OFF_VALUE 0</span></div>
<div class="line"><a name="l00315"></a><span class="lineno"> 315</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_4_IDC 0</span></div>
<div class="line"><a name="l00316"></a><span class="lineno"> 316</span>&#160; </div>
<div class="line"><a name="l00317"></a><span class="lineno"> 317</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_5_ENABLE 0</span></div>
<div class="line"><a name="l00318"></a><span class="lineno"> 318</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_5_RUN_IN_STANDBY 0</span></div>
<div class="line"><a name="l00319"></a><span class="lineno"> 319</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_5_CLOCK_SOURCE GCLK_GENCTRL_SRC_XOSC0</span></div>
<div class="line"><a name="l00320"></a><span class="lineno"> 320</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_5_DIV_VAL 1</span></div>
<div class="line"><a name="l00321"></a><span class="lineno"> 321</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_5_DIVSEL 0</span></div>
<div class="line"><a name="l00322"></a><span class="lineno"> 322</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_5_OUTPUT_ENABLE 0</span></div>
<div class="line"><a name="l00323"></a><span class="lineno"> 323</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_5_OUTPUT_OFF_VALUE 0</span></div>
<div class="line"><a name="l00324"></a><span class="lineno"> 324</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_5_IDC 0</span></div>
<div class="line"><a name="l00325"></a><span class="lineno"> 325</span>&#160; </div>
<div class="line"><a name="l00326"></a><span class="lineno"> 326</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_6_ENABLE 0</span></div>
<div class="line"><a name="l00327"></a><span class="lineno"> 327</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_6_RUN_IN_STANDBY 0</span></div>
<div class="line"><a name="l00328"></a><span class="lineno"> 328</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_6_CLOCK_SOURCE GCLK_GENCTRL_SRC_XOSC0</span></div>
<div class="line"><a name="l00329"></a><span class="lineno"> 329</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_6_DIV_VAL 1</span></div>
<div class="line"><a name="l00330"></a><span class="lineno"> 330</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_6_DIVSEL 0</span></div>
<div class="line"><a name="l00331"></a><span class="lineno"> 331</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_6_OUTPUT_ENABLE 0</span></div>
<div class="line"><a name="l00332"></a><span class="lineno"> 332</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_6_OUTPUT_OFF_VALUE 0</span></div>
<div class="line"><a name="l00333"></a><span class="lineno"> 333</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_6_IDC 0</span></div>
<div class="line"><a name="l00334"></a><span class="lineno"> 334</span>&#160; </div>
<div class="line"><a name="l00335"></a><span class="lineno"> 335</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_7_ENABLE 0</span></div>
<div class="line"><a name="l00336"></a><span class="lineno"> 336</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_7_RUN_IN_STANDBY 0</span></div>
<div class="line"><a name="l00337"></a><span class="lineno"> 337</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_7_CLOCK_SOURCE GCLK_GENCTRL_SRC_XOSC0</span></div>
<div class="line"><a name="l00338"></a><span class="lineno"> 338</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_7_DIV_VAL 1</span></div>
<div class="line"><a name="l00339"></a><span class="lineno"> 339</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_7_DIVSEL 0</span></div>
<div class="line"><a name="l00340"></a><span class="lineno"> 340</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_7_OUTPUT_ENABLE 0</span></div>
<div class="line"><a name="l00341"></a><span class="lineno"> 341</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_7_OUTPUT_OFF_VALUE 0</span></div>
<div class="line"><a name="l00342"></a><span class="lineno"> 342</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_7_IDC 0</span></div>
<div class="line"><a name="l00343"></a><span class="lineno"> 343</span>&#160; </div>
<div class="line"><a name="l00344"></a><span class="lineno"> 344</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_8_ENABLE 0</span></div>
<div class="line"><a name="l00345"></a><span class="lineno"> 345</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_8_RUN_IN_STANDBY 0</span></div>
<div class="line"><a name="l00346"></a><span class="lineno"> 346</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_8_CLOCK_SOURCE GCLK_GENCTRL_SRC_XOSC0</span></div>
<div class="line"><a name="l00347"></a><span class="lineno"> 347</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_8_DIV_VAL 1</span></div>
<div class="line"><a name="l00348"></a><span class="lineno"> 348</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_8_DIVSEL 0</span></div>
<div class="line"><a name="l00349"></a><span class="lineno"> 349</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_8_OUTPUT_ENABLE 0</span></div>
<div class="line"><a name="l00350"></a><span class="lineno"> 350</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_8_OUTPUT_OFF_VALUE 0</span></div>
<div class="line"><a name="l00351"></a><span class="lineno"> 351</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_8_IDC 0</span></div>
<div class="line"><a name="l00352"></a><span class="lineno"> 352</span>&#160; </div>
<div class="line"><a name="l00353"></a><span class="lineno"> 353</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_9_ENABLE 0</span></div>
<div class="line"><a name="l00354"></a><span class="lineno"> 354</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_9_RUN_IN_STANDBY 0</span></div>
<div class="line"><a name="l00355"></a><span class="lineno"> 355</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_9_CLOCK_SOURCE GCLK_GENCTRL_SRC_XOSC0</span></div>
<div class="line"><a name="l00356"></a><span class="lineno"> 356</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_9_DIV_VAL 1</span></div>
<div class="line"><a name="l00357"></a><span class="lineno"> 357</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_9_DIVSEL 0</span></div>
<div class="line"><a name="l00358"></a><span class="lineno"> 358</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_9_OUTPUT_ENABLE 0</span></div>
<div class="line"><a name="l00359"></a><span class="lineno"> 359</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_9_OUTPUT_OFF_VALUE 0</span></div>
<div class="line"><a name="l00360"></a><span class="lineno"> 360</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_9_IDC 0</span></div>
<div class="line"><a name="l00314"></a><span class="lineno"><a class="line" href="conf__core_8h.html#a8d70a30b50febec035af6b982daac395"> 314</a></span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_XOSC32K_ONDEMAND (1)</span></div>
<div class="line"><a name="l00315"></a><span class="lineno"> 315</span>&#160; </div>
<div class="line"><a name="l00322"></a><span class="lineno"><a class="line" href="conf__core_8h.html#adc7a2f161e9e8e54388b1f290066247e"> 322</a></span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_XOSC32K_RUNSTDBY (0)</span></div>
<div class="line"><a name="l00323"></a><span class="lineno"> 323</span>&#160; </div>
<div class="line"><a name="l00329"></a><span class="lineno"><a class="line" href="conf__core_8h.html#a033f3571fb50a6ed02278d65ea84b45e"> 329</a></span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_XOSC32K_EN1K (0)</span></div>
<div class="line"><a name="l00330"></a><span class="lineno"> 330</span>&#160; </div>
<div class="line"><a name="l00336"></a><span class="lineno"><a class="line" href="conf__core_8h.html#ae9fbb8d05dc5808f510eae4e8a629826"> 336</a></span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_XOSC32K_EN32K (1)</span></div>
<div class="line"><a name="l00337"></a><span class="lineno"> 337</span>&#160; </div>
<div class="line"><a name="l00344"></a><span class="lineno"><a class="line" href="conf__core_8h.html#a6a65a6f4bf7e21dc2003b61a7045e24a"> 344</a></span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_XOSC32K_XTALEN (1)</span></div>
<div class="line"><a name="l00345"></a><span class="lineno"> 345</span>&#160; </div>
<div class="line"><a name="l00352"></a><span class="lineno"><a class="line" href="conf__core_8h.html#a79567f94a0f3ad2d628bcf5e1cff62d1"> 352</a></span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_XOSC32K_CFDPRESC (0)</span></div>
<div class="line"><a name="l00353"></a><span class="lineno"> 353</span>&#160; </div>
<div class="line"><a name="l00360"></a><span class="lineno"><a class="line" href="conf__core_8h.html#a668d68edf9a7ac05be5b9cda247225ad"> 360</a></span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_XOSC32K_CFDEN (0)</span></div>
<div class="line"><a name="l00361"></a><span class="lineno"> 361</span>&#160; </div>
<div class="line"><a name="l00362"></a><span class="lineno"> 362</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_10_ENABLE 0</span></div>
<div class="line"><a name="l00363"></a><span class="lineno"> 363</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_10_RUN_IN_STANDBY 0</span></div>
<div class="line"><a name="l00364"></a><span class="lineno"> 364</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_10_CLOCK_SOURCE GCLK_GENCTRL_SRC_XOSC0</span></div>
<div class="line"><a name="l00365"></a><span class="lineno"> 365</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_10_DIV_VAL 1</span></div>
<div class="line"><a name="l00366"></a><span class="lineno"> 366</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_10_DIVSEL 0</span></div>
<div class="line"><a name="l00367"></a><span class="lineno"> 367</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_10_OUTPUT_ENABLE 0</span></div>
<div class="line"><a name="l00368"></a><span class="lineno"> 368</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_10_OUTPUT_OFF_VALUE 0</span></div>
<div class="line"><a name="l00369"></a><span class="lineno"> 369</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_10_IDC 0</span></div>
<div class="line"><a name="l00370"></a><span class="lineno"> 370</span>&#160; </div>
<div class="line"><a name="l00371"></a><span class="lineno"> 371</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_11_ENABLE 0</span></div>
<div class="line"><a name="l00372"></a><span class="lineno"> 372</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_11_RUN_IN_STANDBY 0</span></div>
<div class="line"><a name="l00373"></a><span class="lineno"> 373</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_11_CLOCK_SOURCE GCLK_GENCTRL_SRC_XOSC0</span></div>
<div class="line"><a name="l00374"></a><span class="lineno"> 374</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_11_DIV_VAL 1</span></div>
<div class="line"><a name="l00375"></a><span class="lineno"> 375</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_11_DIVSEL 0</span></div>
<div class="line"><a name="l00376"></a><span class="lineno"> 376</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_11_OUTPUT_ENABLE 0</span></div>
<div class="line"><a name="l00377"></a><span class="lineno"> 377</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_11_OUTPUT_OFF_VALUE 0</span></div>
<div class="line"><a name="l00378"></a><span class="lineno"> 378</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_11_IDC 0</span></div>
<div class="line"><a name="l00379"></a><span class="lineno"> 379</span>&#160; </div>
<div class="line"><a name="l00380"></a><span class="lineno"> 380</span>&#160; </div>
<div class="line"><a name="l00381"></a><span class="lineno"> 381</span>&#160; </div>
<div class="line"><a name="l00382"></a><span class="lineno"> 382</span>&#160;<span class="preprocessor">#endif</span></div>
<div class="line"><a name="l00368"></a><span class="lineno"><a class="line" href="conf__core_8h.html#ac6e671eee4ca4aeb9fcbb87d52b457b5"> 368</a></span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_XOSC32K_SWBACK (0)</span></div>
<div class="line"><a name="l00369"></a><span class="lineno"> 369</span>&#160; </div>
<div class="line"><a name="l00376"></a><span class="lineno"><a class="line" href="conf__core_8h.html#a42b0270d2f3c0f51c4b3d2b8ac397fda"> 376</a></span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_XOSC32K_WRTLOCK (0)</span></div>
<div class="line"><a name="l00377"></a><span class="lineno"> 377</span>&#160; </div>
<div class="line"><a name="l00390"></a><span class="lineno"><a class="line" href="conf__core_8h.html#a03160c4c7871685bbde0e96f02825842"> 390</a></span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_DFLL_ENABLE (1)</span></div>
<div class="line"><a name="l00391"></a><span class="lineno"> 391</span>&#160; </div>
<div class="line"><a name="l00398"></a><span class="lineno"><a class="line" href="conf__core_8h.html#a55515b150245a993779a0d5f417cc828"> 398</a></span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_DFLL_ONDEMAND (0)</span></div>
<div class="line"><a name="l00399"></a><span class="lineno"> 399</span>&#160; </div>
<div class="line"><a name="l00406"></a><span class="lineno"><a class="line" href="conf__core_8h.html#ab6b320dcf67ec88f534adcbf77e2ce7b"> 406</a></span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_DFLL_RUNSTDBY (0)</span></div>
<div class="line"><a name="l00407"></a><span class="lineno"> 407</span>&#160; </div>
<div class="line"><a name="l00414"></a><span class="lineno"><a class="line" href="conf__core_8h.html#a1f088d6654bb907ff388ced455b2dbb2"> 414</a></span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_DFLL_WAITLOCK (0)</span></div>
<div class="line"><a name="l00415"></a><span class="lineno"> 415</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_DFLL_BPLKC (0)</span></div>
<div class="line"><a name="l00416"></a><span class="lineno"> 416</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_DFLL_QLDIS (0)</span></div>
<div class="line"><a name="l00417"></a><span class="lineno"> 417</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_DFLL_CCDIS (1)</span></div>
<div class="line"><a name="l00418"></a><span class="lineno"> 418</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_DFLL_USBCRM (1)</span></div>
<div class="line"><a name="l00419"></a><span class="lineno"> 419</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_DFLL_LLAW (0)</span></div>
<div class="line"><a name="l00420"></a><span class="lineno"> 420</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_DFLL_STABLE_FCALIB CONF_CORE_CLK_DFLLCTRL_STABLE_FCALIB_NOT_FIXED</span></div>
<div class="line"><a name="l00421"></a><span class="lineno"> 421</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_DFLL_MODE 0x01</span></div>
<div class="line"><a name="l00422"></a><span class="lineno"> 422</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_DFLL_DIFF_VAL 0</span></div>
<div class="line"><a name="l00423"></a><span class="lineno"> 423</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_DFLL_COARSE_VAL (0x1f / 4)</span></div>
<div class="line"><a name="l00424"></a><span class="lineno"> 424</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_DFLL_FINE_VAL 128</span></div>
<div class="line"><a name="l00425"></a><span class="lineno"> 425</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_DFLL_CSTEP_VAL 1</span></div>
<div class="line"><a name="l00426"></a><span class="lineno"> 426</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_DFLL_FSTEP_VAL 1</span></div>
<div class="line"><a name="l00427"></a><span class="lineno"> 427</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_DFLL_MUL_VAL (48000000)</span></div>
<div class="line"><a name="l00428"></a><span class="lineno"> 428</span>&#160; </div>
<div class="line"><a name="l00444"></a><span class="lineno"><a class="line" href="conf__core_8h.html#a0d8e56832f3d1f24b98173e3a3aa0046"> 444</a></span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_DFLL_GCLK_SRC 3</span></div>
<div class="line"><a name="l00445"></a><span class="lineno"> 445</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_DFLL_OVERWRITE_CAL 0</span></div>
<div class="line"><a name="l00446"></a><span class="lineno"> 446</span>&#160; </div>
<div class="line"><a name="l00453"></a><span class="lineno"> 453</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_DPLL0_ENABLE (1)</span></div>
<div class="line"><a name="l00454"></a><span class="lineno"> 454</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_DPLL0_ONDEMAND (0)</span></div>
<div class="line"><a name="l00455"></a><span class="lineno"> 455</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_DPLL0_RUNSTDBY (0)</span></div>
<div class="line"><a name="l00456"></a><span class="lineno"> 456</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_DPLL0_LDRFRAC_VAL 0</span></div>
<div class="line"><a name="l00457"></a><span class="lineno"> 457</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_DPLL0_LDR_VAL (119)</span></div>
<div class="line"><a name="l00458"></a><span class="lineno"> 458</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_DPLL0_DIV_VAL (5)</span></div>
<div class="line"><a name="l00459"></a><span class="lineno"> 459</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_DPLL0_DCOEN 0</span></div>
<div class="line"><a name="l00460"></a><span class="lineno"> 460</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_DPLL0_DCOFILTER CONF_CORE_CLK_DPLLCTRL_DCOFILTER_3210KHZ</span></div>
<div class="line"><a name="l00461"></a><span class="lineno"> 461</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_DPLL0_LBYPASS 1</span></div>
<div class="line"><a name="l00462"></a><span class="lineno"> 462</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_DPLL0_LTIME 0</span></div>
<div class="line"><a name="l00463"></a><span class="lineno"> 463</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_DPLL0_WUF 0</span></div>
<div class="line"><a name="l00464"></a><span class="lineno"> 464</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_DPLL0_GCLK_SRC GCLK_GENCTRL_SRC_XOSC0</span></div>
<div class="line"><a name="l00465"></a><span class="lineno"> 465</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_DPLL0_REFCLK CONF_CORE_CLK_DPLLCTRL_REFCLK_XOSC0</span></div>
<div class="line"><a name="l00466"></a><span class="lineno"> 466</span>&#160; </div>
<div class="line"><a name="l00490"></a><span class="lineno"><a class="line" href="conf__core_8h.html#a5cd9abca6f486eaebb6ddd236960b01a"> 490</a></span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_DPLL0_FILTER 0x0</span></div>
<div class="line"><a name="l00491"></a><span class="lineno"> 491</span>&#160; </div>
<div class="line"><a name="l00498"></a><span class="lineno"> 498</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_DPLL1_ENABLE (0)</span></div>
<div class="line"><a name="l00499"></a><span class="lineno"> 499</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_DPLL1_ONDEMAND (0)</span></div>
<div class="line"><a name="l00500"></a><span class="lineno"> 500</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_DPLL1_RUNSTDBY (0)</span></div>
<div class="line"><a name="l00501"></a><span class="lineno"> 501</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_DPLL1_LDRFRAC_VAL 0</span></div>
<div class="line"><a name="l00502"></a><span class="lineno"> 502</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_DPLL1_LDR_VAL (0)</span></div>
<div class="line"><a name="l00503"></a><span class="lineno"> 503</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_DPLL1_DIV_VAL (0)</span></div>
<div class="line"><a name="l00504"></a><span class="lineno"> 504</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_DPLL1_DCOEN 0</span></div>
<div class="line"><a name="l00505"></a><span class="lineno"> 505</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_DPLL1_DCOFILTER CONF_CORE_CLK_DPLLCTRL_DCOFILTER_3210KHZ</span></div>
<div class="line"><a name="l00506"></a><span class="lineno"> 506</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_DPLL1_LBYPASS 0</span></div>
<div class="line"><a name="l00507"></a><span class="lineno"> 507</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_DPLL1_LTIME 0</span></div>
<div class="line"><a name="l00508"></a><span class="lineno"> 508</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_DPLL1_WUF 0</span></div>
<div class="line"><a name="l00509"></a><span class="lineno"> 509</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_DPLL1_GCLK_SRC GCLK_GENCTRL_SRC_XOSC0</span></div>
<div class="line"><a name="l00510"></a><span class="lineno"> 510</span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_DPLL1_REFCLK CONF_CORE_CLK_DPLLCTRL_REFCLK_XOSC0</span></div>
<div class="line"><a name="l00511"></a><span class="lineno"> 511</span>&#160; </div>
<div class="line"><a name="l00535"></a><span class="lineno"><a class="line" href="conf__core_8h.html#a9de3ab7eb7e3c001d6aa7040f6311f10"> 535</a></span>&#160;<span class="preprocessor">#define CONF_CORE_CLK_DPLL1_FILTER 0x0</span></div>
<div class="line"><a name="l00536"></a><span class="lineno"> 536</span>&#160; </div>
<div class="line"><a name="l00539"></a><span class="lineno"> 539</span>&#160;<span class="comment">// GCLK Generators Config</span></div>
<div class="line"><a name="l00540"></a><span class="lineno"> 540</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_0_ENABLE 1</span></div>
<div class="line"><a name="l00541"></a><span class="lineno"> 541</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_0_RUN_IN_STANDBY 1</span></div>
<div class="line"><a name="l00542"></a><span class="lineno"> 542</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_0_CLOCK_SOURCE GCLK_GENCTRL_SRC_XOSC0</span></div>
<div class="line"><a name="l00543"></a><span class="lineno"> 543</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_0_DIV_VAL 1</span></div>
<div class="line"><a name="l00544"></a><span class="lineno"> 544</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_0_DIVSEL 0</span></div>
<div class="line"><a name="l00545"></a><span class="lineno"> 545</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_0_OUTPUT_ENABLE 1</span></div>
<div class="line"><a name="l00546"></a><span class="lineno"> 546</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_0_OUTPUT_OFF_VALUE 1</span></div>
<div class="line"><a name="l00547"></a><span class="lineno"> 547</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_0_IDC 1</span></div>
<div class="line"><a name="l00548"></a><span class="lineno"> 548</span>&#160; </div>
<div class="line"><a name="l00549"></a><span class="lineno"> 549</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_1_ENABLE 0</span></div>
<div class="line"><a name="l00550"></a><span class="lineno"> 550</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_1_RUN_IN_STANDBY 0</span></div>
<div class="line"><a name="l00551"></a><span class="lineno"> 551</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_1_CLOCK_SOURCE GCLK_GENCTRL_SRC_XOSC0</span></div>
<div class="line"><a name="l00552"></a><span class="lineno"> 552</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_1_DIV_VAL 1</span></div>
<div class="line"><a name="l00553"></a><span class="lineno"> 553</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_1_DIVSEL 0</span></div>
<div class="line"><a name="l00554"></a><span class="lineno"> 554</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_1_OUTPUT_ENABLE 0</span></div>
<div class="line"><a name="l00555"></a><span class="lineno"> 555</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_1_OUTPUT_OFF_VALUE 0</span></div>
<div class="line"><a name="l00556"></a><span class="lineno"> 556</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_1_IDC 0</span></div>
<div class="line"><a name="l00557"></a><span class="lineno"> 557</span>&#160; </div>
<div class="line"><a name="l00558"></a><span class="lineno"> 558</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_2_ENABLE 0</span></div>
<div class="line"><a name="l00559"></a><span class="lineno"> 559</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_2_RUN_IN_STANDBY 0</span></div>
<div class="line"><a name="l00560"></a><span class="lineno"> 560</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_2_CLOCK_SOURCE GCLK_GENCTRL_SRC_XOSC0</span></div>
<div class="line"><a name="l00561"></a><span class="lineno"> 561</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_2_DIV_VAL 1</span></div>
<div class="line"><a name="l00562"></a><span class="lineno"> 562</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_2_DIVSEL 0</span></div>
<div class="line"><a name="l00563"></a><span class="lineno"> 563</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_2_OUTPUT_ENABLE 0</span></div>
<div class="line"><a name="l00564"></a><span class="lineno"> 564</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_2_OUTPUT_OFF_VALUE 0</span></div>
<div class="line"><a name="l00565"></a><span class="lineno"> 565</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_2_IDC 0</span></div>
<div class="line"><a name="l00566"></a><span class="lineno"> 566</span>&#160; </div>
<div class="line"><a name="l00567"></a><span class="lineno"> 567</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_3_ENABLE 1</span></div>
<div class="line"><a name="l00568"></a><span class="lineno"> 568</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_3_RUN_IN_STANDBY 0</span></div>
<div class="line"><a name="l00569"></a><span class="lineno"> 569</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_3_CLOCK_SOURCE GCLK_GENCTRL_SRC_XOSC32K</span></div>
<div class="line"><a name="l00570"></a><span class="lineno"> 570</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_3_DIV_VAL 1</span></div>
<div class="line"><a name="l00571"></a><span class="lineno"> 571</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_3_DIVSEL 0</span></div>
<div class="line"><a name="l00572"></a><span class="lineno"> 572</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_3_OUTPUT_ENABLE 0</span></div>
<div class="line"><a name="l00573"></a><span class="lineno"> 573</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_3_OUTPUT_OFF_VALUE 0</span></div>
<div class="line"><a name="l00574"></a><span class="lineno"> 574</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_3_IDC 0</span></div>
<div class="line"><a name="l00575"></a><span class="lineno"> 575</span>&#160; </div>
<div class="line"><a name="l00576"></a><span class="lineno"> 576</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_4_ENABLE 0</span></div>
<div class="line"><a name="l00577"></a><span class="lineno"> 577</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_4_RUN_IN_STANDBY 0</span></div>
<div class="line"><a name="l00578"></a><span class="lineno"> 578</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_4_CLOCK_SOURCE GCLK_GENCTRL_SRC_XOSC0</span></div>
<div class="line"><a name="l00579"></a><span class="lineno"> 579</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_4_DIV_VAL 1</span></div>
<div class="line"><a name="l00580"></a><span class="lineno"> 580</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_4_DIVSEL 1</span></div>
<div class="line"><a name="l00581"></a><span class="lineno"> 581</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_4_OUTPUT_ENABLE 0</span></div>
<div class="line"><a name="l00582"></a><span class="lineno"> 582</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_4_OUTPUT_OFF_VALUE 0</span></div>
<div class="line"><a name="l00583"></a><span class="lineno"> 583</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_4_IDC 0</span></div>
<div class="line"><a name="l00584"></a><span class="lineno"> 584</span>&#160; </div>
<div class="line"><a name="l00585"></a><span class="lineno"> 585</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_5_ENABLE 0</span></div>
<div class="line"><a name="l00586"></a><span class="lineno"> 586</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_5_RUN_IN_STANDBY 0</span></div>
<div class="line"><a name="l00587"></a><span class="lineno"> 587</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_5_CLOCK_SOURCE GCLK_GENCTRL_SRC_XOSC0</span></div>
<div class="line"><a name="l00588"></a><span class="lineno"> 588</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_5_DIV_VAL 1</span></div>
<div class="line"><a name="l00589"></a><span class="lineno"> 589</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_5_DIVSEL 0</span></div>
<div class="line"><a name="l00590"></a><span class="lineno"> 590</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_5_OUTPUT_ENABLE 0</span></div>
<div class="line"><a name="l00591"></a><span class="lineno"> 591</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_5_OUTPUT_OFF_VALUE 0</span></div>
<div class="line"><a name="l00592"></a><span class="lineno"> 592</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_5_IDC 0</span></div>
<div class="line"><a name="l00593"></a><span class="lineno"> 593</span>&#160; </div>
<div class="line"><a name="l00594"></a><span class="lineno"> 594</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_6_ENABLE 0</span></div>
<div class="line"><a name="l00595"></a><span class="lineno"> 595</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_6_RUN_IN_STANDBY 0</span></div>
<div class="line"><a name="l00596"></a><span class="lineno"> 596</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_6_CLOCK_SOURCE GCLK_GENCTRL_SRC_XOSC0</span></div>
<div class="line"><a name="l00597"></a><span class="lineno"> 597</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_6_DIV_VAL 1</span></div>
<div class="line"><a name="l00598"></a><span class="lineno"> 598</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_6_DIVSEL 0</span></div>
<div class="line"><a name="l00599"></a><span class="lineno"> 599</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_6_OUTPUT_ENABLE 0</span></div>
<div class="line"><a name="l00600"></a><span class="lineno"> 600</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_6_OUTPUT_OFF_VALUE 0</span></div>
<div class="line"><a name="l00601"></a><span class="lineno"> 601</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_6_IDC 0</span></div>
<div class="line"><a name="l00602"></a><span class="lineno"> 602</span>&#160; </div>
<div class="line"><a name="l00603"></a><span class="lineno"> 603</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_7_ENABLE 0</span></div>
<div class="line"><a name="l00604"></a><span class="lineno"> 604</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_7_RUN_IN_STANDBY 0</span></div>
<div class="line"><a name="l00605"></a><span class="lineno"> 605</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_7_CLOCK_SOURCE GCLK_GENCTRL_SRC_XOSC0</span></div>
<div class="line"><a name="l00606"></a><span class="lineno"> 606</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_7_DIV_VAL 1</span></div>
<div class="line"><a name="l00607"></a><span class="lineno"> 607</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_7_DIVSEL 0</span></div>
<div class="line"><a name="l00608"></a><span class="lineno"> 608</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_7_OUTPUT_ENABLE 0</span></div>
<div class="line"><a name="l00609"></a><span class="lineno"> 609</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_7_OUTPUT_OFF_VALUE 0</span></div>
<div class="line"><a name="l00610"></a><span class="lineno"> 610</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_7_IDC 0</span></div>
<div class="line"><a name="l00611"></a><span class="lineno"> 611</span>&#160; </div>
<div class="line"><a name="l00612"></a><span class="lineno"> 612</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_8_ENABLE 0</span></div>
<div class="line"><a name="l00613"></a><span class="lineno"> 613</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_8_RUN_IN_STANDBY 0</span></div>
<div class="line"><a name="l00614"></a><span class="lineno"> 614</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_8_CLOCK_SOURCE GCLK_GENCTRL_SRC_XOSC0</span></div>
<div class="line"><a name="l00615"></a><span class="lineno"> 615</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_8_DIV_VAL 1</span></div>
<div class="line"><a name="l00616"></a><span class="lineno"> 616</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_8_DIVSEL 0</span></div>
<div class="line"><a name="l00617"></a><span class="lineno"> 617</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_8_OUTPUT_ENABLE 0</span></div>
<div class="line"><a name="l00618"></a><span class="lineno"> 618</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_8_OUTPUT_OFF_VALUE 0</span></div>
<div class="line"><a name="l00619"></a><span class="lineno"> 619</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_8_IDC 0</span></div>
<div class="line"><a name="l00620"></a><span class="lineno"> 620</span>&#160; </div>
<div class="line"><a name="l00621"></a><span class="lineno"> 621</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_9_ENABLE 0</span></div>
<div class="line"><a name="l00622"></a><span class="lineno"> 622</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_9_RUN_IN_STANDBY 0</span></div>
<div class="line"><a name="l00623"></a><span class="lineno"> 623</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_9_CLOCK_SOURCE GCLK_GENCTRL_SRC_XOSC0</span></div>
<div class="line"><a name="l00624"></a><span class="lineno"> 624</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_9_DIV_VAL 1</span></div>
<div class="line"><a name="l00625"></a><span class="lineno"> 625</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_9_DIVSEL 0</span></div>
<div class="line"><a name="l00626"></a><span class="lineno"> 626</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_9_OUTPUT_ENABLE 0</span></div>
<div class="line"><a name="l00627"></a><span class="lineno"> 627</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_9_OUTPUT_OFF_VALUE 0</span></div>
<div class="line"><a name="l00628"></a><span class="lineno"> 628</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_9_IDC 0</span></div>
<div class="line"><a name="l00629"></a><span class="lineno"> 629</span>&#160; </div>
<div class="line"><a name="l00630"></a><span class="lineno"> 630</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_10_ENABLE 0</span></div>
<div class="line"><a name="l00631"></a><span class="lineno"> 631</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_10_RUN_IN_STANDBY 0</span></div>
<div class="line"><a name="l00632"></a><span class="lineno"> 632</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_10_CLOCK_SOURCE GCLK_GENCTRL_SRC_XOSC0</span></div>
<div class="line"><a name="l00633"></a><span class="lineno"> 633</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_10_DIV_VAL 1</span></div>
<div class="line"><a name="l00634"></a><span class="lineno"> 634</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_10_DIVSEL 0</span></div>
<div class="line"><a name="l00635"></a><span class="lineno"> 635</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_10_OUTPUT_ENABLE 0</span></div>
<div class="line"><a name="l00636"></a><span class="lineno"> 636</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_10_OUTPUT_OFF_VALUE 0</span></div>
<div class="line"><a name="l00637"></a><span class="lineno"> 637</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_10_IDC 0</span></div>
<div class="line"><a name="l00638"></a><span class="lineno"> 638</span>&#160; </div>
<div class="line"><a name="l00639"></a><span class="lineno"> 639</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_11_ENABLE 0</span></div>
<div class="line"><a name="l00640"></a><span class="lineno"> 640</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_11_RUN_IN_STANDBY 0</span></div>
<div class="line"><a name="l00641"></a><span class="lineno"> 641</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_11_CLOCK_SOURCE GCLK_GENCTRL_SRC_XOSC0</span></div>
<div class="line"><a name="l00642"></a><span class="lineno"> 642</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_11_DIV_VAL 1</span></div>
<div class="line"><a name="l00643"></a><span class="lineno"> 643</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_11_DIVSEL 0</span></div>
<div class="line"><a name="l00644"></a><span class="lineno"> 644</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_11_OUTPUT_ENABLE 0</span></div>
<div class="line"><a name="l00645"></a><span class="lineno"> 645</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_11_OUTPUT_OFF_VALUE 0</span></div>
<div class="line"><a name="l00646"></a><span class="lineno"> 646</span>&#160;<span class="preprocessor">#define CONF_CORE_GCLK_11_IDC 0</span></div>
<div class="line"><a name="l00647"></a><span class="lineno"> 647</span>&#160; </div>
<div class="line"><a name="l00648"></a><span class="lineno"> 648</span>&#160; </div>
<div class="line"><a name="l00649"></a><span class="lineno"> 649</span>&#160; </div>
<div class="line"><a name="l00650"></a><span class="lineno"> 650</span>&#160;<span class="preprocessor">#endif</span></div>
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161
test/same54p20a_test/doc/html/globals_c.html
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@ -2693,10 +2693,10 @@ $(function() {
: <a class="el" href="can_8h.html#aaab04fd1d52c69c14da84e4ce24fdac1">can.h</a>
</li>
<li>CCL
: <a class="el" href="same54n19a_8h.html#a97cc076f2f5a6f58fb8e221f440cc699">same54n19a.h</a>
, <a class="el" href="same54p19a_8h.html#a97cc076f2f5a6f58fb8e221f440cc699">same54p19a.h</a>
, <a class="el" href="same54n20a_8h.html#a97cc076f2f5a6f58fb8e221f440cc699">same54n20a.h</a>
: <a class="el" href="same54n20a_8h.html#a97cc076f2f5a6f58fb8e221f440cc699">same54n20a.h</a>
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, <a class="el" href="same54n19a_8h.html#a97cc076f2f5a6f58fb8e221f440cc699">same54n19a.h</a>
</li>
<li>CCL_CTRL_ENABLE_Pos
: <a class="el" href="component_2ccl_8h.html#ab7d01a15f8a8b66256c97685bf99fbdb">ccl.h</a>
@ -2717,16 +2717,16 @@ $(function() {
: <a class="el" href="component_2ccl_8h.html#ad7e603a55fe052e0c0a8cc5089e3d268">ccl.h</a>
</li>
<li>CCL_INST_NUM
: <a class="el" href="same54n19a_8h.html#aecb5ddd2712e1386e4f7052615ddf4aa">same54n19a.h</a>
, <a class="el" href="same54p20a_8h.html#aecb5ddd2712e1386e4f7052615ddf4aa">same54p20a.h</a>
: <a class="el" href="same54p20a_8h.html#aecb5ddd2712e1386e4f7052615ddf4aa">same54p20a.h</a>
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</li>
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: <a class="el" href="same54p20a_8h.html#ab8fb16d09c7b2e66c57f70a34ee90a8f">same54p20a.h</a>
, <a class="el" href="same54n19a_8h.html#ab8fb16d09c7b2e66c57f70a34ee90a8f">same54n19a.h</a>
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<li>CCL_LUTCTRL_EDGESEL_Pos
: <a class="el" href="component_2ccl_8h.html#ab20c6c3c219abf3c1f952d47e94c7cae">ccl.h</a>
@ -2894,16 +2894,16 @@ $(function() {
: <a class="el" href="component_2ccl_8h.html#a190ccdf8b60ec2ab4a231060bcafa23d">ccl.h</a>
</li>
<li>CMCC
: <a class="el" href="same54n20a_8h.html#af68d6c12c7cc42263ca0716ab41e0b9c">same54n20a.h</a>
, <a class="el" href="same54p19a_8h.html#af68d6c12c7cc42263ca0716ab41e0b9c">same54p19a.h</a>
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</li>
<li>CMCC_AHB
: <a class="el" href="same54n20a_8h.html#acd17c9b305224e21918249647d61133e">same54n20a.h</a>
, <a class="el" href="same54n19a_8h.html#acd17c9b305224e21918249647d61133e">same54n19a.h</a>
, <a class="el" href="same54p20a_8h.html#acd17c9b305224e21918249647d61133e">same54p20a.h</a>
: <a class="el" href="same54p20a_8h.html#acd17c9b305224e21918249647d61133e">same54p20a.h</a>
, <a class="el" href="same54p19a_8h.html#acd17c9b305224e21918249647d61133e">same54p19a.h</a>
, <a class="el" href="same54n19a_8h.html#acd17c9b305224e21918249647d61133e">same54n19a.h</a>
, <a class="el" href="same54n20a_8h.html#acd17c9b305224e21918249647d61133e">same54n20a.h</a>
</li>
<li>CMCC_CFG_CSIZESW_CONF_CSIZE_16KB_Val
: <a class="el" href="component_2cmcc_8h.html#a4e3a8c639977ce43caab50557ba7c87d">cmcc.h</a>
@ -2957,10 +2957,10 @@ $(function() {
: <a class="el" href="component_2cmcc_8h.html#a23e8a4d94f9cffe75f8091024550a7bf">cmcc.h</a>
</li>
<li>CMCC_DATARAM_ADDR
: <a class="el" href="same54p19a_8h.html#ab2557b0f4e6472677c3a905b61c5461c">same54p19a.h</a>
, <a class="el" href="same54p20a_8h.html#ab2557b0f4e6472677c3a905b61c5461c">same54p20a.h</a>
: <a class="el" href="same54n19a_8h.html#ab2557b0f4e6472677c3a905b61c5461c">same54n19a.h</a>
, <a class="el" href="same54n20a_8h.html#ab2557b0f4e6472677c3a905b61c5461c">same54n20a.h</a>
, <a class="el" href="same54n19a_8h.html#ab2557b0f4e6472677c3a905b61c5461c">same54n19a.h</a>
, <a class="el" href="same54p20a_8h.html#ab2557b0f4e6472677c3a905b61c5461c">same54p20a.h</a>
, <a class="el" href="same54p19a_8h.html#ab2557b0f4e6472677c3a905b61c5461c">same54p19a.h</a>
</li>
<li>CMCC_DATARAM_SIZE
: <a class="el" href="same54n19a_8h.html#a1c4ba597b0b697e59b03c6c518b14f1a">same54n19a.h</a>
@ -2969,15 +2969,15 @@ $(function() {
, <a class="el" href="same54n20a_8h.html#a1c4ba597b0b697e59b03c6c518b14f1a">same54n20a.h</a>
</li>
<li>CMCC_INST_NUM
: <a class="el" href="same54p20a_8h.html#ac2ae29936d5d738ad2d7f9d8675cf5e1">same54p20a.h</a>
: <a class="el" href="same54n19a_8h.html#ac2ae29936d5d738ad2d7f9d8675cf5e1">same54n19a.h</a>
, <a class="el" href="same54p19a_8h.html#ac2ae29936d5d738ad2d7f9d8675cf5e1">same54p19a.h</a>
, <a class="el" href="same54p20a_8h.html#ac2ae29936d5d738ad2d7f9d8675cf5e1">same54p20a.h</a>
, <a class="el" href="same54n20a_8h.html#ac2ae29936d5d738ad2d7f9d8675cf5e1">same54n20a.h</a>
, <a class="el" href="same54n19a_8h.html#ac2ae29936d5d738ad2d7f9d8675cf5e1">same54n19a.h</a>
</li>
<li>CMCC_INSTS
: <a class="el" href="same54p19a_8h.html#aa98cb2974a20471b5c9433bbc10ae183">same54p19a.h</a>
: <a class="el" href="same54n19a_8h.html#aa98cb2974a20471b5c9433bbc10ae183">same54n19a.h</a>
, <a class="el" href="same54p19a_8h.html#aa98cb2974a20471b5c9433bbc10ae183">same54p19a.h</a>
, <a class="el" href="same54p20a_8h.html#aa98cb2974a20471b5c9433bbc10ae183">same54p20a.h</a>
, <a class="el" href="same54n19a_8h.html#aa98cb2974a20471b5c9433bbc10ae183">same54n19a.h</a>
, <a class="el" href="same54n20a_8h.html#aa98cb2974a20471b5c9433bbc10ae183">same54n20a.h</a>
</li>
<li>CMCC_LCKWAY_LCKWAY_Pos
@ -3102,14 +3102,14 @@ $(function() {
</li>
<li>CMCC_TAGRAM_ADDR
: <a class="el" href="same54p19a_8h.html#afef03c63b74f524f76f3778a16120481">same54p19a.h</a>
, <a class="el" href="same54p20a_8h.html#afef03c63b74f524f76f3778a16120481">same54p20a.h</a>
, <a class="el" href="same54n19a_8h.html#afef03c63b74f524f76f3778a16120481">same54n19a.h</a>
, <a class="el" href="same54n20a_8h.html#afef03c63b74f524f76f3778a16120481">same54n20a.h</a>
, <a class="el" href="same54p20a_8h.html#afef03c63b74f524f76f3778a16120481">same54p20a.h</a>
</li>
<li>CMCC_TAGRAM_SIZE
: <a class="el" href="same54p19a_8h.html#abfc17a8c4bad997b27d53d6a61bd93b9">same54p19a.h</a>
, <a class="el" href="same54p20a_8h.html#abfc17a8c4bad997b27d53d6a61bd93b9">same54p20a.h</a>
, <a class="el" href="same54n19a_8h.html#abfc17a8c4bad997b27d53d6a61bd93b9">same54n19a.h</a>
, <a class="el" href="same54p20a_8h.html#abfc17a8c4bad997b27d53d6a61bd93b9">same54p20a.h</a>
, <a class="el" href="same54n20a_8h.html#abfc17a8c4bad997b27d53d6a61bd93b9">same54n20a.h</a>
</li>
<li>CMCC_TYPE_CLSIZE_CLSIZE_128B_Val
@ -3189,15 +3189,15 @@ $(function() {
</li>
<li>CMCC_VALIDRAM_ADDR
: <a class="el" href="same54p20a_8h.html#aef97ab61968f56c6b8f19c44dc706f2d">same54p20a.h</a>
, <a class="el" href="same54n19a_8h.html#aef97ab61968f56c6b8f19c44dc706f2d">same54n19a.h</a>
, <a class="el" href="same54p19a_8h.html#aef97ab61968f56c6b8f19c44dc706f2d">same54p19a.h</a>
, <a class="el" href="same54n20a_8h.html#aef97ab61968f56c6b8f19c44dc706f2d">same54n20a.h</a>
, <a class="el" href="same54p19a_8h.html#aef97ab61968f56c6b8f19c44dc706f2d">same54p19a.h</a>
, <a class="el" href="same54n19a_8h.html#aef97ab61968f56c6b8f19c44dc706f2d">same54n19a.h</a>
</li>
<li>CMCC_VALIDRAM_SIZE
: <a class="el" href="same54n20a_8h.html#a767a65126e4ad0ba3e5a62d8ae140a3a">same54n20a.h</a>
, <a class="el" href="same54p20a_8h.html#a767a65126e4ad0ba3e5a62d8ae140a3a">same54p20a.h</a>
, <a class="el" href="same54p19a_8h.html#a767a65126e4ad0ba3e5a62d8ae140a3a">same54p19a.h</a>
: <a class="el" href="same54p19a_8h.html#a767a65126e4ad0ba3e5a62d8ae140a3a">same54p19a.h</a>
, <a class="el" href="same54n20a_8h.html#a767a65126e4ad0ba3e5a62d8ae140a3a">same54n20a.h</a>
, <a class="el" href="same54n19a_8h.html#a767a65126e4ad0ba3e5a62d8ae140a3a">same54n19a.h</a>
, <a class="el" href="same54p20a_8h.html#a767a65126e4ad0ba3e5a62d8ae140a3a">same54p20a.h</a>
</li>
<li>CONF_CORE_CLK_DFLL_ENABLE
: <a class="el" href="conf__core_8h.html#a03160c4c7871685bbde0e96f02825842">conf_core.h</a>
@ -3220,6 +3220,102 @@ $(function() {
<li>CONF_CORE_CLK_DPLL1_FILTER
: <a class="el" href="conf__core_8h.html#a9de3ab7eb7e3c001d6aa7040f6311f10">conf_core.h</a>
</li>
<li>CONF_CORE_CLK_XOSC0_CFDEN
: <a class="el" href="conf__core_8h.html#a17cd20bb954bc137251cf7fb63889151">conf_core.h</a>
</li>
<li>CONF_CORE_CLK_XOSC0_ENABLE
: <a class="el" href="conf__core_8h.html#a61559adc856ce1dcfa046e749af63bc3">conf_core.h</a>
</li>
<li>CONF_CORE_CLK_XOSC0_ENALC
: <a class="el" href="conf__core_8h.html#a2683d3721ab44a85e60cfff0d0cbf96e">conf_core.h</a>
</li>
<li>CONF_CORE_CLK_XOSC0_FREQUENCY
: <a class="el" href="conf__core_8h.html#af6ec0afa1da472db5f1def1d1923faad">conf_core.h</a>
</li>
<li>CONF_CORE_CLK_XOSC0_LOWBUFGAIN
: <a class="el" href="conf__core_8h.html#aeea7b0d3663bb6d5ccc3218017f9a05b">conf_core.h</a>
</li>
<li>CONF_CORE_CLK_XOSC0_ONDEMAND
: <a class="el" href="conf__core_8h.html#a5ffaa1551b7ffb8a342b2cc5fbc5950c">conf_core.h</a>
</li>
<li>CONF_CORE_CLK_XOSC0_RUNSTDBY
: <a class="el" href="conf__core_8h.html#afac0686157854cc021424410ded071f1">conf_core.h</a>
</li>
<li>CONF_CORE_CLK_XOSC0_STARTUP_TIME
: <a class="el" href="conf__core_8h.html#affc8201cf2340d2236ba9ca44a1e657c">conf_core.h</a>
</li>
<li>CONF_CORE_CLK_XOSC0_SWBEN
: <a class="el" href="conf__core_8h.html#abe235b3b13f253acb855d15c8f33c95a">conf_core.h</a>
</li>
<li>CONF_CORE_CLK_XOSC0_XTALEN
: <a class="el" href="conf__core_8h.html#ac2ca0e9037347eb69d53a0011f989910">conf_core.h</a>
</li>
<li>CONF_CORE_CLK_XOSC1_CFDEN
: <a class="el" href="conf__core_8h.html#a924214b0f469bde71ff28fe5544466db">conf_core.h</a>
</li>
<li>CONF_CORE_CLK_XOSC1_ENABLE
: <a class="el" href="conf__core_8h.html#aa54465cc56631333a22ae84ab66d5f3a">conf_core.h</a>
</li>
<li>CONF_CORE_CLK_XOSC1_ENALC
: <a class="el" href="conf__core_8h.html#a3a42de5c6251540e7b8c000974acfc62">conf_core.h</a>
</li>
<li>CONF_CORE_CLK_XOSC1_FREQUENCY
: <a class="el" href="conf__core_8h.html#a3fc3ea49b9d78438e5a8c19a22849469">conf_core.h</a>
</li>
<li>CONF_CORE_CLK_XOSC1_LOWBUFGAIN
: <a class="el" href="conf__core_8h.html#a985ebd23986d9411d3602040e33bb405">conf_core.h</a>
</li>
<li>CONF_CORE_CLK_XOSC1_ONDEMAND
: <a class="el" href="conf__core_8h.html#aaf561ace0fee1e373536a251ce8a9726">conf_core.h</a>
</li>
<li>CONF_CORE_CLK_XOSC1_RUNSTDBY
: <a class="el" href="conf__core_8h.html#a8bec34fdc01ac38ec0c2d13112f28aa0">conf_core.h</a>
</li>
<li>CONF_CORE_CLK_XOSC1_STARTUP_TIME
: <a class="el" href="conf__core_8h.html#ae8d2fdac3b52964174863149986db625">conf_core.h</a>
</li>
<li>CONF_CORE_CLK_XOSC1_SWBEN
: <a class="el" href="conf__core_8h.html#a590b1e68a3f666bdea576a32f4e74ba0">conf_core.h</a>
</li>
<li>CONF_CORE_CLK_XOSC1_XTALEN
: <a class="el" href="conf__core_8h.html#ae3f8741e2be4b37a46dfb49af2c2a09d">conf_core.h</a>
</li>
<li>CONF_CORE_CLK_XOSC32K_CFDEN
: <a class="el" href="conf__core_8h.html#a668d68edf9a7ac05be5b9cda247225ad">conf_core.h</a>
</li>
<li>CONF_CORE_CLK_XOSC32K_CFDPRESC
: <a class="el" href="conf__core_8h.html#a79567f94a0f3ad2d628bcf5e1cff62d1">conf_core.h</a>
</li>
<li>CONF_CORE_CLK_XOSC32K_CGM
: <a class="el" href="conf__core_8h.html#a031a77340c697036538d218724837de1">conf_core.h</a>
</li>
<li>CONF_CORE_CLK_XOSC32K_EN1K
: <a class="el" href="conf__core_8h.html#a033f3571fb50a6ed02278d65ea84b45e">conf_core.h</a>
</li>
<li>CONF_CORE_CLK_XOSC32K_EN32K
: <a class="el" href="conf__core_8h.html#ae9fbb8d05dc5808f510eae4e8a629826">conf_core.h</a>
</li>
<li>CONF_CORE_CLK_XOSC32K_ENABLE
: <a class="el" href="conf__core_8h.html#accf341cf268c0883a3d862b98667bc9c">conf_core.h</a>
</li>
<li>CONF_CORE_CLK_XOSC32K_ONDEMAND
: <a class="el" href="conf__core_8h.html#a8d70a30b50febec035af6b982daac395">conf_core.h</a>
</li>
<li>CONF_CORE_CLK_XOSC32K_RUNSTDBY
: <a class="el" href="conf__core_8h.html#adc7a2f161e9e8e54388b1f290066247e">conf_core.h</a>
</li>
<li>CONF_CORE_CLK_XOSC32K_STARTUP_TIME
: <a class="el" href="conf__core_8h.html#a314b78ee48f1ecf6c40f4bad7ef63d9d">conf_core.h</a>
</li>
<li>CONF_CORE_CLK_XOSC32K_SWBACK
: <a class="el" href="conf__core_8h.html#ac6e671eee4ca4aeb9fcbb87d52b457b5">conf_core.h</a>
</li>
<li>CONF_CORE_CLK_XOSC32K_WRTLOCK
: <a class="el" href="conf__core_8h.html#a42b0270d2f3c0f51c4b3d2b8ac397fda">conf_core.h</a>
</li>
<li>CONF_CORE_CLK_XOSC32K_XTALEN
: <a class="el" href="conf__core_8h.html#a6a65a6f4bf7e21dc2003b61a7045e24a">conf_core.h</a>
</li>
<li>CONF_CORE_CMCC_ENABLE
: <a class="el" href="conf__core_8h.html#a81edcdaa3908cc3d99a95047e4431405">conf_core.h</a>
</li>
@ -3232,6 +3328,15 @@ $(function() {
<li>CONF_CORE_MCLK_NVM_WAIT_STATE
: <a class="el" href="conf__core_8h.html#ab46aa120e454ecf957efa4bd97be5bdf">conf_core.h</a>
</li>
<li>CONF_CORE_PORT_EVCTRL_0_ENABLE
: <a class="el" href="conf__core_8h.html#a4e846249cdbec567989afa93b6653671">conf_core.h</a>
</li>
<li>CONF_CORE_PORT_EVCTRL_1_ENABLE
: <a class="el" href="conf__core_8h.html#ab1c71bf1f1249ce9046aca27329ae588">conf_core.h</a>
</li>
<li>CONF_CORE_PORT_EVCTRL_2_ENABLE
: <a class="el" href="conf__core_8h.html#a7971c1d952e35ecc50ae18de2b2c48ed">conf_core.h</a>
</li>
</ul>
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153
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@ -2681,10 +2681,10 @@ $(function() {
: <a class="el" href="can_8h.html#aaab04fd1d52c69c14da84e4ce24fdac1">can.h</a>
</li>
<li>CCL
: <a class="el" href="same54n19a_8h.html#a97cc076f2f5a6f58fb8e221f440cc699">same54n19a.h</a>
: <a class="el" href="same54n20a_8h.html#a97cc076f2f5a6f58fb8e221f440cc699">same54n20a.h</a>
, <a class="el" href="same54n19a_8h.html#a97cc076f2f5a6f58fb8e221f440cc699">same54n19a.h</a>
, <a class="el" href="same54p20a_8h.html#a97cc076f2f5a6f58fb8e221f440cc699">same54p20a.h</a>
, <a class="el" href="same54p19a_8h.html#a97cc076f2f5a6f58fb8e221f440cc699">same54p19a.h</a>
, <a class="el" href="same54n20a_8h.html#a97cc076f2f5a6f58fb8e221f440cc699">same54n20a.h</a>
</li>
<li>CCL_CTRL_ENABLE_Pos
: <a class="el" href="component_2ccl_8h.html#ab7d01a15f8a8b66256c97685bf99fbdb">ccl.h</a>
@ -2705,16 +2705,16 @@ $(function() {
: <a class="el" href="component_2ccl_8h.html#ad7e603a55fe052e0c0a8cc5089e3d268">ccl.h</a>
</li>
<li>CCL_INST_NUM
: <a class="el" href="same54n19a_8h.html#aecb5ddd2712e1386e4f7052615ddf4aa">same54n19a.h</a>
, <a class="el" href="same54p20a_8h.html#aecb5ddd2712e1386e4f7052615ddf4aa">same54p20a.h</a>
, <a class="el" href="same54n20a_8h.html#aecb5ddd2712e1386e4f7052615ddf4aa">same54n20a.h</a>
: <a class="el" href="same54n20a_8h.html#aecb5ddd2712e1386e4f7052615ddf4aa">same54n20a.h</a>
, <a class="el" href="same54p19a_8h.html#aecb5ddd2712e1386e4f7052615ddf4aa">same54p19a.h</a>
, <a class="el" href="same54p20a_8h.html#aecb5ddd2712e1386e4f7052615ddf4aa">same54p20a.h</a>
, <a class="el" href="same54n19a_8h.html#aecb5ddd2712e1386e4f7052615ddf4aa">same54n19a.h</a>
</li>
<li>CCL_INSTS
: <a class="el" href="same54p19a_8h.html#ab8fb16d09c7b2e66c57f70a34ee90a8f">same54p19a.h</a>
, <a class="el" href="same54n19a_8h.html#ab8fb16d09c7b2e66c57f70a34ee90a8f">same54n19a.h</a>
, <a class="el" href="same54p20a_8h.html#ab8fb16d09c7b2e66c57f70a34ee90a8f">same54p20a.h</a>
: <a class="el" href="same54p20a_8h.html#ab8fb16d09c7b2e66c57f70a34ee90a8f">same54p20a.h</a>
, <a class="el" href="same54n20a_8h.html#ab8fb16d09c7b2e66c57f70a34ee90a8f">same54n20a.h</a>
, <a class="el" href="same54p19a_8h.html#ab8fb16d09c7b2e66c57f70a34ee90a8f">same54p19a.h</a>
, <a class="el" href="same54n19a_8h.html#ab8fb16d09c7b2e66c57f70a34ee90a8f">same54n19a.h</a>
</li>
<li>CCL_LUTCTRL_EDGESEL_Pos
: <a class="el" href="component_2ccl_8h.html#ab20c6c3c219abf3c1f952d47e94c7cae">ccl.h</a>
@ -2945,28 +2945,28 @@ $(function() {
: <a class="el" href="component_2cmcc_8h.html#a23e8a4d94f9cffe75f8091024550a7bf">cmcc.h</a>
</li>
<li>CMCC_DATARAM_ADDR
: <a class="el" href="same54p19a_8h.html#ab2557b0f4e6472677c3a905b61c5461c">same54p19a.h</a>
, <a class="el" href="same54p20a_8h.html#ab2557b0f4e6472677c3a905b61c5461c">same54p20a.h</a>
: <a class="el" href="same54p20a_8h.html#ab2557b0f4e6472677c3a905b61c5461c">same54p20a.h</a>
, <a class="el" href="same54n19a_8h.html#ab2557b0f4e6472677c3a905b61c5461c">same54n19a.h</a>
, <a class="el" href="same54p19a_8h.html#ab2557b0f4e6472677c3a905b61c5461c">same54p19a.h</a>
, <a class="el" href="same54n20a_8h.html#ab2557b0f4e6472677c3a905b61c5461c">same54n20a.h</a>
</li>
<li>CMCC_DATARAM_SIZE
: <a class="el" href="same54p19a_8h.html#a1c4ba597b0b697e59b03c6c518b14f1a">same54p19a.h</a>
, <a class="el" href="same54n20a_8h.html#a1c4ba597b0b697e59b03c6c518b14f1a">same54n20a.h</a>
: <a class="el" href="same54n19a_8h.html#a1c4ba597b0b697e59b03c6c518b14f1a">same54n19a.h</a>
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, <a class="el" href="same54p19a_8h.html#aa98cb2974a20471b5c9433bbc10ae183">same54p19a.h</a>
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, <a class="el" href="same54n19a_8h.html#aa98cb2974a20471b5c9433bbc10ae183">same54n19a.h</a>
</li>
<li>CMCC_LCKWAY_LCKWAY_Pos
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@ -3089,10 +3089,10 @@ $(function() {
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, <a class="el" href="same54n20a_8h.html#afef03c63b74f524f76f3778a16120481">same54n20a.h</a>
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<li>CMCC_TAGRAM_SIZE
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<li>CMCC_VALIDRAM_ADDR
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, <a class="el" href="same54n19a_8h.html#aef97ab61968f56c6b8f19c44dc706f2d">same54n19a.h</a>
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<li>CMCC_VALIDRAM_SIZE
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: <a class="el" href="same54n20a_8h.html#a767a65126e4ad0ba3e5a62d8ae140a3a">same54n20a.h</a>
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</li>
<li>CONF_CORE_CLK_DFLL_ENABLE
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@ -3208,6 +3208,102 @@ $(function() {
<li>CONF_CORE_CLK_DPLL1_FILTER
: <a class="el" href="conf__core_8h.html#a9de3ab7eb7e3c001d6aa7040f6311f10">conf_core.h</a>
</li>
<li>CONF_CORE_CLK_XOSC0_CFDEN
: <a class="el" href="conf__core_8h.html#a17cd20bb954bc137251cf7fb63889151">conf_core.h</a>
</li>
<li>CONF_CORE_CLK_XOSC0_ENABLE
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</li>
<li>CONF_CORE_CLK_XOSC0_ENALC
: <a class="el" href="conf__core_8h.html#a2683d3721ab44a85e60cfff0d0cbf96e">conf_core.h</a>
</li>
<li>CONF_CORE_CLK_XOSC0_FREQUENCY
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</li>
<li>CONF_CORE_CLK_XOSC0_LOWBUFGAIN
: <a class="el" href="conf__core_8h.html#aeea7b0d3663bb6d5ccc3218017f9a05b">conf_core.h</a>
</li>
<li>CONF_CORE_CLK_XOSC0_ONDEMAND
: <a class="el" href="conf__core_8h.html#a5ffaa1551b7ffb8a342b2cc5fbc5950c">conf_core.h</a>
</li>
<li>CONF_CORE_CLK_XOSC0_RUNSTDBY
: <a class="el" href="conf__core_8h.html#afac0686157854cc021424410ded071f1">conf_core.h</a>
</li>
<li>CONF_CORE_CLK_XOSC0_STARTUP_TIME
: <a class="el" href="conf__core_8h.html#affc8201cf2340d2236ba9ca44a1e657c">conf_core.h</a>
</li>
<li>CONF_CORE_CLK_XOSC0_SWBEN
: <a class="el" href="conf__core_8h.html#abe235b3b13f253acb855d15c8f33c95a">conf_core.h</a>
</li>
<li>CONF_CORE_CLK_XOSC0_XTALEN
: <a class="el" href="conf__core_8h.html#ac2ca0e9037347eb69d53a0011f989910">conf_core.h</a>
</li>
<li>CONF_CORE_CLK_XOSC1_CFDEN
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</li>
<li>CONF_CORE_CLK_XOSC1_ENABLE
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</li>
<li>CONF_CORE_CLK_XOSC1_ENALC
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</li>
<li>CONF_CORE_CLK_XOSC1_FREQUENCY
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<li>CONF_CORE_CLK_XOSC1_LOWBUFGAIN
: <a class="el" href="conf__core_8h.html#a985ebd23986d9411d3602040e33bb405">conf_core.h</a>
</li>
<li>CONF_CORE_CLK_XOSC1_ONDEMAND
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</li>
<li>CONF_CORE_CLK_XOSC1_RUNSTDBY
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<li>CONF_CORE_CLK_XOSC1_STARTUP_TIME
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</li>
<li>CONF_CORE_CLK_XOSC1_SWBEN
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<li>CONF_CORE_CLK_XOSC1_XTALEN
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</li>
<li>CONF_CORE_CLK_XOSC32K_CFDEN
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</li>
<li>CONF_CORE_CLK_XOSC32K_CFDPRESC
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<li>CONF_CORE_CLK_XOSC32K_CGM
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</li>
<li>CONF_CORE_CLK_XOSC32K_EN1K
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<li>CONF_CORE_CLK_XOSC32K_EN32K
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</li>
<li>CONF_CORE_CLK_XOSC32K_STARTUP_TIME
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<li>CONF_CORE_CLK_XOSC32K_SWBACK
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<li>CONF_CORE_CLK_XOSC32K_WRTLOCK
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<li>CONF_CORE_CLK_XOSC32K_XTALEN
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<li>CONF_CORE_CMCC_ENABLE
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<li>CONF_CORE_PORT_EVCTRL_0_ENABLE
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</li>
<li>CONF_CORE_PORT_EVCTRL_1_ENABLE
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</li>
<li>CONF_CORE_PORT_EVCTRL_2_ENABLE
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<div class="ttc" id="aconf__core_8h_html_ab46aa120e454ecf957efa4bd97be5bdf"><div class="ttname"><a href="conf__core_8h.html#ab46aa120e454ecf957efa4bd97be5bdf">CONF_CORE_MCLK_NVM_WAIT_STATE</a></div><div class="ttdeci">#define CONF_CORE_MCLK_NVM_WAIT_STATE</div><div class="ttdef"><b>Definition:</b> <a href="conf__core_8h_source.html#l00023">conf_core.h:23</a></div></div>
<div class="ttc" id="aconf__core_8h_html_ab46aa120e454ecf957efa4bd97be5bdf"><div class="ttname"><a href="conf__core_8h.html#ab46aa120e454ecf957efa4bd97be5bdf">CONF_CORE_MCLK_NVM_WAIT_STATE</a></div><div class="ttdeci">#define CONF_CORE_MCLK_NVM_WAIT_STATE</div><div class="ttdoc">Define the number of wait states for the master clock. Can be [0-15]. See Datasheet Reference</div><div class="ttdef"><b>Definition:</b> <a href="conf__core_8h_source.html#l00024">conf_core.h:24</a></div></div>
<div class="ttc" id="asame54n19a_8h_html_ad18608913d3d6e423f3a79d84348910a"><div class="ttname"><a href="same54n19a_8h.html#ad18608913d3d6e423f3a79d84348910a">NVMCTRL</a></div><div class="ttdeci">#define NVMCTRL</div><div class="ttdoc">(NVMCTRL) APB Base Address</div><div class="ttdef"><b>Definition:</b> <a href="same54n19a_8h_source.html#l00918">same54n19a.h:918</a></div></div>
<div class="ttc" id="asame54n19a_8h_html_a625e6fdb4c2120fc163e1b04178af3dd"><div class="ttname"><a href="same54n19a_8h.html#a625e6fdb4c2120fc163e1b04178af3dd">MCLK</a></div><div class="ttdeci">#define MCLK</div><div class="ttdoc">(MCLK) APB Base Address</div><div class="ttdef"><b>Definition:</b> <a href="same54n19a_8h_source.html#l00914">same54n19a.h:914</a></div></div>
<div class="ttc" id="aconf__core_8h_html"><div class="ttname"><a href="conf__core_8h.html">conf_core.h</a></div></div>

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