From b9d5e38ccec561867d42433c18f0b483d3173362 Mon Sep 17 00:00:00 2001 From: penguin Date: Mon, 28 Dec 2020 13:26:49 -0600 Subject: [PATCH] updating docs again --- .../ESF/modules/core/.#clocks.h | 1 + .../same54p20a_test/ESF/modules/core/clocks.h | 17 - test/same54p20a_test/cfg/conf_core.h | 298 +- .../doc/html/clocks_8c_source.html | 107 +- .../doc/html/clocks_8h_source.html | 105 +- .../doc/html/conf__core_8h.html | 1003 ++- .../doc/html/conf__core_8h_source.html | 457 +- test/same54p20a_test/doc/html/globals_c.html | 161 +- .../doc/html/globals_defs_c.html | 153 +- .../doc/html/memory_8c_source.html | 2 +- .../same54p20a_test/doc/html/search/all_10.js | 666 +- .../same54p20a_test/doc/html/search/all_11.js | 4400 +++++------ .../same54p20a_test/doc/html/search/all_12.js | 322 +- .../same54p20a_test/doc/html/search/all_13.js | 6432 ++++++++--------- .../same54p20a_test/doc/html/search/all_14.js | 3580 ++++----- .../same54p20a_test/doc/html/search/all_15.js | 2276 +++--- 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.../doc/html/search/variables_5.js | 276 +- .../doc/html/search/variables_6.js | 202 +- .../doc/html/search/variables_7.js | 74 +- .../doc/html/search/variables_8.js | 114 +- .../doc/html/search/variables_9.js | 200 +- .../doc/html/search/variables_a.js | 14 +- .../doc/html/search/variables_b.js | 10 +- .../doc/html/search/variables_c.js | 132 +- .../doc/html/search/variables_d.js | 202 +- .../doc/html/search/variables_e.js | 242 +- .../doc/html/search/variables_f.js | 86 +- 163 files changed, 30721 insertions(+), 29331 deletions(-) create mode 120000 test/same54p20a_test/ESF/modules/core/.#clocks.h diff --git a/test/same54p20a_test/ESF/modules/core/.#clocks.h b/test/same54p20a_test/ESF/modules/core/.#clocks.h new file mode 120000 index 00000000..5f065dba --- /dev/null +++ b/test/same54p20a_test/ESF/modules/core/.#clocks.h @@ -0,0 +1 @@ +penguin@penguin-arch-home.19167:1609094009 \ No newline at end of file diff --git a/test/same54p20a_test/ESF/modules/core/clocks.h b/test/same54p20a_test/ESF/modules/core/clocks.h index 08c073aa..f99a82ba 100644 --- a/test/same54p20a_test/ESF/modules/core/clocks.h +++ b/test/same54p20a_test/ESF/modules/core/clocks.h @@ -16,23 +16,6 @@ #define CONF_CORE_CLK_XOSC32KCTRL_STARTUP_4000009200ns (0x5) #define CONF_CORE_CLK_XOSC32KCTRL_STARTUP_8000009200ns (0x6) -#define CONF_CORE_CLK_XOSCCTRL_STARTUP_31us 0x0 -#define CONF_CORE_CLK_XOSCCTRL_STARTUP_61us 0x1 -#define CONF_CORE_CLK_XOSCCTRL_STARTUP_122us 0x2 -#define CONF_CORE_CLK_XOSCCTRL_STARTUP_244us 0x3 -#define CONF_CORE_CLK_XOSCCTRL_STARTUP_488us 0x4 -#define CONF_CORE_CLK_XOSCCTRL_STARTUP_977us 0x5 -#define CONF_CORE_CLK_XOSCCTRL_STARTUP_1953us 0x6 -#define CONF_CORE_CLK_XOSCCTRL_STARTUP_3906us 0x7 -#define CONF_CORE_CLK_XOSCCTRL_STARTUP_7813us 0x8 -#define CONF_CORE_CLK_XOSCCTRL_STARTUP_15625us 0x9 -#define CONF_CORE_CLK_XOSCCTRL_STARTUP_31250us 0xA -#define CONF_CORE_CLK_XOSCCTRL_STARTUP_62500us 0xB -#define CONF_CORE_CLK_XOSCCTRL_STARTUP_125000us 0xC -#define CONF_CORE_CLK_XOSCCTRL_STARTUP_250000us 0xD -#define CONF_CORE_CLK_XOSCCTRL_STARTUP_500000us 0xE -#define CONF_CORE_CLK_XOSCCTRL_STARTUP_1000000us 0xF - // Oscillator Current Multiplier #define CONF_CORE_CLK_XOSCCTRL_IMULT_24MHZ_TO_48MHZ (6) #define CONF_CORE_CLK_XOSCCTRL_IMULT_16MHZ_TO_24MHZ (5) diff --git a/test/same54p20a_test/cfg/conf_core.h b/test/same54p20a_test/cfg/conf_core.h index d90a74b1..fd4a2a86 100644 --- a/test/same54p20a_test/cfg/conf_core.h +++ b/test/same54p20a_test/cfg/conf_core.h @@ -17,13 +17,14 @@ */ /** - * Define the number of wait states for the master clock. - * Can be [0-15]. + * @brief Define the number of wait states for the master clock. + *
Can be [0-15]. + *
See Datasheet Reference */ #define CONF_CORE_MCLK_NVM_WAIT_STATE 0x5 /** - * Define the master clock divisor. + * @brief Define the master clock divisor. * - 0x1 => Clock Divide by 1 * - 0x2 => Clock Divide by 2 * - 0x4 => Clock Divide by 4 @@ -32,16 +33,18 @@ * - 0x20 => Clock Divide by 32 * - 0x40 => Clock Divide by 64 * - 0x80 => Clock Divide by 128 + *
See Datasheet Reference */ #define CONF_CORE_MCLK_CPUDIV 0x1 +/** @} */ + /** * Define whether the DMAC is enabled or not. * - 0 => Disabled * - 1 => Enabled + *
See Datasheet Reference */ - -/** @} */ #define CONF_CORE_DMA_ENABLE (0) /** @@ -51,63 +54,326 @@ */ #define CONF_CORE_CMCC_ENABLE (0) +/** Currently Unused */ #define CONF_CORE_PORT_EVCTRL_0_ENABLE (0) +/** Currently Unused */ #define CONF_CORE_PORT_EVCTRL_1_ENABLE (0) +/** Currently Unused */ #define CONF_CORE_PORT_EVCTRL_2_ENABLE (0) + /** @name Core-XOSC0-Configuration * Configuration options for XOSC0. + *
See Datasheet Reference * @{ */ - +/** + * XOSC0 Enable + * @brief Enables or Disables the XOSC0 Clock + * - 0 => Disables XOSC0 + * - 1 => Enables XOSC0 + *
See Datasheet Reference + */ #define CONF_CORE_CLK_XOSC0_ENABLE (1) +/** + * XOSC0 XTALEN + * @brief This bit controls the connections between the I/O pads and the external clock or crystal oscillator XOSC0: + * - 0 => External clock connected on XIN. XOUT can be used as general purpose I/O. + * - 1 => Crystal connected to XIN/XOUT. + *
See Datasheet Reference + */ #define CONF_CORE_CLK_XOSC0_XTALEN (1) +/** + * XOSC0 Run in Standby + * @brief This bit controls how the XOSC0 behaves during standby sleep mode: + * - 0 => XOSC0 is not running in standby sleep mode if no peripheral requests the clock. + * - 1 => XOSC0 is running in standby sleep mode. + * If ONDEMAND is 1, XOSC0 will be running when a peripheral is requesting the clock. + * If ONDEMAND is 0, the clock source will always be running in standby sleep mode. + *
See Datasheet Reference + */ #define CONF_CORE_CLK_XOSC0_RUNSTDBY (0) +/** + * XOSC0 On Demand Control + * @brief The On Demand operation mode allows the oscillator XOSC0 to be enabled or disabled, depending on peripheral clock requests. + * - 0 => Oscillator is always on. + * - 1 => The oscillator is running when a peripheral is requesting the oscillator to be used as a clock source. + * The oscillator is not running if no peripheral is requesting the clock source. + *
See Datasheet Reference + */ #define CONF_CORE_CLK_XOSC0_ONDEMAND (0) +/** + * XOSC0 Low Buffer Gain Control Bit + * @brief The default value of LOWBUFGAIN=0 should be used to allow operating with a low amplitude oscillator. + * Don't use this setting except to solve stability issues. + * - 0 => The low buffer gain of XOSC0 is disabled. + * - 1 => The low buffer gain of XOSC0 is enabled. + *
See Datasheet Reference + */ #define CONF_CORE_CLK_XOSC0_LOWBUFGAIN (0) +/** + * XOSC0 Automatic Loop Control + * @brief This bit controls the XOSC0 automatic loop control: + * - 0 => The automatic loop control is disabled. + * - 1 => The automatic loop control is enabled. Oscillator's amplitude will be automatically adjusted during Crystal Oscillator operation. + *
See Datasheet Reference + */ #define CONF_CORE_CLK_XOSC0_ENALC (1) +/** + * XOSC0 Clock Failure Detector Control + * @brief This bit controls the XOSC0 clock failure detector: + * - 0 => Clock Failure Detector is disabled. + * - 1 => Clock Failure Detector is enabled. + *
See Datasheet Reference + */ #define CONF_CORE_CLK_XOSC0_CFDEN (1) +/** + * XOSC0 Clock Switch Enable + * @brief This bit controls the XOSC0 output clock switch back to the external clock or crystal oscillator in case of clock recovery: + * - 0 => The clock switch back is disabled. + * - 1 => The clock switch back is enabled. + * This bit is reset once the XOSC0 output clock is switched back to the external clock or crystal oscillator. + *
See Datasheet Reference + */ #define CONF_CORE_CLK_XOSC0_SWBEN (0) -#define CONF_CORE_CLK_XOSC0_STARTUP_TIME CONF_CORE_CLK_XOSCCTRL_STARTUP_31us +/** + * XOSC0 Startup Time + * @brief These bits select start-up time for XOSC0 according to the table below: + * - 0x00 => 31us + * - 0x01 => 61us + * - 0x02 => 122us + * - 0x03 => 244us + * - 0x04 => 488us + * - 0x05 => 977us + * - 0x06 => 1953us + * - 0x07 => 3906us + * - 0x08 => 7813us + * - 0x09 => 15625us + * - 0x0A => 31250us + * - 0x0B => 62500us + * - 0x0C => 125000us + * - 0x0D => 250000us + * - 0x0E => 500000us + * - 0x0F => 1000000us + *
See Datasheet Reference + */ +#define CONF_CORE_CLK_XOSC0_STARTUP_TIME (0x00) +/** + * XOSC0 Frequency + * @brief This is the frequency of the external clock you're using for XOSC0. + * This can be anything from 8MHz to 48MHz. + */ #define CONF_CORE_CLK_XOSC0_FREQUENCY 12000000 - /** @} */ /** @name Core-XOSC1-Configuration * Configuration options for XOSC1. + *
See Datasheet Reference * @{ */ - +/** + * XOSC1 Enable + * @brief Enables or Disables the XOSC1 Clock + * - 0 => Disables XOSC1 + * - 1 => Enables XOSC1 + *
See Datasheet Reference + */ #define CONF_CORE_CLK_XOSC1_ENABLE (0) +/** + * XOSC1 XTALEN + * @brief This bit controls the connections between the I/O pads and the external clock or crystal oscillator XOSC1: + * - 0 => External clock connected on XIN. XOUT can be used as general purpose I/O. + * - 1 => Crystal connected to XIN/XOUT. + *
See Datasheet Reference + */ #define CONF_CORE_CLK_XOSC1_XTALEN (0) +/** + * XOSC1 Run in Standby + * @brief This bit controls how the XOSC1 behaves during standby sleep mode: + * - 0 => XOSC1 is not running in standby sleep mode if no peripheral requests the clock. + * - 1 => XOSC1 is running in standby sleep mode. + * If ONDEMAND is 1, XOSC1 will be running when a peripheral is requesting the clock. + * If ONDEMAND is 0, the clock source will always be running in standby sleep mode. + *
See Datasheet Reference + */ #define CONF_CORE_CLK_XOSC1_RUNSTDBY (0) +/** + * XOSC1 On Demand Control + * @brief The On Demand operation mode allows the oscillator XOSC1 to be enabled or disabled, depending on peripheral clock requests. + * - 0 => Oscillator is always on. + * - 1 => The oscillator is running when a peripheral is requesting the oscillator to be used as a clock source. + * The oscillator is not running if no peripheral is requesting the clock source. + *
See Datasheet Reference + */ #define CONF_CORE_CLK_XOSC1_ONDEMAND (0) +/** + * XOSC1 Low Buffer Gain Control Bit + * @brief The default value of LOWBUFGAIN=0 should be used to allow operating with a low amplitude oscillator. + * Don't use this setting except to solve stability issues. + * - 0 => The low buffer gain of XOSC1 is disabled. + * - 1 => The low buffer gain of XOSC1 is enabled. + *
See Datasheet Reference + */ #define CONF_CORE_CLK_XOSC1_LOWBUFGAIN (0) +/** + * XOSC1 Automatic Loop Control + * @brief This bit controls the XOSC1 automatic loop control: + * - 0 => The automatic loop control is disabled. + * - 1 => The automatic loop control is enabled. Oscillator's amplitude will be automatically adjusted during Crystal Oscillator operation. + *
See Datasheet Reference + */ #define CONF_CORE_CLK_XOSC1_ENALC (0) +/** + * XOSC1 Clock Failure Detector Control + * @brief This bit controls the XOSC1 clock failure detector: + * - 0 => Clock Failure Detector is disabled. + * - 1 => Clock Failure Detector is enabled. + *
See Datasheet Reference + */ #define CONF_CORE_CLK_XOSC1_CFDEN (0) +/** + * XOSC1 Clock Switch Enable + * @brief This bit controls the XOSC1 output clock switch back to the external clock or crystal oscillator in case of clock recovery: + * - 0 => The clock switch back is disabled. + * - 1 => The clock switch back is enabled. + * This bit is reset once the XOSC1 output clock is switched back to the external clock or crystal oscillator. + *
See Datasheet Reference + */ #define CONF_CORE_CLK_XOSC1_SWBEN (0) -#define CONF_CORE_CLK_XOSC1_STARTUP_TIME CONF_CORE_CLK_XOSCCTRL_STARTUP_31us +/** + * XOSC1 Startup Time + * @brief These bits select start-up time for XOSC1 according to the table below: + * - 0x00 => 31us + * - 0x01 => 61us + * - 0x02 => 122us + * - 0x03 => 244us + * - 0x04 => 488us + * - 0x05 => 977us + * - 0x06 => 1953us + * - 0x07 => 3906us + * - 0x08 => 7813us + * - 0x09 => 15625us + * - 0x0A => 31250us + * - 0x0B => 62500us + * - 0x0C => 125000us + * - 0x0D => 250000us + * - 0x0E => 500000us + * - 0x0F => 1000000us + *
See Datasheet Reference + */ +#define CONF_CORE_CLK_XOSC1_STARTUP_TIME (0x00) +/** + * XOSC1 Frequency + * @brief This is the frequency of the external clock you're using for XOSC1. + * This can be anything from 8MHz to 48MHz. + */ #define CONF_CORE_CLK_XOSC1_FREQUENCY 12000000 - /** @} */ /** @name Core-XOSC32K-Configuration * Configuration options for the external 32khz oscillator. + *
See Datasheet Reference * @{ */ - +/** + * XOSC32K Enable + * @brief Enables or Disables XOSC32K. + * - 0 => The oscillator is disabled. + * - 1 => The oscillator is enabled. + *
See Datasheet Reference + */ #define CONF_CORE_CLK_XOSC32K_ENABLE (1) -#define CONF_CORE_CLK_XOSC32K_CGM CONF_CORE_CLK_XOSC32KCTRL_CGM_STD_MODE +/** + * XOSC32K Control Gain Mode + * @brief These bits control the gain of the external crstal oscillator. + * - 0x00 => Low Power Mode + * - 0x01 => Standard Mode (Default) + * - 0x02 => High Speed Mode + *
See Datasheet Reference + */ +#define CONF_CORE_CLK_XOSC32K_CGM (0x01) +/** + * XOSC32K Startup Time + * @brief These bits select the startup time for the oscillator. + * - 0x00 => 62.592ms + * - 0x01 => 125.092ms + * - 0x02 => 500.092ms + * - 0x03 => 1000.0092ms + * - 0x04 => 2000.0092ms + * - 0x05 => 4000.0092ms + * - 0x06 => 8000.0092ms + *
See Datasheet Reference + */ #define CONF_CORE_CLK_XOSC32K_STARTUP_TIME CONF_CORE_CLK_XOSC32KCTRL_STARTUP_62592us +/** + * XOSC32K On Demand Control + * @brief This bit controls how XOSC32K behaves when a peripheral clock request is detected. + * - 0 => On Demand Control disabled + * - 1 => On Demand Control enabled + *
See Datasheet Reference + */ #define CONF_CORE_CLK_XOSC32K_ONDEMAND (1) +/** + * XOSC32K Run in Standby + * @brief This bit controls how XOSC32K behaves during standby sleep mode. + * - 0 => Run if requested by peripheral. + * - 1 => Run if requested by peripheral OR always run depending ONDEMAND value. + *
See Datasheet Reference + */ #define CONF_CORE_CLK_XOSC32K_RUNSTDBY (0) +/** + * XOSC32K 1KHz Output Control + * - 0 => 1KHz output is disabled. + * - 1 => 1KHz output is enabled. + *
See Datasheet Reference + */ #define CONF_CORE_CLK_XOSC32K_EN1K (0) +/** + * XOSC32K 32KHz Output Control + * - 0 => 32KHz output is disabled. + * - 1 => 32KHz output is enabled. + *
See Datasheet Reference + */ #define CONF_CORE_CLK_XOSC32K_EN32K (1) +/** + * XOSC32K Crystal Oscillator Enable + * @brief This bit controls the connections between the I/O pads and the external clock or crystal oscillator. + * - 0 => External clock is connected on XIN32. XOUT32 can be used as general-purpose I/O. + * - 1 => Crystal connected to XIN32/XOUT32. + *
See Datasheet Reference + */ #define CONF_CORE_CLK_XOSC32K_XTALEN (1) +/** + * XOSC32K Clock Failure Detector Prescaler + * @brief This bit selects the prescaler for the CLock Failure Detector: + * - 0 => The CFD safe clock frequency is the OSCULP32K frequency. + * - 1 => The CFD safe clock frequency is the OSCULP32K frequency divided by 2. + *
See Datasheet Reference + */ #define CONF_CORE_CLK_XOSC32K_CFDPRESC (0) +/** + * XOSC32K Clock Failure Detector Control + * @brief This bit selects the Clock Failulre Detector state. + * - 0 => The CFD is disabled. + * - 1 => The CFD is enabled. + *
See Datasheet Reference + */ #define CONF_CORE_CLK_XOSC32K_CFDEN (0) +/** + * XOSC32K Clock Switch Back + * @brief This bit controls the XOSC32K output switch back to the external clock or crystal oscillator in case of clock recovery. + * - 0 => The clock switch is disabled. + * - 1 => The clock switch is enabled. This bit is reset when XOSC32K output is switched back to the external clock or crystal oscillator. + *
See Datasheet Reference + */ #define CONF_CORE_CLK_XOSC32K_SWBACK (0) +/** + * XOSC32K Write Lock + * @brief This bit locks the XOSC32K register for future writes, effectively freezing the XOSC32K configuration. + * - 0 => XOSC32K configuration is not locked. + * - 1 => XOSC32K configuration is locked. + *
See Datasheet Reference + */ #define CONF_CORE_CLK_XOSC32K_WRTLOCK (0) - /** @} */ /** @name Core-DFLL48M-Configuration @@ -199,6 +465,7 @@ #define CONF_CORE_CLK_DPLL0_REFCLK CONF_CORE_CLK_DPLLCTRL_REFCLK_XOSC0 /** * pg. 732 of the datasheet + * ~~~ * FILTER[3:0] | PLL Bandwidth (fn) | Damping Factor * 0x0 | 92.7 kHz | 0.76 * 0x1 | 131 kHz | 1.08 @@ -216,7 +483,8 @@ * 0xD | 92.7 kHz | 1.51 * 0xE | 32.8 kHz | 0.53 * 0xF | 46.4 kHz | 0.75 - * + * ~~~ + * * When in doubt, leave this at its default. */ #define CONF_CORE_CLK_DPLL0_FILTER 0x0 diff --git a/test/same54p20a_test/doc/html/clocks_8c_source.html b/test/same54p20a_test/doc/html/clocks_8c_source.html index c0dfeafd..66e86828 100644 --- a/test/same54p20a_test/doc/html/clocks_8c_source.html +++ b/test/same54p20a_test/doc/html/clocks_8c_source.html @@ -111,17 +111,17 @@ $(function() {
40 void clock_osc32k_init(void)
41 {
42 #if CONF_CORE_CLK_XOSC32K_ENABLE == 1
-
43  OSC32KCTRL->XOSC32K.bit.CGM = CONF_CORE_CLK_XOSC32K_CGM;
-
44  OSC32KCTRL->XOSC32K.bit.WRTLOCK = CONF_CORE_CLK_XOSC32K_WRTLOCK;
-
45  OSC32KCTRL->XOSC32K.bit.STARTUP = CONF_CORE_CLK_XOSC32K_STARTUP_TIME;
-
46  OSC32KCTRL->XOSC32K.bit.RUNSTDBY = CONF_CORE_CLK_XOSC32K_RUNSTDBY;
-
47  OSC32KCTRL->XOSC32K.bit.ONDEMAND = CONF_CORE_CLK_XOSC32K_ONDEMAND;
-
48  OSC32KCTRL->XOSC32K.bit.EN1K = CONF_CORE_CLK_XOSC32K_EN1K;
-
49  OSC32KCTRL->XOSC32K.bit.EN32K = CONF_CORE_CLK_XOSC32K_EN32K;
-
50  OSC32KCTRL->XOSC32K.bit.XTALEN = CONF_CORE_CLK_XOSC32K_XTALEN;
-
51  OSC32KCTRL->CFDCTRL.bit.CFDPRESC = CONF_CORE_CLK_XOSC32K_CFDPRESC;
-
52  OSC32KCTRL->CFDCTRL.bit.SWBACK = CONF_CORE_CLK_XOSC32K_SWBACK;
-
53  OSC32KCTRL->CFDCTRL.bit.CFDEN = CONF_CORE_CLK_XOSC32K_CFDEN;
+
43  OSC32KCTRL->XOSC32K.bit.CGM = CONF_CORE_CLK_XOSC32K_CGM;
+
44  OSC32KCTRL->XOSC32K.bit.WRTLOCK = CONF_CORE_CLK_XOSC32K_WRTLOCK;
+
45  OSC32KCTRL->XOSC32K.bit.STARTUP = CONF_CORE_CLK_XOSC32K_STARTUP_TIME;
+
46  OSC32KCTRL->XOSC32K.bit.RUNSTDBY = CONF_CORE_CLK_XOSC32K_RUNSTDBY;
+
47  OSC32KCTRL->XOSC32K.bit.ONDEMAND = CONF_CORE_CLK_XOSC32K_ONDEMAND;
+
48  OSC32KCTRL->XOSC32K.bit.EN1K = CONF_CORE_CLK_XOSC32K_EN1K;
+
49  OSC32KCTRL->XOSC32K.bit.EN32K = CONF_CORE_CLK_XOSC32K_EN32K;
+
50  OSC32KCTRL->XOSC32K.bit.XTALEN = CONF_CORE_CLK_XOSC32K_XTALEN;
+
51  OSC32KCTRL->CFDCTRL.bit.CFDPRESC = CONF_CORE_CLK_XOSC32K_CFDPRESC;
+
52  OSC32KCTRL->CFDCTRL.bit.SWBACK = CONF_CORE_CLK_XOSC32K_SWBACK;
+
53  OSC32KCTRL->CFDCTRL.bit.CFDEN = CONF_CORE_CLK_XOSC32K_CFDEN;
54 
55 #if CONF_CORE_CLK_XOSC32K_ENABLE == 1 && CONF_CORE_CLK_XOSC32K_ONDEMAND == 0
56  while(OSC32KCTRL->STATUS.bit.XOSC32KRDY == 0);
@@ -133,34 +133,34 @@ $(function() {
62 {
63 #if CONF_CORE_CLK_XOSC0_ENABLE == 1
64  CRITICAL_SECTION_ENTER();
-
65  OSCCTRL->XOSCCTRL[0].bit.XTALEN = CONF_CORE_CLK_XOSC0_XTALEN;
-
66  OSCCTRL->XOSCCTRL[0].bit.RUNSTDBY = CONF_CORE_CLK_XOSC0_RUNSTDBY;
-
67  OSCCTRL->XOSCCTRL[0].bit.ONDEMAND = CONF_CORE_CLK_XOSC0_ONDEMAND;
-
68  OSCCTRL->XOSCCTRL[0].bit.LOWBUFGAIN = CONF_CORE_CLK_XOSC0_LOWBUFGAIN;
+
65  OSCCTRL->XOSCCTRL[0].bit.XTALEN = CONF_CORE_CLK_XOSC0_XTALEN;
+
66  OSCCTRL->XOSCCTRL[0].bit.RUNSTDBY = CONF_CORE_CLK_XOSC0_RUNSTDBY;
+
67  OSCCTRL->XOSCCTRL[0].bit.ONDEMAND = CONF_CORE_CLK_XOSC0_ONDEMAND;
+
68  OSCCTRL->XOSCCTRL[0].bit.LOWBUFGAIN = CONF_CORE_CLK_XOSC0_LOWBUFGAIN;
69  OSCCTRL->XOSCCTRL[0].bit.IPTAT = CONF_CORE_CLK_XOSC0_IPTAT;
70  OSCCTRL->XOSCCTRL[0].bit.IMULT = CONF_CORE_CLK_XOSC0_IMULT;
-
71  OSCCTRL->XOSCCTRL[0].bit.ENALC = CONF_CORE_CLK_XOSC0_ENALC;
-
72  OSCCTRL->XOSCCTRL[0].bit.CFDEN = CONF_CORE_CLK_XOSC0_CFDEN;
+
71  OSCCTRL->XOSCCTRL[0].bit.ENALC = CONF_CORE_CLK_XOSC0_ENALC;
+
72  OSCCTRL->XOSCCTRL[0].bit.CFDEN = CONF_CORE_CLK_XOSC0_CFDEN;
73  OSCCTRL->XOSCCTRL[0].bit.CFDPRESC = CONF_CORE_CLK_XOSC0_CFDPRESC;
-
74  OSCCTRL->XOSCCTRL[0].bit.SWBEN = CONF_CORE_CLK_XOSC0_SWBEN;
-
75  OSCCTRL->XOSCCTRL[0].bit.STARTUP = CONF_CORE_CLK_XOSC0_STARTUP_TIME;
-
76  OSCCTRL->XOSCCTRL[0].bit.ENABLE = CONF_CORE_CLK_XOSC0_ENABLE;
+
74  OSCCTRL->XOSCCTRL[0].bit.SWBEN = CONF_CORE_CLK_XOSC0_SWBEN;
+
75  OSCCTRL->XOSCCTRL[0].bit.STARTUP = CONF_CORE_CLK_XOSC0_STARTUP_TIME;
+
76  OSCCTRL->XOSCCTRL[0].bit.ENABLE = CONF_CORE_CLK_XOSC0_ENABLE;
77  CRITICAL_SECTION_LEAVE();
78  while(0 == OSCCTRL->STATUS.bit.XOSCRDY0);
79 #endif
80 
81 #if CONF_CORE_CLK_XOSC1_ENABLE == 1
82  CRITICAL_SECTION_ENTER();
-
83  OSCCTRL->XOSCCTRL[1].bit.XTALEN = CONF_CORE_CLK_XOSC1_XTALEN;
-
84  OSCCTRL->XOSCCTRL[1].bit.RUNSTDBY = CONF_CORE_CLK_XOSC1_RUNSTDBY;
-
85  OSCCTRL->XOSCCTRL[1].bit.LOWBUFGAIN = CONF_CORE_CLK_XOSC1_LOWBUFGAIN;
+
83  OSCCTRL->XOSCCTRL[1].bit.XTALEN = CONF_CORE_CLK_XOSC1_XTALEN;
+
84  OSCCTRL->XOSCCTRL[1].bit.RUNSTDBY = CONF_CORE_CLK_XOSC1_RUNSTDBY;
+
85  OSCCTRL->XOSCCTRL[1].bit.LOWBUFGAIN = CONF_CORE_CLK_XOSC1_LOWBUFGAIN;
86  OSCCTRL->XOSCCTRL[1].bit.IPTAT = CONF_CORE_CLK_XOSC1_IPTAT;
87  OSCCTRL->XOSCCTRL[1].bit.IMULT = CONF_CORE_CLK_XOSC1_IMULT;
-
88  OSCCTRL->XOSCCTRL[1].bit.CFDEN = CONF_CORE_CLK_XOSC1_CFDEN;
+
88  OSCCTRL->XOSCCTRL[1].bit.CFDEN = CONF_CORE_CLK_XOSC1_CFDEN;
89  OSCCTRL->XOSCCTRL[1].bit.CFDPRESC = CONF_CORE_CLK_XOSC1_CFDPRESC;
-
90  OSCCTRL->XOSCCTRL[1].bit.SWBEN = CONF_CORE_CLK_XOSC1_SWBEN;
-
91  OSCCTRL->XOSCCTRL[1].bit.STARTUP = CONF_CORE_CLK_XOSC1_STARTUP_TIME;
-
92  OSCCTRL->XOSCCTRL[1].bit.ENABLE = CONF_CORE_CLK_XOSC1_ENABLE;
+
90  OSCCTRL->XOSCCTRL[1].bit.SWBEN = CONF_CORE_CLK_XOSC1_SWBEN;
+
91  OSCCTRL->XOSCCTRL[1].bit.STARTUP = CONF_CORE_CLK_XOSC1_STARTUP_TIME;
+
92  OSCCTRL->XOSCCTRL[1].bit.ENABLE = CONF_CORE_CLK_XOSC1_ENABLE;
93  CRITICAL_SECTION_LEAVE();
94  while(0 == OSCCTRL->STATUS.bit.XOSCRDY1);
95 #endif
@@ -168,11 +168,11 @@ $(function() {
97 #if CONF_CORE_CLK_XOSC0_ENABLE == 1
98  CRITICAL_SECTION_ENTER();
99 #if CONF_CORE_CLK_XOSC0_ENALC == 1
-
100  OSCCTRL->XOSCCTRL[0].bit.ENALC = CONF_CORE_CLK_XOSC0_ENALC;
+
100  OSCCTRL->XOSCCTRL[0].bit.ENALC = CONF_CORE_CLK_XOSC0_ENALC;
101 #endif
102 
103 #if CONF_CORE_CLK_XOSC0_ONDEMAND == 1
-
104  OSCCTRL->XOSCCTRL[0].bit.ONDEMAND = CONF_CORE_CLK_XOSC0_ONDEMAND;
+
104  OSCCTRL->XOSCCTRL[0].bit.ONDEMAND = CONF_CORE_CLK_XOSC0_ONDEMAND;
105 #endif
106  CRITICAL_SECTION_LEAVE();
107 #endif
@@ -180,11 +180,11 @@ $(function() {
109 #if CONF_CORE_CLK_XOSC1_ENABLE == 1
110  CRITICAL_SECTION_ENTER();
111 #if CONF_CORE_CLK_XOSC1_ENALC == 1
-
112  OSCCTRL->XOSCCTRL[1].bit.ENALC = CONF_CORE_CLK_XOSC1_ENALC;
+
112  OSCCTRL->XOSCCTRL[1].bit.ENALC = CONF_CORE_CLK_XOSC1_ENALC;
113 #endif
114 
115 #if CONF_CORE_CLK_XOSC1_ONDEMAND == 1
-
116  OSCCTRL->XOSCCTRL[1].bit.ONDEMAND = CONF_CORE_CLK_XOSC1_ONDEMAND;
+
116  OSCCTRL->XOSCCTRL[1].bit.ONDEMAND = CONF_CORE_CLK_XOSC1_ONDEMAND;
117 #endif
118  CRITICAL_SECTION_LEAVE();
119 #endif
@@ -526,19 +526,48 @@ $(function() {
455 #endif
456 }
-
CONF_CORE_CLK_DFLL_WAITLOCK
#define CONF_CORE_CLK_DFLL_WAITLOCK
This bit controls the DFLL output clock, depending on the lock status:
Definition: conf_core.h:148
-
CONF_CORE_CLK_DPLL1_FILTER
#define CONF_CORE_CLK_DPLL1_FILTER
Definition: conf_core.h:267
-
CONF_CORE_CLK_DPLL0_FILTER
#define CONF_CORE_CLK_DPLL0_FILTER
Definition: conf_core.h:222
-
CONF_CORE_MCLK_CPUDIV
#define CONF_CORE_MCLK_CPUDIV
Definition: conf_core.h:36
+
CONF_CORE_CLK_DFLL_WAITLOCK
#define CONF_CORE_CLK_DFLL_WAITLOCK
This bit controls the DFLL output clock, depending on the lock status:
Definition: conf_core.h:414
+
CONF_CORE_CLK_XOSC1_ONDEMAND
#define CONF_CORE_CLK_XOSC1_ONDEMAND
The On Demand operation mode allows the oscillator XOSC1 to be enabled or disabled,...
Definition: conf_core.h:207
+
CONF_CORE_CLK_XOSC0_CFDEN
#define CONF_CORE_CLK_XOSC0_CFDEN
This bit controls the XOSC0 clock failure detector:
Definition: conf_core.h:128
+
CONF_CORE_CLK_DPLL1_FILTER
#define CONF_CORE_CLK_DPLL1_FILTER
Definition: conf_core.h:535
+
CONF_CORE_CLK_XOSC1_SWBEN
#define CONF_CORE_CLK_XOSC1_SWBEN
This bit controls the XOSC1 output clock switch back to the external clock or crystal oscillator in c...
Definition: conf_core.h:241
+
CONF_CORE_CLK_XOSC0_ENALC
#define CONF_CORE_CLK_XOSC0_ENALC
This bit controls the XOSC0 automatic loop control:
Definition: conf_core.h:120
+
CONF_CORE_CLK_XOSC32K_EN32K
#define CONF_CORE_CLK_XOSC32K_EN32K
Definition: conf_core.h:336
+
CONF_CORE_CLK_DPLL0_FILTER
#define CONF_CORE_CLK_DPLL0_FILTER
Definition: conf_core.h:490
+
CONF_CORE_CLK_XOSC32K_CGM
#define CONF_CORE_CLK_XOSC32K_CGM
These bits control the gain of the external crstal oscillator.
Definition: conf_core.h:293
+
CONF_CORE_MCLK_CPUDIV
#define CONF_CORE_MCLK_CPUDIV
Define the master clock divisor.
Definition: conf_core.h:38
+
CONF_CORE_CLK_XOSC0_XTALEN
#define CONF_CORE_CLK_XOSC0_XTALEN
This bit controls the connections between the I/O pads and the external clock or crystal oscillator X...
Definition: conf_core.h:84
+
CONF_CORE_CLK_XOSC1_RUNSTDBY
#define CONF_CORE_CLK_XOSC1_RUNSTDBY
This bit controls how the XOSC1 behaves during standby sleep mode:
Definition: conf_core.h:198
+
CONF_CORE_CLK_XOSC1_CFDEN
#define CONF_CORE_CLK_XOSC1_CFDEN
This bit controls the XOSC1 clock failure detector:
Definition: conf_core.h:232
+
CONF_CORE_CLK_XOSC32K_CFDEN
#define CONF_CORE_CLK_XOSC32K_CFDEN
This bit selects the Clock Failulre Detector state.
Definition: conf_core.h:360
MCLK
#define MCLK
(MCLK) APB Base Address
Definition: same54n19a.h:914
+
CONF_CORE_CLK_XOSC1_ENABLE
#define CONF_CORE_CLK_XOSC1_ENABLE
Enables or Disables the XOSC1 Clock.
Definition: conf_core.h:180
+
CONF_CORE_CLK_XOSC1_ENALC
#define CONF_CORE_CLK_XOSC1_ENALC
This bit controls the XOSC1 automatic loop control:
Definition: conf_core.h:224
+
CONF_CORE_CLK_XOSC0_SWBEN
#define CONF_CORE_CLK_XOSC0_SWBEN
This bit controls the XOSC0 output clock switch back to the external clock or crystal oscillator in c...
Definition: conf_core.h:137
+
CONF_CORE_CLK_XOSC0_ENABLE
#define CONF_CORE_CLK_XOSC0_ENABLE
Enables or Disables the XOSC0 Clock.
Definition: conf_core.h:76
+
CONF_CORE_CLK_XOSC1_XTALEN
#define CONF_CORE_CLK_XOSC1_XTALEN
This bit controls the connections between the I/O pads and the external clock or crystal oscillator X...
Definition: conf_core.h:188
+
CONF_CORE_CLK_XOSC32K_XTALEN
#define CONF_CORE_CLK_XOSC32K_XTALEN
This bit controls the connections between the I/O pads and the external clock or crystal oscillator.
Definition: conf_core.h:344
OSC32KCTRL
#define OSC32KCTRL
(OSC32KCTRL) APB Base Address
Definition: same54n19a.h:929
-
CONF_CORE_CLK_DFLL_ONDEMAND
#define CONF_CORE_CLK_DFLL_ONDEMAND
Enables or Disables on-demand operation.
Definition: conf_core.h:132
+
CONF_CORE_CLK_XOSC32K_STARTUP_TIME
#define CONF_CORE_CLK_XOSC32K_STARTUP_TIME
These bits select the startup time for the oscillator.
Definition: conf_core.h:306
+
CONF_CORE_CLK_DFLL_ONDEMAND
#define CONF_CORE_CLK_DFLL_ONDEMAND
Enables or Disables on-demand operation.
Definition: conf_core.h:398
+
CONF_CORE_CLK_XOSC32K_RUNSTDBY
#define CONF_CORE_CLK_XOSC32K_RUNSTDBY
This bit controls how XOSC32K behaves during standby sleep mode.
Definition: conf_core.h:322
+
CONF_CORE_CLK_XOSC0_STARTUP_TIME
#define CONF_CORE_CLK_XOSC0_STARTUP_TIME
These bits select start-up time for XOSC0 according to the table below:
Definition: conf_core.h:159
+
CONF_CORE_CLK_XOSC32K_ONDEMAND
#define CONF_CORE_CLK_XOSC32K_ONDEMAND
This bit controls how XOSC32K behaves when a peripheral clock request is detected.
Definition: conf_core.h:314
OSCCTRL
#define OSCCTRL
(OSCCTRL) APB Base Address
Definition: same54n19a.h:925
-
CONF_CORE_CLK_DFLL_RUNSTDBY
#define CONF_CORE_CLK_DFLL_RUNSTDBY
Enables or Disables run-in-standby operation.
Definition: conf_core.h:140
+
CONF_CORE_CLK_XOSC32K_WRTLOCK
#define CONF_CORE_CLK_XOSC32K_WRTLOCK
This bit locks the XOSC32K register for future writes, effectively freezing the XOSC32K configuration...
Definition: conf_core.h:376
+
CONF_CORE_CLK_XOSC32K_CFDPRESC
#define CONF_CORE_CLK_XOSC32K_CFDPRESC
This bit selects the prescaler for the CLock Failure Detector:
Definition: conf_core.h:352
+
CONF_CORE_CLK_XOSC0_RUNSTDBY
#define CONF_CORE_CLK_XOSC0_RUNSTDBY
This bit controls how the XOSC0 behaves during standby sleep mode:
Definition: conf_core.h:94
+
CONF_CORE_CLK_XOSC1_STARTUP_TIME
#define CONF_CORE_CLK_XOSC1_STARTUP_TIME
These bits select start-up time for XOSC1 according to the table below:
Definition: conf_core.h:263
+
CONF_CORE_CLK_XOSC32K_EN1K
#define CONF_CORE_CLK_XOSC32K_EN1K
Definition: conf_core.h:329
+
CONF_CORE_CLK_DFLL_RUNSTDBY
#define CONF_CORE_CLK_DFLL_RUNSTDBY
Enables or Disables run-in-standby operation.
Definition: conf_core.h:406
conf_core.h
-
CONF_CORE_CLK_DFLL_ENABLE
#define CONF_CORE_CLK_DFLL_ENABLE
Enables or Disables the DFLL48M Clock.
Definition: conf_core.h:124
+
CONF_CORE_CLK_XOSC0_ONDEMAND
#define CONF_CORE_CLK_XOSC0_ONDEMAND
The On Demand operation mode allows the oscillator XOSC0 to be enabled or disabled,...
Definition: conf_core.h:103
+
CONF_CORE_CLK_XOSC32K_SWBACK
#define CONF_CORE_CLK_XOSC32K_SWBACK
This bit controls the XOSC32K output switch back to the external clock or crystal oscillator in case ...
Definition: conf_core.h:368
+
CONF_CORE_CLK_XOSC0_LOWBUFGAIN
#define CONF_CORE_CLK_XOSC0_LOWBUFGAIN
The default value of LOWBUFGAIN=0 should be used to allow operating with a low amplitude oscillator....
Definition: conf_core.h:112
+
CONF_CORE_CLK_DFLL_ENABLE
#define CONF_CORE_CLK_DFLL_ENABLE
Enables or Disables the DFLL48M Clock.
Definition: conf_core.h:390
GCLK
#define GCLK
(GCLK) APB Base Address
Definition: same54n19a.h:894
-
CONF_CORE_CLK_DFLL_GCLK_SRC
#define CONF_CORE_CLK_DFLL_GCLK_SRC
GCLK Source used to generate DFLL48M.
Definition: conf_core.h:178
+
CONF_CORE_CLK_DFLL_GCLK_SRC
#define CONF_CORE_CLK_DFLL_GCLK_SRC
GCLK Source used to generate DFLL48M.
Definition: conf_core.h:444
+
CONF_CORE_CLK_XOSC1_LOWBUFGAIN
#define CONF_CORE_CLK_XOSC1_LOWBUFGAIN
The default value of LOWBUFGAIN=0 should be used to allow operating with a low amplitude oscillator....
Definition: conf_core.h:216
Generated by doxygen 1.8.20 diff --git a/test/same54p20a_test/doc/html/clocks_8h_source.html b/test/same54p20a_test/doc/html/clocks_8h_source.html index 6f2e2b42..2c49f175 100644 --- a/test/same54p20a_test/doc/html/clocks_8h_source.html +++ b/test/same54p20a_test/doc/html/clocks_8h_source.html @@ -87,67 +87,50 @@ $(function() {
16 #define CONF_CORE_CLK_XOSC32KCTRL_STARTUP_4000009200ns (0x5)
17 #define CONF_CORE_CLK_XOSC32KCTRL_STARTUP_8000009200ns (0x6)
18 
-
19 #define CONF_CORE_CLK_XOSCCTRL_STARTUP_31us 0x0
-
20 #define CONF_CORE_CLK_XOSCCTRL_STARTUP_61us 0x1
-
21 #define CONF_CORE_CLK_XOSCCTRL_STARTUP_122us 0x2
-
22 #define CONF_CORE_CLK_XOSCCTRL_STARTUP_244us 0x3
-
23 #define CONF_CORE_CLK_XOSCCTRL_STARTUP_488us 0x4
-
24 #define CONF_CORE_CLK_XOSCCTRL_STARTUP_977us 0x5
-
25 #define CONF_CORE_CLK_XOSCCTRL_STARTUP_1953us 0x6
-
26 #define CONF_CORE_CLK_XOSCCTRL_STARTUP_3906us 0x7
-
27 #define CONF_CORE_CLK_XOSCCTRL_STARTUP_7813us 0x8
-
28 #define CONF_CORE_CLK_XOSCCTRL_STARTUP_15625us 0x9
-
29 #define CONF_CORE_CLK_XOSCCTRL_STARTUP_31250us 0xA
-
30 #define CONF_CORE_CLK_XOSCCTRL_STARTUP_62500us 0xB
-
31 #define CONF_CORE_CLK_XOSCCTRL_STARTUP_125000us 0xC
-
32 #define CONF_CORE_CLK_XOSCCTRL_STARTUP_250000us 0xD
-
33 #define CONF_CORE_CLK_XOSCCTRL_STARTUP_500000us 0xE
-
34 #define CONF_CORE_CLK_XOSCCTRL_STARTUP_1000000us 0xF
-
35 
-
36 // Oscillator Current Multiplier
-
37 #define CONF_CORE_CLK_XOSCCTRL_IMULT_24MHZ_TO_48MHZ (6)
-
38 #define CONF_CORE_CLK_XOSCCTRL_IMULT_16MHZ_TO_24MHZ (5)
-
39 #define CONF_CORE_CLK_XOSCCTRL_IMULT_8MHZ_TO_16MHZ (4)
-
40 #define CONF_CORE_CLK_XOSCCTRL_IMULT_8MHZ (3)
-
41 
-
42 // Oscillator Current Reference
-
43 #define CONF_CORE_CLK_XOSCCTRL_IPTAT_24MHZ_TO_48MHZ (3)
-
44 #define CONF_CORE_CLK_XOSCCTRL_IPTAT_16MHZ_TO_24MHZ (3)
-
45 #define CONF_CORE_CLK_XOSCCTRL_IPTAT_8MHZ_TO_16MHZ (3)
-
46 #define CONF_CORE_CLK_XOSCCTRL_IPTAT_8MHZ (2)
-
47 
-
48 // DFLL Definitions
-
49 #define CONF_CORE_CLK_DFLLCTRL_STABLE_FCALIB_NOT_FIXED (0)
-
50 #define CONF_CORE_CLK_DFLLCTRL_STABLE_FCALIB_FIXED (1)
-
51 
-
52 // DPLL Definitions
-
53 #define CONF_CORE_CLK_DPLLCTRL_DCOFILTER_3210KHZ (0x0)
-
54 #define CONF_CORE_CLK_DPLLCTRL_DCOFILTER_1600KHZ (0x1)
-
55 #define CONF_CORE_CLK_DPLLCTRL_DCOFILTER_1100KHZ (0x2)
-
56 #define CONF_CORE_CLK_DPLLCTRL_DCOFILTER_800KHZ (0x3)
-
57 #define CONF_CORE_CLK_DPLLCTRL_DCOFILTER_640KHZ (0x4)
-
58 #define CONF_CORE_CLK_DPLLCTRL_DCOFILTER_550KHZ (0x5)
-
59 #define CONF_CORE_CLK_DPLLCTRL_DCOFILTER_450KHZ (0x6)
-
60 #define CONF_CORE_CLK_DPLLCTRL_DCOFILTER_400KHZ (0x7)
-
61 
-
62 #define CONF_CORE_CLK_DPLLCTRL_LTIME_TIMEOUT_NONE (0x0)
-
63 #define CONF_CORE_CLK_DPLLCTRL_LTIME_TIMEOUT_800us (0x4)
-
64 #define CONF_CORE_CLK_DPLLCTRL_LTIME_TIMEOUT_900us (0x5)
-
65 #define CONF_CORE_CLK_DPLLCTRL_LTIME_TIMEOUT_1000us (0x6)
-
66 #define CONF_CORE_CLK_DPLLCTRL_LTIME_TIMEOUT_1100us (0x7)
-
67 
-
68 #define CONF_CORE_CLK_DPLLCTRL_REFCLK_GCLK (0x0)
-
69 #define CONF_CORE_CLK_DPLLCTRL_REFCLK_XOSC32 (0x1)
-
70 #define CONF_CORE_CLK_DPLLCTRL_REFCLK_XOSC0 (0x2)
-
71 #define CONF_CORE_CLK_DPLLCTRL_REFCLK_XOSC1 (0x3)
-
72 
-
73 void clock_osc32k_init(void);
-
74 void clock_osc_init(void);
-
75 void clock_mclk_init(void);
-
76 void clock_gclk_init(void);
-
77 void clock_dpll_init(void);
-
78 void clock_dfll_init(void);
-
79 #endif
+
19 // Oscillator Current Multiplier
+
20 #define CONF_CORE_CLK_XOSCCTRL_IMULT_24MHZ_TO_48MHZ (6)
+
21 #define CONF_CORE_CLK_XOSCCTRL_IMULT_16MHZ_TO_24MHZ (5)
+
22 #define CONF_CORE_CLK_XOSCCTRL_IMULT_8MHZ_TO_16MHZ (4)
+
23 #define CONF_CORE_CLK_XOSCCTRL_IMULT_8MHZ (3)
+
24 
+
25 // Oscillator Current Reference
+
26 #define CONF_CORE_CLK_XOSCCTRL_IPTAT_24MHZ_TO_48MHZ (3)
+
27 #define CONF_CORE_CLK_XOSCCTRL_IPTAT_16MHZ_TO_24MHZ (3)
+
28 #define CONF_CORE_CLK_XOSCCTRL_IPTAT_8MHZ_TO_16MHZ (3)
+
29 #define CONF_CORE_CLK_XOSCCTRL_IPTAT_8MHZ (2)
+
30 
+
31 // DFLL Definitions
+
32 #define CONF_CORE_CLK_DFLLCTRL_STABLE_FCALIB_NOT_FIXED (0)
+
33 #define CONF_CORE_CLK_DFLLCTRL_STABLE_FCALIB_FIXED (1)
+
34 
+
35 // DPLL Definitions
+
36 #define CONF_CORE_CLK_DPLLCTRL_DCOFILTER_3210KHZ (0x0)
+
37 #define CONF_CORE_CLK_DPLLCTRL_DCOFILTER_1600KHZ (0x1)
+
38 #define CONF_CORE_CLK_DPLLCTRL_DCOFILTER_1100KHZ (0x2)
+
39 #define CONF_CORE_CLK_DPLLCTRL_DCOFILTER_800KHZ (0x3)
+
40 #define CONF_CORE_CLK_DPLLCTRL_DCOFILTER_640KHZ (0x4)
+
41 #define CONF_CORE_CLK_DPLLCTRL_DCOFILTER_550KHZ (0x5)
+
42 #define CONF_CORE_CLK_DPLLCTRL_DCOFILTER_450KHZ (0x6)
+
43 #define CONF_CORE_CLK_DPLLCTRL_DCOFILTER_400KHZ (0x7)
+
44 
+
45 #define CONF_CORE_CLK_DPLLCTRL_LTIME_TIMEOUT_NONE (0x0)
+
46 #define CONF_CORE_CLK_DPLLCTRL_LTIME_TIMEOUT_800us (0x4)
+
47 #define CONF_CORE_CLK_DPLLCTRL_LTIME_TIMEOUT_900us (0x5)
+
48 #define CONF_CORE_CLK_DPLLCTRL_LTIME_TIMEOUT_1000us (0x6)
+
49 #define CONF_CORE_CLK_DPLLCTRL_LTIME_TIMEOUT_1100us (0x7)
+
50 
+
51 #define CONF_CORE_CLK_DPLLCTRL_REFCLK_GCLK (0x0)
+
52 #define CONF_CORE_CLK_DPLLCTRL_REFCLK_XOSC32 (0x1)
+
53 #define CONF_CORE_CLK_DPLLCTRL_REFCLK_XOSC0 (0x2)
+
54 #define CONF_CORE_CLK_DPLLCTRL_REFCLK_XOSC1 (0x3)
+
55 
+
56 void clock_osc32k_init(void);
+
57 void clock_osc_init(void);
+
58 void clock_mclk_init(void);
+
59 void clock_gclk_init(void);
+
60 void clock_dpll_init(void);
+
61 void clock_dfll_init(void);
+
62 #endif
diff --git a/test/same54p20a_test/doc/html/conf__core_8h.html b/test/same54p20a_test/doc/html/conf__core_8h.html index f5dcba59..7ee0263e 100644 --- a/test/same54p20a_test/doc/html/conf__core_8h.html +++ b/test/same54p20a_test/doc/html/conf__core_8h.html @@ -81,14 +81,11 @@ Macros   #define CONF_CORE_CMCC_ENABLE   (0)   - -#define CONF_CORE_PORT_EVCTRL_0_ENABLE   (0) +#define CONF_CORE_PORT_EVCTRL_0_ENABLE   (0)   - -#define CONF_CORE_PORT_EVCTRL_1_ENABLE   (0) +#define CONF_CORE_PORT_EVCTRL_1_ENABLE   (0)   - -#define CONF_CORE_PORT_EVCTRL_2_ENABLE   (0) +#define CONF_CORE_PORT_EVCTRL_2_ENABLE   (0)   #define CONF_CORE_GCLK_0_ENABLE   1 @@ -381,114 +378,120 @@ Macros
Core-Master-Clock-Configuration

Configuration options for the master clock.

-#define CONF_CORE_MCLK_NVM_WAIT_STATE   0x5 + +#define CONF_CORE_MCLK_NVM_WAIT_STATE   0x5 + Define the number of wait states for the master clock.
+Can be [0-15].
+See Datasheet Reference
  #define CONF_CORE_MCLK_CPUDIV   0x1 + Define the master clock divisor. More...
 
Core-XOSC0-Configuration
-

Configuration options for XOSC0.

+

Configuration options for XOSC0.
+See Datasheet Reference

- -#define CONF_CORE_CLK_XOSC0_ENABLE   (1) +#define CONF_CORE_CLK_XOSC0_ENABLE   (1) + Enables or Disables the XOSC0 Clock. More...
  - -#define CONF_CORE_CLK_XOSC0_XTALEN   (1) +#define CONF_CORE_CLK_XOSC0_XTALEN   (1) + This bit controls the connections between the I/O pads and the external clock or crystal oscillator XOSC0: More...
  - -#define CONF_CORE_CLK_XOSC0_RUNSTDBY   (0) +#define CONF_CORE_CLK_XOSC0_RUNSTDBY   (0) + This bit controls how the XOSC0 behaves during standby sleep mode: More...
  - -#define CONF_CORE_CLK_XOSC0_ONDEMAND   (0) +#define CONF_CORE_CLK_XOSC0_ONDEMAND   (0) + The On Demand operation mode allows the oscillator XOSC0 to be enabled or disabled, depending on peripheral clock requests. More...
  - -#define CONF_CORE_CLK_XOSC0_LOWBUFGAIN   (0) +#define CONF_CORE_CLK_XOSC0_LOWBUFGAIN   (0) + The default value of LOWBUFGAIN=0 should be used to allow operating with a low amplitude oscillator. Don't use this setting except to solve stability issues. More...
  - -#define CONF_CORE_CLK_XOSC0_ENALC   (1) +#define CONF_CORE_CLK_XOSC0_ENALC   (1) + This bit controls the XOSC0 automatic loop control: More...
  - -#define CONF_CORE_CLK_XOSC0_CFDEN   (1) +#define CONF_CORE_CLK_XOSC0_CFDEN   (1) + This bit controls the XOSC0 clock failure detector: More...
  - -#define CONF_CORE_CLK_XOSC0_SWBEN   (0) +#define CONF_CORE_CLK_XOSC0_SWBEN   (0) + This bit controls the XOSC0 output clock switch back to the external clock or crystal oscillator in case of clock recovery: More...
  - -#define CONF_CORE_CLK_XOSC0_STARTUP_TIME   CONF_CORE_CLK_XOSCCTRL_STARTUP_31us +#define CONF_CORE_CLK_XOSC0_STARTUP_TIME   (0x00) + These bits select start-up time for XOSC0 according to the table below: More...
  - -#define CONF_CORE_CLK_XOSC0_FREQUENCY   12000000 +#define CONF_CORE_CLK_XOSC0_FREQUENCY   12000000 + This is the frequency of the external clock you're using for XOSC0. This can be anything from 8MHz to 48MHz. More...
 
Core-XOSC1-Configuration
-

Configuration options for XOSC1.

+

Configuration options for XOSC1.
+See Datasheet Reference

- -#define CONF_CORE_CLK_XOSC1_ENABLE   (0) +#define CONF_CORE_CLK_XOSC1_ENABLE   (0) + Enables or Disables the XOSC1 Clock. More...
  - -#define CONF_CORE_CLK_XOSC1_XTALEN   (0) +#define CONF_CORE_CLK_XOSC1_XTALEN   (0) + This bit controls the connections between the I/O pads and the external clock or crystal oscillator XOSC1: More...
  - -#define CONF_CORE_CLK_XOSC1_RUNSTDBY   (0) +#define CONF_CORE_CLK_XOSC1_RUNSTDBY   (0) + This bit controls how the XOSC1 behaves during standby sleep mode: More...
  - -#define CONF_CORE_CLK_XOSC1_ONDEMAND   (0) +#define CONF_CORE_CLK_XOSC1_ONDEMAND   (0) + The On Demand operation mode allows the oscillator XOSC1 to be enabled or disabled, depending on peripheral clock requests. More...
  - -#define CONF_CORE_CLK_XOSC1_LOWBUFGAIN   (0) +#define CONF_CORE_CLK_XOSC1_LOWBUFGAIN   (0) + The default value of LOWBUFGAIN=0 should be used to allow operating with a low amplitude oscillator. Don't use this setting except to solve stability issues. More...
  - -#define CONF_CORE_CLK_XOSC1_ENALC   (0) +#define CONF_CORE_CLK_XOSC1_ENALC   (0) + This bit controls the XOSC1 automatic loop control: More...
  - -#define CONF_CORE_CLK_XOSC1_CFDEN   (0) +#define CONF_CORE_CLK_XOSC1_CFDEN   (0) + This bit controls the XOSC1 clock failure detector: More...
  - -#define CONF_CORE_CLK_XOSC1_SWBEN   (0) +#define CONF_CORE_CLK_XOSC1_SWBEN   (0) + This bit controls the XOSC1 output clock switch back to the external clock or crystal oscillator in case of clock recovery: More...
  - -#define CONF_CORE_CLK_XOSC1_STARTUP_TIME   CONF_CORE_CLK_XOSCCTRL_STARTUP_31us +#define CONF_CORE_CLK_XOSC1_STARTUP_TIME   (0x00) + These bits select start-up time for XOSC1 according to the table below: More...
  - -#define CONF_CORE_CLK_XOSC1_FREQUENCY   12000000 +#define CONF_CORE_CLK_XOSC1_FREQUENCY   12000000 + This is the frequency of the external clock you're using for XOSC1. This can be anything from 8MHz to 48MHz. More...
 
Core-XOSC32K-Configuration
-

Configuration options for the external 32khz oscillator.

+

Configuration options for the external 32khz oscillator.
+See Datasheet Reference

- -#define CONF_CORE_CLK_XOSC32K_ENABLE   (1) +#define CONF_CORE_CLK_XOSC32K_ENABLE   (1) + Enables or Disables XOSC32K. More...
  - -#define CONF_CORE_CLK_XOSC32K_CGM   CONF_CORE_CLK_XOSC32KCTRL_CGM_STD_MODE +#define CONF_CORE_CLK_XOSC32K_CGM   (0x01) + These bits control the gain of the external crstal oscillator. More...
  - -#define CONF_CORE_CLK_XOSC32K_STARTUP_TIME   CONF_CORE_CLK_XOSC32KCTRL_STARTUP_62592us +#define CONF_CORE_CLK_XOSC32K_STARTUP_TIME   CONF_CORE_CLK_XOSC32KCTRL_STARTUP_62592us + These bits select the startup time for the oscillator. More...
  - -#define CONF_CORE_CLK_XOSC32K_ONDEMAND   (1) +#define CONF_CORE_CLK_XOSC32K_ONDEMAND   (1) + This bit controls how XOSC32K behaves when a peripheral clock request is detected. More...
  - -#define CONF_CORE_CLK_XOSC32K_RUNSTDBY   (0) +#define CONF_CORE_CLK_XOSC32K_RUNSTDBY   (0) + This bit controls how XOSC32K behaves during standby sleep mode. More...
  - -#define CONF_CORE_CLK_XOSC32K_EN1K   (0) +#define CONF_CORE_CLK_XOSC32K_EN1K   (0)   - -#define CONF_CORE_CLK_XOSC32K_EN32K   (1) +#define CONF_CORE_CLK_XOSC32K_EN32K   (1)   - -#define CONF_CORE_CLK_XOSC32K_XTALEN   (1) +#define CONF_CORE_CLK_XOSC32K_XTALEN   (1) + This bit controls the connections between the I/O pads and the external clock or crystal oscillator. More...
  - -#define CONF_CORE_CLK_XOSC32K_CFDPRESC   (0) +#define CONF_CORE_CLK_XOSC32K_CFDPRESC   (0) + This bit selects the prescaler for the CLock Failure Detector: More...
  - -#define CONF_CORE_CLK_XOSC32K_CFDEN   (0) +#define CONF_CORE_CLK_XOSC32K_CFDEN   (0) + This bit selects the Clock Failulre Detector state. More...
  - -#define CONF_CORE_CLK_XOSC32K_SWBACK   (0) +#define CONF_CORE_CLK_XOSC32K_SWBACK   (0) + This bit controls the XOSC32K output switch back to the external clock or crystal oscillator in case of clock recovery. More...
  - -#define CONF_CORE_CLK_XOSC32K_WRTLOCK   (0) +#define CONF_CORE_CLK_XOSC32K_WRTLOCK   (0) + This bit locks the XOSC32K register for future writes, effectively freezing the XOSC32K configuration. More...
 
Core-DFLL48M-Configuration

Configuration options for DFLL48M

@@ -666,7 +669,7 @@ Description pg. 724 of datasheet -

Definition at line 124 of file conf_core.h.

+

Definition at line 390 of file conf_core.h.

@@ -698,7 +701,7 @@ pg. 724 of datasheet
  • 11 => Generic clock generator 11
    • -

    Definition at line 178 of file conf_core.h.

    +

    Definition at line 444 of file conf_core.h.

    @@ -721,7 +724,7 @@ pg. 724 of datasheet pg. 724 of datasheet -

    Definition at line 132 of file conf_core.h.

    +

    Definition at line 398 of file conf_core.h.

    @@ -744,7 +747,7 @@ pg. 724 of datasheet pg. 724 of datasheet -

    Definition at line 140 of file conf_core.h.

    +

    Definition at line 406 of file conf_core.h.

    @@ -767,7 +770,7 @@ pg. 724 of datasheet pg. 725 of datasheet -

    Definition at line 148 of file conf_core.h.

    +

    Definition at line 414 of file conf_core.h.

    @@ -782,10 +785,26 @@ pg. 725 of datasheet
    -

    pg. 732 of the datasheet FILTER[3:0] | PLL Bandwidth (fn) | Damping Factor 0x0 | 92.7 kHz | 0.76 0x1 | 131 kHz | 1.08 0x2 | 46.4 kHz | 0.38 0x3 | 65.6 kHz | 0.54 0x4 | 131 kHz | 0.56 0x5 | 185 kHz | 0.79 0x6 | 65.6 kHz | 0.28 0x7 | 92.7 kHz | 0.39 0x8 | 46.4 kHz | 1.49 0x9 | 65.6 kHz | 2.11 0xA | 23.2 kHz | 0.75 0xB | 32.8 kHz | 1.06 0xC | 65.6 kHz | 1.07 0xD | 92.7 kHz | 1.51 0xE | 32.8 kHz | 0.53 0xF | 46.4 kHz | 0.75

    -

    When in doubt, leave this at its default.

    +

    pg. 732 of the datasheet

    FILTER[3:0] | PLL Bandwidth (fn) | Damping Factor
    +
    0x0 | 92.7 kHz | 0.76
    +
    0x1 | 131 kHz | 1.08
    +
    0x2 | 46.4 kHz | 0.38
    +
    0x3 | 65.6 kHz | 0.54
    +
    0x4 | 131 kHz | 0.56
    +
    0x5 | 185 kHz | 0.79
    +
    0x6 | 65.6 kHz | 0.28
    +
    0x7 | 92.7 kHz | 0.39
    +
    0x8 | 46.4 kHz | 1.49
    +
    0x9 | 65.6 kHz | 2.11
    +
    0xA | 23.2 kHz | 0.75
    +
    0xB | 32.8 kHz | 1.06
    +
    0xC | 65.6 kHz | 1.07
    +
    0xD | 92.7 kHz | 1.51
    +
    0xE | 32.8 kHz | 0.53
    +
    0xF | 46.4 kHz | 0.75
    +

    When in doubt, leave this at its default.

    -

    Definition at line 222 of file conf_core.h.

    +

    Definition at line 490 of file conf_core.h.

    @@ -819,7 +838,765 @@ pg. 725 of datasheet
    0xF | 46.4 kHz | 0.75

    When in doubt, leave this at its default.

    -

    Definition at line 267 of file conf_core.h.

    +

    Definition at line 535 of file conf_core.h.

    + + + + +

    ◆ CONF_CORE_CLK_XOSC0_CFDEN

    + +
    +
    + + + + +
    #define CONF_CORE_CLK_XOSC0_CFDEN   (1)
    +
    + +

    This bit controls the XOSC0 clock failure detector:

    +

    XOSC0 Clock Failure Detector Control

      +
    • 0 => Clock Failure Detector is disabled.
      • +
    • 1 => Clock Failure Detector is enabled.
      +See Datasheet Reference
      • +
    + +

    Definition at line 128 of file conf_core.h.

    + +
    +
    + +

    ◆ CONF_CORE_CLK_XOSC0_ENABLE

    + +
    +
    + + + + +
    #define CONF_CORE_CLK_XOSC0_ENABLE   (1)
    +
    + +

    Enables or Disables the XOSC0 Clock.

    +

    XOSC0 Enable

    + +

    Definition at line 76 of file conf_core.h.

    + +
    +
    + +

    ◆ CONF_CORE_CLK_XOSC0_ENALC

    + +
    +
    + + + + +
    #define CONF_CORE_CLK_XOSC0_ENALC   (1)
    +
    + +

    This bit controls the XOSC0 automatic loop control:

    +

    XOSC0 Automatic Loop Control

      +
    • 0 => The automatic loop control is disabled.
      • +
    • 1 => The automatic loop control is enabled. Oscillator's amplitude will be automatically adjusted during Crystal Oscillator operation.
      +See Datasheet Reference
      • +
    + +

    Definition at line 120 of file conf_core.h.

    + +
    +
    + +

    ◆ CONF_CORE_CLK_XOSC0_FREQUENCY

    + +
    +
    + + + + +
    #define CONF_CORE_CLK_XOSC0_FREQUENCY   12000000
    +
    + +

    This is the frequency of the external clock you're using for XOSC0. This can be anything from 8MHz to 48MHz.

    +

    XOSC0 Frequency

    + +

    Definition at line 165 of file conf_core.h.

    + +
    +
    + +

    ◆ CONF_CORE_CLK_XOSC0_LOWBUFGAIN

    + +
    +
    + + + + +
    #define CONF_CORE_CLK_XOSC0_LOWBUFGAIN   (0)
    +
    + +

    The default value of LOWBUFGAIN=0 should be used to allow operating with a low amplitude oscillator. Don't use this setting except to solve stability issues.

    +

    XOSC0 Low Buffer Gain Control Bit

      +
    • 0 => The low buffer gain of XOSC0 is disabled.
      • +
    • 1 => The low buffer gain of XOSC0 is enabled.
      +See Datasheet Reference
      • +
    + +

    Definition at line 112 of file conf_core.h.

    + +
    +
    + +

    ◆ CONF_CORE_CLK_XOSC0_ONDEMAND

    + +
    +
    + + + + +
    #define CONF_CORE_CLK_XOSC0_ONDEMAND   (0)
    +
    + +

    The On Demand operation mode allows the oscillator XOSC0 to be enabled or disabled, depending on peripheral clock requests.

    +

    XOSC0 On Demand Control

      +
    • 0 => Oscillator is always on.
      • +
    • 1 => The oscillator is running when a peripheral is requesting the oscillator to be used as a clock source. The oscillator is not running if no peripheral is requesting the clock source.
      +See Datasheet Reference
      • +
    + +

    Definition at line 103 of file conf_core.h.

    + +
    +
    + +

    ◆ CONF_CORE_CLK_XOSC0_RUNSTDBY

    + +
    +
    + + + + +
    #define CONF_CORE_CLK_XOSC0_RUNSTDBY   (0)
    +
    + +

    This bit controls how the XOSC0 behaves during standby sleep mode:

    +

    XOSC0 Run in Standby

      +
    • 0 => XOSC0 is not running in standby sleep mode if no peripheral requests the clock.
      • +
    • 1 => XOSC0 is running in standby sleep mode. If ONDEMAND is 1, XOSC0 will be running when a peripheral is requesting the clock. If ONDEMAND is 0, the clock source will always be running in standby sleep mode.
      +See Datasheet Reference
      • +
    + +

    Definition at line 94 of file conf_core.h.

    + +
    +
    + +

    ◆ CONF_CORE_CLK_XOSC0_STARTUP_TIME

    + +
    +
    + + + + +
    #define CONF_CORE_CLK_XOSC0_STARTUP_TIME   (0x00)
    +
    + +

    These bits select start-up time for XOSC0 according to the table below:

    +

    XOSC0 Startup Time

      +
    • 0x00 => 31us
      • +
    • 0x01 => 61us
      • +
    • 0x02 => 122us
      • +
    • 0x03 => 244us
      • +
    • 0x04 => 488us
      • +
    • 0x05 => 977us
      • +
    • 0x06 => 1953us
      • +
    • 0x07 => 3906us
      • +
    • 0x08 => 7813us
      • +
    • 0x09 => 15625us
      • +
    • 0x0A => 31250us
      • +
    • 0x0B => 62500us
      • +
    • 0x0C => 125000us
      • +
    • 0x0D => 250000us
      • +
    • 0x0E => 500000us
      • +
    • 0x0F => 1000000us
      +See Datasheet Reference
      • +
    + +

    Definition at line 159 of file conf_core.h.

    + +
    +
    + +

    ◆ CONF_CORE_CLK_XOSC0_SWBEN

    + +
    +
    + + + + +
    #define CONF_CORE_CLK_XOSC0_SWBEN   (0)
    +
    + +

    This bit controls the XOSC0 output clock switch back to the external clock or crystal oscillator in case of clock recovery:

    +

    XOSC0 Clock Switch Enable

      +
    • 0 => The clock switch back is disabled.
      • +
    • 1 => The clock switch back is enabled. This bit is reset once the XOSC0 output clock is switched back to the external clock or crystal oscillator.
      +See Datasheet Reference
      • +
    + +

    Definition at line 137 of file conf_core.h.

    + +
    +
    + +

    ◆ CONF_CORE_CLK_XOSC0_XTALEN

    + +
    +
    + + + + +
    #define CONF_CORE_CLK_XOSC0_XTALEN   (1)
    +
    + +

    This bit controls the connections between the I/O pads and the external clock or crystal oscillator XOSC0:

    +

    XOSC0 XTALEN

      +
    • 0 => External clock connected on XIN. XOUT can be used as general purpose I/O.
      • +
    • 1 => Crystal connected to XIN/XOUT.
      +See Datasheet Reference
      • +
    + +

    Definition at line 84 of file conf_core.h.

    + +
    +
    + +

    ◆ CONF_CORE_CLK_XOSC1_CFDEN

    + +
    +
    + + + + +
    #define CONF_CORE_CLK_XOSC1_CFDEN   (0)
    +
    + +

    This bit controls the XOSC1 clock failure detector:

    +

    XOSC1 Clock Failure Detector Control

      +
    • 0 => Clock Failure Detector is disabled.
      • +
    • 1 => Clock Failure Detector is enabled.
      +See Datasheet Reference
      • +
    + +

    Definition at line 232 of file conf_core.h.

    + +
    +
    + +

    ◆ CONF_CORE_CLK_XOSC1_ENABLE

    + +
    +
    + + + + +
    #define CONF_CORE_CLK_XOSC1_ENABLE   (0)
    +
    + +

    Enables or Disables the XOSC1 Clock.

    +

    XOSC1 Enable

    + +

    Definition at line 180 of file conf_core.h.

    + +
    +
    + +

    ◆ CONF_CORE_CLK_XOSC1_ENALC

    + +
    +
    + + + + +
    #define CONF_CORE_CLK_XOSC1_ENALC   (0)
    +
    + +

    This bit controls the XOSC1 automatic loop control:

    +

    XOSC1 Automatic Loop Control

      +
    • 0 => The automatic loop control is disabled.
      • +
    • 1 => The automatic loop control is enabled. Oscillator's amplitude will be automatically adjusted during Crystal Oscillator operation.
      +See Datasheet Reference
      • +
    + +

    Definition at line 224 of file conf_core.h.

    + +
    +
    + +

    ◆ CONF_CORE_CLK_XOSC1_FREQUENCY

    + +
    +
    + + + + +
    #define CONF_CORE_CLK_XOSC1_FREQUENCY   12000000
    +
    + +

    This is the frequency of the external clock you're using for XOSC1. This can be anything from 8MHz to 48MHz.

    +

    XOSC1 Frequency

    + +

    Definition at line 269 of file conf_core.h.

    + +
    +
    + +

    ◆ CONF_CORE_CLK_XOSC1_LOWBUFGAIN

    + +
    +
    + + + + +
    #define CONF_CORE_CLK_XOSC1_LOWBUFGAIN   (0)
    +
    + +

    The default value of LOWBUFGAIN=0 should be used to allow operating with a low amplitude oscillator. Don't use this setting except to solve stability issues.

    +

    XOSC1 Low Buffer Gain Control Bit

      +
    • 0 => The low buffer gain of XOSC1 is disabled.
      • +
    • 1 => The low buffer gain of XOSC1 is enabled.
      +See Datasheet Reference
      • +
    + +

    Definition at line 216 of file conf_core.h.

    + +
    +
    + +

    ◆ CONF_CORE_CLK_XOSC1_ONDEMAND

    + +
    +
    + + + + +
    #define CONF_CORE_CLK_XOSC1_ONDEMAND   (0)
    +
    + +

    The On Demand operation mode allows the oscillator XOSC1 to be enabled or disabled, depending on peripheral clock requests.

    +

    XOSC1 On Demand Control

      +
    • 0 => Oscillator is always on.
      • +
    • 1 => The oscillator is running when a peripheral is requesting the oscillator to be used as a clock source. The oscillator is not running if no peripheral is requesting the clock source.
      +See Datasheet Reference
      • +
    + +

    Definition at line 207 of file conf_core.h.

    + +
    +
    + +

    ◆ CONF_CORE_CLK_XOSC1_RUNSTDBY

    + +
    +
    + + + + +
    #define CONF_CORE_CLK_XOSC1_RUNSTDBY   (0)
    +
    + +

    This bit controls how the XOSC1 behaves during standby sleep mode:

    +

    XOSC1 Run in Standby

      +
    • 0 => XOSC1 is not running in standby sleep mode if no peripheral requests the clock.
      • +
    • 1 => XOSC1 is running in standby sleep mode. If ONDEMAND is 1, XOSC1 will be running when a peripheral is requesting the clock. If ONDEMAND is 0, the clock source will always be running in standby sleep mode.
      +See Datasheet Reference
      • +
    + +

    Definition at line 198 of file conf_core.h.

    + +
    +
    + +

    ◆ CONF_CORE_CLK_XOSC1_STARTUP_TIME

    + +
    +
    + + + + +
    #define CONF_CORE_CLK_XOSC1_STARTUP_TIME   (0x00)
    +
    + +

    These bits select start-up time for XOSC1 according to the table below:

    +

    XOSC1 Startup Time

      +
    • 0x00 => 31us
      • +
    • 0x01 => 61us
      • +
    • 0x02 => 122us
      • +
    • 0x03 => 244us
      • +
    • 0x04 => 488us
      • +
    • 0x05 => 977us
      • +
    • 0x06 => 1953us
      • +
    • 0x07 => 3906us
      • +
    • 0x08 => 7813us
      • +
    • 0x09 => 15625us
      • +
    • 0x0A => 31250us
      • +
    • 0x0B => 62500us
      • +
    • 0x0C => 125000us
      • +
    • 0x0D => 250000us
      • +
    • 0x0E => 500000us
      • +
    • 0x0F => 1000000us
      +See Datasheet Reference
      • +
    + +

    Definition at line 263 of file conf_core.h.

    + +
    +
    + +

    ◆ CONF_CORE_CLK_XOSC1_SWBEN

    + +
    +
    + + + + +
    #define CONF_CORE_CLK_XOSC1_SWBEN   (0)
    +
    + +

    This bit controls the XOSC1 output clock switch back to the external clock or crystal oscillator in case of clock recovery:

    +

    XOSC1 Clock Switch Enable

      +
    • 0 => The clock switch back is disabled.
      • +
    • 1 => The clock switch back is enabled. This bit is reset once the XOSC1 output clock is switched back to the external clock or crystal oscillator.
      +See Datasheet Reference
      • +
    + +

    Definition at line 241 of file conf_core.h.

    + +
    +
    + +

    ◆ CONF_CORE_CLK_XOSC1_XTALEN

    + +
    +
    + + + + +
    #define CONF_CORE_CLK_XOSC1_XTALEN   (0)
    +
    + +

    This bit controls the connections between the I/O pads and the external clock or crystal oscillator XOSC1:

    +

    XOSC1 XTALEN

      +
    • 0 => External clock connected on XIN. XOUT can be used as general purpose I/O.
      • +
    • 1 => Crystal connected to XIN/XOUT.
      +See Datasheet Reference
      • +
    + +

    Definition at line 188 of file conf_core.h.

    + +
    +
    + +

    ◆ CONF_CORE_CLK_XOSC32K_CFDEN

    + +
    +
    + + + + +
    #define CONF_CORE_CLK_XOSC32K_CFDEN   (0)
    +
    + +

    This bit selects the Clock Failulre Detector state.

    +

    XOSC32K Clock Failure Detector Control

    + +

    Definition at line 360 of file conf_core.h.

    + +
    +
    + +

    ◆ CONF_CORE_CLK_XOSC32K_CFDPRESC

    + +
    +
    + + + + +
    #define CONF_CORE_CLK_XOSC32K_CFDPRESC   (0)
    +
    + +

    This bit selects the prescaler for the CLock Failure Detector:

    +

    XOSC32K Clock Failure Detector Prescaler

      +
    • 0 => The CFD safe clock frequency is the OSCULP32K frequency.
      • +
    • 1 => The CFD safe clock frequency is the OSCULP32K frequency divided by 2.
      +See Datasheet Reference
      • +
    + +

    Definition at line 352 of file conf_core.h.

    + +
    +
    + +

    ◆ CONF_CORE_CLK_XOSC32K_CGM

    + +
    +
    + + + + +
    #define CONF_CORE_CLK_XOSC32K_CGM   (0x01)
    +
    + +

    These bits control the gain of the external crstal oscillator.

    +

    XOSC32K Control Gain Mode

      +
    • 0x00 => Low Power Mode
      • +
    • 0x01 => Standard Mode (Default)
      • +
    • 0x02 => High Speed Mode
      +See Datasheet Reference
      • +
    + +

    Definition at line 293 of file conf_core.h.

    + +
    +
    + +

    ◆ CONF_CORE_CLK_XOSC32K_EN1K

    + +
    +
    + + + + +
    #define CONF_CORE_CLK_XOSC32K_EN1K   (0)
    +
    +

    XOSC32K 1KHz Output Control

    + +

    Definition at line 329 of file conf_core.h.

    + +
    +
    + +

    ◆ CONF_CORE_CLK_XOSC32K_EN32K

    + +
    +
    + + + + +
    #define CONF_CORE_CLK_XOSC32K_EN32K   (1)
    +
    +

    XOSC32K 32KHz Output Control

    + +

    Definition at line 336 of file conf_core.h.

    + +
    +
    + +

    ◆ CONF_CORE_CLK_XOSC32K_ENABLE

    + +
    +
    + + + + +
    #define CONF_CORE_CLK_XOSC32K_ENABLE   (1)
    +
    + +

    Enables or Disables XOSC32K.

    +

    XOSC32K Enable

    + +

    Definition at line 284 of file conf_core.h.

    + +
    +
    + +

    ◆ CONF_CORE_CLK_XOSC32K_ONDEMAND

    + +
    +
    + + + + +
    #define CONF_CORE_CLK_XOSC32K_ONDEMAND   (1)
    +
    + +

    This bit controls how XOSC32K behaves when a peripheral clock request is detected.

    +

    XOSC32K On Demand Control

    + +

    Definition at line 314 of file conf_core.h.

    + +
    +
    + +

    ◆ CONF_CORE_CLK_XOSC32K_RUNSTDBY

    + +
    +
    + + + + +
    #define CONF_CORE_CLK_XOSC32K_RUNSTDBY   (0)
    +
    + +

    This bit controls how XOSC32K behaves during standby sleep mode.

    +

    XOSC32K Run in Standby

      +
    • 0 => Run if requested by peripheral.
      • +
    • 1 => Run if requested by peripheral OR always run depending ONDEMAND value.
      +See Datasheet Reference
      • +
    + +

    Definition at line 322 of file conf_core.h.

    + +
    +
    + +

    ◆ CONF_CORE_CLK_XOSC32K_STARTUP_TIME

    + +
    +
    + + + + +
    #define CONF_CORE_CLK_XOSC32K_STARTUP_TIME   CONF_CORE_CLK_XOSC32KCTRL_STARTUP_62592us
    +
    + +

    These bits select the startup time for the oscillator.

    +

    XOSC32K Startup Time

      +
    • 0x00 => 62.592ms
      • +
    • 0x01 => 125.092ms
      • +
    • 0x02 => 500.092ms
      • +
    • 0x03 => 1000.0092ms
      • +
    • 0x04 => 2000.0092ms
      • +
    • 0x05 => 4000.0092ms
      • +
    • 0x06 => 8000.0092ms
      +See Datasheet Reference
      • +
    + +

    Definition at line 306 of file conf_core.h.

    + +
    +
    + +

    ◆ CONF_CORE_CLK_XOSC32K_SWBACK

    + +
    +
    + + + + +
    #define CONF_CORE_CLK_XOSC32K_SWBACK   (0)
    +
    + +

    This bit controls the XOSC32K output switch back to the external clock or crystal oscillator in case of clock recovery.

    +

    XOSC32K Clock Switch Back

      +
    • 0 => The clock switch is disabled.
      • +
    • 1 => The clock switch is enabled. This bit is reset when XOSC32K output is switched back to the external clock or crystal oscillator.
      +See Datasheet Reference
      • +
    + +

    Definition at line 368 of file conf_core.h.

    + +
    +
    + +

    ◆ CONF_CORE_CLK_XOSC32K_WRTLOCK

    + +
    +
    + + + + +
    #define CONF_CORE_CLK_XOSC32K_WRTLOCK   (0)
    +
    + +

    This bit locks the XOSC32K register for future writes, effectively freezing the XOSC32K configuration.

    +

    XOSC32K Write Lock

      +
    • 0 => XOSC32K configuration is not locked.
      • +
    • 1 => XOSC32K configuration is locked.
      +See Datasheet Reference
      • +
    + +

    Definition at line 376 of file conf_core.h.

    + +
    +
    + +

    ◆ CONF_CORE_CLK_XOSC32K_XTALEN

    + +
    +
    + + + + +
    #define CONF_CORE_CLK_XOSC32K_XTALEN   (1)
    +
    + +

    This bit controls the connections between the I/O pads and the external clock or crystal oscillator.

    +

    XOSC32K Crystal Oscillator Enable

      +
    • 0 => External clock is connected on XIN32. XOUT32 can be used as general-purpose I/O.
      • +
    • 1 => Crystal connected to XIN32/XOUT32.
      +See Datasheet Reference
      • +
    + +

    Definition at line 344 of file conf_core.h.

    @@ -839,7 +1616,7 @@ pg. 725 of datasheet
  • 1 => Enabled
    • -

    Definition at line 52 of file conf_core.h.

    +

    Definition at line 55 of file conf_core.h.

    @@ -856,10 +1633,11 @@ pg. 725 of datasheet

    Define whether the DMAC is enabled or not.

    -

    Definition at line 45 of file conf_core.h.

    +

    Definition at line 48 of file conf_core.h.

    @@ -874,7 +1652,9 @@ pg. 725 of datasheet
    -

    Define the master clock divisor.

      + +

      Define the master clock divisor.

      +
      • 0x1 => Clock Divide by 1
      • 0x2 => Clock Divide by 2
      • 0x4 => Clock Divide by 4
        • @@ -882,27 +1662,62 @@ pg. 725 of datasheet
      • 0x10 => Clock Divide by 16
      • 0x20 => Clock Divide by 32
      • 0x40 => Clock Divide by 64
        • -
      • 0x80 => Clock Divide by 128
        • +
      • 0x80 => Clock Divide by 128
        +See Datasheet Reference
      -

      Definition at line 36 of file conf_core.h.

      +

      Definition at line 38 of file conf_core.h.

      + +
    + + +

    ◆ CONF_CORE_PORT_EVCTRL_0_ENABLE

    + +
    +
    + + + + +
    #define CONF_CORE_PORT_EVCTRL_0_ENABLE   (0)
    +
    +

    Currently Unused

    + +

    Definition at line 58 of file conf_core.h.

    + +
    +
    + +

    ◆ CONF_CORE_PORT_EVCTRL_1_ENABLE

    + +
    +
    + + + + +
    #define CONF_CORE_PORT_EVCTRL_1_ENABLE   (0)
    +
    +

    Currently Unused

    + +

    Definition at line 60 of file conf_core.h.

    - -

    ◆ CONF_CORE_MCLK_NVM_WAIT_STATE

    + +

    ◆ CONF_CORE_PORT_EVCTRL_2_ENABLE

    - +
    #define CONF_CORE_MCLK_NVM_WAIT_STATE   0x5#define CONF_CORE_PORT_EVCTRL_2_ENABLE   (0)
    -

    Define the number of wait states for the master clock. Can be [0-15].

    +

    Currently Unused

    -

    Definition at line 23 of file conf_core.h.

    +

    Definition at line 62 of file conf_core.h.

    diff --git a/test/same54p20a_test/doc/html/conf__core_8h_source.html b/test/same54p20a_test/doc/html/conf__core_8h_source.html index 1681016a..d16ec690 100644 --- a/test/same54p20a_test/doc/html/conf__core_8h_source.html +++ b/test/same54p20a_test/doc/html/conf__core_8h_source.html @@ -74,221 +74,252 @@ $(function() {
    11 #define _CONF_CLOCKS_H_
    12 #include "clocks.h"
    13 
    -
    23 #define CONF_CORE_MCLK_NVM_WAIT_STATE 0x5
    -
    24 
    -
    36 #define CONF_CORE_MCLK_CPUDIV 0x1
    -
    37 
    -
    45 #define CONF_CORE_DMA_ENABLE (0)
    -
    46 
    -
    52 #define CONF_CORE_CMCC_ENABLE (0)
    -
    53 
    -
    54 #define CONF_CORE_PORT_EVCTRL_0_ENABLE (0)
    -
    55 #define CONF_CORE_PORT_EVCTRL_1_ENABLE (0)
    -
    56 #define CONF_CORE_PORT_EVCTRL_2_ENABLE (0)
    -
    57 
    -
    62 #define CONF_CORE_CLK_XOSC0_ENABLE (1)
    -
    63 #define CONF_CORE_CLK_XOSC0_XTALEN (1)
    -
    64 #define CONF_CORE_CLK_XOSC0_RUNSTDBY (0)
    -
    65 #define CONF_CORE_CLK_XOSC0_ONDEMAND (0)
    -
    66 #define CONF_CORE_CLK_XOSC0_LOWBUFGAIN (0)
    -
    67 #define CONF_CORE_CLK_XOSC0_ENALC (1)
    -
    68 #define CONF_CORE_CLK_XOSC0_CFDEN (1)
    -
    69 #define CONF_CORE_CLK_XOSC0_SWBEN (0)
    -
    70 #define CONF_CORE_CLK_XOSC0_STARTUP_TIME CONF_CORE_CLK_XOSCCTRL_STARTUP_31us
    -
    71 #define CONF_CORE_CLK_XOSC0_FREQUENCY 12000000
    -
    72 
    -
    80 #define CONF_CORE_CLK_XOSC1_ENABLE (0)
    -
    81 #define CONF_CORE_CLK_XOSC1_XTALEN (0)
    -
    82 #define CONF_CORE_CLK_XOSC1_RUNSTDBY (0)
    -
    83 #define CONF_CORE_CLK_XOSC1_ONDEMAND (0)
    -
    84 #define CONF_CORE_CLK_XOSC1_LOWBUFGAIN (0)
    -
    85 #define CONF_CORE_CLK_XOSC1_ENALC (0)
    -
    86 #define CONF_CORE_CLK_XOSC1_CFDEN (0)
    -
    87 #define CONF_CORE_CLK_XOSC1_SWBEN (0)
    -
    88 #define CONF_CORE_CLK_XOSC1_STARTUP_TIME CONF_CORE_CLK_XOSCCTRL_STARTUP_31us
    -
    89 #define CONF_CORE_CLK_XOSC1_FREQUENCY 12000000
    -
    90 
    -
    98 #define CONF_CORE_CLK_XOSC32K_ENABLE (1)
    -
    99 #define CONF_CORE_CLK_XOSC32K_CGM CONF_CORE_CLK_XOSC32KCTRL_CGM_STD_MODE
    -
    100 #define CONF_CORE_CLK_XOSC32K_STARTUP_TIME CONF_CORE_CLK_XOSC32KCTRL_STARTUP_62592us
    -
    101 #define CONF_CORE_CLK_XOSC32K_ONDEMAND (1)
    -
    102 #define CONF_CORE_CLK_XOSC32K_RUNSTDBY (0)
    -
    103 #define CONF_CORE_CLK_XOSC32K_EN1K (0)
    -
    104 #define CONF_CORE_CLK_XOSC32K_EN32K (1)
    -
    105 #define CONF_CORE_CLK_XOSC32K_XTALEN (1)
    -
    106 #define CONF_CORE_CLK_XOSC32K_CFDPRESC (0)
    -
    107 #define CONF_CORE_CLK_XOSC32K_CFDEN (0)
    -
    108 #define CONF_CORE_CLK_XOSC32K_SWBACK (0)
    -
    109 #define CONF_CORE_CLK_XOSC32K_WRTLOCK (0)
    -
    110 
    -
    124 #define CONF_CORE_CLK_DFLL_ENABLE (1)
    -
    125 
    -
    132 #define CONF_CORE_CLK_DFLL_ONDEMAND (0)
    -
    133 
    -
    140 #define CONF_CORE_CLK_DFLL_RUNSTDBY (0)
    -
    141 
    -
    148 #define CONF_CORE_CLK_DFLL_WAITLOCK (0)
    -
    149 #define CONF_CORE_CLK_DFLL_BPLKC (0)
    -
    150 #define CONF_CORE_CLK_DFLL_QLDIS (0)
    -
    151 #define CONF_CORE_CLK_DFLL_CCDIS (1)
    -
    152 #define CONF_CORE_CLK_DFLL_USBCRM (1)
    -
    153 #define CONF_CORE_CLK_DFLL_LLAW (0)
    -
    154 #define CONF_CORE_CLK_DFLL_STABLE_FCALIB CONF_CORE_CLK_DFLLCTRL_STABLE_FCALIB_NOT_FIXED
    -
    155 #define CONF_CORE_CLK_DFLL_MODE 0x01
    -
    156 #define CONF_CORE_CLK_DFLL_DIFF_VAL 0
    -
    157 #define CONF_CORE_CLK_DFLL_COARSE_VAL (0x1f / 4)
    -
    158 #define CONF_CORE_CLK_DFLL_FINE_VAL 128
    -
    159 #define CONF_CORE_CLK_DFLL_CSTEP_VAL 1
    -
    160 #define CONF_CORE_CLK_DFLL_FSTEP_VAL 1
    -
    161 #define CONF_CORE_CLK_DFLL_MUL_VAL (48000000)
    -
    162 
    -
    178 #define CONF_CORE_CLK_DFLL_GCLK_SRC 3
    -
    179 #define CONF_CORE_CLK_DFLL_OVERWRITE_CAL 0
    -
    180 
    -
    187 #define CONF_CORE_CLK_DPLL0_ENABLE (1)
    -
    188 #define CONF_CORE_CLK_DPLL0_ONDEMAND (0)
    -
    189 #define CONF_CORE_CLK_DPLL0_RUNSTDBY (0)
    -
    190 #define CONF_CORE_CLK_DPLL0_LDRFRAC_VAL 0
    -
    191 #define CONF_CORE_CLK_DPLL0_LDR_VAL (119)
    -
    192 #define CONF_CORE_CLK_DPLL0_DIV_VAL (5)
    -
    193 #define CONF_CORE_CLK_DPLL0_DCOEN 0
    -
    194 #define CONF_CORE_CLK_DPLL0_DCOFILTER CONF_CORE_CLK_DPLLCTRL_DCOFILTER_3210KHZ
    -
    195 #define CONF_CORE_CLK_DPLL0_LBYPASS 1
    -
    196 #define CONF_CORE_CLK_DPLL0_LTIME 0
    -
    197 #define CONF_CORE_CLK_DPLL0_WUF 0
    -
    198 #define CONF_CORE_CLK_DPLL0_GCLK_SRC GCLK_GENCTRL_SRC_XOSC0
    -
    199 #define CONF_CORE_CLK_DPLL0_REFCLK CONF_CORE_CLK_DPLLCTRL_REFCLK_XOSC0
    -
    200 
    -
    222 #define CONF_CORE_CLK_DPLL0_FILTER 0x0
    -
    223 
    -
    230 #define CONF_CORE_CLK_DPLL1_ENABLE (0)
    -
    231 #define CONF_CORE_CLK_DPLL1_ONDEMAND (0)
    -
    232 #define CONF_CORE_CLK_DPLL1_RUNSTDBY (0)
    -
    233 #define CONF_CORE_CLK_DPLL1_LDRFRAC_VAL 0
    -
    234 #define CONF_CORE_CLK_DPLL1_LDR_VAL (0)
    -
    235 #define CONF_CORE_CLK_DPLL1_DIV_VAL (0)
    -
    236 #define CONF_CORE_CLK_DPLL1_DCOEN 0
    -
    237 #define CONF_CORE_CLK_DPLL1_DCOFILTER CONF_CORE_CLK_DPLLCTRL_DCOFILTER_3210KHZ
    -
    238 #define CONF_CORE_CLK_DPLL1_LBYPASS 0
    -
    239 #define CONF_CORE_CLK_DPLL1_LTIME 0
    -
    240 #define CONF_CORE_CLK_DPLL1_WUF 0
    -
    241 #define CONF_CORE_CLK_DPLL1_GCLK_SRC GCLK_GENCTRL_SRC_XOSC0
    -
    242 #define CONF_CORE_CLK_DPLL1_REFCLK CONF_CORE_CLK_DPLLCTRL_REFCLK_XOSC0
    -
    243 
    -
    267 #define CONF_CORE_CLK_DPLL1_FILTER 0x0
    -
    268 
    -
    271 // GCLK Generators Config
    -
    272 #define CONF_CORE_GCLK_0_ENABLE 1
    -
    273 #define CONF_CORE_GCLK_0_RUN_IN_STANDBY 1
    -
    274 #define CONF_CORE_GCLK_0_CLOCK_SOURCE GCLK_GENCTRL_SRC_XOSC0
    -
    275 #define CONF_CORE_GCLK_0_DIV_VAL 1
    -
    276 #define CONF_CORE_GCLK_0_DIVSEL 0
    -
    277 #define CONF_CORE_GCLK_0_OUTPUT_ENABLE 1
    -
    278 #define CONF_CORE_GCLK_0_OUTPUT_OFF_VALUE 1
    -
    279 #define CONF_CORE_GCLK_0_IDC 1
    -
    280 
    -
    281 #define CONF_CORE_GCLK_1_ENABLE 0
    -
    282 #define CONF_CORE_GCLK_1_RUN_IN_STANDBY 0
    -
    283 #define CONF_CORE_GCLK_1_CLOCK_SOURCE GCLK_GENCTRL_SRC_XOSC0
    -
    284 #define CONF_CORE_GCLK_1_DIV_VAL 1
    -
    285 #define CONF_CORE_GCLK_1_DIVSEL 0
    -
    286 #define CONF_CORE_GCLK_1_OUTPUT_ENABLE 0
    -
    287 #define CONF_CORE_GCLK_1_OUTPUT_OFF_VALUE 0
    -
    288 #define CONF_CORE_GCLK_1_IDC 0
    -
    289 
    -
    290 #define CONF_CORE_GCLK_2_ENABLE 0
    -
    291 #define CONF_CORE_GCLK_2_RUN_IN_STANDBY 0
    -
    292 #define CONF_CORE_GCLK_2_CLOCK_SOURCE GCLK_GENCTRL_SRC_XOSC0
    -
    293 #define CONF_CORE_GCLK_2_DIV_VAL 1
    -
    294 #define CONF_CORE_GCLK_2_DIVSEL 0
    -
    295 #define CONF_CORE_GCLK_2_OUTPUT_ENABLE 0
    -
    296 #define CONF_CORE_GCLK_2_OUTPUT_OFF_VALUE 0
    -
    297 #define CONF_CORE_GCLK_2_IDC 0
    -
    298 
    -
    299 #define CONF_CORE_GCLK_3_ENABLE 1
    -
    300 #define CONF_CORE_GCLK_3_RUN_IN_STANDBY 0
    -
    301 #define CONF_CORE_GCLK_3_CLOCK_SOURCE GCLK_GENCTRL_SRC_XOSC32K
    -
    302 #define CONF_CORE_GCLK_3_DIV_VAL 1
    -
    303 #define CONF_CORE_GCLK_3_DIVSEL 0
    -
    304 #define CONF_CORE_GCLK_3_OUTPUT_ENABLE 0
    -
    305 #define CONF_CORE_GCLK_3_OUTPUT_OFF_VALUE 0
    -
    306 #define CONF_CORE_GCLK_3_IDC 0
    +
    24 #define CONF_CORE_MCLK_NVM_WAIT_STATE 0x5
    +
    25 
    +
    38 #define CONF_CORE_MCLK_CPUDIV 0x1
    +
    39 
    +
    48 #define CONF_CORE_DMA_ENABLE (0)
    +
    49 
    +
    55 #define CONF_CORE_CMCC_ENABLE (0)
    +
    56 
    +
    58 #define CONF_CORE_PORT_EVCTRL_0_ENABLE (0)
    +
    59 
    +
    60 #define CONF_CORE_PORT_EVCTRL_1_ENABLE (0)
    +
    61 
    +
    62 #define CONF_CORE_PORT_EVCTRL_2_ENABLE (0)
    +
    63 
    +
    76 #define CONF_CORE_CLK_XOSC0_ENABLE (1)
    +
    77 
    +
    84 #define CONF_CORE_CLK_XOSC0_XTALEN (1)
    +
    85 
    +
    94 #define CONF_CORE_CLK_XOSC0_RUNSTDBY (0)
    +
    95 
    +
    103 #define CONF_CORE_CLK_XOSC0_ONDEMAND (0)
    +
    104 
    +
    112 #define CONF_CORE_CLK_XOSC0_LOWBUFGAIN (0)
    +
    113 
    +
    120 #define CONF_CORE_CLK_XOSC0_ENALC (1)
    +
    121 
    +
    128 #define CONF_CORE_CLK_XOSC0_CFDEN (1)
    +
    129 
    +
    137 #define CONF_CORE_CLK_XOSC0_SWBEN (0)
    +
    138 
    +
    159 #define CONF_CORE_CLK_XOSC0_STARTUP_TIME (0x00)
    +
    160 
    +
    165 #define CONF_CORE_CLK_XOSC0_FREQUENCY 12000000
    +
    166 
    +
    180 #define CONF_CORE_CLK_XOSC1_ENABLE (0)
    +
    181 
    +
    188 #define CONF_CORE_CLK_XOSC1_XTALEN (0)
    +
    189 
    +
    198 #define CONF_CORE_CLK_XOSC1_RUNSTDBY (0)
    +
    199 
    +
    207 #define CONF_CORE_CLK_XOSC1_ONDEMAND (0)
    +
    208 
    +
    216 #define CONF_CORE_CLK_XOSC1_LOWBUFGAIN (0)
    +
    217 
    +
    224 #define CONF_CORE_CLK_XOSC1_ENALC (0)
    +
    225 
    +
    232 #define CONF_CORE_CLK_XOSC1_CFDEN (0)
    +
    233 
    +
    241 #define CONF_CORE_CLK_XOSC1_SWBEN (0)
    +
    242 
    +
    263 #define CONF_CORE_CLK_XOSC1_STARTUP_TIME (0x00)
    +
    264 
    +
    269 #define CONF_CORE_CLK_XOSC1_FREQUENCY 12000000
    +
    270 
    +
    284 #define CONF_CORE_CLK_XOSC32K_ENABLE (1)
    +
    285 
    +
    293 #define CONF_CORE_CLK_XOSC32K_CGM (0x01)
    +
    294 
    +
    306 #define CONF_CORE_CLK_XOSC32K_STARTUP_TIME CONF_CORE_CLK_XOSC32KCTRL_STARTUP_62592us
    307 
    -
    308 #define CONF_CORE_GCLK_4_ENABLE 0
    -
    309 #define CONF_CORE_GCLK_4_RUN_IN_STANDBY 0
    -
    310 #define CONF_CORE_GCLK_4_CLOCK_SOURCE GCLK_GENCTRL_SRC_XOSC0
    -
    311 #define CONF_CORE_GCLK_4_DIV_VAL 1
    -
    312 #define CONF_CORE_GCLK_4_DIVSEL 1
    -
    313 #define CONF_CORE_GCLK_4_OUTPUT_ENABLE 0
    -
    314 #define CONF_CORE_GCLK_4_OUTPUT_OFF_VALUE 0
    -
    315 #define CONF_CORE_GCLK_4_IDC 0
    -
    316 
    -
    317 #define CONF_CORE_GCLK_5_ENABLE 0
    -
    318 #define CONF_CORE_GCLK_5_RUN_IN_STANDBY 0
    -
    319 #define CONF_CORE_GCLK_5_CLOCK_SOURCE GCLK_GENCTRL_SRC_XOSC0
    -
    320 #define CONF_CORE_GCLK_5_DIV_VAL 1
    -
    321 #define CONF_CORE_GCLK_5_DIVSEL 0
    -
    322 #define CONF_CORE_GCLK_5_OUTPUT_ENABLE 0
    -
    323 #define CONF_CORE_GCLK_5_OUTPUT_OFF_VALUE 0
    -
    324 #define CONF_CORE_GCLK_5_IDC 0
    -
    325 
    -
    326 #define CONF_CORE_GCLK_6_ENABLE 0
    -
    327 #define CONF_CORE_GCLK_6_RUN_IN_STANDBY 0
    -
    328 #define CONF_CORE_GCLK_6_CLOCK_SOURCE GCLK_GENCTRL_SRC_XOSC0
    -
    329 #define CONF_CORE_GCLK_6_DIV_VAL 1
    -
    330 #define CONF_CORE_GCLK_6_DIVSEL 0
    -
    331 #define CONF_CORE_GCLK_6_OUTPUT_ENABLE 0
    -
    332 #define CONF_CORE_GCLK_6_OUTPUT_OFF_VALUE 0
    -
    333 #define CONF_CORE_GCLK_6_IDC 0
    -
    334 
    -
    335 #define CONF_CORE_GCLK_7_ENABLE 0
    -
    336 #define CONF_CORE_GCLK_7_RUN_IN_STANDBY 0
    -
    337 #define CONF_CORE_GCLK_7_CLOCK_SOURCE GCLK_GENCTRL_SRC_XOSC0
    -
    338 #define CONF_CORE_GCLK_7_DIV_VAL 1
    -
    339 #define CONF_CORE_GCLK_7_DIVSEL 0
    -
    340 #define CONF_CORE_GCLK_7_OUTPUT_ENABLE 0
    -
    341 #define CONF_CORE_GCLK_7_OUTPUT_OFF_VALUE 0
    -
    342 #define CONF_CORE_GCLK_7_IDC 0
    -
    343 
    -
    344 #define CONF_CORE_GCLK_8_ENABLE 0
    -
    345 #define CONF_CORE_GCLK_8_RUN_IN_STANDBY 0
    -
    346 #define CONF_CORE_GCLK_8_CLOCK_SOURCE GCLK_GENCTRL_SRC_XOSC0
    -
    347 #define CONF_CORE_GCLK_8_DIV_VAL 1
    -
    348 #define CONF_CORE_GCLK_8_DIVSEL 0
    -
    349 #define CONF_CORE_GCLK_8_OUTPUT_ENABLE 0
    -
    350 #define CONF_CORE_GCLK_8_OUTPUT_OFF_VALUE 0
    -
    351 #define CONF_CORE_GCLK_8_IDC 0
    -
    352 
    -
    353 #define CONF_CORE_GCLK_9_ENABLE 0
    -
    354 #define CONF_CORE_GCLK_9_RUN_IN_STANDBY 0
    -
    355 #define CONF_CORE_GCLK_9_CLOCK_SOURCE GCLK_GENCTRL_SRC_XOSC0
    -
    356 #define CONF_CORE_GCLK_9_DIV_VAL 1
    -
    357 #define CONF_CORE_GCLK_9_DIVSEL 0
    -
    358 #define CONF_CORE_GCLK_9_OUTPUT_ENABLE 0
    -
    359 #define CONF_CORE_GCLK_9_OUTPUT_OFF_VALUE 0
    -
    360 #define CONF_CORE_GCLK_9_IDC 0
    +
    314 #define CONF_CORE_CLK_XOSC32K_ONDEMAND (1)
    +
    315 
    +
    322 #define CONF_CORE_CLK_XOSC32K_RUNSTDBY (0)
    +
    323 
    +
    329 #define CONF_CORE_CLK_XOSC32K_EN1K (0)
    +
    330 
    +
    336 #define CONF_CORE_CLK_XOSC32K_EN32K (1)
    +
    337 
    +
    344 #define CONF_CORE_CLK_XOSC32K_XTALEN (1)
    +
    345 
    +
    352 #define CONF_CORE_CLK_XOSC32K_CFDPRESC (0)
    +
    353 
    +
    360 #define CONF_CORE_CLK_XOSC32K_CFDEN (0)
    361 
    -
    362 #define CONF_CORE_GCLK_10_ENABLE 0
    -
    363 #define CONF_CORE_GCLK_10_RUN_IN_STANDBY 0
    -
    364 #define CONF_CORE_GCLK_10_CLOCK_SOURCE GCLK_GENCTRL_SRC_XOSC0
    -
    365 #define CONF_CORE_GCLK_10_DIV_VAL 1
    -
    366 #define CONF_CORE_GCLK_10_DIVSEL 0
    -
    367 #define CONF_CORE_GCLK_10_OUTPUT_ENABLE 0
    -
    368 #define CONF_CORE_GCLK_10_OUTPUT_OFF_VALUE 0
    -
    369 #define CONF_CORE_GCLK_10_IDC 0
    -
    370 
    -
    371 #define CONF_CORE_GCLK_11_ENABLE 0
    -
    372 #define CONF_CORE_GCLK_11_RUN_IN_STANDBY 0
    -
    373 #define CONF_CORE_GCLK_11_CLOCK_SOURCE GCLK_GENCTRL_SRC_XOSC0
    -
    374 #define CONF_CORE_GCLK_11_DIV_VAL 1
    -
    375 #define CONF_CORE_GCLK_11_DIVSEL 0
    -
    376 #define CONF_CORE_GCLK_11_OUTPUT_ENABLE 0
    -
    377 #define CONF_CORE_GCLK_11_OUTPUT_OFF_VALUE 0
    -
    378 #define CONF_CORE_GCLK_11_IDC 0
    -
    379 
    -
    380 
    -
    381 
    -
    382 #endif
    +
    368 #define CONF_CORE_CLK_XOSC32K_SWBACK (0)
    +
    369 
    +
    376 #define CONF_CORE_CLK_XOSC32K_WRTLOCK (0)
    +
    377 
    +
    390 #define CONF_CORE_CLK_DFLL_ENABLE (1)
    +
    391 
    +
    398 #define CONF_CORE_CLK_DFLL_ONDEMAND (0)
    +
    399 
    +
    406 #define CONF_CORE_CLK_DFLL_RUNSTDBY (0)
    +
    407 
    +
    414 #define CONF_CORE_CLK_DFLL_WAITLOCK (0)
    +
    415 #define CONF_CORE_CLK_DFLL_BPLKC (0)
    +
    416 #define CONF_CORE_CLK_DFLL_QLDIS (0)
    +
    417 #define CONF_CORE_CLK_DFLL_CCDIS (1)
    +
    418 #define CONF_CORE_CLK_DFLL_USBCRM (1)
    +
    419 #define CONF_CORE_CLK_DFLL_LLAW (0)
    +
    420 #define CONF_CORE_CLK_DFLL_STABLE_FCALIB CONF_CORE_CLK_DFLLCTRL_STABLE_FCALIB_NOT_FIXED
    +
    421 #define CONF_CORE_CLK_DFLL_MODE 0x01
    +
    422 #define CONF_CORE_CLK_DFLL_DIFF_VAL 0
    +
    423 #define CONF_CORE_CLK_DFLL_COARSE_VAL (0x1f / 4)
    +
    424 #define CONF_CORE_CLK_DFLL_FINE_VAL 128
    +
    425 #define CONF_CORE_CLK_DFLL_CSTEP_VAL 1
    +
    426 #define CONF_CORE_CLK_DFLL_FSTEP_VAL 1
    +
    427 #define CONF_CORE_CLK_DFLL_MUL_VAL (48000000)
    +
    428 
    +
    444 #define CONF_CORE_CLK_DFLL_GCLK_SRC 3
    +
    445 #define CONF_CORE_CLK_DFLL_OVERWRITE_CAL 0
    +
    446 
    +
    453 #define CONF_CORE_CLK_DPLL0_ENABLE (1)
    +
    454 #define CONF_CORE_CLK_DPLL0_ONDEMAND (0)
    +
    455 #define CONF_CORE_CLK_DPLL0_RUNSTDBY (0)
    +
    456 #define CONF_CORE_CLK_DPLL0_LDRFRAC_VAL 0
    +
    457 #define CONF_CORE_CLK_DPLL0_LDR_VAL (119)
    +
    458 #define CONF_CORE_CLK_DPLL0_DIV_VAL (5)
    +
    459 #define CONF_CORE_CLK_DPLL0_DCOEN 0
    +
    460 #define CONF_CORE_CLK_DPLL0_DCOFILTER CONF_CORE_CLK_DPLLCTRL_DCOFILTER_3210KHZ
    +
    461 #define CONF_CORE_CLK_DPLL0_LBYPASS 1
    +
    462 #define CONF_CORE_CLK_DPLL0_LTIME 0
    +
    463 #define CONF_CORE_CLK_DPLL0_WUF 0
    +
    464 #define CONF_CORE_CLK_DPLL0_GCLK_SRC GCLK_GENCTRL_SRC_XOSC0
    +
    465 #define CONF_CORE_CLK_DPLL0_REFCLK CONF_CORE_CLK_DPLLCTRL_REFCLK_XOSC0
    +
    466 
    +
    490 #define CONF_CORE_CLK_DPLL0_FILTER 0x0
    +
    491 
    +
    498 #define CONF_CORE_CLK_DPLL1_ENABLE (0)
    +
    499 #define CONF_CORE_CLK_DPLL1_ONDEMAND (0)
    +
    500 #define CONF_CORE_CLK_DPLL1_RUNSTDBY (0)
    +
    501 #define CONF_CORE_CLK_DPLL1_LDRFRAC_VAL 0
    +
    502 #define CONF_CORE_CLK_DPLL1_LDR_VAL (0)
    +
    503 #define CONF_CORE_CLK_DPLL1_DIV_VAL (0)
    +
    504 #define CONF_CORE_CLK_DPLL1_DCOEN 0
    +
    505 #define CONF_CORE_CLK_DPLL1_DCOFILTER CONF_CORE_CLK_DPLLCTRL_DCOFILTER_3210KHZ
    +
    506 #define CONF_CORE_CLK_DPLL1_LBYPASS 0
    +
    507 #define CONF_CORE_CLK_DPLL1_LTIME 0
    +
    508 #define CONF_CORE_CLK_DPLL1_WUF 0
    +
    509 #define CONF_CORE_CLK_DPLL1_GCLK_SRC GCLK_GENCTRL_SRC_XOSC0
    +
    510 #define CONF_CORE_CLK_DPLL1_REFCLK CONF_CORE_CLK_DPLLCTRL_REFCLK_XOSC0
    +
    511 
    +
    535 #define CONF_CORE_CLK_DPLL1_FILTER 0x0
    +
    536 
    +
    539 // GCLK Generators Config
    +
    540 #define CONF_CORE_GCLK_0_ENABLE 1
    +
    541 #define CONF_CORE_GCLK_0_RUN_IN_STANDBY 1
    +
    542 #define CONF_CORE_GCLK_0_CLOCK_SOURCE GCLK_GENCTRL_SRC_XOSC0
    +
    543 #define CONF_CORE_GCLK_0_DIV_VAL 1
    +
    544 #define CONF_CORE_GCLK_0_DIVSEL 0
    +
    545 #define CONF_CORE_GCLK_0_OUTPUT_ENABLE 1
    +
    546 #define CONF_CORE_GCLK_0_OUTPUT_OFF_VALUE 1
    +
    547 #define CONF_CORE_GCLK_0_IDC 1
    +
    548 
    +
    549 #define CONF_CORE_GCLK_1_ENABLE 0
    +
    550 #define CONF_CORE_GCLK_1_RUN_IN_STANDBY 0
    +
    551 #define CONF_CORE_GCLK_1_CLOCK_SOURCE GCLK_GENCTRL_SRC_XOSC0
    +
    552 #define CONF_CORE_GCLK_1_DIV_VAL 1
    +
    553 #define CONF_CORE_GCLK_1_DIVSEL 0
    +
    554 #define CONF_CORE_GCLK_1_OUTPUT_ENABLE 0
    +
    555 #define CONF_CORE_GCLK_1_OUTPUT_OFF_VALUE 0
    +
    556 #define CONF_CORE_GCLK_1_IDC 0
    +
    557 
    +
    558 #define CONF_CORE_GCLK_2_ENABLE 0
    +
    559 #define CONF_CORE_GCLK_2_RUN_IN_STANDBY 0
    +
    560 #define CONF_CORE_GCLK_2_CLOCK_SOURCE GCLK_GENCTRL_SRC_XOSC0
    +
    561 #define CONF_CORE_GCLK_2_DIV_VAL 1
    +
    562 #define CONF_CORE_GCLK_2_DIVSEL 0
    +
    563 #define CONF_CORE_GCLK_2_OUTPUT_ENABLE 0
    +
    564 #define CONF_CORE_GCLK_2_OUTPUT_OFF_VALUE 0
    +
    565 #define CONF_CORE_GCLK_2_IDC 0
    +
    566 
    +
    567 #define CONF_CORE_GCLK_3_ENABLE 1
    +
    568 #define CONF_CORE_GCLK_3_RUN_IN_STANDBY 0
    +
    569 #define CONF_CORE_GCLK_3_CLOCK_SOURCE GCLK_GENCTRL_SRC_XOSC32K
    +
    570 #define CONF_CORE_GCLK_3_DIV_VAL 1
    +
    571 #define CONF_CORE_GCLK_3_DIVSEL 0
    +
    572 #define CONF_CORE_GCLK_3_OUTPUT_ENABLE 0
    +
    573 #define CONF_CORE_GCLK_3_OUTPUT_OFF_VALUE 0
    +
    574 #define CONF_CORE_GCLK_3_IDC 0
    +
    575 
    +
    576 #define CONF_CORE_GCLK_4_ENABLE 0
    +
    577 #define CONF_CORE_GCLK_4_RUN_IN_STANDBY 0
    +
    578 #define CONF_CORE_GCLK_4_CLOCK_SOURCE GCLK_GENCTRL_SRC_XOSC0
    +
    579 #define CONF_CORE_GCLK_4_DIV_VAL 1
    +
    580 #define CONF_CORE_GCLK_4_DIVSEL 1
    +
    581 #define CONF_CORE_GCLK_4_OUTPUT_ENABLE 0
    +
    582 #define CONF_CORE_GCLK_4_OUTPUT_OFF_VALUE 0
    +
    583 #define CONF_CORE_GCLK_4_IDC 0
    +
    584 
    +
    585 #define CONF_CORE_GCLK_5_ENABLE 0
    +
    586 #define CONF_CORE_GCLK_5_RUN_IN_STANDBY 0
    +
    587 #define CONF_CORE_GCLK_5_CLOCK_SOURCE GCLK_GENCTRL_SRC_XOSC0
    +
    588 #define CONF_CORE_GCLK_5_DIV_VAL 1
    +
    589 #define CONF_CORE_GCLK_5_DIVSEL 0
    +
    590 #define CONF_CORE_GCLK_5_OUTPUT_ENABLE 0
    +
    591 #define CONF_CORE_GCLK_5_OUTPUT_OFF_VALUE 0
    +
    592 #define CONF_CORE_GCLK_5_IDC 0
    +
    593 
    +
    594 #define CONF_CORE_GCLK_6_ENABLE 0
    +
    595 #define CONF_CORE_GCLK_6_RUN_IN_STANDBY 0
    +
    596 #define CONF_CORE_GCLK_6_CLOCK_SOURCE GCLK_GENCTRL_SRC_XOSC0
    +
    597 #define CONF_CORE_GCLK_6_DIV_VAL 1
    +
    598 #define CONF_CORE_GCLK_6_DIVSEL 0
    +
    599 #define CONF_CORE_GCLK_6_OUTPUT_ENABLE 0
    +
    600 #define CONF_CORE_GCLK_6_OUTPUT_OFF_VALUE 0
    +
    601 #define CONF_CORE_GCLK_6_IDC 0
    +
    602 
    +
    603 #define CONF_CORE_GCLK_7_ENABLE 0
    +
    604 #define CONF_CORE_GCLK_7_RUN_IN_STANDBY 0
    +
    605 #define CONF_CORE_GCLK_7_CLOCK_SOURCE GCLK_GENCTRL_SRC_XOSC0
    +
    606 #define CONF_CORE_GCLK_7_DIV_VAL 1
    +
    607 #define CONF_CORE_GCLK_7_DIVSEL 0
    +
    608 #define CONF_CORE_GCLK_7_OUTPUT_ENABLE 0
    +
    609 #define CONF_CORE_GCLK_7_OUTPUT_OFF_VALUE 0
    +
    610 #define CONF_CORE_GCLK_7_IDC 0
    +
    611 
    +
    612 #define CONF_CORE_GCLK_8_ENABLE 0
    +
    613 #define CONF_CORE_GCLK_8_RUN_IN_STANDBY 0
    +
    614 #define CONF_CORE_GCLK_8_CLOCK_SOURCE GCLK_GENCTRL_SRC_XOSC0
    +
    615 #define CONF_CORE_GCLK_8_DIV_VAL 1
    +
    616 #define CONF_CORE_GCLK_8_DIVSEL 0
    +
    617 #define CONF_CORE_GCLK_8_OUTPUT_ENABLE 0
    +
    618 #define CONF_CORE_GCLK_8_OUTPUT_OFF_VALUE 0
    +
    619 #define CONF_CORE_GCLK_8_IDC 0
    +
    620 
    +
    621 #define CONF_CORE_GCLK_9_ENABLE 0
    +
    622 #define CONF_CORE_GCLK_9_RUN_IN_STANDBY 0
    +
    623 #define CONF_CORE_GCLK_9_CLOCK_SOURCE GCLK_GENCTRL_SRC_XOSC0
    +
    624 #define CONF_CORE_GCLK_9_DIV_VAL 1
    +
    625 #define CONF_CORE_GCLK_9_DIVSEL 0
    +
    626 #define CONF_CORE_GCLK_9_OUTPUT_ENABLE 0
    +
    627 #define CONF_CORE_GCLK_9_OUTPUT_OFF_VALUE 0
    +
    628 #define CONF_CORE_GCLK_9_IDC 0
    +
    629 
    +
    630 #define CONF_CORE_GCLK_10_ENABLE 0
    +
    631 #define CONF_CORE_GCLK_10_RUN_IN_STANDBY 0
    +
    632 #define CONF_CORE_GCLK_10_CLOCK_SOURCE GCLK_GENCTRL_SRC_XOSC0
    +
    633 #define CONF_CORE_GCLK_10_DIV_VAL 1
    +
    634 #define CONF_CORE_GCLK_10_DIVSEL 0
    +
    635 #define CONF_CORE_GCLK_10_OUTPUT_ENABLE 0
    +
    636 #define CONF_CORE_GCLK_10_OUTPUT_OFF_VALUE 0
    +
    637 #define CONF_CORE_GCLK_10_IDC 0
    +
    638 
    +
    639 #define CONF_CORE_GCLK_11_ENABLE 0
    +
    640 #define CONF_CORE_GCLK_11_RUN_IN_STANDBY 0
    +
    641 #define CONF_CORE_GCLK_11_CLOCK_SOURCE GCLK_GENCTRL_SRC_XOSC0
    +
    642 #define CONF_CORE_GCLK_11_DIV_VAL 1
    +
    643 #define CONF_CORE_GCLK_11_DIVSEL 0
    +
    644 #define CONF_CORE_GCLK_11_OUTPUT_ENABLE 0
    +
    645 #define CONF_CORE_GCLK_11_OUTPUT_OFF_VALUE 0
    +
    646 #define CONF_CORE_GCLK_11_IDC 0
    +
    647 
    +
    648 
    +
    649 
    +
    650 #endif
    diff --git a/test/same54p20a_test/doc/html/globals_c.html b/test/same54p20a_test/doc/html/globals_c.html index c8e1fbd1..f47ec481 100644 --- a/test/same54p20a_test/doc/html/globals_c.html +++ b/test/same54p20a_test/doc/html/globals_c.html @@ -2693,10 +2693,10 @@ $(function() { : can.h
  • CCL -: same54n19a.h -, same54p19a.h -, same54n20a.h +: same54n20a.h , same54p20a.h +, same54p19a.h +, same54n19a.h
  • CCL_CTRL_ENABLE_Pos : ccl.h @@ -2717,16 +2717,16 @@ $(function() { : ccl.h
  • CCL_INST_NUM -: same54n19a.h -, same54p20a.h +: same54p20a.h , same54n20a.h , same54p19a.h +, same54n19a.h
  • CCL_INSTS -: same54p20a.h -, same54n19a.h +: same54n20a.h +, same54p20a.h , same54p19a.h -, same54n20a.h +, same54n19a.h
  • CCL_LUTCTRL_EDGESEL_Pos : ccl.h @@ -2894,16 +2894,16 @@ $(function() { : ccl.h
  • CMCC -: same54n20a.h -, same54p19a.h -, same54p20a.h +: same54p19a.h , same54n19a.h +, same54p20a.h +, same54n20a.h
  • CMCC_AHB -: same54n20a.h -, same54n19a.h -, same54p20a.h +: same54p20a.h , same54p19a.h +, same54n19a.h +, same54n20a.h
  • CMCC_CFG_CSIZESW_CONF_CSIZE_16KB_Val : cmcc.h @@ -2957,10 +2957,10 @@ $(function() { : cmcc.h
  • CMCC_DATARAM_ADDR -: same54p19a.h -, same54p20a.h +: same54n19a.h , same54n20a.h -, same54n19a.h +, same54p20a.h +, same54p19a.h
  • CMCC_DATARAM_SIZE : same54n19a.h @@ -2969,15 +2969,15 @@ $(function() { , same54n20a.h
  • CMCC_INST_NUM -: same54p20a.h +: same54n19a.h , same54p19a.h +, same54p20a.h , same54n20a.h -, same54n19a.h
  • CMCC_INSTS -: same54p19a.h +: same54n19a.h +, same54p19a.h , same54p20a.h -, same54n19a.h , same54n20a.h
  • CMCC_LCKWAY_LCKWAY_Pos @@ -3102,14 +3102,14 @@ $(function() {
  • CMCC_TAGRAM_ADDR : same54p19a.h +, same54p20a.h , same54n19a.h , same54n20a.h -, same54p20a.h
  • CMCC_TAGRAM_SIZE : same54p19a.h -, same54p20a.h , same54n19a.h +, same54p20a.h , same54n20a.h
  • CMCC_TYPE_CLSIZE_CLSIZE_128B_Val @@ -3189,15 +3189,15 @@ $(function() {
  • CMCC_VALIDRAM_ADDR : same54p20a.h -, same54n19a.h -, same54p19a.h , same54n20a.h +, same54p19a.h +, same54n19a.h
  • CMCC_VALIDRAM_SIZE -: same54n20a.h -, same54p20a.h -, same54p19a.h +: same54p19a.h +, same54n20a.h , same54n19a.h +, same54p20a.h
  • CONF_CORE_CLK_DFLL_ENABLE : conf_core.h @@ -3220,6 +3220,102 @@ $(function() {
  • CONF_CORE_CLK_DPLL1_FILTER : conf_core.h
    • +
  • CONF_CORE_CLK_XOSC0_CFDEN +: conf_core.h +
    • +
  • CONF_CORE_CLK_XOSC0_ENABLE +: conf_core.h +
    • +
  • CONF_CORE_CLK_XOSC0_ENALC +: conf_core.h +
    • +
  • CONF_CORE_CLK_XOSC0_FREQUENCY +: conf_core.h +
    • +
  • CONF_CORE_CLK_XOSC0_LOWBUFGAIN +: conf_core.h +
    • +
  • CONF_CORE_CLK_XOSC0_ONDEMAND +: conf_core.h +
    • +
  • CONF_CORE_CLK_XOSC0_RUNSTDBY +: conf_core.h +
    • +
  • CONF_CORE_CLK_XOSC0_STARTUP_TIME +: conf_core.h +
    • +
  • CONF_CORE_CLK_XOSC0_SWBEN +: conf_core.h +
    • +
  • CONF_CORE_CLK_XOSC0_XTALEN +: conf_core.h +
    • +
  • CONF_CORE_CLK_XOSC1_CFDEN +: conf_core.h +
    • +
  • CONF_CORE_CLK_XOSC1_ENABLE +: conf_core.h +
    • +
  • CONF_CORE_CLK_XOSC1_ENALC +: conf_core.h +
    • +
  • CONF_CORE_CLK_XOSC1_FREQUENCY +: conf_core.h +
    • +
  • CONF_CORE_CLK_XOSC1_LOWBUFGAIN +: conf_core.h +
    • +
  • CONF_CORE_CLK_XOSC1_ONDEMAND +: conf_core.h +
    • +
  • CONF_CORE_CLK_XOSC1_RUNSTDBY +: conf_core.h +
    • +
  • CONF_CORE_CLK_XOSC1_STARTUP_TIME +: conf_core.h +
    • +
  • CONF_CORE_CLK_XOSC1_SWBEN +: conf_core.h +
    • +
  • CONF_CORE_CLK_XOSC1_XTALEN +: conf_core.h +
    • +
  • CONF_CORE_CLK_XOSC32K_CFDEN +: conf_core.h +
    • +
  • CONF_CORE_CLK_XOSC32K_CFDPRESC +: conf_core.h +
    • +
  • CONF_CORE_CLK_XOSC32K_CGM +: conf_core.h +
    • +
  • CONF_CORE_CLK_XOSC32K_EN1K +: conf_core.h +
    • +
  • CONF_CORE_CLK_XOSC32K_EN32K +: conf_core.h +
    • +
  • CONF_CORE_CLK_XOSC32K_ENABLE +: conf_core.h +
    • +
  • CONF_CORE_CLK_XOSC32K_ONDEMAND +: conf_core.h +
    • +
  • CONF_CORE_CLK_XOSC32K_RUNSTDBY +: conf_core.h +
    • +
  • CONF_CORE_CLK_XOSC32K_STARTUP_TIME +: conf_core.h +
    • +
  • CONF_CORE_CLK_XOSC32K_SWBACK +: conf_core.h +
    • +
  • CONF_CORE_CLK_XOSC32K_WRTLOCK +: conf_core.h +
    • +
  • CONF_CORE_CLK_XOSC32K_XTALEN +: conf_core.h +
  • CONF_CORE_CMCC_ENABLE : conf_core.h
    • @@ -3232,6 +3328,15 @@ $(function() {
  • CONF_CORE_MCLK_NVM_WAIT_STATE : conf_core.h
    • +
  • CONF_CORE_PORT_EVCTRL_0_ENABLE +: conf_core.h +
    • +
  • CONF_CORE_PORT_EVCTRL_1_ENABLE +: conf_core.h +
    • +
  • CONF_CORE_PORT_EVCTRL_2_ENABLE +: conf_core.h +
    • diff --git a/test/same54p20a_test/doc/html/globals_defs_c.html b/test/same54p20a_test/doc/html/globals_defs_c.html index 814acc36..403039e8 100644 --- a/test/same54p20a_test/doc/html/globals_defs_c.html +++ b/test/same54p20a_test/doc/html/globals_defs_c.html @@ -2681,10 +2681,10 @@ $(function() { : can.h
  • CCL -: same54n19a.h +: same54n20a.h +, same54n19a.h , same54p20a.h , same54p19a.h -, same54n20a.h
  • CCL_CTRL_ENABLE_Pos : ccl.h @@ -2705,16 +2705,16 @@ $(function() { : ccl.h
  • CCL_INST_NUM -: same54n19a.h -, same54p20a.h -, same54n20a.h +: same54n20a.h , same54p19a.h +, same54p20a.h +, same54n19a.h
  • CCL_INSTS -: same54p19a.h -, same54n19a.h -, same54p20a.h +: same54p20a.h , same54n20a.h +, same54p19a.h +, same54n19a.h
  • CCL_LUTCTRL_EDGESEL_Pos : ccl.h @@ -2945,28 +2945,28 @@ $(function() { : cmcc.h
  • CMCC_DATARAM_ADDR -: same54p19a.h -, same54p20a.h +: same54p20a.h , same54n19a.h +, same54p19a.h , same54n20a.h
  • CMCC_DATARAM_SIZE -: same54p19a.h -, same54n20a.h +: same54n19a.h +, same54p19a.h , same54p20a.h -, same54n19a.h +, same54n20a.h
  • CMCC_INST_NUM -: same54p20a.h +: same54n20a.h +, same54p20a.h , same54p19a.h -, same54n20a.h , same54n19a.h
  • CMCC_INSTS -: same54p20a.h -, same54p19a.h -, same54n19a.h +: same54p19a.h +, same54p20a.h , same54n20a.h +, same54n19a.h
  • CMCC_LCKWAY_LCKWAY_Pos : cmcc.h @@ -3089,10 +3089,10 @@ $(function() { : cmcc.h
  • CMCC_TAGRAM_ADDR -: same54n19a.h -, same54n20a.h +: same54p19a.h , same54p20a.h -, same54p19a.h +, same54n20a.h +, same54n19a.h
  • CMCC_TAGRAM_SIZE : same54n20a.h @@ -3177,15 +3177,15 @@ $(function() {
  • CMCC_VALIDRAM_ADDR : same54p20a.h -, same54n19a.h , same54p19a.h +, same54n19a.h , same54n20a.h
  • CMCC_VALIDRAM_SIZE -: same54n19a.h +: same54n20a.h , same54p19a.h +, same54n19a.h , same54p20a.h -, same54n20a.h
  • CONF_CORE_CLK_DFLL_ENABLE : conf_core.h @@ -3208,6 +3208,102 @@ $(function() {
  • CONF_CORE_CLK_DPLL1_FILTER : conf_core.h
    • +
  • CONF_CORE_CLK_XOSC0_CFDEN +: conf_core.h +
    • +
  • CONF_CORE_CLK_XOSC0_ENABLE +: conf_core.h +
    • +
  • CONF_CORE_CLK_XOSC0_ENALC +: conf_core.h +
    • +
  • CONF_CORE_CLK_XOSC0_FREQUENCY +: conf_core.h +
    • +
  • CONF_CORE_CLK_XOSC0_LOWBUFGAIN +: conf_core.h +
    • +
  • CONF_CORE_CLK_XOSC0_ONDEMAND +: conf_core.h +
    • +
  • CONF_CORE_CLK_XOSC0_RUNSTDBY +: conf_core.h +
    • +
  • CONF_CORE_CLK_XOSC0_STARTUP_TIME +: conf_core.h +
    • +
  • CONF_CORE_CLK_XOSC0_SWBEN +: conf_core.h +
    • +
  • CONF_CORE_CLK_XOSC0_XTALEN +: conf_core.h +
    • +
  • CONF_CORE_CLK_XOSC1_CFDEN +: conf_core.h +
    • +
  • CONF_CORE_CLK_XOSC1_ENABLE +: conf_core.h +
    • +
  • CONF_CORE_CLK_XOSC1_ENALC +: conf_core.h +
    • +
  • CONF_CORE_CLK_XOSC1_FREQUENCY +: conf_core.h +
    • +
  • CONF_CORE_CLK_XOSC1_LOWBUFGAIN +: conf_core.h +
    • +
  • CONF_CORE_CLK_XOSC1_ONDEMAND +: conf_core.h +
    • +
  • CONF_CORE_CLK_XOSC1_RUNSTDBY +: conf_core.h +
    • +
  • CONF_CORE_CLK_XOSC1_STARTUP_TIME +: conf_core.h +
    • +
  • CONF_CORE_CLK_XOSC1_SWBEN +: conf_core.h +
    • +
  • CONF_CORE_CLK_XOSC1_XTALEN +: conf_core.h +
    • +
  • CONF_CORE_CLK_XOSC32K_CFDEN +: conf_core.h +
    • +
  • CONF_CORE_CLK_XOSC32K_CFDPRESC +: conf_core.h +
    • +
  • CONF_CORE_CLK_XOSC32K_CGM +: conf_core.h +
    • +
  • CONF_CORE_CLK_XOSC32K_EN1K +: conf_core.h +
    • +
  • CONF_CORE_CLK_XOSC32K_EN32K +: conf_core.h +
    • +
  • CONF_CORE_CLK_XOSC32K_ENABLE +: conf_core.h +
    • +
  • CONF_CORE_CLK_XOSC32K_ONDEMAND +: conf_core.h +
    • +
  • CONF_CORE_CLK_XOSC32K_RUNSTDBY +: conf_core.h +
    • +
  • CONF_CORE_CLK_XOSC32K_STARTUP_TIME +: conf_core.h +
    • +
  • CONF_CORE_CLK_XOSC32K_SWBACK +: conf_core.h +
    • +
  • CONF_CORE_CLK_XOSC32K_WRTLOCK +: conf_core.h +
    • +
  • CONF_CORE_CLK_XOSC32K_XTALEN +: conf_core.h +
  • CONF_CORE_CMCC_ENABLE : conf_core.h
    • @@ -3220,6 +3316,15 @@ $(function() {
  • CONF_CORE_MCLK_NVM_WAIT_STATE : conf_core.h
    • +
  • CONF_CORE_PORT_EVCTRL_0_ENABLE +: conf_core.h +
    • +
  • CONF_CORE_PORT_EVCTRL_1_ENABLE +: conf_core.h +
    • +
  • CONF_CORE_PORT_EVCTRL_2_ENABLE +: conf_core.h +
    • diff --git a/test/same54p20a_test/doc/html/memory_8c_source.html b/test/same54p20a_test/doc/html/memory_8c_source.html index e664ac86..456971e2 100644 --- a/test/same54p20a_test/doc/html/memory_8c_source.html +++ b/test/same54p20a_test/doc/html/memory_8c_source.html @@ -96,7 +96,7 @@ $(function() {
    25 }
    26 
    -
    CONF_CORE_MCLK_NVM_WAIT_STATE
    #define CONF_CORE_MCLK_NVM_WAIT_STATE
    Definition: conf_core.h:23
    +
    CONF_CORE_MCLK_NVM_WAIT_STATE
    #define CONF_CORE_MCLK_NVM_WAIT_STATE
    Define the number of wait states for the master clock. Can be [0-15]. See Datasheet Reference
    Definition: conf_core.h:24
    NVMCTRL
    #define NVMCTRL
    (NVMCTRL) APB Base Address
    Definition: same54n19a.h:918
    MCLK
    #define MCLK
    (MCLK) APB Base Address
    Definition: same54n19a.h:914
    conf_core.h
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9b1c06b1..8e53f4dd 100644 --- a/test/same54p20a_test/doc/html/search/classes_9.js +++ b/test/same54p20a_test/doc/html/search/classes_9.js @@ -1,14 +1,14 @@ var searchData= [ - ['mclk_15920',['Mclk',['../structMclk.html',1,'']]], - ['mclk_5fahbmask_5ftype_15921',['MCLK_AHBMASK_Type',['../unionMCLK__AHBMASK__Type.html',1,'']]], - ['mclk_5fapbamask_5ftype_15922',['MCLK_APBAMASK_Type',['../unionMCLK__APBAMASK__Type.html',1,'']]], - ['mclk_5fapbbmask_5ftype_15923',['MCLK_APBBMASK_Type',['../unionMCLK__APBBMASK__Type.html',1,'']]], - ['mclk_5fapbcmask_5ftype_15924',['MCLK_APBCMASK_Type',['../unionMCLK__APBCMASK__Type.html',1,'']]], - ['mclk_5fapbdmask_5ftype_15925',['MCLK_APBDMASK_Type',['../unionMCLK__APBDMASK__Type.html',1,'']]], - ['mclk_5fcpudiv_5ftype_15926',['MCLK_CPUDIV_Type',['../unionMCLK__CPUDIV__Type.html',1,'']]], - ['mclk_5fhsdiv_5ftype_15927',['MCLK_HSDIV_Type',['../unionMCLK__HSDIV__Type.html',1,'']]], - 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a/test/same54p20a_test/doc/html/search/classes_b.js b/test/same54p20a_test/doc/html/search/classes_b.js index d11bb855..3bcae08b 100644 --- a/test/same54p20a_test/doc/html/search/classes_b.js +++ b/test/same54p20a_test/doc/html/search/classes_b.js @@ -1,31 +1,31 @@ var searchData= [ - ['osc32kctrl_15946',['Osc32kctrl',['../structOsc32kctrl.html',1,'']]], - ['osc32kctrl_5fcfdctrl_5ftype_15947',['OSC32KCTRL_CFDCTRL_Type',['../unionOSC32KCTRL__CFDCTRL__Type.html',1,'']]], - ['osc32kctrl_5fevctrl_5ftype_15948',['OSC32KCTRL_EVCTRL_Type',['../unionOSC32KCTRL__EVCTRL__Type.html',1,'']]], - ['osc32kctrl_5fintenclr_5ftype_15949',['OSC32KCTRL_INTENCLR_Type',['../unionOSC32KCTRL__INTENCLR__Type.html',1,'']]], - ['osc32kctrl_5fintenset_5ftype_15950',['OSC32KCTRL_INTENSET_Type',['../unionOSC32KCTRL__INTENSET__Type.html',1,'']]], - ['osc32kctrl_5fintflag_5ftype_15951',['OSC32KCTRL_INTFLAG_Type',['../unionOSC32KCTRL__INTFLAG__Type.html',1,'']]], - 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