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<li class="navelem"><a class="el" href="dir_e498f07834f57e09d3c418a37b65ec3b.html">ESF</a></li><li class="navelem"><a class="el" href="dir_2c010a15ee55606c39d249a8f09d70a6.html">modules</a></li><li class="navelem"><a class="el" href="dir_1e3b112bfad1074f4c8038c4c4396c2b.html">core</a></li> </ul>
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<div class="title">clocks.c</div> </div>
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<div class="fragment"><div class="line"><a name="l00001"></a><span class="lineno"> 1</span> <span class="preprocessor">#include "clocks.h"</span></div>
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<div class="line"><a name="l00002"></a><span class="lineno"> 2</span> <span class="preprocessor">#include "<a class="code" href="conf__core_8h.html">conf_core.h</a>"</span></div>
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<div class="line"><a name="l00003"></a><span class="lineno"> 3</span>  </div>
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<div class="line"><a name="l00004"></a><span class="lineno"> 4</span> <span class="preprocessor">#if CONF_CORE_CLK_XOSC0_FREQUENCY > 24000000</span></div>
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<div class="line"><a name="l00005"></a><span class="lineno"> 5</span> <span class="preprocessor"> #define CONF_CORE_CLK_XOSC0_IPTAT (3)</span></div>
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<div class="line"><a name="l00006"></a><span class="lineno"> 6</span> <span class="preprocessor"> #define CONF_CORE_CLK_XOSC0_IMULT (6)</span></div>
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<div class="line"><a name="l00007"></a><span class="lineno"> 7</span> <span class="preprocessor"> #define CONF_CORE_CLK_XOSC0_CFDPRESC (0x0)</span></div>
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<div class="line"><a name="l00008"></a><span class="lineno"> 8</span> <span class="preprocessor">#elif CONF_CORE_CLK_XOSC0_FREQUENCY > 16000000</span></div>
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<div class="line"><a name="l00009"></a><span class="lineno"> 9</span> <span class="preprocessor"> #define CONF_CORE_CLK_XOSC0_IPTAT (3)</span></div>
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<div class="line"><a name="l00010"></a><span class="lineno"> 10</span> <span class="preprocessor"> #define CONF_CORE_CLK_XOSC0_IMULT (5)</span></div>
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<div class="line"><a name="l00011"></a><span class="lineno"> 11</span> <span class="preprocessor"> #define CONF_CORE_CLK_XOSC0_CFDPRESC (0x1)</span></div>
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<div class="line"><a name="l00012"></a><span class="lineno"> 12</span> <span class="preprocessor">#elif CONF_CORE_CLK_XOSC0_FREQUENCY > 8000000</span></div>
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<div class="line"><a name="l00013"></a><span class="lineno"> 13</span> <span class="preprocessor"> #define CONF_CORE_CLK_XOSC0_IPTAT (3)</span></div>
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<div class="line"><a name="l00014"></a><span class="lineno"> 14</span> <span class="preprocessor"> #define CONF_CORE_CLK_XOSC0_IMULT (4)</span></div>
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<div class="line"><a name="l00015"></a><span class="lineno"> 15</span> <span class="preprocessor"> #define CONF_CORE_CLK_XOSC0_CFDPRESC (0x2)</span></div>
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<div class="line"><a name="l00016"></a><span class="lineno"> 16</span> <span class="preprocessor">#else</span></div>
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<div class="line"><a name="l00017"></a><span class="lineno"> 17</span> <span class="preprocessor"> #define CONF_CORE_CLK_XOSC0_IPTAT (2)</span></div>
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<div class="line"><a name="l00018"></a><span class="lineno"> 18</span> <span class="preprocessor"> #define CONF_CORE_CLK_XOSC0_IMULT (3)</span></div>
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<div class="line"><a name="l00019"></a><span class="lineno"> 19</span> <span class="preprocessor"> #define CONF_CORE_CLK_XOSC0_CFDPRESC (0x3)</span></div>
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<div class="line"><a name="l00020"></a><span class="lineno"> 20</span> <span class="preprocessor">#endif</span></div>
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<div class="line"><a name="l00021"></a><span class="lineno"> 21</span>  </div>
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<div class="line"><a name="l00022"></a><span class="lineno"> 22</span> <span class="preprocessor">#if CONF_CORE_CLK_XOSC1_FREQUENCY > 24000000</span></div>
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<div class="line"><a name="l00023"></a><span class="lineno"> 23</span> <span class="preprocessor"> #define CONF_CORE_CLK_XOSC1_IPTAT (3)</span></div>
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<div class="line"><a name="l00024"></a><span class="lineno"> 24</span> <span class="preprocessor"> #define CONF_CORE_CLK_XOSC1_IMULT (6)</span></div>
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<div class="line"><a name="l00025"></a><span class="lineno"> 25</span> <span class="preprocessor"> #define CONF_CORE_CLK_XOSC1_CFDPRESC (0x0)</span></div>
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<div class="line"><a name="l00026"></a><span class="lineno"> 26</span> <span class="preprocessor">#elif CONF_CORE_CLK_XOSC1_FREQUENCY > 16000000</span></div>
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<div class="line"><a name="l00027"></a><span class="lineno"> 27</span> <span class="preprocessor"> #define CONF_CORE_CLK_XOSC1_IPTAT (3)</span></div>
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<div class="line"><a name="l00028"></a><span class="lineno"> 28</span> <span class="preprocessor"> #define CONF_CORE_CLK_XOSC1_IMULT (5)</span></div>
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<div class="line"><a name="l00029"></a><span class="lineno"> 29</span> <span class="preprocessor"> #define CONF_CORE_CLK_XOSC1_CFDPRESC (0x1)</span></div>
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<div class="line"><a name="l00030"></a><span class="lineno"> 30</span> <span class="preprocessor">#elif CONF_CORE_CLK_XOSC1_FREQUENCY > 8000000</span></div>
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<div class="line"><a name="l00031"></a><span class="lineno"> 31</span> <span class="preprocessor"> #define CONF_CORE_CLK_XOSC1_IPTAT (3)</span></div>
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<div class="line"><a name="l00032"></a><span class="lineno"> 32</span> <span class="preprocessor"> #define CONF_CORE_CLK_XOSC1_IMULT (4)</span></div>
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<div class="line"><a name="l00033"></a><span class="lineno"> 33</span> <span class="preprocessor"> #define CONF_CORE_CLK_XOSC1_CFDPRESC (0x2)</span></div>
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<div class="line"><a name="l00034"></a><span class="lineno"> 34</span> <span class="preprocessor">#else</span></div>
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<div class="line"><a name="l00035"></a><span class="lineno"> 35</span> <span class="preprocessor"> #define CONF_CORE_CLK_XOSC1_IPTAT (2)</span></div>
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<div class="line"><a name="l00036"></a><span class="lineno"> 36</span> <span class="preprocessor"> #define CONF_CORE_CLK_XOSC1_IMULT (3)</span></div>
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<div class="line"><a name="l00037"></a><span class="lineno"> 37</span> <span class="preprocessor"> #define CONF_CORE_CLK_XOSC1_CFDPRESC (0x3)</span></div>
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<div class="line"><a name="l00038"></a><span class="lineno"> 38</span> <span class="preprocessor">#endif</span></div>
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<div class="line"><a name="l00039"></a><span class="lineno"> 39</span>  </div>
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<div class="line"><a name="l00040"></a><span class="lineno"> 40</span> <span class="keywordtype">void</span> clock_osc32k_init(<span class="keywordtype">void</span>)</div>
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<div class="line"><a name="l00041"></a><span class="lineno"> 41</span> {</div>
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<div class="line"><a name="l00042"></a><span class="lineno"> 42</span> <span class="preprocessor">#if CONF_CORE_CLK_XOSC32K_ENABLE == 1</span></div>
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<div class="line"><a name="l00043"></a><span class="lineno"> 43</span>  <a class="code" href="same54n19a_8h.html#af1a4b8f1d1a2265b93f22621f7903f88">OSC32KCTRL</a>->XOSC32K.bit.CGM = <a class="code" href="conf__core_8h.html#a031a77340c697036538d218724837de1">CONF_CORE_CLK_XOSC32K_CGM</a>;</div>
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<div class="line"><a name="l00044"></a><span class="lineno"> 44</span>  <a class="code" href="same54n19a_8h.html#af1a4b8f1d1a2265b93f22621f7903f88">OSC32KCTRL</a>->XOSC32K.bit.WRTLOCK = <a class="code" href="conf__core_8h.html#a42b0270d2f3c0f51c4b3d2b8ac397fda">CONF_CORE_CLK_XOSC32K_WRTLOCK</a>;</div>
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<div class="line"><a name="l00045"></a><span class="lineno"> 45</span>  <a class="code" href="same54n19a_8h.html#af1a4b8f1d1a2265b93f22621f7903f88">OSC32KCTRL</a>->XOSC32K.bit.STARTUP = <a class="code" href="conf__core_8h.html#a314b78ee48f1ecf6c40f4bad7ef63d9d">CONF_CORE_CLK_XOSC32K_STARTUP_TIME</a>;</div>
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<div class="line"><a name="l00046"></a><span class="lineno"> 46</span>  <a class="code" href="same54n19a_8h.html#af1a4b8f1d1a2265b93f22621f7903f88">OSC32KCTRL</a>->XOSC32K.bit.RUNSTDBY = <a class="code" href="conf__core_8h.html#adc7a2f161e9e8e54388b1f290066247e">CONF_CORE_CLK_XOSC32K_RUNSTDBY</a>;</div>
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<div class="line"><a name="l00047"></a><span class="lineno"> 47</span>  <a class="code" href="same54n19a_8h.html#af1a4b8f1d1a2265b93f22621f7903f88">OSC32KCTRL</a>->XOSC32K.bit.ONDEMAND = <a class="code" href="conf__core_8h.html#a8d70a30b50febec035af6b982daac395">CONF_CORE_CLK_XOSC32K_ONDEMAND</a>;</div>
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<div class="line"><a name="l00048"></a><span class="lineno"> 48</span>  <a class="code" href="same54n19a_8h.html#af1a4b8f1d1a2265b93f22621f7903f88">OSC32KCTRL</a>->XOSC32K.bit.EN1K = <a class="code" href="conf__core_8h.html#a033f3571fb50a6ed02278d65ea84b45e">CONF_CORE_CLK_XOSC32K_EN1K</a>;</div>
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<div class="line"><a name="l00049"></a><span class="lineno"> 49</span>  <a class="code" href="same54n19a_8h.html#af1a4b8f1d1a2265b93f22621f7903f88">OSC32KCTRL</a>->XOSC32K.bit.EN32K = <a class="code" href="conf__core_8h.html#ae9fbb8d05dc5808f510eae4e8a629826">CONF_CORE_CLK_XOSC32K_EN32K</a>;</div>
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<div class="line"><a name="l00050"></a><span class="lineno"> 50</span>  <a class="code" href="same54n19a_8h.html#af1a4b8f1d1a2265b93f22621f7903f88">OSC32KCTRL</a>->XOSC32K.bit.XTALEN = <a class="code" href="conf__core_8h.html#a6a65a6f4bf7e21dc2003b61a7045e24a">CONF_CORE_CLK_XOSC32K_XTALEN</a>;</div>
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<div class="line"><a name="l00051"></a><span class="lineno"> 51</span>  <a class="code" href="same54n19a_8h.html#af1a4b8f1d1a2265b93f22621f7903f88">OSC32KCTRL</a>->CFDCTRL.bit.CFDPRESC = <a class="code" href="conf__core_8h.html#a79567f94a0f3ad2d628bcf5e1cff62d1">CONF_CORE_CLK_XOSC32K_CFDPRESC</a>;</div>
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<div class="line"><a name="l00052"></a><span class="lineno"> 52</span>  <a class="code" href="same54n19a_8h.html#af1a4b8f1d1a2265b93f22621f7903f88">OSC32KCTRL</a>->CFDCTRL.bit.SWBACK = <a class="code" href="conf__core_8h.html#ac6e671eee4ca4aeb9fcbb87d52b457b5">CONF_CORE_CLK_XOSC32K_SWBACK</a>;</div>
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<div class="line"><a name="l00053"></a><span class="lineno"> 53</span>  <a class="code" href="same54n19a_8h.html#af1a4b8f1d1a2265b93f22621f7903f88">OSC32KCTRL</a>->CFDCTRL.bit.CFDEN = <a class="code" href="conf__core_8h.html#a668d68edf9a7ac05be5b9cda247225ad">CONF_CORE_CLK_XOSC32K_CFDEN</a>;</div>
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<div class="line"><a name="l00054"></a><span class="lineno"> 54</span>  </div>
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<div class="line"><a name="l00055"></a><span class="lineno"> 55</span> <span class="preprocessor">#if CONF_CORE_CLK_XOSC32K_ENABLE == 1 && CONF_CORE_CLK_XOSC32K_ONDEMAND == 0</span></div>
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<div class="line"><a name="l00056"></a><span class="lineno"> 56</span>  <span class="keywordflow">while</span>(<a class="code" href="same54n19a_8h.html#af1a4b8f1d1a2265b93f22621f7903f88">OSC32KCTRL</a>->STATUS.bit.XOSC32KRDY == 0);</div>
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<div class="line"><a name="l00057"></a><span class="lineno"> 57</span> <span class="preprocessor">#endif</span></div>
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<div class="line"><a name="l00058"></a><span class="lineno"> 58</span>  </div>
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<div class="line"><a name="l00059"></a><span class="lineno"> 59</span> <span class="preprocessor">#endif</span></div>
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<div class="line"><a name="l00060"></a><span class="lineno"> 60</span> }</div>
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<div class="line"><a name="l00061"></a><span class="lineno"> 61</span> <span class="keywordtype">void</span> clock_osc_init(<span class="keywordtype">void</span>)</div>
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<div class="line"><a name="l00062"></a><span class="lineno"> 62</span> {</div>
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<div class="line"><a name="l00063"></a><span class="lineno"> 63</span> <span class="preprocessor">#if CONF_CORE_CLK_XOSC0_ENABLE == 1</span></div>
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<div class="line"><a name="l00064"></a><span class="lineno"> 64</span>  CRITICAL_SECTION_ENTER();</div>
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<div class="line"><a name="l00065"></a><span class="lineno"> 65</span>  <a class="code" href="same54n19a_8h.html#a49136ad5bf1adc9e9a0232349bcdce57">OSCCTRL</a>->XOSCCTRL[0].bit.XTALEN = <a class="code" href="conf__core_8h.html#ac2ca0e9037347eb69d53a0011f989910">CONF_CORE_CLK_XOSC0_XTALEN</a>;</div>
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<div class="line"><a name="l00066"></a><span class="lineno"> 66</span>  <a class="code" href="same54n19a_8h.html#a49136ad5bf1adc9e9a0232349bcdce57">OSCCTRL</a>->XOSCCTRL[0].bit.RUNSTDBY = <a class="code" href="conf__core_8h.html#afac0686157854cc021424410ded071f1">CONF_CORE_CLK_XOSC0_RUNSTDBY</a>;</div>
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<div class="line"><a name="l00067"></a><span class="lineno"> 67</span>  <a class="code" href="same54n19a_8h.html#a49136ad5bf1adc9e9a0232349bcdce57">OSCCTRL</a>->XOSCCTRL[0].bit.ONDEMAND = <a class="code" href="conf__core_8h.html#a5ffaa1551b7ffb8a342b2cc5fbc5950c">CONF_CORE_CLK_XOSC0_ONDEMAND</a>;</div>
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<div class="line"><a name="l00068"></a><span class="lineno"> 68</span>  <a class="code" href="same54n19a_8h.html#a49136ad5bf1adc9e9a0232349bcdce57">OSCCTRL</a>->XOSCCTRL[0].bit.LOWBUFGAIN = <a class="code" href="conf__core_8h.html#aeea7b0d3663bb6d5ccc3218017f9a05b">CONF_CORE_CLK_XOSC0_LOWBUFGAIN</a>;</div>
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<div class="line"><a name="l00069"></a><span class="lineno"> 69</span>  <a class="code" href="same54n19a_8h.html#a49136ad5bf1adc9e9a0232349bcdce57">OSCCTRL</a>->XOSCCTRL[0].bit.IPTAT = CONF_CORE_CLK_XOSC0_IPTAT;</div>
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<div class="line"><a name="l00070"></a><span class="lineno"> 70</span>  <a class="code" href="same54n19a_8h.html#a49136ad5bf1adc9e9a0232349bcdce57">OSCCTRL</a>->XOSCCTRL[0].bit.IMULT = CONF_CORE_CLK_XOSC0_IMULT;</div>
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<div class="line"><a name="l00071"></a><span class="lineno"> 71</span>  <a class="code" href="same54n19a_8h.html#a49136ad5bf1adc9e9a0232349bcdce57">OSCCTRL</a>->XOSCCTRL[0].bit.ENALC = <a class="code" href="conf__core_8h.html#a2683d3721ab44a85e60cfff0d0cbf96e">CONF_CORE_CLK_XOSC0_ENALC</a>;</div>
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<div class="line"><a name="l00072"></a><span class="lineno"> 72</span>  <a class="code" href="same54n19a_8h.html#a49136ad5bf1adc9e9a0232349bcdce57">OSCCTRL</a>->XOSCCTRL[0].bit.CFDEN = <a class="code" href="conf__core_8h.html#a17cd20bb954bc137251cf7fb63889151">CONF_CORE_CLK_XOSC0_CFDEN</a>;</div>
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<div class="line"><a name="l00073"></a><span class="lineno"> 73</span>  <a class="code" href="same54n19a_8h.html#a49136ad5bf1adc9e9a0232349bcdce57">OSCCTRL</a>->XOSCCTRL[0].bit.CFDPRESC = CONF_CORE_CLK_XOSC0_CFDPRESC;</div>
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<div class="line"><a name="l00074"></a><span class="lineno"> 74</span>  <a class="code" href="same54n19a_8h.html#a49136ad5bf1adc9e9a0232349bcdce57">OSCCTRL</a>->XOSCCTRL[0].bit.SWBEN = <a class="code" href="conf__core_8h.html#abe235b3b13f253acb855d15c8f33c95a">CONF_CORE_CLK_XOSC0_SWBEN</a>;</div>
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<div class="line"><a name="l00075"></a><span class="lineno"> 75</span>  <a class="code" href="same54n19a_8h.html#a49136ad5bf1adc9e9a0232349bcdce57">OSCCTRL</a>->XOSCCTRL[0].bit.STARTUP = <a class="code" href="conf__core_8h.html#affc8201cf2340d2236ba9ca44a1e657c">CONF_CORE_CLK_XOSC0_STARTUP_TIME</a>;</div>
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<div class="line"><a name="l00076"></a><span class="lineno"> 76</span>  <a class="code" href="same54n19a_8h.html#a49136ad5bf1adc9e9a0232349bcdce57">OSCCTRL</a>->XOSCCTRL[0].bit.ENABLE = <a class="code" href="conf__core_8h.html#a61559adc856ce1dcfa046e749af63bc3">CONF_CORE_CLK_XOSC0_ENABLE</a>;</div>
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<div class="line"><a name="l00077"></a><span class="lineno"> 77</span>  CRITICAL_SECTION_LEAVE();</div>
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<div class="line"><a name="l00078"></a><span class="lineno"> 78</span>  <span class="keywordflow">while</span>(0 == <a class="code" href="same54n19a_8h.html#a49136ad5bf1adc9e9a0232349bcdce57">OSCCTRL</a>->STATUS.bit.XOSCRDY0);</div>
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<div class="line"><a name="l00079"></a><span class="lineno"> 79</span> <span class="preprocessor">#endif</span></div>
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<div class="line"><a name="l00080"></a><span class="lineno"> 80</span>  </div>
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<div class="line"><a name="l00081"></a><span class="lineno"> 81</span> <span class="preprocessor">#if CONF_CORE_CLK_XOSC1_ENABLE == 1</span></div>
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<div class="line"><a name="l00082"></a><span class="lineno"> 82</span>  CRITICAL_SECTION_ENTER();</div>
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<div class="line"><a name="l00083"></a><span class="lineno"> 83</span>  <a class="code" href="same54n19a_8h.html#a49136ad5bf1adc9e9a0232349bcdce57">OSCCTRL</a>->XOSCCTRL[1].bit.XTALEN = <a class="code" href="conf__core_8h.html#ae3f8741e2be4b37a46dfb49af2c2a09d">CONF_CORE_CLK_XOSC1_XTALEN</a>;</div>
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<div class="line"><a name="l00084"></a><span class="lineno"> 84</span>  <a class="code" href="same54n19a_8h.html#a49136ad5bf1adc9e9a0232349bcdce57">OSCCTRL</a>->XOSCCTRL[1].bit.RUNSTDBY = <a class="code" href="conf__core_8h.html#a8bec34fdc01ac38ec0c2d13112f28aa0">CONF_CORE_CLK_XOSC1_RUNSTDBY</a>;</div>
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<div class="line"><a name="l00085"></a><span class="lineno"> 85</span>  <a class="code" href="same54n19a_8h.html#a49136ad5bf1adc9e9a0232349bcdce57">OSCCTRL</a>->XOSCCTRL[1].bit.LOWBUFGAIN = <a class="code" href="conf__core_8h.html#a985ebd23986d9411d3602040e33bb405">CONF_CORE_CLK_XOSC1_LOWBUFGAIN</a>;</div>
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<div class="line"><a name="l00086"></a><span class="lineno"> 86</span>  <a class="code" href="same54n19a_8h.html#a49136ad5bf1adc9e9a0232349bcdce57">OSCCTRL</a>->XOSCCTRL[1].bit.IPTAT = CONF_CORE_CLK_XOSC1_IPTAT;</div>
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<div class="line"><a name="l00087"></a><span class="lineno"> 87</span>  <a class="code" href="same54n19a_8h.html#a49136ad5bf1adc9e9a0232349bcdce57">OSCCTRL</a>->XOSCCTRL[1].bit.IMULT = CONF_CORE_CLK_XOSC1_IMULT;</div>
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<div class="line"><a name="l00088"></a><span class="lineno"> 88</span>  <a class="code" href="same54n19a_8h.html#a49136ad5bf1adc9e9a0232349bcdce57">OSCCTRL</a>->XOSCCTRL[1].bit.CFDEN = <a class="code" href="conf__core_8h.html#a924214b0f469bde71ff28fe5544466db">CONF_CORE_CLK_XOSC1_CFDEN</a>;</div>
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<div class="line"><a name="l00089"></a><span class="lineno"> 89</span>  <a class="code" href="same54n19a_8h.html#a49136ad5bf1adc9e9a0232349bcdce57">OSCCTRL</a>->XOSCCTRL[1].bit.CFDPRESC = CONF_CORE_CLK_XOSC1_CFDPRESC;</div>
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<div class="line"><a name="l00090"></a><span class="lineno"> 90</span>  <a class="code" href="same54n19a_8h.html#a49136ad5bf1adc9e9a0232349bcdce57">OSCCTRL</a>->XOSCCTRL[1].bit.SWBEN = <a class="code" href="conf__core_8h.html#a590b1e68a3f666bdea576a32f4e74ba0">CONF_CORE_CLK_XOSC1_SWBEN</a>;</div>
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<div class="line"><a name="l00091"></a><span class="lineno"> 91</span>  <a class="code" href="same54n19a_8h.html#a49136ad5bf1adc9e9a0232349bcdce57">OSCCTRL</a>->XOSCCTRL[1].bit.STARTUP = <a class="code" href="conf__core_8h.html#ae8d2fdac3b52964174863149986db625">CONF_CORE_CLK_XOSC1_STARTUP_TIME</a>;</div>
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<div class="line"><a name="l00092"></a><span class="lineno"> 92</span>  <a class="code" href="same54n19a_8h.html#a49136ad5bf1adc9e9a0232349bcdce57">OSCCTRL</a>->XOSCCTRL[1].bit.ENABLE = <a class="code" href="conf__core_8h.html#aa54465cc56631333a22ae84ab66d5f3a">CONF_CORE_CLK_XOSC1_ENABLE</a>;</div>
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<div class="line"><a name="l00093"></a><span class="lineno"> 93</span>  CRITICAL_SECTION_LEAVE();</div>
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<div class="line"><a name="l00094"></a><span class="lineno"> 94</span>  <span class="keywordflow">while</span>(0 == <a class="code" href="same54n19a_8h.html#a49136ad5bf1adc9e9a0232349bcdce57">OSCCTRL</a>->STATUS.bit.XOSCRDY1);</div>
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<div class="line"><a name="l00095"></a><span class="lineno"> 95</span> <span class="preprocessor">#endif</span></div>
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<div class="line"><a name="l00096"></a><span class="lineno"> 96</span>  </div>
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<div class="line"><a name="l00097"></a><span class="lineno"> 97</span> <span class="preprocessor">#if CONF_CORE_CLK_XOSC0_ENABLE == 1</span></div>
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<div class="line"><a name="l00098"></a><span class="lineno"> 98</span>  CRITICAL_SECTION_ENTER();</div>
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<div class="line"><a name="l00099"></a><span class="lineno"> 99</span> <span class="preprocessor">#if CONF_CORE_CLK_XOSC0_ENALC == 1</span></div>
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<div class="line"><a name="l00100"></a><span class="lineno"> 100</span>  <a class="code" href="same54n19a_8h.html#a49136ad5bf1adc9e9a0232349bcdce57">OSCCTRL</a>->XOSCCTRL[0].bit.ENALC = <a class="code" href="conf__core_8h.html#a2683d3721ab44a85e60cfff0d0cbf96e">CONF_CORE_CLK_XOSC0_ENALC</a>;</div>
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<div class="line"><a name="l00101"></a><span class="lineno"> 101</span> <span class="preprocessor">#endif</span></div>
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<div class="line"><a name="l00102"></a><span class="lineno"> 102</span>  </div>
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<div class="line"><a name="l00103"></a><span class="lineno"> 103</span> <span class="preprocessor">#if CONF_CORE_CLK_XOSC0_ONDEMAND == 1</span></div>
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<div class="line"><a name="l00104"></a><span class="lineno"> 104</span>  <a class="code" href="same54n19a_8h.html#a49136ad5bf1adc9e9a0232349bcdce57">OSCCTRL</a>->XOSCCTRL[0].bit.ONDEMAND = <a class="code" href="conf__core_8h.html#a5ffaa1551b7ffb8a342b2cc5fbc5950c">CONF_CORE_CLK_XOSC0_ONDEMAND</a>;</div>
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<div class="line"><a name="l00105"></a><span class="lineno"> 105</span> <span class="preprocessor">#endif</span></div>
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<div class="line"><a name="l00106"></a><span class="lineno"> 106</span>  CRITICAL_SECTION_LEAVE();</div>
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<div class="line"><a name="l00107"></a><span class="lineno"> 107</span> <span class="preprocessor">#endif</span></div>
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<div class="line"><a name="l00108"></a><span class="lineno"> 108</span>  </div>
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<div class="line"><a name="l00109"></a><span class="lineno"> 109</span> <span class="preprocessor">#if CONF_CORE_CLK_XOSC1_ENABLE == 1</span></div>
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<div class="line"><a name="l00110"></a><span class="lineno"> 110</span>  CRITICAL_SECTION_ENTER();</div>
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<div class="line"><a name="l00111"></a><span class="lineno"> 111</span> <span class="preprocessor">#if CONF_CORE_CLK_XOSC1_ENALC == 1</span></div>
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<div class="line"><a name="l00112"></a><span class="lineno"> 112</span>  <a class="code" href="same54n19a_8h.html#a49136ad5bf1adc9e9a0232349bcdce57">OSCCTRL</a>->XOSCCTRL[1].bit.ENALC = <a class="code" href="conf__core_8h.html#a3a42de5c6251540e7b8c000974acfc62">CONF_CORE_CLK_XOSC1_ENALC</a>;</div>
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<div class="line"><a name="l00113"></a><span class="lineno"> 113</span> <span class="preprocessor">#endif</span></div>
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<div class="line"><a name="l00114"></a><span class="lineno"> 114</span>  </div>
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<div class="line"><a name="l00115"></a><span class="lineno"> 115</span> <span class="preprocessor">#if CONF_CORE_CLK_XOSC1_ONDEMAND == 1</span></div>
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<div class="line"><a name="l00116"></a><span class="lineno"> 116</span>  <a class="code" href="same54n19a_8h.html#a49136ad5bf1adc9e9a0232349bcdce57">OSCCTRL</a>->XOSCCTRL[1].bit.ONDEMAND = <a class="code" href="conf__core_8h.html#aaf561ace0fee1e373536a251ce8a9726">CONF_CORE_CLK_XOSC1_ONDEMAND</a>;</div>
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<div class="line"><a name="l00117"></a><span class="lineno"> 117</span> <span class="preprocessor">#endif</span></div>
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<div class="line"><a name="l00118"></a><span class="lineno"> 118</span>  CRITICAL_SECTION_LEAVE();</div>
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<div class="line"><a name="l00119"></a><span class="lineno"> 119</span> <span class="preprocessor">#endif</span></div>
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<div class="line"><a name="l00120"></a><span class="lineno"> 120</span> }</div>
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<div class="line"><a name="l00121"></a><span class="lineno"> 121</span>  </div>
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<div class="line"><a name="l00122"></a><span class="lineno"> 122</span> <span class="keywordtype">void</span> clock_mclk_init(<span class="keywordtype">void</span>)</div>
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<div class="line"><a name="l00123"></a><span class="lineno"> 123</span> {</div>
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<div class="line"><a name="l00124"></a><span class="lineno"> 124</span>  CRITICAL_SECTION_ENTER();</div>
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<div class="line"><a name="l00125"></a><span class="lineno"> 125</span>  <a class="code" href="same54n19a_8h.html#a625e6fdb4c2120fc163e1b04178af3dd">MCLK</a>->CPUDIV.reg = <a class="code" href="conf__core_8h.html#aa9643e96439d0d47e0684a4b11c1f529">CONF_CORE_MCLK_CPUDIV</a>;</div>
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<div class="line"><a name="l00126"></a><span class="lineno"> 126</span>  CRITICAL_SECTION_LEAVE();</div>
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<div class="line"><a name="l00127"></a><span class="lineno"> 127</span> }</div>
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<div class="line"><a name="l00128"></a><span class="lineno"> 128</span>  </div>
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<div class="line"><a name="l00129"></a><span class="lineno"> 129</span> <span class="keywordtype">void</span> clock_gclk_init(<span class="keywordtype">void</span>)</div>
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<div class="line"><a name="l00130"></a><span class="lineno"> 130</span> {</div>
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<div class="line"><a name="l00131"></a><span class="lineno"> 131</span> <span class="preprocessor">#if CONF_CORE_GCLK_0_ENABLE == 1</span></div>
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<div class="line"><a name="l00132"></a><span class="lineno"> 132</span>  CRITICAL_SECTION_ENTER();</div>
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<div class="line"><a name="l00133"></a><span class="lineno"> 133</span>  <a class="code" href="same54n19a_8h.html#a23f9186cfd6ee5e60c8485315183271f">GCLK</a>->GENCTRL[0].bit.DIV = CONF_CORE_GCLK_0_DIV_VAL;</div>
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<div class="line"><a name="l00134"></a><span class="lineno"> 134</span>  <a class="code" href="same54n19a_8h.html#a23f9186cfd6ee5e60c8485315183271f">GCLK</a>->GENCTRL[0].bit.DIVSEL = CONF_CORE_GCLK_0_DIVSEL;</div>
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<div class="line"><a name="l00135"></a><span class="lineno"> 135</span>  <a class="code" href="same54n19a_8h.html#a23f9186cfd6ee5e60c8485315183271f">GCLK</a>->GENCTRL[0].bit.RUNSTDBY = CONF_CORE_GCLK_0_RUN_IN_STANDBY;</div>
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<div class="line"><a name="l00136"></a><span class="lineno"> 136</span>  <a class="code" href="same54n19a_8h.html#a23f9186cfd6ee5e60c8485315183271f">GCLK</a>->GENCTRL[0].bit.OE = CONF_CORE_GCLK_0_OUTPUT_ENABLE;</div>
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<div class="line"><a name="l00137"></a><span class="lineno"> 137</span>  <a class="code" href="same54n19a_8h.html#a23f9186cfd6ee5e60c8485315183271f">GCLK</a>->GENCTRL[0].bit.OOV = CONF_CORE_GCLK_0_DIVSEL;</div>
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<div class="line"><a name="l00138"></a><span class="lineno"> 138</span>  <a class="code" href="same54n19a_8h.html#a23f9186cfd6ee5e60c8485315183271f">GCLK</a>->GENCTRL[0].bit.IDC = CONF_CORE_GCLK_0_IDC;</div>
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<div class="line"><a name="l00139"></a><span class="lineno"> 139</span>  <a class="code" href="same54n19a_8h.html#a23f9186cfd6ee5e60c8485315183271f">GCLK</a>->GENCTRL[0].bit.GENEN = CONF_CORE_GCLK_0_ENABLE;</div>
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<div class="line"><a name="l00140"></a><span class="lineno"> 140</span>  <a class="code" href="same54n19a_8h.html#a23f9186cfd6ee5e60c8485315183271f">GCLK</a>->GENCTRL[0].bit.SRC = CONF_CORE_GCLK_0_CLOCK_SOURCE;</div>
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<div class="line"><a name="l00141"></a><span class="lineno"> 141</span>  CRITICAL_SECTION_LEAVE();</div>
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<div class="line"><a name="l00142"></a><span class="lineno"> 142</span> <span class="preprocessor">#endif</span></div>
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<div class="line"><a name="l00143"></a><span class="lineno"> 143</span> <span class="preprocessor">#if CONF_CORE_GCLK_1_ENABLE == 1</span></div>
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<div class="line"><a name="l00144"></a><span class="lineno"> 144</span>  CRITICAL_SECTION_ENTER();</div>
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<div class="line"><a name="l00145"></a><span class="lineno"> 145</span>  <a class="code" href="same54n19a_8h.html#a23f9186cfd6ee5e60c8485315183271f">GCLK</a>->GENCTRL[1].bit.DIV = CONF_CORE_GCLK_1_DIV_VAL;</div>
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<div class="line"><a name="l00146"></a><span class="lineno"> 146</span>  <a class="code" href="same54n19a_8h.html#a23f9186cfd6ee5e60c8485315183271f">GCLK</a>->GENCTRL[1].bit.DIVSEL = CONF_CORE_GCLK_1_DIVSEL;</div>
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<div class="line"><a name="l00147"></a><span class="lineno"> 147</span>  <a class="code" href="same54n19a_8h.html#a23f9186cfd6ee5e60c8485315183271f">GCLK</a>->GENCTRL[1].bit.RUNSTDBY = CONF_CORE_GCLK_1_RUN_IN_STANDBY;</div>
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<div class="line"><a name="l00148"></a><span class="lineno"> 148</span>  <a class="code" href="same54n19a_8h.html#a23f9186cfd6ee5e60c8485315183271f">GCLK</a>->GENCTRL[1].bit.OE = CONF_CORE_GCLK_1_OUTPUT_ENABLE;</div>
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<div class="line"><a name="l00149"></a><span class="lineno"> 149</span>  <a class="code" href="same54n19a_8h.html#a23f9186cfd6ee5e60c8485315183271f">GCLK</a>->GENCTRL[1].bit.OOV = CONF_CORE_GCLK_1_DIVSEL;</div>
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<div class="line"><a name="l00150"></a><span class="lineno"> 150</span>  <a class="code" href="same54n19a_8h.html#a23f9186cfd6ee5e60c8485315183271f">GCLK</a>->GENCTRL[1].bit.IDC = CONF_CORE_GCLK_1_IDC;</div>
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<div class="line"><a name="l00151"></a><span class="lineno"> 151</span>  <a class="code" href="same54n19a_8h.html#a23f9186cfd6ee5e60c8485315183271f">GCLK</a>->GENCTRL[1].bit.GENEN = CONF_CORE_GCLK_1_ENABLE;</div>
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<div class="line"><a name="l00152"></a><span class="lineno"> 152</span>  <a class="code" href="same54n19a_8h.html#a23f9186cfd6ee5e60c8485315183271f">GCLK</a>->GENCTRL[1].bit.SRC = CONF_CORE_GCLK_1_CLOCK_SOURCE;</div>
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<div class="line"><a name="l00153"></a><span class="lineno"> 153</span>  CRITICAL_SECTION_LEAVE();</div>
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<div class="line"><a name="l00154"></a><span class="lineno"> 154</span> <span class="preprocessor">#endif</span></div>
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<div class="line"><a name="l00155"></a><span class="lineno"> 155</span> <span class="preprocessor">#if CONF_CORE_GCLK_2_ENABLE == 1</span></div>
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<div class="line"><a name="l00156"></a><span class="lineno"> 156</span>  CRITICAL_SECTION_ENTER();</div>
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<div class="line"><a name="l00157"></a><span class="lineno"> 157</span>  <a class="code" href="same54n19a_8h.html#a23f9186cfd6ee5e60c8485315183271f">GCLK</a>->GENCTRL[2].bit.DIV = CONF_CORE_GCLK_2_DIV_VAL;</div>
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<div class="line"><a name="l00158"></a><span class="lineno"> 158</span>  <a class="code" href="same54n19a_8h.html#a23f9186cfd6ee5e60c8485315183271f">GCLK</a>->GENCTRL[2].bit.DIVSEL = CONF_CORE_GCLK_2_DIVSEL;</div>
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<div class="line"><a name="l00159"></a><span class="lineno"> 159</span>  <a class="code" href="same54n19a_8h.html#a23f9186cfd6ee5e60c8485315183271f">GCLK</a>->GENCTRL[2].bit.RUNSTDBY = CONF_CORE_GCLK_2_RUN_IN_STANDBY;</div>
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<div class="line"><a name="l00160"></a><span class="lineno"> 160</span>  <a class="code" href="same54n19a_8h.html#a23f9186cfd6ee5e60c8485315183271f">GCLK</a>->GENCTRL[2].bit.OE = CONF_CORE_GCLK_2_OUTPUT_ENABLE;</div>
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<div class="line"><a name="l00161"></a><span class="lineno"> 161</span>  <a class="code" href="same54n19a_8h.html#a23f9186cfd6ee5e60c8485315183271f">GCLK</a>->GENCTRL[2].bit.OOV = CONF_CORE_GCLK_2_DIVSEL;</div>
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<div class="line"><a name="l00162"></a><span class="lineno"> 162</span>  <a class="code" href="same54n19a_8h.html#a23f9186cfd6ee5e60c8485315183271f">GCLK</a>->GENCTRL[2].bit.IDC = CONF_CORE_GCLK_2_IDC;</div>
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<div class="line"><a name="l00163"></a><span class="lineno"> 163</span>  <a class="code" href="same54n19a_8h.html#a23f9186cfd6ee5e60c8485315183271f">GCLK</a>->GENCTRL[2].bit.GENEN = CONF_CORE_GCLK_2_ENABLE;</div>
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<div class="line"><a name="l00164"></a><span class="lineno"> 164</span>  <a class="code" href="same54n19a_8h.html#a23f9186cfd6ee5e60c8485315183271f">GCLK</a>->GENCTRL[2].bit.SRC = CONF_CORE_GCLK_2_CLOCK_SOURCE;</div>
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<div class="line"><a name="l00165"></a><span class="lineno"> 165</span>  CRITICAL_SECTION_LEAVE();</div>
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<div class="line"><a name="l00166"></a><span class="lineno"> 166</span> <span class="preprocessor">#endif</span></div>
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<div class="line"><a name="l00167"></a><span class="lineno"> 167</span> <span class="preprocessor">#if CONF_CORE_GCLK_3_ENABLE == 1</span></div>
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<div class="line"><a name="l00168"></a><span class="lineno"> 168</span>  CRITICAL_SECTION_ENTER();</div>
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<div class="line"><a name="l00169"></a><span class="lineno"> 169</span>  <a class="code" href="same54n19a_8h.html#a23f9186cfd6ee5e60c8485315183271f">GCLK</a>->GENCTRL[3].bit.DIV = CONF_CORE_GCLK_3_DIV_VAL;</div>
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<div class="line"><a name="l00170"></a><span class="lineno"> 170</span>  <a class="code" href="same54n19a_8h.html#a23f9186cfd6ee5e60c8485315183271f">GCLK</a>->GENCTRL[3].bit.DIVSEL = CONF_CORE_GCLK_3_DIVSEL;</div>
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<div class="line"><a name="l00171"></a><span class="lineno"> 171</span>  <a class="code" href="same54n19a_8h.html#a23f9186cfd6ee5e60c8485315183271f">GCLK</a>->GENCTRL[3].bit.RUNSTDBY = CONF_CORE_GCLK_3_RUN_IN_STANDBY;</div>
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<div class="line"><a name="l00172"></a><span class="lineno"> 172</span>  <a class="code" href="same54n19a_8h.html#a23f9186cfd6ee5e60c8485315183271f">GCLK</a>->GENCTRL[3].bit.OE = CONF_CORE_GCLK_3_OUTPUT_ENABLE;</div>
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<div class="line"><a name="l00173"></a><span class="lineno"> 173</span>  <a class="code" href="same54n19a_8h.html#a23f9186cfd6ee5e60c8485315183271f">GCLK</a>->GENCTRL[3].bit.OOV = CONF_CORE_GCLK_3_DIVSEL;</div>
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<div class="line"><a name="l00174"></a><span class="lineno"> 174</span>  <a class="code" href="same54n19a_8h.html#a23f9186cfd6ee5e60c8485315183271f">GCLK</a>->GENCTRL[3].bit.IDC = CONF_CORE_GCLK_3_IDC;</div>
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<div class="line"><a name="l00175"></a><span class="lineno"> 175</span>  <a class="code" href="same54n19a_8h.html#a23f9186cfd6ee5e60c8485315183271f">GCLK</a>->GENCTRL[3].bit.GENEN = CONF_CORE_GCLK_3_ENABLE;</div>
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<div class="line"><a name="l00176"></a><span class="lineno"> 176</span>  <a class="code" href="same54n19a_8h.html#a23f9186cfd6ee5e60c8485315183271f">GCLK</a>->GENCTRL[3].bit.SRC = CONF_CORE_GCLK_3_CLOCK_SOURCE;</div>
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<div class="line"><a name="l00177"></a><span class="lineno"> 177</span>  CRITICAL_SECTION_LEAVE();</div>
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<div class="line"><a name="l00178"></a><span class="lineno"> 178</span> <span class="preprocessor">#endif</span></div>
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<div class="line"><a name="l00179"></a><span class="lineno"> 179</span> <span class="preprocessor">#if CONF_CORE_GCLK_4_ENABLE == 1</span></div>
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<div class="line"><a name="l00180"></a><span class="lineno"> 180</span>  CRITICAL_SECTION_ENTER();</div>
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<div class="line"><a name="l00181"></a><span class="lineno"> 181</span>  <a class="code" href="same54n19a_8h.html#a23f9186cfd6ee5e60c8485315183271f">GCLK</a>->GENCTRL[4].bit.DIV = CONF_CORE_GCLK_4_DIV_VAL;</div>
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<div class="line"><a name="l00182"></a><span class="lineno"> 182</span>  <a class="code" href="same54n19a_8h.html#a23f9186cfd6ee5e60c8485315183271f">GCLK</a>->GENCTRL[4].bit.DIVSEL = CONF_CORE_GCLK_4_DIVSEL;</div>
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<div class="line"><a name="l00183"></a><span class="lineno"> 183</span>  <a class="code" href="same54n19a_8h.html#a23f9186cfd6ee5e60c8485315183271f">GCLK</a>->GENCTRL[4].bit.RUNSTDBY = CONF_CORE_GCLK_4_RUN_IN_STANDBY;</div>
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<div class="line"><a name="l00184"></a><span class="lineno"> 184</span>  <a class="code" href="same54n19a_8h.html#a23f9186cfd6ee5e60c8485315183271f">GCLK</a>->GENCTRL[4].bit.OE = CONF_CORE_GCLK_4_OUTPUT_ENABLE;</div>
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<div class="line"><a name="l00185"></a><span class="lineno"> 185</span>  <a class="code" href="same54n19a_8h.html#a23f9186cfd6ee5e60c8485315183271f">GCLK</a>->GENCTRL[4].bit.OOV = CONF_CORE_GCLK_4_DIVSEL;</div>
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<div class="line"><a name="l00186"></a><span class="lineno"> 186</span>  <a class="code" href="same54n19a_8h.html#a23f9186cfd6ee5e60c8485315183271f">GCLK</a>->GENCTRL[4].bit.IDC = CONF_CORE_GCLK_4_IDC;</div>
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<div class="line"><a name="l00187"></a><span class="lineno"> 187</span>  <a class="code" href="same54n19a_8h.html#a23f9186cfd6ee5e60c8485315183271f">GCLK</a>->GENCTRL[4].bit.GENEN = CONF_CORE_GCLK_4_ENABLE;</div>
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<div class="line"><a name="l00188"></a><span class="lineno"> 188</span>  <a class="code" href="same54n19a_8h.html#a23f9186cfd6ee5e60c8485315183271f">GCLK</a>->GENCTRL[4].bit.SRC = CONF_CORE_GCLK_4_CLOCK_SOURCE;</div>
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<div class="line"><a name="l00189"></a><span class="lineno"> 189</span>  CRITICAL_SECTION_LEAVE();</div>
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<div class="line"><a name="l00190"></a><span class="lineno"> 190</span> <span class="preprocessor">#endif</span></div>
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<div class="line"><a name="l00191"></a><span class="lineno"> 191</span> <span class="preprocessor">#if CONF_CORE_GCLK_5_ENABLE == 1</span></div>
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<div class="line"><a name="l00192"></a><span class="lineno"> 192</span>  CRITICAL_SECTION_ENTER();</div>
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<div class="line"><a name="l00193"></a><span class="lineno"> 193</span>  <a class="code" href="same54n19a_8h.html#a23f9186cfd6ee5e60c8485315183271f">GCLK</a>->GENCTRL[5].bit.DIV = CONF_CORE_GCLK_5_DIV_VAL;</div>
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<div class="line"><a name="l00194"></a><span class="lineno"> 194</span>  <a class="code" href="same54n19a_8h.html#a23f9186cfd6ee5e60c8485315183271f">GCLK</a>->GENCTRL[5].bit.DIVSEL = CONF_CORE_GCLK_5_DIVSEL;</div>
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<div class="line"><a name="l00195"></a><span class="lineno"> 195</span>  <a class="code" href="same54n19a_8h.html#a23f9186cfd6ee5e60c8485315183271f">GCLK</a>->GENCTRL[5].bit.RUNSTDBY = CONF_CORE_GCLK_5_RUN_IN_STANDBY;</div>
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<div class="line"><a name="l00196"></a><span class="lineno"> 196</span>  <a class="code" href="same54n19a_8h.html#a23f9186cfd6ee5e60c8485315183271f">GCLK</a>->GENCTRL[5].bit.OE = CONF_CORE_GCLK_5_OUTPUT_ENABLE;</div>
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<div class="line"><a name="l00197"></a><span class="lineno"> 197</span>  <a class="code" href="same54n19a_8h.html#a23f9186cfd6ee5e60c8485315183271f">GCLK</a>->GENCTRL[5].bit.OOV = CONF_CORE_GCLK_5_DIVSEL;</div>
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<div class="line"><a name="l00198"></a><span class="lineno"> 198</span>  <a class="code" href="same54n19a_8h.html#a23f9186cfd6ee5e60c8485315183271f">GCLK</a>->GENCTRL[5].bit.IDC = CONF_CORE_GCLK_5_IDC;</div>
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<div class="line"><a name="l00199"></a><span class="lineno"> 199</span>  <a class="code" href="same54n19a_8h.html#a23f9186cfd6ee5e60c8485315183271f">GCLK</a>->GENCTRL[5].bit.GENEN = CONF_CORE_GCLK_5_ENABLE;</div>
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<div class="line"><a name="l00200"></a><span class="lineno"> 200</span>  <a class="code" href="same54n19a_8h.html#a23f9186cfd6ee5e60c8485315183271f">GCLK</a>->GENCTRL[5].bit.SRC = CONF_CORE_GCLK_5_CLOCK_SOURCE;</div>
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<div class="line"><a name="l00201"></a><span class="lineno"> 201</span>  CRITICAL_SECTION_LEAVE();</div>
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<div class="line"><a name="l00202"></a><span class="lineno"> 202</span> <span class="preprocessor">#endif</span></div>
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<div class="line"><a name="l00203"></a><span class="lineno"> 203</span> <span class="preprocessor">#if CONF_CORE_GCLK_6_ENABLE == 1</span></div>
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<div class="line"><a name="l00204"></a><span class="lineno"> 204</span>  CRITICAL_SECTION_ENTER();</div>
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<div class="line"><a name="l00205"></a><span class="lineno"> 205</span>  <a class="code" href="same54n19a_8h.html#a23f9186cfd6ee5e60c8485315183271f">GCLK</a>->GENCTRL[6].bit.DIV = CONF_CORE_GCLK_6_DIV_VAL;</div>
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<div class="line"><a name="l00206"></a><span class="lineno"> 206</span>  <a class="code" href="same54n19a_8h.html#a23f9186cfd6ee5e60c8485315183271f">GCLK</a>->GENCTRL[6].bit.DIVSEL = CONF_CORE_GCLK_6_DIVSEL;</div>
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<div class="line"><a name="l00207"></a><span class="lineno"> 207</span>  <a class="code" href="same54n19a_8h.html#a23f9186cfd6ee5e60c8485315183271f">GCLK</a>->GENCTRL[6].bit.RUNSTDBY = CONF_CORE_GCLK_6_RUN_IN_STANDBY;</div>
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<div class="line"><a name="l00208"></a><span class="lineno"> 208</span>  <a class="code" href="same54n19a_8h.html#a23f9186cfd6ee5e60c8485315183271f">GCLK</a>->GENCTRL[6].bit.OE = CONF_CORE_GCLK_6_OUTPUT_ENABLE;</div>
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<div class="line"><a name="l00209"></a><span class="lineno"> 209</span>  <a class="code" href="same54n19a_8h.html#a23f9186cfd6ee5e60c8485315183271f">GCLK</a>->GENCTRL[6].bit.OOV = CONF_CORE_GCLK_6_DIVSEL;</div>
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<div class="line"><a name="l00210"></a><span class="lineno"> 210</span>  <a class="code" href="same54n19a_8h.html#a23f9186cfd6ee5e60c8485315183271f">GCLK</a>->GENCTRL[6].bit.IDC = CONF_CORE_GCLK_6_IDC;</div>
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<div class="line"><a name="l00211"></a><span class="lineno"> 211</span>  <a class="code" href="same54n19a_8h.html#a23f9186cfd6ee5e60c8485315183271f">GCLK</a>->GENCTRL[6].bit.GENEN = CONF_CORE_GCLK_6_ENABLE;</div>
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<div class="line"><a name="l00212"></a><span class="lineno"> 212</span>  <a class="code" href="same54n19a_8h.html#a23f9186cfd6ee5e60c8485315183271f">GCLK</a>->GENCTRL[6].bit.SRC = CONF_CORE_GCLK_6_CLOCK_SOURCE;</div>
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<div class="line"><a name="l00213"></a><span class="lineno"> 213</span>  CRITICAL_SECTION_LEAVE();</div>
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<div class="line"><a name="l00214"></a><span class="lineno"> 214</span> <span class="preprocessor">#endif</span></div>
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<div class="line"><a name="l00215"></a><span class="lineno"> 215</span> <span class="preprocessor">#if CONF_CORE_GCLK_7_ENABLE == 1</span></div>
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<div class="line"><a name="l00216"></a><span class="lineno"> 216</span>  CRITICAL_SECTION_ENTER();</div>
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<div class="line"><a name="l00217"></a><span class="lineno"> 217</span>  <a class="code" href="same54n19a_8h.html#a23f9186cfd6ee5e60c8485315183271f">GCLK</a>->GENCTRL[7].bit.DIV = CONF_CORE_GCLK_7_DIV_VAL;</div>
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<div class="line"><a name="l00218"></a><span class="lineno"> 218</span>  <a class="code" href="same54n19a_8h.html#a23f9186cfd6ee5e60c8485315183271f">GCLK</a>->GENCTRL[7].bit.DIVSEL = CONF_CORE_GCLK_7_DIVSEL;</div>
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<div class="line"><a name="l00219"></a><span class="lineno"> 219</span>  <a class="code" href="same54n19a_8h.html#a23f9186cfd6ee5e60c8485315183271f">GCLK</a>->GENCTRL[7].bit.RUNSTDBY = CONF_CORE_GCLK_7_RUN_IN_STANDBY;</div>
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<div class="line"><a name="l00220"></a><span class="lineno"> 220</span>  <a class="code" href="same54n19a_8h.html#a23f9186cfd6ee5e60c8485315183271f">GCLK</a>->GENCTRL[7].bit.OE = CONF_CORE_GCLK_7_OUTPUT_ENABLE;</div>
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<div class="line"><a name="l00221"></a><span class="lineno"> 221</span>  <a class="code" href="same54n19a_8h.html#a23f9186cfd6ee5e60c8485315183271f">GCLK</a>->GENCTRL[7].bit.OOV = CONF_CORE_GCLK_7_DIVSEL;</div>
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<div class="line"><a name="l00222"></a><span class="lineno"> 222</span>  <a class="code" href="same54n19a_8h.html#a23f9186cfd6ee5e60c8485315183271f">GCLK</a>->GENCTRL[7].bit.IDC = CONF_CORE_GCLK_7_IDC;</div>
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<div class="line"><a name="l00223"></a><span class="lineno"> 223</span>  <a class="code" href="same54n19a_8h.html#a23f9186cfd6ee5e60c8485315183271f">GCLK</a>->GENCTRL[7].bit.GENEN = CONF_CORE_GCLK_7_ENABLE;</div>
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<div class="line"><a name="l00224"></a><span class="lineno"> 224</span>  <a class="code" href="same54n19a_8h.html#a23f9186cfd6ee5e60c8485315183271f">GCLK</a>->GENCTRL[7].bit.SRC = CONF_CORE_GCLK_7_CLOCK_SOURCE;</div>
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<div class="line"><a name="l00225"></a><span class="lineno"> 225</span>  CRITICAL_SECTION_LEAVE();</div>
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<div class="line"><a name="l00226"></a><span class="lineno"> 226</span> <span class="preprocessor">#endif</span></div>
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<div class="line"><a name="l00227"></a><span class="lineno"> 227</span> <span class="preprocessor">#if CONF_CORE_GCLK_8_ENABLE == 1</span></div>
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<div class="line"><a name="l00228"></a><span class="lineno"> 228</span>  CRITICAL_SECTION_ENTER();</div>
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<div class="line"><a name="l00229"></a><span class="lineno"> 229</span>  <a class="code" href="same54n19a_8h.html#a23f9186cfd6ee5e60c8485315183271f">GCLK</a>->GENCTRL[8].bit.DIV = CONF_CORE_GCLK_8_DIV_VAL;</div>
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<div class="line"><a name="l00230"></a><span class="lineno"> 230</span>  <a class="code" href="same54n19a_8h.html#a23f9186cfd6ee5e60c8485315183271f">GCLK</a>->GENCTRL[8].bit.DIVSEL = CONF_CORE_GCLK_8_DIVSEL;</div>
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<div class="line"><a name="l00231"></a><span class="lineno"> 231</span>  <a class="code" href="same54n19a_8h.html#a23f9186cfd6ee5e60c8485315183271f">GCLK</a>->GENCTRL[8].bit.RUNSTDBY = CONF_CORE_GCLK_8_RUN_IN_STANDBY;</div>
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<div class="line"><a name="l00232"></a><span class="lineno"> 232</span>  <a class="code" href="same54n19a_8h.html#a23f9186cfd6ee5e60c8485315183271f">GCLK</a>->GENCTRL[8].bit.OE = CONF_CORE_GCLK_8_OUTPUT_ENABLE;</div>
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<div class="line"><a name="l00233"></a><span class="lineno"> 233</span>  <a class="code" href="same54n19a_8h.html#a23f9186cfd6ee5e60c8485315183271f">GCLK</a>->GENCTRL[8].bit.OOV = CONF_CORE_GCLK_8_DIVSEL;</div>
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<div class="line"><a name="l00234"></a><span class="lineno"> 234</span>  <a class="code" href="same54n19a_8h.html#a23f9186cfd6ee5e60c8485315183271f">GCLK</a>->GENCTRL[8].bit.IDC = CONF_CORE_GCLK_8_IDC;</div>
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<div class="line"><a name="l00235"></a><span class="lineno"> 235</span>  <a class="code" href="same54n19a_8h.html#a23f9186cfd6ee5e60c8485315183271f">GCLK</a>->GENCTRL[8].bit.GENEN = CONF_CORE_GCLK_8_ENABLE;</div>
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<div class="line"><a name="l00236"></a><span class="lineno"> 236</span>  <a class="code" href="same54n19a_8h.html#a23f9186cfd6ee5e60c8485315183271f">GCLK</a>->GENCTRL[8].bit.SRC = CONF_CORE_GCLK_8_CLOCK_SOURCE;</div>
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<div class="line"><a name="l00237"></a><span class="lineno"> 237</span>  CRITICAL_SECTION_LEAVE();</div>
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<div class="line"><a name="l00238"></a><span class="lineno"> 238</span> <span class="preprocessor">#endif</span></div>
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<div class="line"><a name="l00239"></a><span class="lineno"> 239</span> <span class="preprocessor">#if CONF_CORE_GCLK_9_ENABLE == 1</span></div>
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<div class="line"><a name="l00240"></a><span class="lineno"> 240</span>  CRITICAL_SECTION_ENTER();</div>
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<div class="line"><a name="l00241"></a><span class="lineno"> 241</span>  <a class="code" href="same54n19a_8h.html#a23f9186cfd6ee5e60c8485315183271f">GCLK</a>->GENCTRL[9].bit.DIV = CONF_CORE_GCLK_9_DIV_VAL;</div>
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<div class="line"><a name="l00242"></a><span class="lineno"> 242</span>  <a class="code" href="same54n19a_8h.html#a23f9186cfd6ee5e60c8485315183271f">GCLK</a>->GENCTRL[9].bit.DIVSEL = CONF_CORE_GCLK_9_DIVSEL;</div>
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<div class="line"><a name="l00243"></a><span class="lineno"> 243</span>  <a class="code" href="same54n19a_8h.html#a23f9186cfd6ee5e60c8485315183271f">GCLK</a>->GENCTRL[9].bit.RUNSTDBY = CONF_CORE_GCLK_9_RUN_IN_STANDBY;</div>
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<div class="line"><a name="l00244"></a><span class="lineno"> 244</span>  <a class="code" href="same54n19a_8h.html#a23f9186cfd6ee5e60c8485315183271f">GCLK</a>->GENCTRL[9].bit.OE = CONF_CORE_GCLK_9_OUTPUT_ENABLE;</div>
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<div class="line"><a name="l00245"></a><span class="lineno"> 245</span>  <a class="code" href="same54n19a_8h.html#a23f9186cfd6ee5e60c8485315183271f">GCLK</a>->GENCTRL[9].bit.OOV = CONF_CORE_GCLK_9_DIVSEL;</div>
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<div class="line"><a name="l00246"></a><span class="lineno"> 246</span>  <a class="code" href="same54n19a_8h.html#a23f9186cfd6ee5e60c8485315183271f">GCLK</a>->GENCTRL[9].bit.IDC = CONF_CORE_GCLK_9_IDC;</div>
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<div class="line"><a name="l00247"></a><span class="lineno"> 247</span>  <a class="code" href="same54n19a_8h.html#a23f9186cfd6ee5e60c8485315183271f">GCLK</a>->GENCTRL[9].bit.GENEN = CONF_CORE_GCLK_9_ENABLE;</div>
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<div class="line"><a name="l00248"></a><span class="lineno"> 248</span>  <a class="code" href="same54n19a_8h.html#a23f9186cfd6ee5e60c8485315183271f">GCLK</a>->GENCTRL[9].bit.SRC = CONF_CORE_GCLK_9_CLOCK_SOURCE;</div>
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<div class="line"><a name="l00249"></a><span class="lineno"> 249</span>  CRITICAL_SECTION_LEAVE();</div>
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<div class="line"><a name="l00250"></a><span class="lineno"> 250</span> <span class="preprocessor">#endif</span></div>
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<div class="line"><a name="l00251"></a><span class="lineno"> 251</span> <span class="preprocessor">#if CONF_CORE_GCLK_10_ENABLE == 1</span></div>
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<div class="line"><a name="l00252"></a><span class="lineno"> 252</span>  CRITICAL_SECTION_ENTER();</div>
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<div class="line"><a name="l00253"></a><span class="lineno"> 253</span>  <a class="code" href="same54n19a_8h.html#a23f9186cfd6ee5e60c8485315183271f">GCLK</a>->GENCTRL[10].bit.DIV = CONF_CORE_GCLK_10_DIV_VAL;</div>
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<div class="line"><a name="l00254"></a><span class="lineno"> 254</span>  <a class="code" href="same54n19a_8h.html#a23f9186cfd6ee5e60c8485315183271f">GCLK</a>->GENCTRL[10].bit.DIVSEL = CONF_CORE_GCLK_10_DIVSEL;</div>
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<div class="line"><a name="l00255"></a><span class="lineno"> 255</span>  <a class="code" href="same54n19a_8h.html#a23f9186cfd6ee5e60c8485315183271f">GCLK</a>->GENCTRL[10].bit.RUNSTDBY = CONF_CORE_GCLK_10_RUN_IN_STANDBY;</div>
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<div class="line"><a name="l00256"></a><span class="lineno"> 256</span>  <a class="code" href="same54n19a_8h.html#a23f9186cfd6ee5e60c8485315183271f">GCLK</a>->GENCTRL[10].bit.OE = CONF_CORE_GCLK_10_OUTPUT_ENABLE;</div>
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<div class="line"><a name="l00257"></a><span class="lineno"> 257</span>  <a class="code" href="same54n19a_8h.html#a23f9186cfd6ee5e60c8485315183271f">GCLK</a>->GENCTRL[10].bit.OOV = CONF_CORE_GCLK_10_DIVSEL;</div>
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<div class="line"><a name="l00258"></a><span class="lineno"> 258</span>  <a class="code" href="same54n19a_8h.html#a23f9186cfd6ee5e60c8485315183271f">GCLK</a>->GENCTRL[10].bit.IDC = CONF_CORE_GCLK_10_IDC;</div>
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<div class="line"><a name="l00259"></a><span class="lineno"> 259</span>  <a class="code" href="same54n19a_8h.html#a23f9186cfd6ee5e60c8485315183271f">GCLK</a>->GENCTRL[10].bit.GENEN = CONF_CORE_GCLK_10_ENABLE;</div>
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<div class="line"><a name="l00260"></a><span class="lineno"> 260</span>  <a class="code" href="same54n19a_8h.html#a23f9186cfd6ee5e60c8485315183271f">GCLK</a>->GENCTRL[10].bit.SRC = CONF_CORE_GCLK_10_CLOCK_SOURCE;</div>
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<div class="line"><a name="l00261"></a><span class="lineno"> 261</span>  CRITICAL_SECTION_LEAVE();</div>
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<div class="line"><a name="l00262"></a><span class="lineno"> 262</span> <span class="preprocessor">#endif</span></div>
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<div class="line"><a name="l00263"></a><span class="lineno"> 263</span> <span class="preprocessor">#if CONF_CORE_GCLK_11_ENABLE == 1</span></div>
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<div class="line"><a name="l00264"></a><span class="lineno"> 264</span>  CRITICAL_SECTION_ENTER();</div>
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<div class="line"><a name="l00265"></a><span class="lineno"> 265</span>  <a class="code" href="same54n19a_8h.html#a23f9186cfd6ee5e60c8485315183271f">GCLK</a>->GENCTRL[11].bit.DIV = CONF_CORE_GCLK_11_DIV_VAL;</div>
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<div class="line"><a name="l00266"></a><span class="lineno"> 266</span>  <a class="code" href="same54n19a_8h.html#a23f9186cfd6ee5e60c8485315183271f">GCLK</a>->GENCTRL[11].bit.DIVSEL = CONF_CORE_GCLK_11_DIVSEL;</div>
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<div class="line"><a name="l00267"></a><span class="lineno"> 267</span>  <a class="code" href="same54n19a_8h.html#a23f9186cfd6ee5e60c8485315183271f">GCLK</a>->GENCTRL[11].bit.RUNSTDBY = CONF_CORE_GCLK_11_RUN_IN_STANDBY;</div>
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<div class="line"><a name="l00268"></a><span class="lineno"> 268</span>  <a class="code" href="same54n19a_8h.html#a23f9186cfd6ee5e60c8485315183271f">GCLK</a>->GENCTRL[11].bit.OE = CONF_CORE_GCLK_11_OUTPUT_ENABLE;</div>
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<div class="line"><a name="l00269"></a><span class="lineno"> 269</span>  <a class="code" href="same54n19a_8h.html#a23f9186cfd6ee5e60c8485315183271f">GCLK</a>->GENCTRL[11].bit.OOV = CONF_CORE_GCLK_11_DIVSEL;</div>
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<div class="line"><a name="l00270"></a><span class="lineno"> 270</span>  <a class="code" href="same54n19a_8h.html#a23f9186cfd6ee5e60c8485315183271f">GCLK</a>->GENCTRL[11].bit.IDC = CONF_CORE_GCLK_11_IDC;</div>
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<div class="line"><a name="l00271"></a><span class="lineno"> 271</span>  <a class="code" href="same54n19a_8h.html#a23f9186cfd6ee5e60c8485315183271f">GCLK</a>->GENCTRL[11].bit.GENEN = CONF_CORE_GCLK_11_ENABLE;</div>
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<div class="line"><a name="l00272"></a><span class="lineno"> 272</span>  <a class="code" href="same54n19a_8h.html#a23f9186cfd6ee5e60c8485315183271f">GCLK</a>->GENCTRL[11].bit.SRC = CONF_CORE_GCLK_11_CLOCK_SOURCE;</div>
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<div class="line"><a name="l00273"></a><span class="lineno"> 273</span>  CRITICAL_SECTION_LEAVE();</div>
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<div class="line"><a name="l00274"></a><span class="lineno"> 274</span> <span class="preprocessor">#endif</span></div>
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<div class="line"><a name="l00275"></a><span class="lineno"> 275</span> }</div>
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<div class="line"><a name="l00276"></a><span class="lineno"> 276</span>  </div>
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<div class="line"><a name="l00277"></a><span class="lineno"> 277</span> <span class="keywordtype">void</span> clock_dpll_init(<span class="keywordtype">void</span>)</div>
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<div class="line"><a name="l00278"></a><span class="lineno"> 278</span> {</div>
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<div class="line"><a name="l00279"></a><span class="lineno"> 279</span> <span class="preprocessor">#if CONF_CORE_CLK_DPLL0_ENABLE == 1</span></div>
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<div class="line"><a name="l00280"></a><span class="lineno"> 280</span> <span class="preprocessor">#if CONF_CORE_CLK_DPLL0_REFCLK == 0</span></div>
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<div class="line"><a name="l00281"></a><span class="lineno"> 281</span>  CRITICAL_SECTION_ENTER();</div>
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<div class="line"><a name="l00282"></a><span class="lineno"> 282</span>  <a class="code" href="same54n19a_8h.html#a23f9186cfd6ee5e60c8485315183271f">GCLK</a>->PCHCTRL[OSCCTRL_GCLK_ID_FDPLL0].bit.GEN =</div>
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<div class="line"><a name="l00283"></a><span class="lineno"> 283</span>  GCLK_PCHCTRL_GEN(CONF_CORE_CLK_DPLL0_GCLK_SRC);</div>
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<div class="line"><a name="l00284"></a><span class="lineno"> 284</span>  <a class="code" href="same54n19a_8h.html#a23f9186cfd6ee5e60c8485315183271f">GCLK</a>->PCHCTRL[OSCCTRL_GCLK_ID_FDPLL0].bit.CHEN =</div>
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<div class="line"><a name="l00285"></a><span class="lineno"> 285</span>  CONF_CORE_CLK_DPLL0_ENABLE;</div>
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<div class="line"><a name="l00286"></a><span class="lineno"> 286</span>  CRITICAL_SECTION_LEAVE();</div>
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<div class="line"><a name="l00287"></a><span class="lineno"> 287</span> <span class="preprocessor">#endif</span></div>
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<div class="line"><a name="l00288"></a><span class="lineno"> 288</span>  </div>
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<div class="line"><a name="l00289"></a><span class="lineno"> 289</span>  CRITICAL_SECTION_ENTER();</div>
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<div class="line"><a name="l00290"></a><span class="lineno"> 290</span>  <span class="comment">// write dpll ratio</span></div>
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<div class="line"><a name="l00291"></a><span class="lineno"> 291</span>  <a class="code" href="same54n19a_8h.html#a49136ad5bf1adc9e9a0232349bcdce57">OSCCTRL</a>->Dpll[0].DPLLRATIO.bit.LDRFRAC = CONF_CORE_CLK_DPLL0_LDRFRAC_VAL;</div>
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<div class="line"><a name="l00292"></a><span class="lineno"> 292</span>  <a class="code" href="same54n19a_8h.html#a49136ad5bf1adc9e9a0232349bcdce57">OSCCTRL</a>->Dpll[0].DPLLRATIO.bit.LDR = CONF_CORE_CLK_DPLL0_LDR_VAL;</div>
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<div class="line"><a name="l00293"></a><span class="lineno"> 293</span>  </div>
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<div class="line"><a name="l00294"></a><span class="lineno"> 294</span>  <span class="comment">// write dpll ctrlb</span></div>
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<div class="line"><a name="l00295"></a><span class="lineno"> 295</span>  <a class="code" href="same54n19a_8h.html#a49136ad5bf1adc9e9a0232349bcdce57">OSCCTRL</a>->Dpll[0].DPLLCTRLB.bit.DIV = CONF_CORE_CLK_DPLL0_DIV_VAL;</div>
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<div class="line"><a name="l00296"></a><span class="lineno"> 296</span>  <a class="code" href="same54n19a_8h.html#a49136ad5bf1adc9e9a0232349bcdce57">OSCCTRL</a>->Dpll[0].DPLLCTRLB.bit.DCOEN = CONF_CORE_CLK_DPLL0_DCOEN;</div>
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<div class="line"><a name="l00297"></a><span class="lineno"> 297</span>  <a class="code" href="same54n19a_8h.html#a49136ad5bf1adc9e9a0232349bcdce57">OSCCTRL</a>->Dpll[0].DPLLCTRLB.bit.DCOFILTER = CONF_CORE_CLK_DPLL0_DCOFILTER;</div>
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<div class="line"><a name="l00298"></a><span class="lineno"> 298</span>  <a class="code" href="same54n19a_8h.html#a49136ad5bf1adc9e9a0232349bcdce57">OSCCTRL</a>->Dpll[0].DPLLCTRLB.bit.LBYPASS = CONF_CORE_CLK_DPLL0_LBYPASS;</div>
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<div class="line"><a name="l00299"></a><span class="lineno"> 299</span>  <a class="code" href="same54n19a_8h.html#a49136ad5bf1adc9e9a0232349bcdce57">OSCCTRL</a>->Dpll[0].DPLLCTRLB.bit.LTIME = CONF_CORE_CLK_DPLL0_LTIME;</div>
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<div class="line"><a name="l00300"></a><span class="lineno"> 300</span>  <a class="code" href="same54n19a_8h.html#a49136ad5bf1adc9e9a0232349bcdce57">OSCCTRL</a>->Dpll[0].DPLLCTRLB.bit.REFCLK = CONF_CORE_CLK_DPLL0_REFCLK;</div>
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<div class="line"><a name="l00301"></a><span class="lineno"> 301</span>  <a class="code" href="same54n19a_8h.html#a49136ad5bf1adc9e9a0232349bcdce57">OSCCTRL</a>->Dpll[0].DPLLCTRLB.bit.WUF = CONF_CORE_CLK_DPLL0_WUF;</div>
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<div class="line"><a name="l00302"></a><span class="lineno"> 302</span>  <a class="code" href="same54n19a_8h.html#a49136ad5bf1adc9e9a0232349bcdce57">OSCCTRL</a>->Dpll[0].DPLLCTRLB.bit.FILTER = <a class="code" href="conf__core_8h.html#a5cd9abca6f486eaebb6ddd236960b01a">CONF_CORE_CLK_DPLL0_FILTER</a>;</div>
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<div class="line"><a name="l00303"></a><span class="lineno"> 303</span>  CRITICAL_SECTION_LEAVE();</div>
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<div class="line"><a name="l00304"></a><span class="lineno"> 304</span>  </div>
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<div class="line"><a name="l00305"></a><span class="lineno"> 305</span>  CRITICAL_SECTION_ENTER();</div>
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<div class="line"><a name="l00306"></a><span class="lineno"> 306</span>  <a class="code" href="same54n19a_8h.html#a49136ad5bf1adc9e9a0232349bcdce57">OSCCTRL</a>->Dpll[0].DPLLCTRLA.reg = 0;</div>
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<div class="line"><a name="l00307"></a><span class="lineno"> 307</span>  <a class="code" href="same54n19a_8h.html#a49136ad5bf1adc9e9a0232349bcdce57">OSCCTRL</a>->Dpll[0].DPLLCTRLA.bit.RUNSTDBY = CONF_CORE_CLK_DPLL0_RUNSTDBY;</div>
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<div class="line"><a name="l00308"></a><span class="lineno"> 308</span>  <a class="code" href="same54n19a_8h.html#a49136ad5bf1adc9e9a0232349bcdce57">OSCCTRL</a>->Dpll[0].DPLLCTRLA.bit.ENABLE = CONF_CORE_CLK_DPLL0_ENABLE;</div>
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<div class="line"><a name="l00309"></a><span class="lineno"> 309</span>  CRITICAL_SECTION_LEAVE();</div>
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<div class="line"><a name="l00310"></a><span class="lineno"> 310</span> <span class="preprocessor">#endif</span></div>
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<div class="line"><a name="l00311"></a><span class="lineno"> 311</span>  </div>
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<div class="line"><a name="l00312"></a><span class="lineno"> 312</span> <span class="preprocessor">#if CONF_CORE_CLK_DPLL1_ENABLE == 1</span></div>
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<div class="line"><a name="l00313"></a><span class="lineno"> 313</span> <span class="preprocessor">#if CONF_CORE_CLK_DPLL0_REFCLK == 0</span></div>
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<div class="line"><a name="l00314"></a><span class="lineno"> 314</span>  CRITICAL_SECTION_ENTER();</div>
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<div class="line"><a name="l00315"></a><span class="lineno"> 315</span>  <a class="code" href="same54n19a_8h.html#a23f9186cfd6ee5e60c8485315183271f">GCLK</a>->PCHCTRL[OSCCTRL_GCLK_ID_FDPLL1].bit.GEN =</div>
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<div class="line"><a name="l00316"></a><span class="lineno"> 316</span>  GCLK_PCHCTRL_GEN(CONF_CORE_CLK_DPLL1_GCLK_SRC);</div>
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<div class="line"><a name="l00317"></a><span class="lineno"> 317</span>  <a class="code" href="same54n19a_8h.html#a23f9186cfd6ee5e60c8485315183271f">GCLK</a>->PCHCTRL[OSCCTRL_GCLK_ID_FDPLL1].bit.CHEN =</div>
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<div class="line"><a name="l00318"></a><span class="lineno"> 318</span>  CONF_CORE_CLK_DPLL1_ENABLE;</div>
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<div class="line"><a name="l00319"></a><span class="lineno"> 319</span>  CRITICAL_SECTION_LEAVE();</div>
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<div class="line"><a name="l00320"></a><span class="lineno"> 320</span> <span class="preprocessor">#endif</span></div>
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<div class="line"><a name="l00321"></a><span class="lineno"> 321</span>  </div>
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<div class="line"><a name="l00322"></a><span class="lineno"> 322</span>  CRITICAL_SECTION_ENTER();</div>
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<div class="line"><a name="l00323"></a><span class="lineno"> 323</span>  <span class="comment">// write dpll ratio</span></div>
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<div class="line"><a name="l00324"></a><span class="lineno"> 324</span>  <a class="code" href="same54n19a_8h.html#a49136ad5bf1adc9e9a0232349bcdce57">OSCCTRL</a>->Dpll[1].DPLLRATIO.bit.LDRFRAC = CONF_CORE_CLK_DPLL1_LDRFRAC_VAL;</div>
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<div class="line"><a name="l00325"></a><span class="lineno"> 325</span>  <a class="code" href="same54n19a_8h.html#a49136ad5bf1adc9e9a0232349bcdce57">OSCCTRL</a>->Dpll[1].DPLLRATIO.bit.LDR = CONF_CORE_CLK_DPLL1_LDR_VAL;</div>
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<div class="line"><a name="l00326"></a><span class="lineno"> 326</span>  <span class="comment">// write dpll ctrlb</span></div>
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<div class="line"><a name="l00327"></a><span class="lineno"> 327</span>  <a class="code" href="same54n19a_8h.html#a49136ad5bf1adc9e9a0232349bcdce57">OSCCTRL</a>->Dpll[1].DPLLCTRLB.bit.DIV = CONF_CORE_CLK_DPLL1_DIV_VAL;</div>
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<div class="line"><a name="l00328"></a><span class="lineno"> 328</span>  <a class="code" href="same54n19a_8h.html#a49136ad5bf1adc9e9a0232349bcdce57">OSCCTRL</a>->Dpll[1].DPLLCTRLB.bit.DCOEN = CONF_CORE_CLK_DPLL1_DCOEN;</div>
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<div class="line"><a name="l00329"></a><span class="lineno"> 329</span>  <a class="code" href="same54n19a_8h.html#a49136ad5bf1adc9e9a0232349bcdce57">OSCCTRL</a>->Dpll[1].DPLLCTRLB.bit.DCOFILTER = CONF_CORE_CLK_DPLL1_DCOFILTER;</div>
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<div class="line"><a name="l00330"></a><span class="lineno"> 330</span>  <a class="code" href="same54n19a_8h.html#a49136ad5bf1adc9e9a0232349bcdce57">OSCCTRL</a>->Dpll[1].DPLLCTRLB.bit.LBYPASS = CONF_CORE_CLK_DPLL1_LBYPASS;</div>
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<div class="line"><a name="l00331"></a><span class="lineno"> 331</span>  <a class="code" href="same54n19a_8h.html#a49136ad5bf1adc9e9a0232349bcdce57">OSCCTRL</a>->Dpll[1].DPLLCTRLB.bit.LTIME = CONF_CORE_CLK_DPLL1_LTIME;</div>
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<div class="line"><a name="l00332"></a><span class="lineno"> 332</span>  <a class="code" href="same54n19a_8h.html#a49136ad5bf1adc9e9a0232349bcdce57">OSCCTRL</a>->Dpll[1].DPLLCTRLB.bit.REFCLK = CONF_CORE_CLK_DPLL1_REFCLK;</div>
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<div class="line"><a name="l00333"></a><span class="lineno"> 333</span>  <a class="code" href="same54n19a_8h.html#a49136ad5bf1adc9e9a0232349bcdce57">OSCCTRL</a>->Dpll[1].DPLLCTRLB.bit.WUF = CONF_CORE_CLK_DPLL1_WUF;</div>
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<div class="line"><a name="l00334"></a><span class="lineno"> 334</span>  <a class="code" href="same54n19a_8h.html#a49136ad5bf1adc9e9a0232349bcdce57">OSCCTRL</a>->Dpll[1].DPLLCTRLB.bit.FILTER = <a class="code" href="conf__core_8h.html#a9de3ab7eb7e3c001d6aa7040f6311f10">CONF_CORE_CLK_DPLL1_FILTER</a>;</div>
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<div class="line"><a name="l00335"></a><span class="lineno"> 335</span>  CRITICAL_SECTION_LEAVE();</div>
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<div class="line"><a name="l00336"></a><span class="lineno"> 336</span>  </div>
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<div class="line"><a name="l00337"></a><span class="lineno"> 337</span>  CRITICAL_SECTION_ENTER();</div>
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<div class="line"><a name="l00338"></a><span class="lineno"> 338</span>  <a class="code" href="same54n19a_8h.html#a49136ad5bf1adc9e9a0232349bcdce57">OSCCTRL</a>->Dpll[1].DPLLCTRLA.reg = 0;</div>
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<div class="line"><a name="l00339"></a><span class="lineno"> 339</span>  <a class="code" href="same54n19a_8h.html#a49136ad5bf1adc9e9a0232349bcdce57">OSCCTRL</a>->Dpll[1].DPLLCTRLA.bit.RUNSTDBY = CONF_CORE_CLK_DPLL1_RUNSTDBY;</div>
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<div class="line"><a name="l00340"></a><span class="lineno"> 340</span>  <a class="code" href="same54n19a_8h.html#a49136ad5bf1adc9e9a0232349bcdce57">OSCCTRL</a>->Dpll[1].DPLLCTRLA.bit.ENABLE = CONF_CORE_CLK_DPLL1_ENABLE;</div>
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<div class="line"><a name="l00341"></a><span class="lineno"> 341</span>  CRITICAL_SECTION_LEAVE();</div>
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<div class="line"><a name="l00342"></a><span class="lineno"> 342</span> <span class="preprocessor">#endif</span></div>
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<div class="line"><a name="l00343"></a><span class="lineno"> 343</span>  </div>
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<div class="line"><a name="l00344"></a><span class="lineno"> 344</span> <span class="preprocessor">#if CONF_CORE_CLK_DPLL0_ENABLE == 1</span></div>
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<div class="line"><a name="l00345"></a><span class="lineno"> 345</span>  <span class="keywordflow">while</span>(!(<a class="code" href="same54n19a_8h.html#a49136ad5bf1adc9e9a0232349bcdce57">OSCCTRL</a>->Dpll[0].DPLLSTATUS.bit.LOCK || <a class="code" href="same54n19a_8h.html#a49136ad5bf1adc9e9a0232349bcdce57">OSCCTRL</a>->Dpll[0].DPLLSTATUS.bit.CLKRDY));</div>
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<div class="line"><a name="l00346"></a><span class="lineno"> 346</span>  CRITICAL_SECTION_ENTER();</div>
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<div class="line"><a name="l00347"></a><span class="lineno"> 347</span> <span class="preprocessor">#if CONF_CORE_CLK_DPLL0_ONDEMAND == 1</span></div>
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<div class="line"><a name="l00348"></a><span class="lineno"> 348</span>  <a class="code" href="same54n19a_8h.html#a49136ad5bf1adc9e9a0232349bcdce57">OSCCTRL</a>->Dpll[0].DPLLCTRLA.bit.ONDEMAND = CONF_CORE_CLK_DPLL0_ONDEMAND;</div>
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<div class="line"><a name="l00349"></a><span class="lineno"> 349</span> <span class="preprocessor">#endif</span></div>
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<div class="line"><a name="l00350"></a><span class="lineno"> 350</span>  CRITICAL_SECTION_LEAVE();</div>
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<div class="line"><a name="l00351"></a><span class="lineno"> 351</span> <span class="preprocessor">#endif</span></div>
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<div class="line"><a name="l00352"></a><span class="lineno"> 352</span>  </div>
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<div class="line"><a name="l00353"></a><span class="lineno"> 353</span> <span class="preprocessor">#if CONF_CORE_CLK_DPLL1_ENABLE == 1</span></div>
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<div class="line"><a name="l00354"></a><span class="lineno"> 354</span>  <span class="keywordflow">while</span>(!(<a class="code" href="same54n19a_8h.html#a49136ad5bf1adc9e9a0232349bcdce57">OSCCTRL</a>->Dpll[1].DPLLSTATUS.bit.LOCK || <a class="code" href="same54n19a_8h.html#a49136ad5bf1adc9e9a0232349bcdce57">OSCCTRL</a>->Dpll[1].DPLLSTATUS.bit.CLKRDY));</div>
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<div class="line"><a name="l00355"></a><span class="lineno"> 355</span>  CRITICAL_SECTION_ENTER();</div>
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<div class="line"><a name="l00356"></a><span class="lineno"> 356</span> <span class="preprocessor">#if CONF_CORE_CLK_DPLL1_ONDEMAND == 1</span></div>
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<div class="line"><a name="l00357"></a><span class="lineno"> 357</span>  <a class="code" href="same54n19a_8h.html#a49136ad5bf1adc9e9a0232349bcdce57">OSCCTRL</a>->Dpll[1].DPLLCTRLA.bit.ONDEMAND = CONF_CORE_CLK_DPLL1_ONDEMAND;</div>
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<div class="line"><a name="l00358"></a><span class="lineno"> 358</span> <span class="preprocessor">#endif</span></div>
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<div class="line"><a name="l00359"></a><span class="lineno"> 359</span>  CRITICAL_SECTION_LEAVE();</div>
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<div class="line"><a name="l00360"></a><span class="lineno"> 360</span> <span class="preprocessor">#endif</span></div>
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<div class="line"><a name="l00361"></a><span class="lineno"> 361</span> }</div>
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<div class="line"><a name="l00362"></a><span class="lineno"> 362</span>  </div>
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<div class="line"><a name="l00363"></a><span class="lineno"> 363</span> <span class="keywordtype">void</span> clock_dfll_init(<span class="keywordtype">void</span>)</div>
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<div class="line"><a name="l00364"></a><span class="lineno"> 364</span> {</div>
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<div class="line"><a name="l00365"></a><span class="lineno"> 365</span> <span class="preprocessor">#if CONF_CORE_CLK_DFLL_ENABLE</span></div>
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<div class="line"><a name="l00366"></a><span class="lineno"> 366</span>  CRITICAL_SECTION_ENTER();</div>
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<div class="line"><a name="l00367"></a><span class="lineno"> 367</span>  <a class="code" href="same54n19a_8h.html#a23f9186cfd6ee5e60c8485315183271f">GCLK</a>->GENCTRL[0].bit.SRC = GCLK_GENCTRL_SRC_OSCULP32K;</div>
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<div class="line"><a name="l00368"></a><span class="lineno"> 368</span>  CRITICAL_SECTION_LEAVE();</div>
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<div class="line"><a name="l00369"></a><span class="lineno"> 369</span>  <span class="keywordflow">while</span>(<a class="code" href="same54n19a_8h.html#a23f9186cfd6ee5e60c8485315183271f">GCLK</a>->SYNCBUSY.bit.GENCTRL0);</div>
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<div class="line"><a name="l00370"></a><span class="lineno"> 370</span>  </div>
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<div class="line"><a name="l00371"></a><span class="lineno"> 371</span>  CRITICAL_SECTION_ENTER();</div>
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<div class="line"><a name="l00372"></a><span class="lineno"> 372</span>  <span class="comment">// reset stuff</span></div>
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<div class="line"><a name="l00373"></a><span class="lineno"> 373</span>  <a class="code" href="same54n19a_8h.html#a49136ad5bf1adc9e9a0232349bcdce57">OSCCTRL</a>->DFLLCTRLA.reg = 0;</div>
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<div class="line"><a name="l00374"></a><span class="lineno"> 374</span>  CRITICAL_SECTION_LEAVE();</div>
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<div class="line"><a name="l00375"></a><span class="lineno"> 375</span> <span class="preprocessor">#if CONF_CORE_CLK_DFLL_USBCRM != 1 && CONF_CORE_CLK_DFLL_MODE != 0</span></div>
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<div class="line"><a name="l00376"></a><span class="lineno"> 376</span>  CRITICAL_SECTION_ENTER();</div>
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<div class="line"><a name="l00377"></a><span class="lineno"> 377</span>  <span class="comment">// reset stuff</span></div>
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<div class="line"><a name="l00378"></a><span class="lineno"> 378</span>  <a class="code" href="same54n19a_8h.html#a23f9186cfd6ee5e60c8485315183271f">GCLK</a>->PCHCTRL[OSCCTRL_GCLK_ID_DFLL48].bit.GEN =</div>
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<div class="line"><a name="l00379"></a><span class="lineno"> 379</span>  GCLK_PCHCTRL_GEN(<a class="code" href="conf__core_8h.html#a0d8e56832f3d1f24b98173e3a3aa0046">CONF_CORE_CLK_DFLL_GCLK_SRC</a>);</div>
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<div class="line"><a name="l00380"></a><span class="lineno"> 380</span>  <a class="code" href="same54n19a_8h.html#a23f9186cfd6ee5e60c8485315183271f">GCLK</a>->PCHCTRL[OSCCTRL_GCLK_ID_DFLL48].bit.EN = <a class="code" href="conf__core_8h.html#a03160c4c7871685bbde0e96f02825842">CONF_CORE_CLK_DFLL_ENABLE</a>;</div>
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<div class="line"><a name="l00381"></a><span class="lineno"> 381</span>  CRITICAL_SECTION_LEAVE();</div>
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<div class="line"><a name="l00382"></a><span class="lineno"> 382</span> <span class="preprocessor">#endif</span></div>
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<div class="line"><a name="l00383"></a><span class="lineno"> 383</span>  </div>
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<div class="line"><a name="l00384"></a><span class="lineno"> 384</span>  CRITICAL_SECTION_ENTER();</div>
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<div class="line"><a name="l00385"></a><span class="lineno"> 385</span>  <span class="comment">// configure clock multiplier stuff</span></div>
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<div class="line"><a name="l00386"></a><span class="lineno"> 386</span>  <a class="code" href="same54n19a_8h.html#a49136ad5bf1adc9e9a0232349bcdce57">OSCCTRL</a>->DFLLMUL.bit.MUL = CONF_CORE_CLK_DFLL_MUL_VAL;</div>
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<div class="line"><a name="l00387"></a><span class="lineno"> 387</span>  <a class="code" href="same54n19a_8h.html#a49136ad5bf1adc9e9a0232349bcdce57">OSCCTRL</a>->DFLLMUL.bit.CSTEP = CONF_CORE_CLK_DFLL_CSTEP_VAL;</div>
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<div class="line"><a name="l00388"></a><span class="lineno"> 388</span>  <a class="code" href="same54n19a_8h.html#a49136ad5bf1adc9e9a0232349bcdce57">OSCCTRL</a>->DFLLMUL.bit.FSTEP = CONF_CORE_CLK_DFLL_FSTEP_VAL;</div>
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<div class="line"><a name="l00389"></a><span class="lineno"> 389</span>  CRITICAL_SECTION_LEAVE();</div>
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<div class="line"><a name="l00390"></a><span class="lineno"> 390</span>  <span class="keywordflow">while</span>(<a class="code" href="same54n19a_8h.html#a49136ad5bf1adc9e9a0232349bcdce57">OSCCTRL</a>->DFLLSYNC.bit.DFLLMUL);</div>
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<div class="line"><a name="l00391"></a><span class="lineno"> 391</span>  </div>
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<div class="line"><a name="l00392"></a><span class="lineno"> 392</span>  CRITICAL_SECTION_ENTER();</div>
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<div class="line"><a name="l00393"></a><span class="lineno"> 393</span>  <span class="comment">// reset dfll ctrlb</span></div>
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<div class="line"><a name="l00394"></a><span class="lineno"> 394</span>  <a class="code" href="same54n19a_8h.html#a49136ad5bf1adc9e9a0232349bcdce57">OSCCTRL</a>->DFLLCTRLB.reg = 0;</div>
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<div class="line"><a name="l00395"></a><span class="lineno"> 395</span>  CRITICAL_SECTION_LEAVE();</div>
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<div class="line"><a name="l00396"></a><span class="lineno"> 396</span>  <span class="comment">// wait for ctrlb sync</span></div>
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<div class="line"><a name="l00397"></a><span class="lineno"> 397</span>  <span class="keywordflow">while</span>(<a class="code" href="same54n19a_8h.html#a49136ad5bf1adc9e9a0232349bcdce57">OSCCTRL</a>->DFLLSYNC.bit.DFLLCTRLB);</div>
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<div class="line"><a name="l00398"></a><span class="lineno"> 398</span>  </div>
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<div class="line"><a name="l00399"></a><span class="lineno"> 399</span>  CRITICAL_SECTION_ENTER();</div>
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<div class="line"><a name="l00400"></a><span class="lineno"> 400</span>  <a class="code" href="same54n19a_8h.html#a49136ad5bf1adc9e9a0232349bcdce57">OSCCTRL</a>->DFLLCTRLA.bit.RUNSTDBY = <a class="code" href="conf__core_8h.html#ab6b320dcf67ec88f534adcbf77e2ce7b">CONF_CORE_CLK_DFLL_RUNSTDBY</a>;</div>
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<div class="line"><a name="l00401"></a><span class="lineno"> 401</span>  <a class="code" href="same54n19a_8h.html#a49136ad5bf1adc9e9a0232349bcdce57">OSCCTRL</a>->DFLLCTRLA.bit.ENABLE = <a class="code" href="conf__core_8h.html#a03160c4c7871685bbde0e96f02825842">CONF_CORE_CLK_DFLL_ENABLE</a>;</div>
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<div class="line"><a name="l00402"></a><span class="lineno"> 402</span>  CRITICAL_SECTION_LEAVE();</div>
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<div class="line"><a name="l00403"></a><span class="lineno"> 403</span>  <span class="keywordflow">while</span>(<a class="code" href="same54n19a_8h.html#a49136ad5bf1adc9e9a0232349bcdce57">OSCCTRL</a>->DFLLSYNC.bit.ENABLE);</div>
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<div class="line"><a name="l00404"></a><span class="lineno"> 404</span> <span class="preprocessor">#if CONF_CORE_CLK_DFLL_OVERWRITE_CAL == 1</span></div>
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<div class="line"><a name="l00405"></a><span class="lineno"> 405</span>  CRITICAL_SECTION_ENTER();</div>
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<div class="line"><a name="l00406"></a><span class="lineno"> 406</span>  <span class="comment">// set calib for dfll48m</span></div>
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<div class="line"><a name="l00407"></a><span class="lineno"> 407</span>  <a class="code" href="same54n19a_8h.html#a49136ad5bf1adc9e9a0232349bcdce57">OSCCTRL</a>->DFLLVAL.bit.COARSE = CONF_CORE_CLK_DFLL_COARSE_VAL;</div>
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<div class="line"><a name="l00408"></a><span class="lineno"> 408</span>  <a class="code" href="same54n19a_8h.html#a49136ad5bf1adc9e9a0232349bcdce57">OSCCTRL</a>->DFLLVAL.bit.FINE = CONF_CORE_CLK_DFLL_FINE_VAL;</div>
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<div class="line"><a name="l00409"></a><span class="lineno"> 409</span>  <a class="code" href="same54n19a_8h.html#a49136ad5bf1adc9e9a0232349bcdce57">OSCCTRL</a>->DFLLVAL.bit.DIFF = CONF_CORE_CLK_DFLL_DIFF_VAL;</div>
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<div class="line"><a name="l00410"></a><span class="lineno"> 410</span>  CRITICAL_SECTION_LEAVE();</div>
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<div class="line"><a name="l00411"></a><span class="lineno"> 411</span> <span class="preprocessor">#endif</span></div>
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<div class="line"><a name="l00412"></a><span class="lineno"> 412</span>  </div>
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<div class="line"><a name="l00413"></a><span class="lineno"> 413</span>  CRITICAL_SECTION_ENTER();</div>
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<div class="line"><a name="l00414"></a><span class="lineno"> 414</span>  <span class="comment">// write dfll val</span></div>
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<div class="line"><a name="l00415"></a><span class="lineno"> 415</span>  <span class="comment">// rewriting this for some reason?</span></div>
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<div class="line"><a name="l00416"></a><span class="lineno"> 416</span>  <a class="code" href="same54n19a_8h.html#a49136ad5bf1adc9e9a0232349bcdce57">OSCCTRL</a>->DFLLVAL.reg = <a class="code" href="same54n19a_8h.html#a49136ad5bf1adc9e9a0232349bcdce57">OSCCTRL</a>->DFLLVAL.reg;</div>
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<div class="line"><a name="l00417"></a><span class="lineno"> 417</span>  CRITICAL_SECTION_LEAVE();</div>
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<div class="line"><a name="l00418"></a><span class="lineno"> 418</span>  <span class="comment">// let dfll val sync</span></div>
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<div class="line"><a name="l00419"></a><span class="lineno"> 419</span>  <span class="keywordflow">while</span>(<a class="code" href="same54n19a_8h.html#a49136ad5bf1adc9e9a0232349bcdce57">OSCCTRL</a>->DFLLSYNC.bit.DFLLVAL);</div>
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<div class="line"><a name="l00420"></a><span class="lineno"> 420</span>  </div>
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<div class="line"><a name="l00421"></a><span class="lineno"> 421</span>  CRITICAL_SECTION_ENTER();</div>
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<div class="line"><a name="l00422"></a><span class="lineno"> 422</span>  <span class="comment">// write dfll ctrlb</span></div>
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<div class="line"><a name="l00423"></a><span class="lineno"> 423</span>  <a class="code" href="same54n19a_8h.html#a49136ad5bf1adc9e9a0232349bcdce57">OSCCTRL</a>->DFLLCTRLB.bit.WAITLOCK = <a class="code" href="conf__core_8h.html#a1f088d6654bb907ff388ced455b2dbb2">CONF_CORE_CLK_DFLL_WAITLOCK</a>;</div>
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<div class="line"><a name="l00424"></a><span class="lineno"> 424</span>  <a class="code" href="same54n19a_8h.html#a49136ad5bf1adc9e9a0232349bcdce57">OSCCTRL</a>->DFLLCTRLB.bit.BPLCKC = CONF_CORE_CLK_DFLL_BPLKC;</div>
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<div class="line"><a name="l00425"></a><span class="lineno"> 425</span>  <a class="code" href="same54n19a_8h.html#a49136ad5bf1adc9e9a0232349bcdce57">OSCCTRL</a>->DFLLCTRLB.bit.QLDIS = CONF_CORE_CLK_DFLL_QLDIS;</div>
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<div class="line"><a name="l00426"></a><span class="lineno"> 426</span>  <a class="code" href="same54n19a_8h.html#a49136ad5bf1adc9e9a0232349bcdce57">OSCCTRL</a>->DFLLCTRLB.bit.CCDIS = CONF_CORE_CLK_DFLL_CCDIS;</div>
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<div class="line"><a name="l00427"></a><span class="lineno"> 427</span>  <a class="code" href="same54n19a_8h.html#a49136ad5bf1adc9e9a0232349bcdce57">OSCCTRL</a>->DFLLCTRLB.bit.USBCRM = CONF_CORE_CLK_DFLL_USBCRM;</div>
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<div class="line"><a name="l00428"></a><span class="lineno"> 428</span>  <a class="code" href="same54n19a_8h.html#a49136ad5bf1adc9e9a0232349bcdce57">OSCCTRL</a>->DFLLCTRLB.bit.LLAW = CONF_CORE_CLK_DFLL_LLAW;</div>
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<div class="line"><a name="l00429"></a><span class="lineno"> 429</span>  <a class="code" href="same54n19a_8h.html#a49136ad5bf1adc9e9a0232349bcdce57">OSCCTRL</a>->DFLLCTRLB.bit.STABLE = CONF_CORE_CLK_DFLL_STABLE_FCALIB;</div>
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<div class="line"><a name="l00430"></a><span class="lineno"> 430</span>  <a class="code" href="same54n19a_8h.html#a49136ad5bf1adc9e9a0232349bcdce57">OSCCTRL</a>->DFLLCTRLB.bit.MODE = CONF_CORE_CLK_DFLL_MODE;</div>
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<div class="line"><a name="l00431"></a><span class="lineno"> 431</span>  CRITICAL_SECTION_LEAVE();</div>
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<div class="line"><a name="l00432"></a><span class="lineno"> 432</span>  <span class="keywordflow">while</span>(<a class="code" href="same54n19a_8h.html#a49136ad5bf1adc9e9a0232349bcdce57">OSCCTRL</a>->DFLLSYNC.bit.DFLLCTRLB);</div>
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<div class="line"><a name="l00433"></a><span class="lineno"> 433</span>  </div>
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<div class="line"><a name="l00434"></a><span class="lineno"> 434</span>  <span class="keywordflow">if</span> (<a class="code" href="same54n19a_8h.html#a49136ad5bf1adc9e9a0232349bcdce57">OSCCTRL</a>->DFLLCTRLB.bit.MODE)</div>
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<div class="line"><a name="l00435"></a><span class="lineno"> 435</span>  {</div>
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<div class="line"><a name="l00436"></a><span class="lineno"> 436</span>  <span class="keyword">volatile</span> uint32_t status_mask = OSCCTRL_STATUS_DFLLRDY | OSCCTRL_STATUS_DFLLLCKC;</div>
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<div class="line"><a name="l00437"></a><span class="lineno"> 437</span>  <span class="keywordflow">while</span>((<a class="code" href="same54n19a_8h.html#a49136ad5bf1adc9e9a0232349bcdce57">OSCCTRL</a>->STATUS.reg & status_mask) != status_mask);</div>
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<div class="line"><a name="l00438"></a><span class="lineno"> 438</span>  }</div>
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<div class="line"><a name="l00439"></a><span class="lineno"> 439</span>  <span class="keywordflow">else</span></div>
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<div class="line"><a name="l00440"></a><span class="lineno"> 440</span>  {</div>
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<div class="line"><a name="l00441"></a><span class="lineno"> 441</span>  <span class="keywordflow">while</span>(!<a class="code" href="same54n19a_8h.html#a49136ad5bf1adc9e9a0232349bcdce57">OSCCTRL</a>->STATUS.bit.DFLLRDY);</div>
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<div class="line"><a name="l00442"></a><span class="lineno"> 442</span>  }</div>
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<div class="line"><a name="l00443"></a><span class="lineno"> 443</span>  </div>
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<div class="line"><a name="l00444"></a><span class="lineno"> 444</span> <span class="preprocessor">#if CONF_CORE_CLK_DFLL_ONDEMAND == 1</span></div>
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<div class="line"><a name="l00445"></a><span class="lineno"> 445</span>  CRITICAL_SECTION_ENTER();</div>
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<div class="line"><a name="l00446"></a><span class="lineno"> 446</span>  <a class="code" href="same54n19a_8h.html#a49136ad5bf1adc9e9a0232349bcdce57">OSCCTRL</a>->DFLLCTRLA.bit.ONDEMAND = <a class="code" href="conf__core_8h.html#a55515b150245a993779a0d5f417cc828">CONF_CORE_CLK_DFLL_ONDEMAND</a>;</div>
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<div class="line"><a name="l00447"></a><span class="lineno"> 447</span>  CRITICAL_SECTION_LEAVE();</div>
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<div class="line"><a name="l00448"></a><span class="lineno"> 448</span> <span class="preprocessor">#endif</span></div>
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<div class="line"><a name="l00449"></a><span class="lineno"> 449</span>  </div>
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<div class="line"><a name="l00450"></a><span class="lineno"> 450</span>  <span class="keywordflow">while</span>(<a class="code" href="same54n19a_8h.html#a23f9186cfd6ee5e60c8485315183271f">GCLK</a>->SYNCBUSY.reg);</div>
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<div class="line"><a name="l00451"></a><span class="lineno"> 451</span>  CRITICAL_SECTION_ENTER();</div>
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<div class="line"><a name="l00452"></a><span class="lineno"> 452</span>  <span class="comment">// reset gclk 0</span></div>
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<div class="line"><a name="l00453"></a><span class="lineno"> 453</span>  <a class="code" href="same54n19a_8h.html#a23f9186cfd6ee5e60c8485315183271f">GCLK</a>->GENCTRL[0].bit.SRC = CONF_CORE_GCLK_0_CLOCK_SOURCE;</div>
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<div class="line"><a name="l00454"></a><span class="lineno"> 454</span>  CRITICAL_SECTION_LEAVE();</div>
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<div class="line"><a name="l00455"></a><span class="lineno"> 455</span> <span class="preprocessor">#endif</span></div>
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<div class="line"><a name="l00456"></a><span class="lineno"> 456</span> }</div>
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</div><!-- fragment --></div><!-- contents -->
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<div class="ttc" id="aconf__core_8h_html_a1f088d6654bb907ff388ced455b2dbb2"><div class="ttname"><a href="conf__core_8h.html#a1f088d6654bb907ff388ced455b2dbb2">CONF_CORE_CLK_DFLL_WAITLOCK</a></div><div class="ttdeci">#define CONF_CORE_CLK_DFLL_WAITLOCK</div><div class="ttdoc">This bit controls the DFLL output clock, depending on the lock status:</div><div class="ttdef"><b>Definition:</b> <a href="conf__core_8h_source.html#l00414">conf_core.h:414</a></div></div>
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<div class="ttc" id="aconf__core_8h_html_aaf561ace0fee1e373536a251ce8a9726"><div class="ttname"><a href="conf__core_8h.html#aaf561ace0fee1e373536a251ce8a9726">CONF_CORE_CLK_XOSC1_ONDEMAND</a></div><div class="ttdeci">#define CONF_CORE_CLK_XOSC1_ONDEMAND</div><div class="ttdoc">The On Demand operation mode allows the oscillator XOSC1 to be enabled or disabled,...</div><div class="ttdef"><b>Definition:</b> <a href="conf__core_8h_source.html#l00207">conf_core.h:207</a></div></div>
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<div class="ttc" id="aconf__core_8h_html_a17cd20bb954bc137251cf7fb63889151"><div class="ttname"><a href="conf__core_8h.html#a17cd20bb954bc137251cf7fb63889151">CONF_CORE_CLK_XOSC0_CFDEN</a></div><div class="ttdeci">#define CONF_CORE_CLK_XOSC0_CFDEN</div><div class="ttdoc">This bit controls the XOSC0 clock failure detector:</div><div class="ttdef"><b>Definition:</b> <a href="conf__core_8h_source.html#l00128">conf_core.h:128</a></div></div>
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<div class="ttc" id="aconf__core_8h_html_a9de3ab7eb7e3c001d6aa7040f6311f10"><div class="ttname"><a href="conf__core_8h.html#a9de3ab7eb7e3c001d6aa7040f6311f10">CONF_CORE_CLK_DPLL1_FILTER</a></div><div class="ttdeci">#define CONF_CORE_CLK_DPLL1_FILTER</div><div class="ttdef"><b>Definition:</b> <a href="conf__core_8h_source.html#l00535">conf_core.h:535</a></div></div>
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<div class="ttc" id="aconf__core_8h_html_a590b1e68a3f666bdea576a32f4e74ba0"><div class="ttname"><a href="conf__core_8h.html#a590b1e68a3f666bdea576a32f4e74ba0">CONF_CORE_CLK_XOSC1_SWBEN</a></div><div class="ttdeci">#define CONF_CORE_CLK_XOSC1_SWBEN</div><div class="ttdoc">This bit controls the XOSC1 output clock switch back to the external clock or crystal oscillator in c...</div><div class="ttdef"><b>Definition:</b> <a href="conf__core_8h_source.html#l00241">conf_core.h:241</a></div></div>
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<div class="ttc" id="aconf__core_8h_html_a2683d3721ab44a85e60cfff0d0cbf96e"><div class="ttname"><a href="conf__core_8h.html#a2683d3721ab44a85e60cfff0d0cbf96e">CONF_CORE_CLK_XOSC0_ENALC</a></div><div class="ttdeci">#define CONF_CORE_CLK_XOSC0_ENALC</div><div class="ttdoc">This bit controls the XOSC0 automatic loop control:</div><div class="ttdef"><b>Definition:</b> <a href="conf__core_8h_source.html#l00120">conf_core.h:120</a></div></div>
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<div class="ttc" id="aconf__core_8h_html_ae9fbb8d05dc5808f510eae4e8a629826"><div class="ttname"><a href="conf__core_8h.html#ae9fbb8d05dc5808f510eae4e8a629826">CONF_CORE_CLK_XOSC32K_EN32K</a></div><div class="ttdeci">#define CONF_CORE_CLK_XOSC32K_EN32K</div><div class="ttdef"><b>Definition:</b> <a href="conf__core_8h_source.html#l00336">conf_core.h:336</a></div></div>
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<div class="ttc" id="aconf__core_8h_html_a5cd9abca6f486eaebb6ddd236960b01a"><div class="ttname"><a href="conf__core_8h.html#a5cd9abca6f486eaebb6ddd236960b01a">CONF_CORE_CLK_DPLL0_FILTER</a></div><div class="ttdeci">#define CONF_CORE_CLK_DPLL0_FILTER</div><div class="ttdef"><b>Definition:</b> <a href="conf__core_8h_source.html#l00490">conf_core.h:490</a></div></div>
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<div class="ttc" id="aconf__core_8h_html_a031a77340c697036538d218724837de1"><div class="ttname"><a href="conf__core_8h.html#a031a77340c697036538d218724837de1">CONF_CORE_CLK_XOSC32K_CGM</a></div><div class="ttdeci">#define CONF_CORE_CLK_XOSC32K_CGM</div><div class="ttdoc">These bits control the gain of the external crstal oscillator.</div><div class="ttdef"><b>Definition:</b> <a href="conf__core_8h_source.html#l00293">conf_core.h:293</a></div></div>
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<div class="ttc" id="aconf__core_8h_html_aa9643e96439d0d47e0684a4b11c1f529"><div class="ttname"><a href="conf__core_8h.html#aa9643e96439d0d47e0684a4b11c1f529">CONF_CORE_MCLK_CPUDIV</a></div><div class="ttdeci">#define CONF_CORE_MCLK_CPUDIV</div><div class="ttdoc">Define the master clock divisor.</div><div class="ttdef"><b>Definition:</b> <a href="conf__core_8h_source.html#l00038">conf_core.h:38</a></div></div>
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<div class="ttc" id="aconf__core_8h_html_ac2ca0e9037347eb69d53a0011f989910"><div class="ttname"><a href="conf__core_8h.html#ac2ca0e9037347eb69d53a0011f989910">CONF_CORE_CLK_XOSC0_XTALEN</a></div><div class="ttdeci">#define CONF_CORE_CLK_XOSC0_XTALEN</div><div class="ttdoc">This bit controls the connections between the I/O pads and the external clock or crystal oscillator X...</div><div class="ttdef"><b>Definition:</b> <a href="conf__core_8h_source.html#l00084">conf_core.h:84</a></div></div>
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<div class="ttc" id="aconf__core_8h_html_a8bec34fdc01ac38ec0c2d13112f28aa0"><div class="ttname"><a href="conf__core_8h.html#a8bec34fdc01ac38ec0c2d13112f28aa0">CONF_CORE_CLK_XOSC1_RUNSTDBY</a></div><div class="ttdeci">#define CONF_CORE_CLK_XOSC1_RUNSTDBY</div><div class="ttdoc">This bit controls how the XOSC1 behaves during standby sleep mode:</div><div class="ttdef"><b>Definition:</b> <a href="conf__core_8h_source.html#l00198">conf_core.h:198</a></div></div>
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<div class="ttc" id="aconf__core_8h_html_a924214b0f469bde71ff28fe5544466db"><div class="ttname"><a href="conf__core_8h.html#a924214b0f469bde71ff28fe5544466db">CONF_CORE_CLK_XOSC1_CFDEN</a></div><div class="ttdeci">#define CONF_CORE_CLK_XOSC1_CFDEN</div><div class="ttdoc">This bit controls the XOSC1 clock failure detector:</div><div class="ttdef"><b>Definition:</b> <a href="conf__core_8h_source.html#l00232">conf_core.h:232</a></div></div>
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<div class="ttc" id="aconf__core_8h_html_a668d68edf9a7ac05be5b9cda247225ad"><div class="ttname"><a href="conf__core_8h.html#a668d68edf9a7ac05be5b9cda247225ad">CONF_CORE_CLK_XOSC32K_CFDEN</a></div><div class="ttdeci">#define CONF_CORE_CLK_XOSC32K_CFDEN</div><div class="ttdoc">This bit selects the Clock Failulre Detector state.</div><div class="ttdef"><b>Definition:</b> <a href="conf__core_8h_source.html#l00360">conf_core.h:360</a></div></div>
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<div class="ttc" id="asame54n19a_8h_html_a625e6fdb4c2120fc163e1b04178af3dd"><div class="ttname"><a href="same54n19a_8h.html#a625e6fdb4c2120fc163e1b04178af3dd">MCLK</a></div><div class="ttdeci">#define MCLK</div><div class="ttdoc">(MCLK) APB Base Address</div><div class="ttdef"><b>Definition:</b> <a href="same54n19a_8h_source.html#l00914">same54n19a.h:914</a></div></div>
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<div class="ttc" id="aconf__core_8h_html_aa54465cc56631333a22ae84ab66d5f3a"><div class="ttname"><a href="conf__core_8h.html#aa54465cc56631333a22ae84ab66d5f3a">CONF_CORE_CLK_XOSC1_ENABLE</a></div><div class="ttdeci">#define CONF_CORE_CLK_XOSC1_ENABLE</div><div class="ttdoc">Enables or Disables the XOSC1 Clock.</div><div class="ttdef"><b>Definition:</b> <a href="conf__core_8h_source.html#l00180">conf_core.h:180</a></div></div>
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<div class="ttc" id="aconf__core_8h_html_a3a42de5c6251540e7b8c000974acfc62"><div class="ttname"><a href="conf__core_8h.html#a3a42de5c6251540e7b8c000974acfc62">CONF_CORE_CLK_XOSC1_ENALC</a></div><div class="ttdeci">#define CONF_CORE_CLK_XOSC1_ENALC</div><div class="ttdoc">This bit controls the XOSC1 automatic loop control:</div><div class="ttdef"><b>Definition:</b> <a href="conf__core_8h_source.html#l00224">conf_core.h:224</a></div></div>
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<div class="ttc" id="aconf__core_8h_html_abe235b3b13f253acb855d15c8f33c95a"><div class="ttname"><a href="conf__core_8h.html#abe235b3b13f253acb855d15c8f33c95a">CONF_CORE_CLK_XOSC0_SWBEN</a></div><div class="ttdeci">#define CONF_CORE_CLK_XOSC0_SWBEN</div><div class="ttdoc">This bit controls the XOSC0 output clock switch back to the external clock or crystal oscillator in c...</div><div class="ttdef"><b>Definition:</b> <a href="conf__core_8h_source.html#l00137">conf_core.h:137</a></div></div>
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<div class="ttc" id="aconf__core_8h_html_a61559adc856ce1dcfa046e749af63bc3"><div class="ttname"><a href="conf__core_8h.html#a61559adc856ce1dcfa046e749af63bc3">CONF_CORE_CLK_XOSC0_ENABLE</a></div><div class="ttdeci">#define CONF_CORE_CLK_XOSC0_ENABLE</div><div class="ttdoc">Enables or Disables the XOSC0 Clock.</div><div class="ttdef"><b>Definition:</b> <a href="conf__core_8h_source.html#l00076">conf_core.h:76</a></div></div>
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<div class="ttc" id="aconf__core_8h_html_ae3f8741e2be4b37a46dfb49af2c2a09d"><div class="ttname"><a href="conf__core_8h.html#ae3f8741e2be4b37a46dfb49af2c2a09d">CONF_CORE_CLK_XOSC1_XTALEN</a></div><div class="ttdeci">#define CONF_CORE_CLK_XOSC1_XTALEN</div><div class="ttdoc">This bit controls the connections between the I/O pads and the external clock or crystal oscillator X...</div><div class="ttdef"><b>Definition:</b> <a href="conf__core_8h_source.html#l00188">conf_core.h:188</a></div></div>
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<div class="ttc" id="aconf__core_8h_html_a6a65a6f4bf7e21dc2003b61a7045e24a"><div class="ttname"><a href="conf__core_8h.html#a6a65a6f4bf7e21dc2003b61a7045e24a">CONF_CORE_CLK_XOSC32K_XTALEN</a></div><div class="ttdeci">#define CONF_CORE_CLK_XOSC32K_XTALEN</div><div class="ttdoc">This bit controls the connections between the I/O pads and the external clock or crystal oscillator.</div><div class="ttdef"><b>Definition:</b> <a href="conf__core_8h_source.html#l00344">conf_core.h:344</a></div></div>
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<div class="ttc" id="asame54n19a_8h_html_af1a4b8f1d1a2265b93f22621f7903f88"><div class="ttname"><a href="same54n19a_8h.html#af1a4b8f1d1a2265b93f22621f7903f88">OSC32KCTRL</a></div><div class="ttdeci">#define OSC32KCTRL</div><div class="ttdoc">(OSC32KCTRL) APB Base Address</div><div class="ttdef"><b>Definition:</b> <a href="same54n19a_8h_source.html#l00929">same54n19a.h:929</a></div></div>
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<div class="ttc" id="aconf__core_8h_html_a314b78ee48f1ecf6c40f4bad7ef63d9d"><div class="ttname"><a href="conf__core_8h.html#a314b78ee48f1ecf6c40f4bad7ef63d9d">CONF_CORE_CLK_XOSC32K_STARTUP_TIME</a></div><div class="ttdeci">#define CONF_CORE_CLK_XOSC32K_STARTUP_TIME</div><div class="ttdoc">These bits select the startup time for the oscillator.</div><div class="ttdef"><b>Definition:</b> <a href="conf__core_8h_source.html#l00306">conf_core.h:306</a></div></div>
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<div class="ttc" id="aconf__core_8h_html_a55515b150245a993779a0d5f417cc828"><div class="ttname"><a href="conf__core_8h.html#a55515b150245a993779a0d5f417cc828">CONF_CORE_CLK_DFLL_ONDEMAND</a></div><div class="ttdeci">#define CONF_CORE_CLK_DFLL_ONDEMAND</div><div class="ttdoc">Enables or Disables on-demand operation.</div><div class="ttdef"><b>Definition:</b> <a href="conf__core_8h_source.html#l00398">conf_core.h:398</a></div></div>
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<div class="ttc" id="aconf__core_8h_html_adc7a2f161e9e8e54388b1f290066247e"><div class="ttname"><a href="conf__core_8h.html#adc7a2f161e9e8e54388b1f290066247e">CONF_CORE_CLK_XOSC32K_RUNSTDBY</a></div><div class="ttdeci">#define CONF_CORE_CLK_XOSC32K_RUNSTDBY</div><div class="ttdoc">This bit controls how XOSC32K behaves during standby sleep mode.</div><div class="ttdef"><b>Definition:</b> <a href="conf__core_8h_source.html#l00322">conf_core.h:322</a></div></div>
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<div class="ttc" id="aconf__core_8h_html_affc8201cf2340d2236ba9ca44a1e657c"><div class="ttname"><a href="conf__core_8h.html#affc8201cf2340d2236ba9ca44a1e657c">CONF_CORE_CLK_XOSC0_STARTUP_TIME</a></div><div class="ttdeci">#define CONF_CORE_CLK_XOSC0_STARTUP_TIME</div><div class="ttdoc">These bits select start-up time for XOSC0 according to the table below:</div><div class="ttdef"><b>Definition:</b> <a href="conf__core_8h_source.html#l00159">conf_core.h:159</a></div></div>
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<div class="ttc" id="aconf__core_8h_html_a8d70a30b50febec035af6b982daac395"><div class="ttname"><a href="conf__core_8h.html#a8d70a30b50febec035af6b982daac395">CONF_CORE_CLK_XOSC32K_ONDEMAND</a></div><div class="ttdeci">#define CONF_CORE_CLK_XOSC32K_ONDEMAND</div><div class="ttdoc">This bit controls how XOSC32K behaves when a peripheral clock request is detected.</div><div class="ttdef"><b>Definition:</b> <a href="conf__core_8h_source.html#l00314">conf_core.h:314</a></div></div>
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<div class="ttc" id="asame54n19a_8h_html_a49136ad5bf1adc9e9a0232349bcdce57"><div class="ttname"><a href="same54n19a_8h.html#a49136ad5bf1adc9e9a0232349bcdce57">OSCCTRL</a></div><div class="ttdeci">#define OSCCTRL</div><div class="ttdoc">(OSCCTRL) APB Base Address</div><div class="ttdef"><b>Definition:</b> <a href="same54n19a_8h_source.html#l00925">same54n19a.h:925</a></div></div>
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<div class="ttc" id="aconf__core_8h_html_a42b0270d2f3c0f51c4b3d2b8ac397fda"><div class="ttname"><a href="conf__core_8h.html#a42b0270d2f3c0f51c4b3d2b8ac397fda">CONF_CORE_CLK_XOSC32K_WRTLOCK</a></div><div class="ttdeci">#define CONF_CORE_CLK_XOSC32K_WRTLOCK</div><div class="ttdoc">This bit locks the XOSC32K register for future writes, effectively freezing the XOSC32K configuration...</div><div class="ttdef"><b>Definition:</b> <a href="conf__core_8h_source.html#l00376">conf_core.h:376</a></div></div>
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<div class="ttc" id="aconf__core_8h_html_a79567f94a0f3ad2d628bcf5e1cff62d1"><div class="ttname"><a href="conf__core_8h.html#a79567f94a0f3ad2d628bcf5e1cff62d1">CONF_CORE_CLK_XOSC32K_CFDPRESC</a></div><div class="ttdeci">#define CONF_CORE_CLK_XOSC32K_CFDPRESC</div><div class="ttdoc">This bit selects the prescaler for the CLock Failure Detector:</div><div class="ttdef"><b>Definition:</b> <a href="conf__core_8h_source.html#l00352">conf_core.h:352</a></div></div>
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<div class="ttc" id="aconf__core_8h_html_afac0686157854cc021424410ded071f1"><div class="ttname"><a href="conf__core_8h.html#afac0686157854cc021424410ded071f1">CONF_CORE_CLK_XOSC0_RUNSTDBY</a></div><div class="ttdeci">#define CONF_CORE_CLK_XOSC0_RUNSTDBY</div><div class="ttdoc">This bit controls how the XOSC0 behaves during standby sleep mode:</div><div class="ttdef"><b>Definition:</b> <a href="conf__core_8h_source.html#l00094">conf_core.h:94</a></div></div>
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<div class="ttc" id="aconf__core_8h_html_ae8d2fdac3b52964174863149986db625"><div class="ttname"><a href="conf__core_8h.html#ae8d2fdac3b52964174863149986db625">CONF_CORE_CLK_XOSC1_STARTUP_TIME</a></div><div class="ttdeci">#define CONF_CORE_CLK_XOSC1_STARTUP_TIME</div><div class="ttdoc">These bits select start-up time for XOSC1 according to the table below:</div><div class="ttdef"><b>Definition:</b> <a href="conf__core_8h_source.html#l00263">conf_core.h:263</a></div></div>
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<div class="ttc" id="aconf__core_8h_html_a033f3571fb50a6ed02278d65ea84b45e"><div class="ttname"><a href="conf__core_8h.html#a033f3571fb50a6ed02278d65ea84b45e">CONF_CORE_CLK_XOSC32K_EN1K</a></div><div class="ttdeci">#define CONF_CORE_CLK_XOSC32K_EN1K</div><div class="ttdef"><b>Definition:</b> <a href="conf__core_8h_source.html#l00329">conf_core.h:329</a></div></div>
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<div class="ttc" id="aconf__core_8h_html_ab6b320dcf67ec88f534adcbf77e2ce7b"><div class="ttname"><a href="conf__core_8h.html#ab6b320dcf67ec88f534adcbf77e2ce7b">CONF_CORE_CLK_DFLL_RUNSTDBY</a></div><div class="ttdeci">#define CONF_CORE_CLK_DFLL_RUNSTDBY</div><div class="ttdoc">Enables or Disables run-in-standby operation.</div><div class="ttdef"><b>Definition:</b> <a href="conf__core_8h_source.html#l00406">conf_core.h:406</a></div></div>
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<div class="ttc" id="aconf__core_8h_html"><div class="ttname"><a href="conf__core_8h.html">conf_core.h</a></div></div>
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<div class="ttc" id="aconf__core_8h_html_a5ffaa1551b7ffb8a342b2cc5fbc5950c"><div class="ttname"><a href="conf__core_8h.html#a5ffaa1551b7ffb8a342b2cc5fbc5950c">CONF_CORE_CLK_XOSC0_ONDEMAND</a></div><div class="ttdeci">#define CONF_CORE_CLK_XOSC0_ONDEMAND</div><div class="ttdoc">The On Demand operation mode allows the oscillator XOSC0 to be enabled or disabled,...</div><div class="ttdef"><b>Definition:</b> <a href="conf__core_8h_source.html#l00103">conf_core.h:103</a></div></div>
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<div class="ttc" id="aconf__core_8h_html_ac6e671eee4ca4aeb9fcbb87d52b457b5"><div class="ttname"><a href="conf__core_8h.html#ac6e671eee4ca4aeb9fcbb87d52b457b5">CONF_CORE_CLK_XOSC32K_SWBACK</a></div><div class="ttdeci">#define CONF_CORE_CLK_XOSC32K_SWBACK</div><div class="ttdoc">This bit controls the XOSC32K output switch back to the external clock or crystal oscillator in case ...</div><div class="ttdef"><b>Definition:</b> <a href="conf__core_8h_source.html#l00368">conf_core.h:368</a></div></div>
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<div class="ttc" id="aconf__core_8h_html_aeea7b0d3663bb6d5ccc3218017f9a05b"><div class="ttname"><a href="conf__core_8h.html#aeea7b0d3663bb6d5ccc3218017f9a05b">CONF_CORE_CLK_XOSC0_LOWBUFGAIN</a></div><div class="ttdeci">#define CONF_CORE_CLK_XOSC0_LOWBUFGAIN</div><div class="ttdoc">The default value of LOWBUFGAIN=0 should be used to allow operating with a low amplitude oscillator....</div><div class="ttdef"><b>Definition:</b> <a href="conf__core_8h_source.html#l00112">conf_core.h:112</a></div></div>
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<div class="ttc" id="aconf__core_8h_html_a03160c4c7871685bbde0e96f02825842"><div class="ttname"><a href="conf__core_8h.html#a03160c4c7871685bbde0e96f02825842">CONF_CORE_CLK_DFLL_ENABLE</a></div><div class="ttdeci">#define CONF_CORE_CLK_DFLL_ENABLE</div><div class="ttdoc">Enables or Disables the DFLL48M Clock.</div><div class="ttdef"><b>Definition:</b> <a href="conf__core_8h_source.html#l00390">conf_core.h:390</a></div></div>
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<div class="ttc" id="asame54n19a_8h_html_a23f9186cfd6ee5e60c8485315183271f"><div class="ttname"><a href="same54n19a_8h.html#a23f9186cfd6ee5e60c8485315183271f">GCLK</a></div><div class="ttdeci">#define GCLK</div><div class="ttdoc">(GCLK) APB Base Address</div><div class="ttdef"><b>Definition:</b> <a href="same54n19a_8h_source.html#l00894">same54n19a.h:894</a></div></div>
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<div class="ttc" id="aconf__core_8h_html_a0d8e56832f3d1f24b98173e3a3aa0046"><div class="ttname"><a href="conf__core_8h.html#a0d8e56832f3d1f24b98173e3a3aa0046">CONF_CORE_CLK_DFLL_GCLK_SRC</a></div><div class="ttdeci">#define CONF_CORE_CLK_DFLL_GCLK_SRC</div><div class="ttdoc">GCLK Source used to generate DFLL48M.</div><div class="ttdef"><b>Definition:</b> <a href="conf__core_8h_source.html#l00444">conf_core.h:444</a></div></div>
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<div class="ttc" id="aconf__core_8h_html_a985ebd23986d9411d3602040e33bb405"><div class="ttname"><a href="conf__core_8h.html#a985ebd23986d9411d3602040e33bb405">CONF_CORE_CLK_XOSC1_LOWBUFGAIN</a></div><div class="ttdeci">#define CONF_CORE_CLK_XOSC1_LOWBUFGAIN</div><div class="ttdoc">The default value of LOWBUFGAIN=0 should be used to allow operating with a low amplitude oscillator....</div><div class="ttdef"><b>Definition:</b> <a href="conf__core_8h_source.html#l00216">conf_core.h:216</a></div></div>
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