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651 lines
25 KiB
C
651 lines
25 KiB
C
/**
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* @file conf_core.h
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* @author Penguin
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*
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* @section Description
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*
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* This is the master config for the core module for this mcu. This file is *required*
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* for the core module to function.
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*/
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#ifndef _CONF_CLOCKS_H_
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#define _CONF_CLOCKS_H_
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#include "clocks.h"
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/** @name Core-Master-Clock-Configuration
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* Configuration options for the master clock.
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* @{
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*/
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/**
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* @brief Define the number of wait states for the master clock.
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* <br>Can be [0-15].
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* <br>See <a href="https://ww1.microchip.com/downloads/en/DeviceDoc/SAM_D5xE5x_Family_Data_Sheet_DS60001507F.pdf#page=605">Datasheet Reference</a>
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*/
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#define CONF_CORE_MCLK_NVM_WAIT_STATE 0x5
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/**
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* @brief Define the master clock divisor.
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* - 0x1 => Clock Divide by 1
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* - 0x2 => Clock Divide by 2
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* - 0x4 => Clock Divide by 4
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* - 0x8 => Clock Divide by 8
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* - 0x10 => Clock Divide by 16
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* - 0x20 => Clock Divide by 32
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* - 0x40 => Clock Divide by 64
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* - 0x80 => Clock Divide by 128
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* <br>See <a href="https://ww1.microchip.com/downloads/en/DeviceDoc/SAM_D5xE5x_Family_Data_Sheet_DS60001507F.pdf#page=170">Datasheet Reference</a>
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*/
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#define CONF_CORE_MCLK_CPUDIV 0x1
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/** @} */
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/**
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* Define whether the DMAC is enabled or not.
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* - 0 => Disabled
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* - 1 => Enabled
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* <br>See <a href="https://ww1.microchip.com/downloads/en/DeviceDoc/SAM_D5xE5x_Family_Data_Sheet_DS60001507F.pdf#page=172">Datasheet Reference</a>
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*/
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#define CONF_CORE_DMA_ENABLE (0)
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/**
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* Define whether the CMCC (Cortex-M Cache Controller) is enabled or not.
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* - 0 => Disabled
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* - 1 => Enabled
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*/
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#define CONF_CORE_CMCC_ENABLE (0)
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/** Currently Unused */
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#define CONF_CORE_PORT_EVCTRL_0_ENABLE (0)
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/** Currently Unused */
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#define CONF_CORE_PORT_EVCTRL_1_ENABLE (0)
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/** Currently Unused */
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#define CONF_CORE_PORT_EVCTRL_2_ENABLE (0)
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/** @name Core-XOSC0-Configuration
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* Configuration options for XOSC0.
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* <br>See <a href="https://ww1.microchip.com/downloads/en/DeviceDoc/SAM_D5xE5x_Family_Data_Sheet_DS60001507F.pdf#page=693">Datasheet Reference</a>
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* @{
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*/
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/**
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* XOSC0 Enable
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* @brief Enables or Disables the XOSC0 Clock
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* - 0 => Disables XOSC0
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* - 1 => Enables XOSC0
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* <br>See <a href="https://ww1.microchip.com/downloads/en/DeviceDoc/SAM_D5xE5x_Family_Data_Sheet_DS60001507F.pdf#page=723">Datasheet Reference</a>
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*/
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#define CONF_CORE_CLK_XOSC0_ENABLE (1)
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/**
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* XOSC0 XTALEN
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* @brief This bit controls the connections between the I/O pads and the external clock or crystal oscillator XOSC0:
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* - 0 => External clock connected on XIN. XOUT can be used as general purpose I/O.
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* - 1 => Crystal connected to XIN/XOUT.
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* <br>See <a href="https://ww1.microchip.com/downloads/en/DeviceDoc/SAM_D5xE5x_Family_Data_Sheet_DS60001507F.pdf#page=723">Datasheet Reference</a>
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*/
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#define CONF_CORE_CLK_XOSC0_XTALEN (1)
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/**
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* XOSC0 Run in Standby
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* @brief This bit controls how the XOSC0 behaves during standby sleep mode:
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* - 0 => XOSC0 is not running in standby sleep mode if no peripheral requests the clock.
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* - 1 => XOSC0 is running in standby sleep mode.
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* If ONDEMAND is 1, XOSC0 will be running when a peripheral is requesting the clock.
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* If ONDEMAND is 0, the clock source will always be running in standby sleep mode.
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* <br>See <a href="https://ww1.microchip.com/downloads/en/DeviceDoc/SAM_D5xE5x_Family_Data_Sheet_DS60001507F.pdf#page=723">Datasheet Reference</a>
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*/
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#define CONF_CORE_CLK_XOSC0_RUNSTDBY (0)
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/**
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* XOSC0 On Demand Control
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* @brief The On Demand operation mode allows the oscillator XOSC0 to be enabled or disabled, depending on peripheral clock requests.
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* - 0 => Oscillator is always on.
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* - 1 => The oscillator is running when a peripheral is requesting the oscillator to be used as a clock source.
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* The oscillator is not running if no peripheral is requesting the clock source.
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* <br>See <a href="https://ww1.microchip.com/downloads/en/DeviceDoc/SAM_D5xE5x_Family_Data_Sheet_DS60001507F.pdf#page=722">Datasheet Reference</a>
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*/
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#define CONF_CORE_CLK_XOSC0_ONDEMAND (0)
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/**
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* XOSC0 Low Buffer Gain Control Bit
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* @brief The default value of LOWBUFGAIN=0 should be used to allow operating with a low amplitude oscillator.
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* Don't use this setting except to solve stability issues.
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* - 0 => The low buffer gain of XOSC0 is disabled.
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* - 1 => The low buffer gain of XOSC0 is enabled.
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* <br>See <a href="https://ww1.microchip.com/downloads/en/DeviceDoc/SAM_D5xE5x_Family_Data_Sheet_DS60001507F.pdf#page=722">Datasheet Reference</a>
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*/
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#define CONF_CORE_CLK_XOSC0_LOWBUFGAIN (0)
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/**
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* XOSC0 Automatic Loop Control
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* @brief This bit controls the XOSC0 automatic loop control:
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* - 0 => The automatic loop control is disabled.
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* - 1 => The automatic loop control is enabled. Oscillator's amplitude will be automatically adjusted during Crystal Oscillator operation.
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* <br>See <a href="https://ww1.microchip.com/downloads/en/DeviceDoc/SAM_D5xE5x_Family_Data_Sheet_DS60001507F.pdf#page=722">Datasheet Reference</a>
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*/
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#define CONF_CORE_CLK_XOSC0_ENALC (1)
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/**
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* XOSC0 Clock Failure Detector Control
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* @brief This bit controls the XOSC0 clock failure detector:
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* - 0 => Clock Failure Detector is disabled.
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* - 1 => Clock Failure Detector is enabled.
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* <br>See <a href="https://ww1.microchip.com/downloads/en/DeviceDoc/SAM_D5xE5x_Family_Data_Sheet_DS60001507F.pdf#page=722">Datasheet Reference</a>
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*/
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#define CONF_CORE_CLK_XOSC0_CFDEN (1)
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/**
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* XOSC0 Clock Switch Enable
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* @brief This bit controls the XOSC0 output clock switch back to the external clock or crystal oscillator in case of clock recovery:
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* - 0 => The clock switch back is disabled.
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* - 1 => The clock switch back is enabled.
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* This bit is reset once the XOSC0 output clock is switched back to the external clock or crystal oscillator.
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* <br>See <a href="https://ww1.microchip.com/downloads/en/DeviceDoc/SAM_D5xE5x_Family_Data_Sheet_DS60001507F.pdf#page=722">Datasheet Reference</a>
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*/
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#define CONF_CORE_CLK_XOSC0_SWBEN (0)
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/**
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* XOSC0 Startup Time
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* @brief These bits select start-up time for XOSC0 according to the table below:
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* - 0x00 => 31us
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* - 0x01 => 61us
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* - 0x02 => 122us
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* - 0x03 => 244us
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* - 0x04 => 488us
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* - 0x05 => 977us
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* - 0x06 => 1953us
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* - 0x07 => 3906us
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* - 0x08 => 7813us
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* - 0x09 => 15625us
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* - 0x0A => 31250us
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* - 0x0B => 62500us
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* - 0x0C => 125000us
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* - 0x0D => 250000us
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* - 0x0E => 500000us
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* - 0x0F => 1000000us
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* <br>See <a href="https://ww1.microchip.com/downloads/en/DeviceDoc/SAM_D5xE5x_Family_Data_Sheet_DS60001507F.pdf#page=721">Datasheet Reference</a>
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*/
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#define CONF_CORE_CLK_XOSC0_STARTUP_TIME (0x00)
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/**
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* XOSC0 Frequency
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* @brief This is the frequency of the external clock you're using for XOSC0.
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* This can be anything from 8MHz to 48MHz.
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*/
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#define CONF_CORE_CLK_XOSC0_FREQUENCY 12000000
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/** @} */
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/** @name Core-XOSC1-Configuration
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* Configuration options for XOSC1.
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* <br>See <a href="https://ww1.microchip.com/downloads/en/DeviceDoc/SAM_D5xE5x_Family_Data_Sheet_DS60001507F.pdf#page=693">Datasheet Reference</a>
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* @{
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*/
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/**
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* XOSC1 Enable
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* @brief Enables or Disables the XOSC1 Clock
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* - 0 => Disables XOSC1
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* - 1 => Enables XOSC1
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* <br>See <a href="https://ww1.microchip.com/downloads/en/DeviceDoc/SAM_D5xE5x_Family_Data_Sheet_DS60001507F.pdf#page=723">Datasheet Reference</a>
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*/
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#define CONF_CORE_CLK_XOSC1_ENABLE (0)
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/**
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* XOSC1 XTALEN
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* @brief This bit controls the connections between the I/O pads and the external clock or crystal oscillator XOSC1:
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* - 0 => External clock connected on XIN. XOUT can be used as general purpose I/O.
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* - 1 => Crystal connected to XIN/XOUT.
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* <br>See <a href="https://ww1.microchip.com/downloads/en/DeviceDoc/SAM_D5xE5x_Family_Data_Sheet_DS60001507F.pdf#page=723">Datasheet Reference</a>
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*/
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#define CONF_CORE_CLK_XOSC1_XTALEN (0)
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/**
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* XOSC1 Run in Standby
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* @brief This bit controls how the XOSC1 behaves during standby sleep mode:
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* - 0 => XOSC1 is not running in standby sleep mode if no peripheral requests the clock.
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* - 1 => XOSC1 is running in standby sleep mode.
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* If ONDEMAND is 1, XOSC1 will be running when a peripheral is requesting the clock.
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* If ONDEMAND is 0, the clock source will always be running in standby sleep mode.
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* <br>See <a href="https://ww1.microchip.com/downloads/en/DeviceDoc/SAM_D5xE5x_Family_Data_Sheet_DS60001507F.pdf#page=723">Datasheet Reference</a>
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*/
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#define CONF_CORE_CLK_XOSC1_RUNSTDBY (0)
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/**
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* XOSC1 On Demand Control
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* @brief The On Demand operation mode allows the oscillator XOSC1 to be enabled or disabled, depending on peripheral clock requests.
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* - 0 => Oscillator is always on.
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* - 1 => The oscillator is running when a peripheral is requesting the oscillator to be used as a clock source.
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* The oscillator is not running if no peripheral is requesting the clock source.
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* <br>See <a href="https://ww1.microchip.com/downloads/en/DeviceDoc/SAM_D5xE5x_Family_Data_Sheet_DS60001507F.pdf#page=722">Datasheet Reference</a>
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*/
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#define CONF_CORE_CLK_XOSC1_ONDEMAND (0)
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/**
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* XOSC1 Low Buffer Gain Control Bit
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* @brief The default value of LOWBUFGAIN=0 should be used to allow operating with a low amplitude oscillator.
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* Don't use this setting except to solve stability issues.
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* - 0 => The low buffer gain of XOSC1 is disabled.
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* - 1 => The low buffer gain of XOSC1 is enabled.
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* <br>See <a href="https://ww1.microchip.com/downloads/en/DeviceDoc/SAM_D5xE5x_Family_Data_Sheet_DS60001507F.pdf#page=722">Datasheet Reference</a>
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*/
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#define CONF_CORE_CLK_XOSC1_LOWBUFGAIN (0)
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/**
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* XOSC1 Automatic Loop Control
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* @brief This bit controls the XOSC1 automatic loop control:
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* - 0 => The automatic loop control is disabled.
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* - 1 => The automatic loop control is enabled. Oscillator's amplitude will be automatically adjusted during Crystal Oscillator operation.
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* <br>See <a href="https://ww1.microchip.com/downloads/en/DeviceDoc/SAM_D5xE5x_Family_Data_Sheet_DS60001507F.pdf#page=722">Datasheet Reference</a>
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*/
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#define CONF_CORE_CLK_XOSC1_ENALC (0)
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/**
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* XOSC1 Clock Failure Detector Control
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* @brief This bit controls the XOSC1 clock failure detector:
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* - 0 => Clock Failure Detector is disabled.
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* - 1 => Clock Failure Detector is enabled.
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* <br>See <a href="https://ww1.microchip.com/downloads/en/DeviceDoc/SAM_D5xE5x_Family_Data_Sheet_DS60001507F.pdf#page=722">Datasheet Reference</a>
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*/
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#define CONF_CORE_CLK_XOSC1_CFDEN (0)
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/**
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* XOSC1 Clock Switch Enable
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* @brief This bit controls the XOSC1 output clock switch back to the external clock or crystal oscillator in case of clock recovery:
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* - 0 => The clock switch back is disabled.
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* - 1 => The clock switch back is enabled.
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* This bit is reset once the XOSC1 output clock is switched back to the external clock or crystal oscillator.
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* <br>See <a href="https://ww1.microchip.com/downloads/en/DeviceDoc/SAM_D5xE5x_Family_Data_Sheet_DS60001507F.pdf#page=722">Datasheet Reference</a>
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*/
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#define CONF_CORE_CLK_XOSC1_SWBEN (0)
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/**
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* XOSC1 Startup Time
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* @brief These bits select start-up time for XOSC1 according to the table below:
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* - 0x00 => 31us
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* - 0x01 => 61us
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* - 0x02 => 122us
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* - 0x03 => 244us
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* - 0x04 => 488us
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* - 0x05 => 977us
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* - 0x06 => 1953us
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* - 0x07 => 3906us
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* - 0x08 => 7813us
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* - 0x09 => 15625us
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* - 0x0A => 31250us
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* - 0x0B => 62500us
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* - 0x0C => 125000us
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* - 0x0D => 250000us
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* - 0x0E => 500000us
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* - 0x0F => 1000000us
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* <br>See <a href="https://ww1.microchip.com/downloads/en/DeviceDoc/SAM_D5xE5x_Family_Data_Sheet_DS60001507F.pdf#page=721">Datasheet Reference</a>
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*/
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#define CONF_CORE_CLK_XOSC1_STARTUP_TIME (0x00)
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/**
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* XOSC1 Frequency
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* @brief This is the frequency of the external clock you're using for XOSC1.
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* This can be anything from 8MHz to 48MHz.
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*/
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#define CONF_CORE_CLK_XOSC1_FREQUENCY 12000000
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/** @} */
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/** @name Core-XOSC32K-Configuration
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* Configuration options for the external 32khz oscillator.
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* <br>See <a href="https://ww1.microchip.com/downloads/en/DeviceDoc/SAM_D5xE5x_Family_Data_Sheet_DS60001507F.pdf#page=735">Datasheet Reference</a>
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* @{
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*/
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/**
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* XOSC32K Enable
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* @brief Enables or Disables XOSC32K.
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* - 0 => The oscillator is disabled.
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* - 1 => The oscillator is enabled.
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* <br>See <a href="https://ww1.microchip.com/downloads/en/DeviceDoc/SAM_D5xE5x_Family_Data_Sheet_DS60001507F.pdf#page=749">Datasheet Reference</a>
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*/
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#define CONF_CORE_CLK_XOSC32K_ENABLE (1)
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/**
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* XOSC32K Control Gain Mode
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* @brief These bits control the gain of the external crstal oscillator.
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* - 0x00 => Low Power Mode
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* - 0x01 => Standard Mode (Default)
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* - 0x02 => High Speed Mode
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* <br>See <a href="https://ww1.microchip.com/downloads/en/DeviceDoc/SAM_D5xE5x_Family_Data_Sheet_DS60001507F.pdf#page=748">Datasheet Reference</a>
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*/
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#define CONF_CORE_CLK_XOSC32K_CGM (0x01)
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/**
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* XOSC32K Startup Time
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* @brief These bits select the startup time for the oscillator.
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* - 0x00 => 62.592ms
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* - 0x01 => 125.092ms
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* - 0x02 => 500.092ms
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* - 0x03 => 1000.0092ms
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* - 0x04 => 2000.0092ms
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* - 0x05 => 4000.0092ms
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* - 0x06 => 8000.0092ms
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* <br>See <a href="https://ww1.microchip.com/downloads/en/DeviceDoc/SAM_D5xE5x_Family_Data_Sheet_DS60001507F.pdf#page=748">Datasheet Reference</a>
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*/
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#define CONF_CORE_CLK_XOSC32K_STARTUP_TIME CONF_CORE_CLK_XOSC32KCTRL_STARTUP_62592us
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/**
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* XOSC32K On Demand Control
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* @brief This bit controls how XOSC32K behaves when a peripheral clock request is detected.
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* - 0 => On Demand Control disabled
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* - 1 => On Demand Control enabled
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* <br>See <a href="https://ww1.microchip.com/downloads/en/DeviceDoc/SAM_D5xE5x_Family_Data_Sheet_DS60001507F.pdf#page=748">Datasheet Reference</a>
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*/
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#define CONF_CORE_CLK_XOSC32K_ONDEMAND (1)
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/**
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* XOSC32K Run in Standby
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* @brief This bit controls how XOSC32K behaves during standby sleep mode.
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* - 0 => Run if requested by peripheral.
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* - 1 => Run if requested by peripheral OR always run depending ONDEMAND value.
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* <br>See <a href="https://ww1.microchip.com/downloads/en/DeviceDoc/SAM_D5xE5x_Family_Data_Sheet_DS60001507F.pdf#page=748">Datasheet Reference</a>
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*/
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#define CONF_CORE_CLK_XOSC32K_RUNSTDBY (0)
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/**
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* XOSC32K 1KHz Output Control
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* - 0 => 1KHz output is disabled.
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* - 1 => 1KHz output is enabled.
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* <br>See <a href="https://ww1.microchip.com/downloads/en/DeviceDoc/SAM_D5xE5x_Family_Data_Sheet_DS60001507F.pdf#page=749">Datasheet Reference</a>
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*/
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#define CONF_CORE_CLK_XOSC32K_EN1K (0)
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/**
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* XOSC32K 32KHz Output Control
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* - 0 => 32KHz output is disabled.
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* - 1 => 32KHz output is enabled.
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* <br>See <a href="https://ww1.microchip.com/downloads/en/DeviceDoc/SAM_D5xE5x_Family_Data_Sheet_DS60001507F.pdf#page=749">Datasheet Reference</a>
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*/
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#define CONF_CORE_CLK_XOSC32K_EN32K (1)
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/**
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* XOSC32K Crystal Oscillator Enable
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* @brief This bit controls the connections between the I/O pads and the external clock or crystal oscillator.
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* - 0 => External clock is connected on XIN32. XOUT32 can be used as general-purpose I/O.
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* - 1 => Crystal connected to XIN32/XOUT32.
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* <br>See <a href="https://ww1.microchip.com/downloads/en/DeviceDoc/SAM_D5xE5x_Family_Data_Sheet_DS60001507F.pdf#page=749">Datasheet Reference</a>
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*/
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#define CONF_CORE_CLK_XOSC32K_XTALEN (1)
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/**
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* XOSC32K Clock Failure Detector Prescaler
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* @brief This bit selects the prescaler for the CLock Failure Detector:
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* - 0 => The CFD safe clock frequency is the OSCULP32K frequency.
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* - 1 => The CFD safe clock frequency is the OSCULP32K frequency divided by 2.
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* <br>See <a href="https://ww1.microchip.com/downloads/en/DeviceDoc/SAM_D5xE5x_Family_Data_Sheet_DS60001507F.pdf#page=750">Datasheet Reference</a>
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*/
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#define CONF_CORE_CLK_XOSC32K_CFDPRESC (0)
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/**
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* XOSC32K Clock Failure Detector Control
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* @brief This bit selects the Clock Failulre Detector state.
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* - 0 => The CFD is disabled.
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|
* - 1 => The CFD is enabled.
|
|
* <br>See <a href="https://ww1.microchip.com/downloads/en/DeviceDoc/SAM_D5xE5x_Family_Data_Sheet_DS60001507F.pdf#page=750">Datasheet Reference</a>
|
|
*/
|
|
#define CONF_CORE_CLK_XOSC32K_CFDEN (0)
|
|
/**
|
|
* XOSC32K Clock Switch Back
|
|
* @brief This bit controls the XOSC32K output switch back to the external clock or crystal oscillator in case of clock recovery.
|
|
* - 0 => The clock switch is disabled.
|
|
* - 1 => The clock switch is enabled. This bit is reset when XOSC32K output is switched back to the external clock or crystal oscillator.
|
|
* <br>See <a href="https://ww1.microchip.com/downloads/en/DeviceDoc/SAM_D5xE5x_Family_Data_Sheet_DS60001507F.pdf#page=750">Datasheet Reference</a>
|
|
*/
|
|
#define CONF_CORE_CLK_XOSC32K_SWBACK (0)
|
|
/**
|
|
* XOSC32K Write Lock
|
|
* @brief This bit locks the XOSC32K register for future writes, effectively freezing the XOSC32K configuration.
|
|
* - 0 => XOSC32K configuration is not locked.
|
|
* - 1 => XOSC32K configuration is locked.
|
|
* <br>See <a href="https://ww1.microchip.com/downloads/en/DeviceDoc/SAM_D5xE5x_Family_Data_Sheet_DS60001507F.pdf#page=748">Datasheet Reference</a>
|
|
*/
|
|
#define CONF_CORE_CLK_XOSC32K_WRTLOCK (0)
|
|
/** @} */
|
|
|
|
/** @name Core-DFLL48M-Configuration
|
|
* Configuration options for DFLL48M
|
|
*/
|
|
/** @{ */
|
|
/**
|
|
* DFLL48M Enable
|
|
* @brief Enables or Disables the DFLL48M Clock
|
|
* - 0 => Disables DFLL48M
|
|
* - 1 => Enables DFLL48M
|
|
* <br>pg. 724 of datasheet
|
|
*/
|
|
#define CONF_CORE_CLK_DFLL_ENABLE (1)
|
|
/**
|
|
* DFLL48M On Demand Control
|
|
* @brief Enables or Disables on-demand operation
|
|
* - 0 => Disables On Demand Operation
|
|
* - 1 => Enables On Demand Operation
|
|
* <br>pg. 724 of datasheet
|
|
*/
|
|
#define CONF_CORE_CLK_DFLL_ONDEMAND (0)
|
|
/**
|
|
* DFLL48M Run in Standby Control
|
|
* @brief Enables or Disables run-in-standby operation
|
|
* - 0 => Disables run-in-standby operation
|
|
* - 1 => Enables run-in-standby operation
|
|
* <br>pg. 724 of datasheet
|
|
*/
|
|
#define CONF_CORE_CLK_DFLL_RUNSTDBY (0)
|
|
/**
|
|
* DFLL48M Wait Lock Control
|
|
@brief This bit controls the DFLL output clock, depending on the lock status:
|
|
* - 0 => Output clock before the DFLL is locked.
|
|
* - 1 => Output clock when DFLL is locked (Fine lock).
|
|
* <br>pg. 725 of datasheet
|
|
*/
|
|
#define CONF_CORE_CLK_DFLL_WAITLOCK (0)
|
|
#define CONF_CORE_CLK_DFLL_BPLKC (0)
|
|
#define CONF_CORE_CLK_DFLL_QLDIS (0)
|
|
#define CONF_CORE_CLK_DFLL_CCDIS (1)
|
|
#define CONF_CORE_CLK_DFLL_USBCRM (1)
|
|
#define CONF_CORE_CLK_DFLL_LLAW (0)
|
|
#define CONF_CORE_CLK_DFLL_STABLE_FCALIB CONF_CORE_CLK_DFLLCTRL_STABLE_FCALIB_NOT_FIXED
|
|
#define CONF_CORE_CLK_DFLL_MODE 0x01
|
|
#define CONF_CORE_CLK_DFLL_DIFF_VAL 0
|
|
#define CONF_CORE_CLK_DFLL_COARSE_VAL (0x1f / 4)
|
|
#define CONF_CORE_CLK_DFLL_FINE_VAL 128
|
|
#define CONF_CORE_CLK_DFLL_CSTEP_VAL 1
|
|
#define CONF_CORE_CLK_DFLL_FSTEP_VAL 1
|
|
#define CONF_CORE_CLK_DFLL_MUL_VAL (48000000)
|
|
/**
|
|
* DFLL48M GCLK Source
|
|
* @brief GCLK Source used to generate DFLL48M
|
|
* - 0 => Generic clock generator 0
|
|
* - 1 => Generic clock generator 1
|
|
* - 2 => Generic clock generator 2
|
|
* - 3 => Generic clock generator 3
|
|
* - 4 => Generic clock generator 4
|
|
* - 5 => Generic clock generator 5
|
|
* - 6 => Generic clock generator 6
|
|
* - 7 => Generic clock generator 7
|
|
* - 8 => Generic clock generator 8
|
|
* - 9 => Generic clock generator 9
|
|
* - 10 => Generic clock generator 10
|
|
* - 11 => Generic clock generator 11
|
|
*/
|
|
#define CONF_CORE_CLK_DFLL_GCLK_SRC 3
|
|
#define CONF_CORE_CLK_DFLL_OVERWRITE_CAL 0
|
|
/** @} */
|
|
|
|
/** @name Core-DPLL0-Configuration
|
|
* Configuration Options for DPLL0.
|
|
* @{
|
|
*/
|
|
|
|
#define CONF_CORE_CLK_DPLL0_ENABLE (1)
|
|
#define CONF_CORE_CLK_DPLL0_ONDEMAND (0)
|
|
#define CONF_CORE_CLK_DPLL0_RUNSTDBY (0)
|
|
#define CONF_CORE_CLK_DPLL0_LDRFRAC_VAL 0
|
|
#define CONF_CORE_CLK_DPLL0_LDR_VAL (119)
|
|
#define CONF_CORE_CLK_DPLL0_DIV_VAL (5)
|
|
#define CONF_CORE_CLK_DPLL0_DCOEN 0
|
|
#define CONF_CORE_CLK_DPLL0_DCOFILTER CONF_CORE_CLK_DPLLCTRL_DCOFILTER_3210KHZ
|
|
#define CONF_CORE_CLK_DPLL0_LBYPASS 1
|
|
#define CONF_CORE_CLK_DPLL0_LTIME 0
|
|
#define CONF_CORE_CLK_DPLL0_WUF 0
|
|
#define CONF_CORE_CLK_DPLL0_GCLK_SRC GCLK_GENCTRL_SRC_XOSC0
|
|
#define CONF_CORE_CLK_DPLL0_REFCLK CONF_CORE_CLK_DPLLCTRL_REFCLK_XOSC0
|
|
/**
|
|
* pg. 732 of the datasheet
|
|
* ~~~
|
|
* FILTER[3:0] | PLL Bandwidth (fn) | Damping Factor
|
|
* 0x0 | 92.7 kHz | 0.76
|
|
* 0x1 | 131 kHz | 1.08
|
|
* 0x2 | 46.4 kHz | 0.38
|
|
* 0x3 | 65.6 kHz | 0.54
|
|
* 0x4 | 131 kHz | 0.56
|
|
* 0x5 | 185 kHz | 0.79
|
|
* 0x6 | 65.6 kHz | 0.28
|
|
* 0x7 | 92.7 kHz | 0.39
|
|
* 0x8 | 46.4 kHz | 1.49
|
|
* 0x9 | 65.6 kHz | 2.11
|
|
* 0xA | 23.2 kHz | 0.75
|
|
* 0xB | 32.8 kHz | 1.06
|
|
* 0xC | 65.6 kHz | 1.07
|
|
* 0xD | 92.7 kHz | 1.51
|
|
* 0xE | 32.8 kHz | 0.53
|
|
* 0xF | 46.4 kHz | 0.75
|
|
* ~~~
|
|
*
|
|
* When in doubt, leave this at its default.
|
|
*/
|
|
#define CONF_CORE_CLK_DPLL0_FILTER 0x0
|
|
|
|
/** @} */
|
|
|
|
/** @name Core-DPLL1-Configuration
|
|
* Configuration Options for DPLL1.
|
|
* @{
|
|
*/
|
|
#define CONF_CORE_CLK_DPLL1_ENABLE (0)
|
|
#define CONF_CORE_CLK_DPLL1_ONDEMAND (0)
|
|
#define CONF_CORE_CLK_DPLL1_RUNSTDBY (0)
|
|
#define CONF_CORE_CLK_DPLL1_LDRFRAC_VAL 0
|
|
#define CONF_CORE_CLK_DPLL1_LDR_VAL (0)
|
|
#define CONF_CORE_CLK_DPLL1_DIV_VAL (0)
|
|
#define CONF_CORE_CLK_DPLL1_DCOEN 0
|
|
#define CONF_CORE_CLK_DPLL1_DCOFILTER CONF_CORE_CLK_DPLLCTRL_DCOFILTER_3210KHZ
|
|
#define CONF_CORE_CLK_DPLL1_LBYPASS 0
|
|
#define CONF_CORE_CLK_DPLL1_LTIME 0
|
|
#define CONF_CORE_CLK_DPLL1_WUF 0
|
|
#define CONF_CORE_CLK_DPLL1_GCLK_SRC GCLK_GENCTRL_SRC_XOSC0
|
|
#define CONF_CORE_CLK_DPLL1_REFCLK CONF_CORE_CLK_DPLLCTRL_REFCLK_XOSC0
|
|
/**
|
|
* pg. 732 of the datasheet
|
|
* ~~~
|
|
* FILTER[3:0] | PLL Bandwidth (fn) | Damping Factor
|
|
* 0x0 | 92.7 kHz | 0.76
|
|
* 0x1 | 131 kHz | 1.08
|
|
* 0x2 | 46.4 kHz | 0.38
|
|
* 0x3 | 65.6 kHz | 0.54
|
|
* 0x4 | 131 kHz | 0.56
|
|
* 0x5 | 185 kHz | 0.79
|
|
* 0x6 | 65.6 kHz | 0.28
|
|
* 0x7 | 92.7 kHz | 0.39
|
|
* 0x8 | 46.4 kHz | 1.49
|
|
* 0x9 | 65.6 kHz | 2.11
|
|
* 0xA | 23.2 kHz | 0.75
|
|
* 0xB | 32.8 kHz | 1.06
|
|
* 0xC | 65.6 kHz | 1.07
|
|
* 0xD | 92.7 kHz | 1.51
|
|
* 0xE | 32.8 kHz | 0.53
|
|
* 0xF | 46.4 kHz | 0.75
|
|
* ~~~
|
|
*
|
|
* When in doubt, leave this at its default.
|
|
*/
|
|
#define CONF_CORE_CLK_DPLL1_FILTER 0x0
|
|
|
|
/** @} */
|
|
|
|
// GCLK Generators Config
|
|
#define CONF_CORE_GCLK_0_ENABLE 1
|
|
#define CONF_CORE_GCLK_0_RUN_IN_STANDBY 1
|
|
#define CONF_CORE_GCLK_0_CLOCK_SOURCE GCLK_GENCTRL_SRC_XOSC0
|
|
#define CONF_CORE_GCLK_0_DIV_VAL 1
|
|
#define CONF_CORE_GCLK_0_DIVSEL 0
|
|
#define CONF_CORE_GCLK_0_OUTPUT_ENABLE 1
|
|
#define CONF_CORE_GCLK_0_OUTPUT_OFF_VALUE 1
|
|
#define CONF_CORE_GCLK_0_IDC 1
|
|
|
|
#define CONF_CORE_GCLK_1_ENABLE 0
|
|
#define CONF_CORE_GCLK_1_RUN_IN_STANDBY 0
|
|
#define CONF_CORE_GCLK_1_CLOCK_SOURCE GCLK_GENCTRL_SRC_XOSC0
|
|
#define CONF_CORE_GCLK_1_DIV_VAL 1
|
|
#define CONF_CORE_GCLK_1_DIVSEL 0
|
|
#define CONF_CORE_GCLK_1_OUTPUT_ENABLE 0
|
|
#define CONF_CORE_GCLK_1_OUTPUT_OFF_VALUE 0
|
|
#define CONF_CORE_GCLK_1_IDC 0
|
|
|
|
#define CONF_CORE_GCLK_2_ENABLE 0
|
|
#define CONF_CORE_GCLK_2_RUN_IN_STANDBY 0
|
|
#define CONF_CORE_GCLK_2_CLOCK_SOURCE GCLK_GENCTRL_SRC_XOSC0
|
|
#define CONF_CORE_GCLK_2_DIV_VAL 1
|
|
#define CONF_CORE_GCLK_2_DIVSEL 0
|
|
#define CONF_CORE_GCLK_2_OUTPUT_ENABLE 0
|
|
#define CONF_CORE_GCLK_2_OUTPUT_OFF_VALUE 0
|
|
#define CONF_CORE_GCLK_2_IDC 0
|
|
|
|
#define CONF_CORE_GCLK_3_ENABLE 1
|
|
#define CONF_CORE_GCLK_3_RUN_IN_STANDBY 0
|
|
#define CONF_CORE_GCLK_3_CLOCK_SOURCE GCLK_GENCTRL_SRC_XOSC32K
|
|
#define CONF_CORE_GCLK_3_DIV_VAL 1
|
|
#define CONF_CORE_GCLK_3_DIVSEL 0
|
|
#define CONF_CORE_GCLK_3_OUTPUT_ENABLE 0
|
|
#define CONF_CORE_GCLK_3_OUTPUT_OFF_VALUE 0
|
|
#define CONF_CORE_GCLK_3_IDC 0
|
|
|
|
#define CONF_CORE_GCLK_4_ENABLE 0
|
|
#define CONF_CORE_GCLK_4_RUN_IN_STANDBY 0
|
|
#define CONF_CORE_GCLK_4_CLOCK_SOURCE GCLK_GENCTRL_SRC_XOSC0
|
|
#define CONF_CORE_GCLK_4_DIV_VAL 1
|
|
#define CONF_CORE_GCLK_4_DIVSEL 1
|
|
#define CONF_CORE_GCLK_4_OUTPUT_ENABLE 0
|
|
#define CONF_CORE_GCLK_4_OUTPUT_OFF_VALUE 0
|
|
#define CONF_CORE_GCLK_4_IDC 0
|
|
|
|
#define CONF_CORE_GCLK_5_ENABLE 0
|
|
#define CONF_CORE_GCLK_5_RUN_IN_STANDBY 0
|
|
#define CONF_CORE_GCLK_5_CLOCK_SOURCE GCLK_GENCTRL_SRC_XOSC0
|
|
#define CONF_CORE_GCLK_5_DIV_VAL 1
|
|
#define CONF_CORE_GCLK_5_DIVSEL 0
|
|
#define CONF_CORE_GCLK_5_OUTPUT_ENABLE 0
|
|
#define CONF_CORE_GCLK_5_OUTPUT_OFF_VALUE 0
|
|
#define CONF_CORE_GCLK_5_IDC 0
|
|
|
|
#define CONF_CORE_GCLK_6_ENABLE 0
|
|
#define CONF_CORE_GCLK_6_RUN_IN_STANDBY 0
|
|
#define CONF_CORE_GCLK_6_CLOCK_SOURCE GCLK_GENCTRL_SRC_XOSC0
|
|
#define CONF_CORE_GCLK_6_DIV_VAL 1
|
|
#define CONF_CORE_GCLK_6_DIVSEL 0
|
|
#define CONF_CORE_GCLK_6_OUTPUT_ENABLE 0
|
|
#define CONF_CORE_GCLK_6_OUTPUT_OFF_VALUE 0
|
|
#define CONF_CORE_GCLK_6_IDC 0
|
|
|
|
#define CONF_CORE_GCLK_7_ENABLE 0
|
|
#define CONF_CORE_GCLK_7_RUN_IN_STANDBY 0
|
|
#define CONF_CORE_GCLK_7_CLOCK_SOURCE GCLK_GENCTRL_SRC_XOSC0
|
|
#define CONF_CORE_GCLK_7_DIV_VAL 1
|
|
#define CONF_CORE_GCLK_7_DIVSEL 0
|
|
#define CONF_CORE_GCLK_7_OUTPUT_ENABLE 0
|
|
#define CONF_CORE_GCLK_7_OUTPUT_OFF_VALUE 0
|
|
#define CONF_CORE_GCLK_7_IDC 0
|
|
|
|
#define CONF_CORE_GCLK_8_ENABLE 0
|
|
#define CONF_CORE_GCLK_8_RUN_IN_STANDBY 0
|
|
#define CONF_CORE_GCLK_8_CLOCK_SOURCE GCLK_GENCTRL_SRC_XOSC0
|
|
#define CONF_CORE_GCLK_8_DIV_VAL 1
|
|
#define CONF_CORE_GCLK_8_DIVSEL 0
|
|
#define CONF_CORE_GCLK_8_OUTPUT_ENABLE 0
|
|
#define CONF_CORE_GCLK_8_OUTPUT_OFF_VALUE 0
|
|
#define CONF_CORE_GCLK_8_IDC 0
|
|
|
|
#define CONF_CORE_GCLK_9_ENABLE 0
|
|
#define CONF_CORE_GCLK_9_RUN_IN_STANDBY 0
|
|
#define CONF_CORE_GCLK_9_CLOCK_SOURCE GCLK_GENCTRL_SRC_XOSC0
|
|
#define CONF_CORE_GCLK_9_DIV_VAL 1
|
|
#define CONF_CORE_GCLK_9_DIVSEL 0
|
|
#define CONF_CORE_GCLK_9_OUTPUT_ENABLE 0
|
|
#define CONF_CORE_GCLK_9_OUTPUT_OFF_VALUE 0
|
|
#define CONF_CORE_GCLK_9_IDC 0
|
|
|
|
#define CONF_CORE_GCLK_10_ENABLE 0
|
|
#define CONF_CORE_GCLK_10_RUN_IN_STANDBY 0
|
|
#define CONF_CORE_GCLK_10_CLOCK_SOURCE GCLK_GENCTRL_SRC_XOSC0
|
|
#define CONF_CORE_GCLK_10_DIV_VAL 1
|
|
#define CONF_CORE_GCLK_10_DIVSEL 0
|
|
#define CONF_CORE_GCLK_10_OUTPUT_ENABLE 0
|
|
#define CONF_CORE_GCLK_10_OUTPUT_OFF_VALUE 0
|
|
#define CONF_CORE_GCLK_10_IDC 0
|
|
|
|
#define CONF_CORE_GCLK_11_ENABLE 0
|
|
#define CONF_CORE_GCLK_11_RUN_IN_STANDBY 0
|
|
#define CONF_CORE_GCLK_11_CLOCK_SOURCE GCLK_GENCTRL_SRC_XOSC0
|
|
#define CONF_CORE_GCLK_11_DIV_VAL 1
|
|
#define CONF_CORE_GCLK_11_DIVSEL 0
|
|
#define CONF_CORE_GCLK_11_OUTPUT_ENABLE 0
|
|
#define CONF_CORE_GCLK_11_OUTPUT_OFF_VALUE 0
|
|
#define CONF_CORE_GCLK_11_IDC 0
|
|
|
|
|
|
|
|
#endif
|