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<div class="textblock"><code>#include "clocks.h"</code><br />
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Macros</h2></td></tr>
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<tr class="memitem:a16a34b830edda5b571c41a0f865f7051"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="conf__core_8h.html#a16a34b830edda5b571c41a0f865f7051">CONF_CORE_DMA_ENABLE</a>   (0)</td></tr>
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<tr class="memitem:a81edcdaa3908cc3d99a95047e4431405"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="conf__core_8h.html#a81edcdaa3908cc3d99a95047e4431405">CONF_CORE_CMCC_ENABLE</a>   (0)</td></tr>
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<tr class="memitem:a4e846249cdbec567989afa93b6653671"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="conf__core_8h.html#a4e846249cdbec567989afa93b6653671">CONF_CORE_PORT_EVCTRL_0_ENABLE</a>   (0)</td></tr>
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<tr class="separator:a4e846249cdbec567989afa93b6653671"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ab1c71bf1f1249ce9046aca27329ae588"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="conf__core_8h.html#ab1c71bf1f1249ce9046aca27329ae588">CONF_CORE_PORT_EVCTRL_1_ENABLE</a>   (0)</td></tr>
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<tr class="separator:ab1c71bf1f1249ce9046aca27329ae588"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a7971c1d952e35ecc50ae18de2b2c48ed"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="conf__core_8h.html#a7971c1d952e35ecc50ae18de2b2c48ed">CONF_CORE_PORT_EVCTRL_2_ENABLE</a>   (0)</td></tr>
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<tr class="separator:a7971c1d952e35ecc50ae18de2b2c48ed"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aa12d1235b86b670a7ef905dd19684394"><td class="memItemLeft" align="right" valign="top"><a id="aa12d1235b86b670a7ef905dd19684394"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>CONF_CORE_GCLK_0_ENABLE</b>   1</td></tr>
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<tr class="separator:aa12d1235b86b670a7ef905dd19684394"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a6dc24676c572ffb475d100ff95c5199b"><td class="memItemLeft" align="right" valign="top"><a id="a6dc24676c572ffb475d100ff95c5199b"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>CONF_CORE_GCLK_0_RUN_IN_STANDBY</b>   1</td></tr>
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<tr class="separator:a6dc24676c572ffb475d100ff95c5199b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a08979972c234f656e181c8ace594706d"><td class="memItemLeft" align="right" valign="top"><a id="a08979972c234f656e181c8ace594706d"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>CONF_CORE_GCLK_0_CLOCK_SOURCE</b>   GCLK_GENCTRL_SRC_XOSC0</td></tr>
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<tr class="separator:a08979972c234f656e181c8ace594706d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:af0c0c62090c344a4d4acf61a7a4eb0df"><td class="memItemLeft" align="right" valign="top"><a id="af0c0c62090c344a4d4acf61a7a4eb0df"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>CONF_CORE_GCLK_0_DIV_VAL</b>   1</td></tr>
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<tr class="separator:af0c0c62090c344a4d4acf61a7a4eb0df"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a5c9fae37e7a649df4320056c724a726f"><td class="memItemLeft" align="right" valign="top"><a id="a5c9fae37e7a649df4320056c724a726f"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>CONF_CORE_GCLK_0_DIVSEL</b>   0</td></tr>
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<tr class="separator:a5c9fae37e7a649df4320056c724a726f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a28f3e46699ee7f15f3472c83f0bdc3f9"><td class="memItemLeft" align="right" valign="top"><a id="a28f3e46699ee7f15f3472c83f0bdc3f9"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>CONF_CORE_GCLK_0_OUTPUT_ENABLE</b>   1</td></tr>
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<tr class="separator:a28f3e46699ee7f15f3472c83f0bdc3f9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a209ad10d24a0da3b0b74395e40d0d0d0"><td class="memItemLeft" align="right" valign="top"><a id="a209ad10d24a0da3b0b74395e40d0d0d0"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>CONF_CORE_GCLK_0_OUTPUT_OFF_VALUE</b>   1</td></tr>
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<tr class="separator:a209ad10d24a0da3b0b74395e40d0d0d0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a40c081b3a742d3c55373bcef391b5c07"><td class="memItemLeft" align="right" valign="top"><a id="a40c081b3a742d3c55373bcef391b5c07"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>CONF_CORE_GCLK_0_IDC</b>   1</td></tr>
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<tr class="separator:a40c081b3a742d3c55373bcef391b5c07"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a8d9ccb2f35ff5d8a40abfb50fc61fd55"><td class="memItemLeft" align="right" valign="top"><a id="a8d9ccb2f35ff5d8a40abfb50fc61fd55"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>CONF_CORE_GCLK_1_ENABLE</b>   0</td></tr>
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<tr class="separator:a8d9ccb2f35ff5d8a40abfb50fc61fd55"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a8c81d8e4f7d8ca9d3c77b62a0e02fe82"><td class="memItemLeft" align="right" valign="top"><a id="a8c81d8e4f7d8ca9d3c77b62a0e02fe82"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>CONF_CORE_GCLK_1_RUN_IN_STANDBY</b>   0</td></tr>
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<tr class="separator:a8c81d8e4f7d8ca9d3c77b62a0e02fe82"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aaa4c22e3db3f9e5abdd4bb17b601321c"><td class="memItemLeft" align="right" valign="top"><a id="aaa4c22e3db3f9e5abdd4bb17b601321c"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>CONF_CORE_GCLK_1_CLOCK_SOURCE</b>   GCLK_GENCTRL_SRC_XOSC0</td></tr>
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<tr class="separator:aaa4c22e3db3f9e5abdd4bb17b601321c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a5e428b4c66b439761ddd85ffe62217f4"><td class="memItemLeft" align="right" valign="top"><a id="a5e428b4c66b439761ddd85ffe62217f4"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>CONF_CORE_GCLK_1_DIV_VAL</b>   1</td></tr>
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<tr class="separator:a5e428b4c66b439761ddd85ffe62217f4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ab2e12f8a900da42d0ca3185486aa3653"><td class="memItemLeft" align="right" valign="top"><a id="ab2e12f8a900da42d0ca3185486aa3653"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>CONF_CORE_GCLK_1_DIVSEL</b>   0</td></tr>
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<tr class="separator:ab2e12f8a900da42d0ca3185486aa3653"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ad5f70ffa2565a521897a629837d9c5a9"><td class="memItemLeft" align="right" valign="top"><a id="ad5f70ffa2565a521897a629837d9c5a9"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>CONF_CORE_GCLK_1_OUTPUT_ENABLE</b>   0</td></tr>
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<tr class="separator:ad5f70ffa2565a521897a629837d9c5a9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aa5c814d9d6ba645e7bd3eebf492a0c38"><td class="memItemLeft" align="right" valign="top"><a id="aa5c814d9d6ba645e7bd3eebf492a0c38"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>CONF_CORE_GCLK_1_OUTPUT_OFF_VALUE</b>   0</td></tr>
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<tr class="separator:aa5c814d9d6ba645e7bd3eebf492a0c38"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:af8fa5cba6da8e7352bcd60fc6e8a850f"><td class="memItemLeft" align="right" valign="top"><a id="af8fa5cba6da8e7352bcd60fc6e8a850f"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>CONF_CORE_GCLK_1_IDC</b>   0</td></tr>
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<tr class="separator:af8fa5cba6da8e7352bcd60fc6e8a850f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a54011e35887479079cfd4a6f627e3ea0"><td class="memItemLeft" align="right" valign="top"><a id="a54011e35887479079cfd4a6f627e3ea0"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>CONF_CORE_GCLK_2_ENABLE</b>   0</td></tr>
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<tr class="separator:a54011e35887479079cfd4a6f627e3ea0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a6964718e73d3745689f7b534943215a3"><td class="memItemLeft" align="right" valign="top"><a id="a6964718e73d3745689f7b534943215a3"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>CONF_CORE_GCLK_2_RUN_IN_STANDBY</b>   0</td></tr>
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<tr class="separator:a6964718e73d3745689f7b534943215a3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a025cbbf0db710bb350bba8e7caa9c5d3"><td class="memItemLeft" align="right" valign="top"><a id="a025cbbf0db710bb350bba8e7caa9c5d3"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>CONF_CORE_GCLK_2_CLOCK_SOURCE</b>   GCLK_GENCTRL_SRC_XOSC0</td></tr>
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<tr class="separator:a025cbbf0db710bb350bba8e7caa9c5d3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a648ada94019a7b9cf1eda7858b96489e"><td class="memItemLeft" align="right" valign="top"><a id="a648ada94019a7b9cf1eda7858b96489e"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>CONF_CORE_GCLK_2_DIV_VAL</b>   1</td></tr>
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<tr class="separator:a648ada94019a7b9cf1eda7858b96489e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:abe952ac9fc21072d02bff9bc2ee8811e"><td class="memItemLeft" align="right" valign="top"><a id="abe952ac9fc21072d02bff9bc2ee8811e"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>CONF_CORE_GCLK_2_DIVSEL</b>   0</td></tr>
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<tr class="separator:abe952ac9fc21072d02bff9bc2ee8811e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a7860471b5a86c901ffab0022aa68508d"><td class="memItemLeft" align="right" valign="top"><a id="a7860471b5a86c901ffab0022aa68508d"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>CONF_CORE_GCLK_2_OUTPUT_ENABLE</b>   0</td></tr>
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<tr class="separator:a7860471b5a86c901ffab0022aa68508d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aa0034247e1d641ba67e703c539038ff4"><td class="memItemLeft" align="right" valign="top"><a id="aa0034247e1d641ba67e703c539038ff4"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>CONF_CORE_GCLK_2_OUTPUT_OFF_VALUE</b>   0</td></tr>
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<tr class="separator:aa0034247e1d641ba67e703c539038ff4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a1c2d6f8a76f2561e5bd74ddb640e30e3"><td class="memItemLeft" align="right" valign="top"><a id="a1c2d6f8a76f2561e5bd74ddb640e30e3"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>CONF_CORE_GCLK_2_IDC</b>   0</td></tr>
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<tr class="separator:a1c2d6f8a76f2561e5bd74ddb640e30e3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a8b37fb187198a9f784562cf97cc5fb86"><td class="memItemLeft" align="right" valign="top"><a id="a8b37fb187198a9f784562cf97cc5fb86"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>CONF_CORE_GCLK_3_ENABLE</b>   1</td></tr>
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<tr class="separator:a8b37fb187198a9f784562cf97cc5fb86"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a5d5810e2f03156f584a3cfc74dce6a80"><td class="memItemLeft" align="right" valign="top"><a id="a5d5810e2f03156f584a3cfc74dce6a80"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>CONF_CORE_GCLK_3_RUN_IN_STANDBY</b>   0</td></tr>
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<tr class="separator:a5d5810e2f03156f584a3cfc74dce6a80"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:af819c0dfb85cbfaf670f1f3c5f7ca599"><td class="memItemLeft" align="right" valign="top"><a id="af819c0dfb85cbfaf670f1f3c5f7ca599"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>CONF_CORE_GCLK_3_CLOCK_SOURCE</b>   GCLK_GENCTRL_SRC_XOSC32K</td></tr>
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<tr class="separator:af819c0dfb85cbfaf670f1f3c5f7ca599"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a4867cc4b465eb7ab5a55e6147a898d49"><td class="memItemLeft" align="right" valign="top"><a id="a4867cc4b465eb7ab5a55e6147a898d49"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>CONF_CORE_GCLK_3_DIV_VAL</b>   1</td></tr>
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<tr class="separator:a4867cc4b465eb7ab5a55e6147a898d49"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a81c4f743e2921601f8983a23c73ca542"><td class="memItemLeft" align="right" valign="top"><a id="a81c4f743e2921601f8983a23c73ca542"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>CONF_CORE_GCLK_3_DIVSEL</b>   0</td></tr>
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<tr class="separator:a81c4f743e2921601f8983a23c73ca542"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a71c7f3af2d2424a4aaaa95dc688ef346"><td class="memItemLeft" align="right" valign="top"><a id="a71c7f3af2d2424a4aaaa95dc688ef346"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>CONF_CORE_GCLK_3_OUTPUT_ENABLE</b>   0</td></tr>
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<tr class="separator:a71c7f3af2d2424a4aaaa95dc688ef346"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ab4a1a2ff24b72346826ca8f7977a241e"><td class="memItemLeft" align="right" valign="top"><a id="ab4a1a2ff24b72346826ca8f7977a241e"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>CONF_CORE_GCLK_3_OUTPUT_OFF_VALUE</b>   0</td></tr>
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<tr class="separator:ab4a1a2ff24b72346826ca8f7977a241e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:af74509cca20395024395b5038e55381e"><td class="memItemLeft" align="right" valign="top"><a id="af74509cca20395024395b5038e55381e"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>CONF_CORE_GCLK_3_IDC</b>   0</td></tr>
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<tr class="separator:af74509cca20395024395b5038e55381e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:acdc4a5166c8ece69d0ea638f2ead27fe"><td class="memItemLeft" align="right" valign="top"><a id="acdc4a5166c8ece69d0ea638f2ead27fe"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>CONF_CORE_GCLK_4_ENABLE</b>   0</td></tr>
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<tr class="separator:acdc4a5166c8ece69d0ea638f2ead27fe"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a0231ddce59c662379960060ed9b7a369"><td class="memItemLeft" align="right" valign="top"><a id="a0231ddce59c662379960060ed9b7a369"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>CONF_CORE_GCLK_4_RUN_IN_STANDBY</b>   0</td></tr>
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<tr class="separator:a0231ddce59c662379960060ed9b7a369"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a039d8f33779d89aa82dbae18d60b8a07"><td class="memItemLeft" align="right" valign="top"><a id="a039d8f33779d89aa82dbae18d60b8a07"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>CONF_CORE_GCLK_4_CLOCK_SOURCE</b>   GCLK_GENCTRL_SRC_XOSC0</td></tr>
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<tr class="separator:a039d8f33779d89aa82dbae18d60b8a07"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:abc1dc6107525b5807953811577c8aa87"><td class="memItemLeft" align="right" valign="top"><a id="abc1dc6107525b5807953811577c8aa87"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>CONF_CORE_GCLK_4_DIV_VAL</b>   1</td></tr>
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<tr class="separator:abc1dc6107525b5807953811577c8aa87"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a2bf161a2f7f14380cb5ad75b1246fd32"><td class="memItemLeft" align="right" valign="top"><a id="a2bf161a2f7f14380cb5ad75b1246fd32"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>CONF_CORE_GCLK_4_DIVSEL</b>   1</td></tr>
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<tr class="separator:a2bf161a2f7f14380cb5ad75b1246fd32"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ade70e6596f04be8b65992a5a418acac7"><td class="memItemLeft" align="right" valign="top"><a id="ade70e6596f04be8b65992a5a418acac7"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>CONF_CORE_GCLK_4_OUTPUT_ENABLE</b>   0</td></tr>
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<tr class="separator:ade70e6596f04be8b65992a5a418acac7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a8f6e5da9bfb7222db73befe43fac1a49"><td class="memItemLeft" align="right" valign="top"><a id="a8f6e5da9bfb7222db73befe43fac1a49"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>CONF_CORE_GCLK_4_OUTPUT_OFF_VALUE</b>   0</td></tr>
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<tr class="separator:a8f6e5da9bfb7222db73befe43fac1a49"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a2f782b52f7658f9ef32e84a74f48c9ab"><td class="memItemLeft" align="right" valign="top"><a id="a2f782b52f7658f9ef32e84a74f48c9ab"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>CONF_CORE_GCLK_4_IDC</b>   0</td></tr>
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<tr class="separator:a2f782b52f7658f9ef32e84a74f48c9ab"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a4d203327fee818fa6b0e3b8743ebb67f"><td class="memItemLeft" align="right" valign="top"><a id="a4d203327fee818fa6b0e3b8743ebb67f"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>CONF_CORE_GCLK_5_ENABLE</b>   0</td></tr>
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<tr class="separator:a4d203327fee818fa6b0e3b8743ebb67f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a87de7d100864fda4540ff555fda9c018"><td class="memItemLeft" align="right" valign="top"><a id="a87de7d100864fda4540ff555fda9c018"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>CONF_CORE_GCLK_5_RUN_IN_STANDBY</b>   0</td></tr>
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<tr class="separator:a87de7d100864fda4540ff555fda9c018"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aeeae865bcdff91234ae577f07ccd4d4c"><td class="memItemLeft" align="right" valign="top"><a id="aeeae865bcdff91234ae577f07ccd4d4c"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>CONF_CORE_GCLK_5_CLOCK_SOURCE</b>   GCLK_GENCTRL_SRC_XOSC0</td></tr>
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<tr class="separator:aeeae865bcdff91234ae577f07ccd4d4c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ac1e32d8e3867a596316d0f8a42426567"><td class="memItemLeft" align="right" valign="top"><a id="ac1e32d8e3867a596316d0f8a42426567"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>CONF_CORE_GCLK_5_DIV_VAL</b>   1</td></tr>
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<tr class="separator:ac1e32d8e3867a596316d0f8a42426567"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a77d7091d371ae0615b061c0d13a12cbc"><td class="memItemLeft" align="right" valign="top"><a id="a77d7091d371ae0615b061c0d13a12cbc"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>CONF_CORE_GCLK_5_DIVSEL</b>   0</td></tr>
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<tr class="separator:a77d7091d371ae0615b061c0d13a12cbc"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a96c8781dd896c47a6f4b608d70b7b835"><td class="memItemLeft" align="right" valign="top"><a id="a96c8781dd896c47a6f4b608d70b7b835"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>CONF_CORE_GCLK_5_OUTPUT_ENABLE</b>   0</td></tr>
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<tr class="separator:a96c8781dd896c47a6f4b608d70b7b835"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a060444d50d30a898b2b54052901369d0"><td class="memItemLeft" align="right" valign="top"><a id="a060444d50d30a898b2b54052901369d0"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>CONF_CORE_GCLK_5_OUTPUT_OFF_VALUE</b>   0</td></tr>
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<tr class="separator:a060444d50d30a898b2b54052901369d0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a141a12a1ae0047e42b7b05a7798a68ba"><td class="memItemLeft" align="right" valign="top"><a id="a141a12a1ae0047e42b7b05a7798a68ba"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>CONF_CORE_GCLK_5_IDC</b>   0</td></tr>
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<tr class="separator:a141a12a1ae0047e42b7b05a7798a68ba"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a9d3944cbd45124b8f2b382454d327ea6"><td class="memItemLeft" align="right" valign="top"><a id="a9d3944cbd45124b8f2b382454d327ea6"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>CONF_CORE_GCLK_6_ENABLE</b>   0</td></tr>
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<tr class="separator:a9d3944cbd45124b8f2b382454d327ea6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ac8c62af469ef470bf75f74bc0c4d812d"><td class="memItemLeft" align="right" valign="top"><a id="ac8c62af469ef470bf75f74bc0c4d812d"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>CONF_CORE_GCLK_6_RUN_IN_STANDBY</b>   0</td></tr>
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<tr class="separator:ac8c62af469ef470bf75f74bc0c4d812d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a2a8164befe9456a03dab53948db981f5"><td class="memItemLeft" align="right" valign="top"><a id="a2a8164befe9456a03dab53948db981f5"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>CONF_CORE_GCLK_6_CLOCK_SOURCE</b>   GCLK_GENCTRL_SRC_XOSC0</td></tr>
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<tr class="separator:a2a8164befe9456a03dab53948db981f5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a8bb853dfce647b4c6fffff289f271649"><td class="memItemLeft" align="right" valign="top"><a id="a8bb853dfce647b4c6fffff289f271649"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>CONF_CORE_GCLK_6_DIV_VAL</b>   1</td></tr>
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<tr class="separator:a8bb853dfce647b4c6fffff289f271649"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a9b7d8cf9cb680b5625263f950b19a7eb"><td class="memItemLeft" align="right" valign="top"><a id="a9b7d8cf9cb680b5625263f950b19a7eb"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>CONF_CORE_GCLK_6_DIVSEL</b>   0</td></tr>
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<tr class="separator:a9b7d8cf9cb680b5625263f950b19a7eb"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a52623c0b5125b29049ff2f873435d863"><td class="memItemLeft" align="right" valign="top"><a id="a52623c0b5125b29049ff2f873435d863"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>CONF_CORE_GCLK_6_OUTPUT_ENABLE</b>   0</td></tr>
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<tr class="separator:a52623c0b5125b29049ff2f873435d863"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a348ccf99dad16cff9a098bf173124bba"><td class="memItemLeft" align="right" valign="top"><a id="a348ccf99dad16cff9a098bf173124bba"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>CONF_CORE_GCLK_6_OUTPUT_OFF_VALUE</b>   0</td></tr>
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<tr class="separator:a348ccf99dad16cff9a098bf173124bba"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:abe063829d53d7190c5bfe3e204655419"><td class="memItemLeft" align="right" valign="top"><a id="abe063829d53d7190c5bfe3e204655419"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>CONF_CORE_GCLK_6_IDC</b>   0</td></tr>
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<tr class="separator:abe063829d53d7190c5bfe3e204655419"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:abe08f7b1dfd886620cee30c5d3aed94c"><td class="memItemLeft" align="right" valign="top"><a id="abe08f7b1dfd886620cee30c5d3aed94c"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>CONF_CORE_GCLK_7_ENABLE</b>   0</td></tr>
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<tr class="separator:abe08f7b1dfd886620cee30c5d3aed94c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aec25fddceb6c49ac3b23ba32b9a10ad2"><td class="memItemLeft" align="right" valign="top"><a id="aec25fddceb6c49ac3b23ba32b9a10ad2"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>CONF_CORE_GCLK_7_RUN_IN_STANDBY</b>   0</td></tr>
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<tr class="separator:aec25fddceb6c49ac3b23ba32b9a10ad2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a31561940aa5d97b1e96eb8a7bb36c774"><td class="memItemLeft" align="right" valign="top"><a id="a31561940aa5d97b1e96eb8a7bb36c774"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>CONF_CORE_GCLK_7_CLOCK_SOURCE</b>   GCLK_GENCTRL_SRC_XOSC0</td></tr>
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<tr class="separator:a31561940aa5d97b1e96eb8a7bb36c774"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a6d9d0b00baa5e77d3edaae69978cbf93"><td class="memItemLeft" align="right" valign="top"><a id="a6d9d0b00baa5e77d3edaae69978cbf93"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>CONF_CORE_GCLK_7_DIV_VAL</b>   1</td></tr>
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<tr class="separator:a6d9d0b00baa5e77d3edaae69978cbf93"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:abf11131c5f334a989e9068709f73ea52"><td class="memItemLeft" align="right" valign="top"><a id="abf11131c5f334a989e9068709f73ea52"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>CONF_CORE_GCLK_7_DIVSEL</b>   0</td></tr>
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<tr class="separator:abf11131c5f334a989e9068709f73ea52"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a8f95dca168af124770fe26a0a13fb919"><td class="memItemLeft" align="right" valign="top"><a id="a8f95dca168af124770fe26a0a13fb919"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>CONF_CORE_GCLK_7_OUTPUT_ENABLE</b>   0</td></tr>
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<tr class="separator:a8f95dca168af124770fe26a0a13fb919"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a447c9d85f25f40a1f842aebae49f817b"><td class="memItemLeft" align="right" valign="top"><a id="a447c9d85f25f40a1f842aebae49f817b"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>CONF_CORE_GCLK_7_OUTPUT_OFF_VALUE</b>   0</td></tr>
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<tr class="separator:a447c9d85f25f40a1f842aebae49f817b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a581643e3531a10ea6177f2cc3ad22991"><td class="memItemLeft" align="right" valign="top"><a id="a581643e3531a10ea6177f2cc3ad22991"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>CONF_CORE_GCLK_7_IDC</b>   0</td></tr>
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<tr class="separator:a581643e3531a10ea6177f2cc3ad22991"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a1b5930361c483c5f525faa266229aa49"><td class="memItemLeft" align="right" valign="top"><a id="a1b5930361c483c5f525faa266229aa49"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>CONF_CORE_GCLK_8_ENABLE</b>   0</td></tr>
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<tr class="separator:a1b5930361c483c5f525faa266229aa49"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ae5025a1abf16f116c2d9c2972b210953"><td class="memItemLeft" align="right" valign="top"><a id="ae5025a1abf16f116c2d9c2972b210953"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>CONF_CORE_GCLK_8_RUN_IN_STANDBY</b>   0</td></tr>
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<tr class="separator:ae5025a1abf16f116c2d9c2972b210953"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a778d90218f23f60b6ba8ac66924bd6da"><td class="memItemLeft" align="right" valign="top"><a id="a778d90218f23f60b6ba8ac66924bd6da"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>CONF_CORE_GCLK_8_CLOCK_SOURCE</b>   GCLK_GENCTRL_SRC_XOSC0</td></tr>
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<tr class="separator:a778d90218f23f60b6ba8ac66924bd6da"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:afb8616e7031ac9cdce7528f9fb5d81ae"><td class="memItemLeft" align="right" valign="top"><a id="afb8616e7031ac9cdce7528f9fb5d81ae"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>CONF_CORE_GCLK_8_DIV_VAL</b>   1</td></tr>
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<tr class="separator:afb8616e7031ac9cdce7528f9fb5d81ae"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a5ab2e88e62c2a49c996634882a1d3888"><td class="memItemLeft" align="right" valign="top"><a id="a5ab2e88e62c2a49c996634882a1d3888"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>CONF_CORE_GCLK_8_DIVSEL</b>   0</td></tr>
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<tr class="separator:a5ab2e88e62c2a49c996634882a1d3888"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a24999aca0c92cbc94b12a03d1057e99a"><td class="memItemLeft" align="right" valign="top"><a id="a24999aca0c92cbc94b12a03d1057e99a"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>CONF_CORE_GCLK_8_OUTPUT_ENABLE</b>   0</td></tr>
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<tr class="separator:a24999aca0c92cbc94b12a03d1057e99a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a44ce2d9ecf9c967a93e6ec6c7d0a13fb"><td class="memItemLeft" align="right" valign="top"><a id="a44ce2d9ecf9c967a93e6ec6c7d0a13fb"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>CONF_CORE_GCLK_8_OUTPUT_OFF_VALUE</b>   0</td></tr>
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<tr class="separator:a44ce2d9ecf9c967a93e6ec6c7d0a13fb"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a745a2c905f215f02909859dfc840f7ae"><td class="memItemLeft" align="right" valign="top"><a id="a745a2c905f215f02909859dfc840f7ae"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>CONF_CORE_GCLK_8_IDC</b>   0</td></tr>
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<tr class="separator:a745a2c905f215f02909859dfc840f7ae"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aedaac2b9ad4241c252288a049f9d5e97"><td class="memItemLeft" align="right" valign="top"><a id="aedaac2b9ad4241c252288a049f9d5e97"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>CONF_CORE_GCLK_9_ENABLE</b>   0</td></tr>
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<tr class="separator:aedaac2b9ad4241c252288a049f9d5e97"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a25477b98ee7a48725d2702f4925138b1"><td class="memItemLeft" align="right" valign="top"><a id="a25477b98ee7a48725d2702f4925138b1"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>CONF_CORE_GCLK_9_RUN_IN_STANDBY</b>   0</td></tr>
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<tr class="separator:a25477b98ee7a48725d2702f4925138b1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a1c08dc8f723d13b8f8481525bf98316c"><td class="memItemLeft" align="right" valign="top"><a id="a1c08dc8f723d13b8f8481525bf98316c"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>CONF_CORE_GCLK_9_CLOCK_SOURCE</b>   GCLK_GENCTRL_SRC_XOSC0</td></tr>
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<tr class="separator:a1c08dc8f723d13b8f8481525bf98316c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a9172510253cf26ab1df5f0bb29dff5a9"><td class="memItemLeft" align="right" valign="top"><a id="a9172510253cf26ab1df5f0bb29dff5a9"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>CONF_CORE_GCLK_9_DIV_VAL</b>   1</td></tr>
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#define </td><td class="memItemRight" valign="bottom"><b>CONF_CORE_GCLK_9_DIVSEL</b>   0</td></tr>
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#define </td><td class="memItemRight" valign="bottom"><b>CONF_CORE_GCLK_9_OUTPUT_ENABLE</b>   0</td></tr>
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#define </td><td class="memItemRight" valign="bottom"><b>CONF_CORE_GCLK_9_OUTPUT_OFF_VALUE</b>   0</td></tr>
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#define </td><td class="memItemRight" valign="bottom"><b>CONF_CORE_GCLK_9_IDC</b>   0</td></tr>
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#define </td><td class="memItemRight" valign="bottom"><b>CONF_CORE_GCLK_10_ENABLE</b>   0</td></tr>
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#define </td><td class="memItemRight" valign="bottom"><b>CONF_CORE_GCLK_10_RUN_IN_STANDBY</b>   0</td></tr>
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#define </td><td class="memItemRight" valign="bottom"><b>CONF_CORE_GCLK_10_CLOCK_SOURCE</b>   GCLK_GENCTRL_SRC_XOSC0</td></tr>
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#define </td><td class="memItemRight" valign="bottom"><b>CONF_CORE_GCLK_10_DIV_VAL</b>   1</td></tr>
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#define </td><td class="memItemRight" valign="bottom"><b>CONF_CORE_GCLK_10_DIVSEL</b>   0</td></tr>
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#define </td><td class="memItemRight" valign="bottom"><b>CONF_CORE_GCLK_10_OUTPUT_ENABLE</b>   0</td></tr>
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#define </td><td class="memItemRight" valign="bottom"><b>CONF_CORE_GCLK_10_OUTPUT_OFF_VALUE</b>   0</td></tr>
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#define </td><td class="memItemRight" valign="bottom"><b>CONF_CORE_GCLK_10_IDC</b>   0</td></tr>
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#define </td><td class="memItemRight" valign="bottom"><b>CONF_CORE_GCLK_11_ENABLE</b>   0</td></tr>
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#define </td><td class="memItemRight" valign="bottom"><b>CONF_CORE_GCLK_11_RUN_IN_STANDBY</b>   0</td></tr>
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#define </td><td class="memItemRight" valign="bottom"><b>CONF_CORE_GCLK_11_CLOCK_SOURCE</b>   GCLK_GENCTRL_SRC_XOSC0</td></tr>
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#define </td><td class="memItemRight" valign="bottom"><b>CONF_CORE_GCLK_11_DIV_VAL</b>   1</td></tr>
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#define </td><td class="memItemRight" valign="bottom"><b>CONF_CORE_GCLK_11_DIVSEL</b>   0</td></tr>
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#define </td><td class="memItemRight" valign="bottom"><b>CONF_CORE_GCLK_11_OUTPUT_ENABLE</b>   0</td></tr>
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#define </td><td class="memItemRight" valign="bottom"><b>CONF_CORE_GCLK_11_OUTPUT_OFF_VALUE</b>   0</td></tr>
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#define </td><td class="memItemRight" valign="bottom"><b>CONF_CORE_GCLK_11_IDC</b>   0</td></tr>
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<tr><td colspan="2"><div class="groupHeader">Core-Master-Clock-Configuration</div></td></tr>
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<tr><td colspan="2"><div class="groupText"><p>Configuration options for the master clock. </p>
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</div></td></tr>
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<tr class="memitem:ab46aa120e454ecf957efa4bd97be5bdf"><td class="memItemLeft" align="right" valign="top"><a id="ab46aa120e454ecf957efa4bd97be5bdf"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="conf__core_8h.html#ab46aa120e454ecf957efa4bd97be5bdf">CONF_CORE_MCLK_NVM_WAIT_STATE</a>   0x5</td></tr>
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<tr class="memdesc:ab46aa120e454ecf957efa4bd97be5bdf"><td class="mdescLeft"> </td><td class="mdescRight">Define the number of wait states for the master clock. <br />
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<a class="el" href="structCan.html" title="CAN APB hardware registers.">Can</a> be [0-15]. <br />
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See <a href="https://ww1.microchip.com/downloads/en/DeviceDoc/SAM_D5xE5x_Family_Data_Sheet_DS60001507F.pdf#page=605">Datasheet Reference</a> <br /></td></tr>
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<tr class="memitem:aa9643e96439d0d47e0684a4b11c1f529"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="conf__core_8h.html#aa9643e96439d0d47e0684a4b11c1f529">CONF_CORE_MCLK_CPUDIV</a>   0x1</td></tr>
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<tr class="memdesc:aa9643e96439d0d47e0684a4b11c1f529"><td class="mdescLeft"> </td><td class="mdescRight">Define the master clock divisor. <a href="conf__core_8h.html#aa9643e96439d0d47e0684a4b11c1f529">More...</a><br /></td></tr>
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<tr class="separator:aa9643e96439d0d47e0684a4b11c1f529"><td class="memSeparator" colspan="2"> </td></tr>
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<tr><td colspan="2"><div class="groupHeader">Core-XOSC0-Configuration</div></td></tr>
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<tr><td colspan="2"><div class="groupText"><p>Configuration options for XOSC0. <br />
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See <a href="https://ww1.microchip.com/downloads/en/DeviceDoc/SAM_D5xE5x_Family_Data_Sheet_DS60001507F.pdf#page=693">Datasheet Reference</a> </p>
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</div></td></tr>
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<tr class="memitem:a61559adc856ce1dcfa046e749af63bc3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="conf__core_8h.html#a61559adc856ce1dcfa046e749af63bc3">CONF_CORE_CLK_XOSC0_ENABLE</a>   (1)</td></tr>
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<tr class="memdesc:a61559adc856ce1dcfa046e749af63bc3"><td class="mdescLeft"> </td><td class="mdescRight">Enables or Disables the XOSC0 Clock. <a href="conf__core_8h.html#a61559adc856ce1dcfa046e749af63bc3">More...</a><br /></td></tr>
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<tr class="separator:a61559adc856ce1dcfa046e749af63bc3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ac2ca0e9037347eb69d53a0011f989910"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="conf__core_8h.html#ac2ca0e9037347eb69d53a0011f989910">CONF_CORE_CLK_XOSC0_XTALEN</a>   (1)</td></tr>
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<tr class="memdesc:ac2ca0e9037347eb69d53a0011f989910"><td class="mdescLeft"> </td><td class="mdescRight">This bit controls the connections between the I/O pads and the external clock or crystal oscillator XOSC0: <a href="conf__core_8h.html#ac2ca0e9037347eb69d53a0011f989910">More...</a><br /></td></tr>
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<tr class="separator:ac2ca0e9037347eb69d53a0011f989910"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:afac0686157854cc021424410ded071f1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="conf__core_8h.html#afac0686157854cc021424410ded071f1">CONF_CORE_CLK_XOSC0_RUNSTDBY</a>   (0)</td></tr>
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<tr class="memdesc:afac0686157854cc021424410ded071f1"><td class="mdescLeft"> </td><td class="mdescRight">This bit controls how the XOSC0 behaves during standby sleep mode: <a href="conf__core_8h.html#afac0686157854cc021424410ded071f1">More...</a><br /></td></tr>
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<tr class="separator:afac0686157854cc021424410ded071f1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a5ffaa1551b7ffb8a342b2cc5fbc5950c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="conf__core_8h.html#a5ffaa1551b7ffb8a342b2cc5fbc5950c">CONF_CORE_CLK_XOSC0_ONDEMAND</a>   (0)</td></tr>
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<tr class="memdesc:a5ffaa1551b7ffb8a342b2cc5fbc5950c"><td class="mdescLeft"> </td><td class="mdescRight">The On Demand operation mode allows the oscillator XOSC0 to be enabled or disabled, depending on peripheral clock requests. <a href="conf__core_8h.html#a5ffaa1551b7ffb8a342b2cc5fbc5950c">More...</a><br /></td></tr>
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<tr class="separator:a5ffaa1551b7ffb8a342b2cc5fbc5950c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aeea7b0d3663bb6d5ccc3218017f9a05b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="conf__core_8h.html#aeea7b0d3663bb6d5ccc3218017f9a05b">CONF_CORE_CLK_XOSC0_LOWBUFGAIN</a>   (0)</td></tr>
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<tr class="memdesc:aeea7b0d3663bb6d5ccc3218017f9a05b"><td class="mdescLeft"> </td><td class="mdescRight">The default value of LOWBUFGAIN=0 should be used to allow operating with a low amplitude oscillator. Don't use this setting except to solve stability issues. <a href="conf__core_8h.html#aeea7b0d3663bb6d5ccc3218017f9a05b">More...</a><br /></td></tr>
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<tr class="separator:aeea7b0d3663bb6d5ccc3218017f9a05b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a2683d3721ab44a85e60cfff0d0cbf96e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="conf__core_8h.html#a2683d3721ab44a85e60cfff0d0cbf96e">CONF_CORE_CLK_XOSC0_ENALC</a>   (1)</td></tr>
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<tr class="memdesc:a2683d3721ab44a85e60cfff0d0cbf96e"><td class="mdescLeft"> </td><td class="mdescRight">This bit controls the XOSC0 automatic loop control: <a href="conf__core_8h.html#a2683d3721ab44a85e60cfff0d0cbf96e">More...</a><br /></td></tr>
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<tr class="separator:a2683d3721ab44a85e60cfff0d0cbf96e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a17cd20bb954bc137251cf7fb63889151"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="conf__core_8h.html#a17cd20bb954bc137251cf7fb63889151">CONF_CORE_CLK_XOSC0_CFDEN</a>   (1)</td></tr>
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<tr class="memdesc:a17cd20bb954bc137251cf7fb63889151"><td class="mdescLeft"> </td><td class="mdescRight">This bit controls the XOSC0 clock failure detector: <a href="conf__core_8h.html#a17cd20bb954bc137251cf7fb63889151">More...</a><br /></td></tr>
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<tr class="separator:a17cd20bb954bc137251cf7fb63889151"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:abe235b3b13f253acb855d15c8f33c95a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="conf__core_8h.html#abe235b3b13f253acb855d15c8f33c95a">CONF_CORE_CLK_XOSC0_SWBEN</a>   (0)</td></tr>
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<tr class="memdesc:abe235b3b13f253acb855d15c8f33c95a"><td class="mdescLeft"> </td><td class="mdescRight">This bit controls the XOSC0 output clock switch back to the external clock or crystal oscillator in case of clock recovery: <a href="conf__core_8h.html#abe235b3b13f253acb855d15c8f33c95a">More...</a><br /></td></tr>
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<tr class="separator:abe235b3b13f253acb855d15c8f33c95a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:affc8201cf2340d2236ba9ca44a1e657c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="conf__core_8h.html#affc8201cf2340d2236ba9ca44a1e657c">CONF_CORE_CLK_XOSC0_STARTUP_TIME</a>   (0x00)</td></tr>
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<tr class="memdesc:affc8201cf2340d2236ba9ca44a1e657c"><td class="mdescLeft"> </td><td class="mdescRight">These bits select start-up time for XOSC0 according to the table below: <a href="conf__core_8h.html#affc8201cf2340d2236ba9ca44a1e657c">More...</a><br /></td></tr>
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<tr class="separator:affc8201cf2340d2236ba9ca44a1e657c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:af6ec0afa1da472db5f1def1d1923faad"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="conf__core_8h.html#af6ec0afa1da472db5f1def1d1923faad">CONF_CORE_CLK_XOSC0_FREQUENCY</a>   12000000</td></tr>
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<tr class="memdesc:af6ec0afa1da472db5f1def1d1923faad"><td class="mdescLeft"> </td><td class="mdescRight">This is the frequency of the external clock you're using for XOSC0. This can be anything from 8MHz to 48MHz. <a href="conf__core_8h.html#af6ec0afa1da472db5f1def1d1923faad">More...</a><br /></td></tr>
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<tr class="separator:af6ec0afa1da472db5f1def1d1923faad"><td class="memSeparator" colspan="2"> </td></tr>
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<tr><td colspan="2"><div class="groupHeader">Core-XOSC1-Configuration</div></td></tr>
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<tr><td colspan="2"><div class="groupText"><p>Configuration options for XOSC1. <br />
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See <a href="https://ww1.microchip.com/downloads/en/DeviceDoc/SAM_D5xE5x_Family_Data_Sheet_DS60001507F.pdf#page=693">Datasheet Reference</a> </p>
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</div></td></tr>
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<tr class="memitem:aa54465cc56631333a22ae84ab66d5f3a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="conf__core_8h.html#aa54465cc56631333a22ae84ab66d5f3a">CONF_CORE_CLK_XOSC1_ENABLE</a>   (0)</td></tr>
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<tr class="memdesc:aa54465cc56631333a22ae84ab66d5f3a"><td class="mdescLeft"> </td><td class="mdescRight">Enables or Disables the XOSC1 Clock. <a href="conf__core_8h.html#aa54465cc56631333a22ae84ab66d5f3a">More...</a><br /></td></tr>
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<tr class="separator:aa54465cc56631333a22ae84ab66d5f3a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ae3f8741e2be4b37a46dfb49af2c2a09d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="conf__core_8h.html#ae3f8741e2be4b37a46dfb49af2c2a09d">CONF_CORE_CLK_XOSC1_XTALEN</a>   (0)</td></tr>
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<tr class="memdesc:ae3f8741e2be4b37a46dfb49af2c2a09d"><td class="mdescLeft"> </td><td class="mdescRight">This bit controls the connections between the I/O pads and the external clock or crystal oscillator XOSC1: <a href="conf__core_8h.html#ae3f8741e2be4b37a46dfb49af2c2a09d">More...</a><br /></td></tr>
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<tr class="separator:ae3f8741e2be4b37a46dfb49af2c2a09d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a8bec34fdc01ac38ec0c2d13112f28aa0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="conf__core_8h.html#a8bec34fdc01ac38ec0c2d13112f28aa0">CONF_CORE_CLK_XOSC1_RUNSTDBY</a>   (0)</td></tr>
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<tr class="memdesc:a8bec34fdc01ac38ec0c2d13112f28aa0"><td class="mdescLeft"> </td><td class="mdescRight">This bit controls how the XOSC1 behaves during standby sleep mode: <a href="conf__core_8h.html#a8bec34fdc01ac38ec0c2d13112f28aa0">More...</a><br /></td></tr>
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<tr class="separator:a8bec34fdc01ac38ec0c2d13112f28aa0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aaf561ace0fee1e373536a251ce8a9726"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="conf__core_8h.html#aaf561ace0fee1e373536a251ce8a9726">CONF_CORE_CLK_XOSC1_ONDEMAND</a>   (0)</td></tr>
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<tr class="memdesc:aaf561ace0fee1e373536a251ce8a9726"><td class="mdescLeft"> </td><td class="mdescRight">The On Demand operation mode allows the oscillator XOSC1 to be enabled or disabled, depending on peripheral clock requests. <a href="conf__core_8h.html#aaf561ace0fee1e373536a251ce8a9726">More...</a><br /></td></tr>
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<tr class="separator:aaf561ace0fee1e373536a251ce8a9726"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a985ebd23986d9411d3602040e33bb405"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="conf__core_8h.html#a985ebd23986d9411d3602040e33bb405">CONF_CORE_CLK_XOSC1_LOWBUFGAIN</a>   (0)</td></tr>
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<tr class="memdesc:a985ebd23986d9411d3602040e33bb405"><td class="mdescLeft"> </td><td class="mdescRight">The default value of LOWBUFGAIN=0 should be used to allow operating with a low amplitude oscillator. Don't use this setting except to solve stability issues. <a href="conf__core_8h.html#a985ebd23986d9411d3602040e33bb405">More...</a><br /></td></tr>
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<tr class="separator:a985ebd23986d9411d3602040e33bb405"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a3a42de5c6251540e7b8c000974acfc62"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="conf__core_8h.html#a3a42de5c6251540e7b8c000974acfc62">CONF_CORE_CLK_XOSC1_ENALC</a>   (0)</td></tr>
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<tr class="memdesc:a3a42de5c6251540e7b8c000974acfc62"><td class="mdescLeft"> </td><td class="mdescRight">This bit controls the XOSC1 automatic loop control: <a href="conf__core_8h.html#a3a42de5c6251540e7b8c000974acfc62">More...</a><br /></td></tr>
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<tr class="separator:a3a42de5c6251540e7b8c000974acfc62"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a924214b0f469bde71ff28fe5544466db"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="conf__core_8h.html#a924214b0f469bde71ff28fe5544466db">CONF_CORE_CLK_XOSC1_CFDEN</a>   (0)</td></tr>
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<tr class="memdesc:a924214b0f469bde71ff28fe5544466db"><td class="mdescLeft"> </td><td class="mdescRight">This bit controls the XOSC1 clock failure detector: <a href="conf__core_8h.html#a924214b0f469bde71ff28fe5544466db">More...</a><br /></td></tr>
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<tr class="separator:a924214b0f469bde71ff28fe5544466db"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a590b1e68a3f666bdea576a32f4e74ba0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="conf__core_8h.html#a590b1e68a3f666bdea576a32f4e74ba0">CONF_CORE_CLK_XOSC1_SWBEN</a>   (0)</td></tr>
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<tr class="memdesc:a590b1e68a3f666bdea576a32f4e74ba0"><td class="mdescLeft"> </td><td class="mdescRight">This bit controls the XOSC1 output clock switch back to the external clock or crystal oscillator in case of clock recovery: <a href="conf__core_8h.html#a590b1e68a3f666bdea576a32f4e74ba0">More...</a><br /></td></tr>
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<tr class="separator:a590b1e68a3f666bdea576a32f4e74ba0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ae8d2fdac3b52964174863149986db625"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="conf__core_8h.html#ae8d2fdac3b52964174863149986db625">CONF_CORE_CLK_XOSC1_STARTUP_TIME</a>   (0x00)</td></tr>
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<tr class="memdesc:ae8d2fdac3b52964174863149986db625"><td class="mdescLeft"> </td><td class="mdescRight">These bits select start-up time for XOSC1 according to the table below: <a href="conf__core_8h.html#ae8d2fdac3b52964174863149986db625">More...</a><br /></td></tr>
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<tr class="separator:ae8d2fdac3b52964174863149986db625"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a3fc3ea49b9d78438e5a8c19a22849469"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="conf__core_8h.html#a3fc3ea49b9d78438e5a8c19a22849469">CONF_CORE_CLK_XOSC1_FREQUENCY</a>   12000000</td></tr>
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<tr class="memdesc:a3fc3ea49b9d78438e5a8c19a22849469"><td class="mdescLeft"> </td><td class="mdescRight">This is the frequency of the external clock you're using for XOSC1. This can be anything from 8MHz to 48MHz. <a href="conf__core_8h.html#a3fc3ea49b9d78438e5a8c19a22849469">More...</a><br /></td></tr>
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<tr class="separator:a3fc3ea49b9d78438e5a8c19a22849469"><td class="memSeparator" colspan="2"> </td></tr>
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<tr><td colspan="2"><div class="groupHeader">Core-XOSC32K-Configuration</div></td></tr>
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<tr><td colspan="2"><div class="groupText"><p>Configuration options for the external 32khz oscillator. <br />
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See <a href="https://ww1.microchip.com/downloads/en/DeviceDoc/SAM_D5xE5x_Family_Data_Sheet_DS60001507F.pdf#page=735">Datasheet Reference</a> </p>
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</div></td></tr>
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<tr class="memitem:accf341cf268c0883a3d862b98667bc9c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="conf__core_8h.html#accf341cf268c0883a3d862b98667bc9c">CONF_CORE_CLK_XOSC32K_ENABLE</a>   (1)</td></tr>
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<tr class="memdesc:accf341cf268c0883a3d862b98667bc9c"><td class="mdescLeft"> </td><td class="mdescRight">Enables or Disables XOSC32K. <a href="conf__core_8h.html#accf341cf268c0883a3d862b98667bc9c">More...</a><br /></td></tr>
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<tr class="separator:accf341cf268c0883a3d862b98667bc9c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a031a77340c697036538d218724837de1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="conf__core_8h.html#a031a77340c697036538d218724837de1">CONF_CORE_CLK_XOSC32K_CGM</a>   (0x01)</td></tr>
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<tr class="memdesc:a031a77340c697036538d218724837de1"><td class="mdescLeft"> </td><td class="mdescRight">These bits control the gain of the external crstal oscillator. <a href="conf__core_8h.html#a031a77340c697036538d218724837de1">More...</a><br /></td></tr>
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<tr class="separator:a031a77340c697036538d218724837de1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a314b78ee48f1ecf6c40f4bad7ef63d9d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="conf__core_8h.html#a314b78ee48f1ecf6c40f4bad7ef63d9d">CONF_CORE_CLK_XOSC32K_STARTUP_TIME</a>   CONF_CORE_CLK_XOSC32KCTRL_STARTUP_62592us</td></tr>
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<tr class="memdesc:a314b78ee48f1ecf6c40f4bad7ef63d9d"><td class="mdescLeft"> </td><td class="mdescRight">These bits select the startup time for the oscillator. <a href="conf__core_8h.html#a314b78ee48f1ecf6c40f4bad7ef63d9d">More...</a><br /></td></tr>
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<tr class="separator:a314b78ee48f1ecf6c40f4bad7ef63d9d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a8d70a30b50febec035af6b982daac395"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="conf__core_8h.html#a8d70a30b50febec035af6b982daac395">CONF_CORE_CLK_XOSC32K_ONDEMAND</a>   (1)</td></tr>
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<tr class="memdesc:a8d70a30b50febec035af6b982daac395"><td class="mdescLeft"> </td><td class="mdescRight">This bit controls how XOSC32K behaves when a peripheral clock request is detected. <a href="conf__core_8h.html#a8d70a30b50febec035af6b982daac395">More...</a><br /></td></tr>
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<tr class="separator:a8d70a30b50febec035af6b982daac395"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:adc7a2f161e9e8e54388b1f290066247e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="conf__core_8h.html#adc7a2f161e9e8e54388b1f290066247e">CONF_CORE_CLK_XOSC32K_RUNSTDBY</a>   (0)</td></tr>
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<tr class="memdesc:adc7a2f161e9e8e54388b1f290066247e"><td class="mdescLeft"> </td><td class="mdescRight">This bit controls how XOSC32K behaves during standby sleep mode. <a href="conf__core_8h.html#adc7a2f161e9e8e54388b1f290066247e">More...</a><br /></td></tr>
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<tr class="separator:adc7a2f161e9e8e54388b1f290066247e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a033f3571fb50a6ed02278d65ea84b45e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="conf__core_8h.html#a033f3571fb50a6ed02278d65ea84b45e">CONF_CORE_CLK_XOSC32K_EN1K</a>   (0)</td></tr>
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<tr class="separator:a033f3571fb50a6ed02278d65ea84b45e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ae9fbb8d05dc5808f510eae4e8a629826"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="conf__core_8h.html#ae9fbb8d05dc5808f510eae4e8a629826">CONF_CORE_CLK_XOSC32K_EN32K</a>   (1)</td></tr>
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<tr class="separator:ae9fbb8d05dc5808f510eae4e8a629826"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a6a65a6f4bf7e21dc2003b61a7045e24a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="conf__core_8h.html#a6a65a6f4bf7e21dc2003b61a7045e24a">CONF_CORE_CLK_XOSC32K_XTALEN</a>   (1)</td></tr>
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<tr class="memdesc:a6a65a6f4bf7e21dc2003b61a7045e24a"><td class="mdescLeft"> </td><td class="mdescRight">This bit controls the connections between the I/O pads and the external clock or crystal oscillator. <a href="conf__core_8h.html#a6a65a6f4bf7e21dc2003b61a7045e24a">More...</a><br /></td></tr>
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<tr class="separator:a6a65a6f4bf7e21dc2003b61a7045e24a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a79567f94a0f3ad2d628bcf5e1cff62d1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="conf__core_8h.html#a79567f94a0f3ad2d628bcf5e1cff62d1">CONF_CORE_CLK_XOSC32K_CFDPRESC</a>   (0)</td></tr>
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<tr class="memdesc:a79567f94a0f3ad2d628bcf5e1cff62d1"><td class="mdescLeft"> </td><td class="mdescRight">This bit selects the prescaler for the CLock Failure Detector: <a href="conf__core_8h.html#a79567f94a0f3ad2d628bcf5e1cff62d1">More...</a><br /></td></tr>
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<tr class="separator:a79567f94a0f3ad2d628bcf5e1cff62d1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a668d68edf9a7ac05be5b9cda247225ad"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="conf__core_8h.html#a668d68edf9a7ac05be5b9cda247225ad">CONF_CORE_CLK_XOSC32K_CFDEN</a>   (0)</td></tr>
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<tr class="memdesc:a668d68edf9a7ac05be5b9cda247225ad"><td class="mdescLeft"> </td><td class="mdescRight">This bit selects the Clock Failulre Detector state. <a href="conf__core_8h.html#a668d68edf9a7ac05be5b9cda247225ad">More...</a><br /></td></tr>
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<tr class="separator:a668d68edf9a7ac05be5b9cda247225ad"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ac6e671eee4ca4aeb9fcbb87d52b457b5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="conf__core_8h.html#ac6e671eee4ca4aeb9fcbb87d52b457b5">CONF_CORE_CLK_XOSC32K_SWBACK</a>   (0)</td></tr>
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<tr class="memdesc:ac6e671eee4ca4aeb9fcbb87d52b457b5"><td class="mdescLeft"> </td><td class="mdescRight">This bit controls the XOSC32K output switch back to the external clock or crystal oscillator in case of clock recovery. <a href="conf__core_8h.html#ac6e671eee4ca4aeb9fcbb87d52b457b5">More...</a><br /></td></tr>
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<tr class="separator:ac6e671eee4ca4aeb9fcbb87d52b457b5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a42b0270d2f3c0f51c4b3d2b8ac397fda"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="conf__core_8h.html#a42b0270d2f3c0f51c4b3d2b8ac397fda">CONF_CORE_CLK_XOSC32K_WRTLOCK</a>   (0)</td></tr>
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<tr class="memdesc:a42b0270d2f3c0f51c4b3d2b8ac397fda"><td class="mdescLeft"> </td><td class="mdescRight">This bit locks the XOSC32K register for future writes, effectively freezing the XOSC32K configuration. <a href="conf__core_8h.html#a42b0270d2f3c0f51c4b3d2b8ac397fda">More...</a><br /></td></tr>
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<tr class="separator:a42b0270d2f3c0f51c4b3d2b8ac397fda"><td class="memSeparator" colspan="2"> </td></tr>
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<tr><td colspan="2"><div class="groupHeader">Core-DFLL48M-Configuration</div></td></tr>
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<tr><td colspan="2"><div class="groupText"><p>Configuration options for DFLL48M </p>
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</div></td></tr>
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<tr class="memitem:a03160c4c7871685bbde0e96f02825842"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="conf__core_8h.html#a03160c4c7871685bbde0e96f02825842">CONF_CORE_CLK_DFLL_ENABLE</a>   (1)</td></tr>
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<tr class="memdesc:a03160c4c7871685bbde0e96f02825842"><td class="mdescLeft"> </td><td class="mdescRight">Enables or Disables the DFLL48M Clock. <a href="conf__core_8h.html#a03160c4c7871685bbde0e96f02825842">More...</a><br /></td></tr>
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<tr class="separator:a03160c4c7871685bbde0e96f02825842"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a55515b150245a993779a0d5f417cc828"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="conf__core_8h.html#a55515b150245a993779a0d5f417cc828">CONF_CORE_CLK_DFLL_ONDEMAND</a>   (0)</td></tr>
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<tr class="memdesc:a55515b150245a993779a0d5f417cc828"><td class="mdescLeft"> </td><td class="mdescRight">Enables or Disables on-demand operation. <a href="conf__core_8h.html#a55515b150245a993779a0d5f417cc828">More...</a><br /></td></tr>
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<tr class="separator:a55515b150245a993779a0d5f417cc828"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ab6b320dcf67ec88f534adcbf77e2ce7b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="conf__core_8h.html#ab6b320dcf67ec88f534adcbf77e2ce7b">CONF_CORE_CLK_DFLL_RUNSTDBY</a>   (0)</td></tr>
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<tr class="memdesc:ab6b320dcf67ec88f534adcbf77e2ce7b"><td class="mdescLeft"> </td><td class="mdescRight">Enables or Disables run-in-standby operation. <a href="conf__core_8h.html#ab6b320dcf67ec88f534adcbf77e2ce7b">More...</a><br /></td></tr>
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<tr class="separator:ab6b320dcf67ec88f534adcbf77e2ce7b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a1f088d6654bb907ff388ced455b2dbb2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="conf__core_8h.html#a1f088d6654bb907ff388ced455b2dbb2">CONF_CORE_CLK_DFLL_WAITLOCK</a>   (0)</td></tr>
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<tr class="memdesc:a1f088d6654bb907ff388ced455b2dbb2"><td class="mdescLeft"> </td><td class="mdescRight">This bit controls the DFLL output clock, depending on the lock status: <a href="conf__core_8h.html#a1f088d6654bb907ff388ced455b2dbb2">More...</a><br /></td></tr>
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<tr class="separator:a1f088d6654bb907ff388ced455b2dbb2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a5c4e5f19e855fba0042ae119ce1be273"><td class="memItemLeft" align="right" valign="top"><a id="a5c4e5f19e855fba0042ae119ce1be273"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>CONF_CORE_CLK_DFLL_BPLKC</b>   (0)</td></tr>
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<tr class="memitem:a09e3dee90c8d6a09b50e78a21d5ad7a5"><td class="memItemLeft" align="right" valign="top"><a id="a09e3dee90c8d6a09b50e78a21d5ad7a5"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>CONF_CORE_CLK_DFLL_QLDIS</b>   (0)</td></tr>
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<tr class="memitem:ae74d5c634b10eef6a79e7e55fbb2cf07"><td class="memItemLeft" align="right" valign="top"><a id="ae74d5c634b10eef6a79e7e55fbb2cf07"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>CONF_CORE_CLK_DFLL_CCDIS</b>   (1)</td></tr>
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<tr class="memitem:a74344d95253ee83ec8feed88bf1ffdd5"><td class="memItemLeft" align="right" valign="top"><a id="a74344d95253ee83ec8feed88bf1ffdd5"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>CONF_CORE_CLK_DFLL_USBCRM</b>   (1)</td></tr>
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#define </td><td class="memItemRight" valign="bottom"><b>CONF_CORE_CLK_DFLL_LLAW</b>   (0)</td></tr>
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#define </td><td class="memItemRight" valign="bottom"><b>CONF_CORE_CLK_DFLL_STABLE_FCALIB</b>   CONF_CORE_CLK_DFLLCTRL_STABLE_FCALIB_NOT_FIXED</td></tr>
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#define </td><td class="memItemRight" valign="bottom"><b>CONF_CORE_CLK_DFLL_MODE</b>   0x01</td></tr>
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#define </td><td class="memItemRight" valign="bottom"><b>CONF_CORE_CLK_DFLL_DIFF_VAL</b>   0</td></tr>
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#define </td><td class="memItemRight" valign="bottom"><b>CONF_CORE_CLK_DFLL_COARSE_VAL</b>   (0x1f / 4)</td></tr>
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#define </td><td class="memItemRight" valign="bottom"><b>CONF_CORE_CLK_DFLL_FINE_VAL</b>   128</td></tr>
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<tr class="memitem:a87369bb1b036d78a49c44658f1e4e157"><td class="memItemLeft" align="right" valign="top"><a id="a87369bb1b036d78a49c44658f1e4e157"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>CONF_CORE_CLK_DFLL_CSTEP_VAL</b>   1</td></tr>
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#define </td><td class="memItemRight" valign="bottom"><b>CONF_CORE_CLK_DFLL_FSTEP_VAL</b>   1</td></tr>
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#define </td><td class="memItemRight" valign="bottom"><b>CONF_CORE_CLK_DFLL_MUL_VAL</b>   (48000000)</td></tr>
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<tr class="memitem:a0d8e56832f3d1f24b98173e3a3aa0046"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="conf__core_8h.html#a0d8e56832f3d1f24b98173e3a3aa0046">CONF_CORE_CLK_DFLL_GCLK_SRC</a>   3</td></tr>
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<tr class="memdesc:a0d8e56832f3d1f24b98173e3a3aa0046"><td class="mdescLeft"> </td><td class="mdescRight">GCLK Source used to generate DFLL48M. <a href="conf__core_8h.html#a0d8e56832f3d1f24b98173e3a3aa0046">More...</a><br /></td></tr>
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<tr class="separator:a0d8e56832f3d1f24b98173e3a3aa0046"><td class="memSeparator" colspan="2"> </td></tr>
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#define </td><td class="memItemRight" valign="bottom"><b>CONF_CORE_CLK_DFLL_OVERWRITE_CAL</b>   0</td></tr>
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<tr><td colspan="2"><div class="groupHeader">Core-DPLL0-Configuration</div></td></tr>
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<tr><td colspan="2"><div class="groupText"><p>Configuration Options for DPLL0. </p>
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</div></td></tr>
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<tr class="memitem:a32837c3455721c1e932c7adcccfdf0cd"><td class="memItemLeft" align="right" valign="top"><a id="a32837c3455721c1e932c7adcccfdf0cd"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>CONF_CORE_CLK_DPLL0_ENABLE</b>   (1)</td></tr>
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<tr class="memitem:a2b830cd50489a764556e8b1f8e541202"><td class="memItemLeft" align="right" valign="top"><a id="a2b830cd50489a764556e8b1f8e541202"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>CONF_CORE_CLK_DPLL0_ONDEMAND</b>   (0)</td></tr>
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<tr class="memitem:a232a0f414a1c0a62a825ca70d160651a"><td class="memItemLeft" align="right" valign="top"><a id="a232a0f414a1c0a62a825ca70d160651a"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>CONF_CORE_CLK_DPLL0_RUNSTDBY</b>   (0)</td></tr>
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<tr class="memitem:af8301c10a83c8d93ce10a737b1c28d96"><td class="memItemLeft" align="right" valign="top"><a id="af8301c10a83c8d93ce10a737b1c28d96"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>CONF_CORE_CLK_DPLL0_LDRFRAC_VAL</b>   0</td></tr>
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<tr class="memitem:a4dc011b4bae77aea3e2e78b4e58bda9f"><td class="memItemLeft" align="right" valign="top"><a id="a4dc011b4bae77aea3e2e78b4e58bda9f"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>CONF_CORE_CLK_DPLL0_LDR_VAL</b>   (119)</td></tr>
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<tr class="memitem:a8fc4add22bc160d41a48900de8d37b9d"><td class="memItemLeft" align="right" valign="top"><a id="a8fc4add22bc160d41a48900de8d37b9d"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>CONF_CORE_CLK_DPLL0_DIV_VAL</b>   (5)</td></tr>
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<tr class="memitem:adfd061b8e76628b32a3e75f8eaaa2121"><td class="memItemLeft" align="right" valign="top"><a id="adfd061b8e76628b32a3e75f8eaaa2121"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>CONF_CORE_CLK_DPLL0_DCOEN</b>   0</td></tr>
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<tr class="memitem:ac3f9bf6a11f84f688e26c37033f442f6"><td class="memItemLeft" align="right" valign="top"><a id="ac3f9bf6a11f84f688e26c37033f442f6"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>CONF_CORE_CLK_DPLL0_DCOFILTER</b>   CONF_CORE_CLK_DPLLCTRL_DCOFILTER_3210KHZ</td></tr>
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<tr class="separator:ac3f9bf6a11f84f688e26c37033f442f6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a36fb00b9e83f81a6ad52a639c65b14dd"><td class="memItemLeft" align="right" valign="top"><a id="a36fb00b9e83f81a6ad52a639c65b14dd"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>CONF_CORE_CLK_DPLL0_LBYPASS</b>   1</td></tr>
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<tr class="memitem:aec55e35583b422f3fba9ddd0fe315e32"><td class="memItemLeft" align="right" valign="top"><a id="aec55e35583b422f3fba9ddd0fe315e32"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>CONF_CORE_CLK_DPLL0_LTIME</b>   0</td></tr>
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#define </td><td class="memItemRight" valign="bottom"><b>CONF_CORE_CLK_DPLL0_WUF</b>   0</td></tr>
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<tr class="memitem:adcfac6cd48f945b481bd9b9c2fc14aab"><td class="memItemLeft" align="right" valign="top"><a id="adcfac6cd48f945b481bd9b9c2fc14aab"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>CONF_CORE_CLK_DPLL0_GCLK_SRC</b>   GCLK_GENCTRL_SRC_XOSC0</td></tr>
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<tr class="memitem:a8eab8998f300dc63cf9cf750a51cafa9"><td class="memItemLeft" align="right" valign="top"><a id="a8eab8998f300dc63cf9cf750a51cafa9"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>CONF_CORE_CLK_DPLL0_REFCLK</b>   CONF_CORE_CLK_DPLLCTRL_REFCLK_XOSC0</td></tr>
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<tr class="memitem:a5cd9abca6f486eaebb6ddd236960b01a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="conf__core_8h.html#a5cd9abca6f486eaebb6ddd236960b01a">CONF_CORE_CLK_DPLL0_FILTER</a>   0x0</td></tr>
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<tr class="separator:a5cd9abca6f486eaebb6ddd236960b01a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr><td colspan="2"><div class="groupHeader">Core-DPLL1-Configuration</div></td></tr>
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<tr><td colspan="2"><div class="groupText"><p>Configuration Options for DPLL1. </p>
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</div></td></tr>
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<tr class="memitem:a98d3a5ebaa868e372e467d61e8f0915e"><td class="memItemLeft" align="right" valign="top"><a id="a98d3a5ebaa868e372e467d61e8f0915e"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>CONF_CORE_CLK_DPLL1_ENABLE</b>   (0)</td></tr>
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<tr class="memitem:a9e78bd13faa639f138ab9ea20bd1b1dd"><td class="memItemLeft" align="right" valign="top"><a id="a9e78bd13faa639f138ab9ea20bd1b1dd"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>CONF_CORE_CLK_DPLL1_ONDEMAND</b>   (0)</td></tr>
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<tr class="memitem:ac2a6f39d072c0aa33b8c9c90c626f742"><td class="memItemLeft" align="right" valign="top"><a id="ac2a6f39d072c0aa33b8c9c90c626f742"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>CONF_CORE_CLK_DPLL1_RUNSTDBY</b>   (0)</td></tr>
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<tr class="memitem:aad9c291ed981573062103b6930f56434"><td class="memItemLeft" align="right" valign="top"><a id="aad9c291ed981573062103b6930f56434"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>CONF_CORE_CLK_DPLL1_LDRFRAC_VAL</b>   0</td></tr>
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<tr class="memitem:a8fb5c78ecfdc3179bc1cf0fd09b93b43"><td class="memItemLeft" align="right" valign="top"><a id="a8fb5c78ecfdc3179bc1cf0fd09b93b43"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>CONF_CORE_CLK_DPLL1_LDR_VAL</b>   (0)</td></tr>
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<tr class="memitem:a420a27c14d9796b27cb4467dd9be4b25"><td class="memItemLeft" align="right" valign="top"><a id="a420a27c14d9796b27cb4467dd9be4b25"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>CONF_CORE_CLK_DPLL1_DIV_VAL</b>   (0)</td></tr>
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<tr class="memitem:a928c76f06226be2ce5121b60d04d7d0f"><td class="memItemLeft" align="right" valign="top"><a id="a928c76f06226be2ce5121b60d04d7d0f"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>CONF_CORE_CLK_DPLL1_DCOEN</b>   0</td></tr>
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<tr class="memitem:a1860168cd66107207d6bcd2a6104a953"><td class="memItemLeft" align="right" valign="top"><a id="a1860168cd66107207d6bcd2a6104a953"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>CONF_CORE_CLK_DPLL1_DCOFILTER</b>   CONF_CORE_CLK_DPLLCTRL_DCOFILTER_3210KHZ</td></tr>
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<tr class="memitem:aa82d590e2d2bfbfff5f921600657332f"><td class="memItemLeft" align="right" valign="top"><a id="aa82d590e2d2bfbfff5f921600657332f"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>CONF_CORE_CLK_DPLL1_LBYPASS</b>   0</td></tr>
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<tr class="memitem:a51e32a541cfcdef0a10077488b1bda87"><td class="memItemLeft" align="right" valign="top"><a id="a51e32a541cfcdef0a10077488b1bda87"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>CONF_CORE_CLK_DPLL1_LTIME</b>   0</td></tr>
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<tr class="separator:a51e32a541cfcdef0a10077488b1bda87"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a537f2fb05f6ee6cca0692bd32f2e23bb"><td class="memItemLeft" align="right" valign="top"><a id="a537f2fb05f6ee6cca0692bd32f2e23bb"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>CONF_CORE_CLK_DPLL1_WUF</b>   0</td></tr>
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<tr class="separator:a537f2fb05f6ee6cca0692bd32f2e23bb"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a0780d9ac15356ac35efcc516ef288017"><td class="memItemLeft" align="right" valign="top"><a id="a0780d9ac15356ac35efcc516ef288017"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>CONF_CORE_CLK_DPLL1_GCLK_SRC</b>   GCLK_GENCTRL_SRC_XOSC0</td></tr>
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<tr class="memitem:a4ee0e9569732ce043f243a86c068b51a"><td class="memItemLeft" align="right" valign="top"><a id="a4ee0e9569732ce043f243a86c068b51a"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>CONF_CORE_CLK_DPLL1_REFCLK</b>   CONF_CORE_CLK_DPLLCTRL_REFCLK_XOSC0</td></tr>
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<tr class="memitem:a9de3ab7eb7e3c001d6aa7040f6311f10"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="conf__core_8h.html#a9de3ab7eb7e3c001d6aa7040f6311f10">CONF_CORE_CLK_DPLL1_FILTER</a>   0x0</td></tr>
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<tr class="separator:a9de3ab7eb7e3c001d6aa7040f6311f10"><td class="memSeparator" colspan="2"> </td></tr>
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</table>
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<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2>
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<div class="textblock"><dl class="section author"><dt>Author</dt><dd>Penguin</dd></dl>
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<h1><a class="anchor" id="Description"></a>
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Description</h1>
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<p>This is the master config for the core module for this mcu. This file is <em>required</em> for the core module to function. </p>
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<p class="definition">Definition in file <a class="el" href="conf__core_8h_source.html">conf_core.h</a>.</p>
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</div><h2 class="groupheader">Macro Definition Documentation</h2>
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<a id="a03160c4c7871685bbde0e96f02825842"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#a03160c4c7871685bbde0e96f02825842">◆ </a></span>CONF_CORE_CLK_DFLL_ENABLE</h2>
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<div class="memitem">
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<div class="memproto">
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<table class="memname">
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<tr>
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<td class="memname">#define CONF_CORE_CLK_DFLL_ENABLE   (1)</td>
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</tr>
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</table>
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</div><div class="memdoc">
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<p>Enables or Disables the DFLL48M Clock. </p>
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<p>DFLL48M Enable</p><ul>
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<li>0 => Disables DFLL48M</li>
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<li>1 => Enables DFLL48M <br />
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pg. 724 of datasheet </li>
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</ul>
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<p class="definition">Definition at line <a class="el" href="conf__core_8h_source.html#l00390">390</a> of file <a class="el" href="conf__core_8h_source.html">conf_core.h</a>.</p>
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</div>
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</div>
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<h2 class="memtitle"><span class="permalink"><a href="#a0d8e56832f3d1f24b98173e3a3aa0046">◆ </a></span>CONF_CORE_CLK_DFLL_GCLK_SRC</h2>
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<td class="memname">#define CONF_CORE_CLK_DFLL_GCLK_SRC   3</td>
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<p>GCLK Source used to generate DFLL48M. </p>
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<p>DFLL48M GCLK Source</p><ul>
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<li>0 => Generic clock generator 0</li>
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<li>1 => Generic clock generator 1</li>
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<li>2 => Generic clock generator 2</li>
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<li>3 => Generic clock generator 3</li>
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<li>4 => Generic clock generator 4</li>
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<li>5 => Generic clock generator 5</li>
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<li>6 => Generic clock generator 6</li>
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<li>7 => Generic clock generator 7</li>
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<li>8 => Generic clock generator 8</li>
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<li>9 => Generic clock generator 9</li>
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<li>10 => Generic clock generator 10</li>
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<li>11 => Generic clock generator 11 </li>
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</ul>
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<p class="definition">Definition at line <a class="el" href="conf__core_8h_source.html#l00444">444</a> of file <a class="el" href="conf__core_8h_source.html">conf_core.h</a>.</p>
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<a id="a55515b150245a993779a0d5f417cc828"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#a55515b150245a993779a0d5f417cc828">◆ </a></span>CONF_CORE_CLK_DFLL_ONDEMAND</h2>
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<td class="memname">#define CONF_CORE_CLK_DFLL_ONDEMAND   (0)</td>
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<p>Enables or Disables on-demand operation. </p>
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<p>DFLL48M On Demand Control</p><ul>
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<li>0 => Disables On Demand Operation</li>
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<li>1 => Enables On Demand Operation <br />
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pg. 724 of datasheet </li>
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</ul>
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<p class="definition">Definition at line <a class="el" href="conf__core_8h_source.html#l00398">398</a> of file <a class="el" href="conf__core_8h_source.html">conf_core.h</a>.</p>
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<a id="ab6b320dcf67ec88f534adcbf77e2ce7b"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#ab6b320dcf67ec88f534adcbf77e2ce7b">◆ </a></span>CONF_CORE_CLK_DFLL_RUNSTDBY</h2>
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<td class="memname">#define CONF_CORE_CLK_DFLL_RUNSTDBY   (0)</td>
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<p>Enables or Disables run-in-standby operation. </p>
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<p>DFLL48M Run in Standby Control</p><ul>
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<li>0 => Disables run-in-standby operation</li>
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<li>1 => Enables run-in-standby operation <br />
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pg. 724 of datasheet </li>
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</ul>
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<p class="definition">Definition at line <a class="el" href="conf__core_8h_source.html#l00406">406</a> of file <a class="el" href="conf__core_8h_source.html">conf_core.h</a>.</p>
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</div>
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<a id="a1f088d6654bb907ff388ced455b2dbb2"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#a1f088d6654bb907ff388ced455b2dbb2">◆ </a></span>CONF_CORE_CLK_DFLL_WAITLOCK</h2>
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<td class="memname">#define CONF_CORE_CLK_DFLL_WAITLOCK   (0)</td>
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<p>This bit controls the DFLL output clock, depending on the lock status: </p>
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<p>DFLL48M Wait Lock Control</p><ul>
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<li>0 => Output clock before the DFLL is locked.</li>
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<li>1 => Output clock when DFLL is locked (Fine lock). <br />
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pg. 725 of datasheet </li>
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</ul>
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<p class="definition">Definition at line <a class="el" href="conf__core_8h_source.html#l00414">414</a> of file <a class="el" href="conf__core_8h_source.html">conf_core.h</a>.</p>
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<h2 class="memtitle"><span class="permalink"><a href="#a5cd9abca6f486eaebb6ddd236960b01a">◆ </a></span>CONF_CORE_CLK_DPLL0_FILTER</h2>
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<td class="memname">#define CONF_CORE_CLK_DPLL0_FILTER   0x0</td>
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<p>pg. 732 of the datasheet </p><div class="fragment"><div class="line">FILTER[3:0] | PLL Bandwidth (fn) | Damping Factor</div>
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<div class="line">0x0 | 92.7 kHz | 0.76</div>
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<div class="line">0x1 | 131 kHz | 1.08</div>
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<div class="line">0x2 | 46.4 kHz | 0.38</div>
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<div class="line">0x3 | 65.6 kHz | 0.54</div>
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<div class="line">0x4 | 131 kHz | 0.56</div>
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<div class="line">0x5 | 185 kHz | 0.79</div>
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<div class="line">0x6 | 65.6 kHz | 0.28</div>
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<div class="line">0x7 | 92.7 kHz | 0.39</div>
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<div class="line">0x8 | 46.4 kHz | 1.49</div>
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<div class="line">0x9 | 65.6 kHz | 2.11</div>
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<div class="line">0xA | 23.2 kHz | 0.75</div>
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<div class="line">0xB | 32.8 kHz | 1.06</div>
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<div class="line">0xC | 65.6 kHz | 1.07</div>
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<div class="line">0xD | 92.7 kHz | 1.51</div>
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<div class="line">0xE | 32.8 kHz | 0.53</div>
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<div class="line">0xF | 46.4 kHz | 0.75</div>
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</div><!-- fragment --><p>When in doubt, leave this at its default. </p>
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<p class="definition">Definition at line <a class="el" href="conf__core_8h_source.html#l00490">490</a> of file <a class="el" href="conf__core_8h_source.html">conf_core.h</a>.</p>
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<a id="a9de3ab7eb7e3c001d6aa7040f6311f10"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#a9de3ab7eb7e3c001d6aa7040f6311f10">◆ </a></span>CONF_CORE_CLK_DPLL1_FILTER</h2>
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<td class="memname">#define CONF_CORE_CLK_DPLL1_FILTER   0x0</td>
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</div><div class="memdoc">
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<p>pg. 732 of the datasheet </p><div class="fragment"><div class="line">FILTER[3:0] | PLL Bandwidth (fn) | Damping Factor</div>
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<div class="line">0x0 | 92.7 kHz | 0.76</div>
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<div class="line">0x1 | 131 kHz | 1.08</div>
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<div class="line">0x2 | 46.4 kHz | 0.38</div>
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<div class="line">0x3 | 65.6 kHz | 0.54</div>
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<div class="line">0x4 | 131 kHz | 0.56</div>
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<div class="line">0x5 | 185 kHz | 0.79</div>
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<div class="line">0x6 | 65.6 kHz | 0.28</div>
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<div class="line">0x7 | 92.7 kHz | 0.39</div>
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<div class="line">0x8 | 46.4 kHz | 1.49</div>
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<div class="line">0x9 | 65.6 kHz | 2.11</div>
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<div class="line">0xA | 23.2 kHz | 0.75</div>
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<div class="line">0xB | 32.8 kHz | 1.06</div>
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<div class="line">0xC | 65.6 kHz | 1.07</div>
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<div class="line">0xD | 92.7 kHz | 1.51</div>
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<div class="line">0xE | 32.8 kHz | 0.53</div>
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<div class="line">0xF | 46.4 kHz | 0.75</div>
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</div><!-- fragment --><p>When in doubt, leave this at its default. </p>
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<p class="definition">Definition at line <a class="el" href="conf__core_8h_source.html#l00535">535</a> of file <a class="el" href="conf__core_8h_source.html">conf_core.h</a>.</p>
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<a id="a17cd20bb954bc137251cf7fb63889151"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#a17cd20bb954bc137251cf7fb63889151">◆ </a></span>CONF_CORE_CLK_XOSC0_CFDEN</h2>
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<td class="memname">#define CONF_CORE_CLK_XOSC0_CFDEN   (1)</td>
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<p>This bit controls the XOSC0 clock failure detector: </p>
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<p>XOSC0 Clock Failure Detector Control</p><ul>
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<li>0 => Clock Failure Detector is disabled.</li>
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<li>1 => Clock Failure Detector is enabled. <br />
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See <a href="https://ww1.microchip.com/downloads/en/DeviceDoc/SAM_D5xE5x_Family_Data_Sheet_DS60001507F.pdf#page=722">Datasheet Reference</a> </li>
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<p class="definition">Definition at line <a class="el" href="conf__core_8h_source.html#l00128">128</a> of file <a class="el" href="conf__core_8h_source.html">conf_core.h</a>.</p>
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<a id="a61559adc856ce1dcfa046e749af63bc3"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#a61559adc856ce1dcfa046e749af63bc3">◆ </a></span>CONF_CORE_CLK_XOSC0_ENABLE</h2>
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<td class="memname">#define CONF_CORE_CLK_XOSC0_ENABLE   (1)</td>
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<p>Enables or Disables the XOSC0 Clock. </p>
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<p>XOSC0 Enable</p><ul>
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<li>0 => Disables XOSC0</li>
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<li>1 => Enables XOSC0 <br />
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See <a href="https://ww1.microchip.com/downloads/en/DeviceDoc/SAM_D5xE5x_Family_Data_Sheet_DS60001507F.pdf#page=723">Datasheet Reference</a> </li>
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<p class="definition">Definition at line <a class="el" href="conf__core_8h_source.html#l00076">76</a> of file <a class="el" href="conf__core_8h_source.html">conf_core.h</a>.</p>
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<a id="a2683d3721ab44a85e60cfff0d0cbf96e"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#a2683d3721ab44a85e60cfff0d0cbf96e">◆ </a></span>CONF_CORE_CLK_XOSC0_ENALC</h2>
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<td class="memname">#define CONF_CORE_CLK_XOSC0_ENALC   (1)</td>
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<p>This bit controls the XOSC0 automatic loop control: </p>
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<p>XOSC0 Automatic Loop Control</p><ul>
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<li>0 => The automatic loop control is disabled.</li>
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<li>1 => The automatic loop control is enabled. Oscillator's amplitude will be automatically adjusted during Crystal Oscillator operation. <br />
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See <a href="https://ww1.microchip.com/downloads/en/DeviceDoc/SAM_D5xE5x_Family_Data_Sheet_DS60001507F.pdf#page=722">Datasheet Reference</a> </li>
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<p class="definition">Definition at line <a class="el" href="conf__core_8h_source.html#l00120">120</a> of file <a class="el" href="conf__core_8h_source.html">conf_core.h</a>.</p>
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<a id="af6ec0afa1da472db5f1def1d1923faad"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#af6ec0afa1da472db5f1def1d1923faad">◆ </a></span>CONF_CORE_CLK_XOSC0_FREQUENCY</h2>
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<td class="memname">#define CONF_CORE_CLK_XOSC0_FREQUENCY   12000000</td>
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<p>This is the frequency of the external clock you're using for XOSC0. This can be anything from 8MHz to 48MHz. </p>
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<p>XOSC0 Frequency </p>
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<p class="definition">Definition at line <a class="el" href="conf__core_8h_source.html#l00165">165</a> of file <a class="el" href="conf__core_8h_source.html">conf_core.h</a>.</p>
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<a id="aeea7b0d3663bb6d5ccc3218017f9a05b"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#aeea7b0d3663bb6d5ccc3218017f9a05b">◆ </a></span>CONF_CORE_CLK_XOSC0_LOWBUFGAIN</h2>
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<td class="memname">#define CONF_CORE_CLK_XOSC0_LOWBUFGAIN   (0)</td>
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<p>The default value of LOWBUFGAIN=0 should be used to allow operating with a low amplitude oscillator. Don't use this setting except to solve stability issues. </p>
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<p>XOSC0 Low Buffer Gain Control Bit</p><ul>
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<li>0 => The low buffer gain of XOSC0 is disabled.</li>
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<li>1 => The low buffer gain of XOSC0 is enabled. <br />
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See <a href="https://ww1.microchip.com/downloads/en/DeviceDoc/SAM_D5xE5x_Family_Data_Sheet_DS60001507F.pdf#page=722">Datasheet Reference</a> </li>
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<p class="definition">Definition at line <a class="el" href="conf__core_8h_source.html#l00112">112</a> of file <a class="el" href="conf__core_8h_source.html">conf_core.h</a>.</p>
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<a id="a5ffaa1551b7ffb8a342b2cc5fbc5950c"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#a5ffaa1551b7ffb8a342b2cc5fbc5950c">◆ </a></span>CONF_CORE_CLK_XOSC0_ONDEMAND</h2>
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<td class="memname">#define CONF_CORE_CLK_XOSC0_ONDEMAND   (0)</td>
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<p>The On Demand operation mode allows the oscillator XOSC0 to be enabled or disabled, depending on peripheral clock requests. </p>
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<p>XOSC0 On Demand Control</p><ul>
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<li>0 => Oscillator is always on.</li>
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<li>1 => The oscillator is running when a peripheral is requesting the oscillator to be used as a clock source. The oscillator is not running if no peripheral is requesting the clock source. <br />
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See <a href="https://ww1.microchip.com/downloads/en/DeviceDoc/SAM_D5xE5x_Family_Data_Sheet_DS60001507F.pdf#page=722">Datasheet Reference</a> </li>
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<p class="definition">Definition at line <a class="el" href="conf__core_8h_source.html#l00103">103</a> of file <a class="el" href="conf__core_8h_source.html">conf_core.h</a>.</p>
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<a id="afac0686157854cc021424410ded071f1"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#afac0686157854cc021424410ded071f1">◆ </a></span>CONF_CORE_CLK_XOSC0_RUNSTDBY</h2>
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<td class="memname">#define CONF_CORE_CLK_XOSC0_RUNSTDBY   (0)</td>
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<p>This bit controls how the XOSC0 behaves during standby sleep mode: </p>
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<p>XOSC0 Run in Standby</p><ul>
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<li>0 => XOSC0 is not running in standby sleep mode if no peripheral requests the clock.</li>
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<li>1 => XOSC0 is running in standby sleep mode. If ONDEMAND is 1, XOSC0 will be running when a peripheral is requesting the clock. If ONDEMAND is 0, the clock source will always be running in standby sleep mode. <br />
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See <a href="https://ww1.microchip.com/downloads/en/DeviceDoc/SAM_D5xE5x_Family_Data_Sheet_DS60001507F.pdf#page=723">Datasheet Reference</a> </li>
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<p class="definition">Definition at line <a class="el" href="conf__core_8h_source.html#l00094">94</a> of file <a class="el" href="conf__core_8h_source.html">conf_core.h</a>.</p>
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<h2 class="memtitle"><span class="permalink"><a href="#affc8201cf2340d2236ba9ca44a1e657c">◆ </a></span>CONF_CORE_CLK_XOSC0_STARTUP_TIME</h2>
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<td class="memname">#define CONF_CORE_CLK_XOSC0_STARTUP_TIME   (0x00)</td>
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<p>These bits select start-up time for XOSC0 according to the table below: </p>
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<p>XOSC0 Startup Time</p><ul>
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<li>0x00 => 31us</li>
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<li>0x01 => 61us</li>
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<li>0x02 => 122us</li>
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<li>0x03 => 244us</li>
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<li>0x04 => 488us</li>
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<li>0x05 => 977us</li>
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<li>0x06 => 1953us</li>
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<li>0x07 => 3906us</li>
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<li>0x08 => 7813us</li>
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<li>0x09 => 15625us</li>
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<li>0x0A => 31250us</li>
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<li>0x0B => 62500us</li>
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<li>0x0C => 125000us</li>
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<li>0x0D => 250000us</li>
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<li>0x0E => 500000us</li>
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<li>0x0F => 1000000us <br />
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See <a href="https://ww1.microchip.com/downloads/en/DeviceDoc/SAM_D5xE5x_Family_Data_Sheet_DS60001507F.pdf#page=721">Datasheet Reference</a> </li>
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<p class="definition">Definition at line <a class="el" href="conf__core_8h_source.html#l00159">159</a> of file <a class="el" href="conf__core_8h_source.html">conf_core.h</a>.</p>
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<a id="abe235b3b13f253acb855d15c8f33c95a"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#abe235b3b13f253acb855d15c8f33c95a">◆ </a></span>CONF_CORE_CLK_XOSC0_SWBEN</h2>
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<td class="memname">#define CONF_CORE_CLK_XOSC0_SWBEN   (0)</td>
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<p>This bit controls the XOSC0 output clock switch back to the external clock or crystal oscillator in case of clock recovery: </p>
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<p>XOSC0 Clock Switch Enable</p><ul>
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<li>0 => The clock switch back is disabled.</li>
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<li>1 => The clock switch back is enabled. This bit is reset once the XOSC0 output clock is switched back to the external clock or crystal oscillator. <br />
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See <a href="https://ww1.microchip.com/downloads/en/DeviceDoc/SAM_D5xE5x_Family_Data_Sheet_DS60001507F.pdf#page=722">Datasheet Reference</a> </li>
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</ul>
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<p class="definition">Definition at line <a class="el" href="conf__core_8h_source.html#l00137">137</a> of file <a class="el" href="conf__core_8h_source.html">conf_core.h</a>.</p>
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<a id="ac2ca0e9037347eb69d53a0011f989910"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#ac2ca0e9037347eb69d53a0011f989910">◆ </a></span>CONF_CORE_CLK_XOSC0_XTALEN</h2>
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<td class="memname">#define CONF_CORE_CLK_XOSC0_XTALEN   (1)</td>
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<p>This bit controls the connections between the I/O pads and the external clock or crystal oscillator XOSC0: </p>
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<p>XOSC0 XTALEN</p><ul>
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<li>0 => External clock connected on XIN. XOUT can be used as general purpose I/O.</li>
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<li>1 => Crystal connected to XIN/XOUT. <br />
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See <a href="https://ww1.microchip.com/downloads/en/DeviceDoc/SAM_D5xE5x_Family_Data_Sheet_DS60001507F.pdf#page=723">Datasheet Reference</a> </li>
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<p class="definition">Definition at line <a class="el" href="conf__core_8h_source.html#l00084">84</a> of file <a class="el" href="conf__core_8h_source.html">conf_core.h</a>.</p>
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<a id="a924214b0f469bde71ff28fe5544466db"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#a924214b0f469bde71ff28fe5544466db">◆ </a></span>CONF_CORE_CLK_XOSC1_CFDEN</h2>
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<td class="memname">#define CONF_CORE_CLK_XOSC1_CFDEN   (0)</td>
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<p>This bit controls the XOSC1 clock failure detector: </p>
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<p>XOSC1 Clock Failure Detector Control</p><ul>
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<li>0 => Clock Failure Detector is disabled.</li>
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<li>1 => Clock Failure Detector is enabled. <br />
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See <a href="https://ww1.microchip.com/downloads/en/DeviceDoc/SAM_D5xE5x_Family_Data_Sheet_DS60001507F.pdf#page=722">Datasheet Reference</a> </li>
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<p class="definition">Definition at line <a class="el" href="conf__core_8h_source.html#l00232">232</a> of file <a class="el" href="conf__core_8h_source.html">conf_core.h</a>.</p>
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<a id="aa54465cc56631333a22ae84ab66d5f3a"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#aa54465cc56631333a22ae84ab66d5f3a">◆ </a></span>CONF_CORE_CLK_XOSC1_ENABLE</h2>
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<td class="memname">#define CONF_CORE_CLK_XOSC1_ENABLE   (0)</td>
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<p>Enables or Disables the XOSC1 Clock. </p>
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<p>XOSC1 Enable</p><ul>
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<li>0 => Disables XOSC1</li>
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<li>1 => Enables XOSC1 <br />
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See <a href="https://ww1.microchip.com/downloads/en/DeviceDoc/SAM_D5xE5x_Family_Data_Sheet_DS60001507F.pdf#page=723">Datasheet Reference</a> </li>
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</ul>
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<p class="definition">Definition at line <a class="el" href="conf__core_8h_source.html#l00180">180</a> of file <a class="el" href="conf__core_8h_source.html">conf_core.h</a>.</p>
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<a id="a3a42de5c6251540e7b8c000974acfc62"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#a3a42de5c6251540e7b8c000974acfc62">◆ </a></span>CONF_CORE_CLK_XOSC1_ENALC</h2>
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<td class="memname">#define CONF_CORE_CLK_XOSC1_ENALC   (0)</td>
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<p>This bit controls the XOSC1 automatic loop control: </p>
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<p>XOSC1 Automatic Loop Control</p><ul>
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<li>0 => The automatic loop control is disabled.</li>
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<li>1 => The automatic loop control is enabled. Oscillator's amplitude will be automatically adjusted during Crystal Oscillator operation. <br />
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See <a href="https://ww1.microchip.com/downloads/en/DeviceDoc/SAM_D5xE5x_Family_Data_Sheet_DS60001507F.pdf#page=722">Datasheet Reference</a> </li>
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</ul>
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<p class="definition">Definition at line <a class="el" href="conf__core_8h_source.html#l00224">224</a> of file <a class="el" href="conf__core_8h_source.html">conf_core.h</a>.</p>
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<a id="a3fc3ea49b9d78438e5a8c19a22849469"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#a3fc3ea49b9d78438e5a8c19a22849469">◆ </a></span>CONF_CORE_CLK_XOSC1_FREQUENCY</h2>
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<td class="memname">#define CONF_CORE_CLK_XOSC1_FREQUENCY   12000000</td>
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<p>This is the frequency of the external clock you're using for XOSC1. This can be anything from 8MHz to 48MHz. </p>
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<p>XOSC1 Frequency </p>
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<p class="definition">Definition at line <a class="el" href="conf__core_8h_source.html#l00269">269</a> of file <a class="el" href="conf__core_8h_source.html">conf_core.h</a>.</p>
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<a id="a985ebd23986d9411d3602040e33bb405"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#a985ebd23986d9411d3602040e33bb405">◆ </a></span>CONF_CORE_CLK_XOSC1_LOWBUFGAIN</h2>
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<td class="memname">#define CONF_CORE_CLK_XOSC1_LOWBUFGAIN   (0)</td>
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<p>The default value of LOWBUFGAIN=0 should be used to allow operating with a low amplitude oscillator. Don't use this setting except to solve stability issues. </p>
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<p>XOSC1 Low Buffer Gain Control Bit</p><ul>
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<li>0 => The low buffer gain of XOSC1 is disabled.</li>
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<li>1 => The low buffer gain of XOSC1 is enabled. <br />
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See <a href="https://ww1.microchip.com/downloads/en/DeviceDoc/SAM_D5xE5x_Family_Data_Sheet_DS60001507F.pdf#page=722">Datasheet Reference</a> </li>
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<p class="definition">Definition at line <a class="el" href="conf__core_8h_source.html#l00216">216</a> of file <a class="el" href="conf__core_8h_source.html">conf_core.h</a>.</p>
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<a id="aaf561ace0fee1e373536a251ce8a9726"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#aaf561ace0fee1e373536a251ce8a9726">◆ </a></span>CONF_CORE_CLK_XOSC1_ONDEMAND</h2>
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<td class="memname">#define CONF_CORE_CLK_XOSC1_ONDEMAND   (0)</td>
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<p>The On Demand operation mode allows the oscillator XOSC1 to be enabled or disabled, depending on peripheral clock requests. </p>
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<p>XOSC1 On Demand Control</p><ul>
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<li>0 => Oscillator is always on.</li>
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<li>1 => The oscillator is running when a peripheral is requesting the oscillator to be used as a clock source. The oscillator is not running if no peripheral is requesting the clock source. <br />
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See <a href="https://ww1.microchip.com/downloads/en/DeviceDoc/SAM_D5xE5x_Family_Data_Sheet_DS60001507F.pdf#page=722">Datasheet Reference</a> </li>
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<p class="definition">Definition at line <a class="el" href="conf__core_8h_source.html#l00207">207</a> of file <a class="el" href="conf__core_8h_source.html">conf_core.h</a>.</p>
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<a id="a8bec34fdc01ac38ec0c2d13112f28aa0"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#a8bec34fdc01ac38ec0c2d13112f28aa0">◆ </a></span>CONF_CORE_CLK_XOSC1_RUNSTDBY</h2>
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<td class="memname">#define CONF_CORE_CLK_XOSC1_RUNSTDBY   (0)</td>
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<p>This bit controls how the XOSC1 behaves during standby sleep mode: </p>
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<p>XOSC1 Run in Standby</p><ul>
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<li>0 => XOSC1 is not running in standby sleep mode if no peripheral requests the clock.</li>
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<li>1 => XOSC1 is running in standby sleep mode. If ONDEMAND is 1, XOSC1 will be running when a peripheral is requesting the clock. If ONDEMAND is 0, the clock source will always be running in standby sleep mode. <br />
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See <a href="https://ww1.microchip.com/downloads/en/DeviceDoc/SAM_D5xE5x_Family_Data_Sheet_DS60001507F.pdf#page=723">Datasheet Reference</a> </li>
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<p class="definition">Definition at line <a class="el" href="conf__core_8h_source.html#l00198">198</a> of file <a class="el" href="conf__core_8h_source.html">conf_core.h</a>.</p>
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<a id="ae8d2fdac3b52964174863149986db625"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#ae8d2fdac3b52964174863149986db625">◆ </a></span>CONF_CORE_CLK_XOSC1_STARTUP_TIME</h2>
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<td class="memname">#define CONF_CORE_CLK_XOSC1_STARTUP_TIME   (0x00)</td>
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<p>These bits select start-up time for XOSC1 according to the table below: </p>
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<p>XOSC1 Startup Time</p><ul>
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<li>0x00 => 31us</li>
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<li>0x01 => 61us</li>
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<li>0x02 => 122us</li>
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<li>0x03 => 244us</li>
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<li>0x04 => 488us</li>
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<li>0x05 => 977us</li>
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<li>0x06 => 1953us</li>
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<li>0x07 => 3906us</li>
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<li>0x08 => 7813us</li>
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<li>0x09 => 15625us</li>
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<li>0x0A => 31250us</li>
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<li>0x0B => 62500us</li>
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<li>0x0C => 125000us</li>
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<li>0x0D => 250000us</li>
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<li>0x0E => 500000us</li>
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<li>0x0F => 1000000us <br />
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See <a href="https://ww1.microchip.com/downloads/en/DeviceDoc/SAM_D5xE5x_Family_Data_Sheet_DS60001507F.pdf#page=721">Datasheet Reference</a> </li>
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<p class="definition">Definition at line <a class="el" href="conf__core_8h_source.html#l00263">263</a> of file <a class="el" href="conf__core_8h_source.html">conf_core.h</a>.</p>
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<a id="a590b1e68a3f666bdea576a32f4e74ba0"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#a590b1e68a3f666bdea576a32f4e74ba0">◆ </a></span>CONF_CORE_CLK_XOSC1_SWBEN</h2>
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<p>This bit controls the XOSC1 output clock switch back to the external clock or crystal oscillator in case of clock recovery: </p>
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<p>XOSC1 Clock Switch Enable</p><ul>
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<li>0 => The clock switch back is disabled.</li>
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<li>1 => The clock switch back is enabled. This bit is reset once the XOSC1 output clock is switched back to the external clock or crystal oscillator. <br />
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See <a href="https://ww1.microchip.com/downloads/en/DeviceDoc/SAM_D5xE5x_Family_Data_Sheet_DS60001507F.pdf#page=722">Datasheet Reference</a> </li>
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<p class="definition">Definition at line <a class="el" href="conf__core_8h_source.html#l00241">241</a> of file <a class="el" href="conf__core_8h_source.html">conf_core.h</a>.</p>
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<a id="ae3f8741e2be4b37a46dfb49af2c2a09d"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#ae3f8741e2be4b37a46dfb49af2c2a09d">◆ </a></span>CONF_CORE_CLK_XOSC1_XTALEN</h2>
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<td class="memname">#define CONF_CORE_CLK_XOSC1_XTALEN   (0)</td>
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<p>This bit controls the connections between the I/O pads and the external clock or crystal oscillator XOSC1: </p>
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<p>XOSC1 XTALEN</p><ul>
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<li>0 => External clock connected on XIN. XOUT can be used as general purpose I/O.</li>
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<li>1 => Crystal connected to XIN/XOUT. <br />
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See <a href="https://ww1.microchip.com/downloads/en/DeviceDoc/SAM_D5xE5x_Family_Data_Sheet_DS60001507F.pdf#page=723">Datasheet Reference</a> </li>
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<p class="definition">Definition at line <a class="el" href="conf__core_8h_source.html#l00188">188</a> of file <a class="el" href="conf__core_8h_source.html">conf_core.h</a>.</p>
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<a id="a668d68edf9a7ac05be5b9cda247225ad"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#a668d68edf9a7ac05be5b9cda247225ad">◆ </a></span>CONF_CORE_CLK_XOSC32K_CFDEN</h2>
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<td class="memname">#define CONF_CORE_CLK_XOSC32K_CFDEN   (0)</td>
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<p>This bit selects the Clock Failulre Detector state. </p>
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<p>XOSC32K Clock Failure Detector Control</p><ul>
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<li>0 => The CFD is disabled.</li>
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<li>1 => The CFD is enabled. <br />
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See <a href="https://ww1.microchip.com/downloads/en/DeviceDoc/SAM_D5xE5x_Family_Data_Sheet_DS60001507F.pdf#page=750">Datasheet Reference</a> </li>
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<p class="definition">Definition at line <a class="el" href="conf__core_8h_source.html#l00360">360</a> of file <a class="el" href="conf__core_8h_source.html">conf_core.h</a>.</p>
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<a id="a79567f94a0f3ad2d628bcf5e1cff62d1"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#a79567f94a0f3ad2d628bcf5e1cff62d1">◆ </a></span>CONF_CORE_CLK_XOSC32K_CFDPRESC</h2>
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<td class="memname">#define CONF_CORE_CLK_XOSC32K_CFDPRESC   (0)</td>
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<p>This bit selects the prescaler for the CLock Failure Detector: </p>
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<p>XOSC32K Clock Failure Detector Prescaler</p><ul>
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<li>0 => The CFD safe clock frequency is the OSCULP32K frequency.</li>
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<li>1 => The CFD safe clock frequency is the OSCULP32K frequency divided by 2. <br />
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See <a href="https://ww1.microchip.com/downloads/en/DeviceDoc/SAM_D5xE5x_Family_Data_Sheet_DS60001507F.pdf#page=750">Datasheet Reference</a> </li>
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</ul>
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<p class="definition">Definition at line <a class="el" href="conf__core_8h_source.html#l00352">352</a> of file <a class="el" href="conf__core_8h_source.html">conf_core.h</a>.</p>
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<a id="a031a77340c697036538d218724837de1"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#a031a77340c697036538d218724837de1">◆ </a></span>CONF_CORE_CLK_XOSC32K_CGM</h2>
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<td class="memname">#define CONF_CORE_CLK_XOSC32K_CGM   (0x01)</td>
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<p>These bits control the gain of the external crstal oscillator. </p>
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<p>XOSC32K Control Gain Mode</p><ul>
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<li>0x00 => Low Power Mode</li>
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<li>0x01 => Standard Mode (Default)</li>
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<li>0x02 => High Speed Mode <br />
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See <a href="https://ww1.microchip.com/downloads/en/DeviceDoc/SAM_D5xE5x_Family_Data_Sheet_DS60001507F.pdf#page=748">Datasheet Reference</a> </li>
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</ul>
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<p class="definition">Definition at line <a class="el" href="conf__core_8h_source.html#l00293">293</a> of file <a class="el" href="conf__core_8h_source.html">conf_core.h</a>.</p>
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<a id="a033f3571fb50a6ed02278d65ea84b45e"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#a033f3571fb50a6ed02278d65ea84b45e">◆ </a></span>CONF_CORE_CLK_XOSC32K_EN1K</h2>
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<td class="memname">#define CONF_CORE_CLK_XOSC32K_EN1K   (0)</td>
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<p>XOSC32K 1KHz Output Control</p><ul>
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<li>0 => 1KHz output is disabled.</li>
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<li>1 => 1KHz output is enabled. <br />
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See <a href="https://ww1.microchip.com/downloads/en/DeviceDoc/SAM_D5xE5x_Family_Data_Sheet_DS60001507F.pdf#page=749">Datasheet Reference</a> </li>
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<p class="definition">Definition at line <a class="el" href="conf__core_8h_source.html#l00329">329</a> of file <a class="el" href="conf__core_8h_source.html">conf_core.h</a>.</p>
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<a id="ae9fbb8d05dc5808f510eae4e8a629826"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#ae9fbb8d05dc5808f510eae4e8a629826">◆ </a></span>CONF_CORE_CLK_XOSC32K_EN32K</h2>
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<td class="memname">#define CONF_CORE_CLK_XOSC32K_EN32K   (1)</td>
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<p>XOSC32K 32KHz Output Control</p><ul>
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<li>0 => 32KHz output is disabled.</li>
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<li>1 => 32KHz output is enabled. <br />
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See <a href="https://ww1.microchip.com/downloads/en/DeviceDoc/SAM_D5xE5x_Family_Data_Sheet_DS60001507F.pdf#page=749">Datasheet Reference</a> </li>
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<p class="definition">Definition at line <a class="el" href="conf__core_8h_source.html#l00336">336</a> of file <a class="el" href="conf__core_8h_source.html">conf_core.h</a>.</p>
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<a id="accf341cf268c0883a3d862b98667bc9c"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#accf341cf268c0883a3d862b98667bc9c">◆ </a></span>CONF_CORE_CLK_XOSC32K_ENABLE</h2>
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<td class="memname">#define CONF_CORE_CLK_XOSC32K_ENABLE   (1)</td>
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<p>Enables or Disables XOSC32K. </p>
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<p>XOSC32K Enable</p><ul>
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<li>0 => The oscillator is disabled.</li>
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<li>1 => The oscillator is enabled. <br />
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See <a href="https://ww1.microchip.com/downloads/en/DeviceDoc/SAM_D5xE5x_Family_Data_Sheet_DS60001507F.pdf#page=749">Datasheet Reference</a> </li>
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</ul>
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<p class="definition">Definition at line <a class="el" href="conf__core_8h_source.html#l00284">284</a> of file <a class="el" href="conf__core_8h_source.html">conf_core.h</a>.</p>
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<a id="a8d70a30b50febec035af6b982daac395"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#a8d70a30b50febec035af6b982daac395">◆ </a></span>CONF_CORE_CLK_XOSC32K_ONDEMAND</h2>
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<td class="memname">#define CONF_CORE_CLK_XOSC32K_ONDEMAND   (1)</td>
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<p>This bit controls how XOSC32K behaves when a peripheral clock request is detected. </p>
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<p>XOSC32K On Demand Control</p><ul>
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<li>0 => On Demand Control disabled</li>
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<li>1 => On Demand Control enabled <br />
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See <a href="https://ww1.microchip.com/downloads/en/DeviceDoc/SAM_D5xE5x_Family_Data_Sheet_DS60001507F.pdf#page=748">Datasheet Reference</a> </li>
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</ul>
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<p class="definition">Definition at line <a class="el" href="conf__core_8h_source.html#l00314">314</a> of file <a class="el" href="conf__core_8h_source.html">conf_core.h</a>.</p>
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<a id="adc7a2f161e9e8e54388b1f290066247e"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#adc7a2f161e9e8e54388b1f290066247e">◆ </a></span>CONF_CORE_CLK_XOSC32K_RUNSTDBY</h2>
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<td class="memname">#define CONF_CORE_CLK_XOSC32K_RUNSTDBY   (0)</td>
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<p>This bit controls how XOSC32K behaves during standby sleep mode. </p>
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<p>XOSC32K Run in Standby</p><ul>
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<li>0 => Run if requested by peripheral.</li>
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<li>1 => Run if requested by peripheral OR always run depending ONDEMAND value. <br />
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See <a href="https://ww1.microchip.com/downloads/en/DeviceDoc/SAM_D5xE5x_Family_Data_Sheet_DS60001507F.pdf#page=748">Datasheet Reference</a> </li>
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</ul>
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<p class="definition">Definition at line <a class="el" href="conf__core_8h_source.html#l00322">322</a> of file <a class="el" href="conf__core_8h_source.html">conf_core.h</a>.</p>
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<a id="a314b78ee48f1ecf6c40f4bad7ef63d9d"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#a314b78ee48f1ecf6c40f4bad7ef63d9d">◆ </a></span>CONF_CORE_CLK_XOSC32K_STARTUP_TIME</h2>
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<td class="memname">#define CONF_CORE_CLK_XOSC32K_STARTUP_TIME   CONF_CORE_CLK_XOSC32KCTRL_STARTUP_62592us</td>
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<p>These bits select the startup time for the oscillator. </p>
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<p>XOSC32K Startup Time</p><ul>
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<li>0x00 => 62.592ms</li>
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<li>0x01 => 125.092ms</li>
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<li>0x02 => 500.092ms</li>
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<li>0x03 => 1000.0092ms</li>
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<li>0x04 => 2000.0092ms</li>
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<li>0x05 => 4000.0092ms</li>
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<li>0x06 => 8000.0092ms <br />
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See <a href="https://ww1.microchip.com/downloads/en/DeviceDoc/SAM_D5xE5x_Family_Data_Sheet_DS60001507F.pdf#page=748">Datasheet Reference</a> </li>
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</ul>
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<p class="definition">Definition at line <a class="el" href="conf__core_8h_source.html#l00306">306</a> of file <a class="el" href="conf__core_8h_source.html">conf_core.h</a>.</p>
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<a id="ac6e671eee4ca4aeb9fcbb87d52b457b5"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#ac6e671eee4ca4aeb9fcbb87d52b457b5">◆ </a></span>CONF_CORE_CLK_XOSC32K_SWBACK</h2>
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<td class="memname">#define CONF_CORE_CLK_XOSC32K_SWBACK   (0)</td>
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<p>This bit controls the XOSC32K output switch back to the external clock or crystal oscillator in case of clock recovery. </p>
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<p>XOSC32K Clock Switch Back</p><ul>
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<li>0 => The clock switch is disabled.</li>
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<li>1 => The clock switch is enabled. This bit is reset when XOSC32K output is switched back to the external clock or crystal oscillator. <br />
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See <a href="https://ww1.microchip.com/downloads/en/DeviceDoc/SAM_D5xE5x_Family_Data_Sheet_DS60001507F.pdf#page=750">Datasheet Reference</a> </li>
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<p class="definition">Definition at line <a class="el" href="conf__core_8h_source.html#l00368">368</a> of file <a class="el" href="conf__core_8h_source.html">conf_core.h</a>.</p>
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<a id="a42b0270d2f3c0f51c4b3d2b8ac397fda"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#a42b0270d2f3c0f51c4b3d2b8ac397fda">◆ </a></span>CONF_CORE_CLK_XOSC32K_WRTLOCK</h2>
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<td class="memname">#define CONF_CORE_CLK_XOSC32K_WRTLOCK   (0)</td>
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<p>This bit locks the XOSC32K register for future writes, effectively freezing the XOSC32K configuration. </p>
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<p>XOSC32K Write Lock</p><ul>
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<li>0 => XOSC32K configuration is not locked.</li>
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<li>1 => XOSC32K configuration is locked. <br />
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See <a href="https://ww1.microchip.com/downloads/en/DeviceDoc/SAM_D5xE5x_Family_Data_Sheet_DS60001507F.pdf#page=748">Datasheet Reference</a> </li>
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<p class="definition">Definition at line <a class="el" href="conf__core_8h_source.html#l00376">376</a> of file <a class="el" href="conf__core_8h_source.html">conf_core.h</a>.</p>
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<a id="a6a65a6f4bf7e21dc2003b61a7045e24a"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#a6a65a6f4bf7e21dc2003b61a7045e24a">◆ </a></span>CONF_CORE_CLK_XOSC32K_XTALEN</h2>
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<td class="memname">#define CONF_CORE_CLK_XOSC32K_XTALEN   (1)</td>
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<p>This bit controls the connections between the I/O pads and the external clock or crystal oscillator. </p>
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<p>XOSC32K Crystal Oscillator Enable</p><ul>
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<li>0 => External clock is connected on XIN32. XOUT32 can be used as general-purpose I/O.</li>
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<li>1 => Crystal connected to XIN32/XOUT32. <br />
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See <a href="https://ww1.microchip.com/downloads/en/DeviceDoc/SAM_D5xE5x_Family_Data_Sheet_DS60001507F.pdf#page=749">Datasheet Reference</a> </li>
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<p class="definition">Definition at line <a class="el" href="conf__core_8h_source.html#l00344">344</a> of file <a class="el" href="conf__core_8h_source.html">conf_core.h</a>.</p>
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<a id="a81edcdaa3908cc3d99a95047e4431405"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#a81edcdaa3908cc3d99a95047e4431405">◆ </a></span>CONF_CORE_CMCC_ENABLE</h2>
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<td class="memname">#define CONF_CORE_CMCC_ENABLE   (0)</td>
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<p>Define whether the CMCC (Cortex-M Cache Controller) is enabled or not.</p><ul>
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<li>0 => Disabled</li>
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<li>1 => Enabled </li>
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<p class="definition">Definition at line <a class="el" href="conf__core_8h_source.html#l00055">55</a> of file <a class="el" href="conf__core_8h_source.html">conf_core.h</a>.</p>
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<a id="a16a34b830edda5b571c41a0f865f7051"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#a16a34b830edda5b571c41a0f865f7051">◆ </a></span>CONF_CORE_DMA_ENABLE</h2>
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<td class="memname">#define CONF_CORE_DMA_ENABLE   (0)</td>
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<p>Define whether the DMAC is enabled or not.</p><ul>
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<li>0 => Disabled</li>
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<li>1 => Enabled <br />
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See <a href="https://ww1.microchip.com/downloads/en/DeviceDoc/SAM_D5xE5x_Family_Data_Sheet_DS60001507F.pdf#page=172">Datasheet Reference</a> </li>
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<p class="definition">Definition at line <a class="el" href="conf__core_8h_source.html#l00048">48</a> of file <a class="el" href="conf__core_8h_source.html">conf_core.h</a>.</p>
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<a id="aa9643e96439d0d47e0684a4b11c1f529"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#aa9643e96439d0d47e0684a4b11c1f529">◆ </a></span>CONF_CORE_MCLK_CPUDIV</h2>
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<td class="memname">#define CONF_CORE_MCLK_CPUDIV   0x1</td>
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<p>Define the master clock divisor. </p>
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<ul>
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<li>0x1 => Clock Divide by 1</li>
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<li>0x2 => Clock Divide by 2</li>
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<li>0x4 => Clock Divide by 4</li>
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<li>0x8 => Clock Divide by 8</li>
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<li>0x10 => Clock Divide by 16</li>
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<li>0x20 => Clock Divide by 32</li>
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<li>0x40 => Clock Divide by 64</li>
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<li>0x80 => Clock Divide by 128 <br />
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See <a href="https://ww1.microchip.com/downloads/en/DeviceDoc/SAM_D5xE5x_Family_Data_Sheet_DS60001507F.pdf#page=170">Datasheet Reference</a> </li>
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<p class="definition">Definition at line <a class="el" href="conf__core_8h_source.html#l00038">38</a> of file <a class="el" href="conf__core_8h_source.html">conf_core.h</a>.</p>
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<h2 class="memtitle"><span class="permalink"><a href="#a4e846249cdbec567989afa93b6653671">◆ </a></span>CONF_CORE_PORT_EVCTRL_0_ENABLE</h2>
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<td class="memname">#define CONF_CORE_PORT_EVCTRL_0_ENABLE   (0)</td>
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<p>Currently Unused </p>
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<p class="definition">Definition at line <a class="el" href="conf__core_8h_source.html#l00058">58</a> of file <a class="el" href="conf__core_8h_source.html">conf_core.h</a>.</p>
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<a id="ab1c71bf1f1249ce9046aca27329ae588"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#ab1c71bf1f1249ce9046aca27329ae588">◆ </a></span>CONF_CORE_PORT_EVCTRL_1_ENABLE</h2>
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<p>Currently Unused </p>
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<p class="definition">Definition at line <a class="el" href="conf__core_8h_source.html#l00060">60</a> of file <a class="el" href="conf__core_8h_source.html">conf_core.h</a>.</p>
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<a id="a7971c1d952e35ecc50ae18de2b2c48ed"></a>
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<h2 class="memtitle"><span class="permalink"><a href="#a7971c1d952e35ecc50ae18de2b2c48ed">◆ </a></span>CONF_CORE_PORT_EVCTRL_2_ENABLE</h2>
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<td class="memname">#define CONF_CORE_PORT_EVCTRL_2_ENABLE   (0)</td>
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<p>Currently Unused </p>
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<p class="definition">Definition at line <a class="el" href="conf__core_8h_source.html#l00062">62</a> of file <a class="el" href="conf__core_8h_source.html">conf_core.h</a>.</p>
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