Browse Source

working on core module for same54

stable
penguin 1 year ago
parent
commit
f8fca08efe
100 changed files with 39307 additions and 25256 deletions
  1. +2
    -2
      arch/arm/SAMD21/SAMD21A/scripts/samd21j18a.cfg
  2. +0
    -163
      arch/arm/SAME54/SAME54A/ld/same54n19a_flash.ld
  3. +0
    -162
      arch/arm/SAME54/SAME54A/ld/same54n19a_sram.ld
  4. +0
    -163
      arch/arm/SAME54/SAME54A/ld/same54n20a_flash.ld
  5. +0
    -162
      arch/arm/SAME54/SAME54A/ld/same54n20a_sram.ld
  6. +0
    -163
      arch/arm/SAME54/SAME54A/ld/same54p19a_flash.ld
  7. +0
    -162
      arch/arm/SAME54/SAME54A/ld/same54p19a_sram.ld
  8. +1
    -1
      arch/arm/SAME54/SAME54A/manifest/same54a.toml
  9. +64
    -64
      arch/arm/SAME54/SAME54A/mcu/inc/component-version.h
  10. +598
    -410
      arch/arm/SAME54/SAME54A/mcu/inc/component/ac.h
  11. +871
    -649
      arch/arm/SAME54/SAME54A/mcu/inc/component/adc.h
  12. +375
    -276
      arch/arm/SAME54/SAME54A/mcu/inc/component/aes.h
  13. +3187
    -2527
      arch/arm/SAME54/SAME54A/mcu/inc/component/can.h
  14. +228
    -217
      arch/arm/SAME54/SAME54A/mcu/inc/component/ccl.h
  15. +357
    -247
      arch/arm/SAME54/SAME54A/mcu/inc/component/cmcc.h
  16. +544
    -439
      arch/arm/SAME54/SAME54A/mcu/inc/component/dac.h
  17. +1416
    -1125
      arch/arm/SAME54/SAME54A/mcu/inc/component/dmac.h
  18. +647
    -445
      arch/arm/SAME54/SAME54A/mcu/inc/component/dsu.h
  19. +497
    -421
      arch/arm/SAME54/SAME54A/mcu/inc/component/eic.h
  20. +587
    -452
      arch/arm/SAME54/SAME54A/mcu/inc/component/evsys.h
  21. +233
    -150
      arch/arm/SAME54/SAME54A/mcu/inc/component/freqm.h
  22. +272
    -188
      arch/arm/SAME54/SAME54A/mcu/inc/component/gclk.h
  23. +2593
    -1680
      arch/arm/SAME54/SAME54A/mcu/inc/component/gmac.h
  24. +84
    -66
      arch/arm/SAME54/SAME54A/mcu/inc/component/hmatrixb.h
  25. +747
    -596
      arch/arm/SAME54/SAME54A/mcu/inc/component/i2s.h
  26. +582
    -409
      arch/arm/SAME54/SAME54A/mcu/inc/component/icm.h
  27. +482
    -429
      arch/arm/SAME54/SAME54A/mcu/inc/component/mclk.h
  28. +787
    -526
      arch/arm/SAME54/SAME54A/mcu/inc/component/nvmctrl.h
  29. +303
    -222
      arch/arm/SAME54/SAME54A/mcu/inc/component/osc32kctrl.h
  30. +793
    -692
      arch/arm/SAME54/SAME54A/mcu/inc/component/oscctrl.h
  31. +686
    -645
      arch/arm/SAME54/SAME54A/mcu/inc/component/pac.h
  32. +251
    -169
      arch/arm/SAME54/SAME54A/mcu/inc/component/pcc.h
  33. +726
    -521
      arch/arm/SAME54/SAME54A/mcu/inc/component/pdec.h
  34. +1321
    -0
      arch/arm/SAME54/SAME54A/mcu/inc/component/picop.h
  35. +261
    -194
      arch/arm/SAME54/SAME54A/mcu/inc/component/pm.h
  36. +414
    -281
      arch/arm/SAME54/SAME54A/mcu/inc/component/port.h
  37. +0
    -39
      arch/arm/SAME54/SAME54A/mcu/inc/component/pukcc.h
  38. +528
    -383
      arch/arm/SAME54/SAME54A/mcu/inc/component/qspi.h
  39. +178
    -120
      arch/arm/SAME54/SAME54A/mcu/inc/component/ramecc.h
  40. +115
    -89
      arch/arm/SAME54/SAME54A/mcu/inc/component/rstc.h
  41. +2098
    -1683
      arch/arm/SAME54/SAME54A/mcu/inc/component/rtc.h
  42. +2599
    -1771
      arch/arm/SAME54/SAME54A/mcu/inc/component/sdhc.h
  43. +1680
    -2200
      arch/arm/SAME54/SAME54A/mcu/inc/component/sercom.h
  44. +435
    -344
      arch/arm/SAME54/SAME54A/mcu/inc/component/supc.h
  45. +851
    -595
      arch/arm/SAME54/SAME54A/mcu/inc/component/tc.h
  46. +1762
    -1396
      arch/arm/SAME54/SAME54A/mcu/inc/component/tcc.h
  47. +172
    -113
      arch/arm/SAME54/SAME54A/mcu/inc/component/trng.h
  48. +1777
    -1282
      arch/arm/SAME54/SAME54A/mcu/inc/component/usb.h
  49. +300
    -223
      arch/arm/SAME54/SAME54A/mcu/inc/component/wdt.h
  50. +79
    -0
      arch/arm/SAME54/SAME54A/mcu/inc/instance/ac.h
  51. +99
    -0
      arch/arm/SAME54/SAME54A/mcu/inc/instance/adc0.h
  52. +100
    -0
      arch/arm/SAME54/SAME54A/mcu/inc/instance/adc1.h
  53. +105
    -0
      arch/arm/SAME54/SAME54A/mcu/inc/instance/aes.h
  54. +139
    -0
      arch/arm/SAME54/SAME54A/mcu/inc/instance/can0.h
  55. +139
    -0
      arch/arm/SAME54/SAME54A/mcu/inc/instance/can1.h
  56. +57
    -0
      arch/arm/SAME54/SAME54A/mcu/inc/instance/ccl.h
  57. +61
    -0
      arch/arm/SAME54/SAME54A/mcu/inc/instance/cmcc.h
  58. +88
    -0
      arch/arm/SAME54/SAME54A/mcu/inc/instance/dac.h
  59. +596
    -0
      arch/arm/SAME54/SAME54A/mcu/inc/instance/dmac.h
  60. +95
    -0
      arch/arm/SAME54/SAME54A/mcu/inc/instance/dsu.h
  61. +73
    -0
      arch/arm/SAME54/SAME54A/mcu/inc/instance/eic.h
  62. +720
    -0
      arch/arm/SAME54/SAME54A/mcu/inc/instance/evsys.h
  63. +59
    -0
      arch/arm/SAME54/SAME54A/mcu/inc/instance/freqm.h
  64. +191
    -0
      arch/arm/SAME54/SAME54A/mcu/inc/instance/gclk.h
  65. +263
    -0
      arch/arm/SAME54/SAME54A/mcu/inc/instance/gmac.h
  66. +133
    -0
      arch/arm/SAME54/SAME54A/mcu/inc/instance/hmatrix.h
  67. +81
    -0
      arch/arm/SAME54/SAME54A/mcu/inc/instance/i2s.h
  68. +77
    -0
      arch/arm/SAME54/SAME54A/mcu/inc/instance/icm.h
  69. +61
    -0
      arch/arm/SAME54/SAME54A/mcu/inc/instance/mclk.h
  70. +75
    -0
      arch/arm/SAME54/SAME54A/mcu/inc/instance/nvmctrl.h
  71. +59
    -0
      arch/arm/SAME54/SAME54A/mcu/inc/instance/osc32kctrl.h
  72. +130
    -0
      arch/arm/SAME54/SAME54A/mcu/inc/instance/oscctrl.h
  73. +69
    -0
      arch/arm/SAME54/SAME54A/mcu/inc/instance/pac.h
  74. +58
    -0
      arch/arm/SAME54/SAME54A/mcu/inc/instance/pcc.h
  75. +80
    -0
      arch/arm/SAME54/SAME54A/mcu/inc/instance/pdec.h
  76. +147
    -0
      arch/arm/SAME54/SAME54A/mcu/inc/instance/picop.h
  77. +59
    -0
      arch/arm/SAME54/SAME54A/mcu/inc/instance/pm.h
  78. +184
    -0
      arch/arm/SAME54/SAME54A/mcu/inc/instance/port.h
  79. +38
    -0
      arch/arm/SAME54/SAME54A/mcu/inc/instance/pukcc.h
  80. +72
    -0
      arch/arm/SAME54/SAME54A/mcu/inc/instance/qspi.h
  81. +54
    -0
      arch/arm/SAME54/SAME54A/mcu/inc/instance/ramecc.h
  82. +48
    -0
      arch/arm/SAME54/SAME54A/mcu/inc/instance/rstc.h
  83. +156
    -0
      arch/arm/SAME54/SAME54A/mcu/inc/instance/rtc.h
  84. +147
    -0
      arch/arm/SAME54/SAME54A/mcu/inc/instance/sdhc0.h
  85. +147
    -0
      arch/arm/SAME54/SAME54A/mcu/inc/instance/sdhc1.h
  86. +181
    -0
      arch/arm/SAME54/SAME54A/mcu/inc/instance/sercom0.h
  87. +181
    -0
      arch/arm/SAME54/SAME54A/mcu/inc/instance/sercom1.h
  88. +181
    -0
      arch/arm/SAME54/SAME54A/mcu/inc/instance/sercom2.h
  89. +181
    -0
      arch/arm/SAME54/SAME54A/mcu/inc/instance/sercom3.h
  90. +181
    -0
      arch/arm/SAME54/SAME54A/mcu/inc/instance/sercom4.h
  91. +181
    -0
      arch/arm/SAME54/SAME54A/mcu/inc/instance/sercom5.h
  92. +181
    -0
      arch/arm/SAME54/SAME54A/mcu/inc/instance/sercom6.h
  93. +181
    -0
      arch/arm/SAME54/SAME54A/mcu/inc/instance/sercom7.h
  94. +62
    -0
      arch/arm/SAME54/SAME54A/mcu/inc/instance/supc.h
  95. +109
    -0
      arch/arm/SAME54/SAME54A/mcu/inc/instance/tc0.h
  96. +109
    -0
      arch/arm/SAME54/SAME54A/mcu/inc/instance/tc1.h
  97. +109
    -0
      arch/arm/SAME54/SAME54A/mcu/inc/instance/tc2.h
  98. +109
    -0
      arch/arm/SAME54/SAME54A/mcu/inc/instance/tc3.h
  99. +109
    -0
      arch/arm/SAME54/SAME54A/mcu/inc/instance/tc4.h
  100. +109
    -0
      arch/arm/SAME54/SAME54A/mcu/inc/instance/tc5.h

+ 2
- 2
arch/arm/SAMD21/SAMD21A/scripts/samd21j18a.cfg View File

@@ -4,9 +4,9 @@


# Transport Select
source [find interface//jlink.cfg]
source [find interface/jlink.cfg]
transport select swd

# Chip Information
set CHIPNAME samd21j18a
source [find target//at91samdXX.cfg]
source [find target/at91samdXX.cfg]

+ 0
- 163
arch/arm/SAME54/SAME54A/ld/same54n19a_flash.ld View File

@@ -1,163 +0,0 @@
/**
* \file
*
* \brief Linker script for running in internal FLASH on the SAME54N19A
*
* Copyright (c) 2019 Microchip Technology Inc.
*
* \asf_license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \asf_license_stop
*
*/
OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
OUTPUT_ARCH(arm)
SEARCH_DIR(.)
/* Memory Spaces Definitions */
MEMORY
{
rom (rx) : ORIGIN = 0x00000000, LENGTH = 0x00080000
ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00030000
bkupram (rwx) : ORIGIN = 0x47000000, LENGTH = 0x00002000
qspi (rwx) : ORIGIN = 0x04000000, LENGTH = 0x01000000
}
/* The stack size used by the application. NOTE: you need to adjust according to your application. */
STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0xC000;
/* Section Definitions */
SECTIONS
{
.text :
{
. = ALIGN(4);
_sfixed = .;
KEEP(*(.vectors .vectors.*))
*(.text .text.* .gnu.linkonce.t.*)
*(.glue_7t) *(.glue_7)
*(.rodata .rodata* .gnu.linkonce.r.*)
*(.ARM.extab* .gnu.linkonce.armextab.*)
/* Support C constructors, and C destructors in both user code
and the C library. This also provides support for C++ code. */
. = ALIGN(4);
KEEP(*(.init))
. = ALIGN(4);
__preinit_array_start = .;
KEEP (*(.preinit_array))
__preinit_array_end = .;
. = ALIGN(4);
__init_array_start = .;
KEEP (*(SORT(.init_array.*)))
KEEP (*(.init_array))
__init_array_end = .;
. = ALIGN(4);
KEEP (*crtbegin.o(.ctors))
KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
KEEP (*(SORT(.ctors.*)))
KEEP (*crtend.o(.ctors))
. = ALIGN(4);
KEEP(*(.fini))
. = ALIGN(4);
__fini_array_start = .;
KEEP (*(.fini_array))
KEEP (*(SORT(.fini_array.*)))
__fini_array_end = .;
KEEP (*crtbegin.o(.dtors))
KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
KEEP (*(SORT(.dtors.*)))
KEEP (*crtend.o(.dtors))
. = ALIGN(4);
_efixed = .; /* End of text section */
} > rom
/* .ARM.exidx is sorted, so has to go in its own output section. */
PROVIDE_HIDDEN (__exidx_start = .);
.ARM.exidx :
{
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
} > rom
PROVIDE_HIDDEN (__exidx_end = .);
. = ALIGN(4);
_etext = .;
.relocate : AT (_etext)
{
. = ALIGN(4);
_srelocate = .;
*(.ramfunc .ramfunc.*);
*(.data .data.*);
. = ALIGN(4);
_erelocate = .;
} > ram
.bkupram (NOLOAD):
{
. = ALIGN(8);
_sbkupram = .;
*(.bkupram .bkupram.*);
. = ALIGN(8);
_ebkupram = .;
} > bkupram
.qspi (NOLOAD):
{
. = ALIGN(8);
_sqspi = .;
*(.qspi .qspi.*);
. = ALIGN(8);
_eqspi = .;
} > qspi
/* .bss section which is used for uninitialized data */
.bss (NOLOAD) :
{
. = ALIGN(4);
_sbss = . ;
_szero = .;
*(.bss .bss.*)
*(COMMON)
. = ALIGN(4);
_ebss = . ;
_ezero = .;
} > ram
/* stack section */
.stack (NOLOAD):
{
. = ALIGN(8);
_sstack = .;
. = . + STACK_SIZE;
. = ALIGN(8);
_estack = .;
} > ram
. = ALIGN(4);
_end = . ;
}

+ 0
- 162
arch/arm/SAME54/SAME54A/ld/same54n19a_sram.ld View File

@@ -1,162 +0,0 @@
/**
* \file
*
* \brief Linker script for running in internal SRAM on the SAME54N19A
*
* Copyright (c) 2019 Microchip Technology Inc.
*
* \asf_license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \asf_license_stop
*
*/
OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
OUTPUT_ARCH(arm)
SEARCH_DIR(.)
/* Memory Spaces Definitions */
MEMORY
{
ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00030000
bkupram (rwx) : ORIGIN = 0x47000000, LENGTH = 0x00002000
qspi (rwx) : ORIGIN = 0x04000000, LENGTH = 0x01000000
}
/* The stack size used by the application. NOTE: you need to adjust according to your application. */
STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0xC000;
/* Section Definitions */
SECTIONS
{
.text :
{
. = ALIGN(4);
_sfixed = .;
KEEP(*(.vectors .vectors.*))
*(.text .text.* .gnu.linkonce.t.*)
*(.glue_7t) *(.glue_7)
*(.rodata .rodata* .gnu.linkonce.r.*)
*(.ARM.extab* .gnu.linkonce.armextab.*)
/* Support C constructors, and C destructors in both user code
and the C library. This also provides support for C++ code. */
. = ALIGN(4);
KEEP(*(.init))
. = ALIGN(4);
__preinit_array_start = .;
KEEP (*(.preinit_array))
__preinit_array_end = .;
. = ALIGN(4);
__init_array_start = .;
KEEP (*(SORT(.init_array.*)))
KEEP (*(.init_array))
__init_array_end = .;
. = ALIGN(4);
KEEP (*crtbegin.o(.ctors))
KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
KEEP (*(SORT(.ctors.*)))
KEEP (*crtend.o(.ctors))
. = ALIGN(4);
KEEP(*(.fini))
. = ALIGN(4);
__fini_array_start = .;
KEEP (*(.fini_array))
KEEP (*(SORT(.fini_array.*)))
__fini_array_end = .;
KEEP (*crtbegin.o(.dtors))
KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
KEEP (*(SORT(.dtors.*)))
KEEP (*crtend.o(.dtors))
. = ALIGN(4);
_efixed = .; /* End of text section */
} > ram
/* .ARM.exidx is sorted, so has to go in its own output section. */
PROVIDE_HIDDEN (__exidx_start = .);
.ARM.exidx :
{
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
} > ram
PROVIDE_HIDDEN (__exidx_end = .);
. = ALIGN(4);
_etext = .;
.relocate : AT (_etext)
{
. = ALIGN(4);
_srelocate = .;
*(.ramfunc .ramfunc.*);
*(.data .data.*);
. = ALIGN(4);
_erelocate = .;
} > ram
.bkupram (NOLOAD):
{
. = ALIGN(8);
_sbkupram = .;
*(.bkupram .bkupram.*);
. = ALIGN(8);
_ebkupram = .;
} > bkupram
.qspi (NOLOAD):
{
. = ALIGN(8);
_sqspi = .;
*(.qspi .qspi.*);
. = ALIGN(8);
_eqspi = .;
} > qspi
/* .bss section which is used for uninitialized data */
.bss (NOLOAD) :
{
. = ALIGN(4);
_sbss = . ;
_szero = .;
*(.bss .bss.*)
*(COMMON)
. = ALIGN(4);
_ebss = . ;
_ezero = .;
} > ram
/* stack section */
.stack (NOLOAD):
{
. = ALIGN(8);
_sstack = .;
. = . + STACK_SIZE;
. = ALIGN(8);
_estack = .;
} > ram
. = ALIGN(4);
_end = . ;
}

+ 0
- 163
arch/arm/SAME54/SAME54A/ld/same54n20a_flash.ld View File

@@ -1,163 +0,0 @@
/**
* \file
*
* \brief Linker script for running in internal FLASH on the SAME54N20A
*
* Copyright (c) 2019 Microchip Technology Inc.
*
* \asf_license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \asf_license_stop
*
*/
OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
OUTPUT_ARCH(arm)
SEARCH_DIR(.)
/* Memory Spaces Definitions */
MEMORY
{
rom (rx) : ORIGIN = 0x00000000, LENGTH = 0x00100000
ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00040000
bkupram (rwx) : ORIGIN = 0x47000000, LENGTH = 0x00002000
qspi (rwx) : ORIGIN = 0x04000000, LENGTH = 0x01000000
}
/* The stack size used by the application. NOTE: you need to adjust according to your application. */
STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x10000;
/* Section Definitions */
SECTIONS
{
.text :
{
. = ALIGN(4);
_sfixed = .;
KEEP(*(.vectors .vectors.*))
*(.text .text.* .gnu.linkonce.t.*)
*(.glue_7t) *(.glue_7)
*(.rodata .rodata* .gnu.linkonce.r.*)
*(.ARM.extab* .gnu.linkonce.armextab.*)
/* Support C constructors, and C destructors in both user code
and the C library. This also provides support for C++ code. */
. = ALIGN(4);
KEEP(*(.init))
. = ALIGN(4);
__preinit_array_start = .;
KEEP (*(.preinit_array))
__preinit_array_end = .;
. = ALIGN(4);
__init_array_start = .;
KEEP (*(SORT(.init_array.*)))
KEEP (*(.init_array))
__init_array_end = .;
. = ALIGN(4);
KEEP (*crtbegin.o(.ctors))
KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
KEEP (*(SORT(.ctors.*)))
KEEP (*crtend.o(.ctors))
. = ALIGN(4);
KEEP(*(.fini))
. = ALIGN(4);
__fini_array_start = .;
KEEP (*(.fini_array))
KEEP (*(SORT(.fini_array.*)))
__fini_array_end = .;
KEEP (*crtbegin.o(.dtors))
KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
KEEP (*(SORT(.dtors.*)))
KEEP (*crtend.o(.dtors))
. = ALIGN(4);
_efixed = .; /* End of text section */
} > rom
/* .ARM.exidx is sorted, so has to go in its own output section. */
PROVIDE_HIDDEN (__exidx_start = .);
.ARM.exidx :
{
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
} > rom
PROVIDE_HIDDEN (__exidx_end = .);
. = ALIGN(4);
_etext = .;
.relocate : AT (_etext)
{
. = ALIGN(4);
_srelocate = .;
*(.ramfunc .ramfunc.*);
*(.data .data.*);
. = ALIGN(4);
_erelocate = .;
} > ram
.bkupram (NOLOAD):
{
. = ALIGN(8);
_sbkupram = .;
*(.bkupram .bkupram.*);
. = ALIGN(8);
_ebkupram = .;
} > bkupram
.qspi (NOLOAD):
{
. = ALIGN(8);
_sqspi = .;
*(.qspi .qspi.*);
. = ALIGN(8);
_eqspi = .;
} > qspi
/* .bss section which is used for uninitialized data */
.bss (NOLOAD) :
{
. = ALIGN(4);
_sbss = . ;
_szero = .;
*(.bss .bss.*)
*(COMMON)
. = ALIGN(4);
_ebss = . ;
_ezero = .;
} > ram
/* stack section */
.stack (NOLOAD):
{
. = ALIGN(8);
_sstack = .;
. = . + STACK_SIZE;
. = ALIGN(8);
_estack = .;
} > ram
. = ALIGN(4);
_end = . ;
}

+ 0
- 162
arch/arm/SAME54/SAME54A/ld/same54n20a_sram.ld View File

@@ -1,162 +0,0 @@
/**
* \file
*
* \brief Linker script for running in internal SRAM on the SAME54N20A
*
* Copyright (c) 2019 Microchip Technology Inc.
*
* \asf_license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \asf_license_stop
*
*/
OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
OUTPUT_ARCH(arm)
SEARCH_DIR(.)
/* Memory Spaces Definitions */
MEMORY
{
ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00040000
bkupram (rwx) : ORIGIN = 0x47000000, LENGTH = 0x00002000
qspi (rwx) : ORIGIN = 0x04000000, LENGTH = 0x01000000
}
/* The stack size used by the application. NOTE: you need to adjust according to your application. */
STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x10000;
/* Section Definitions */
SECTIONS
{
.text :
{
. = ALIGN(4);
_sfixed = .;
KEEP(*(.vectors .vectors.*))
*(.text .text.* .gnu.linkonce.t.*)
*(.glue_7t) *(.glue_7)
*(.rodata .rodata* .gnu.linkonce.r.*)
*(.ARM.extab* .gnu.linkonce.armextab.*)
/* Support C constructors, and C destructors in both user code
and the C library. This also provides support for C++ code. */
. = ALIGN(4);
KEEP(*(.init))
. = ALIGN(4);
__preinit_array_start = .;
KEEP (*(.preinit_array))
__preinit_array_end = .;
. = ALIGN(4);
__init_array_start = .;
KEEP (*(SORT(.init_array.*)))
KEEP (*(.init_array))
__init_array_end = .;
. = ALIGN(4);
KEEP (*crtbegin.o(.ctors))
KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
KEEP (*(SORT(.ctors.*)))
KEEP (*crtend.o(.ctors))
. = ALIGN(4);
KEEP(*(.fini))
. = ALIGN(4);
__fini_array_start = .;
KEEP (*(.fini_array))
KEEP (*(SORT(.fini_array.*)))
__fini_array_end = .;
KEEP (*crtbegin.o(.dtors))
KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
KEEP (*(SORT(.dtors.*)))
KEEP (*crtend.o(.dtors))
. = ALIGN(4);
_efixed = .; /* End of text section */
} > ram
/* .ARM.exidx is sorted, so has to go in its own output section. */
PROVIDE_HIDDEN (__exidx_start = .);
.ARM.exidx :
{
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
} > ram
PROVIDE_HIDDEN (__exidx_end = .);
. = ALIGN(4);
_etext = .;
.relocate : AT (_etext)
{
. = ALIGN(4);
_srelocate = .;
*(.ramfunc .ramfunc.*);
*(.data .data.*);
. = ALIGN(4);
_erelocate = .;
} > ram
.bkupram (NOLOAD):
{
. = ALIGN(8);
_sbkupram = .;
*(.bkupram .bkupram.*);
. = ALIGN(8);
_ebkupram = .;
} > bkupram
.qspi (NOLOAD):
{
. = ALIGN(8);
_sqspi = .;
*(.qspi .qspi.*);
. = ALIGN(8);
_eqspi = .;
} > qspi
/* .bss section which is used for uninitialized data */
.bss (NOLOAD) :
{
. = ALIGN(4);
_sbss = . ;
_szero = .;
*(.bss .bss.*)
*(COMMON)
. = ALIGN(4);
_ebss = . ;
_ezero = .;
} > ram
/* stack section */
.stack (NOLOAD):
{
. = ALIGN(8);
_sstack = .;
. = . + STACK_SIZE;
. = ALIGN(8);
_estack = .;
} > ram
. = ALIGN(4);
_end = . ;
}

+ 0
- 163
arch/arm/SAME54/SAME54A/ld/same54p19a_flash.ld View File

@@ -1,163 +0,0 @@
/**
* \file
*
* \brief Linker script for running in internal FLASH on the SAME54P19A
*
* Copyright (c) 2019 Microchip Technology Inc.
*
* \asf_license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \asf_license_stop
*
*/
OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
OUTPUT_ARCH(arm)
SEARCH_DIR(.)
/* Memory Spaces Definitions */
MEMORY
{
rom (rx) : ORIGIN = 0x00000000, LENGTH = 0x00080000
ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00030000
bkupram (rwx) : ORIGIN = 0x47000000, LENGTH = 0x00002000
qspi (rwx) : ORIGIN = 0x04000000, LENGTH = 0x01000000
}
/* The stack size used by the application. NOTE: you need to adjust according to your application. */
STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0xC000;
/* Section Definitions */
SECTIONS
{
.text :
{
. = ALIGN(4);
_sfixed = .;
KEEP(*(.vectors .vectors.*))
*(.text .text.* .gnu.linkonce.t.*)
*(.glue_7t) *(.glue_7)
*(.rodata .rodata* .gnu.linkonce.r.*)
*(.ARM.extab* .gnu.linkonce.armextab.*)
/* Support C constructors, and C destructors in both user code
and the C library. This also provides support for C++ code. */
. = ALIGN(4);
KEEP(*(.init))
. = ALIGN(4);
__preinit_array_start = .;
KEEP (*(.preinit_array))
__preinit_array_end = .;
. = ALIGN(4);
__init_array_start = .;
KEEP (*(SORT(.init_array.*)))
KEEP (*(.init_array))
__init_array_end = .;
. = ALIGN(4);
KEEP (*crtbegin.o(.ctors))
KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
KEEP (*(SORT(.ctors.*)))
KEEP (*crtend.o(.ctors))
. = ALIGN(4);
KEEP(*(.fini))
. = ALIGN(4);
__fini_array_start = .;
KEEP (*(.fini_array))
KEEP (*(SORT(.fini_array.*)))
__fini_array_end = .;
KEEP (*crtbegin.o(.dtors))
KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
KEEP (*(SORT(.dtors.*)))
KEEP (*crtend.o(.dtors))
. = ALIGN(4);
_efixed = .; /* End of text section */
} > rom
/* .ARM.exidx is sorted, so has to go in its own output section. */
PROVIDE_HIDDEN (__exidx_start = .);
.ARM.exidx :
{
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
} > rom
PROVIDE_HIDDEN (__exidx_end = .);
. = ALIGN(4);
_etext = .;
.relocate : AT (_etext)
{
. = ALIGN(4);
_srelocate = .;
*(.ramfunc .ramfunc.*);
*(.data .data.*);
. = ALIGN(4);
_erelocate = .;
} > ram
.bkupram (NOLOAD):
{
. = ALIGN(8);
_sbkupram = .;
*(.bkupram .bkupram.*);
. = ALIGN(8);
_ebkupram = .;
} > bkupram
.qspi (NOLOAD):
{
. = ALIGN(8);
_sqspi = .;
*(.qspi .qspi.*);
. = ALIGN(8);
_eqspi = .;
} > qspi
/* .bss section which is used for uninitialized data */
.bss (NOLOAD) :
{
. = ALIGN(4);
_sbss = . ;
_szero = .;
*(.bss .bss.*)
*(COMMON)
. = ALIGN(4);
_ebss = . ;
_ezero = .;
} > ram
/* stack section */
.stack (NOLOAD):
{
. = ALIGN(8);
_sstack = .;
. = . + STACK_SIZE;
. = ALIGN(8);
_estack = .;
} > ram
. = ALIGN(4);
_end = . ;
}

+ 0
- 162
arch/arm/SAME54/SAME54A/ld/same54p19a_sram.ld View File

@@ -1,162 +0,0 @@
/**
* \file
*
* \brief Linker script for running in internal SRAM on the SAME54P19A
*
* Copyright (c) 2019 Microchip Technology Inc.
*
* \asf_license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \asf_license_stop
*
*/
OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
OUTPUT_ARCH(arm)
SEARCH_DIR(.)
/* Memory Spaces Definitions */
MEMORY
{
ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00030000
bkupram (rwx) : ORIGIN = 0x47000000, LENGTH = 0x00002000
qspi (rwx) : ORIGIN = 0x04000000, LENGTH = 0x01000000
}
/* The stack size used by the application. NOTE: you need to adjust according to your application. */
STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0xC000;
/* Section Definitions */
SECTIONS
{
.text :
{
. = ALIGN(4);
_sfixed = .;
KEEP(*(.vectors .vectors.*))
*(.text .text.* .gnu.linkonce.t.*)
*(.glue_7t) *(.glue_7)
*(.rodata .rodata* .gnu.linkonce.r.*)
*(.ARM.extab* .gnu.linkonce.armextab.*)
/* Support C constructors, and C destructors in both user code
and the C library. This also provides support for C++ code. */
. = ALIGN(4);
KEEP(*(.init))
. = ALIGN(4);
__preinit_array_start = .;
KEEP (*(.preinit_array))
__preinit_array_end = .;
. = ALIGN(4);
__init_array_start = .;
KEEP (*(SORT(.init_array.*)))
KEEP (*(.init_array))
__init_array_end = .;
. = ALIGN(4);
KEEP (*crtbegin.o(.ctors))
KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
KEEP (*(SORT(.ctors.*)))
KEEP (*crtend.o(.ctors))
. = ALIGN(4);
KEEP(*(.fini))
. = ALIGN(4);
__fini_array_start = .;
KEEP (*(.fini_array))
KEEP (*(SORT(.fini_array.*)))
__fini_array_end = .;
KEEP (*crtbegin.o(.dtors))
KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
KEEP (*(SORT(.dtors.*)))
KEEP (*crtend.o(.dtors))
. = ALIGN(4);
_efixed = .; /* End of text section */
} > ram
/* .ARM.exidx is sorted, so has to go in its own output section. */
PROVIDE_HIDDEN (__exidx_start = .);
.ARM.exidx :
{
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
} > ram
PROVIDE_HIDDEN (__exidx_end = .);
. = ALIGN(4);
_etext = .;
.relocate : AT (_etext)
{
. = ALIGN(4);
_srelocate = .;
*(.ramfunc .ramfunc.*);
*(.data .data.*);
. = ALIGN(4);
_erelocate = .;
} > ram
.bkupram (NOLOAD):
{
. = ALIGN(8);
_sbkupram = .;
*(.bkupram .bkupram.*);
. = ALIGN(8);
_ebkupram = .;
} > bkupram
.qspi (NOLOAD):
{
. = ALIGN(8);
_sqspi = .;
*(.qspi .qspi.*);
. = ALIGN(8);
_eqspi = .;
} > qspi
/* .bss section which is used for uninitialized data */
.bss (NOLOAD) :
{
. = ALIGN(4);
_sbss = . ;
_szero = .;
*(.bss .bss.*)
*(COMMON)
. = ALIGN(4);
_ebss = . ;
_ezero = .;
} > ram
/* stack section */
.stack (NOLOAD):
{
. = ALIGN(8);
_sstack = .;
. = . + STACK_SIZE;
. = ALIGN(8);
_estack = .;
} > ram
. = ALIGN(4);
_end = . ;
}

+ 1
- 1
arch/arm/SAME54/SAME54A/manifest/same54a.toml View File

@@ -3,9 +3,9 @@ common = "arch/arm/common"
mcu = "arch/arm/SAME54/SAME54A/mcu/"
ld = "arch/arm/SAME54/SAME54A/ld/"
cfg = "arch/arm/SAME54/SAME54A/manifest/"

[esf.includes]
IGLOO_INCLUDES = ["sam.h"]

# These are defaults. Once a project is generated, the .cfg can be freely edited without fear of anything being overwritten. However, I do not recommend editing any of the _cfg variables.
[esf.openocd]
scripts = "arch/arm/SAME54/SAME54A/scripts/"

+ 64
- 64
arch/arm/SAME54/SAME54A/mcu/inc/component-version.h View File

@@ -1,64 +1,64 @@
/**
* \file
*
* \brief Component version header file
*
* Copyright (c) 2020 Atmel Corporation, a wholly owned subsidiary of Microchip Technology Inc.
*
* \license_start
*
* \page License
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \license_stop
*
*/
#ifndef _COMPONENT_VERSION_H_INCLUDED
#define _COMPONENT_VERSION_H_INCLUDED
#define COMPONENT_VERSION_MAJOR 3
#define COMPONENT_VERSION_MINOR 3
//
// The COMPONENT_VERSION define is composed of the major and the minor version number.
//
// The last four digits of the COMPONENT_VERSION is the minor version with leading zeros.
// The rest of the COMPONENT_VERSION is the major version.
//
#define COMPONENT_VERSION 30003
//
// The build number does not refer to the component, but to the build number
// of the device pack that provides the component.
//
#define BUILD_NUMBER 64
//
// The COMPONENT_VERSION_STRING is a string (enclosed in ") that can be used for logging or embedding.
//
#define COMPONENT_VERSION_STRING "3.3"
//
// The COMPONENT_DATE_STRING contains a timestamp of when the pack was generated.
//
// The COMPONENT_DATE_STRING is written out using the following strftime pattern.
//
// "%Y-%m-%d %H:%M:%S"
//
//
#define COMPONENT_DATE_STRING "2020-04-28 23:52:31"
#endif/* #ifndef _COMPONENT_VERSION_H_INCLUDED */
/**
* \file
*
* \brief Component version header file
*
* Copyright (c) 2019 Atmel Corporation, a wholly owned subsidiary of Microchip Technology Inc.
*
* \license_start
*
* \page License
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \license_stop
*
*/
#ifndef _COMPONENT_VERSION_H_INCLUDED
#define _COMPONENT_VERSION_H_INCLUDED
#define COMPONENT_VERSION_MAJOR 1
#define COMPONENT_VERSION_MINOR 1
//
// The COMPONENT_VERSION define is composed of the major and the minor version number.
//
// The last four digits of the COMPONENT_VERSION is the minor version with leading zeros.
// The rest of the COMPONENT_VERSION is the major version.
//
#define COMPONENT_VERSION 10001
//
// The build number does not refer to the component, but to the build number
// of the device pack that provides the component.
//
#define BUILD_NUMBER 134
//
// The COMPONENT_VERSION_STRING is a string (enclosed in ") that can be used for logging or embedding.
//
#define COMPONENT_VERSION_STRING "1.1"
//
// The COMPONENT_DATE_STRING contains a timestamp of when the pack was generated.
//
// The COMPONENT_DATE_STRING is written out using the following strftime pattern.
//
// "%Y-%m-%d %H:%M:%S"
//
//
#define COMPONENT_DATE_STRING "2019-04-09 08:16:19"
#endif/* #ifndef _COMPONENT_VERSION_H_INCLUDED */

+ 598
- 410
arch/arm/SAME54/SAME54A/mcu/inc/component/ac.h
File diff suppressed because it is too large
View File


+ 871
- 649
arch/arm/SAME54/SAME54A/mcu/inc/component/adc.h
File diff suppressed because it is too large
View File


+ 375
- 276
arch/arm/SAME54/SAME54A/mcu/inc/component/aes.h View File

@@ -1,276 +1,375 @@
/**
* \brief Component description for AES
*
* Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries.
*
* Subject to your compliance with these terms, you may use Microchip software and any derivatives
* exclusively with Microchip products. It is your responsibility to comply with third party license
* terms applicable to your use of third party software (including open source software) that may
* accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY,
* APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND
* FITNESS FOR A PARTICULAR PURPOSE.
*
* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF
* MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT
* EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
*/

/* file generated from device description version 2020-03-12T17:27:04Z */
#ifndef _SAME54_AES_COMPONENT_H_
#define _SAME54_AES_COMPONENT_H_

/* ************************************************************************** */
/* SOFTWARE API DEFINITION FOR AES */
/* ************************************************************************** */

/* -------- AES_CTRLA : (AES Offset: 0x00) (R/W 32) Control A -------- */
#define AES_CTRLA_RESETVALUE _U_(0x00) /**< (AES_CTRLA) Control A Reset Value */

#define AES_CTRLA_SWRST_Pos _U_(0) /**< (AES_CTRLA) Software Reset Position */
#define AES_CTRLA_SWRST_Msk (_U_(0x1) << AES_CTRLA_SWRST_Pos) /**< (AES_CTRLA) Software Reset Mask */
#define AES_CTRLA_SWRST(value) (AES_CTRLA_SWRST_Msk & ((value) << AES_CTRLA_SWRST_Pos))
#define AES_CTRLA_ENABLE_Pos _U_(1) /**< (AES_CTRLA) Enable Position */
#define AES_CTRLA_ENABLE_Msk (_U_(0x1) << AES_CTRLA_ENABLE_Pos) /**< (AES_CTRLA) Enable Mask */
#define AES_CTRLA_ENABLE(value) (AES_CTRLA_ENABLE_Msk & ((value) << AES_CTRLA_ENABLE_Pos))
#define AES_CTRLA_AESMODE_Pos _U_(2) /**< (AES_CTRLA) AES Modes of operation Position */
#define AES_CTRLA_AESMODE_Msk (_U_(0x7) << AES_CTRLA_AESMODE_Pos) /**< (AES_CTRLA) AES Modes of operation Mask */
#define AES_CTRLA_AESMODE(value) (AES_CTRLA_AESMODE_Msk & ((value) << AES_CTRLA_AESMODE_Pos))
#define AES_CTRLA_AESMODE_ECB_Val _U_(0x0) /**< (AES_CTRLA) Electronic code book mode */
#define AES_CTRLA_AESMODE_CBC_Val _U_(0x1) /**< (AES_CTRLA) Cipher block chaining mode */
#define AES_CTRLA_AESMODE_OFB_Val _U_(0x2) /**< (AES_CTRLA) Output feedback mode */
#define AES_CTRLA_AESMODE_CFB_Val _U_(0x3) /**< (AES_CTRLA) Cipher feedback mode */
#define AES_CTRLA_AESMODE_COUNTER_Val _U_(0x4) /**< (AES_CTRLA) Counter mode */
#define AES_CTRLA_AESMODE_CCM_Val _U_(0x5) /**< (AES_CTRLA) CCM mode */
#define AES_CTRLA_AESMODE_GCM_Val _U_(0x6) /**< (AES_CTRLA) Galois counter mode */
#define AES_CTRLA_AESMODE_ECB (AES_CTRLA_AESMODE_ECB_Val << AES_CTRLA_AESMODE_Pos) /**< (AES_CTRLA) Electronic code book mode Position */
#define AES_CTRLA_AESMODE_CBC (AES_CTRLA_AESMODE_CBC_Val << AES_CTRLA_AESMODE_Pos) /**< (AES_CTRLA) Cipher block chaining mode Position */
#define AES_CTRLA_AESMODE_OFB (AES_CTRLA_AESMODE_OFB_Val << AES_CTRLA_AESMODE_Pos) /**< (AES_CTRLA) Output feedback mode Position */
#define AES_CTRLA_AESMODE_CFB (AES_CTRLA_AESMODE_CFB_Val << AES_CTRLA_AESMODE_Pos) /**< (AES_CTRLA) Cipher feedback mode Position */
#define AES_CTRLA_AESMODE_COUNTER (AES_CTRLA_AESMODE_COUNTER_Val << AES_CTRLA_AESMODE_Pos) /**< (AES_CTRLA) Counter mode Position */
#define AES_CTRLA_AESMODE_CCM (AES_CTRLA_AESMODE_CCM_Val << AES_CTRLA_AESMODE_Pos) /**< (AES_CTRLA) CCM mode Position */
#define AES_CTRLA_AESMODE_GCM (AES_CTRLA_AESMODE_GCM_Val << AES_CTRLA_AESMODE_Pos) /**< (AES_CTRLA) Galois counter mode Position */
#define AES_CTRLA_CFBS_Pos _U_(5) /**< (AES_CTRLA) Cipher Feedback Block Size Position */
#define AES_CTRLA_CFBS_Msk (_U_(0x7) << AES_CTRLA_CFBS_Pos) /**< (AES_CTRLA) Cipher Feedback Block Size Mask */
#define AES_CTRLA_CFBS(value) (AES_CTRLA_CFBS_Msk & ((value) << AES_CTRLA_CFBS_Pos))
#define AES_CTRLA_CFBS_128BIT_Val _U_(0x0) /**< (AES_CTRLA) 128-bit Input data block for Encryption/Decryption in Cipher Feedback mode */
#define AES_CTRLA_CFBS_64BIT_Val _U_(0x1) /**< (AES_CTRLA) 64-bit Input data block for Encryption/Decryption in Cipher Feedback mode */
#define AES_CTRLA_CFBS_32BIT_Val _U_(0x2) /**< (AES_CTRLA) 32-bit Input data block for Encryption/Decryption in Cipher Feedback mode */
#define AES_CTRLA_CFBS_16BIT_Val _U_(0x3) /**< (AES_CTRLA) 16-bit Input data block for Encryption/Decryption in Cipher Feedback mode */
#define AES_CTRLA_CFBS_8BIT_Val _U_(0x4) /**< (AES_CTRLA) 8-bit Input data block for Encryption/Decryption in Cipher Feedback mode */
#define AES_CTRLA_CFBS_128BIT (AES_CTRLA_CFBS_128BIT_Val << AES_CTRLA_CFBS_Pos) /**< (AES_CTRLA) 128-bit Input data block for Encryption/Decryption in Cipher Feedback mode Position */
#define AES_CTRLA_CFBS_64BIT (AES_CTRLA_CFBS_64BIT_Val << AES_CTRLA_CFBS_Pos) /**< (AES_CTRLA) 64-bit Input data block for Encryption/Decryption in Cipher Feedback mode Position */
#define AES_CTRLA_CFBS_32BIT (AES_CTRLA_CFBS_32BIT_Val << AES_CTRLA_CFBS_Pos) /**< (AES_CTRLA) 32-bit Input data block for Encryption/Decryption in Cipher Feedback mode Position */
#define AES_CTRLA_CFBS_16BIT (AES_CTRLA_CFBS_16BIT_Val << AES_CTRLA_CFBS_Pos) /**< (AES_CTRLA) 16-bit Input data block for Encryption/Decryption in Cipher Feedback mode Position */
#define AES_CTRLA_CFBS_8BIT (AES_CTRLA_CFBS_8BIT_Val << AES_CTRLA_CFBS_Pos) /**< (AES_CTRLA) 8-bit Input data block for Encryption/Decryption in Cipher Feedback mode Position */
#define AES_CTRLA_KEYSIZE_Pos _U_(8) /**< (AES_CTRLA) Encryption Key Size Position */
#define AES_CTRLA_KEYSIZE_Msk (_U_(0x3) << AES_CTRLA_KEYSIZE_Pos) /**< (AES_CTRLA) Encryption Key Size Mask */
#define AES_CTRLA_KEYSIZE(value) (AES_CTRLA_KEYSIZE_Msk & ((value) << AES_CTRLA_KEYSIZE_Pos))
#define AES_CTRLA_KEYSIZE_128BIT_Val _U_(0x0) /**< (AES_CTRLA) 128-bit Key for Encryption / Decryption */
#define AES_CTRLA_KEYSIZE_192BIT_Val _U_(0x1) /**< (AES_CTRLA) 192-bit Key for Encryption / Decryption */
#define AES_CTRLA_KEYSIZE_256BIT_Val _U_(0x2) /**< (AES_CTRLA) 256-bit Key for Encryption / Decryption */
#define AES_CTRLA_KEYSIZE_128BIT (AES_CTRLA_KEYSIZE_128BIT_Val << AES_CTRLA_KEYSIZE_Pos) /**< (AES_CTRLA) 128-bit Key for Encryption / Decryption Position */
#define AES_CTRLA_KEYSIZE_192BIT (AES_CTRLA_KEYSIZE_192BIT_Val << AES_CTRLA_KEYSIZE_Pos) /**< (AES_CTRLA) 192-bit Key for Encryption / Decryption Position */
#define AES_CTRLA_KEYSIZE_256BIT (AES_CTRLA_KEYSIZE_256BIT_Val << AES_CTRLA_KEYSIZE_Pos) /**< (AES_CTRLA) 256-bit Key for Encryption / Decryption Position */
#define AES_CTRLA_CIPHER_Pos _U_(10) /**< (AES_CTRLA) Cipher Mode Position */
#define AES_CTRLA_CIPHER_Msk (_U_(0x1) << AES_CTRLA_CIPHER_Pos) /**< (AES_CTRLA) Cipher Mode Mask */
#define AES_CTRLA_CIPHER(value) (AES_CTRLA_CIPHER_Msk & ((value) << AES_CTRLA_CIPHER_Pos))
#define AES_CTRLA_CIPHER_DEC_Val _U_(0x0) /**< (AES_CTRLA) Decryption */
#define AES_CTRLA_CIPHER_ENC_Val _U_(0x1) /**< (AES_CTRLA) Encryption */
#define AES_CTRLA_CIPHER_DEC (AES_CTRLA_CIPHER_DEC_Val << AES_CTRLA_CIPHER_Pos) /**< (AES_CTRLA) Decryption Position */
#define AES_CTRLA_CIPHER_ENC (AES_CTRLA_CIPHER_ENC_Val << AES_CTRLA_CIPHER_Pos) /**< (AES_CTRLA) Encryption Position */
#define AES_CTRLA_STARTMODE_Pos _U_(11) /**< (AES_CTRLA) Start Mode Select Position */
#define AES_CTRLA_STARTMODE_Msk (_U_(0x1) << AES_CTRLA_STARTMODE_Pos) /**< (AES_CTRLA) Start Mode Select Mask */
#define AES_CTRLA_STARTMODE(value) (AES_CTRLA_STARTMODE_Msk & ((value) << AES_CTRLA_STARTMODE_Pos))
#define AES_CTRLA_STARTMODE_MANUAL_Val _U_(0x0) /**< (AES_CTRLA) Start Encryption / Decryption in Manual mode */
#define AES_CTRLA_STARTMODE_AUTO_Val _U_(0x1) /**< (AES_CTRLA) Start Encryption / Decryption in Auto mode */
#define AES_CTRLA_STARTMODE_MANUAL (AES_CTRLA_STARTMODE_MANUAL_Val << AES_CTRLA_STARTMODE_Pos) /**< (AES_CTRLA) Start Encryption / Decryption in Manual mode Position */
#define AES_CTRLA_STARTMODE_AUTO (AES_CTRLA_STARTMODE_AUTO_Val << AES_CTRLA_STARTMODE_Pos) /**< (AES_CTRLA) Start Encryption / Decryption in Auto mode Position */
#define AES_CTRLA_LOD_Pos _U_(12) /**< (AES_CTRLA) Last Output Data Mode Position */
#define AES_CTRLA_LOD_Msk (_U_(0x1) << AES_CTRLA_LOD_Pos) /**< (AES_CTRLA) Last Output Data Mode Mask */
#define AES_CTRLA_LOD(value) (AES_CTRLA_LOD_Msk & ((value) << AES_CTRLA_LOD_Pos))
#define AES_CTRLA_LOD_NONE_Val _U_(0x0) /**< (AES_CTRLA) No effect */
#define AES_CTRLA_LOD_LAST_Val _U_(0x1) /**< (AES_CTRLA) Start encryption in Last Output Data mode */
#define AES_CTRLA_LOD_NONE (AES_CTRLA_LOD_NONE_Val << AES_CTRLA_LOD_Pos) /**< (AES_CTRLA) No effect Position */
#define AES_CTRLA_LOD_LAST (AES_CTRLA_LOD_LAST_Val << AES_CTRLA_LOD_Pos) /**< (AES_CTRLA) Start encryption in Last Output Data mode Position */
#define AES_CTRLA_KEYGEN_Pos _U_(13) /**< (AES_CTRLA) Last Key Generation Position */
#define AES_CTRLA_KEYGEN_Msk (_U_(0x1) << AES_CTRLA_KEYGEN_Pos) /**< (AES_CTRLA) Last Key Generation Mask */
#define AES_CTRLA_KEYGEN(value) (AES_CTRLA_KEYGEN_Msk & ((value) << AES_CTRLA_KEYGEN_Pos))
#define AES_CTRLA_KEYGEN_NONE_Val _U_(0x0) /**< (AES_CTRLA) No effect */
#define AES_CTRLA_KEYGEN_LAST_Val _U_(0x1) /**< (AES_CTRLA) Start Computation of the last NK words of the expanded key */
#define AES_CTRLA_KEYGEN_NONE (AES_CTRLA_KEYGEN_NONE_Val << AES_CTRLA_KEYGEN_Pos) /**< (AES_CTRLA) No effect Position */
#define AES_CTRLA_KEYGEN_LAST (AES_CTRLA_KEYGEN_LAST_Val << AES_CTRLA_KEYGEN_Pos) /**< (AES_CTRLA) Start Computation of the last NK words of the expanded key Position */
#define AES_CTRLA_XORKEY_Pos _U_(14) /**< (AES_CTRLA) XOR Key Operation Position */
#define AES_CTRLA_XORKEY_Msk (_U_(0x1) << AES_CTRLA_XORKEY_Pos) /**< (AES_CTRLA) XOR Key Operation Mask */
#define AES_CTRLA_XORKEY(value) (AES_CTRLA_XORKEY_Msk & ((value) << AES_CTRLA_XORKEY_Pos))
#define AES_CTRLA_XORKEY_NONE_Val _U_(0x0) /**< (AES_CTRLA) No effect */
#define AES_CTRLA_XORKEY_XOR_Val _U_(0x1) /**< (AES_CTRLA) The user keyword gets XORed with the previous keyword register content. */
#define AES_CTRLA_XORKEY_NONE (AES_CTRLA_XORKEY_NONE_Val << AES_CTRLA_XORKEY_Pos) /**< (AES_CTRLA) No effect Position */
#define AES_CTRLA_XORKEY_XOR (AES_CTRLA_XORKEY_XOR_Val << AES_CTRLA_XORKEY_Pos) /**< (AES_CTRLA) The user keyword gets XORed with the previous keyword register content. Position */
#define AES_CTRLA_CTYPE_Pos _U_(16) /**< (AES_CTRLA) Counter Measure Type Position */
#define AES_CTRLA_CTYPE_Msk (_U_(0xF) << AES_CTRLA_CTYPE_Pos) /**< (AES_CTRLA) Counter Measure Type Mask */
#define AES_CTRLA_CTYPE(value) (AES_CTRLA_CTYPE_Msk & ((value) << AES_CTRLA_CTYPE_Pos))
#define AES_CTRLA_Msk _U_(0x000F7FFF) /**< (AES_CTRLA) Register Mask */


/* -------- AES_CTRLB : (AES Offset: 0x04) (R/W 8) Control B -------- */
#define AES_CTRLB_RESETVALUE _U_(0x00) /**< (AES_CTRLB) Control B Reset Value */

#define AES_CTRLB_START_Pos _U_(0) /**< (AES_CTRLB) Start Encryption/Decryption Position */
#define AES_CTRLB_START_Msk (_U_(0x1) << AES_CTRLB_START_Pos) /**< (AES_CTRLB) Start Encryption/Decryption Mask */
#define AES_CTRLB_START(value) (AES_CTRLB_START_Msk & ((value) << AES_CTRLB_START_Pos))
#define AES_CTRLB_NEWMSG_Pos _U_(1) /**< (AES_CTRLB) New message Position */
#define AES_CTRLB_NEWMSG_Msk (_U_(0x1) << AES_CTRLB_NEWMSG_Pos) /**< (AES_CTRLB) New message Mask */
#define AES_CTRLB_NEWMSG(value) (AES_CTRLB_NEWMSG_Msk & ((value) << AES_CTRLB_NEWMSG_Pos))
#define AES_CTRLB_EOM_Pos _U_(2) /**< (AES_CTRLB) End of message Position */
#define AES_CTRLB_EOM_Msk (_U_(0x1) << AES_CTRLB_EOM_Pos) /**< (AES_CTRLB) End of message Mask */
#define AES_CTRLB_EOM(value) (AES_CTRLB_EOM_Msk & ((value) << AES_CTRLB_EOM_Pos))
#define AES_CTRLB_GFMUL_Pos _U_(3) /**< (AES_CTRLB) GF Multiplication Position */
#define AES_CTRLB_GFMUL_Msk (_U_(0x1) << AES_CTRLB_GFMUL_Pos) /**< (AES_CTRLB) GF Multiplication Mask */
#define AES_CTRLB_GFMUL(value) (AES_CTRLB_GFMUL_Msk & ((value) << AES_CTRLB_GFMUL_Pos))
#define AES_CTRLB_Msk _U_(0x0F) /**< (AES_CTRLB) Register Mask */


/* -------- AES_INTENCLR : (AES Offset: 0x05) (R/W 8) Interrupt Enable Clear -------- */
#define AES_INTENCLR_RESETVALUE _U_(0x00) /**< (AES_INTENCLR) Interrupt Enable Clear Reset Value */

#define AES_INTENCLR_ENCCMP_Pos _U_(0) /**< (AES_INTENCLR) Encryption Complete Interrupt Enable Position */
#define AES_INTENCLR_ENCCMP_Msk (_U_(0x1) << AES_INTENCLR_ENCCMP_Pos) /**< (AES_INTENCLR) Encryption Complete Interrupt Enable Mask */
#define AES_INTENCLR_ENCCMP(value) (AES_INTENCLR_ENCCMP_Msk & ((value) << AES_INTENCLR_ENCCMP_Pos))
#define AES_INTENCLR_GFMCMP_Pos _U_(1) /**< (AES_INTENCLR) GF Multiplication Complete Interrupt Enable Position */
#define AES_INTENCLR_GFMCMP_Msk (_U_(0x1) << AES_INTENCLR_GFMCMP_Pos) /**< (AES_INTENCLR) GF Multiplication Complete Interrupt Enable Mask */
#define AES_INTENCLR_GFMCMP(value) (AES_INTENCLR_GFMCMP_Msk & ((value) << AES_INTENCLR_GFMCMP_Pos))
#define AES_INTENCLR_Msk _U_(0x03) /**< (AES_INTENCLR) Register Mask */


/* -------- AES_INTENSET : (AES Offset: 0x06) (R/W 8) Interrupt Enable Set -------- */
#define AES_INTENSET_RESETVALUE _U_(0x00) /**< (AES_INTENSET) Interrupt Enable Set Reset Value */

#define AES_INTENSET_ENCCMP_Pos _U_(0) /**< (AES_INTENSET) Encryption Complete Interrupt Enable Position */
#define AES_INTENSET_ENCCMP_Msk (_U_(0x1) << AES_INTENSET_ENCCMP_Pos) /**< (AES_INTENSET) Encryption Complete Interrupt Enable Mask */
#define AES_INTENSET_ENCCMP(value) (AES_INTENSET_ENCCMP_Msk & ((value) << AES_INTENSET_ENCCMP_Pos))
#define AES_INTENSET_GFMCMP_Pos _U_(1) /**< (AES_INTENSET) GF Multiplication Complete Interrupt Enable Position */
#define AES_INTENSET_GFMCMP_Msk (_U_(0x1) << AES_INTENSET_GFMCMP_Pos) /**< (AES_INTENSET) GF Multiplication Complete Interrupt Enable Mask */
#define AES_INTENSET_GFMCMP(value) (AES_INTENSET_GFMCMP_Msk & ((value) << AES_INTENSET_GFMCMP_Pos))
#define AES_INTENSET_Msk _U_(0x03) /**< (AES_INTENSET) Register Mask */


/* -------- AES_INTFLAG : (AES Offset: 0x07) (R/W 8) Interrupt Flag Status -------- */
#define AES_INTFLAG_RESETVALUE _U_(0x00) /**< (AES_INTFLAG) Interrupt Flag Status Reset Value */

#define AES_INTFLAG_ENCCMP_Pos _U_(0) /**< (AES_INTFLAG) Encryption Complete Position */
#define AES_INTFLAG_ENCCMP_Msk (_U_(0x1) << AES_INTFLAG_ENCCMP_Pos) /**< (AES_INTFLAG) Encryption Complete Mask */
#define AES_INTFLAG_ENCCMP(value) (AES_INTFLAG_ENCCMP_Msk & ((value) << AES_INTFLAG_ENCCMP_Pos))
#define AES_INTFLAG_GFMCMP_Pos _U_(1) /**< (AES_INTFLAG) GF Multiplication Complete Position */
#define AES_INTFLAG_GFMCMP_Msk (_U_(0x1) << AES_INTFLAG_GFMCMP_Pos) /**< (AES_INTFLAG) GF Multiplication Complete Mask */
#define AES_INTFLAG_GFMCMP(value) (AES_INTFLAG_GFMCMP_Msk & ((value) << AES_INTFLAG_GFMCMP_Pos))
#define AES_INTFLAG_Msk _U_(0x03) /**< (AES_INTFLAG) Register Mask */


/* -------- AES_DATABUFPTR : (AES Offset: 0x08) (R/W 8) Data buffer pointer -------- */
#define AES_DATABUFPTR_RESETVALUE _U_(0x00) /**< (AES_DATABUFPTR) Data buffer pointer Reset Value */

#define AES_DATABUFPTR_INDATAPTR_Pos _U_(0) /**< (AES_DATABUFPTR) Input Data Pointer Position */
#define AES_DATABUFPTR_INDATAPTR_Msk (_U_(0x3) << AES_DATABUFPTR_INDATAPTR_Pos) /**< (AES_DATABUFPTR) Input Data Pointer Mask */
#define AES_DATABUFPTR_INDATAPTR(value) (AES_DATABUFPTR_INDATAPTR_Msk & ((value) << AES_DATABUFPTR_INDATAPTR_Pos))
#define AES_DATABUFPTR_Msk _U_(0x03) /**< (AES_DATABUFPTR) Register Mask */


/* -------- AES_DBGCTRL : (AES Offset: 0x09) (R/W 8) Debug control -------- */
#define AES_DBGCTRL_RESETVALUE _U_(0x00) /**< (AES_DBGCTRL) Debug control Reset Value */

#define AES_DBGCTRL_DBGRUN_Pos _U_(0) /**< (AES_DBGCTRL) Debug Run Position */
#define AES_DBGCTRL_DBGRUN_Msk (_U_(0x1) << AES_DBGCTRL_DBGRUN_Pos) /**< (AES_DBGCTRL) Debug Run Mask */
#define AES_DBGCTRL_DBGRUN(value) (AES_DBGCTRL_DBGRUN_Msk & ((value) << AES_DBGCTRL_DBGRUN_Pos))
#define AES_DBGCTRL_Msk _U_(0x01) /**< (AES_DBGCTRL) Register Mask */


/* -------- AES_KEYWORD : (AES Offset: 0x0C) ( /W 32) Keyword n -------- */
#define AES_KEYWORD_RESETVALUE _U_(0x00) /**< (AES_KEYWORD) Keyword n Reset Value */

#define AES_KEYWORD_Msk _U_(0x00000000) /**< (AES_KEYWORD) Register Mask */


/* -------- AES_INDATA : (AES Offset: 0x38) (R/W 32) Indata -------- */
#define AES_INDATA_RESETVALUE _U_(0x00) /**< (AES_INDATA) Indata Reset Value */

#define AES_INDATA_Msk _U_(0x00000000) /**< (AES_INDATA) Register Mask */


/* -------- AES_INTVECTV : (AES Offset: 0x3C) ( /W 32) Initialisation Vector n -------- */
#define AES_INTVECTV_RESETVALUE _U_(0x00) /**< (AES_INTVECTV) Initialisation Vector n Reset Value */

#define AES_INTVECTV_Msk _U_(0x00000000) /**< (AES_INTVECTV) Register Mask */


/* -------- AES_HASHKEY : (AES Offset: 0x5C) (R/W 32) Hash key n -------- */
#define AES_HASHKEY_RESETVALUE _U_(0x00) /**< (AES_HASHKEY) Hash key n Reset Value */

#define AES_HASHKEY_Msk _U_(0x00000000) /**< (AES_HASHKEY) Register Mask */


/* -------- AES_GHASH : (AES Offset: 0x6C) (R/W 32) Galois Hash n -------- */
#define AES_GHASH_RESETVALUE _U_(0x00) /**< (AES_GHASH) Galois Hash n Reset Value */

#define AES_GHASH_Msk _U_(0x00000000) /**< (AES_GHASH) Register Mask */


/* -------- AES_CIPLEN : (AES Offset: 0x80) (R/W 32) Cipher Length -------- */
#define AES_CIPLEN_RESETVALUE _U_(0x00) /**< (AES_CIPLEN) Cipher Length Reset Value */

#define AES_CIPLEN_Msk _U_(0x00000000) /**< (AES_CIPLEN) Register Mask */


/* -------- AES_RANDSEED : (AES Offset: 0x84) (R/W 32) Random Seed -------- */
#define AES_RANDSEED_RESETVALUE _U_(0x00) /**< (AES_RANDSEED) Random Seed Reset Value */

#define AES_RANDSEED_Msk _U_(0x00000000) /**< (AES_RANDSEED) Register Mask */


/** \brief AES register offsets definitions */
#define AES_CTRLA_REG_OFST (0x00) /**< (AES_CTRLA) Control A Offset */
#define AES_CTRLB_REG_OFST (0x04) /**< (AES_CTRLB) Control B Offset */
#define AES_INTENCLR_REG_OFST (0x05) /**< (AES_INTENCLR) Interrupt Enable Clear Offset */
#define AES_INTENSET_REG_OFST (0x06) /**< (AES_INTENSET) Interrupt Enable Set Offset */
#define AES_INTFLAG_REG_OFST (0x07) /**< (AES_INTFLAG) Interrupt Flag Status Offset */
#define AES_DATABUFPTR_REG_OFST (0x08) /**< (AES_DATABUFPTR) Data buffer pointer Offset */
#define AES_DBGCTRL_REG_OFST (0x09) /**< (AES_DBGCTRL) Debug control Offset */
#define AES_KEYWORD_REG_OFST (0x0C) /**< (AES_KEYWORD) Keyword n Offset */
#define AES_INDATA_REG_OFST (0x38) /**< (AES_INDATA) Indata Offset */
#define AES_INTVECTV_REG_OFST (0x3C) /**< (AES_INTVECTV) Initialisation Vector n Offset */
#define AES_HASHKEY_REG_OFST (0x5C) /**< (AES_HASHKEY) Hash key n Offset */
#define AES_GHASH_REG_OFST (0x6C) /**< (AES_GHASH) Galois Hash n Offset */
#define AES_CIPLEN_REG_OFST (0x80) /**< (AES_CIPLEN) Cipher Length Offset */
#define AES_RANDSEED_REG_OFST (0x84) /**< (AES_RANDSEED) Random Seed Offset */

#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
/** \brief AES register API structure */
typedef struct
{ /* Advanced Encryption Standard */
__IO uint32_t AES_CTRLA; /**< Offset: 0x00 (R/W 32) Control A */
__IO uint8_t AES_CTRLB; /**< Offset: 0x04 (R/W 8) Control B */
__IO uint8_t AES_INTENCLR; /**< Offset: 0x05 (R/W 8) Interrupt Enable Clear */
__IO uint8_t AES_INTENSET; /**< Offset: 0x06 (R/W 8) Interrupt Enable Set */
__IO uint8_t AES_INTFLAG; /**< Offset: 0x07 (R/W 8) Interrupt Flag Status */
__IO uint8_t AES_DATABUFPTR; /**< Offset: 0x08 (R/W 8) Data buffer pointer */
__IO uint8_t AES_DBGCTRL; /**< Offset: 0x09 (R/W 8) Debug control */
__I uint8_t Reserved1[0x02];
__O uint32_t AES_KEYWORD[8]; /**< Offset: 0x0C ( /W 32) Keyword n */
__I uint8_t Reserved2[0x0C];
__IO uint32_t AES_INDATA; /**< Offset: 0x38 (R/W 32) Indata */
__O uint32_t AES_INTVECTV[4]; /**< Offset: 0x3C ( /W 32) Initialisation Vector n */
__I uint8_t Reserved3[0x10];
__IO uint32_t AES_HASHKEY[4]; /**< Offset: 0x5C (R/W 32) Hash key n */
__IO uint32_t AES_GHASH[4]; /**< Offset: 0x6C (R/W 32) Galois Hash n */
__I uint8_t Reserved4[0x04];
__IO uint32_t AES_CIPLEN; /**< Offset: 0x80 (R/W 32) Cipher Length */
__IO uint32_t AES_RANDSEED; /**< Offset: 0x84 (R/W 32) Random Seed */
} aes_registers_t;


#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
#endif /* _SAME54_AES_COMPONENT_H_ */
/**
* \file
*
* \brief Component description for AES
*
* Copyright (c) 2019 Microchip Technology Inc.
*
* \asf_license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \asf_license_stop
*
*/
#ifndef _SAME54_AES_COMPONENT_
#define _SAME54_AES_COMPONENT_
/* ========================================================================== */
/** SOFTWARE API DEFINITION FOR AES */
/* ========================================================================== */
/** \addtogroup SAME54_AES Advanced Encryption Standard */
/*@{*/
#define AES_U2238
#define REV_AES 0x220
/* -------- AES_CTRLA : (AES Offset: 0x00) (R/W 32) Control A -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t SWRST:1; /*!< bit: 0 Software Reset */
uint32_t ENABLE:1; /*!< bit: 1 Enable */
uint32_t AESMODE:3; /*!< bit: 2.. 4 AES Modes of operation */
uint32_t CFBS:3; /*!< bit: 5.. 7 Cipher Feedback Block Size */
uint32_t KEYSIZE:2; /*!< bit: 8.. 9 Encryption Key Size */
uint32_t CIPHER:1; /*!< bit: 10 Cipher Mode */
uint32_t STARTMODE:1; /*!< bit: 11 Start Mode Select */
uint32_t LOD:1; /*!< bit: 12 Last Output Data Mode */
uint32_t KEYGEN:1; /*!< bit: 13 Last Key Generation */
uint32_t XORKEY:1; /*!< bit: 14 XOR Key Operation */
uint32_t :1; /*!< bit: 15 Reserved */
uint32_t CTYPE:4; /*!< bit: 16..19 Counter Measure Type */
uint32_t :12; /*!< bit: 20..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} AES_CTRLA_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define AES_CTRLA_OFFSET 0x00 /**< \brief (AES_CTRLA offset) Control A */
#define AES_CTRLA_RESETVALUE _U_(0x00000000) /**< \brief (AES_CTRLA reset_value) Control A */
#define AES_CTRLA_SWRST_Pos 0 /**< \brief (AES_CTRLA) Software Reset */
#define AES_CTRLA_SWRST (_U_(0x1) << AES_CTRLA_SWRST_Pos)
#define AES_CTRLA_ENABLE_Pos 1 /**< \brief (AES_CTRLA) Enable */
#define AES_CTRLA_ENABLE (_U_(0x1) << AES_CTRLA_ENABLE_Pos)
#define AES_CTRLA_AESMODE_Pos 2 /**< \brief (AES_CTRLA) AES Modes of operation */
#define AES_CTRLA_AESMODE_Msk (_U_(0x7) << AES_CTRLA_AESMODE_Pos)
#define AES_CTRLA_AESMODE(value) (AES_CTRLA_AESMODE_Msk & ((value) << AES_CTRLA_AESMODE_Pos))
#define AES_CTRLA_AESMODE_ECB_Val _U_(0x0) /**< \brief (AES_CTRLA) Electronic code book mode */
#define AES_CTRLA_AESMODE_CBC_Val _U_(0x1) /**< \brief (AES_CTRLA) Cipher block chaining mode */
#define AES_CTRLA_AESMODE_OFB_Val _U_(0x2) /**< \brief (AES_CTRLA) Output feedback mode */
#define AES_CTRLA_AESMODE_CFB_Val _U_(0x3) /**< \brief (AES_CTRLA) Cipher feedback mode */
#define AES_CTRLA_AESMODE_COUNTER_Val _U_(0x4) /**< \brief (AES_CTRLA) Counter mode */
#define AES_CTRLA_AESMODE_CCM_Val _U_(0x5) /**< \brief (AES_CTRLA) CCM mode */
#define AES_CTRLA_AESMODE_GCM_Val _U_(0x6) /**< \brief (AES_CTRLA) Galois counter mode */
#define AES_CTRLA_AESMODE_ECB (AES_CTRLA_AESMODE_ECB_Val << AES_CTRLA_AESMODE_Pos)
#define AES_CTRLA_AESMODE_CBC (AES_CTRLA_AESMODE_CBC_Val << AES_CTRLA_AESMODE_Pos)
#define AES_CTRLA_AESMODE_OFB (AES_CTRLA_AESMODE_OFB_Val << AES_CTRLA_AESMODE_Pos)
#define AES_CTRLA_AESMODE_CFB (AES_CTRLA_AESMODE_CFB_Val << AES_CTRLA_AESMODE_Pos)
#define AES_CTRLA_AESMODE_COUNTER (AES_CTRLA_AESMODE_COUNTER_Val << AES_CTRLA_AESMODE_Pos)
#define AES_CTRLA_AESMODE_CCM (AES_CTRLA_AESMODE_CCM_Val << AES_CTRLA_AESMODE_Pos)
#define AES_CTRLA_AESMODE_GCM (AES_CTRLA_AESMODE_GCM_Val << AES_CTRLA_AESMODE_Pos)
#define AES_CTRLA_CFBS_Pos 5 /**< \brief (AES_CTRLA) Cipher Feedback Block Size */
#define AES_CTRLA_CFBS_Msk (_U_(0x7) << AES_CTRLA_CFBS_Pos)
#define AES_CTRLA_CFBS(value) (AES_CTRLA_CFBS_Msk & ((value) << AES_CTRLA_CFBS_Pos))
#define AES_CTRLA_CFBS_128BIT_Val _U_(0x0) /**< \brief (AES_CTRLA) 128-bit Input data block for Encryption/Decryption in Cipher Feedback mode */
#define AES_CTRLA_CFBS_64BIT_Val _U_(0x1) /**< \brief (AES_CTRLA) 64-bit Input data block for Encryption/Decryption in Cipher Feedback mode */
#define AES_CTRLA_CFBS_32BIT_Val _U_(0x2) /**< \brief (AES_CTRLA) 32-bit Input data block for Encryption/Decryption in Cipher Feedback mode */
#define AES_CTRLA_CFBS_16BIT_Val _U_(0x3) /**< \brief (AES_CTRLA) 16-bit Input data block for Encryption/Decryption in Cipher Feedback mode */
#define AES_CTRLA_CFBS_8BIT_Val _U_(0x4) /**< \brief (AES_CTRLA) 8-bit Input data block for Encryption/Decryption in Cipher Feedback mode */
#define AES_CTRLA_CFBS_128BIT (AES_CTRLA_CFBS_128BIT_Val << AES_CTRLA_CFBS_Pos)
#define AES_CTRLA_CFBS_64BIT (AES_CTRLA_CFBS_64BIT_Val << AES_CTRLA_CFBS_Pos)
#define AES_CTRLA_CFBS_32BIT (AES_CTRLA_CFBS_32BIT_Val << AES_CTRLA_CFBS_Pos)
#define AES_CTRLA_CFBS_16BIT (AES_CTRLA_CFBS_16BIT_Val << AES_CTRLA_CFBS_Pos)
#define AES_CTRLA_CFBS_8BIT (AES_CTRLA_CFBS_8BIT_Val << AES_CTRLA_CFBS_Pos)
#define AES_CTRLA_KEYSIZE_Pos 8 /**< \brief (AES_CTRLA) Encryption Key Size */
#define AES_CTRLA_KEYSIZE_Msk (_U_(0x3) << AES_CTRLA_KEYSIZE_Pos)
#define AES_CTRLA_KEYSIZE(value) (AES_CTRLA_KEYSIZE_Msk & ((value) << AES_CTRLA_KEYSIZE_Pos))
#define AES_CTRLA_KEYSIZE_128BIT_Val _U_(0x0) /**< \brief (AES_CTRLA) 128-bit Key for Encryption / Decryption */
#define AES_CTRLA_KEYSIZE_192BIT_Val _U_(0x1) /**< \brief (AES_CTRLA) 192-bit Key for Encryption / Decryption */
#define AES_CTRLA_KEYSIZE_256BIT_Val _U_(0x2) /**< \brief (AES_CTRLA) 256-bit Key for Encryption / Decryption */
#define AES_CTRLA_KEYSIZE_128BIT (AES_CTRLA_KEYSIZE_128BIT_Val << AES_CTRLA_KEYSIZE_Pos)
#define AES_CTRLA_KEYSIZE_192BIT (AES_CTRLA_KEYSIZE_192BIT_Val << AES_CTRLA_KEYSIZE_Pos)
#define AES_CTRLA_KEYSIZE_256BIT (AES_CTRLA_KEYSIZE_256BIT_Val << AES_CTRLA_KEYSIZE_Pos)
#define AES_CTRLA_CIPHER_Pos 10 /**< \brief (AES_CTRLA) Cipher Mode */
#define AES_CTRLA_CIPHER (_U_(0x1) << AES_CTRLA_CIPHER_Pos)
#define AES_CTRLA_CIPHER_DEC_Val _U_(0x0) /**< \brief (AES_CTRLA) Decryption */
#define AES_CTRLA_CIPHER_ENC_Val _U_(0x1) /**< \brief (AES_CTRLA) Encryption */
#define AES_CTRLA_CIPHER_DEC (AES_CTRLA_CIPHER_DEC_Val << AES_CTRLA_CIPHER_Pos)
#define AES_CTRLA_CIPHER_ENC (AES_CTRLA_CIPHER_ENC_Val << AES_CTRLA_CIPHER_Pos)
#define AES_CTRLA_STARTMODE_Pos 11 /**< \brief (AES_CTRLA) Start Mode Select */
#define AES_CTRLA_STARTMODE (_U_(0x1) << AES_CTRLA_STARTMODE_Pos)
#define AES_CTRLA_STARTMODE_MANUAL_Val _U_(0x0) /**< \brief (AES_CTRLA) Start Encryption / Decryption in Manual mode */
#define AES_CTRLA_STARTMODE_AUTO_Val _U_(0x1) /**< \brief (AES_CTRLA) Start Encryption / Decryption in Auto mode */
#define AES_CTRLA_STARTMODE_MANUAL (AES_CTRLA_STARTMODE_MANUAL_Val << AES_CTRLA_STARTMODE_Pos)
#define AES_CTRLA_STARTMODE_AUTO (AES_CTRLA_STARTMODE_AUTO_Val << AES_CTRLA_STARTMODE_Pos)
#define AES_CTRLA_LOD_Pos 12 /**< \brief (AES_CTRLA) Last Output Data Mode */
#define AES_CTRLA_LOD (_U_(0x1) << AES_CTRLA_LOD_Pos)
#define AES_CTRLA_LOD_NONE_Val _U_(0x0) /**< \brief (AES_CTRLA) No effect */
#define AES_CTRLA_LOD_LAST_Val _U_(0x1) /**< \brief (AES_CTRLA) Start encryption in Last Output Data mode */
#define AES_CTRLA_LOD_NONE (AES_CTRLA_LOD_NONE_Val << AES_CTRLA_LOD_Pos)
#define AES_CTRLA_LOD_LAST (AES_CTRLA_LOD_LAST_Val << AES_CTRLA_LOD_Pos)
#define AES_CTRLA_KEYGEN_Pos 13 /**< \brief (AES_CTRLA) Last Key Generation */
#define AES_CTRLA_KEYGEN (_U_(0x1) << AES_CTRLA_KEYGEN_Pos)
#define AES_CTRLA_KEYGEN_NONE_Val _U_(0x0) /**< \brief (AES_CTRLA) No effect */
#define AES_CTRLA_KEYGEN_LAST_Val _U_(0x1) /**< \brief (AES_CTRLA) Start Computation of the last NK words of the expanded key */
#define AES_CTRLA_KEYGEN_NONE (AES_CTRLA_KEYGEN_NONE_Val << AES_CTRLA_KEYGEN_Pos)
#define AES_CTRLA_KEYGEN_LAST (AES_CTRLA_KEYGEN_LAST_Val << AES_CTRLA_KEYGEN_Pos)
#define AES_CTRLA_XORKEY_Pos 14 /**< \brief (AES_CTRLA) XOR Key Operation */
#define AES_CTRLA_XORKEY (_U_(0x1) << AES_CTRLA_XORKEY_Pos)
#define AES_CTRLA_XORKEY_NONE_Val _U_(0x0) /**< \brief (AES_CTRLA) No effect */
#define AES_CTRLA_XORKEY_XOR_Val _U_(0x1) /**< \brief (AES_CTRLA) The user keyword gets XORed with the previous keyword register content. */
#define AES_CTRLA_XORKEY_NONE (AES_CTRLA_XORKEY_NONE_Val << AES_CTRLA_XORKEY_Pos)
#define AES_CTRLA_XORKEY_XOR (AES_CTRLA_XORKEY_XOR_Val << AES_CTRLA_XORKEY_Pos)
#define AES_CTRLA_CTYPE_Pos 16 /**< \brief (AES_CTRLA) Counter Measure Type */
#define AES_CTRLA_CTYPE_Msk (_U_(0xF) << AES_CTRLA_CTYPE_Pos)
#define AES_CTRLA_CTYPE(value) (AES_CTRLA_CTYPE_Msk & ((value) << AES_CTRLA_CTYPE_Pos))
#define AES_CTRLA_MASK _U_(0x000F7FFF) /**< \brief (AES_CTRLA) MASK Register */
/* -------- AES_CTRLB : (AES Offset: 0x04) (R/W 8) Control B -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t START:1; /*!< bit: 0 Start Encryption/Decryption */
uint8_t NEWMSG:1; /*!< bit: 1 New message */
uint8_t EOM:1; /*!< bit: 2 End of message */
uint8_t GFMUL:1; /*!< bit: 3 GF Multiplication */
uint8_t :4; /*!< bit: 4.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} AES_CTRLB_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define AES_CTRLB_OFFSET 0x04 /**< \brief (AES_CTRLB offset) Control B */
#define AES_CTRLB_RESETVALUE _U_(0x00) /**< \brief (AES_CTRLB reset_value) Control B */
#define AES_CTRLB_START_Pos 0 /**< \brief (AES_CTRLB) Start Encryption/Decryption */
#define AES_CTRLB_START (_U_(0x1) << AES_CTRLB_START_Pos)
#define AES_CTRLB_NEWMSG_Pos 1 /**< \brief (AES_CTRLB) New message */
#define AES_CTRLB_NEWMSG (_U_(0x1) << AES_CTRLB_NEWMSG_Pos)
#define AES_CTRLB_EOM_Pos 2 /**< \brief (AES_CTRLB) End of message */
#define AES_CTRLB_EOM (_U_(0x1) << AES_CTRLB_EOM_Pos)
#define AES_CTRLB_GFMUL_Pos 3 /**< \brief (AES_CTRLB) GF Multiplication */
#define AES_CTRLB_GFMUL (_U_(0x1) << AES_CTRLB_GFMUL_Pos)
#define AES_CTRLB_MASK _U_(0x0F) /**< \brief (AES_CTRLB) MASK Register */
/* -------- AES_INTENCLR : (AES Offset: 0x05) (R/W 8) Interrupt Enable Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t ENCCMP:1; /*!< bit: 0 Encryption Complete Interrupt Enable */
uint8_t GFMCMP:1; /*!< bit: 1 GF Multiplication Complete Interrupt Enable */
uint8_t :6; /*!< bit: 2.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} AES_INTENCLR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define AES_INTENCLR_OFFSET 0x05 /**< \brief (AES_INTENCLR offset) Interrupt Enable Clear */
#define AES_INTENCLR_RESETVALUE _U_(0x00) /**< \brief (AES_INTENCLR reset_value) Interrupt Enable Clear */
#define AES_INTENCLR_ENCCMP_Pos 0 /**< \brief (AES_INTENCLR) Encryption Complete Interrupt Enable */
#define AES_INTENCLR_ENCCMP (_U_(0x1) << AES_INTENCLR_ENCCMP_Pos)
#define AES_INTENCLR_GFMCMP_Pos 1 /**< \brief (AES_INTENCLR) GF Multiplication Complete Interrupt Enable */
#define AES_INTENCLR_GFMCMP (_U_(0x1) << AES_INTENCLR_GFMCMP_Pos)
#define AES_INTENCLR_MASK _U_(0x03) /**< \brief (AES_INTENCLR) MASK Register */
/* -------- AES_INTENSET : (AES Offset: 0x06) (R/W 8) Interrupt Enable Set -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t ENCCMP:1; /*!< bit: 0 Encryption Complete Interrupt Enable */
uint8_t GFMCMP:1; /*!< bit: 1 GF Multiplication Complete Interrupt Enable */
uint8_t :6; /*!< bit: 2.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} AES_INTENSET_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define AES_INTENSET_OFFSET 0x06 /**< \brief (AES_INTENSET offset) Interrupt Enable Set */
#define AES_INTENSET_RESETVALUE _U_(0x00) /**< \brief (AES_INTENSET reset_value) Interrupt Enable Set */
#define AES_INTENSET_ENCCMP_Pos 0 /**< \brief (AES_INTENSET) Encryption Complete Interrupt Enable */
#define AES_INTENSET_ENCCMP (_U_(0x1) << AES_INTENSET_ENCCMP_Pos)
#define AES_INTENSET_GFMCMP_Pos 1 /**< \brief (AES_INTENSET) GF Multiplication Complete Interrupt Enable */
#define AES_INTENSET_GFMCMP (_U_(0x1) << AES_INTENSET_GFMCMP_Pos)
#define AES_INTENSET_MASK _U_(0x03) /**< \brief (AES_INTENSET) MASK Register */
/* -------- AES_INTFLAG : (AES Offset: 0x07) (R/W 8) Interrupt Flag Status -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union { // __I to avoid read-modify-write on write-to-clear register
struct {
__I uint8_t ENCCMP:1; /*!< bit: 0 Encryption Complete */
__I uint8_t GFMCMP:1; /*!< bit: 1 GF Multiplication Complete */
__I uint8_t :6; /*!< bit: 2.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} AES_INTFLAG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define AES_INTFLAG_OFFSET 0x07 /**< \brief (AES_INTFLAG offset) Interrupt Flag Status */
#define AES_INTFLAG_RESETVALUE _U_(0x00) /**< \brief (AES_INTFLAG reset_value) Interrupt Flag Status */
#define AES_INTFLAG_ENCCMP_Pos 0 /**< \brief (AES_INTFLAG) Encryption Complete */
#define AES_INTFLAG_ENCCMP (_U_(0x1) << AES_INTFLAG_ENCCMP_Pos)
#define AES_INTFLAG_GFMCMP_Pos 1 /**< \brief (AES_INTFLAG) GF Multiplication Complete */
#define AES_INTFLAG_GFMCMP (_U_(0x1) << AES_INTFLAG_GFMCMP_Pos)
#define AES_INTFLAG_MASK _U_(0x03) /**< \brief (AES_INTFLAG) MASK Register */
/* -------- AES_DATABUFPTR : (AES Offset: 0x08) (R/W 8) Data buffer pointer -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t INDATAPTR:2; /*!< bit: 0.. 1 Input Data Pointer */
uint8_t :6; /*!< bit: 2.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} AES_DATABUFPTR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define AES_DATABUFPTR_OFFSET 0x08 /**< \brief (AES_DATABUFPTR offset) Data buffer pointer */
#define AES_DATABUFPTR_RESETVALUE _U_(0x00) /**< \brief (AES_DATABUFPTR reset_value) Data buffer pointer */
#define AES_DATABUFPTR_INDATAPTR_Pos 0 /**< \brief (AES_DATABUFPTR) Input Data Pointer */
#define AES_DATABUFPTR_INDATAPTR_Msk (_U_(0x3) << AES_DATABUFPTR_INDATAPTR_Pos)
#define AES_DATABUFPTR_INDATAPTR(value) (AES_DATABUFPTR_INDATAPTR_Msk & ((value) << AES_DATABUFPTR_INDATAPTR_Pos))
#define AES_DATABUFPTR_MASK _U_(0x03) /**< \brief (AES_DATABUFPTR) MASK Register */
/* -------- AES_DBGCTRL : (AES Offset: 0x09) (R/W 8) Debug control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t DBGRUN:1; /*!< bit: 0 Debug Run */
uint8_t :7; /*!< bit: 1.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} AES_DBGCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define AES_DBGCTRL_OFFSET 0x09 /**< \brief (AES_DBGCTRL offset) Debug control */
#define AES_DBGCTRL_RESETVALUE _U_(0x00) /**< \brief (AES_DBGCTRL reset_value) Debug control */
#define AES_DBGCTRL_DBGRUN_Pos 0 /**< \brief (AES_DBGCTRL) Debug Run */
#define AES_DBGCTRL_DBGRUN (_U_(0x1) << AES_DBGCTRL_DBGRUN_Pos)
#define AES_DBGCTRL_MASK _U_(0x01) /**< \brief (AES_DBGCTRL) MASK Register */
/* -------- AES_KEYWORD : (AES Offset: 0x0C) ( /W 32) Keyword n -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
uint32_t reg; /*!< Type used for register access */
} AES_KEYWORD_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define AES_KEYWORD_OFFSET 0x0C /**< \brief (AES_KEYWORD offset) Keyword n */
#define AES_KEYWORD_RESETVALUE _U_(0x00000000) /**< \brief (AES_KEYWORD reset_value) Keyword n */
#define AES_KEYWORD_MASK _U_(0xFFFFFFFF) /**< \brief (AES_KEYWORD) MASK Register */
/* -------- AES_INDATA : (AES Offset: 0x38) (R/W 32) Indata -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
uint32_t reg; /*!< Type used for register access */
} AES_INDATA_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define AES_INDATA_OFFSET 0x38 /**< \brief (AES_INDATA offset) Indata */
#define AES_INDATA_RESETVALUE _U_(0x00000000) /**< \brief (AES_INDATA reset_value) Indata */
#define AES_INDATA_MASK _U_(0xFFFFFFFF) /**< \brief (AES_INDATA) MASK Register */
/* -------- AES_INTVECTV : (AES Offset: 0x3C) ( /W 32) Initialisation Vector n -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
uint32_t reg; /*!< Type used for register access */
} AES_INTVECTV_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define AES_INTVECTV_OFFSET 0x3C /**< \brief (AES_INTVECTV offset) Initialisation Vector n */
#define AES_INTVECTV_RESETVALUE _U_(0x00000000) /**< \brief (AES_INTVECTV reset_value) Initialisation Vector n */
#define AES_INTVECTV_MASK _U_(0xFFFFFFFF) /**< \brief (AES_INTVECTV) MASK Register */
/* -------- AES_HASHKEY : (AES Offset: 0x5C) (R/W 32) Hash key n -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
uint32_t reg; /*!< Type used for register access */
} AES_HASHKEY_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define AES_HASHKEY_OFFSET 0x5C /**< \brief (AES_HASHKEY offset) Hash key n */
#define AES_HASHKEY_RESETVALUE _U_(0x00000000) /**< \brief (AES_HASHKEY reset_value) Hash key n */
#define AES_HASHKEY_MASK _U_(0xFFFFFFFF) /**< \brief (AES_HASHKEY) MASK Register */
/* -------- AES_GHASH : (AES Offset: 0x6C) (R/W 32) Galois Hash n -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
uint32_t reg; /*!< Type used for register access */
} AES_GHASH_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define AES_GHASH_OFFSET 0x6C /**< \brief (AES_GHASH offset) Galois Hash n */
#define AES_GHASH_RESETVALUE _U_(0x00000000) /**< \brief (AES_GHASH reset_value) Galois Hash n */
#define AES_GHASH_MASK _U_(0xFFFFFFFF) /**< \brief (AES_GHASH) MASK Register */
/* -------- AES_CIPLEN : (AES Offset: 0x80) (R/W 32) Cipher Length -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
uint32_t reg; /*!< Type used for register access */
} AES_CIPLEN_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define AES_CIPLEN_OFFSET 0x80 /**< \brief (AES_CIPLEN offset) Cipher Length */
#define AES_CIPLEN_RESETVALUE _U_(0x00000000) /**< \brief (AES_CIPLEN reset_value) Cipher Length */
#define AES_CIPLEN_MASK _U_(0xFFFFFFFF) /**< \brief (AES_CIPLEN) MASK Register */
/* -------- AES_RANDSEED : (AES Offset: 0x84) (R/W 32) Random Seed -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
uint32_t reg; /*!< Type used for register access */
} AES_RANDSEED_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define AES_RANDSEED_OFFSET 0x84 /**< \brief (AES_RANDSEED offset) Random Seed */
#define AES_RANDSEED_RESETVALUE _U_(0x00000000) /**< \brief (AES_RANDSEED reset_value) Random Seed */
#define AES_RANDSEED_MASK _U_(0xFFFFFFFF) /**< \brief (AES_RANDSEED) MASK Register */
/** \brief AES hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct {
__IO AES_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) Control A */
__IO AES_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 8) Control B */
__IO AES_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x05 (R/W 8) Interrupt Enable Clear */
__IO AES_INTENSET_Type INTENSET; /**< \brief Offset: 0x06 (R/W 8) Interrupt Enable Set */
__IO AES_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x07 (R/W 8) Interrupt Flag Status */
__IO AES_DATABUFPTR_Type DATABUFPTR; /**< \brief Offset: 0x08 (R/W 8) Data buffer pointer */
__IO AES_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x09 (R/W 8) Debug control */
RoReg8 Reserved1[0x2];
__O AES_KEYWORD_Type KEYWORD[8]; /**< \brief Offset: 0x0C ( /W 32) Keyword n */
RoReg8 Reserved2[0xC];
__IO AES_INDATA_Type INDATA; /**< \brief Offset: 0x38 (R/W 32) Indata */
__O AES_INTVECTV_Type INTVECTV[4]; /**< \brief Offset: 0x3C ( /W 32) Initialisation Vector n */
RoReg8 Reserved3[0x10];
__IO AES_HASHKEY_Type HASHKEY[4]; /**< \brief Offset: 0x5C (R/W 32) Hash key n */
__IO AES_GHASH_Type GHASH[4]; /**< \brief Offset: 0x6C (R/W 32) Galois Hash n */
RoReg8 Reserved4[0x4];
__IO AES_CIPLEN_Type CIPLEN; /**< \brief Offset: 0x80 (R/W 32) Cipher Length */
__IO AES_RANDSEED_Type RANDSEED; /**< \brief Offset: 0x84 (R/W 32) Random Seed */
} Aes;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/*@}*/
#endif /* _SAME54_AES_COMPONENT_ */

+ 3187
- 2527
arch/arm/SAME54/SAME54A/mcu/inc/component/can.h
File diff suppressed because it is too large
View File


+ 228
- 217
arch/arm/SAME54/SAME54A/mcu/inc/component/ccl.h View File

@@ -1,217 +1,228 @@
/**
* \brief Component description for CCL
*
* Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries.
*
* Subject to your compliance with these terms, you may use Microchip software and any derivatives
* exclusively with Microchip products. It is your responsibility to comply with third party license
* terms applicable to your use of third party software (including open source software) that may
* accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY,
* APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND
* FITNESS FOR A PARTICULAR PURPOSE.
*
* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF
* MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT
* EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
*/

/* file generated from device description version 2020-03-12T17:27:04Z */
#ifndef _SAME54_CCL_COMPONENT_H_
#define _SAME54_CCL_COMPONENT_H_

/* ************************************************************************** */
/* SOFTWARE API DEFINITION FOR CCL */
/* ************************************************************************** */

/* -------- CCL_CTRL : (CCL Offset: 0x00) (R/W 8) Control -------- */
#define CCL_CTRL_RESETVALUE _U_(0x00) /**< (CCL_CTRL) Control Reset Value */

#define CCL_CTRL_SWRST_Pos _U_(0) /**< (CCL_CTRL) Software Reset Position */
#define CCL_CTRL_SWRST_Msk (_U_(0x1) << CCL_CTRL_SWRST_Pos) /**< (CCL_CTRL) Software Reset Mask */
#define CCL_CTRL_SWRST(value) (CCL_CTRL_SWRST_Msk & ((value) << CCL_CTRL_SWRST_Pos))
#define CCL_CTRL_SWRST_DISABLE_Val _U_(0x0) /**< (CCL_CTRL) The peripheral is not reset */
#define CCL_CTRL_SWRST_ENABLE_Val _U_(0x1) /**< (CCL_CTRL) The peripheral is reset */
#define CCL_CTRL_SWRST_DISABLE (CCL_CTRL_SWRST_DISABLE_Val << CCL_CTRL_SWRST_Pos) /**< (CCL_CTRL) The peripheral is not reset Position */
#define CCL_CTRL_SWRST_ENABLE (CCL_CTRL_SWRST_ENABLE_Val << CCL_CTRL_SWRST_Pos) /**< (CCL_CTRL) The peripheral is reset Position */
#define CCL_CTRL_ENABLE_Pos _U_(1) /**< (CCL_CTRL) Enable Position */
#define CCL_CTRL_ENABLE_Msk (_U_(0x1) << CCL_CTRL_ENABLE_Pos) /**< (CCL_CTRL) Enable Mask */
#define CCL_CTRL_ENABLE(value) (CCL_CTRL_ENABLE_Msk & ((value) << CCL_CTRL_ENABLE_Pos))
#define CCL_CTRL_ENABLE_DISABLE_Val _U_(0x0) /**< (CCL_CTRL) The peripheral is disabled */
#define CCL_CTRL_ENABLE_ENABLE_Val _U_(0x1) /**< (CCL_CTRL) The peripheral is enabled */
#define CCL_CTRL_ENABLE_DISABLE (CCL_CTRL_ENABLE_DISABLE_Val << CCL_CTRL_ENABLE_Pos) /**< (CCL_CTRL) The peripheral is disabled Position */
#define CCL_CTRL_ENABLE_ENABLE (CCL_CTRL_ENABLE_ENABLE_Val << CCL_CTRL_ENABLE_Pos) /**< (CCL_CTRL) The peripheral is enabled Position */
#define CCL_CTRL_RUNSTDBY_Pos _U_(6) /**< (CCL_CTRL) Run in Standby Position */
#define CCL_CTRL_RUNSTDBY_Msk (_U_(0x1) << CCL_CTRL_RUNSTDBY_Pos) /**< (CCL_CTRL) Run in Standby Mask */
#define CCL_CTRL_RUNSTDBY(value) (CCL_CTRL_RUNSTDBY_Msk & ((value) << CCL_CTRL_RUNSTDBY_Pos))
#define CCL_CTRL_RUNSTDBY_DISABLE_Val _U_(0x0) /**< (CCL_CTRL) Generic clock is not required in standby sleep mode */
#define CCL_CTRL_RUNSTDBY_ENABLE_Val _U_(0x1) /**< (CCL_CTRL) Generic clock is required in standby sleep mode */
#define CCL_CTRL_RUNSTDBY_DISABLE (CCL_CTRL_RUNSTDBY_DISABLE_Val << CCL_CTRL_RUNSTDBY_Pos) /**< (CCL_CTRL) Generic clock is not required in standby sleep mode Position */
#define CCL_CTRL_RUNSTDBY_ENABLE (CCL_CTRL_RUNSTDBY_ENABLE_Val << CCL_CTRL_RUNSTDBY_Pos) /**< (CCL_CTRL) Generic clock is required in standby sleep mode Position */
#define CCL_CTRL_Msk _U_(0x43) /**< (CCL_CTRL) Register Mask */


/* -------- CCL_SEQCTRL : (CCL Offset: 0x04) (R/W 8) SEQ Control x -------- */
#define CCL_SEQCTRL_RESETVALUE _U_(0x00) /**< (CCL_SEQCTRL) SEQ Control x Reset Value */

#define CCL_SEQCTRL_SEQSEL_Pos _U_(0) /**< (CCL_SEQCTRL) Sequential Selection Position */
#define CCL_SEQCTRL_SEQSEL_Msk (_U_(0xF) << CCL_SEQCTRL_SEQSEL_Pos) /**< (CCL_SEQCTRL) Sequential Selection Mask */
#define CCL_SEQCTRL_SEQSEL(value) (CCL_SEQCTRL_SEQSEL_Msk & ((value) << CCL_SEQCTRL_SEQSEL_Pos))
#define CCL_SEQCTRL_SEQSEL_DISABLE_Val _U_(0x0) /**< (CCL_SEQCTRL) Sequential logic is disabled */
#define CCL_SEQCTRL_SEQSEL_DFF_Val _U_(0x1) /**< (CCL_SEQCTRL) D flip flop */
#define CCL_SEQCTRL_SEQSEL_JK_Val _U_(0x2) /**< (CCL_SEQCTRL) JK flip flop */
#define CCL_SEQCTRL_SEQSEL_LATCH_Val _U_(0x3) /**< (CCL_SEQCTRL) D latch */
#define CCL_SEQCTRL_SEQSEL_RS_Val _U_(0x4) /**< (CCL_SEQCTRL) RS latch */
#define CCL_SEQCTRL_SEQSEL_DISABLE (CCL_SEQCTRL_SEQSEL_DISABLE_Val << CCL_SEQCTRL_SEQSEL_Pos) /**< (CCL_SEQCTRL) Sequential logic is disabled Position */
#define CCL_SEQCTRL_SEQSEL_DFF (CCL_SEQCTRL_SEQSEL_DFF_Val << CCL_SEQCTRL_SEQSEL_Pos) /**< (CCL_SEQCTRL) D flip flop Position */
#define CCL_SEQCTRL_SEQSEL_JK (CCL_SEQCTRL_SEQSEL_JK_Val << CCL_SEQCTRL_SEQSEL_Pos) /**< (CCL_SEQCTRL) JK flip flop Position */
#define CCL_SEQCTRL_SEQSEL_LATCH (CCL_SEQCTRL_SEQSEL_LATCH_Val << CCL_SEQCTRL_SEQSEL_Pos) /**< (CCL_SEQCTRL) D latch Position */
#define CCL_SEQCTRL_SEQSEL_RS (CCL_SEQCTRL_SEQSEL_RS_Val << CCL_SEQCTRL_SEQSEL_Pos) /**< (CCL_SEQCTRL) RS latch Position */
#define CCL_SEQCTRL_Msk _U_(0x0F) /**< (CCL_SEQCTRL) Register Mask */


/* -------- CCL_LUTCTRL : (CCL Offset: 0x08) (R/W 32) LUT Control x -------- */
#define CCL_LUTCTRL_RESETVALUE _U_(0x00) /**< (CCL_LUTCTRL) LUT Control x Reset Value */

#define CCL_LUTCTRL_ENABLE_Pos _U_(1) /**< (CCL_LUTCTRL) LUT Enable Position */
#define CCL_LUTCTRL_ENABLE_Msk (_U_(0x1) << CCL_LUTCTRL_ENABLE_Pos) /**< (CCL_LUTCTRL) LUT Enable Mask */
#define CCL_LUTCTRL_ENABLE(value) (CCL_LUTCTRL_ENABLE_Msk & ((value) << CCL_LUTCTRL_ENABLE_Pos))
#define CCL_LUTCTRL_ENABLE_DISABLE_Val _U_(0x0) /**< (CCL_LUTCTRL) LUT block is disabled */
#define CCL_LUTCTRL_ENABLE_ENABLE_Val _U_(0x1) /**< (CCL_LUTCTRL) LUT block is enabled */
#define CCL_LUTCTRL_ENABLE_DISABLE (CCL_LUTCTRL_ENABLE_DISABLE_Val << CCL_LUTCTRL_ENABLE_Pos) /**< (CCL_LUTCTRL) LUT block is disabled Position */
#define CCL_LUTCTRL_ENABLE_ENABLE (CCL_LUTCTRL_ENABLE_ENABLE_Val << CCL_LUTCTRL_ENABLE_Pos) /**< (CCL_LUTCTRL) LUT block is enabled Position */
#define CCL_LUTCTRL_FILTSEL_Pos _U_(4) /**< (CCL_LUTCTRL) Filter Selection Position */
#define CCL_LUTCTRL_FILTSEL_Msk (_U_(0x3) << CCL_LUTCTRL_FILTSEL_Pos) /**< (CCL_LUTCTRL) Filter Selection Mask */
#define CCL_LUTCTRL_FILTSEL(value) (CCL_LUTCTRL_FILTSEL_Msk & ((value) << CCL_LUTCTRL_FILTSEL_Pos))
#define CCL_LUTCTRL_FILTSEL_DISABLE_Val _U_(0x0) /**< (CCL_LUTCTRL) Filter disabled */
#define CCL_LUTCTRL_FILTSEL_SYNCH_Val _U_(0x1) /**< (CCL_LUTCTRL) Synchronizer enabled */
#define CCL_LUTCTRL_FILTSEL_FILTER_Val _U_(0x2) /**< (CCL_LUTCTRL) Filter enabled */
#define CCL_LUTCTRL_FILTSEL_DISABLE (CCL_LUTCTRL_FILTSEL_DISABLE_Val << CCL_LUTCTRL_FILTSEL_Pos) /**< (CCL_LUTCTRL) Filter disabled Position */
#define CCL_LUTCTRL_FILTSEL_SYNCH (CCL_LUTCTRL_FILTSEL_SYNCH_Val << CCL_LUTCTRL_FILTSEL_Pos) /**< (CCL_LUTCTRL) Synchronizer enabled Position */
#define CCL_LUTCTRL_FILTSEL_FILTER (CCL_LUTCTRL_FILTSEL_FILTER_Val << CCL_LUTCTRL_FILTSEL_Pos) /**< (CCL_LUTCTRL) Filter enabled Position */
#define CCL_LUTCTRL_EDGESEL_Pos _U_(7) /**< (CCL_LUTCTRL) Edge Selection Position */
#define CCL_LUTCTRL_EDGESEL_Msk (_U_(0x1) << CCL_LUTCTRL_EDGESEL_Pos) /**< (CCL_LUTCTRL) Edge Selection Mask */
#define CCL_LUTCTRL_EDGESEL(value) (CCL_LUTCTRL_EDGESEL_Msk & ((value) << CCL_LUTCTRL_EDGESEL_Pos))
#define CCL_LUTCTRL_EDGESEL_DISABLE_Val _U_(0x0) /**< (CCL_LUTCTRL) Edge detector is disabled */
#define CCL_LUTCTRL_EDGESEL_ENABLE_Val _U_(0x1) /**< (CCL_LUTCTRL) Edge detector is enabled */
#define CCL_LUTCTRL_EDGESEL_DISABLE (CCL_LUTCTRL_EDGESEL_DISABLE_Val << CCL_LUTCTRL_EDGESEL_Pos) /**< (CCL_LUTCTRL) Edge detector is disabled Position */
#define CCL_LUTCTRL_EDGESEL_ENABLE (CCL_LUTCTRL_EDGESEL_ENABLE_Val << CCL_LUTCTRL_EDGESEL_Pos) /**< (CCL_LUTCTRL) Edge detector is enabled Position */
#define CCL_LUTCTRL_INSEL0_Pos _U_(8) /**< (CCL_LUTCTRL) Input Selection 0 Position */
#define CCL_LUTCTRL_INSEL0_Msk (_U_(0xF) << CCL_LUTCTRL_INSEL0_Pos) /**< (CCL_LUTCTRL) Input Selection 0 Mask */
#define CCL_LUTCTRL_INSEL0(value) (CCL_LUTCTRL_INSEL0_Msk & ((value) << CCL_LUTCTRL_INSEL0_Pos))
#define CCL_LUTCTRL_INSEL0_MASK_Val _U_(0x0) /**< (CCL_LUTCTRL) Masked input */
#define CCL_LUTCTRL_INSEL0_FEEDBACK_Val _U_(0x1) /**< (CCL_LUTCTRL) Feedback input source */
#define CCL_LUTCTRL_INSEL0_LINK_Val _U_(0x2) /**< (CCL_LUTCTRL) Linked LUT input source */
#define CCL_LUTCTRL_INSEL0_EVENT_Val _U_(0x3) /**< (CCL_LUTCTRL) Event input source */
#define CCL_LUTCTRL_INSEL0_IO_Val _U_(0x4) /**< (CCL_LUTCTRL) I/O pin input source */
#define CCL_LUTCTRL_INSEL0_AC_Val _U_(0x5) /**< (CCL_LUTCTRL) AC input source */
#define CCL_LUTCTRL_INSEL0_TC_Val _U_(0x6) /**< (CCL_LUTCTRL) TC input source */
#define CCL_LUTCTRL_INSEL0_ALTTC_Val _U_(0x7) /**< (CCL_LUTCTRL) Alternate TC input source */
#define CCL_LUTCTRL_INSEL0_TCC_Val _U_(0x8) /**< (CCL_LUTCTRL) TCC input source */
#define CCL_LUTCTRL_INSEL0_SERCOM_Val _U_(0x9) /**< (CCL_LUTCTRL) SERCOM input source */
#define CCL_LUTCTRL_INSEL0_MASK (CCL_LUTCTRL_INSEL0_MASK_Val << CCL_LUTCTRL_INSEL0_Pos) /**< (CCL_LUTCTRL) Masked input Position */
#define CCL_LUTCTRL_INSEL0_FEEDBACK (CCL_LUTCTRL_INSEL0_FEEDBACK_Val << CCL_LUTCTRL_INSEL0_Pos) /**< (CCL_LUTCTRL) Feedback input source Position */
#define CCL_LUTCTRL_INSEL0_LINK (CCL_LUTCTRL_INSEL0_LINK_Val << CCL_LUTCTRL_INSEL0_Pos) /**< (CCL_LUTCTRL) Linked LUT input source Position */
#define CCL_LUTCTRL_INSEL0_EVENT (CCL_LUTCTRL_INSEL0_EVENT_Val << CCL_LUTCTRL_INSEL0_Pos) /**< (CCL_LUTCTRL) Event input source Position */
#define CCL_LUTCTRL_INSEL0_IO (CCL_LUTCTRL_INSEL0_IO_Val << CCL_LUTCTRL_INSEL0_Pos) /**< (CCL_LUTCTRL) I/O pin input source Position */
#define CCL_LUTCTRL_INSEL0_AC (CCL_LUTCTRL_INSEL0_AC_Val << CCL_LUTCTRL_INSEL0_Pos) /**< (CCL_LUTCTRL) AC input source Position */
#define CCL_LUTCTRL_INSEL0_TC (CCL_LUTCTRL_INSEL0_TC_Val << CCL_LUTCTRL_INSEL0_Pos) /**< (CCL_LUTCTRL) TC input source Position */
#define CCL_LUTCTRL_INSEL0_ALTTC (CCL_LUTCTRL_INSEL0_ALTTC_Val << CCL_LUTCTRL_INSEL0_Pos) /**< (CCL_LUTCTRL) Alternate TC input source Position */
#define CCL_LUTCTRL_INSEL0_TCC (CCL_LUTCTRL_INSEL0_TCC_Val << CCL_LUTCTRL_INSEL0_Pos) /**< (CCL_LUTCTRL) TCC input source Position */
#define CCL_LUTCTRL_INSEL0_SERCOM (CCL_LUTCTRL_INSEL0_SERCOM_Val << CCL_LUTCTRL_INSEL0_Pos) /**< (CCL_LUTCTRL) SERCOM input source Position */
#define CCL_LUTCTRL_INSEL1_Pos _U_(12) /**< (CCL_LUTCTRL) Input Selection 1 Position */
#define CCL_LUTCTRL_INSEL1_Msk (_U_(0xF) << CCL_LUTCTRL_INSEL1_Pos) /**< (CCL_LUTCTRL) Input Selection 1 Mask */
#define CCL_LUTCTRL_INSEL1(value) (CCL_LUTCTRL_INSEL1_Msk & ((value) << CCL_LUTCTRL_INSEL1_Pos))
#define CCL_LUTCTRL_INSEL1_MASK_Val _U_(0x0) /**< (CCL_LUTCTRL) Masked input */
#define CCL_LUTCTRL_INSEL1_FEEDBACK_Val _U_(0x1) /**< (CCL_LUTCTRL) Feedback input source */
#define CCL_LUTCTRL_INSEL1_LINK_Val _U_(0x2) /**< (CCL_LUTCTRL) Linked LUT input source */
#define CCL_LUTCTRL_INSEL1_EVENT_Val _U_(0x3) /**< (CCL_LUTCTRL) Event input source */
#define CCL_LUTCTRL_INSEL1_IO_Val _U_(0x4) /**< (CCL_LUTCTRL) I/O pin input source */
#define CCL_LUTCTRL_INSEL1_AC_Val _U_(0x5) /**< (CCL_LUTCTRL) AC input source */
#define CCL_LUTCTRL_INSEL1_TC_Val _U_(0x6) /**< (CCL_LUTCTRL) TC input source */
#define CCL_LUTCTRL_INSEL1_ALTTC_Val _U_(0x7) /**< (CCL_LUTCTRL) Alternate TC input source */
#define CCL_LUTCTRL_INSEL1_TCC_Val _U_(0x8) /**< (CCL_LUTCTRL) TCC input source */
#define CCL_LUTCTRL_INSEL1_SERCOM_Val _U_(0x9) /**< (CCL_LUTCTRL) SERCOM input source */
#define CCL_LUTCTRL_INSEL1_MASK (CCL_LUTCTRL_INSEL1_MASK_Val << CCL_LUTCTRL_INSEL1_Pos) /**< (CCL_LUTCTRL) Masked input Position */
#define CCL_LUTCTRL_INSEL1_FEEDBACK (CCL_LUTCTRL_INSEL1_FEEDBACK_Val << CCL_LUTCTRL_INSEL1_Pos) /**< (CCL_LUTCTRL) Feedback input source Position */
#define CCL_LUTCTRL_INSEL1_LINK (CCL_LUTCTRL_INSEL1_LINK_Val << CCL_LUTCTRL_INSEL1_Pos) /**< (CCL_LUTCTRL) Linked LUT input source Position */
#define CCL_LUTCTRL_INSEL1_EVENT (CCL_LUTCTRL_INSEL1_EVENT_Val << CCL_LUTCTRL_INSEL1_Pos) /**< (CCL_LUTCTRL) Event input source Position */
#define CCL_LUTCTRL_INSEL1_IO (CCL_LUTCTRL_INSEL1_IO_Val << CCL_LUTCTRL_INSEL1_Pos) /**< (CCL_LUTCTRL) I/O pin input source Position */
#define CCL_LUTCTRL_INSEL1_AC (CCL_LUTCTRL_INSEL1_AC_Val << CCL_LUTCTRL_INSEL1_Pos) /**< (CCL_LUTCTRL) AC input source Position */
</