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179 lines
10 KiB
C
179 lines
10 KiB
C
/**
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* \file
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*
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* \brief Component description for RAMECC
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*
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* Copyright (c) 2019 Microchip Technology Inc.
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*
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* \asf_license_start
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*
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* \page License
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed under the Apache License, Version 2.0 (the "License"); you may
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* not use this file except in compliance with the License.
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* You may obtain a copy of the Licence at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an AS IS BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*
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* \asf_license_stop
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*
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*/
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#ifndef _SAME54_RAMECC_COMPONENT_
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#define _SAME54_RAMECC_COMPONENT_
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/* ========================================================================== */
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/** SOFTWARE API DEFINITION FOR RAMECC */
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/* ========================================================================== */
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/** \addtogroup SAME54_RAMECC RAM ECC */
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/*@{*/
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#define RAMECC_U2268
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#define REV_RAMECC 0x100
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/* -------- RAMECC_INTENCLR : (RAMECC Offset: 0x0) (R/W 8) Interrupt Enable Clear -------- */
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#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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typedef union {
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struct {
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uint8_t SINGLEE:1; /*!< bit: 0 Single Bit ECC Error Interrupt Enable Clear */
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uint8_t DUALE:1; /*!< bit: 1 Dual Bit ECC Error Interrupt Enable Clear */
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uint8_t :6; /*!< bit: 2.. 7 Reserved */
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} bit; /*!< Structure used for bit access */
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uint8_t reg; /*!< Type used for register access */
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} RAMECC_INTENCLR_Type;
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#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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#define RAMECC_INTENCLR_OFFSET 0x0 /**< \brief (RAMECC_INTENCLR offset) Interrupt Enable Clear */
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#define RAMECC_INTENCLR_RESETVALUE _U_(0x00) /**< \brief (RAMECC_INTENCLR reset_value) Interrupt Enable Clear */
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#define RAMECC_INTENCLR_SINGLEE_Pos 0 /**< \brief (RAMECC_INTENCLR) Single Bit ECC Error Interrupt Enable Clear */
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#define RAMECC_INTENCLR_SINGLEE (_U_(0x1) << RAMECC_INTENCLR_SINGLEE_Pos)
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#define RAMECC_INTENCLR_DUALE_Pos 1 /**< \brief (RAMECC_INTENCLR) Dual Bit ECC Error Interrupt Enable Clear */
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#define RAMECC_INTENCLR_DUALE (_U_(0x1) << RAMECC_INTENCLR_DUALE_Pos)
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#define RAMECC_INTENCLR_MASK _U_(0x03) /**< \brief (RAMECC_INTENCLR) MASK Register */
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/* -------- RAMECC_INTENSET : (RAMECC Offset: 0x1) (R/W 8) Interrupt Enable Set -------- */
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#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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typedef union {
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struct {
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uint8_t SINGLEE:1; /*!< bit: 0 Single Bit ECC Error Interrupt Enable Set */
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uint8_t DUALE:1; /*!< bit: 1 Dual Bit ECC Error Interrupt Enable Set */
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uint8_t :6; /*!< bit: 2.. 7 Reserved */
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} bit; /*!< Structure used for bit access */
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uint8_t reg; /*!< Type used for register access */
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} RAMECC_INTENSET_Type;
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#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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#define RAMECC_INTENSET_OFFSET 0x1 /**< \brief (RAMECC_INTENSET offset) Interrupt Enable Set */
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#define RAMECC_INTENSET_RESETVALUE _U_(0x00) /**< \brief (RAMECC_INTENSET reset_value) Interrupt Enable Set */
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#define RAMECC_INTENSET_SINGLEE_Pos 0 /**< \brief (RAMECC_INTENSET) Single Bit ECC Error Interrupt Enable Set */
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#define RAMECC_INTENSET_SINGLEE (_U_(0x1) << RAMECC_INTENSET_SINGLEE_Pos)
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#define RAMECC_INTENSET_DUALE_Pos 1 /**< \brief (RAMECC_INTENSET) Dual Bit ECC Error Interrupt Enable Set */
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#define RAMECC_INTENSET_DUALE (_U_(0x1) << RAMECC_INTENSET_DUALE_Pos)
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#define RAMECC_INTENSET_MASK _U_(0x03) /**< \brief (RAMECC_INTENSET) MASK Register */
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/* -------- RAMECC_INTFLAG : (RAMECC Offset: 0x2) (R/W 8) Interrupt Flag -------- */
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#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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typedef union { // __I to avoid read-modify-write on write-to-clear register
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struct {
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__I uint8_t SINGLEE:1; /*!< bit: 0 Single Bit ECC Error Interrupt */
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__I uint8_t DUALE:1; /*!< bit: 1 Dual Bit ECC Error Interrupt */
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__I uint8_t :6; /*!< bit: 2.. 7 Reserved */
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} bit; /*!< Structure used for bit access */
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uint8_t reg; /*!< Type used for register access */
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} RAMECC_INTFLAG_Type;
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#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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#define RAMECC_INTFLAG_OFFSET 0x2 /**< \brief (RAMECC_INTFLAG offset) Interrupt Flag */
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#define RAMECC_INTFLAG_RESETVALUE _U_(0x00) /**< \brief (RAMECC_INTFLAG reset_value) Interrupt Flag */
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#define RAMECC_INTFLAG_SINGLEE_Pos 0 /**< \brief (RAMECC_INTFLAG) Single Bit ECC Error Interrupt */
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#define RAMECC_INTFLAG_SINGLEE (_U_(0x1) << RAMECC_INTFLAG_SINGLEE_Pos)
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#define RAMECC_INTFLAG_DUALE_Pos 1 /**< \brief (RAMECC_INTFLAG) Dual Bit ECC Error Interrupt */
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#define RAMECC_INTFLAG_DUALE (_U_(0x1) << RAMECC_INTFLAG_DUALE_Pos)
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#define RAMECC_INTFLAG_MASK _U_(0x03) /**< \brief (RAMECC_INTFLAG) MASK Register */
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/* -------- RAMECC_STATUS : (RAMECC Offset: 0x3) (R/ 8) Status -------- */
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#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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typedef union {
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struct {
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uint8_t ECCDIS:1; /*!< bit: 0 ECC Disable */
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uint8_t :7; /*!< bit: 1.. 7 Reserved */
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} bit; /*!< Structure used for bit access */
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uint8_t reg; /*!< Type used for register access */
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} RAMECC_STATUS_Type;
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#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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#define RAMECC_STATUS_OFFSET 0x3 /**< \brief (RAMECC_STATUS offset) Status */
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#define RAMECC_STATUS_RESETVALUE _U_(0x00) /**< \brief (RAMECC_STATUS reset_value) Status */
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#define RAMECC_STATUS_ECCDIS_Pos 0 /**< \brief (RAMECC_STATUS) ECC Disable */
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#define RAMECC_STATUS_ECCDIS (_U_(0x1) << RAMECC_STATUS_ECCDIS_Pos)
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#define RAMECC_STATUS_MASK _U_(0x01) /**< \brief (RAMECC_STATUS) MASK Register */
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/* -------- RAMECC_ERRADDR : (RAMECC Offset: 0x4) (R/ 32) Error Address -------- */
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#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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typedef union {
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struct {
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uint32_t ERRADDR:17; /*!< bit: 0..16 Error Address */
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uint32_t :15; /*!< bit: 17..31 Reserved */
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} bit; /*!< Structure used for bit access */
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uint32_t reg; /*!< Type used for register access */
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} RAMECC_ERRADDR_Type;
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#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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#define RAMECC_ERRADDR_OFFSET 0x4 /**< \brief (RAMECC_ERRADDR offset) Error Address */
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#define RAMECC_ERRADDR_RESETVALUE _U_(0x00000000) /**< \brief (RAMECC_ERRADDR reset_value) Error Address */
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#define RAMECC_ERRADDR_ERRADDR_Pos 0 /**< \brief (RAMECC_ERRADDR) Error Address */
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#define RAMECC_ERRADDR_ERRADDR_Msk (_U_(0x1FFFF) << RAMECC_ERRADDR_ERRADDR_Pos)
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#define RAMECC_ERRADDR_ERRADDR(value) (RAMECC_ERRADDR_ERRADDR_Msk & ((value) << RAMECC_ERRADDR_ERRADDR_Pos))
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#define RAMECC_ERRADDR_MASK _U_(0x0001FFFF) /**< \brief (RAMECC_ERRADDR) MASK Register */
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/* -------- RAMECC_DBGCTRL : (RAMECC Offset: 0xF) (R/W 8) Debug Control -------- */
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#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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typedef union {
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struct {
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uint8_t ECCDIS:1; /*!< bit: 0 ECC Disable */
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uint8_t ECCELOG:1; /*!< bit: 1 ECC Error Log */
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uint8_t :6; /*!< bit: 2.. 7 Reserved */
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} bit; /*!< Structure used for bit access */
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uint8_t reg; /*!< Type used for register access */
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} RAMECC_DBGCTRL_Type;
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#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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#define RAMECC_DBGCTRL_OFFSET 0xF /**< \brief (RAMECC_DBGCTRL offset) Debug Control */
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#define RAMECC_DBGCTRL_RESETVALUE _U_(0x00) /**< \brief (RAMECC_DBGCTRL reset_value) Debug Control */
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#define RAMECC_DBGCTRL_ECCDIS_Pos 0 /**< \brief (RAMECC_DBGCTRL) ECC Disable */
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#define RAMECC_DBGCTRL_ECCDIS (_U_(0x1) << RAMECC_DBGCTRL_ECCDIS_Pos)
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#define RAMECC_DBGCTRL_ECCELOG_Pos 1 /**< \brief (RAMECC_DBGCTRL) ECC Error Log */
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#define RAMECC_DBGCTRL_ECCELOG (_U_(0x1) << RAMECC_DBGCTRL_ECCELOG_Pos)
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#define RAMECC_DBGCTRL_MASK _U_(0x03) /**< \brief (RAMECC_DBGCTRL) MASK Register */
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/** \brief RAMECC hardware registers */
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#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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typedef struct {
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__IO RAMECC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x0 (R/W 8) Interrupt Enable Clear */
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__IO RAMECC_INTENSET_Type INTENSET; /**< \brief Offset: 0x1 (R/W 8) Interrupt Enable Set */
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__IO RAMECC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x2 (R/W 8) Interrupt Flag */
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__I RAMECC_STATUS_Type STATUS; /**< \brief Offset: 0x3 (R/ 8) Status */
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__I RAMECC_ERRADDR_Type ERRADDR; /**< \brief Offset: 0x4 (R/ 32) Error Address */
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RoReg8 Reserved1[0x7];
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__IO RAMECC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0xF (R/W 8) Debug Control */
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} Ramecc;
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#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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/*@}*/
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#endif /* _SAME54_RAMECC_COMPONENT_ */
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