From f8fca08efe93433cf3ce2938c7b61d8f5c0d02ee Mon Sep 17 00:00:00 2001 From: penguin Date: Thu, 24 Dec 2020 21:41:10 -0600 Subject: [PATCH] working on core module for same54 --- .../arm/SAMD21/SAMD21A/scripts/samd21j18a.cfg | 4 +- .../arm/SAME54/SAME54A/ld/same54n19a_flash.ld | 163 - arch/arm/SAME54/SAME54A/ld/same54n19a_sram.ld | 162 - .../arm/SAME54/SAME54A/ld/same54n20a_flash.ld | 163 - arch/arm/SAME54/SAME54A/ld/same54n20a_sram.ld | 162 - .../arm/SAME54/SAME54A/ld/same54p19a_flash.ld | 163 - arch/arm/SAME54/SAME54A/ld/same54p19a_sram.ld | 162 - arch/arm/SAME54/SAME54A/manifest/same54a.toml | 2 +- .../SAME54A/mcu/inc/component-version.h | 128 +- .../arm/SAME54/SAME54A/mcu/inc/component/ac.h | 1008 ++- .../SAME54/SAME54A/mcu/inc/component/adc.h | 1520 ++-- .../SAME54/SAME54A/mcu/inc/component/aes.h | 651 +- .../SAME54/SAME54A/mcu/inc/component/can.h | 5714 +++++++------- .../SAME54/SAME54A/mcu/inc/component/ccl.h | 445 +- .../SAME54/SAME54A/mcu/inc/component/cmcc.h | 604 +- .../SAME54/SAME54A/mcu/inc/component/dac.h | 983 +-- .../SAME54/SAME54A/mcu/inc/component/dmac.h | 2541 ++++--- .../SAME54/SAME54A/mcu/inc/component/dsu.h | 1092 +-- .../SAME54/SAME54A/mcu/inc/component/eic.h | 918 +-- .../SAME54/SAME54A/mcu/inc/component/evsys.h | 1039 +-- .../SAME54/SAME54A/mcu/inc/component/freqm.h | 383 +- .../SAME54/SAME54A/mcu/inc/component/gclk.h | 460 +- .../SAME54/SAME54A/mcu/inc/component/gmac.h | 4273 ++++++----- .../SAME54A/mcu/inc/component/hmatrixb.h | 150 +- .../SAME54/SAME54A/mcu/inc/component/i2s.h | 1343 ++-- .../SAME54/SAME54A/mcu/inc/component/icm.h | 991 ++- .../SAME54/SAME54A/mcu/inc/component/mclk.h | 911 +-- .../SAME54A/mcu/inc/component/nvmctrl.h | 1313 ++-- .../SAME54A/mcu/inc/component/osc32kctrl.h | 525 +- .../SAME54A/mcu/inc/component/oscctrl.h | 1485 ++-- .../SAME54/SAME54A/mcu/inc/component/pac.h | 1331 ++-- .../SAME54/SAME54A/mcu/inc/component/pcc.h | 420 +- .../SAME54/SAME54A/mcu/inc/component/pdec.h | 1247 ++-- .../SAME54/SAME54A/mcu/inc/component/picop.h | 1321 ++++ .../arm/SAME54/SAME54A/mcu/inc/component/pm.h | 455 +- .../SAME54/SAME54A/mcu/inc/component/port.h | 695 +- .../SAME54/SAME54A/mcu/inc/component/pukcc.h | 39 - .../SAME54/SAME54A/mcu/inc/component/qspi.h | 911 ++- .../SAME54/SAME54A/mcu/inc/component/ramecc.h | 298 +- .../SAME54/SAME54A/mcu/inc/component/rstc.h | 204 +- .../SAME54/SAME54A/mcu/inc/component/rtc.h | 3781 +++++----- .../SAME54/SAME54A/mcu/inc/component/sdhc.h | 4370 ++++++----- .../SAME54/SAME54A/mcu/inc/component/sercom.h | 3880 +++++----- .../SAME54/SAME54A/mcu/inc/component/supc.h | 779 +- .../arm/SAME54/SAME54A/mcu/inc/component/tc.h | 1446 ++-- .../SAME54/SAME54A/mcu/inc/component/tcc.h | 3158 ++++---- .../SAME54/SAME54A/mcu/inc/component/trng.h | 285 +- .../SAME54/SAME54A/mcu/inc/component/usb.h | 3059 ++++---- .../SAME54/SAME54A/mcu/inc/component/wdt.h | 523 +- arch/arm/SAME54/SAME54A/mcu/inc/instance/ac.h | 79 + .../SAME54/SAME54A/mcu/inc/instance/adc0.h | 99 + .../SAME54/SAME54A/mcu/inc/instance/adc1.h | 100 + .../arm/SAME54/SAME54A/mcu/inc/instance/aes.h | 105 + .../SAME54/SAME54A/mcu/inc/instance/can0.h | 139 + .../SAME54/SAME54A/mcu/inc/instance/can1.h | 139 + .../arm/SAME54/SAME54A/mcu/inc/instance/ccl.h | 57 + .../SAME54/SAME54A/mcu/inc/instance/cmcc.h | 61 + .../arm/SAME54/SAME54A/mcu/inc/instance/dac.h | 88 + .../SAME54/SAME54A/mcu/inc/instance/dmac.h | 596 ++ .../arm/SAME54/SAME54A/mcu/inc/instance/dsu.h | 95 + .../arm/SAME54/SAME54A/mcu/inc/instance/eic.h | 73 + .../SAME54/SAME54A/mcu/inc/instance/evsys.h | 720 ++ .../SAME54/SAME54A/mcu/inc/instance/freqm.h | 59 + .../SAME54/SAME54A/mcu/inc/instance/gclk.h | 191 + .../SAME54/SAME54A/mcu/inc/instance/gmac.h | 263 + .../SAME54/SAME54A/mcu/inc/instance/hmatrix.h | 133 + .../arm/SAME54/SAME54A/mcu/inc/instance/i2s.h | 81 + .../arm/SAME54/SAME54A/mcu/inc/instance/icm.h | 77 + .../SAME54/SAME54A/mcu/inc/instance/mclk.h | 61 + .../SAME54/SAME54A/mcu/inc/instance/nvmctrl.h | 75 + .../SAME54A/mcu/inc/instance/osc32kctrl.h | 59 + .../SAME54/SAME54A/mcu/inc/instance/oscctrl.h | 130 + .../arm/SAME54/SAME54A/mcu/inc/instance/pac.h | 69 + .../arm/SAME54/SAME54A/mcu/inc/instance/pcc.h | 58 + .../SAME54/SAME54A/mcu/inc/instance/pdec.h | 80 + .../SAME54/SAME54A/mcu/inc/instance/picop.h | 147 + arch/arm/SAME54/SAME54A/mcu/inc/instance/pm.h | 59 + .../SAME54/SAME54A/mcu/inc/instance/port.h | 184 + .../SAME54/SAME54A/mcu/inc/instance/pukcc.h | 38 + .../SAME54/SAME54A/mcu/inc/instance/qspi.h | 72 + .../SAME54/SAME54A/mcu/inc/instance/ramecc.h | 54 + .../SAME54/SAME54A/mcu/inc/instance/rstc.h | 48 + .../arm/SAME54/SAME54A/mcu/inc/instance/rtc.h | 156 + .../SAME54/SAME54A/mcu/inc/instance/sdhc0.h | 147 + .../SAME54/SAME54A/mcu/inc/instance/sdhc1.h | 147 + .../SAME54/SAME54A/mcu/inc/instance/sercom0.h | 181 + .../SAME54/SAME54A/mcu/inc/instance/sercom1.h | 181 + .../SAME54/SAME54A/mcu/inc/instance/sercom2.h | 181 + .../SAME54/SAME54A/mcu/inc/instance/sercom3.h | 181 + .../SAME54/SAME54A/mcu/inc/instance/sercom4.h | 181 + .../SAME54/SAME54A/mcu/inc/instance/sercom5.h | 181 + .../SAME54/SAME54A/mcu/inc/instance/sercom6.h | 181 + .../SAME54/SAME54A/mcu/inc/instance/sercom7.h | 181 + .../SAME54/SAME54A/mcu/inc/instance/supc.h | 62 + .../arm/SAME54/SAME54A/mcu/inc/instance/tc0.h | 109 + .../arm/SAME54/SAME54A/mcu/inc/instance/tc1.h | 109 + .../arm/SAME54/SAME54A/mcu/inc/instance/tc2.h | 109 + .../arm/SAME54/SAME54A/mcu/inc/instance/tc3.h | 109 + .../arm/SAME54/SAME54A/mcu/inc/instance/tc4.h | 109 + .../arm/SAME54/SAME54A/mcu/inc/instance/tc5.h | 109 + .../arm/SAME54/SAME54A/mcu/inc/instance/tc6.h | 109 + .../arm/SAME54/SAME54A/mcu/inc/instance/tc7.h | 109 + .../SAME54/SAME54A/mcu/inc/instance/tcc0.h | 125 + .../SAME54/SAME54A/mcu/inc/instance/tcc1.h | 115 + .../SAME54/SAME54A/mcu/inc/instance/tcc2.h | 106 + .../SAME54/SAME54A/mcu/inc/instance/tcc3.h | 99 + .../SAME54/SAME54A/mcu/inc/instance/tcc4.h | 99 + .../SAME54/SAME54A/mcu/inc/instance/trng.h | 51 + .../arm/SAME54/SAME54A/mcu/inc/instance/usb.h | 343 + .../arm/SAME54/SAME54A/mcu/inc/instance/wdt.h | 55 + .../SAME54/SAME54A/mcu/inc/pio/same54n19a.h | 5927 +++++++-------- .../SAME54/SAME54A/mcu/inc/pio/same54n20a.h | 5927 +++++++-------- .../SAME54/SAME54A/mcu/inc/pio/same54p19a.h | 6638 ++++++++--------- .../SAME54/SAME54A/mcu/inc/pio/same54p20a.h | 6638 ++++++++--------- arch/arm/SAME54/SAME54A/mcu/inc/sam.h | 92 +- arch/arm/SAME54/SAME54A/mcu/inc/same54.h | 50 + arch/arm/SAME54/SAME54A/mcu/inc/same54n19a.h | 2198 +++--- arch/arm/SAME54/SAME54A/mcu/inc/same54n20a.h | 2198 +++--- arch/arm/SAME54/SAME54A/mcu/inc/same54p19a.h | 2198 +++--- arch/arm/SAME54/SAME54A/mcu/inc/same54p20a.h | 2198 +++--- .../SAME54/SAME54A/mcu/inc/system_same54.h | 96 +- .../SAME54/SAME54A/mcu/src/startup_same54.c | 546 ++ .../SAME54A/mcu/src/startup_same54n19a.c | 409 - .../SAME54A/mcu/src/startup_same54n20a.c | 409 - .../SAME54A/mcu/src/startup_same54p19a.c | 409 - .../SAME54A/mcu/src/startup_same54p20a.c | 409 - .../SAME54/SAME54A/mcu/src/system_same54.c | 64 + .../SAME54A/mcu/src/system_same54n19a.c | 80 - .../SAME54A/mcu/src/system_same54n20a.c | 80 - .../SAME54A/mcu/src/system_same54p19a.c | 80 - .../SAME54A/mcu/src/system_same54p20a.c | 80 - .../arm/SAME54/SAME54A/scripts/same54p20a.cfg | 2 +- manifest/make-manifest.toml | 36 +- scripts/debug.gdb | 1 + test/same54p20a_test/.dir-locals.el | 8 + .../clangd/index/ac.h.561A2BEF4F9E2144.idx | Bin 0 -> 550 bytes .../clangd/index/ac.h.95DC2C71F43C467B.idx | Bin 0 -> 12844 bytes .../clangd/index/adc.h.78B723BE845BA94C.idx | Bin 0 -> 19076 bytes .../clangd/index/adc0.h.F04C5BA88E044775.idx | Bin 0 -> 732 bytes .../clangd/index/adc1.h.80522AEC4E376CC6.idx | Bin 0 -> 748 bytes .../clangd/index/aes.h.099F7AFB07C54E70.idx | Bin 0 -> 7490 bytes .../clangd/index/aes.h.D179BFA6A833B0D3.idx | Bin 0 -> 732 bytes .../clangd/index/can.h.4097B7F76B504C1A.idx | Bin 0 -> 86648 bytes .../clangd/index/can0.h.181761BA047BABA1.idx | Bin 0 -> 1000 bytes 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arch/arm/SAME54/SAME54A/scripts/samd21e18a.cfg => test/same54p20a_test/.igloo/target/same54p20a/scripts/same54p20a.cfg (70%) create mode 100644 test/same54p20a_test/.igloo/target/same54p20a/src/main.d create mode 100644 test/same54p20a_test/.igloo/target/same54p20a/src/main.o create mode 100644 test/same54p20a_test/.projectile create mode 120000 test/same54p20a_test/ESF/cfg create mode 120000 test/same54p20a_test/ESF/common create mode 120000 test/same54p20a_test/ESF/ld create mode 120000 test/same54p20a_test/ESF/mcu create mode 100644 test/same54p20a_test/ESF/modules/core/clocks.c create mode 100644 test/same54p20a_test/ESF/modules/core/clocks.h create mode 100644 test/same54p20a_test/ESF/modules/usart/usart.c create mode 100644 test/same54p20a_test/ESF/modules/usart/usart.h create mode 100644 test/same54p20a_test/cfg/conf_clocks.h create mode 100644 test/same54p20a_test/inc/igloo.h create mode 100644 test/same54p20a_test/src/main.c create mode 100644 test/scripts/bmdebug.gdb create mode 100644 test/scripts/bmpush.gdb create mode 120000 test/scripts/debug.gdb create mode 120000 test/scripts/push.gdb create mode 100644 test/scripts/same54p20a.cfg diff --git a/arch/arm/SAMD21/SAMD21A/scripts/samd21j18a.cfg b/arch/arm/SAMD21/SAMD21A/scripts/samd21j18a.cfg index f4d012d0..b6139e06 100644 --- a/arch/arm/SAMD21/SAMD21A/scripts/samd21j18a.cfg +++ b/arch/arm/SAMD21/SAMD21A/scripts/samd21j18a.cfg @@ -4,9 +4,9 @@ # Transport Select -source [find interface//jlink.cfg] +source [find interface/jlink.cfg] transport select swd # Chip Information set CHIPNAME samd21j18a -source [find target//at91samdXX.cfg] +source [find target/at91samdXX.cfg] diff --git a/arch/arm/SAME54/SAME54A/ld/same54n19a_flash.ld b/arch/arm/SAME54/SAME54A/ld/same54n19a_flash.ld deleted file mode 100644 index 33b8ed9c..00000000 --- a/arch/arm/SAME54/SAME54A/ld/same54n19a_flash.ld +++ /dev/null @@ -1,163 +0,0 @@ -/** - * \file - * - * \brief Linker script for running in internal FLASH on the SAME54N19A - * - * Copyright (c) 2019 Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - - -OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") -OUTPUT_ARCH(arm) -SEARCH_DIR(.) - -/* Memory Spaces Definitions */ -MEMORY -{ - rom (rx) : ORIGIN = 0x00000000, LENGTH = 0x00080000 - ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00030000 - bkupram (rwx) : ORIGIN = 0x47000000, LENGTH = 0x00002000 - qspi (rwx) : ORIGIN = 0x04000000, LENGTH = 0x01000000 -} - -/* The stack size used by the application. NOTE: you need to adjust according to your application. */ -STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0xC000; - -/* Section Definitions */ -SECTIONS -{ - .text : - { - . = ALIGN(4); - _sfixed = .; - KEEP(*(.vectors .vectors.*)) - *(.text .text.* .gnu.linkonce.t.*) - *(.glue_7t) *(.glue_7) - *(.rodata .rodata* .gnu.linkonce.r.*) - *(.ARM.extab* .gnu.linkonce.armextab.*) - - /* Support C constructors, and C destructors in both user code - and the C library. This also provides support for C++ code. */ - . = ALIGN(4); - KEEP(*(.init)) - . = ALIGN(4); - __preinit_array_start = .; - KEEP (*(.preinit_array)) - __preinit_array_end = .; - - . = ALIGN(4); - __init_array_start = .; - KEEP (*(SORT(.init_array.*))) - KEEP (*(.init_array)) - __init_array_end = .; - - . = ALIGN(4); - KEEP (*crtbegin.o(.ctors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) - KEEP (*(SORT(.ctors.*))) - KEEP (*crtend.o(.ctors)) - - . = ALIGN(4); - KEEP(*(.fini)) - - . = ALIGN(4); - __fini_array_start = .; - KEEP (*(.fini_array)) - KEEP (*(SORT(.fini_array.*))) - __fini_array_end = .; - - KEEP (*crtbegin.o(.dtors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) - KEEP (*(SORT(.dtors.*))) - KEEP (*crtend.o(.dtors)) - - . = ALIGN(4); - _efixed = .; /* End of text section */ - } > rom - - /* .ARM.exidx is sorted, so has to go in its own output section. */ - PROVIDE_HIDDEN (__exidx_start = .); - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > rom - PROVIDE_HIDDEN (__exidx_end = .); - - . = ALIGN(4); - _etext = .; - - .relocate : AT (_etext) - { - . = ALIGN(4); - _srelocate = .; - *(.ramfunc .ramfunc.*); - *(.data .data.*); - . = ALIGN(4); - _erelocate = .; - } > ram - - .bkupram (NOLOAD): - { - . = ALIGN(8); - _sbkupram = .; - *(.bkupram .bkupram.*); - . = ALIGN(8); - _ebkupram = .; - } > bkupram - - .qspi (NOLOAD): - { - . = ALIGN(8); - _sqspi = .; - *(.qspi .qspi.*); - . = ALIGN(8); - _eqspi = .; - } > qspi - - /* .bss section which is used for uninitialized data */ - .bss (NOLOAD) : - { - . = ALIGN(4); - _sbss = . ; - _szero = .; - *(.bss .bss.*) - *(COMMON) - . = ALIGN(4); - _ebss = . ; - _ezero = .; - } > ram - - /* stack section */ - .stack (NOLOAD): - { - . = ALIGN(8); - _sstack = .; - . = . + STACK_SIZE; - . = ALIGN(8); - _estack = .; - } > ram - - . = ALIGN(4); - _end = . ; -} diff --git a/arch/arm/SAME54/SAME54A/ld/same54n19a_sram.ld b/arch/arm/SAME54/SAME54A/ld/same54n19a_sram.ld deleted file mode 100644 index c770c7c6..00000000 --- a/arch/arm/SAME54/SAME54A/ld/same54n19a_sram.ld +++ /dev/null @@ -1,162 +0,0 @@ -/** - * \file - * - * \brief Linker script for running in internal SRAM on the SAME54N19A - * - * Copyright (c) 2019 Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - - -OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") -OUTPUT_ARCH(arm) -SEARCH_DIR(.) - -/* Memory Spaces Definitions */ -MEMORY -{ - ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00030000 - bkupram (rwx) : ORIGIN = 0x47000000, LENGTH = 0x00002000 - qspi (rwx) : ORIGIN = 0x04000000, LENGTH = 0x01000000 -} - -/* The stack size used by the application. NOTE: you need to adjust according to your application. */ -STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0xC000; - -/* Section Definitions */ -SECTIONS -{ - .text : - { - . = ALIGN(4); - _sfixed = .; - KEEP(*(.vectors .vectors.*)) - *(.text .text.* .gnu.linkonce.t.*) - *(.glue_7t) *(.glue_7) - *(.rodata .rodata* .gnu.linkonce.r.*) - *(.ARM.extab* .gnu.linkonce.armextab.*) - - /* Support C constructors, and C destructors in both user code - and the C library. This also provides support for C++ code. */ - . = ALIGN(4); - KEEP(*(.init)) - . = ALIGN(4); - __preinit_array_start = .; - KEEP (*(.preinit_array)) - __preinit_array_end = .; - - . = ALIGN(4); - __init_array_start = .; - KEEP (*(SORT(.init_array.*))) - KEEP (*(.init_array)) - __init_array_end = .; - - . = ALIGN(4); - KEEP (*crtbegin.o(.ctors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) - KEEP (*(SORT(.ctors.*))) - KEEP (*crtend.o(.ctors)) - - . = ALIGN(4); - KEEP(*(.fini)) - - . = ALIGN(4); - __fini_array_start = .; - KEEP (*(.fini_array)) - KEEP (*(SORT(.fini_array.*))) - __fini_array_end = .; - - KEEP (*crtbegin.o(.dtors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) - KEEP (*(SORT(.dtors.*))) - KEEP (*crtend.o(.dtors)) - - . = ALIGN(4); - _efixed = .; /* End of text section */ - } > ram - - /* .ARM.exidx is sorted, so has to go in its own output section. */ - PROVIDE_HIDDEN (__exidx_start = .); - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > ram - PROVIDE_HIDDEN (__exidx_end = .); - - . = ALIGN(4); - _etext = .; - - .relocate : AT (_etext) - { - . = ALIGN(4); - _srelocate = .; - *(.ramfunc .ramfunc.*); - *(.data .data.*); - . = ALIGN(4); - _erelocate = .; - } > ram - - .bkupram (NOLOAD): - { - . = ALIGN(8); - _sbkupram = .; - *(.bkupram .bkupram.*); - . = ALIGN(8); - _ebkupram = .; - } > bkupram - - .qspi (NOLOAD): - { - . = ALIGN(8); - _sqspi = .; - *(.qspi .qspi.*); - . = ALIGN(8); - _eqspi = .; - } > qspi - - /* .bss section which is used for uninitialized data */ - .bss (NOLOAD) : - { - . = ALIGN(4); - _sbss = . ; - _szero = .; - *(.bss .bss.*) - *(COMMON) - . = ALIGN(4); - _ebss = . ; - _ezero = .; - } > ram - - /* stack section */ - .stack (NOLOAD): - { - . = ALIGN(8); - _sstack = .; - . = . + STACK_SIZE; - . = ALIGN(8); - _estack = .; - } > ram - - . = ALIGN(4); - _end = . ; -} diff --git a/arch/arm/SAME54/SAME54A/ld/same54n20a_flash.ld b/arch/arm/SAME54/SAME54A/ld/same54n20a_flash.ld deleted file mode 100644 index b6a797bb..00000000 --- a/arch/arm/SAME54/SAME54A/ld/same54n20a_flash.ld +++ /dev/null @@ -1,163 +0,0 @@ -/** - * \file - * - * \brief Linker script for running in internal FLASH on the SAME54N20A - * - * Copyright (c) 2019 Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - - -OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") -OUTPUT_ARCH(arm) -SEARCH_DIR(.) - -/* Memory Spaces Definitions */ -MEMORY -{ - rom (rx) : ORIGIN = 0x00000000, LENGTH = 0x00100000 - ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00040000 - bkupram (rwx) : ORIGIN = 0x47000000, LENGTH = 0x00002000 - qspi (rwx) : ORIGIN = 0x04000000, LENGTH = 0x01000000 -} - -/* The stack size used by the application. NOTE: you need to adjust according to your application. */ -STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x10000; - -/* Section Definitions */ -SECTIONS -{ - .text : - { - . = ALIGN(4); - _sfixed = .; - KEEP(*(.vectors .vectors.*)) - *(.text .text.* .gnu.linkonce.t.*) - *(.glue_7t) *(.glue_7) - *(.rodata .rodata* .gnu.linkonce.r.*) - *(.ARM.extab* .gnu.linkonce.armextab.*) - - /* Support C constructors, and C destructors in both user code - and the C library. This also provides support for C++ code. */ - . = ALIGN(4); - KEEP(*(.init)) - . = ALIGN(4); - __preinit_array_start = .; - KEEP (*(.preinit_array)) - __preinit_array_end = .; - - . = ALIGN(4); - __init_array_start = .; - KEEP (*(SORT(.init_array.*))) - KEEP (*(.init_array)) - __init_array_end = .; - - . = ALIGN(4); - KEEP (*crtbegin.o(.ctors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) - KEEP (*(SORT(.ctors.*))) - KEEP (*crtend.o(.ctors)) - - . = ALIGN(4); - KEEP(*(.fini)) - - . = ALIGN(4); - __fini_array_start = .; - KEEP (*(.fini_array)) - KEEP (*(SORT(.fini_array.*))) - __fini_array_end = .; - - KEEP (*crtbegin.o(.dtors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) - KEEP (*(SORT(.dtors.*))) - KEEP (*crtend.o(.dtors)) - - . = ALIGN(4); - _efixed = .; /* End of text section */ - } > rom - - /* .ARM.exidx is sorted, so has to go in its own output section. */ - PROVIDE_HIDDEN (__exidx_start = .); - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > rom - PROVIDE_HIDDEN (__exidx_end = .); - - . = ALIGN(4); - _etext = .; - - .relocate : AT (_etext) - { - . = ALIGN(4); - _srelocate = .; - *(.ramfunc .ramfunc.*); - *(.data .data.*); - . = ALIGN(4); - _erelocate = .; - } > ram - - .bkupram (NOLOAD): - { - . = ALIGN(8); - _sbkupram = .; - *(.bkupram .bkupram.*); - . = ALIGN(8); - _ebkupram = .; - } > bkupram - - .qspi (NOLOAD): - { - . = ALIGN(8); - _sqspi = .; - *(.qspi .qspi.*); - . = ALIGN(8); - _eqspi = .; - } > qspi - - /* .bss section which is used for uninitialized data */ - .bss (NOLOAD) : - { - . = ALIGN(4); - _sbss = . ; - _szero = .; - *(.bss .bss.*) - *(COMMON) - . = ALIGN(4); - _ebss = . ; - _ezero = .; - } > ram - - /* stack section */ - .stack (NOLOAD): - { - . = ALIGN(8); - _sstack = .; - . = . + STACK_SIZE; - . = ALIGN(8); - _estack = .; - } > ram - - . = ALIGN(4); - _end = . ; -} diff --git a/arch/arm/SAME54/SAME54A/ld/same54n20a_sram.ld b/arch/arm/SAME54/SAME54A/ld/same54n20a_sram.ld deleted file mode 100644 index 340af27a..00000000 --- a/arch/arm/SAME54/SAME54A/ld/same54n20a_sram.ld +++ /dev/null @@ -1,162 +0,0 @@ -/** - * \file - * - * \brief Linker script for running in internal SRAM on the SAME54N20A - * - * Copyright (c) 2019 Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - - -OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") -OUTPUT_ARCH(arm) -SEARCH_DIR(.) - -/* Memory Spaces Definitions */ -MEMORY -{ - ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00040000 - bkupram (rwx) : ORIGIN = 0x47000000, LENGTH = 0x00002000 - qspi (rwx) : ORIGIN = 0x04000000, LENGTH = 0x01000000 -} - -/* The stack size used by the application. NOTE: you need to adjust according to your application. */ -STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x10000; - -/* Section Definitions */ -SECTIONS -{ - .text : - { - . = ALIGN(4); - _sfixed = .; - KEEP(*(.vectors .vectors.*)) - *(.text .text.* .gnu.linkonce.t.*) - *(.glue_7t) *(.glue_7) - *(.rodata .rodata* .gnu.linkonce.r.*) - *(.ARM.extab* .gnu.linkonce.armextab.*) - - /* Support C constructors, and C destructors in both user code - and the C library. This also provides support for C++ code. */ - . = ALIGN(4); - KEEP(*(.init)) - . = ALIGN(4); - __preinit_array_start = .; - KEEP (*(.preinit_array)) - __preinit_array_end = .; - - . = ALIGN(4); - __init_array_start = .; - KEEP (*(SORT(.init_array.*))) - KEEP (*(.init_array)) - __init_array_end = .; - - . = ALIGN(4); - KEEP (*crtbegin.o(.ctors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) - KEEP (*(SORT(.ctors.*))) - KEEP (*crtend.o(.ctors)) - - . = ALIGN(4); - KEEP(*(.fini)) - - . = ALIGN(4); - __fini_array_start = .; - KEEP (*(.fini_array)) - KEEP (*(SORT(.fini_array.*))) - __fini_array_end = .; - - KEEP (*crtbegin.o(.dtors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) - KEEP (*(SORT(.dtors.*))) - KEEP (*crtend.o(.dtors)) - - . = ALIGN(4); - _efixed = .; /* End of text section */ - } > ram - - /* .ARM.exidx is sorted, so has to go in its own output section. */ - PROVIDE_HIDDEN (__exidx_start = .); - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > ram - PROVIDE_HIDDEN (__exidx_end = .); - - . = ALIGN(4); - _etext = .; - - .relocate : AT (_etext) - { - . = ALIGN(4); - _srelocate = .; - *(.ramfunc .ramfunc.*); - *(.data .data.*); - . = ALIGN(4); - _erelocate = .; - } > ram - - .bkupram (NOLOAD): - { - . = ALIGN(8); - _sbkupram = .; - *(.bkupram .bkupram.*); - . = ALIGN(8); - _ebkupram = .; - } > bkupram - - .qspi (NOLOAD): - { - . = ALIGN(8); - _sqspi = .; - *(.qspi .qspi.*); - . = ALIGN(8); - _eqspi = .; - } > qspi - - /* .bss section which is used for uninitialized data */ - .bss (NOLOAD) : - { - . = ALIGN(4); - _sbss = . ; - _szero = .; - *(.bss .bss.*) - *(COMMON) - . = ALIGN(4); - _ebss = . ; - _ezero = .; - } > ram - - /* stack section */ - .stack (NOLOAD): - { - . = ALIGN(8); - _sstack = .; - . = . + STACK_SIZE; - . = ALIGN(8); - _estack = .; - } > ram - - . = ALIGN(4); - _end = . ; -} diff --git a/arch/arm/SAME54/SAME54A/ld/same54p19a_flash.ld b/arch/arm/SAME54/SAME54A/ld/same54p19a_flash.ld deleted file mode 100644 index f60307a3..00000000 --- a/arch/arm/SAME54/SAME54A/ld/same54p19a_flash.ld +++ /dev/null @@ -1,163 +0,0 @@ -/** - * \file - * - * \brief Linker script for running in internal FLASH on the SAME54P19A - * - * Copyright (c) 2019 Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - - -OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") -OUTPUT_ARCH(arm) -SEARCH_DIR(.) - -/* Memory Spaces Definitions */ -MEMORY -{ - rom (rx) : ORIGIN = 0x00000000, LENGTH = 0x00080000 - ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00030000 - bkupram (rwx) : ORIGIN = 0x47000000, LENGTH = 0x00002000 - qspi (rwx) : ORIGIN = 0x04000000, LENGTH = 0x01000000 -} - -/* The stack size used by the application. NOTE: you need to adjust according to your application. */ -STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0xC000; - -/* Section Definitions */ -SECTIONS -{ - .text : - { - . = ALIGN(4); - _sfixed = .; - KEEP(*(.vectors .vectors.*)) - *(.text .text.* .gnu.linkonce.t.*) - *(.glue_7t) *(.glue_7) - *(.rodata .rodata* .gnu.linkonce.r.*) - *(.ARM.extab* .gnu.linkonce.armextab.*) - - /* Support C constructors, and C destructors in both user code - and the C library. This also provides support for C++ code. */ - . = ALIGN(4); - KEEP(*(.init)) - . = ALIGN(4); - __preinit_array_start = .; - KEEP (*(.preinit_array)) - __preinit_array_end = .; - - . = ALIGN(4); - __init_array_start = .; - KEEP (*(SORT(.init_array.*))) - KEEP (*(.init_array)) - __init_array_end = .; - - . = ALIGN(4); - KEEP (*crtbegin.o(.ctors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) - KEEP (*(SORT(.ctors.*))) - KEEP (*crtend.o(.ctors)) - - . = ALIGN(4); - KEEP(*(.fini)) - - . = ALIGN(4); - __fini_array_start = .; - KEEP (*(.fini_array)) - KEEP (*(SORT(.fini_array.*))) - __fini_array_end = .; - - KEEP (*crtbegin.o(.dtors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) - KEEP (*(SORT(.dtors.*))) - KEEP (*crtend.o(.dtors)) - - . = ALIGN(4); - _efixed = .; /* End of text section */ - } > rom - - /* .ARM.exidx is sorted, so has to go in its own output section. */ - PROVIDE_HIDDEN (__exidx_start = .); - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > rom - PROVIDE_HIDDEN (__exidx_end = .); - - . = ALIGN(4); - _etext = .; - - .relocate : AT (_etext) - { - . = ALIGN(4); - _srelocate = .; - *(.ramfunc .ramfunc.*); - *(.data .data.*); - . = ALIGN(4); - _erelocate = .; - } > ram - - .bkupram (NOLOAD): - { - . = ALIGN(8); - _sbkupram = .; - *(.bkupram .bkupram.*); - . = ALIGN(8); - _ebkupram = .; - } > bkupram - - .qspi (NOLOAD): - { - . = ALIGN(8); - _sqspi = .; - *(.qspi .qspi.*); - . = ALIGN(8); - _eqspi = .; - } > qspi - - /* .bss section which is used for uninitialized data */ - .bss (NOLOAD) : - { - . = ALIGN(4); - _sbss = . ; - _szero = .; - *(.bss .bss.*) - *(COMMON) - . = ALIGN(4); - _ebss = . ; - _ezero = .; - } > ram - - /* stack section */ - .stack (NOLOAD): - { - . = ALIGN(8); - _sstack = .; - . = . + STACK_SIZE; - . = ALIGN(8); - _estack = .; - } > ram - - . = ALIGN(4); - _end = . ; -} diff --git a/arch/arm/SAME54/SAME54A/ld/same54p19a_sram.ld b/arch/arm/SAME54/SAME54A/ld/same54p19a_sram.ld deleted file mode 100644 index 9c45843b..00000000 --- a/arch/arm/SAME54/SAME54A/ld/same54p19a_sram.ld +++ /dev/null @@ -1,162 +0,0 @@ -/** - * \file - * - * \brief Linker script for running in internal SRAM on the SAME54P19A - * - * Copyright (c) 2019 Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - - -OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") -OUTPUT_ARCH(arm) -SEARCH_DIR(.) - -/* Memory Spaces Definitions */ -MEMORY -{ - ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00030000 - bkupram (rwx) : ORIGIN = 0x47000000, LENGTH = 0x00002000 - qspi (rwx) : ORIGIN = 0x04000000, LENGTH = 0x01000000 -} - -/* The stack size used by the application. NOTE: you need to adjust according to your application. */ -STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0xC000; - -/* Section Definitions */ -SECTIONS -{ - .text : - { - . = ALIGN(4); - _sfixed = .; - KEEP(*(.vectors .vectors.*)) - *(.text .text.* .gnu.linkonce.t.*) - *(.glue_7t) *(.glue_7) - *(.rodata .rodata* .gnu.linkonce.r.*) - *(.ARM.extab* .gnu.linkonce.armextab.*) - - /* Support C constructors, and C destructors in both user code - and the C library. This also provides support for C++ code. */ - . = ALIGN(4); - KEEP(*(.init)) - . = ALIGN(4); - __preinit_array_start = .; - KEEP (*(.preinit_array)) - __preinit_array_end = .; - - . = ALIGN(4); - __init_array_start = .; - KEEP (*(SORT(.init_array.*))) - KEEP (*(.init_array)) - __init_array_end = .; - - . = ALIGN(4); - KEEP (*crtbegin.o(.ctors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) - KEEP (*(SORT(.ctors.*))) - KEEP (*crtend.o(.ctors)) - - . = ALIGN(4); - KEEP(*(.fini)) - - . = ALIGN(4); - __fini_array_start = .; - KEEP (*(.fini_array)) - KEEP (*(SORT(.fini_array.*))) - __fini_array_end = .; - - KEEP (*crtbegin.o(.dtors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) - KEEP (*(SORT(.dtors.*))) - KEEP (*crtend.o(.dtors)) - - . = ALIGN(4); - _efixed = .; /* End of text section */ - } > ram - - /* .ARM.exidx is sorted, so has to go in its own output section. */ - PROVIDE_HIDDEN (__exidx_start = .); - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > ram - PROVIDE_HIDDEN (__exidx_end = .); - - . = ALIGN(4); - _etext = .; - - .relocate : AT (_etext) - { - . = ALIGN(4); - _srelocate = .; - *(.ramfunc .ramfunc.*); - *(.data .data.*); - . = ALIGN(4); - _erelocate = .; - } > ram - - .bkupram (NOLOAD): - { - . = ALIGN(8); - _sbkupram = .; - *(.bkupram .bkupram.*); - . = ALIGN(8); - _ebkupram = .; - } > bkupram - - .qspi (NOLOAD): - { - . = ALIGN(8); - _sqspi = .; - *(.qspi .qspi.*); - . = ALIGN(8); - _eqspi = .; - } > qspi - - /* .bss section which is used for uninitialized data */ - .bss (NOLOAD) : - { - . = ALIGN(4); - _sbss = . ; - _szero = .; - *(.bss .bss.*) - *(COMMON) - . = ALIGN(4); - _ebss = . ; - _ezero = .; - } > ram - - /* stack section */ - .stack (NOLOAD): - { - . = ALIGN(8); - _sstack = .; - . = . + STACK_SIZE; - . = ALIGN(8); - _estack = .; - } > ram - - . = ALIGN(4); - _end = . ; -} diff --git a/arch/arm/SAME54/SAME54A/manifest/same54a.toml b/arch/arm/SAME54/SAME54A/manifest/same54a.toml index d7f4774a..d7294e9c 100644 --- a/arch/arm/SAME54/SAME54A/manifest/same54a.toml +++ b/arch/arm/SAME54/SAME54A/manifest/same54a.toml @@ -3,9 +3,9 @@ common = "arch/arm/common" mcu = "arch/arm/SAME54/SAME54A/mcu/" ld = "arch/arm/SAME54/SAME54A/ld/" cfg = "arch/arm/SAME54/SAME54A/manifest/" - [esf.includes] IGLOO_INCLUDES = ["sam.h"] +# These are defaults. Once a project is generated, the .cfg can be freely edited without fear of anything being overwritten. However, I do not recommend editing any of the _cfg variables. [esf.openocd] scripts = "arch/arm/SAME54/SAME54A/scripts/" diff --git a/arch/arm/SAME54/SAME54A/mcu/inc/component-version.h b/arch/arm/SAME54/SAME54A/mcu/inc/component-version.h index 672dd5ee..d786d20d 100644 --- a/arch/arm/SAME54/SAME54A/mcu/inc/component-version.h +++ b/arch/arm/SAME54/SAME54A/mcu/inc/component-version.h @@ -1,64 +1,64 @@ -/** - * \file - * - * \brief Component version header file - * - * Copyright (c) 2020 Atmel Corporation, a wholly owned subsidiary of Microchip Technology Inc. - * - * \license_start - * - * \page License - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \license_stop - * - */ - -#ifndef _COMPONENT_VERSION_H_INCLUDED -#define _COMPONENT_VERSION_H_INCLUDED - -#define COMPONENT_VERSION_MAJOR 3 -#define COMPONENT_VERSION_MINOR 3 - -// -// The COMPONENT_VERSION define is composed of the major and the minor version number. -// -// The last four digits of the COMPONENT_VERSION is the minor version with leading zeros. -// The rest of the COMPONENT_VERSION is the major version. -// -#define COMPONENT_VERSION 30003 - -// -// The build number does not refer to the component, but to the build number -// of the device pack that provides the component. -// -#define BUILD_NUMBER 64 - -// -// The COMPONENT_VERSION_STRING is a string (enclosed in ") that can be used for logging or embedding. -// -#define COMPONENT_VERSION_STRING "3.3" - -// -// The COMPONENT_DATE_STRING contains a timestamp of when the pack was generated. -// -// The COMPONENT_DATE_STRING is written out using the following strftime pattern. -// -// "%Y-%m-%d %H:%M:%S" -// -// -#define COMPONENT_DATE_STRING "2020-04-28 23:52:31" - -#endif/* #ifndef _COMPONENT_VERSION_H_INCLUDED */ - +/** + * \file + * + * \brief Component version header file + * + * Copyright (c) 2019 Atmel Corporation, a wholly owned subsidiary of Microchip Technology Inc. + * + * \license_start + * + * \page License + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \license_stop + * + */ + +#ifndef _COMPONENT_VERSION_H_INCLUDED +#define _COMPONENT_VERSION_H_INCLUDED + +#define COMPONENT_VERSION_MAJOR 1 +#define COMPONENT_VERSION_MINOR 1 + +// +// The COMPONENT_VERSION define is composed of the major and the minor version number. +// +// The last four digits of the COMPONENT_VERSION is the minor version with leading zeros. +// The rest of the COMPONENT_VERSION is the major version. +// +#define COMPONENT_VERSION 10001 + +// +// The build number does not refer to the component, but to the build number +// of the device pack that provides the component. +// +#define BUILD_NUMBER 134 + +// +// The COMPONENT_VERSION_STRING is a string (enclosed in ") that can be used for logging or embedding. +// +#define COMPONENT_VERSION_STRING "1.1" + +// +// The COMPONENT_DATE_STRING contains a timestamp of when the pack was generated. +// +// The COMPONENT_DATE_STRING is written out using the following strftime pattern. +// +// "%Y-%m-%d %H:%M:%S" +// +// +#define COMPONENT_DATE_STRING "2019-04-09 08:16:19" + +#endif/* #ifndef _COMPONENT_VERSION_H_INCLUDED */ + diff --git a/arch/arm/SAME54/SAME54A/mcu/inc/component/ac.h b/arch/arm/SAME54/SAME54A/mcu/inc/component/ac.h index 417aad88..e8a9fc42 100644 --- a/arch/arm/SAME54/SAME54A/mcu/inc/component/ac.h +++ b/arch/arm/SAME54/SAME54A/mcu/inc/component/ac.h @@ -1,410 +1,598 @@ -/** - * \brief Component description for AC - * - * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries. - * - * Subject to your compliance with these terms, you may use Microchip software and any derivatives - * exclusively with Microchip products. It is your responsibility to comply with third party license - * terms applicable to your use of third party software (including open source software) that may - * accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, - * APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND - * FITNESS FOR A PARTICULAR PURPOSE. - * - * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF - * MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT - * EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - */ - -/* file generated from device description version 2020-03-12T17:27:04Z */ -#ifndef _SAME54_AC_COMPONENT_H_ -#define _SAME54_AC_COMPONENT_H_ - -/* ************************************************************************** */ -/* SOFTWARE API DEFINITION FOR AC */ -/* ************************************************************************** */ - -/* -------- AC_CTRLA : (AC Offset: 0x00) (R/W 8) Control A -------- */ -#define AC_CTRLA_RESETVALUE _U_(0x00) /**< (AC_CTRLA) Control A Reset Value */ - -#define AC_CTRLA_SWRST_Pos _U_(0) /**< (AC_CTRLA) Software Reset Position */ -#define AC_CTRLA_SWRST_Msk (_U_(0x1) << AC_CTRLA_SWRST_Pos) /**< (AC_CTRLA) Software Reset Mask */ -#define AC_CTRLA_SWRST(value) (AC_CTRLA_SWRST_Msk & ((value) << AC_CTRLA_SWRST_Pos)) -#define AC_CTRLA_ENABLE_Pos _U_(1) /**< (AC_CTRLA) Enable Position */ -#define AC_CTRLA_ENABLE_Msk (_U_(0x1) << AC_CTRLA_ENABLE_Pos) /**< (AC_CTRLA) Enable Mask */ -#define AC_CTRLA_ENABLE(value) (AC_CTRLA_ENABLE_Msk & ((value) << AC_CTRLA_ENABLE_Pos)) -#define AC_CTRLA_Msk _U_(0x03) /**< (AC_CTRLA) Register Mask */ - - -/* -------- AC_CTRLB : (AC Offset: 0x01) ( /W 8) Control B -------- */ -#define AC_CTRLB_RESETVALUE _U_(0x00) /**< (AC_CTRLB) Control B Reset Value */ - -#define AC_CTRLB_START0_Pos _U_(0) /**< (AC_CTRLB) Comparator 0 Start Comparison Position */ -#define AC_CTRLB_START0_Msk (_U_(0x1) << AC_CTRLB_START0_Pos) /**< (AC_CTRLB) Comparator 0 Start Comparison Mask */ -#define AC_CTRLB_START0(value) (AC_CTRLB_START0_Msk & ((value) << AC_CTRLB_START0_Pos)) -#define AC_CTRLB_START1_Pos _U_(1) /**< (AC_CTRLB) Comparator 1 Start Comparison Position */ -#define AC_CTRLB_START1_Msk (_U_(0x1) << AC_CTRLB_START1_Pos) /**< (AC_CTRLB) Comparator 1 Start Comparison Mask */ -#define AC_CTRLB_START1(value) (AC_CTRLB_START1_Msk & ((value) << AC_CTRLB_START1_Pos)) -#define AC_CTRLB_Msk _U_(0x03) /**< (AC_CTRLB) Register Mask */ - -#define AC_CTRLB_START_Pos _U_(0) /**< (AC_CTRLB Position) Comparator x Start Comparison */ -#define AC_CTRLB_START_Msk (_U_(0x3) << AC_CTRLB_START_Pos) /**< (AC_CTRLB Mask) START */ -#define AC_CTRLB_START(value) (AC_CTRLB_START_Msk & ((value) << AC_CTRLB_START_Pos)) - -/* -------- AC_EVCTRL : (AC Offset: 0x02) (R/W 16) Event Control -------- */ -#define AC_EVCTRL_RESETVALUE _U_(0x00) /**< (AC_EVCTRL) Event Control Reset Value */ - -#define AC_EVCTRL_COMPEO0_Pos _U_(0) /**< (AC_EVCTRL) Comparator 0 Event Output Enable Position */ -#define AC_EVCTRL_COMPEO0_Msk (_U_(0x1) << AC_EVCTRL_COMPEO0_Pos) /**< (AC_EVCTRL) Comparator 0 Event Output Enable Mask */ -#define AC_EVCTRL_COMPEO0(value) (AC_EVCTRL_COMPEO0_Msk & ((value) << AC_EVCTRL_COMPEO0_Pos)) -#define AC_EVCTRL_COMPEO1_Pos _U_(1) /**< (AC_EVCTRL) Comparator 1 Event Output Enable Position */ -#define AC_EVCTRL_COMPEO1_Msk (_U_(0x1) << AC_EVCTRL_COMPEO1_Pos) /**< (AC_EVCTRL) Comparator 1 Event Output Enable Mask */ -#define AC_EVCTRL_COMPEO1(value) (AC_EVCTRL_COMPEO1_Msk & ((value) << AC_EVCTRL_COMPEO1_Pos)) -#define AC_EVCTRL_WINEO0_Pos _U_(4) /**< (AC_EVCTRL) Window 0 Event Output Enable Position */ -#define AC_EVCTRL_WINEO0_Msk (_U_(0x1) << AC_EVCTRL_WINEO0_Pos) /**< (AC_EVCTRL) Window 0 Event Output Enable Mask */ -#define AC_EVCTRL_WINEO0(value) (AC_EVCTRL_WINEO0_Msk & ((value) << AC_EVCTRL_WINEO0_Pos)) -#define AC_EVCTRL_COMPEI0_Pos _U_(8) /**< (AC_EVCTRL) Comparator 0 Event Input Enable Position */ -#define AC_EVCTRL_COMPEI0_Msk (_U_(0x1) << AC_EVCTRL_COMPEI0_Pos) /**< (AC_EVCTRL) Comparator 0 Event Input Enable Mask */ -#define AC_EVCTRL_COMPEI0(value) (AC_EVCTRL_COMPEI0_Msk & ((value) << AC_EVCTRL_COMPEI0_Pos)) -#define AC_EVCTRL_COMPEI1_Pos _U_(9) /**< (AC_EVCTRL) Comparator 1 Event Input Enable Position */ -#define AC_EVCTRL_COMPEI1_Msk (_U_(0x1) << AC_EVCTRL_COMPEI1_Pos) /**< (AC_EVCTRL) Comparator 1 Event Input Enable Mask */ -#define AC_EVCTRL_COMPEI1(value) (AC_EVCTRL_COMPEI1_Msk & ((value) << AC_EVCTRL_COMPEI1_Pos)) -#define AC_EVCTRL_INVEI0_Pos _U_(12) /**< (AC_EVCTRL) Comparator 0 Input Event Invert Enable Position */ -#define AC_EVCTRL_INVEI0_Msk (_U_(0x1) << AC_EVCTRL_INVEI0_Pos) /**< (AC_EVCTRL) Comparator 0 Input Event Invert Enable Mask */ -#define AC_EVCTRL_INVEI0(value) (AC_EVCTRL_INVEI0_Msk & ((value) << AC_EVCTRL_INVEI0_Pos)) -#define AC_EVCTRL_INVEI1_Pos _U_(13) /**< (AC_EVCTRL) Comparator 1 Input Event Invert Enable Position */ -#define AC_EVCTRL_INVEI1_Msk (_U_(0x1) << AC_EVCTRL_INVEI1_Pos) /**< (AC_EVCTRL) Comparator 1 Input Event Invert Enable Mask */ -#define AC_EVCTRL_INVEI1(value) (AC_EVCTRL_INVEI1_Msk & ((value) << AC_EVCTRL_INVEI1_Pos)) -#define AC_EVCTRL_Msk _U_(0x3313) /**< (AC_EVCTRL) Register Mask */ - -#define AC_EVCTRL_COMPEO_Pos _U_(0) /**< (AC_EVCTRL Position) Comparator x Event Output Enable */ -#define AC_EVCTRL_COMPEO_Msk (_U_(0x3) << AC_EVCTRL_COMPEO_Pos) /**< (AC_EVCTRL Mask) COMPEO */ -#define AC_EVCTRL_COMPEO(value) (AC_EVCTRL_COMPEO_Msk & ((value) << AC_EVCTRL_COMPEO_Pos)) -#define AC_EVCTRL_WINEO_Pos _U_(4) /**< (AC_EVCTRL Position) Window x Event Output Enable */ -#define AC_EVCTRL_WINEO_Msk (_U_(0x1) << AC_EVCTRL_WINEO_Pos) /**< (AC_EVCTRL Mask) WINEO */ -#define AC_EVCTRL_WINEO(value) (AC_EVCTRL_WINEO_Msk & ((value) << AC_EVCTRL_WINEO_Pos)) -#define AC_EVCTRL_COMPEI_Pos _U_(8) /**< (AC_EVCTRL Position) Comparator x Event Input Enable */ -#define AC_EVCTRL_COMPEI_Msk (_U_(0x3) << AC_EVCTRL_COMPEI_Pos) /**< (AC_EVCTRL Mask) COMPEI */ -#define AC_EVCTRL_COMPEI(value) (AC_EVCTRL_COMPEI_Msk & ((value) << AC_EVCTRL_COMPEI_Pos)) -#define AC_EVCTRL_INVEI_Pos _U_(12) /**< (AC_EVCTRL Position) Comparator x Input Event Invert Enable */ -#define AC_EVCTRL_INVEI_Msk (_U_(0x3) << AC_EVCTRL_INVEI_Pos) /**< (AC_EVCTRL Mask) INVEI */ -#define AC_EVCTRL_INVEI(value) (AC_EVCTRL_INVEI_Msk & ((value) << AC_EVCTRL_INVEI_Pos)) - -/* -------- AC_INTENCLR : (AC Offset: 0x04) (R/W 8) Interrupt Enable Clear -------- */ -#define AC_INTENCLR_RESETVALUE _U_(0x00) /**< (AC_INTENCLR) Interrupt Enable Clear Reset Value */ - -#define AC_INTENCLR_COMP0_Pos _U_(0) /**< (AC_INTENCLR) Comparator 0 Interrupt Enable Position */ -#define AC_INTENCLR_COMP0_Msk (_U_(0x1) << AC_INTENCLR_COMP0_Pos) /**< (AC_INTENCLR) Comparator 0 Interrupt Enable Mask */ -#define AC_INTENCLR_COMP0(value) (AC_INTENCLR_COMP0_Msk & ((value) << AC_INTENCLR_COMP0_Pos)) -#define AC_INTENCLR_COMP1_Pos _U_(1) /**< (AC_INTENCLR) Comparator 1 Interrupt Enable Position */ -#define AC_INTENCLR_COMP1_Msk (_U_(0x1) << AC_INTENCLR_COMP1_Pos) /**< (AC_INTENCLR) Comparator 1 Interrupt Enable Mask */ -#define AC_INTENCLR_COMP1(value) (AC_INTENCLR_COMP1_Msk & ((value) << AC_INTENCLR_COMP1_Pos)) -#define AC_INTENCLR_WIN0_Pos _U_(4) /**< (AC_INTENCLR) Window 0 Interrupt Enable Position */ -#define AC_INTENCLR_WIN0_Msk (_U_(0x1) << AC_INTENCLR_WIN0_Pos) /**< (AC_INTENCLR) Window 0 Interrupt Enable Mask */ -#define AC_INTENCLR_WIN0(value) (AC_INTENCLR_WIN0_Msk & ((value) << AC_INTENCLR_WIN0_Pos)) -#define AC_INTENCLR_Msk _U_(0x13) /**< (AC_INTENCLR) Register Mask */ - -#define AC_INTENCLR_COMP_Pos _U_(0) /**< (AC_INTENCLR Position) Comparator x Interrupt Enable */ -#define AC_INTENCLR_COMP_Msk (_U_(0x3) << AC_INTENCLR_COMP_Pos) /**< (AC_INTENCLR Mask) COMP */ -#define AC_INTENCLR_COMP(value) (AC_INTENCLR_COMP_Msk & ((value) << AC_INTENCLR_COMP_Pos)) -#define AC_INTENCLR_WIN_Pos _U_(4) /**< (AC_INTENCLR Position) Window x Interrupt Enable */ -#define AC_INTENCLR_WIN_Msk (_U_(0x1) << AC_INTENCLR_WIN_Pos) /**< (AC_INTENCLR Mask) WIN */ -#define AC_INTENCLR_WIN(value) (AC_INTENCLR_WIN_Msk & ((value) << AC_INTENCLR_WIN_Pos)) - -/* -------- AC_INTENSET : (AC Offset: 0x05) (R/W 8) Interrupt Enable Set -------- */ -#define AC_INTENSET_RESETVALUE _U_(0x00) /**< (AC_INTENSET) Interrupt Enable Set Reset Value */ - -#define AC_INTENSET_COMP0_Pos _U_(0) /**< (AC_INTENSET) Comparator 0 Interrupt Enable Position */ -#define AC_INTENSET_COMP0_Msk (_U_(0x1) << AC_INTENSET_COMP0_Pos) /**< (AC_INTENSET) Comparator 0 Interrupt Enable Mask */ -#define AC_INTENSET_COMP0(value) (AC_INTENSET_COMP0_Msk & ((value) << AC_INTENSET_COMP0_Pos)) -#define AC_INTENSET_COMP1_Pos _U_(1) /**< (AC_INTENSET) Comparator 1 Interrupt Enable Position */ -#define AC_INTENSET_COMP1_Msk (_U_(0x1) << AC_INTENSET_COMP1_Pos) /**< (AC_INTENSET) Comparator 1 Interrupt Enable Mask */ -#define AC_INTENSET_COMP1(value) (AC_INTENSET_COMP1_Msk & ((value) << AC_INTENSET_COMP1_Pos)) -#define AC_INTENSET_WIN0_Pos _U_(4) /**< (AC_INTENSET) Window 0 Interrupt Enable Position */ -#define AC_INTENSET_WIN0_Msk (_U_(0x1) << AC_INTENSET_WIN0_Pos) /**< (AC_INTENSET) Window 0 Interrupt Enable Mask */ -#define AC_INTENSET_WIN0(value) (AC_INTENSET_WIN0_Msk & ((value) << AC_INTENSET_WIN0_Pos)) -#define AC_INTENSET_Msk _U_(0x13) /**< (AC_INTENSET) Register Mask */ - -#define AC_INTENSET_COMP_Pos _U_(0) /**< (AC_INTENSET Position) Comparator x Interrupt Enable */ -#define AC_INTENSET_COMP_Msk (_U_(0x3) << AC_INTENSET_COMP_Pos) /**< (AC_INTENSET Mask) COMP */ -#define AC_INTENSET_COMP(value) (AC_INTENSET_COMP_Msk & ((value) << AC_INTENSET_COMP_Pos)) -#define AC_INTENSET_WIN_Pos _U_(4) /**< (AC_INTENSET Position) Window x Interrupt Enable */ -#define AC_INTENSET_WIN_Msk (_U_(0x1) << AC_INTENSET_WIN_Pos) /**< (AC_INTENSET Mask) WIN */ -#define AC_INTENSET_WIN(value) (AC_INTENSET_WIN_Msk & ((value) << AC_INTENSET_WIN_Pos)) - -/* -------- AC_INTFLAG : (AC Offset: 0x06) (R/W 8) Interrupt Flag Status and Clear -------- */ -#define AC_INTFLAG_RESETVALUE _U_(0x00) /**< (AC_INTFLAG) Interrupt Flag Status and Clear Reset Value */ - -#define AC_INTFLAG_COMP0_Pos _U_(0) /**< (AC_INTFLAG) Comparator 0 Position */ -#define AC_INTFLAG_COMP0_Msk (_U_(0x1) << AC_INTFLAG_COMP0_Pos) /**< (AC_INTFLAG) Comparator 0 Mask */ -#define AC_INTFLAG_COMP0(value) (AC_INTFLAG_COMP0_Msk & ((value) << AC_INTFLAG_COMP0_Pos)) -#define AC_INTFLAG_COMP1_Pos _U_(1) /**< (AC_INTFLAG) Comparator 1 Position */ -#define AC_INTFLAG_COMP1_Msk (_U_(0x1) << AC_INTFLAG_COMP1_Pos) /**< (AC_INTFLAG) Comparator 1 Mask */ -#define AC_INTFLAG_COMP1(value) (AC_INTFLAG_COMP1_Msk & ((value) << AC_INTFLAG_COMP1_Pos)) -#define AC_INTFLAG_WIN0_Pos _U_(4) /**< (AC_INTFLAG) Window 0 Position */ -#define AC_INTFLAG_WIN0_Msk (_U_(0x1) << AC_INTFLAG_WIN0_Pos) /**< (AC_INTFLAG) Window 0 Mask */ -#define AC_INTFLAG_WIN0(value) (AC_INTFLAG_WIN0_Msk & ((value) << AC_INTFLAG_WIN0_Pos)) -#define AC_INTFLAG_Msk _U_(0x13) /**< (AC_INTFLAG) Register Mask */ - -#define AC_INTFLAG_COMP_Pos _U_(0) /**< (AC_INTFLAG Position) Comparator x */ -#define AC_INTFLAG_COMP_Msk (_U_(0x3) << AC_INTFLAG_COMP_Pos) /**< (AC_INTFLAG Mask) COMP */ -#define AC_INTFLAG_COMP(value) (AC_INTFLAG_COMP_Msk & ((value) << AC_INTFLAG_COMP_Pos)) -#define AC_INTFLAG_WIN_Pos _U_(4) /**< (AC_INTFLAG Position) Window x */ -#define AC_INTFLAG_WIN_Msk (_U_(0x1) << AC_INTFLAG_WIN_Pos) /**< (AC_INTFLAG Mask) WIN */ -#define AC_INTFLAG_WIN(value) (AC_INTFLAG_WIN_Msk & ((value) << AC_INTFLAG_WIN_Pos)) - -/* -------- AC_STATUSA : (AC Offset: 0x07) ( R/ 8) Status A -------- */ -#define AC_STATUSA_RESETVALUE _U_(0x00) /**< (AC_STATUSA) Status A Reset Value */ - -#define AC_STATUSA_STATE0_Pos _U_(0) /**< (AC_STATUSA) Comparator 0 Current State Position */ -#define AC_STATUSA_STATE0_Msk (_U_(0x1) << AC_STATUSA_STATE0_Pos) /**< (AC_STATUSA) Comparator 0 Current State Mask */ -#define AC_STATUSA_STATE0(value) (AC_STATUSA_STATE0_Msk & ((value) << AC_STATUSA_STATE0_Pos)) -#define AC_STATUSA_STATE1_Pos _U_(1) /**< (AC_STATUSA) Comparator 1 Current State Position */ -#define AC_STATUSA_STATE1_Msk (_U_(0x1) << AC_STATUSA_STATE1_Pos) /**< (AC_STATUSA) Comparator 1 Current State Mask */ -#define AC_STATUSA_STATE1(value) (AC_STATUSA_STATE1_Msk & ((value) << AC_STATUSA_STATE1_Pos)) -#define AC_STATUSA_WSTATE0_Pos _U_(4) /**< (AC_STATUSA) Window 0 Current State Position */ -#define AC_STATUSA_WSTATE0_Msk (_U_(0x3) << AC_STATUSA_WSTATE0_Pos) /**< (AC_STATUSA) Window 0 Current State Mask */ -#define AC_STATUSA_WSTATE0(value) (AC_STATUSA_WSTATE0_Msk & ((value) << AC_STATUSA_WSTATE0_Pos)) -#define AC_STATUSA_WSTATE0_ABOVE_Val _U_(0x0) /**< (AC_STATUSA) Signal is above window */ -#define AC_STATUSA_WSTATE0_INSIDE_Val _U_(0x1) /**< (AC_STATUSA) Signal is inside window */ -#define AC_STATUSA_WSTATE0_BELOW_Val _U_(0x2) /**< (AC_STATUSA) Signal is below window */ -#define AC_STATUSA_WSTATE0_ABOVE (AC_STATUSA_WSTATE0_ABOVE_Val << AC_STATUSA_WSTATE0_Pos) /**< (AC_STATUSA) Signal is above window Position */ -#define AC_STATUSA_WSTATE0_INSIDE (AC_STATUSA_WSTATE0_INSIDE_Val << AC_STATUSA_WSTATE0_Pos) /**< (AC_STATUSA) Signal is inside window Position */ -#define AC_STATUSA_WSTATE0_BELOW (AC_STATUSA_WSTATE0_BELOW_Val << AC_STATUSA_WSTATE0_Pos) /**< (AC_STATUSA) Signal is below window Position */ -#define AC_STATUSA_Msk _U_(0x33) /**< (AC_STATUSA) Register Mask */ - -#define AC_STATUSA_STATE_Pos _U_(0) /**< (AC_STATUSA Position) Comparator x Current State */ -#define AC_STATUSA_STATE_Msk (_U_(0x3) << AC_STATUSA_STATE_Pos) /**< (AC_STATUSA Mask) STATE */ -#define AC_STATUSA_STATE(value) (AC_STATUSA_STATE_Msk & ((value) << AC_STATUSA_STATE_Pos)) - -/* -------- AC_STATUSB : (AC Offset: 0x08) ( R/ 8) Status B -------- */ -#define AC_STATUSB_RESETVALUE _U_(0x00) /**< (AC_STATUSB) Status B Reset Value */ - -#define AC_STATUSB_READY0_Pos _U_(0) /**< (AC_STATUSB) Comparator 0 Ready Position */ -#define AC_STATUSB_READY0_Msk (_U_(0x1) << AC_STATUSB_READY0_Pos) /**< (AC_STATUSB) Comparator 0 Ready Mask */ -#define AC_STATUSB_READY0(value) (AC_STATUSB_READY0_Msk & ((value) << AC_STATUSB_READY0_Pos)) -#define AC_STATUSB_READY1_Pos _U_(1) /**< (AC_STATUSB) Comparator 1 Ready Position */ -#define AC_STATUSB_READY1_Msk (_U_(0x1) << AC_STATUSB_READY1_Pos) /**< (AC_STATUSB) Comparator 1 Ready Mask */ -#define AC_STATUSB_READY1(value) (AC_STATUSB_READY1_Msk & ((value) << AC_STATUSB_READY1_Pos)) -#define AC_STATUSB_Msk _U_(0x03) /**< (AC_STATUSB) Register Mask */ - -#define AC_STATUSB_READY_Pos _U_(0) /**< (AC_STATUSB Position) Comparator x Ready */ -#define AC_STATUSB_READY_Msk (_U_(0x3) << AC_STATUSB_READY_Pos) /**< (AC_STATUSB Mask) READY */ -#define AC_STATUSB_READY(value) (AC_STATUSB_READY_Msk & ((value) << AC_STATUSB_READY_Pos)) - -/* -------- AC_DBGCTRL : (AC Offset: 0x09) (R/W 8) Debug Control -------- */ -#define AC_DBGCTRL_RESETVALUE _U_(0x00) /**< (AC_DBGCTRL) Debug Control Reset Value */ - -#define AC_DBGCTRL_DBGRUN_Pos _U_(0) /**< (AC_DBGCTRL) Debug Run Position */ -#define AC_DBGCTRL_DBGRUN_Msk (_U_(0x1) << AC_DBGCTRL_DBGRUN_Pos) /**< (AC_DBGCTRL) Debug Run Mask */ -#define AC_DBGCTRL_DBGRUN(value) (AC_DBGCTRL_DBGRUN_Msk & ((value) << AC_DBGCTRL_DBGRUN_Pos)) -#define AC_DBGCTRL_Msk _U_(0x01) /**< (AC_DBGCTRL) Register Mask */ - - -/* -------- AC_WINCTRL : (AC Offset: 0x0A) (R/W 8) Window Control -------- */ -#define AC_WINCTRL_RESETVALUE _U_(0x00) /**< (AC_WINCTRL) Window Control Reset Value */ - -#define AC_WINCTRL_WEN0_Pos _U_(0) /**< (AC_WINCTRL) Window 0 Mode Enable Position */ -#define AC_WINCTRL_WEN0_Msk (_U_(0x1) << AC_WINCTRL_WEN0_Pos) /**< (AC_WINCTRL) Window 0 Mode Enable Mask */ -#define AC_WINCTRL_WEN0(value) (AC_WINCTRL_WEN0_Msk & ((value) << AC_WINCTRL_WEN0_Pos)) -#define AC_WINCTRL_WINTSEL0_Pos _U_(1) /**< (AC_WINCTRL) Window 0 Interrupt Selection Position */ -#define AC_WINCTRL_WINTSEL0_Msk (_U_(0x3) << AC_WINCTRL_WINTSEL0_Pos) /**< (AC_WINCTRL) Window 0 Interrupt Selection Mask */ -#define AC_WINCTRL_WINTSEL0(value) (AC_WINCTRL_WINTSEL0_Msk & ((value) << AC_WINCTRL_WINTSEL0_Pos)) -#define AC_WINCTRL_WINTSEL0_ABOVE_Val _U_(0x0) /**< (AC_WINCTRL) Interrupt on signal above window */ -#define AC_WINCTRL_WINTSEL0_INSIDE_Val _U_(0x1) /**< (AC_WINCTRL) Interrupt on signal inside window */ -#define AC_WINCTRL_WINTSEL0_BELOW_Val _U_(0x2) /**< (AC_WINCTRL) Interrupt on signal below window */ -#define AC_WINCTRL_WINTSEL0_OUTSIDE_Val _U_(0x3) /**< (AC_WINCTRL) Interrupt on signal outside window */ -#define AC_WINCTRL_WINTSEL0_ABOVE (AC_WINCTRL_WINTSEL0_ABOVE_Val << AC_WINCTRL_WINTSEL0_Pos) /**< (AC_WINCTRL) Interrupt on signal above window Position */ -#define AC_WINCTRL_WINTSEL0_INSIDE (AC_WINCTRL_WINTSEL0_INSIDE_Val << AC_WINCTRL_WINTSEL0_Pos) /**< (AC_WINCTRL) Interrupt on signal inside window Position */ -#define AC_WINCTRL_WINTSEL0_BELOW (AC_WINCTRL_WINTSEL0_BELOW_Val << AC_WINCTRL_WINTSEL0_Pos) /**< (AC_WINCTRL) Interrupt on signal below window Position */ -#define AC_WINCTRL_WINTSEL0_OUTSIDE (AC_WINCTRL_WINTSEL0_OUTSIDE_Val << AC_WINCTRL_WINTSEL0_Pos) /**< (AC_WINCTRL) Interrupt on signal outside window Position */ -#define AC_WINCTRL_Msk _U_(0x07) /**< (AC_WINCTRL) Register Mask */ - -#define AC_WINCTRL_WEN_Pos _U_(0) /**< (AC_WINCTRL Position) Window x Mode Enable */ -#define AC_WINCTRL_WEN_Msk (_U_(0x1) << AC_WINCTRL_WEN_Pos) /**< (AC_WINCTRL Mask) WEN */ -#define AC_WINCTRL_WEN(value) (AC_WINCTRL_WEN_Msk & ((value) << AC_WINCTRL_WEN_Pos)) - -/* -------- AC_SCALER : (AC Offset: 0x0C) (R/W 8) Scaler n -------- */ -#define AC_SCALER_RESETVALUE _U_(0x00) /**< (AC_SCALER) Scaler n Reset Value */ - -#define AC_SCALER_VALUE_Pos _U_(0) /**< (AC_SCALER) Scaler Value Position */ -#define AC_SCALER_VALUE_Msk (_U_(0x3F) << AC_SCALER_VALUE_Pos) /**< (AC_SCALER) Scaler Value Mask */ -#define AC_SCALER_VALUE(value) (AC_SCALER_VALUE_Msk & ((value) << AC_SCALER_VALUE_Pos)) -#define AC_SCALER_Msk _U_(0x3F) /**< (AC_SCALER) Register Mask */ - - -/* -------- AC_COMPCTRL : (AC Offset: 0x10) (R/W 32) Comparator Control n -------- */ -#define AC_COMPCTRL_RESETVALUE _U_(0x00) /**< (AC_COMPCTRL) Comparator Control n Reset Value */ - -#define AC_COMPCTRL_ENABLE_Pos _U_(1) /**< (AC_COMPCTRL) Enable Position */ -#define AC_COMPCTRL_ENABLE_Msk (_U_(0x1) << AC_COMPCTRL_ENABLE_Pos) /**< (AC_COMPCTRL) Enable Mask */ -#define AC_COMPCTRL_ENABLE(value) (AC_COMPCTRL_ENABLE_Msk & ((value) << AC_COMPCTRL_ENABLE_Pos)) -#define AC_COMPCTRL_SINGLE_Pos _U_(2) /**< (AC_COMPCTRL) Single-Shot Mode Position */ -#define AC_COMPCTRL_SINGLE_Msk (_U_(0x1) << AC_COMPCTRL_SINGLE_Pos) /**< (AC_COMPCTRL) Single-Shot Mode Mask */ -#define AC_COMPCTRL_SINGLE(value) (AC_COMPCTRL_SINGLE_Msk & ((value) << AC_COMPCTRL_SINGLE_Pos)) -#define AC_COMPCTRL_INTSEL_Pos _U_(3) /**< (AC_COMPCTRL) Interrupt Selection Position */ -#define AC_COMPCTRL_INTSEL_Msk (_U_(0x3) << AC_COMPCTRL_INTSEL_Pos) /**< (AC_COMPCTRL) Interrupt Selection Mask */ -#define AC_COMPCTRL_INTSEL(value) (AC_COMPCTRL_INTSEL_Msk & ((value) << AC_COMPCTRL_INTSEL_Pos)) -#define AC_COMPCTRL_INTSEL_TOGGLE_Val _U_(0x0) /**< (AC_COMPCTRL) Interrupt on comparator output toggle */ -#define AC_COMPCTRL_INTSEL_RISING_Val _U_(0x1) /**< (AC_COMPCTRL) Interrupt on comparator output rising */ -#define AC_COMPCTRL_INTSEL_FALLING_Val _U_(0x2) /**< (AC_COMPCTRL) Interrupt on comparator output falling */ -#define AC_COMPCTRL_INTSEL_EOC_Val _U_(0x3) /**< (AC_COMPCTRL) Interrupt on end of comparison (single-shot mode only) */ -#define AC_COMPCTRL_INTSEL_TOGGLE (AC_COMPCTRL_INTSEL_TOGGLE_Val << AC_COMPCTRL_INTSEL_Pos) /**< (AC_COMPCTRL) Interrupt on comparator output toggle Position */ -#define AC_COMPCTRL_INTSEL_RISING (AC_COMPCTRL_INTSEL_RISING_Val << AC_COMPCTRL_INTSEL_Pos) /**< (AC_COMPCTRL) Interrupt on comparator output rising Position */ -#define AC_COMPCTRL_INTSEL_FALLING (AC_COMPCTRL_INTSEL_FALLING_Val << AC_COMPCTRL_INTSEL_Pos) /**< (AC_COMPCTRL) Interrupt on comparator output falling Position */ -#define AC_COMPCTRL_INTSEL_EOC (AC_COMPCTRL_INTSEL_EOC_Val << AC_COMPCTRL_INTSEL_Pos) /**< (AC_COMPCTRL) Interrupt on end of comparison (single-shot mode only) Position */ -#define AC_COMPCTRL_RUNSTDBY_Pos _U_(6) /**< (AC_COMPCTRL) Run in Standby Position */ -#define AC_COMPCTRL_RUNSTDBY_Msk (_U_(0x1) << AC_COMPCTRL_RUNSTDBY_Pos) /**< (AC_COMPCTRL) Run in Standby Mask */ -#define AC_COMPCTRL_RUNSTDBY(value) (AC_COMPCTRL_RUNSTDBY_Msk & ((value) << AC_COMPCTRL_RUNSTDBY_Pos)) -#define AC_COMPCTRL_MUXNEG_Pos _U_(8) /**< (AC_COMPCTRL) Negative Input Mux Selection Position */ -#define AC_COMPCTRL_MUXNEG_Msk (_U_(0x7) << AC_COMPCTRL_MUXNEG_Pos) /**< (AC_COMPCTRL) Negative Input Mux Selection Mask */ -#define AC_COMPCTRL_MUXNEG(value) (AC_COMPCTRL_MUXNEG_Msk & ((value) << AC_COMPCTRL_MUXNEG_Pos)) -#define AC_COMPCTRL_MUXNEG_PIN0_Val _U_(0x0) /**< (AC_COMPCTRL) I/O pin 0 */ -#define AC_COMPCTRL_MUXNEG_PIN1_Val _U_(0x1) /**< (AC_COMPCTRL) I/O pin 1 */ -#define AC_COMPCTRL_MUXNEG_PIN2_Val _U_(0x2) /**< (AC_COMPCTRL) I/O pin 2 */ -#define AC_COMPCTRL_MUXNEG_PIN3_Val _U_(0x3) /**< (AC_COMPCTRL) I/O pin 3 */ -#define AC_COMPCTRL_MUXNEG_GND_Val _U_(0x4) /**< (AC_COMPCTRL) Ground */ -#define AC_COMPCTRL_MUXNEG_VSCALE_Val _U_(0x5) /**< (AC_COMPCTRL) VDD scaler */ -#define AC_COMPCTRL_MUXNEG_BANDGAP_Val _U_(0x6) /**< (AC_COMPCTRL) Internal bandgap voltage */ -#define AC_COMPCTRL_MUXNEG_DAC_Val _U_(0x7) /**< (AC_COMPCTRL) DAC output */ -#define AC_COMPCTRL_MUXNEG_PIN0 (AC_COMPCTRL_MUXNEG_PIN0_Val << AC_COMPCTRL_MUXNEG_Pos) /**< (AC_COMPCTRL) I/O pin 0 Position */ -#define AC_COMPCTRL_MUXNEG_PIN1 (AC_COMPCTRL_MUXNEG_PIN1_Val << AC_COMPCTRL_MUXNEG_Pos) /**< (AC_COMPCTRL) I/O pin 1 Position */ -#define AC_COMPCTRL_MUXNEG_PIN2 (AC_COMPCTRL_MUXNEG_PIN2_Val << AC_COMPCTRL_MUXNEG_Pos) /**< (AC_COMPCTRL) I/O pin 2 Position */ -#define AC_COMPCTRL_MUXNEG_PIN3 (AC_COMPCTRL_MUXNEG_PIN3_Val << AC_COMPCTRL_MUXNEG_Pos) /**< (AC_COMPCTRL) I/O pin 3 Position */ -#define AC_COMPCTRL_MUXNEG_GND (AC_COMPCTRL_MUXNEG_GND_Val << AC_COMPCTRL_MUXNEG_Pos) /**< (AC_COMPCTRL) Ground Position */ -#define AC_COMPCTRL_MUXNEG_VSCALE (AC_COMPCTRL_MUXNEG_VSCALE_Val << AC_COMPCTRL_MUXNEG_Pos) /**< (AC_COMPCTRL) VDD scaler Position */ -#define AC_COMPCTRL_MUXNEG_BANDGAP (AC_COMPCTRL_MUXNEG_BANDGAP_Val << AC_COMPCTRL_MUXNEG_Pos) /**< (AC_COMPCTRL) Internal bandgap voltage Position */ -#define AC_COMPCTRL_MUXNEG_DAC (AC_COMPCTRL_MUXNEG_DAC_Val << AC_COMPCTRL_MUXNEG_Pos) /**< (AC_COMPCTRL) DAC output Position */ -#define AC_COMPCTRL_MUXPOS_Pos _U_(12) /**< (AC_COMPCTRL) Positive Input Mux Selection Position */ -#define AC_COMPCTRL_MUXPOS_Msk (_U_(0x7) << AC_COMPCTRL_MUXPOS_Pos) /**< (AC_COMPCTRL) Positive Input Mux Selection Mask */ -#define AC_COMPCTRL_MUXPOS(value) (AC_COMPCTRL_MUXPOS_Msk & ((value) << AC_COMPCTRL_MUXPOS_Pos)) -#define AC_COMPCTRL_MUXPOS_PIN0_Val _U_(0x0) /**< (AC_COMPCTRL) I/O pin 0 */ -#define AC_COMPCTRL_MUXPOS_PIN1_Val _U_(0x1) /**< (AC_COMPCTRL) I/O pin 1 */ -#define AC_COMPCTRL_MUXPOS_PIN2_Val _U_(0x2) /**< (AC_COMPCTRL) I/O pin 2 */ -#define AC_COMPCTRL_MUXPOS_PIN3_Val _U_(0x3) /**< (AC_COMPCTRL) I/O pin 3 */ -#define AC_COMPCTRL_MUXPOS_VSCALE_Val _U_(0x4) /**< (AC_COMPCTRL) VDD Scaler */ -#define AC_COMPCTRL_MUXPOS_PIN0 (AC_COMPCTRL_MUXPOS_PIN0_Val << AC_COMPCTRL_MUXPOS_Pos) /**< (AC_COMPCTRL) I/O pin 0 Position */ -#define AC_COMPCTRL_MUXPOS_PIN1 (AC_COMPCTRL_MUXPOS_PIN1_Val << AC_COMPCTRL_MUXPOS_Pos) /**< (AC_COMPCTRL) I/O pin 1 Position */ -#define AC_COMPCTRL_MUXPOS_PIN2 (AC_COMPCTRL_MUXPOS_PIN2_Val << AC_COMPCTRL_MUXPOS_Pos) /**< (AC_COMPCTRL) I/O pin 2 Position */ -#define AC_COMPCTRL_MUXPOS_PIN3 (AC_COMPCTRL_MUXPOS_PIN3_Val << AC_COMPCTRL_MUXPOS_Pos) /**< (AC_COMPCTRL) I/O pin 3 Position */ -#define AC_COMPCTRL_MUXPOS_VSCALE (AC_COMPCTRL_MUXPOS_VSCALE_Val << AC_COMPCTRL_MUXPOS_Pos) /**< (AC_COMPCTRL) VDD Scaler Position */ -#define AC_COMPCTRL_SWAP_Pos _U_(15) /**< (AC_COMPCTRL) Swap Inputs and Invert Position */ -#define AC_COMPCTRL_SWAP_Msk (_U_(0x1) << AC_COMPCTRL_SWAP_Pos) /**< (AC_COMPCTRL) Swap Inputs and Invert Mask */ -#define AC_COMPCTRL_SWAP(value) (AC_COMPCTRL_SWAP_Msk & ((value) << AC_COMPCTRL_SWAP_Pos)) -#define AC_COMPCTRL_SPEED_Pos _U_(16) /**< (AC_COMPCTRL) Speed Selection Position */ -#define AC_COMPCTRL_SPEED_Msk (_U_(0x3) << AC_COMPCTRL_SPEED_Pos) /**< (AC_COMPCTRL) Speed Selection Mask */ -#define AC_COMPCTRL_SPEED(value) (AC_COMPCTRL_SPEED_Msk & ((value) << AC_COMPCTRL_SPEED_Pos)) -#define AC_COMPCTRL_SPEED_HIGH_Val _U_(0x3) /**< (AC_COMPCTRL) High speed */ -#define AC_COMPCTRL_SPEED_HIGH (AC_COMPCTRL_SPEED_HIGH_Val << AC_COMPCTRL_SPEED_Pos) /**< (AC_COMPCTRL) High speed Position */ -#define AC_COMPCTRL_HYSTEN_Pos _U_(19) /**< (AC_COMPCTRL) Hysteresis Enable Position */ -#define AC_COMPCTRL_HYSTEN_Msk (_U_(0x1) << AC_COMPCTRL_HYSTEN_Pos) /**< (AC_COMPCTRL) Hysteresis Enable Mask */ -#define AC_COMPCTRL_HYSTEN(value) (AC_COMPCTRL_HYSTEN_Msk & ((value) << AC_COMPCTRL_HYSTEN_Pos)) -#define AC_COMPCTRL_HYST_Pos _U_(20) /**< (AC_COMPCTRL) Hysteresis Level Position */ -#define AC_COMPCTRL_HYST_Msk (_U_(0x3) << AC_COMPCTRL_HYST_Pos) /**< (AC_COMPCTRL) Hysteresis Level Mask */ -#define AC_COMPCTRL_HYST(value) (AC_COMPCTRL_HYST_Msk & ((value) << AC_COMPCTRL_HYST_Pos)) -#define AC_COMPCTRL_HYST_HYST50_Val _U_(0x0) /**< (AC_COMPCTRL) 50mV */ -#define AC_COMPCTRL_HYST_HYST100_Val _U_(0x1) /**< (AC_COMPCTRL) 100mV */ -#define AC_COMPCTRL_HYST_HYST150_Val _U_(0x2) /**< (AC_COMPCTRL) 150mV */ -#define AC_COMPCTRL_HYST_HYST50 (AC_COMPCTRL_HYST_HYST50_Val << AC_COMPCTRL_HYST_Pos) /**< (AC_COMPCTRL) 50mV Position */ -#define AC_COMPCTRL_HYST_HYST100 (AC_COMPCTRL_HYST_HYST100_Val << AC_COMPCTRL_HYST_Pos) /**< (AC_COMPCTRL) 100mV Position */ -#define AC_COMPCTRL_HYST_HYST150 (AC_COMPCTRL_HYST_HYST150_Val << AC_COMPCTRL_HYST_Pos) /**< (AC_COMPCTRL) 150mV Position */ -#define AC_COMPCTRL_FLEN_Pos _U_(24) /**< (AC_COMPCTRL) Filter Length Position */ -#define AC_COMPCTRL_FLEN_Msk (_U_(0x7) << AC_COMPCTRL_FLEN_Pos) /**< (AC_COMPCTRL) Filter Length Mask */ -#define AC_COMPCTRL_FLEN(value) (AC_COMPCTRL_FLEN_Msk & ((value) << AC_COMPCTRL_FLEN_Pos)) -#define AC_COMPCTRL_FLEN_OFF_Val _U_(0x0) /**< (AC_COMPCTRL) No filtering */ -#define AC_COMPCTRL_FLEN_MAJ3_Val _U_(0x1) /**< (AC_COMPCTRL) 3-bit majority function (2 of 3) */ -#define AC_COMPCTRL_FLEN_MAJ5_Val _U_(0x2) /**< (AC_COMPCTRL) 5-bit majority function (3 of 5) */ -#define AC_COMPCTRL_FLEN_OFF (AC_COMPCTRL_FLEN_OFF_Val << AC_COMPCTRL_FLEN_Pos) /**< (AC_COMPCTRL) No filtering Position */ -#define AC_COMPCTRL_FLEN_MAJ3 (AC_COMPCTRL_FLEN_MAJ3_Val << AC_COMPCTRL_FLEN_Pos) /**< (AC_COMPCTRL) 3-bit majority function (2 of 3) Position */ -#define AC_COMPCTRL_FLEN_MAJ5 (AC_COMPCTRL_FLEN_MAJ5_Val << AC_COMPCTRL_FLEN_Pos) /**< (AC_COMPCTRL) 5-bit majority function (3 of 5) Position */ -#define AC_COMPCTRL_OUT_Pos _U_(28) /**< (AC_COMPCTRL) Output Position */ -#define AC_COMPCTRL_OUT_Msk (_U_(0x3) << AC_COMPCTRL_OUT_Pos) /**< (AC_COMPCTRL) Output Mask */ -#define AC_COMPCTRL_OUT(value) (AC_COMPCTRL_OUT_Msk & ((value) << AC_COMPCTRL_OUT_Pos)) -#define AC_COMPCTRL_OUT_OFF_Val _U_(0x0) /**< (AC_COMPCTRL) The output of COMPn is not routed to the COMPn I/O port */ -#define AC_COMPCTRL_OUT_ASYNC_Val _U_(0x1) /**< (AC_COMPCTRL) The asynchronous output of COMPn is routed to the COMPn I/O port */ -#define AC_COMPCTRL_OUT_SYNC_Val _U_(0x2) /**< (AC_COMPCTRL) The synchronous output (including filtering) of COMPn is routed to the COMPn I/O port */ -#define AC_COMPCTRL_OUT_OFF (AC_COMPCTRL_OUT_OFF_Val << AC_COMPCTRL_OUT_Pos) /**< (AC_COMPCTRL) The output of COMPn is not routed to the COMPn I/O port Position */ -#define AC_COMPCTRL_OUT_ASYNC (AC_COMPCTRL_OUT_ASYNC_Val << AC_COMPCTRL_OUT_Pos) /**< (AC_COMPCTRL) The asynchronous output of COMPn is routed to the COMPn I/O port Position */ -#define AC_COMPCTRL_OUT_SYNC (AC_COMPCTRL_OUT_SYNC_Val << AC_COMPCTRL_OUT_Pos) /**< (AC_COMPCTRL) The synchronous output (including filtering) of COMPn is routed to the COMPn I/O port Position */ -#define AC_COMPCTRL_Msk _U_(0x373BF75E) /**< (AC_COMPCTRL) Register Mask */ - - -/* -------- AC_SYNCBUSY : (AC Offset: 0x20) ( R/ 32) Synchronization Busy -------- */ -#define AC_SYNCBUSY_RESETVALUE _U_(0x00) /**< (AC_SYNCBUSY) Synchronization Busy Reset Value */ - -#define AC_SYNCBUSY_SWRST_Pos _U_(0) /**< (AC_SYNCBUSY) Software Reset Synchronization Busy Position */ -#define AC_SYNCBUSY_SWRST_Msk (_U_(0x1) << AC_SYNCBUSY_SWRST_Pos) /**< (AC_SYNCBUSY) Software Reset Synchronization Busy Mask */ -#define AC_SYNCBUSY_SWRST(value) (AC_SYNCBUSY_SWRST_Msk & ((value) << AC_SYNCBUSY_SWRST_Pos)) -#define AC_SYNCBUSY_ENABLE_Pos _U_(1) /**< (AC_SYNCBUSY) Enable Synchronization Busy Position */ -#define AC_SYNCBUSY_ENABLE_Msk (_U_(0x1) << AC_SYNCBUSY_ENABLE_Pos) /**< (AC_SYNCBUSY) Enable Synchronization Busy Mask */ -#define AC_SYNCBUSY_ENABLE(value) (AC_SYNCBUSY_ENABLE_Msk & ((value) << AC_SYNCBUSY_ENABLE_Pos)) -#define AC_SYNCBUSY_WINCTRL_Pos _U_(2) /**< (AC_SYNCBUSY) WINCTRL Synchronization Busy Position */ -#define AC_SYNCBUSY_WINCTRL_Msk (_U_(0x1) << AC_SYNCBUSY_WINCTRL_Pos) /**< (AC_SYNCBUSY) WINCTRL Synchronization Busy Mask */ -#define AC_SYNCBUSY_WINCTRL(value) (AC_SYNCBUSY_WINCTRL_Msk & ((value) << AC_SYNCBUSY_WINCTRL_Pos)) -#define AC_SYNCBUSY_COMPCTRL0_Pos _U_(3) /**< (AC_SYNCBUSY) COMPCTRL 0 Synchronization Busy Position */ -#define AC_SYNCBUSY_COMPCTRL0_Msk (_U_(0x1) << AC_SYNCBUSY_COMPCTRL0_Pos) /**< (AC_SYNCBUSY) COMPCTRL 0 Synchronization Busy Mask */ -#define AC_SYNCBUSY_COMPCTRL0(value) (AC_SYNCBUSY_COMPCTRL0_Msk & ((value) << AC_SYNCBUSY_COMPCTRL0_Pos)) -#define AC_SYNCBUSY_COMPCTRL1_Pos _U_(4) /**< (AC_SYNCBUSY) COMPCTRL 1 Synchronization Busy Position */ -#define AC_SYNCBUSY_COMPCTRL1_Msk (_U_(0x1) << AC_SYNCBUSY_COMPCTRL1_Pos) /**< (AC_SYNCBUSY) COMPCTRL 1 Synchronization Busy Mask */ -#define AC_SYNCBUSY_COMPCTRL1(value) (AC_SYNCBUSY_COMPCTRL1_Msk & ((value) << AC_SYNCBUSY_COMPCTRL1_Pos)) -#define AC_SYNCBUSY_Msk _U_(0x0000001F) /**< (AC_SYNCBUSY) Register Mask */ - -#define AC_SYNCBUSY_COMPCTRL_Pos _U_(3) /**< (AC_SYNCBUSY Position) COMPCTRL x Synchronization Busy */ -#define AC_SYNCBUSY_COMPCTRL_Msk (_U_(0x3) << AC_SYNCBUSY_COMPCTRL_Pos) /**< (AC_SYNCBUSY Mask) COMPCTRL */ -#define AC_SYNCBUSY_COMPCTRL(value) (AC_SYNCBUSY_COMPCTRL_Msk & ((value) << AC_SYNCBUSY_COMPCTRL_Pos)) - -/* -------- AC_CALIB : (AC Offset: 0x24) (R/W 16) Calibration -------- */ -#define AC_CALIB_RESETVALUE _U_(0x101) /**< (AC_CALIB) Calibration Reset Value */ - -#define AC_CALIB_BIAS0_Pos _U_(0) /**< (AC_CALIB) COMP0/1 Bias Scaling Position */ -#define AC_CALIB_BIAS0_Msk (_U_(0x3) << AC_CALIB_BIAS0_Pos) /**< (AC_CALIB) COMP0/1 Bias Scaling Mask */ -#define AC_CALIB_BIAS0(value) (AC_CALIB_BIAS0_Msk & ((value) << AC_CALIB_BIAS0_Pos)) -#define AC_CALIB_Msk _U_(0x0003) /**< (AC_CALIB) Register Mask */ - - -/** \brief AC register offsets definitions */ -#define AC_CTRLA_REG_OFST (0x00) /**< (AC_CTRLA) Control A Offset */ -#define AC_CTRLB_REG_OFST (0x01) /**< (AC_CTRLB) Control B Offset */ -#define AC_EVCTRL_REG_OFST (0x02) /**< (AC_EVCTRL) Event Control Offset */ -#define AC_INTENCLR_REG_OFST (0x04) /**< (AC_INTENCLR) Interrupt Enable Clear Offset */ -#define AC_INTENSET_REG_OFST (0x05) /**< (AC_INTENSET) Interrupt Enable Set Offset */ -#define AC_INTFLAG_REG_OFST (0x06) /**< (AC_INTFLAG) Interrupt Flag Status and Clear Offset */ -#define AC_STATUSA_REG_OFST (0x07) /**< (AC_STATUSA) Status A Offset */ -#define AC_STATUSB_REG_OFST (0x08) /**< (AC_STATUSB) Status B Offset */ -#define AC_DBGCTRL_REG_OFST (0x09) /**< (AC_DBGCTRL) Debug Control Offset */ -#define AC_WINCTRL_REG_OFST (0x0A) /**< (AC_WINCTRL) Window Control Offset */ -#define AC_SCALER_REG_OFST (0x0C) /**< (AC_SCALER) Scaler n Offset */ -#define AC_COMPCTRL_REG_OFST (0x10) /**< (AC_COMPCTRL) Comparator Control n Offset */ -#define AC_SYNCBUSY_REG_OFST (0x20) /**< (AC_SYNCBUSY) Synchronization Busy Offset */ -#define AC_CALIB_REG_OFST (0x24) /**< (AC_CALIB) Calibration Offset */ - -#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) -/** \brief AC register API structure */ -typedef struct -{ /* Analog Comparators */ - __IO uint8_t AC_CTRLA; /**< Offset: 0x00 (R/W 8) Control A */ - __O uint8_t AC_CTRLB; /**< Offset: 0x01 ( /W 8) Control B */ - __IO uint16_t AC_EVCTRL; /**< Offset: 0x02 (R/W 16) Event Control */ - __IO uint8_t AC_INTENCLR; /**< Offset: 0x04 (R/W 8) Interrupt Enable Clear */ - __IO uint8_t AC_INTENSET; /**< Offset: 0x05 (R/W 8) Interrupt Enable Set */ - __IO uint8_t AC_INTFLAG; /**< Offset: 0x06 (R/W 8) Interrupt Flag Status and Clear */ - __I uint8_t AC_STATUSA; /**< Offset: 0x07 (R/ 8) Status A */ - __I uint8_t AC_STATUSB; /**< Offset: 0x08 (R/ 8) Status B */ - __IO uint8_t AC_DBGCTRL; /**< Offset: 0x09 (R/W 8) Debug Control */ - __IO uint8_t AC_WINCTRL; /**< Offset: 0x0A (R/W 8) Window Control */ - __I uint8_t Reserved1[0x01]; - __IO uint8_t AC_SCALER[2]; /**< Offset: 0x0C (R/W 8) Scaler n */ - __I uint8_t Reserved2[0x02]; - __IO uint32_t AC_COMPCTRL[2]; /**< Offset: 0x10 (R/W 32) Comparator Control n */ - __I uint8_t Reserved3[0x08]; - __I uint32_t AC_SYNCBUSY; /**< Offset: 0x20 (R/ 32) Synchronization Busy */ - __IO uint16_t AC_CALIB; /**< Offset: 0x24 (R/W 16) Calibration */ -} ac_registers_t; - - -#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ -#endif /* _SAME54_AC_COMPONENT_H_ */ +/** + * \file + * + * \brief Component description for AC + * + * Copyright (c) 2019 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAME54_AC_COMPONENT_ +#define _SAME54_AC_COMPONENT_ + +/* ========================================================================== */ +/** SOFTWARE API DEFINITION FOR AC */ +/* ========================================================================== */ +/** \addtogroup SAME54_AC Analog Comparators */ +/*@{*/ + +#define AC_U2501 +#define REV_AC 0x100 + +/* -------- AC_CTRLA : (AC Offset: 0x00) (R/W 8) Control A -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t SWRST:1; /*!< bit: 0 Software Reset */ + uint8_t ENABLE:1; /*!< bit: 1 Enable */ + uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} AC_CTRLA_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AC_CTRLA_OFFSET 0x00 /**< \brief (AC_CTRLA offset) Control A */ +#define AC_CTRLA_RESETVALUE _U_(0x00) /**< \brief (AC_CTRLA reset_value) Control A */ + +#define AC_CTRLA_SWRST_Pos 0 /**< \brief (AC_CTRLA) Software Reset */ +#define AC_CTRLA_SWRST (_U_(0x1) << AC_CTRLA_SWRST_Pos) +#define AC_CTRLA_ENABLE_Pos 1 /**< \brief (AC_CTRLA) Enable */ +#define AC_CTRLA_ENABLE (_U_(0x1) << AC_CTRLA_ENABLE_Pos) +#define AC_CTRLA_MASK _U_(0x03) /**< \brief (AC_CTRLA) MASK Register */ + +/* -------- AC_CTRLB : (AC Offset: 0x01) ( /W 8) Control B -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t START0:1; /*!< bit: 0 Comparator 0 Start Comparison */ + uint8_t START1:1; /*!< bit: 1 Comparator 1 Start Comparison */ + uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint8_t START:2; /*!< bit: 0.. 1 Comparator x Start Comparison */ + uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } vec; /*!< Structure used for vec access */ + uint8_t reg; /*!< Type used for register access */ +} AC_CTRLB_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AC_CTRLB_OFFSET 0x01 /**< \brief (AC_CTRLB offset) Control B */ +#define AC_CTRLB_RESETVALUE _U_(0x00) /**< \brief (AC_CTRLB reset_value) Control B */ + +#define AC_CTRLB_START0_Pos 0 /**< \brief (AC_CTRLB) Comparator 0 Start Comparison */ +#define AC_CTRLB_START0 (_U_(1) << AC_CTRLB_START0_Pos) +#define AC_CTRLB_START1_Pos 1 /**< \brief (AC_CTRLB) Comparator 1 Start Comparison */ +#define AC_CTRLB_START1 (_U_(1) << AC_CTRLB_START1_Pos) +#define AC_CTRLB_START_Pos 0 /**< \brief (AC_CTRLB) Comparator x Start Comparison */ +#define AC_CTRLB_START_Msk (_U_(0x3) << AC_CTRLB_START_Pos) +#define AC_CTRLB_START(value) (AC_CTRLB_START_Msk & ((value) << AC_CTRLB_START_Pos)) +#define AC_CTRLB_MASK _U_(0x03) /**< \brief (AC_CTRLB) MASK Register */ + +/* -------- AC_EVCTRL : (AC Offset: 0x02) (R/W 16) Event Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t COMPEO0:1; /*!< bit: 0 Comparator 0 Event Output Enable */ + uint16_t COMPEO1:1; /*!< bit: 1 Comparator 1 Event Output Enable */ + uint16_t :2; /*!< bit: 2.. 3 Reserved */ + uint16_t WINEO0:1; /*!< bit: 4 Window 0 Event Output Enable */ + uint16_t :3; /*!< bit: 5.. 7 Reserved */ + uint16_t COMPEI0:1; /*!< bit: 8 Comparator 0 Event Input Enable */ + uint16_t COMPEI1:1; /*!< bit: 9 Comparator 1 Event Input Enable */ + uint16_t :2; /*!< bit: 10..11 Reserved */ + uint16_t INVEI0:1; /*!< bit: 12 Comparator 0 Input Event Invert Enable */ + uint16_t INVEI1:1; /*!< bit: 13 Comparator 1 Input Event Invert Enable */ + uint16_t :2; /*!< bit: 14..15 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint16_t COMPEO:2; /*!< bit: 0.. 1 Comparator x Event Output Enable */ + uint16_t :2; /*!< bit: 2.. 3 Reserved */ + uint16_t WINEO:1; /*!< bit: 4 Window x Event Output Enable */ + uint16_t :3; /*!< bit: 5.. 7 Reserved */ + uint16_t COMPEI:2; /*!< bit: 8.. 9 Comparator x Event Input Enable */ + uint16_t :2; /*!< bit: 10..11 Reserved */ + uint16_t INVEI:2; /*!< bit: 12..13 Comparator x Input Event Invert Enable */ + uint16_t :2; /*!< bit: 14..15 Reserved */ + } vec; /*!< Structure used for vec access */ + uint16_t reg; /*!< Type used for register access */ +} AC_EVCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AC_EVCTRL_OFFSET 0x02 /**< \brief (AC_EVCTRL offset) Event Control */ +#define AC_EVCTRL_RESETVALUE _U_(0x0000) /**< \brief (AC_EVCTRL reset_value) Event Control */ + +#define AC_EVCTRL_COMPEO0_Pos 0 /**< \brief (AC_EVCTRL) Comparator 0 Event Output Enable */ +#define AC_EVCTRL_COMPEO0 (_U_(1) << AC_EVCTRL_COMPEO0_Pos) +#define AC_EVCTRL_COMPEO1_Pos 1 /**< \brief (AC_EVCTRL) Comparator 1 Event Output Enable */ +#define AC_EVCTRL_COMPEO1 (_U_(1) << AC_EVCTRL_COMPEO1_Pos) +#define AC_EVCTRL_COMPEO_Pos 0 /**< \brief (AC_EVCTRL) Comparator x Event Output Enable */ +#define AC_EVCTRL_COMPEO_Msk (_U_(0x3) << AC_EVCTRL_COMPEO_Pos) +#define AC_EVCTRL_COMPEO(value) (AC_EVCTRL_COMPEO_Msk & ((value) << AC_EVCTRL_COMPEO_Pos)) +#define AC_EVCTRL_WINEO0_Pos 4 /**< \brief (AC_EVCTRL) Window 0 Event Output Enable */ +#define AC_EVCTRL_WINEO0 (_U_(1) << AC_EVCTRL_WINEO0_Pos) +#define AC_EVCTRL_WINEO_Pos 4 /**< \brief (AC_EVCTRL) Window x Event Output Enable */ +#define AC_EVCTRL_WINEO_Msk (_U_(0x1) << AC_EVCTRL_WINEO_Pos) +#define AC_EVCTRL_WINEO(value) (AC_EVCTRL_WINEO_Msk & ((value) << AC_EVCTRL_WINEO_Pos)) +#define AC_EVCTRL_COMPEI0_Pos 8 /**< \brief (AC_EVCTRL) Comparator 0 Event Input Enable */ +#define AC_EVCTRL_COMPEI0 (_U_(1) << AC_EVCTRL_COMPEI0_Pos) +#define AC_EVCTRL_COMPEI1_Pos 9 /**< \brief (AC_EVCTRL) Comparator 1 Event Input Enable */ +#define AC_EVCTRL_COMPEI1 (_U_(1) << AC_EVCTRL_COMPEI1_Pos) +#define AC_EVCTRL_COMPEI_Pos 8 /**< \brief (AC_EVCTRL) Comparator x Event Input Enable */ +#define AC_EVCTRL_COMPEI_Msk (_U_(0x3) << AC_EVCTRL_COMPEI_Pos) +#define AC_EVCTRL_COMPEI(value) (AC_EVCTRL_COMPEI_Msk & ((value) << AC_EVCTRL_COMPEI_Pos)) +#define AC_EVCTRL_INVEI0_Pos 12 /**< \brief (AC_EVCTRL) Comparator 0 Input Event Invert Enable */ +#define AC_EVCTRL_INVEI0 (_U_(1) << AC_EVCTRL_INVEI0_Pos) +#define AC_EVCTRL_INVEI1_Pos 13 /**< \brief (AC_EVCTRL) Comparator 1 Input Event Invert Enable */ +#define AC_EVCTRL_INVEI1 (_U_(1) << AC_EVCTRL_INVEI1_Pos) +#define AC_EVCTRL_INVEI_Pos 12 /**< \brief (AC_EVCTRL) Comparator x Input Event Invert Enable */ +#define AC_EVCTRL_INVEI_Msk (_U_(0x3) << AC_EVCTRL_INVEI_Pos) +#define AC_EVCTRL_INVEI(value) (AC_EVCTRL_INVEI_Msk & ((value) << AC_EVCTRL_INVEI_Pos)) +#define AC_EVCTRL_MASK _U_(0x3313) /**< \brief (AC_EVCTRL) MASK Register */ + +/* -------- AC_INTENCLR : (AC Offset: 0x04) (R/W 8) Interrupt Enable Clear -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t COMP0:1; /*!< bit: 0 Comparator 0 Interrupt Enable */ + uint8_t COMP1:1; /*!< bit: 1 Comparator 1 Interrupt Enable */ + uint8_t :2; /*!< bit: 2.. 3 Reserved */ + uint8_t WIN0:1; /*!< bit: 4 Window 0 Interrupt Enable */ + uint8_t :3; /*!< bit: 5.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint8_t COMP:2; /*!< bit: 0.. 1 Comparator x Interrupt Enable */ + uint8_t :2; /*!< bit: 2.. 3 Reserved */ + uint8_t WIN:1; /*!< bit: 4 Window x Interrupt Enable */ + uint8_t :3; /*!< bit: 5.. 7 Reserved */ + } vec; /*!< Structure used for vec access */ + uint8_t reg; /*!< Type used for register access */ +} AC_INTENCLR_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AC_INTENCLR_OFFSET 0x04 /**< \brief (AC_INTENCLR offset) Interrupt Enable Clear */ +#define AC_INTENCLR_RESETVALUE _U_(0x00) /**< \brief (AC_INTENCLR reset_value) Interrupt Enable Clear */ + +#define AC_INTENCLR_COMP0_Pos 0 /**< \brief (AC_INTENCLR) Comparator 0 Interrupt Enable */ +#define AC_INTENCLR_COMP0 (_U_(1) << AC_INTENCLR_COMP0_Pos) +#define AC_INTENCLR_COMP1_Pos 1 /**< \brief (AC_INTENCLR) Comparator 1 Interrupt Enable */ +#define AC_INTENCLR_COMP1 (_U_(1) << AC_INTENCLR_COMP1_Pos) +#define AC_INTENCLR_COMP_Pos 0 /**< \brief (AC_INTENCLR) Comparator x Interrupt Enable */ +#define AC_INTENCLR_COMP_Msk (_U_(0x3) << AC_INTENCLR_COMP_Pos) +#define AC_INTENCLR_COMP(value) (AC_INTENCLR_COMP_Msk & ((value) << AC_INTENCLR_COMP_Pos)) +#define AC_INTENCLR_WIN0_Pos 4 /**< \brief (AC_INTENCLR) Window 0 Interrupt Enable */ +#define AC_INTENCLR_WIN0 (_U_(1) << AC_INTENCLR_WIN0_Pos) +#define AC_INTENCLR_WIN_Pos 4 /**< \brief (AC_INTENCLR) Window x Interrupt Enable */ +#define AC_INTENCLR_WIN_Msk (_U_(0x1) << AC_INTENCLR_WIN_Pos) +#define AC_INTENCLR_WIN(value) (AC_INTENCLR_WIN_Msk & ((value) << AC_INTENCLR_WIN_Pos)) +#define AC_INTENCLR_MASK _U_(0x13) /**< \brief (AC_INTENCLR) MASK Register */ + +/* -------- AC_INTENSET : (AC Offset: 0x05) (R/W 8) Interrupt Enable Set -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t COMP0:1; /*!< bit: 0 Comparator 0 Interrupt Enable */ + uint8_t COMP1:1; /*!< bit: 1 Comparator 1 Interrupt Enable */ + uint8_t :2; /*!< bit: 2.. 3 Reserved */ + uint8_t WIN0:1; /*!< bit: 4 Window 0 Interrupt Enable */ + uint8_t :3; /*!< bit: 5.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint8_t COMP:2; /*!< bit: 0.. 1 Comparator x Interrupt Enable */ + uint8_t :2; /*!< bit: 2.. 3 Reserved */ + uint8_t WIN:1; /*!< bit: 4 Window x Interrupt Enable */ + uint8_t :3; /*!< bit: 5.. 7 Reserved */ + } vec; /*!< Structure used for vec access */ + uint8_t reg; /*!< Type used for register access */ +} AC_INTENSET_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AC_INTENSET_OFFSET 0x05 /**< \brief (AC_INTENSET offset) Interrupt Enable Set */ +#define AC_INTENSET_RESETVALUE _U_(0x00) /**< \brief (AC_INTENSET reset_value) Interrupt Enable Set */ + +#define AC_INTENSET_COMP0_Pos 0 /**< \brief (AC_INTENSET) Comparator 0 Interrupt Enable */ +#define AC_INTENSET_COMP0 (_U_(1) << AC_INTENSET_COMP0_Pos) +#define AC_INTENSET_COMP1_Pos 1 /**< \brief (AC_INTENSET) Comparator 1 Interrupt Enable */ +#define AC_INTENSET_COMP1 (_U_(1) << AC_INTENSET_COMP1_Pos) +#define AC_INTENSET_COMP_Pos 0 /**< \brief (AC_INTENSET) Comparator x Interrupt Enable */ +#define AC_INTENSET_COMP_Msk (_U_(0x3) << AC_INTENSET_COMP_Pos) +#define AC_INTENSET_COMP(value) (AC_INTENSET_COMP_Msk & ((value) << AC_INTENSET_COMP_Pos)) +#define AC_INTENSET_WIN0_Pos 4 /**< \brief (AC_INTENSET) Window 0 Interrupt Enable */ +#define AC_INTENSET_WIN0 (_U_(1) << AC_INTENSET_WIN0_Pos) +#define AC_INTENSET_WIN_Pos 4 /**< \brief (AC_INTENSET) Window x Interrupt Enable */ +#define AC_INTENSET_WIN_Msk (_U_(0x1) << AC_INTENSET_WIN_Pos) +#define AC_INTENSET_WIN(value) (AC_INTENSET_WIN_Msk & ((value) << AC_INTENSET_WIN_Pos)) +#define AC_INTENSET_MASK _U_(0x13) /**< \brief (AC_INTENSET) MASK Register */ + +/* -------- AC_INTFLAG : (AC Offset: 0x06) (R/W 8) Interrupt Flag Status and Clear -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { // __I to avoid read-modify-write on write-to-clear register + struct { + __I uint8_t COMP0:1; /*!< bit: 0 Comparator 0 */ + __I uint8_t COMP1:1; /*!< bit: 1 Comparator 1 */ + __I uint8_t :2; /*!< bit: 2.. 3 Reserved */ + __I uint8_t WIN0:1; /*!< bit: 4 Window 0 */ + __I uint8_t :3; /*!< bit: 5.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + __I uint8_t COMP:2; /*!< bit: 0.. 1 Comparator x */ + __I uint8_t :2; /*!< bit: 2.. 3 Reserved */ + __I uint8_t WIN:1; /*!< bit: 4 Window x */ + __I uint8_t :3; /*!< bit: 5.. 7 Reserved */ + } vec; /*!< Structure used for vec access */ + uint8_t reg; /*!< Type used for register access */ +} AC_INTFLAG_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AC_INTFLAG_OFFSET 0x06 /**< \brief (AC_INTFLAG offset) Interrupt Flag Status and Clear */ +#define AC_INTFLAG_RESETVALUE _U_(0x00) /**< \brief (AC_INTFLAG reset_value) Interrupt Flag Status and Clear */ + +#define AC_INTFLAG_COMP0_Pos 0 /**< \brief (AC_INTFLAG) Comparator 0 */ +#define AC_INTFLAG_COMP0 (_U_(1) << AC_INTFLAG_COMP0_Pos) +#define AC_INTFLAG_COMP1_Pos 1 /**< \brief (AC_INTFLAG) Comparator 1 */ +#define AC_INTFLAG_COMP1 (_U_(1) << AC_INTFLAG_COMP1_Pos) +#define AC_INTFLAG_COMP_Pos 0 /**< \brief (AC_INTFLAG) Comparator x */ +#define AC_INTFLAG_COMP_Msk (_U_(0x3) << AC_INTFLAG_COMP_Pos) +#define AC_INTFLAG_COMP(value) (AC_INTFLAG_COMP_Msk & ((value) << AC_INTFLAG_COMP_Pos)) +#define AC_INTFLAG_WIN0_Pos 4 /**< \brief (AC_INTFLAG) Window 0 */ +#define AC_INTFLAG_WIN0 (_U_(1) << AC_INTFLAG_WIN0_Pos) +#define AC_INTFLAG_WIN_Pos 4 /**< \brief (AC_INTFLAG) Window x */ +#define AC_INTFLAG_WIN_Msk (_U_(0x1) << AC_INTFLAG_WIN_Pos) +#define AC_INTFLAG_WIN(value) (AC_INTFLAG_WIN_Msk & ((value) << AC_INTFLAG_WIN_Pos)) +#define AC_INTFLAG_MASK _U_(0x13) /**< \brief (AC_INTFLAG) MASK Register */ + +/* -------- AC_STATUSA : (AC Offset: 0x07) (R/ 8) Status A -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t STATE0:1; /*!< bit: 0 Comparator 0 Current State */ + uint8_t STATE1:1; /*!< bit: 1 Comparator 1 Current State */ + uint8_t :2; /*!< bit: 2.. 3 Reserved */ + uint8_t WSTATE0:2; /*!< bit: 4.. 5 Window 0 Current State */ + uint8_t :2; /*!< bit: 6.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint8_t STATE:2; /*!< bit: 0.. 1 Comparator x Current State */ + uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } vec; /*!< Structure used for vec access */ + uint8_t reg; /*!< Type used for register access */ +} AC_STATUSA_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AC_STATUSA_OFFSET 0x07 /**< \brief (AC_STATUSA offset) Status A */ +#define AC_STATUSA_RESETVALUE _U_(0x00) /**< \brief (AC_STATUSA reset_value) Status A */ + +#define AC_STATUSA_STATE0_Pos 0 /**< \brief (AC_STATUSA) Comparator 0 Current State */ +#define AC_STATUSA_STATE0 (_U_(1) << AC_STATUSA_STATE0_Pos) +#define AC_STATUSA_STATE1_Pos 1 /**< \brief (AC_STATUSA) Comparator 1 Current State */ +#define AC_STATUSA_STATE1 (_U_(1) << AC_STATUSA_STATE1_Pos) +#define AC_STATUSA_STATE_Pos 0 /**< \brief (AC_STATUSA) Comparator x Current State */ +#define AC_STATUSA_STATE_Msk (_U_(0x3) << AC_STATUSA_STATE_Pos) +#define AC_STATUSA_STATE(value) (AC_STATUSA_STATE_Msk & ((value) << AC_STATUSA_STATE_Pos)) +#define AC_STATUSA_WSTATE0_Pos 4 /**< \brief (AC_STATUSA) Window 0 Current State */ +#define AC_STATUSA_WSTATE0_Msk (_U_(0x3) << AC_STATUSA_WSTATE0_Pos) +#define AC_STATUSA_WSTATE0(value) (AC_STATUSA_WSTATE0_Msk & ((value) << AC_STATUSA_WSTATE0_Pos)) +#define AC_STATUSA_WSTATE0_ABOVE_Val _U_(0x0) /**< \brief (AC_STATUSA) Signal is above window */ +#define AC_STATUSA_WSTATE0_INSIDE_Val _U_(0x1) /**< \brief (AC_STATUSA) Signal is inside window */ +#define AC_STATUSA_WSTATE0_BELOW_Val _U_(0x2) /**< \brief (AC_STATUSA) Signal is below window */ +#define AC_STATUSA_WSTATE0_ABOVE (AC_STATUSA_WSTATE0_ABOVE_Val << AC_STATUSA_WSTATE0_Pos) +#define AC_STATUSA_WSTATE0_INSIDE (AC_STATUSA_WSTATE0_INSIDE_Val << AC_STATUSA_WSTATE0_Pos) +#define AC_STATUSA_WSTATE0_BELOW (AC_STATUSA_WSTATE0_BELOW_Val << AC_STATUSA_WSTATE0_Pos) +#define AC_STATUSA_MASK _U_(0x33) /**< \brief (AC_STATUSA) MASK Register */ + +/* -------- AC_STATUSB : (AC Offset: 0x08) (R/ 8) Status B -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t READY0:1; /*!< bit: 0 Comparator 0 Ready */ + uint8_t READY1:1; /*!< bit: 1 Comparator 1 Ready */ + uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint8_t READY:2; /*!< bit: 0.. 1 Comparator x Ready */ + uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } vec; /*!< Structure used for vec access */ + uint8_t reg; /*!< Type used for register access */ +} AC_STATUSB_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AC_STATUSB_OFFSET 0x08 /**< \brief (AC_STATUSB offset) Status B */ +#define AC_STATUSB_RESETVALUE _U_(0x00) /**< \brief (AC_STATUSB reset_value) Status B */ + +#define AC_STATUSB_READY0_Pos 0 /**< \brief (AC_STATUSB) Comparator 0 Ready */ +#define AC_STATUSB_READY0 (_U_(1) << AC_STATUSB_READY0_Pos) +#define AC_STATUSB_READY1_Pos 1 /**< \brief (AC_STATUSB) Comparator 1 Ready */ +#define AC_STATUSB_READY1 (_U_(1) << AC_STATUSB_READY1_Pos) +#define AC_STATUSB_READY_Pos 0 /**< \brief (AC_STATUSB) Comparator x Ready */ +#define AC_STATUSB_READY_Msk (_U_(0x3) << AC_STATUSB_READY_Pos) +#define AC_STATUSB_READY(value) (AC_STATUSB_READY_Msk & ((value) << AC_STATUSB_READY_Pos)) +#define AC_STATUSB_MASK _U_(0x03) /**< \brief (AC_STATUSB) MASK Register */ + +/* -------- AC_DBGCTRL : (AC Offset: 0x09) (R/W 8) Debug Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t DBGRUN:1; /*!< bit: 0 Debug Run */ + uint8_t :7; /*!< bit: 1.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} AC_DBGCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AC_DBGCTRL_OFFSET 0x09 /**< \brief (AC_DBGCTRL offset) Debug Control */ +#define AC_DBGCTRL_RESETVALUE _U_(0x00) /**< \brief (AC_DBGCTRL reset_value) Debug Control */ + +#define AC_DBGCTRL_DBGRUN_Pos 0 /**< \brief (AC_DBGCTRL) Debug Run */ +#define AC_DBGCTRL_DBGRUN (_U_(0x1) << AC_DBGCTRL_DBGRUN_Pos) +#define AC_DBGCTRL_MASK _U_(0x01) /**< \brief (AC_DBGCTRL) MASK Register */ + +/* -------- AC_WINCTRL : (AC Offset: 0x0A) (R/W 8) Window Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t WEN0:1; /*!< bit: 0 Window 0 Mode Enable */ + uint8_t WINTSEL0:2; /*!< bit: 1.. 2 Window 0 Interrupt Selection */ + uint8_t :5; /*!< bit: 3.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} AC_WINCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AC_WINCTRL_OFFSET 0x0A /**< \brief (AC_WINCTRL offset) Window Control */ +#define AC_WINCTRL_RESETVALUE _U_(0x00) /**< \brief (AC_WINCTRL reset_value) Window Control */ + +#define AC_WINCTRL_WEN0_Pos 0 /**< \brief (AC_WINCTRL) Window 0 Mode Enable */ +#define AC_WINCTRL_WEN0 (_U_(0x1) << AC_WINCTRL_WEN0_Pos) +#define AC_WINCTRL_WINTSEL0_Pos 1 /**< \brief (AC_WINCTRL) Window 0 Interrupt Selection */ +#define AC_WINCTRL_WINTSEL0_Msk (_U_(0x3) << AC_WINCTRL_WINTSEL0_Pos) +#define AC_WINCTRL_WINTSEL0(value) (AC_WINCTRL_WINTSEL0_Msk & ((value) << AC_WINCTRL_WINTSEL0_Pos)) +#define AC_WINCTRL_WINTSEL0_ABOVE_Val _U_(0x0) /**< \brief (AC_WINCTRL) Interrupt on signal above window */ +#define AC_WINCTRL_WINTSEL0_INSIDE_Val _U_(0x1) /**< \brief (AC_WINCTRL) Interrupt on signal inside window */ +#define AC_WINCTRL_WINTSEL0_BELOW_Val _U_(0x2) /**< \brief (AC_WINCTRL) Interrupt on signal below window */ +#define AC_WINCTRL_WINTSEL0_OUTSIDE_Val _U_(0x3) /**< \brief (AC_WINCTRL) Interrupt on signal outside window */ +#define AC_WINCTRL_WINTSEL0_ABOVE (AC_WINCTRL_WINTSEL0_ABOVE_Val << AC_WINCTRL_WINTSEL0_Pos) +#define AC_WINCTRL_WINTSEL0_INSIDE (AC_WINCTRL_WINTSEL0_INSIDE_Val << AC_WINCTRL_WINTSEL0_Pos) +#define AC_WINCTRL_WINTSEL0_BELOW (AC_WINCTRL_WINTSEL0_BELOW_Val << AC_WINCTRL_WINTSEL0_Pos) +#define AC_WINCTRL_WINTSEL0_OUTSIDE (AC_WINCTRL_WINTSEL0_OUTSIDE_Val << AC_WINCTRL_WINTSEL0_Pos) +#define AC_WINCTRL_MASK _U_(0x07) /**< \brief (AC_WINCTRL) MASK Register */ + +/* -------- AC_SCALER : (AC Offset: 0x0C) (R/W 8) Scaler n -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t VALUE:6; /*!< bit: 0.. 5 Scaler Value */ + uint8_t :2; /*!< bit: 6.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} AC_SCALER_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AC_SCALER_OFFSET 0x0C /**< \brief (AC_SCALER offset) Scaler n */ +#define AC_SCALER_RESETVALUE _U_(0x00) /**< \brief (AC_SCALER reset_value) Scaler n */ + +#define AC_SCALER_VALUE_Pos 0 /**< \brief (AC_SCALER) Scaler Value */ +#define AC_SCALER_VALUE_Msk (_U_(0x3F) << AC_SCALER_VALUE_Pos) +#define AC_SCALER_VALUE(value) (AC_SCALER_VALUE_Msk & ((value) << AC_SCALER_VALUE_Pos)) +#define AC_SCALER_MASK _U_(0x3F) /**< \brief (AC_SCALER) MASK Register */ + +/* -------- AC_COMPCTRL : (AC Offset: 0x10) (R/W 32) Comparator Control n -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t :1; /*!< bit: 0 Reserved */ + uint32_t ENABLE:1; /*!< bit: 1 Enable */ + uint32_t SINGLE:1; /*!< bit: 2 Single-Shot Mode */ + uint32_t INTSEL:2; /*!< bit: 3.. 4 Interrupt Selection */ + uint32_t :1; /*!< bit: 5 Reserved */ + uint32_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */ + uint32_t :1; /*!< bit: 7 Reserved */ + uint32_t MUXNEG:3; /*!< bit: 8..10 Negative Input Mux Selection */ + uint32_t :1; /*!< bit: 11 Reserved */ + uint32_t MUXPOS:3; /*!< bit: 12..14 Positive Input Mux Selection */ + uint32_t SWAP:1; /*!< bit: 15 Swap Inputs and Invert */ + uint32_t SPEED:2; /*!< bit: 16..17 Speed Selection */ + uint32_t :1; /*!< bit: 18 Reserved */ + uint32_t HYSTEN:1; /*!< bit: 19 Hysteresis Enable */ + uint32_t HYST:2; /*!< bit: 20..21 Hysteresis Level */ + uint32_t :2; /*!< bit: 22..23 Reserved */ + uint32_t FLEN:3; /*!< bit: 24..26 Filter Length */ + uint32_t :1; /*!< bit: 27 Reserved */ + uint32_t OUT:2; /*!< bit: 28..29 Output */ + uint32_t :2; /*!< bit: 30..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} AC_COMPCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AC_COMPCTRL_OFFSET 0x10 /**< \brief (AC_COMPCTRL offset) Comparator Control n */ +#define AC_COMPCTRL_RESETVALUE _U_(0x00000000) /**< \brief (AC_COMPCTRL reset_value) Comparator Control n */ + +#define AC_COMPCTRL_ENABLE_Pos 1 /**< \brief (AC_COMPCTRL) Enable */ +#define AC_COMPCTRL_ENABLE (_U_(0x1) << AC_COMPCTRL_ENABLE_Pos) +#define AC_COMPCTRL_SINGLE_Pos 2 /**< \brief (AC_COMPCTRL) Single-Shot Mode */ +#define AC_COMPCTRL_SINGLE (_U_(0x1) << AC_COMPCTRL_SINGLE_Pos) +#define AC_COMPCTRL_INTSEL_Pos 3 /**< \brief (AC_COMPCTRL) Interrupt Selection */ +#define AC_COMPCTRL_INTSEL_Msk (_U_(0x3) << AC_COMPCTRL_INTSEL_Pos) +#define AC_COMPCTRL_INTSEL(value) (AC_COMPCTRL_INTSEL_Msk & ((value) << AC_COMPCTRL_INTSEL_Pos)) +#define AC_COMPCTRL_INTSEL_TOGGLE_Val _U_(0x0) /**< \brief (AC_COMPCTRL) Interrupt on comparator output toggle */ +#define AC_COMPCTRL_INTSEL_RISING_Val _U_(0x1) /**< \brief (AC_COMPCTRL) Interrupt on comparator output rising */ +#define AC_COMPCTRL_INTSEL_FALLING_Val _U_(0x2) /**< \brief (AC_COMPCTRL) Interrupt on comparator output falling */ +#define AC_COMPCTRL_INTSEL_EOC_Val _U_(0x3) /**< \brief (AC_COMPCTRL) Interrupt on end of comparison (single-shot mode only) */ +#define AC_COMPCTRL_INTSEL_TOGGLE (AC_COMPCTRL_INTSEL_TOGGLE_Val << AC_COMPCTRL_INTSEL_Pos) +#define AC_COMPCTRL_INTSEL_RISING (AC_COMPCTRL_INTSEL_RISING_Val << AC_COMPCTRL_INTSEL_Pos) +#define AC_COMPCTRL_INTSEL_FALLING (AC_COMPCTRL_INTSEL_FALLING_Val << AC_COMPCTRL_INTSEL_Pos) +#define AC_COMPCTRL_INTSEL_EOC (AC_COMPCTRL_INTSEL_EOC_Val << AC_COMPCTRL_INTSEL_Pos) +#define AC_COMPCTRL_RUNSTDBY_Pos 6 /**< \brief (AC_COMPCTRL) Run in Standby */ +#define AC_COMPCTRL_RUNSTDBY (_U_(0x1) << AC_COMPCTRL_RUNSTDBY_Pos) +#define AC_COMPCTRL_MUXNEG_Pos 8 /**< \brief (AC_COMPCTRL) Negative Input Mux Selection */ +#define AC_COMPCTRL_MUXNEG_Msk (_U_(0x7) << AC_COMPCTRL_MUXNEG_Pos) +#define AC_COMPCTRL_MUXNEG(value) (AC_COMPCTRL_MUXNEG_Msk & ((value) << AC_COMPCTRL_MUXNEG_Pos)) +#define AC_COMPCTRL_MUXNEG_PIN0_Val _U_(0x0) /**< \brief (AC_COMPCTRL) I/O pin 0 */ +#define AC_COMPCTRL_MUXNEG_PIN1_Val _U_(0x1) /**< \brief (AC_COMPCTRL) I/O pin 1 */ +#define AC_COMPCTRL_MUXNEG_PIN2_Val _U_(0x2) /**< \brief (AC_COMPCTRL) I/O pin 2 */ +#define AC_COMPCTRL_MUXNEG_PIN3_Val _U_(0x3) /**< \brief (AC_COMPCTRL) I/O pin 3 */ +#define AC_COMPCTRL_MUXNEG_GND_Val _U_(0x4) /**< \brief (AC_COMPCTRL) Ground */ +#define AC_COMPCTRL_MUXNEG_VSCALE_Val _U_(0x5) /**< \brief (AC_COMPCTRL) VDD scaler */ +#define AC_COMPCTRL_MUXNEG_BANDGAP_Val _U_(0x6) /**< \brief (AC_COMPCTRL) Internal bandgap voltage */ +#define AC_COMPCTRL_MUXNEG_DAC_Val _U_(0x7) /**< \brief (AC_COMPCTRL) DAC output */ +#define AC_COMPCTRL_MUXNEG_PIN0 (AC_COMPCTRL_MUXNEG_PIN0_Val << AC_COMPCTRL_MUXNEG_Pos) +#define AC_COMPCTRL_MUXNEG_PIN1 (AC_COMPCTRL_MUXNEG_PIN1_Val << AC_COMPCTRL_MUXNEG_Pos) +#define AC_COMPCTRL_MUXNEG_PIN2 (AC_COMPCTRL_MUXNEG_PIN2_Val << AC_COMPCTRL_MUXNEG_Pos) +#define AC_COMPCTRL_MUXNEG_PIN3 (AC_COMPCTRL_MUXNEG_PIN3_Val << AC_COMPCTRL_MUXNEG_Pos) +#define AC_COMPCTRL_MUXNEG_GND (AC_COMPCTRL_MUXNEG_GND_Val << AC_COMPCTRL_MUXNEG_Pos) +#define AC_COMPCTRL_MUXNEG_VSCALE (AC_COMPCTRL_MUXNEG_VSCALE_Val << AC_COMPCTRL_MUXNEG_Pos) +#define AC_COMPCTRL_MUXNEG_BANDGAP (AC_COMPCTRL_MUXNEG_BANDGAP_Val << AC_COMPCTRL_MUXNEG_Pos) +#define AC_COMPCTRL_MUXNEG_DAC (AC_COMPCTRL_MUXNEG_DAC_Val << AC_COMPCTRL_MUXNEG_Pos) +#define AC_COMPCTRL_MUXPOS_Pos 12 /**< \brief (AC_COMPCTRL) Positive Input Mux Selection */ +#define AC_COMPCTRL_MUXPOS_Msk (_U_(0x7) << AC_COMPCTRL_MUXPOS_Pos) +#define AC_COMPCTRL_MUXPOS(value) (AC_COMPCTRL_MUXPOS_Msk & ((value) << AC_COMPCTRL_MUXPOS_Pos)) +#define AC_COMPCTRL_MUXPOS_PIN0_Val _U_(0x0) /**< \brief (AC_COMPCTRL) I/O pin 0 */ +#define AC_COMPCTRL_MUXPOS_PIN1_Val _U_(0x1) /**< \brief (AC_COMPCTRL) I/O pin 1 */ +#define AC_COMPCTRL_MUXPOS_PIN2_Val _U_(0x2) /**< \brief (AC_COMPCTRL) I/O pin 2 */ +#define AC_COMPCTRL_MUXPOS_PIN3_Val _U_(0x3) /**< \brief (AC_COMPCTRL) I/O pin 3 */ +#define AC_COMPCTRL_MUXPOS_VSCALE_Val _U_(0x4) /**< \brief (AC_COMPCTRL) VDD Scaler */ +#define AC_COMPCTRL_MUXPOS_PIN0 (AC_COMPCTRL_MUXPOS_PIN0_Val << AC_COMPCTRL_MUXPOS_Pos) +#define AC_COMPCTRL_MUXPOS_PIN1 (AC_COMPCTRL_MUXPOS_PIN1_Val << AC_COMPCTRL_MUXPOS_Pos) +#define AC_COMPCTRL_MUXPOS_PIN2 (AC_COMPCTRL_MUXPOS_PIN2_Val << AC_COMPCTRL_MUXPOS_Pos) +#define AC_COMPCTRL_MUXPOS_PIN3 (AC_COMPCTRL_MUXPOS_PIN3_Val << AC_COMPCTRL_MUXPOS_Pos) +#define AC_COMPCTRL_MUXPOS_VSCALE (AC_COMPCTRL_MUXPOS_VSCALE_Val << AC_COMPCTRL_MUXPOS_Pos) +#define AC_COMPCTRL_SWAP_Pos 15 /**< \brief (AC_COMPCTRL) Swap Inputs and Invert */ +#define AC_COMPCTRL_SWAP (_U_(0x1) << AC_COMPCTRL_SWAP_Pos) +#define AC_COMPCTRL_SPEED_Pos 16 /**< \brief (AC_COMPCTRL) Speed Selection */ +#define AC_COMPCTRL_SPEED_Msk (_U_(0x3) << AC_COMPCTRL_SPEED_Pos) +#define AC_COMPCTRL_SPEED(value) (AC_COMPCTRL_SPEED_Msk & ((value) << AC_COMPCTRL_SPEED_Pos)) +#define AC_COMPCTRL_SPEED_HIGH_Val _U_(0x3) /**< \brief (AC_COMPCTRL) High speed */ +#define AC_COMPCTRL_SPEED_HIGH (AC_COMPCTRL_SPEED_HIGH_Val << AC_COMPCTRL_SPEED_Pos) +#define AC_COMPCTRL_HYSTEN_Pos 19 /**< \brief (AC_COMPCTRL) Hysteresis Enable */ +#define AC_COMPCTRL_HYSTEN (_U_(0x1) << AC_COMPCTRL_HYSTEN_Pos) +#define AC_COMPCTRL_HYST_Pos 20 /**< \brief (AC_COMPCTRL) Hysteresis Level */ +#define AC_COMPCTRL_HYST_Msk (_U_(0x3) << AC_COMPCTRL_HYST_Pos) +#define AC_COMPCTRL_HYST(value) (AC_COMPCTRL_HYST_Msk & ((value) << AC_COMPCTRL_HYST_Pos)) +#define AC_COMPCTRL_HYST_HYST50_Val _U_(0x0) /**< \brief (AC_COMPCTRL) 50mV */ +#define AC_COMPCTRL_HYST_HYST100_Val _U_(0x1) /**< \brief (AC_COMPCTRL) 100mV */ +#define AC_COMPCTRL_HYST_HYST150_Val _U_(0x2) /**< \brief (AC_COMPCTRL) 150mV */ +#define AC_COMPCTRL_HYST_HYST50 (AC_COMPCTRL_HYST_HYST50_Val << AC_COMPCTRL_HYST_Pos) +#define AC_COMPCTRL_HYST_HYST100 (AC_COMPCTRL_HYST_HYST100_Val << AC_COMPCTRL_HYST_Pos) +#define AC_COMPCTRL_HYST_HYST150 (AC_COMPCTRL_HYST_HYST150_Val << AC_COMPCTRL_HYST_Pos) +#define AC_COMPCTRL_FLEN_Pos 24 /**< \brief (AC_COMPCTRL) Filter Length */ +#define AC_COMPCTRL_FLEN_Msk (_U_(0x7) << AC_COMPCTRL_FLEN_Pos) +#define AC_COMPCTRL_FLEN(value) (AC_COMPCTRL_FLEN_Msk & ((value) << AC_COMPCTRL_FLEN_Pos)) +#define AC_COMPCTRL_FLEN_OFF_Val _U_(0x0) /**< \brief (AC_COMPCTRL) No filtering */ +#define AC_COMPCTRL_FLEN_MAJ3_Val _U_(0x1) /**< \brief (AC_COMPCTRL) 3-bit majority function (2 of 3) */ +#define AC_COMPCTRL_FLEN_MAJ5_Val _U_(0x2) /**< \brief (AC_COMPCTRL) 5-bit majority function (3 of 5) */ +#define AC_COMPCTRL_FLEN_OFF (AC_COMPCTRL_FLEN_OFF_Val << AC_COMPCTRL_FLEN_Pos) +#define AC_COMPCTRL_FLEN_MAJ3 (AC_COMPCTRL_FLEN_MAJ3_Val << AC_COMPCTRL_FLEN_Pos) +#define AC_COMPCTRL_FLEN_MAJ5 (AC_COMPCTRL_FLEN_MAJ5_Val << AC_COMPCTRL_FLEN_Pos) +#define AC_COMPCTRL_OUT_Pos 28 /**< \brief (AC_COMPCTRL) Output */ +#define AC_COMPCTRL_OUT_Msk (_U_(0x3) << AC_COMPCTRL_OUT_Pos) +#define AC_COMPCTRL_OUT(value) (AC_COMPCTRL_OUT_Msk & ((value) << AC_COMPCTRL_OUT_Pos)) +#define AC_COMPCTRL_OUT_OFF_Val _U_(0x0) /**< \brief (AC_COMPCTRL) The output of COMPn is not routed to the COMPn I/O port */ +#define AC_COMPCTRL_OUT_ASYNC_Val _U_(0x1) /**< \brief (AC_COMPCTRL) The asynchronous output of COMPn is routed to the COMPn I/O port */ +#define AC_COMPCTRL_OUT_SYNC_Val _U_(0x2) /**< \brief (AC_COMPCTRL) The synchronous output (including filtering) of COMPn is routed to the COMPn I/O port */ +#define AC_COMPCTRL_OUT_OFF (AC_COMPCTRL_OUT_OFF_Val << AC_COMPCTRL_OUT_Pos) +#define AC_COMPCTRL_OUT_ASYNC (AC_COMPCTRL_OUT_ASYNC_Val << AC_COMPCTRL_OUT_Pos) +#define AC_COMPCTRL_OUT_SYNC (AC_COMPCTRL_OUT_SYNC_Val << AC_COMPCTRL_OUT_Pos) +#define AC_COMPCTRL_MASK _U_(0x373BF75E) /**< \brief (AC_COMPCTRL) MASK Register */ + +/* -------- AC_SYNCBUSY : (AC Offset: 0x20) (R/ 32) Synchronization Busy -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t SWRST:1; /*!< bit: 0 Software Reset Synchronization Busy */ + uint32_t ENABLE:1; /*!< bit: 1 Enable Synchronization Busy */ + uint32_t WINCTRL:1; /*!< bit: 2 WINCTRL Synchronization Busy */ + uint32_t COMPCTRL0:1; /*!< bit: 3 COMPCTRL 0 Synchronization Busy */ + uint32_t COMPCTRL1:1; /*!< bit: 4 COMPCTRL 1 Synchronization Busy */ + uint32_t :27; /*!< bit: 5..31 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint32_t :3; /*!< bit: 0.. 2 Reserved */ + uint32_t COMPCTRL:2; /*!< bit: 3.. 4 COMPCTRL x Synchronization Busy */ + uint32_t :27; /*!< bit: 5..31 Reserved */ + } vec; /*!< Structure used for vec access */ + uint32_t reg; /*!< Type used for register access */ +} AC_SYNCBUSY_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AC_SYNCBUSY_OFFSET 0x20 /**< \brief (AC_SYNCBUSY offset) Synchronization Busy */ +#define AC_SYNCBUSY_RESETVALUE _U_(0x00000000) /**< \brief (AC_SYNCBUSY reset_value) Synchronization Busy */ + +#define AC_SYNCBUSY_SWRST_Pos 0 /**< \brief (AC_SYNCBUSY) Software Reset Synchronization Busy */ +#define AC_SYNCBUSY_SWRST (_U_(0x1) << AC_SYNCBUSY_SWRST_Pos) +#define AC_SYNCBUSY_ENABLE_Pos 1 /**< \brief (AC_SYNCBUSY) Enable Synchronization Busy */ +#define AC_SYNCBUSY_ENABLE (_U_(0x1) << AC_SYNCBUSY_ENABLE_Pos) +#define AC_SYNCBUSY_WINCTRL_Pos 2 /**< \brief (AC_SYNCBUSY) WINCTRL Synchronization Busy */ +#define AC_SYNCBUSY_WINCTRL (_U_(0x1) << AC_SYNCBUSY_WINCTRL_Pos) +#define AC_SYNCBUSY_COMPCTRL0_Pos 3 /**< \brief (AC_SYNCBUSY) COMPCTRL 0 Synchronization Busy */ +#define AC_SYNCBUSY_COMPCTRL0 (_U_(1) << AC_SYNCBUSY_COMPCTRL0_Pos) +#define AC_SYNCBUSY_COMPCTRL1_Pos 4 /**< \brief (AC_SYNCBUSY) COMPCTRL 1 Synchronization Busy */ +#define AC_SYNCBUSY_COMPCTRL1 (_U_(1) << AC_SYNCBUSY_COMPCTRL1_Pos) +#define AC_SYNCBUSY_COMPCTRL_Pos 3 /**< \brief (AC_SYNCBUSY) COMPCTRL x Synchronization Busy */ +#define AC_SYNCBUSY_COMPCTRL_Msk (_U_(0x3) << AC_SYNCBUSY_COMPCTRL_Pos) +#define AC_SYNCBUSY_COMPCTRL(value) (AC_SYNCBUSY_COMPCTRL_Msk & ((value) << AC_SYNCBUSY_COMPCTRL_Pos)) +#define AC_SYNCBUSY_MASK _U_(0x0000001F) /**< \brief (AC_SYNCBUSY) MASK Register */ + +/* -------- AC_CALIB : (AC Offset: 0x24) (R/W 16) Calibration -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t BIAS0:2; /*!< bit: 0.. 1 COMP0/1 Bias Scaling */ + uint16_t :14; /*!< bit: 2..15 Reserved */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} AC_CALIB_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AC_CALIB_OFFSET 0x24 /**< \brief (AC_CALIB offset) Calibration */ +#define AC_CALIB_RESETVALUE _U_(0x0101) /**< \brief (AC_CALIB reset_value) Calibration */ + +#define AC_CALIB_BIAS0_Pos 0 /**< \brief (AC_CALIB) COMP0/1 Bias Scaling */ +#define AC_CALIB_BIAS0_Msk (_U_(0x3) << AC_CALIB_BIAS0_Pos) +#define AC_CALIB_BIAS0(value) (AC_CALIB_BIAS0_Msk & ((value) << AC_CALIB_BIAS0_Pos)) +#define AC_CALIB_MASK _U_(0x0003) /**< \brief (AC_CALIB) MASK Register */ + +/** \brief AC hardware registers */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef struct { + __IO AC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 8) Control A */ + __O AC_CTRLB_Type CTRLB; /**< \brief Offset: 0x01 ( /W 8) Control B */ + __IO AC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x02 (R/W 16) Event Control */ + __IO AC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x04 (R/W 8) Interrupt Enable Clear */ + __IO AC_INTENSET_Type INTENSET; /**< \brief Offset: 0x05 (R/W 8) Interrupt Enable Set */ + __IO AC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x06 (R/W 8) Interrupt Flag Status and Clear */ + __I AC_STATUSA_Type STATUSA; /**< \brief Offset: 0x07 (R/ 8) Status A */ + __I AC_STATUSB_Type STATUSB; /**< \brief Offset: 0x08 (R/ 8) Status B */ + __IO AC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x09 (R/W 8) Debug Control */ + __IO AC_WINCTRL_Type WINCTRL; /**< \brief Offset: 0x0A (R/W 8) Window Control */ + RoReg8 Reserved1[0x1]; + __IO AC_SCALER_Type SCALER[2]; /**< \brief Offset: 0x0C (R/W 8) Scaler n */ + RoReg8 Reserved2[0x2]; + __IO AC_COMPCTRL_Type COMPCTRL[2]; /**< \brief Offset: 0x10 (R/W 32) Comparator Control n */ + RoReg8 Reserved3[0x8]; + __I AC_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x20 (R/ 32) Synchronization Busy */ + __IO AC_CALIB_Type CALIB; /**< \brief Offset: 0x24 (R/W 16) Calibration */ +} Ac; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/*@}*/ + +#endif /* _SAME54_AC_COMPONENT_ */ diff --git a/arch/arm/SAME54/SAME54A/mcu/inc/component/adc.h b/arch/arm/SAME54/SAME54A/mcu/inc/component/adc.h index cb78fd2a..b2fee11e 100644 --- a/arch/arm/SAME54/SAME54A/mcu/inc/component/adc.h +++ b/arch/arm/SAME54/SAME54A/mcu/inc/component/adc.h @@ -1,649 +1,871 @@ -/** - * \brief Component description for ADC - * - * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries. - * - * Subject to your compliance with these terms, you may use Microchip software and any derivatives - * exclusively with Microchip products. It is your responsibility to comply with third party license - * terms applicable to your use of third party software (including open source software) that may - * accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, - * APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND - * FITNESS FOR A PARTICULAR PURPOSE. - * - * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF - * MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT - * EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - */ - -/* file generated from device description version 2020-03-12T17:27:04Z */ -#ifndef _SAME54_ADC_COMPONENT_H_ -#define _SAME54_ADC_COMPONENT_H_ - -/* ************************************************************************** */ -/* SOFTWARE API DEFINITION FOR ADC */ -/* ************************************************************************** */ - -/* -------- ADC_CTRLA : (ADC Offset: 0x00) (R/W 16) Control A -------- */ -#define ADC_CTRLA_RESETVALUE _U_(0x00) /**< (ADC_CTRLA) Control A Reset Value */ - -#define ADC_CTRLA_SWRST_Pos _U_(0) /**< (ADC_CTRLA) Software Reset Position */ -#define ADC_CTRLA_SWRST_Msk (_U_(0x1) << ADC_CTRLA_SWRST_Pos) /**< (ADC_CTRLA) Software Reset Mask */ -#define ADC_CTRLA_SWRST(value) (ADC_CTRLA_SWRST_Msk & ((value) << ADC_CTRLA_SWRST_Pos)) -#define ADC_CTRLA_ENABLE_Pos _U_(1) /**< (ADC_CTRLA) Enable Position */ -#define ADC_CTRLA_ENABLE_Msk (_U_(0x1) << ADC_CTRLA_ENABLE_Pos) /**< (ADC_CTRLA) Enable Mask */ -#define ADC_CTRLA_ENABLE(value) (ADC_CTRLA_ENABLE_Msk & ((value) << ADC_CTRLA_ENABLE_Pos)) -#define ADC_CTRLA_DUALSEL_Pos _U_(3) /**< (ADC_CTRLA) Dual Mode Trigger Selection Position */ -#define ADC_CTRLA_DUALSEL_Msk (_U_(0x3) << ADC_CTRLA_DUALSEL_Pos) /**< (ADC_CTRLA) Dual Mode Trigger Selection Mask */ -#define ADC_CTRLA_DUALSEL(value) (ADC_CTRLA_DUALSEL_Msk & ((value) << ADC_CTRLA_DUALSEL_Pos)) -#define ADC_CTRLA_DUALSEL_BOTH_Val _U_(0x0) /**< (ADC_CTRLA) Start event or software trigger will start a conversion on both ADCs */ -#define ADC_CTRLA_DUALSEL_INTERLEAVE_Val _U_(0x1) /**< (ADC_CTRLA) START event or software trigger will alternatingly start a conversion on ADC0 and ADC1 */ -#define ADC_CTRLA_DUALSEL_BOTH (ADC_CTRLA_DUALSEL_BOTH_Val << ADC_CTRLA_DUALSEL_Pos) /**< (ADC_CTRLA) Start event or software trigger will start a conversion on both ADCs Position */ -#define ADC_CTRLA_DUALSEL_INTERLEAVE (ADC_CTRLA_DUALSEL_INTERLEAVE_Val << ADC_CTRLA_DUALSEL_Pos) /**< (ADC_CTRLA) START event or software trigger will alternatingly start a conversion on ADC0 and ADC1 Position */ -#define ADC_CTRLA_SLAVEEN_Pos _U_(5) /**< (ADC_CTRLA) Slave Enable Position */ -#define ADC_CTRLA_SLAVEEN_Msk (_U_(0x1) << ADC_CTRLA_SLAVEEN_Pos) /**< (ADC_CTRLA) Slave Enable Mask */ -#define ADC_CTRLA_SLAVEEN(value) (ADC_CTRLA_SLAVEEN_Msk & ((value) << ADC_CTRLA_SLAVEEN_Pos)) -#define ADC_CTRLA_RUNSTDBY_Pos _U_(6) /**< (ADC_CTRLA) Run in Standby Position */ -#define ADC_CTRLA_RUNSTDBY_Msk (_U_(0x1) << ADC_CTRLA_RUNSTDBY_Pos) /**< (ADC_CTRLA) Run in Standby Mask */ -#define ADC_CTRLA_RUNSTDBY(value) (ADC_CTRLA_RUNSTDBY_Msk & ((value) << ADC_CTRLA_RUNSTDBY_Pos)) -#define ADC_CTRLA_ONDEMAND_Pos _U_(7) /**< (ADC_CTRLA) On Demand Control Position */ -#define ADC_CTRLA_ONDEMAND_Msk (_U_(0x1) << ADC_CTRLA_ONDEMAND_Pos) /**< (ADC_CTRLA) On Demand Control Mask */ -#define ADC_CTRLA_ONDEMAND(value) (ADC_CTRLA_ONDEMAND_Msk & ((value) << ADC_CTRLA_ONDEMAND_Pos)) -#define ADC_CTRLA_PRESCALER_Pos _U_(8) /**< (ADC_CTRLA) Prescaler Configuration Position */ -#define ADC_CTRLA_PRESCALER_Msk (_U_(0x7) << ADC_CTRLA_PRESCALER_Pos) /**< (ADC_CTRLA) Prescaler Configuration Mask */ -#define ADC_CTRLA_PRESCALER(value) (ADC_CTRLA_PRESCALER_Msk & ((value) << ADC_CTRLA_PRESCALER_Pos)) -#define ADC_CTRLA_PRESCALER_DIV2_Val _U_(0x0) /**< (ADC_CTRLA) Peripheral clock divided by 2 */ -#define ADC_CTRLA_PRESCALER_DIV4_Val _U_(0x1) /**< (ADC_CTRLA) Peripheral clock divided by 4 */ -#define ADC_CTRLA_PRESCALER_DIV8_Val _U_(0x2) /**< (ADC_CTRLA) Peripheral clock divided by 8 */ -#define ADC_CTRLA_PRESCALER_DIV16_Val _U_(0x3) /**< (ADC_CTRLA) Peripheral clock divided by 16 */ -#define ADC_CTRLA_PRESCALER_DIV32_Val _U_(0x4) /**< (ADC_CTRLA) Peripheral clock divided by 32 */ -#define ADC_CTRLA_PRESCALER_DIV64_Val _U_(0x5) /**< (ADC_CTRLA) Peripheral clock divided by 64 */ -#define ADC_CTRLA_PRESCALER_DIV128_Val _U_(0x6) /**< (ADC_CTRLA) Peripheral clock divided by 128 */ -#define ADC_CTRLA_PRESCALER_DIV256_Val _U_(0x7) /**< (ADC_CTRLA) Peripheral clock divided by 256 */ -#define ADC_CTRLA_PRESCALER_DIV2 (ADC_CTRLA_PRESCALER_DIV2_Val << ADC_CTRLA_PRESCALER_Pos) /**< (ADC_CTRLA) Peripheral clock divided by 2 Position */ -#define ADC_CTRLA_PRESCALER_DIV4 (ADC_CTRLA_PRESCALER_DIV4_Val << ADC_CTRLA_PRESCALER_Pos) /**< (ADC_CTRLA) Peripheral clock divided by 4 Position */ -#define ADC_CTRLA_PRESCALER_DIV8 (ADC_CTRLA_PRESCALER_DIV8_Val << ADC_CTRLA_PRESCALER_Pos) /**< (ADC_CTRLA) Peripheral clock divided by 8 Position */ -#define ADC_CTRLA_PRESCALER_DIV16 (ADC_CTRLA_PRESCALER_DIV16_Val << ADC_CTRLA_PRESCALER_Pos) /**< (ADC_CTRLA) Peripheral clock divided by 16 Position */ -#define ADC_CTRLA_PRESCALER_DIV32 (ADC_CTRLA_PRESCALER_DIV32_Val << ADC_CTRLA_PRESCALER_Pos) /**< (ADC_CTRLA) Peripheral clock divided by 32 Position */ -#define ADC_CTRLA_PRESCALER_DIV64 (ADC_CTRLA_PRESCALER_DIV64_Val << ADC_CTRLA_PRESCALER_Pos) /**< (ADC_CTRLA) Peripheral clock divided by 64 Position */ -#define ADC_CTRLA_PRESCALER_DIV128 (ADC_CTRLA_PRESCALER_DIV128_Val << ADC_CTRLA_PRESCALER_Pos) /**< (ADC_CTRLA) Peripheral clock divided by 128 Position */ -#define ADC_CTRLA_PRESCALER_DIV256 (ADC_CTRLA_PRESCALER_DIV256_Val << ADC_CTRLA_PRESCALER_Pos) /**< (ADC_CTRLA) Peripheral clock divided by 256 Position */ -#define ADC_CTRLA_R2R_Pos _U_(15) /**< (ADC_CTRLA) Rail to Rail Operation Enable Position */ -#define ADC_CTRLA_R2R_Msk (_U_(0x1) << ADC_CTRLA_R2R_Pos) /**< (ADC_CTRLA) Rail to Rail Operation Enable Mask */ -#define ADC_CTRLA_R2R(value) (ADC_CTRLA_R2R_Msk & ((value) << ADC_CTRLA_R2R_Pos)) -#define ADC_CTRLA_Msk _U_(0x87FB) /**< (ADC_CTRLA) Register Mask */ - - -/* -------- ADC_EVCTRL : (ADC Offset: 0x02) (R/W 8) Event Control -------- */ -#define ADC_EVCTRL_RESETVALUE _U_(0x00) /**< (ADC_EVCTRL) Event Control Reset Value */ - -#define ADC_EVCTRL_FLUSHEI_Pos _U_(0) /**< (ADC_EVCTRL) Flush Event Input Enable Position */ -#define ADC_EVCTRL_FLUSHEI_Msk (_U_(0x1) << ADC_EVCTRL_FLUSHEI_Pos) /**< (ADC_EVCTRL) Flush Event Input Enable Mask */ -#define ADC_EVCTRL_FLUSHEI(value) (ADC_EVCTRL_FLUSHEI_Msk & ((value) << ADC_EVCTRL_FLUSHEI_Pos)) -#define ADC_EVCTRL_STARTEI_Pos _U_(1) /**< (ADC_EVCTRL) Start Conversion Event Input Enable Position */ -#define ADC_EVCTRL_STARTEI_Msk (_U_(0x1) << ADC_EVCTRL_STARTEI_Pos) /**< (ADC_EVCTRL) Start Conversion Event Input Enable Mask */ -#define ADC_EVCTRL_STARTEI(value) (ADC_EVCTRL_STARTEI_Msk & ((value) << ADC_EVCTRL_STARTEI_Pos)) -#define ADC_EVCTRL_FLUSHINV_Pos _U_(2) /**< (ADC_EVCTRL) Flush Event Invert Enable Position */ -#define ADC_EVCTRL_FLUSHINV_Msk (_U_(0x1) << ADC_EVCTRL_FLUSHINV_Pos) /**< (ADC_EVCTRL) Flush Event Invert Enable Mask */ -#define ADC_EVCTRL_FLUSHINV(value) (ADC_EVCTRL_FLUSHINV_Msk & ((value) << ADC_EVCTRL_FLUSHINV_Pos)) -#define ADC_EVCTRL_STARTINV_Pos _U_(3) /**< (ADC_EVCTRL) Start Conversion Event Invert Enable Position */ -#define ADC_EVCTRL_STARTINV_Msk (_U_(0x1) << ADC_EVCTRL_STARTINV_Pos) /**< (ADC_EVCTRL) Start Conversion Event Invert Enable Mask */ -#define ADC_EVCTRL_STARTINV(value) (ADC_EVCTRL_STARTINV_Msk & ((value) << ADC_EVCTRL_STARTINV_Pos)) -#define ADC_EVCTRL_RESRDYEO_Pos _U_(4) /**< (ADC_EVCTRL) Result Ready Event Out Position */ -#define ADC_EVCTRL_RESRDYEO_Msk (_U_(0x1) << ADC_EVCTRL_RESRDYEO_Pos) /**< (ADC_EVCTRL) Result Ready Event Out Mask */ -#define ADC_EVCTRL_RESRDYEO(value) (ADC_EVCTRL_RESRDYEO_Msk & ((value) << ADC_EVCTRL_RESRDYEO_Pos)) -#define ADC_EVCTRL_WINMONEO_Pos _U_(5) /**< (ADC_EVCTRL) Window Monitor Event Out Position */ -#define ADC_EVCTRL_WINMONEO_Msk (_U_(0x1) << ADC_EVCTRL_WINMONEO_Pos) /**< (ADC_EVCTRL) Window Monitor Event Out Mask */ -#define ADC_EVCTRL_WINMONEO(value) (ADC_EVCTRL_WINMONEO_Msk & ((value) << ADC_EVCTRL_WINMONEO_Pos)) -#define ADC_EVCTRL_Msk _U_(0x3F) /**< (ADC_EVCTRL) Register Mask */ - - -/* -------- ADC_DBGCTRL : (ADC Offset: 0x03) (R/W 8) Debug Control -------- */ -#define ADC_DBGCTRL_RESETVALUE _U_(0x00) /**< (ADC_DBGCTRL) Debug Control Reset Value */ - -#define ADC_DBGCTRL_DBGRUN_Pos _U_(0) /**< (ADC_DBGCTRL) Debug Run Position */ -#define ADC_DBGCTRL_DBGRUN_Msk (_U_(0x1) << ADC_DBGCTRL_DBGRUN_Pos) /**< (ADC_DBGCTRL) Debug Run Mask */ -#define ADC_DBGCTRL_DBGRUN(value) (ADC_DBGCTRL_DBGRUN_Msk & ((value) << ADC_DBGCTRL_DBGRUN_Pos)) -#define ADC_DBGCTRL_Msk _U_(0x01) /**< (ADC_DBGCTRL) Register Mask */ - - -/* -------- ADC_INPUTCTRL : (ADC Offset: 0x04) (R/W 16) Input Control -------- */ -#define ADC_INPUTCTRL_RESETVALUE _U_(0x00) /**< (ADC_INPUTCTRL) Input Control Reset Value */ - -#define ADC_INPUTCTRL_MUXPOS_Pos _U_(0) /**< (ADC_INPUTCTRL) Positive Mux Input Selection Position */ -#define ADC_INPUTCTRL_MUXPOS_Msk (_U_(0x1F) << ADC_INPUTCTRL_MUXPOS_Pos) /**< (ADC_INPUTCTRL) Positive Mux Input Selection Mask */ -#define ADC_INPUTCTRL_MUXPOS(value) (ADC_INPUTCTRL_MUXPOS_Msk & ((value) << ADC_INPUTCTRL_MUXPOS_Pos)) -#define ADC_INPUTCTRL_MUXPOS_AIN0_Val _U_(0x0) /**< (ADC_INPUTCTRL) ADC AIN0 Pin */ -#define ADC_INPUTCTRL_MUXPOS_AIN1_Val _U_(0x1) /**< (ADC_INPUTCTRL) ADC AIN1 Pin */ -#define ADC_INPUTCTRL_MUXPOS_AIN2_Val _U_(0x2) /**< (ADC_INPUTCTRL) ADC AIN2 Pin */ -#define ADC_INPUTCTRL_MUXPOS_AIN3_Val _U_(0x3) /**< (ADC_INPUTCTRL) ADC AIN3 Pin */ -#define ADC_INPUTCTRL_MUXPOS_AIN4_Val _U_(0x4) /**< (ADC_INPUTCTRL) ADC AIN4 Pin */ -#define ADC_INPUTCTRL_MUXPOS_AIN5_Val _U_(0x5) /**< (ADC_INPUTCTRL) ADC AIN5 Pin */ -#define ADC_INPUTCTRL_MUXPOS_AIN6_Val _U_(0x6) /**< (ADC_INPUTCTRL) ADC AIN6 Pin */ -#define ADC_INPUTCTRL_MUXPOS_AIN7_Val _U_(0x7) /**< (ADC_INPUTCTRL) ADC AIN7 Pin */ -#define ADC_INPUTCTRL_MUXPOS_AIN8_Val _U_(0x8) /**< (ADC_INPUTCTRL) ADC AIN8 Pin */ -#define ADC_INPUTCTRL_MUXPOS_AIN9_Val _U_(0x9) /**< (ADC_INPUTCTRL) ADC AIN9 Pin */ -#define ADC_INPUTCTRL_MUXPOS_AIN10_Val _U_(0xA) /**< (ADC_INPUTCTRL) ADC AIN10 Pin */ -#define ADC_INPUTCTRL_MUXPOS_AIN11_Val _U_(0xB) /**< (ADC_INPUTCTRL) ADC AIN11 Pin */ -#define ADC_INPUTCTRL_MUXPOS_AIN12_Val _U_(0xC) /**< (ADC_INPUTCTRL) ADC AIN12 Pin */ -#define ADC_INPUTCTRL_MUXPOS_AIN13_Val _U_(0xD) /**< (ADC_INPUTCTRL) ADC AIN13 Pin */ -#define ADC_INPUTCTRL_MUXPOS_AIN14_Val _U_(0xE) /**< (ADC_INPUTCTRL) ADC AIN14 Pin */ -#define ADC_INPUTCTRL_MUXPOS_AIN15_Val _U_(0xF) /**< (ADC_INPUTCTRL) ADC AIN15 Pin */ -#define ADC_INPUTCTRL_MUXPOS_AIN16_Val _U_(0x10) /**< (ADC_INPUTCTRL) ADC AIN16 Pin */ -#define ADC_INPUTCTRL_MUXPOS_AIN17_Val _U_(0x11) /**< (ADC_INPUTCTRL) ADC AIN17 Pin */ -#define ADC_INPUTCTRL_MUXPOS_AIN18_Val _U_(0x12) /**< (ADC_INPUTCTRL) ADC AIN18 Pin */ -#define ADC_INPUTCTRL_MUXPOS_AIN19_Val _U_(0x13) /**< (ADC_INPUTCTRL) ADC AIN19 Pin */ -#define ADC_INPUTCTRL_MUXPOS_AIN20_Val _U_(0x14) /**< (ADC_INPUTCTRL) ADC AIN20 Pin */ -#define ADC_INPUTCTRL_MUXPOS_AIN21_Val _U_(0x15) /**< (ADC_INPUTCTRL) ADC AIN21 Pin */ -#define ADC_INPUTCTRL_MUXPOS_AIN22_Val _U_(0x16) /**< (ADC_INPUTCTRL) ADC AIN22 Pin */ -#define ADC_INPUTCTRL_MUXPOS_AIN23_Val _U_(0x17) /**< (ADC_INPUTCTRL) ADC AIN23 Pin */ -#define ADC_INPUTCTRL_MUXPOS_SCALEDCOREVCC_Val _U_(0x18) /**< (ADC_INPUTCTRL) 1/4 Scaled Core Supply */ -#define ADC_INPUTCTRL_MUXPOS_SCALEDVBAT_Val _U_(0x19) /**< (ADC_INPUTCTRL) 1/4 Scaled VBAT Supply */ -#define ADC_INPUTCTRL_MUXPOS_SCALEDIOVCC_Val _U_(0x1A) /**< (ADC_INPUTCTRL) 1/4 Scaled I/O Supply */ -#define ADC_INPUTCTRL_MUXPOS_BANDGAP_Val _U_(0x1B) /**< (ADC_INPUTCTRL) Bandgap Voltage */ -#define ADC_INPUTCTRL_MUXPOS_PTAT_Val _U_(0x1C) /**< (ADC_INPUTCTRL) Temperature Sensor TSENSP */ -#define ADC_INPUTCTRL_MUXPOS_CTAT_Val _U_(0x1D) /**< (ADC_INPUTCTRL) Temperature Sensor TSENSC */ -#define ADC_INPUTCTRL_MUXPOS_DAC_Val _U_(0x1E) /**< (ADC_INPUTCTRL) DAC Output */ -#define ADC_INPUTCTRL_MUXPOS_PTC_Val _U_(0x1F) /**< (ADC_INPUTCTRL) PTC output (only on ADC0) */ -#define ADC_INPUTCTRL_MUXPOS_AIN0 (ADC_INPUTCTRL_MUXPOS_AIN0_Val << ADC_INPUTCTRL_MUXPOS_Pos) /**< (ADC_INPUTCTRL) ADC AIN0 Pin Position */ -#define ADC_INPUTCTRL_MUXPOS_AIN1 (ADC_INPUTCTRL_MUXPOS_AIN1_Val << ADC_INPUTCTRL_MUXPOS_Pos) /**< (ADC_INPUTCTRL) ADC AIN1 Pin Position */ -#define ADC_INPUTCTRL_MUXPOS_AIN2 (ADC_INPUTCTRL_MUXPOS_AIN2_Val << ADC_INPUTCTRL_MUXPOS_Pos) /**< (ADC_INPUTCTRL) ADC AIN2 Pin Position */ -#define ADC_INPUTCTRL_MUXPOS_AIN3 (ADC_INPUTCTRL_MUXPOS_AIN3_Val << ADC_INPUTCTRL_MUXPOS_Pos) /**< (ADC_INPUTCTRL) ADC AIN3 Pin Position */ -#define ADC_INPUTCTRL_MUXPOS_AIN4 (ADC_INPUTCTRL_MUXPOS_AIN4_Val << ADC_INPUTCTRL_MUXPOS_Pos) /**< (ADC_INPUTCTRL) ADC AIN4 Pin Position */ -#define ADC_INPUTCTRL_MUXPOS_AIN5 (ADC_INPUTCTRL_MUXPOS_AIN5_Val << ADC_INPUTCTRL_MUXPOS_Pos) /**< (ADC_INPUTCTRL) ADC AIN5 Pin Position */ -#define ADC_INPUTCTRL_MUXPOS_AIN6 (ADC_INPUTCTRL_MUXPOS_AIN6_Val << ADC_INPUTCTRL_MUXPOS_Pos) /**< (ADC_INPUTCTRL) ADC AIN6 Pin Position */ -#define ADC_INPUTCTRL_MUXPOS_AIN7 (ADC_INPUTCTRL_MUXPOS_AIN7_Val << ADC_INPUTCTRL_MUXPOS_Pos) /**< (ADC_INPUTCTRL) ADC AIN7 Pin Position */ -#define ADC_INPUTCTRL_MUXPOS_AIN8 (ADC_INPUTCTRL_MUXPOS_AIN8_Val << ADC_INPUTCTRL_MUXPOS_Pos) /**< (ADC_INPUTCTRL) ADC AIN8 Pin Position */ -#define ADC_INPUTCTRL_MUXPOS_AIN9 (ADC_INPUTCTRL_MUXPOS_AIN9_Val << ADC_INPUTCTRL_MUXPOS_Pos) /**< (ADC_INPUTCTRL) ADC AIN9 Pin Position */ -#define ADC_INPUTCTRL_MUXPOS_AIN10 (ADC_INPUTCTRL_MUXPOS_AIN10_Val << ADC_INPUTCTRL_MUXPOS_Pos) /**< (ADC_INPUTCTRL) ADC AIN10 Pin Position */ -#define ADC_INPUTCTRL_MUXPOS_AIN11 (ADC_INPUTCTRL_MUXPOS_AIN11_Val << ADC_INPUTCTRL_MUXPOS_Pos) /**< (ADC_INPUTCTRL) ADC AIN11 Pin Position */ -#define ADC_INPUTCTRL_MUXPOS_AIN12 (ADC_INPUTCTRL_MUXPOS_AIN12_Val << ADC_INPUTCTRL_MUXPOS_Pos) /**< (ADC_INPUTCTRL) ADC AIN12 Pin Position */ -#define ADC_INPUTCTRL_MUXPOS_AIN13 (ADC_INPUTCTRL_MUXPOS_AIN13_Val << ADC_INPUTCTRL_MUXPOS_Pos) /**< (ADC_INPUTCTRL) ADC AIN13 Pin Position */ -#define ADC_INPUTCTRL_MUXPOS_AIN14 (ADC_INPUTCTRL_MUXPOS_AIN14_Val << ADC_INPUTCTRL_MUXPOS_Pos) /**< (ADC_INPUTCTRL) ADC AIN14 Pin Position */ -#define ADC_INPUTCTRL_MUXPOS_AIN15 (ADC_INPUTCTRL_MUXPOS_AIN15_Val << ADC_INPUTCTRL_MUXPOS_Pos) /**< (ADC_INPUTCTRL) ADC AIN15 Pin Position */ -#define ADC_INPUTCTRL_MUXPOS_AIN16 (ADC_INPUTCTRL_MUXPOS_AIN16_Val << ADC_INPUTCTRL_MUXPOS_Pos) /**< (ADC_INPUTCTRL) ADC AIN16 Pin Position */ -#define ADC_INPUTCTRL_MUXPOS_AIN17 (ADC_INPUTCTRL_MUXPOS_AIN17_Val << ADC_INPUTCTRL_MUXPOS_Pos) /**< (ADC_INPUTCTRL) ADC AIN17 Pin Position */ -#define ADC_INPUTCTRL_MUXPOS_AIN18 (ADC_INPUTCTRL_MUXPOS_AIN18_Val << ADC_INPUTCTRL_MUXPOS_Pos) /**< (ADC_INPUTCTRL) ADC AIN18 Pin Position */ -#define ADC_INPUTCTRL_MUXPOS_AIN19 (ADC_INPUTCTRL_MUXPOS_AIN19_Val << ADC_INPUTCTRL_MUXPOS_Pos) /**< (ADC_INPUTCTRL) ADC AIN19 Pin Position */ -#define ADC_INPUTCTRL_MUXPOS_AIN20 (ADC_INPUTCTRL_MUXPOS_AIN20_Val << ADC_INPUTCTRL_MUXPOS_Pos) /**< (ADC_INPUTCTRL) ADC AIN20 Pin Position */ -#define ADC_INPUTCTRL_MUXPOS_AIN21 (ADC_INPUTCTRL_MUXPOS_AIN21_Val << ADC_INPUTCTRL_MUXPOS_Pos) /**< (ADC_INPUTCTRL) ADC AIN21 Pin Position */ -#define ADC_INPUTCTRL_MUXPOS_AIN22 (ADC_INPUTCTRL_MUXPOS_AIN22_Val << ADC_INPUTCTRL_MUXPOS_Pos) /**< (ADC_INPUTCTRL) ADC AIN22 Pin Position */ -#define ADC_INPUTCTRL_MUXPOS_AIN23 (ADC_INPUTCTRL_MUXPOS_AIN23_Val << ADC_INPUTCTRL_MUXPOS_Pos) /**< (ADC_INPUTCTRL) ADC AIN23 Pin Position */ -#define ADC_INPUTCTRL_MUXPOS_SCALEDCOREVCC (ADC_INPUTCTRL_MUXPOS_SCALEDCOREVCC_Val << ADC_INPUTCTRL_MUXPOS_Pos) /**< (ADC_INPUTCTRL) 1/4 Scaled Core Supply Position */ -#define ADC_INPUTCTRL_MUXPOS_SCALEDVBAT (ADC_INPUTCTRL_MUXPOS_SCALEDVBAT_Val << ADC_INPUTCTRL_MUXPOS_Pos) /**< (ADC_INPUTCTRL) 1/4 Scaled VBAT Supply Position */ -#define ADC_INPUTCTRL_MUXPOS_SCALEDIOVCC (ADC_INPUTCTRL_MUXPOS_SCALEDIOVCC_Val << ADC_INPUTCTRL_MUXPOS_Pos) /**< (ADC_INPUTCTRL) 1/4 Scaled I/O Supply Position */ -#define ADC_INPUTCTRL_MUXPOS_BANDGAP (ADC_INPUTCTRL_MUXPOS_BANDGAP_Val << ADC_INPUTCTRL_MUXPOS_Pos) /**< (ADC_INPUTCTRL) Bandgap Voltage Position */ -#define ADC_INPUTCTRL_MUXPOS_PTAT (ADC_INPUTCTRL_MUXPOS_PTAT_Val << ADC_INPUTCTRL_MUXPOS_Pos) /**< (ADC_INPUTCTRL) Temperature Sensor TSENSP Position */ -#define ADC_INPUTCTRL_MUXPOS_CTAT (ADC_INPUTCTRL_MUXPOS_CTAT_Val << ADC_INPUTCTRL_MUXPOS_Pos) /**< (ADC_INPUTCTRL) Temperature Sensor TSENSC Position */ -#define ADC_INPUTCTRL_MUXPOS_DAC (ADC_INPUTCTRL_MUXPOS_DAC_Val << ADC_INPUTCTRL_MUXPOS_Pos) /**< (ADC_INPUTCTRL) DAC Output Position */ -#define ADC_INPUTCTRL_MUXPOS_PTC (ADC_INPUTCTRL_MUXPOS_PTC_Val << ADC_INPUTCTRL_MUXPOS_Pos) /**< (ADC_INPUTCTRL) PTC output (only on ADC0) Position */ -#define ADC_INPUTCTRL_DIFFMODE_Pos _U_(7) /**< (ADC_INPUTCTRL) Differential Mode Position */ -#define ADC_INPUTCTRL_DIFFMODE_Msk (_U_(0x1) << ADC_INPUTCTRL_DIFFMODE_Pos) /**< (ADC_INPUTCTRL) Differential Mode Mask */ -#define ADC_INPUTCTRL_DIFFMODE(value) (ADC_INPUTCTRL_DIFFMODE_Msk & ((value) << ADC_INPUTCTRL_DIFFMODE_Pos)) -#define ADC_INPUTCTRL_MUXNEG_Pos _U_(8) /**< (ADC_INPUTCTRL) Negative Mux Input Selection Position */ -#define ADC_INPUTCTRL_MUXNEG_Msk (_U_(0x1F) << ADC_INPUTCTRL_MUXNEG_Pos) /**< (ADC_INPUTCTRL) Negative Mux Input Selection Mask */ -#define ADC_INPUTCTRL_MUXNEG(value) (ADC_INPUTCTRL_MUXNEG_Msk & ((value) << ADC_INPUTCTRL_MUXNEG_Pos)) -#define ADC_INPUTCTRL_MUXNEG_AIN0_Val _U_(0x0) /**< (ADC_INPUTCTRL) ADC AIN0 Pin */ -#define ADC_INPUTCTRL_MUXNEG_AIN1_Val _U_(0x1) /**< (ADC_INPUTCTRL) ADC AIN1 Pin */ -#define ADC_INPUTCTRL_MUXNEG_AIN2_Val _U_(0x2) /**< (ADC_INPUTCTRL) ADC AIN2 Pin */ -#define ADC_INPUTCTRL_MUXNEG_AIN3_Val _U_(0x3) /**< (ADC_INPUTCTRL) ADC AIN3 Pin */ -#define ADC_INPUTCTRL_MUXNEG_AIN4_Val _U_(0x4) /**< (ADC_INPUTCTRL) ADC AIN4 Pin */ -#define ADC_INPUTCTRL_MUXNEG_AIN5_Val _U_(0x5) /**< (ADC_INPUTCTRL) ADC AIN5 Pin */ -#define ADC_INPUTCTRL_MUXNEG_AIN6_Val _U_(0x6) /**< (ADC_INPUTCTRL) ADC AIN6 Pin */ -#define ADC_INPUTCTRL_MUXNEG_AIN7_Val _U_(0x7) /**< (ADC_INPUTCTRL) ADC AIN7 Pin */ -#define ADC_INPUTCTRL_MUXNEG_GND_Val _U_(0x18) /**< (ADC_INPUTCTRL) Internal Ground */ -#define ADC_INPUTCTRL_MUXNEG_AIN0 (ADC_INPUTCTRL_MUXNEG_AIN0_Val << ADC_INPUTCTRL_MUXNEG_Pos) /**< (ADC_INPUTCTRL) ADC AIN0 Pin Position */ -#define ADC_INPUTCTRL_MUXNEG_AIN1 (ADC_INPUTCTRL_MUXNEG_AIN1_Val << ADC_INPUTCTRL_MUXNEG_Pos) /**< (ADC_INPUTCTRL) ADC AIN1 Pin Position */ -#define ADC_INPUTCTRL_MUXNEG_AIN2 (ADC_INPUTCTRL_MUXNEG_AIN2_Val << ADC_INPUTCTRL_MUXNEG_Pos) /**< (ADC_INPUTCTRL) ADC AIN2 Pin Position */ -#define ADC_INPUTCTRL_MUXNEG_AIN3 (ADC_INPUTCTRL_MUXNEG_AIN3_Val << ADC_INPUTCTRL_MUXNEG_Pos) /**< (ADC_INPUTCTRL) ADC AIN3 Pin Position */ -#define ADC_INPUTCTRL_MUXNEG_AIN4 (ADC_INPUTCTRL_MUXNEG_AIN4_Val << ADC_INPUTCTRL_MUXNEG_Pos) /**< (ADC_INPUTCTRL) ADC AIN4 Pin Position */ -#define ADC_INPUTCTRL_MUXNEG_AIN5 (ADC_INPUTCTRL_MUXNEG_AIN5_Val << ADC_INPUTCTRL_MUXNEG_Pos) /**< (ADC_INPUTCTRL) ADC AIN5 Pin Position */ -#define ADC_INPUTCTRL_MUXNEG_AIN6 (ADC_INPUTCTRL_MUXNEG_AIN6_Val << ADC_INPUTCTRL_MUXNEG_Pos) /**< (ADC_INPUTCTRL) ADC AIN6 Pin Position */ -#define ADC_INPUTCTRL_MUXNEG_AIN7 (ADC_INPUTCTRL_MUXNEG_AIN7_Val << ADC_INPUTCTRL_MUXNEG_Pos) /**< (ADC_INPUTCTRL) ADC AIN7 Pin Position */ -#define ADC_INPUTCTRL_MUXNEG_GND (ADC_INPUTCTRL_MUXNEG_GND_Val << ADC_INPUTCTRL_MUXNEG_Pos) /**< (ADC_INPUTCTRL) Internal Ground Position */ -#define ADC_INPUTCTRL_DSEQSTOP_Pos _U_(15) /**< (ADC_INPUTCTRL) Stop DMA Sequencing Position */ -#define ADC_INPUTCTRL_DSEQSTOP_Msk (_U_(0x1) << ADC_INPUTCTRL_DSEQSTOP_Pos) /**< (ADC_INPUTCTRL) Stop DMA Sequencing Mask */ -#define ADC_INPUTCTRL_DSEQSTOP(value) (ADC_INPUTCTRL_DSEQSTOP_Msk & ((value) << ADC_INPUTCTRL_DSEQSTOP_Pos)) -#define ADC_INPUTCTRL_Msk _U_(0x9F9F) /**< (ADC_INPUTCTRL) Register Mask */ - - -/* -------- ADC_CTRLB : (ADC Offset: 0x06) (R/W 16) Control B -------- */ -#define ADC_CTRLB_RESETVALUE _U_(0x00) /**< (ADC_CTRLB) Control B Reset Value */ - -#define ADC_CTRLB_LEFTADJ_Pos _U_(0) /**< (ADC_CTRLB) Left-Adjusted Result Position */ -#define ADC_CTRLB_LEFTADJ_Msk (_U_(0x1) << ADC_CTRLB_LEFTADJ_Pos) /**< (ADC_CTRLB) Left-Adjusted Result Mask */ -#define ADC_CTRLB_LEFTADJ(value) (ADC_CTRLB_LEFTADJ_Msk & ((value) << ADC_CTRLB_LEFTADJ_Pos)) -#define ADC_CTRLB_FREERUN_Pos _U_(1) /**< (ADC_CTRLB) Free Running Mode Position */ -#define ADC_CTRLB_FREERUN_Msk (_U_(0x1) << ADC_CTRLB_FREERUN_Pos) /**< (ADC_CTRLB) Free Running Mode Mask */ -#define ADC_CTRLB_FREERUN(value) (ADC_CTRLB_FREERUN_Msk & ((value) << ADC_CTRLB_FREERUN_Pos)) -#define ADC_CTRLB_CORREN_Pos _U_(2) /**< (ADC_CTRLB) Digital Correction Logic Enable Position */ -#define ADC_CTRLB_CORREN_Msk (_U_(0x1) << ADC_CTRLB_CORREN_Pos) /**< (ADC_CTRLB) Digital Correction Logic Enable Mask */ -#define ADC_CTRLB_CORREN(value) (ADC_CTRLB_CORREN_Msk & ((value) << ADC_CTRLB_CORREN_Pos)) -#define ADC_CTRLB_RESSEL_Pos _U_(3) /**< (ADC_CTRLB) Conversion Result Resolution Position */ -#define ADC_CTRLB_RESSEL_Msk (_U_(0x3) << ADC_CTRLB_RESSEL_Pos) /**< (ADC_CTRLB) Conversion Result Resolution Mask */ -#define ADC_CTRLB_RESSEL(value) (ADC_CTRLB_RESSEL_Msk & ((value) << ADC_CTRLB_RESSEL_Pos)) -#define ADC_CTRLB_RESSEL_12BIT_Val _U_(0x0) /**< (ADC_CTRLB) 12-bit result */ -#define ADC_CTRLB_RESSEL_16BIT_Val _U_(0x1) /**< (ADC_CTRLB) For averaging mode output */ -#define ADC_CTRLB_RESSEL_10BIT_Val _U_(0x2) /**< (ADC_CTRLB) 10-bit result */ -#define ADC_CTRLB_RESSEL_8BIT_Val _U_(0x3) /**< (ADC_CTRLB) 8-bit result */ -#define ADC_CTRLB_RESSEL_12BIT (ADC_CTRLB_RESSEL_12BIT_Val << ADC_CTRLB_RESSEL_Pos) /**< (ADC_CTRLB) 12-bit result Position */ -#define ADC_CTRLB_RESSEL_16BIT (ADC_CTRLB_RESSEL_16BIT_Val << ADC_CTRLB_RESSEL_Pos) /**< (ADC_CTRLB) For averaging mode output Position */ -#define ADC_CTRLB_RESSEL_10BIT (ADC_CTRLB_RESSEL_10BIT_Val << ADC_CTRLB_RESSEL_Pos) /**< (ADC_CTRLB) 10-bit result Position */ -#define ADC_CTRLB_RESSEL_8BIT (ADC_CTRLB_RESSEL_8BIT_Val << ADC_CTRLB_RESSEL_Pos) /**< (ADC_CTRLB) 8-bit result Position */ -#define ADC_CTRLB_WINMODE_Pos _U_(8) /**< (ADC_CTRLB) Window Monitor Mode Position */ -#define ADC_CTRLB_WINMODE_Msk (_U_(0x7) << ADC_CTRLB_WINMODE_Pos) /**< (ADC_CTRLB) Window Monitor Mode Mask */ -#define ADC_CTRLB_WINMODE(value) (ADC_CTRLB_WINMODE_Msk & ((value) << ADC_CTRLB_WINMODE_Pos)) -#define ADC_CTRLB_WINMODE_DISABLE_Val _U_(0x0) /**< (ADC_CTRLB) No window mode (default) */ -#define ADC_CTRLB_WINMODE_MODE1_Val _U_(0x1) /**< (ADC_CTRLB) RESULT > WINLT */ -#define ADC_CTRLB_WINMODE_MODE2_Val _U_(0x2) /**< (ADC_CTRLB) RESULT < WINUT */ -#define ADC_CTRLB_WINMODE_MODE3_Val _U_(0x3) /**< (ADC_CTRLB) WINLT < RESULT < WINUT */ -#define ADC_CTRLB_WINMODE_MODE4_Val _U_(0x4) /**< (ADC_CTRLB) !(WINLT < RESULT < WINUT) */ -#define ADC_CTRLB_WINMODE_DISABLE (ADC_CTRLB_WINMODE_DISABLE_Val << ADC_CTRLB_WINMODE_Pos) /**< (ADC_CTRLB) No window mode (default) Position */ -#define ADC_CTRLB_WINMODE_MODE1 (ADC_CTRLB_WINMODE_MODE1_Val << ADC_CTRLB_WINMODE_Pos) /**< (ADC_CTRLB) RESULT > WINLT Position */ -#define ADC_CTRLB_WINMODE_MODE2 (ADC_CTRLB_WINMODE_MODE2_Val << ADC_CTRLB_WINMODE_Pos) /**< (ADC_CTRLB) RESULT < WINUT Position */ -#define ADC_CTRLB_WINMODE_MODE3 (ADC_CTRLB_WINMODE_MODE3_Val << ADC_CTRLB_WINMODE_Pos) /**< (ADC_CTRLB) WINLT < RESULT < WINUT Position */ -#define ADC_CTRLB_WINMODE_MODE4 (ADC_CTRLB_WINMODE_MODE4_Val << ADC_CTRLB_WINMODE_Pos) /**< (ADC_CTRLB) !(WINLT < RESULT < WINUT) Position */ -#define ADC_CTRLB_WINSS_Pos _U_(11) /**< (ADC_CTRLB) Window Single Sample Position */ -#define ADC_CTRLB_WINSS_Msk (_U_(0x1) << ADC_CTRLB_WINSS_Pos) /**< (ADC_CTRLB) Window Single Sample Mask */ -#define ADC_CTRLB_WINSS(value) (ADC_CTRLB_WINSS_Msk & ((value) << ADC_CTRLB_WINSS_Pos)) -#define ADC_CTRLB_Msk _U_(0x0F1F) /**< (ADC_CTRLB) Register Mask */ - - -/* -------- ADC_REFCTRL : (ADC Offset: 0x08) (R/W 8) Reference Control -------- */ -#define ADC_REFCTRL_RESETVALUE _U_(0x00) /**< (ADC_REFCTRL) Reference Control Reset Value */ - -#define ADC_REFCTRL_REFSEL_Pos _U_(0) /**< (ADC_REFCTRL) Reference Selection Position */ -#define ADC_REFCTRL_REFSEL_Msk (_U_(0xF) << ADC_REFCTRL_REFSEL_Pos) /**< (ADC_REFCTRL) Reference Selection Mask */ -#define ADC_REFCTRL_REFSEL(value) (ADC_REFCTRL_REFSEL_Msk & ((value) << ADC_REFCTRL_REFSEL_Pos)) -#define ADC_REFCTRL_REFSEL_INTREF_Val _U_(0x0) /**< (ADC_REFCTRL) Internal Bandgap Reference */ -#define ADC_REFCTRL_REFSEL_INTVCC0_Val _U_(0x2) /**< (ADC_REFCTRL) 1/2 VDDANA */ -#define ADC_REFCTRL_REFSEL_INTVCC1_Val _U_(0x3) /**< (ADC_REFCTRL) VDDANA */ -#define ADC_REFCTRL_REFSEL_AREFA_Val _U_(0x4) /**< (ADC_REFCTRL) External Reference A */ -#define ADC_REFCTRL_REFSEL_AREFB_Val _U_(0x5) /**< (ADC_REFCTRL) External Reference B */ -#define ADC_REFCTRL_REFSEL_AREFC_Val _U_(0x6) /**< (ADC_REFCTRL) External Reference C (only on ADC1) */ -#define ADC_REFCTRL_REFSEL_INTREF (ADC_REFCTRL_REFSEL_INTREF_Val << ADC_REFCTRL_REFSEL_Pos) /**< (ADC_REFCTRL) Internal Bandgap Reference Position */ -#define ADC_REFCTRL_REFSEL_INTVCC0 (ADC_REFCTRL_REFSEL_INTVCC0_Val << ADC_REFCTRL_REFSEL_Pos) /**< (ADC_REFCTRL) 1/2 VDDANA Position */ -#define ADC_REFCTRL_REFSEL_INTVCC1 (ADC_REFCTRL_REFSEL_INTVCC1_Val << ADC_REFCTRL_REFSEL_Pos) /**< (ADC_REFCTRL) VDDANA Position */ -#define ADC_REFCTRL_REFSEL_AREFA (ADC_REFCTRL_REFSEL_AREFA_Val << ADC_REFCTRL_REFSEL_Pos) /**< (ADC_REFCTRL) External Reference A Position */ -#define ADC_REFCTRL_REFSEL_AREFB (ADC_REFCTRL_REFSEL_AREFB_Val << ADC_REFCTRL_REFSEL_Pos) /**< (ADC_REFCTRL) External Reference B Position */ -#define ADC_REFCTRL_REFSEL_AREFC (ADC_REFCTRL_REFSEL_AREFC_Val << ADC_REFCTRL_REFSEL_Pos) /**< (ADC_REFCTRL) External Reference C (only on ADC1) Position */ -#define ADC_REFCTRL_REFCOMP_Pos _U_(7) /**< (ADC_REFCTRL) Reference Buffer Offset Compensation Enable Position */ -#define ADC_REFCTRL_REFCOMP_Msk (_U_(0x1) << ADC_REFCTRL_REFCOMP_Pos) /**< (ADC_REFCTRL) Reference Buffer Offset Compensation Enable Mask */ -#define ADC_REFCTRL_REFCOMP(value) (ADC_REFCTRL_REFCOMP_Msk & ((value) << ADC_REFCTRL_REFCOMP_Pos)) -#define ADC_REFCTRL_Msk _U_(0x8F) /**< (ADC_REFCTRL) Register Mask */ - - -/* -------- ADC_AVGCTRL : (ADC Offset: 0x0A) (R/W 8) Average Control -------- */ -#define ADC_AVGCTRL_RESETVALUE _U_(0x00) /**< (ADC_AVGCTRL) Average Control Reset Value */ - -#define ADC_AVGCTRL_SAMPLENUM_Pos _U_(0) /**< (ADC_AVGCTRL) Number of Samples to be Collected Position */ -#define ADC_AVGCTRL_SAMPLENUM_Msk (_U_(0xF) << ADC_AVGCTRL_SAMPLENUM_Pos) /**< (ADC_AVGCTRL) Number of Samples to be Collected Mask */ -#define ADC_AVGCTRL_SAMPLENUM(value) (ADC_AVGCTRL_SAMPLENUM_Msk & ((value) << ADC_AVGCTRL_SAMPLENUM_Pos)) -#define ADC_AVGCTRL_SAMPLENUM_1_Val _U_(0x0) /**< (ADC_AVGCTRL) 1 sample */ -#define ADC_AVGCTRL_SAMPLENUM_2_Val _U_(0x1) /**< (ADC_AVGCTRL) 2 samples */ -#define ADC_AVGCTRL_SAMPLENUM_4_Val _U_(0x2) /**< (ADC_AVGCTRL) 4 samples */ -#define ADC_AVGCTRL_SAMPLENUM_8_Val _U_(0x3) /**< (ADC_AVGCTRL) 8 samples */ -#define ADC_AVGCTRL_SAMPLENUM_16_Val _U_(0x4) /**< (ADC_AVGCTRL) 16 samples */ -#define ADC_AVGCTRL_SAMPLENUM_32_Val _U_(0x5) /**< (ADC_AVGCTRL) 32 samples */ -#define ADC_AVGCTRL_SAMPLENUM_64_Val _U_(0x6) /**< (ADC_AVGCTRL) 64 samples */ -#define ADC_AVGCTRL_SAMPLENUM_128_Val _U_(0x7) /**< (ADC_AVGCTRL) 128 samples */ -#define ADC_AVGCTRL_SAMPLENUM_256_Val _U_(0x8) /**< (ADC_AVGCTRL) 256 samples */ -#define ADC_AVGCTRL_SAMPLENUM_512_Val _U_(0x9) /**< (ADC_AVGCTRL) 512 samples */ -#define ADC_AVGCTRL_SAMPLENUM_1024_Val _U_(0xA) /**< (ADC_AVGCTRL) 1024 samples */ -#define ADC_AVGCTRL_SAMPLENUM_1 (ADC_AVGCTRL_SAMPLENUM_1_Val << ADC_AVGCTRL_SAMPLENUM_Pos) /**< (ADC_AVGCTRL) 1 sample Position */ -#define ADC_AVGCTRL_SAMPLENUM_2 (ADC_AVGCTRL_SAMPLENUM_2_Val << ADC_AVGCTRL_SAMPLENUM_Pos) /**< (ADC_AVGCTRL) 2 samples Position */ -#define ADC_AVGCTRL_SAMPLENUM_4 (ADC_AVGCTRL_SAMPLENUM_4_Val << ADC_AVGCTRL_SAMPLENUM_Pos) /**< (ADC_AVGCTRL) 4 samples Position */ -#define ADC_AVGCTRL_SAMPLENUM_8 (ADC_AVGCTRL_SAMPLENUM_8_Val << ADC_AVGCTRL_SAMPLENUM_Pos) /**< (ADC_AVGCTRL) 8 samples Position */ -#define ADC_AVGCTRL_SAMPLENUM_16 (ADC_AVGCTRL_SAMPLENUM_16_Val << ADC_AVGCTRL_SAMPLENUM_Pos) /**< (ADC_AVGCTRL) 16 samples Position */ -#define ADC_AVGCTRL_SAMPLENUM_32 (ADC_AVGCTRL_SAMPLENUM_32_Val << ADC_AVGCTRL_SAMPLENUM_Pos) /**< (ADC_AVGCTRL) 32 samples Position */ -#define ADC_AVGCTRL_SAMPLENUM_64 (ADC_AVGCTRL_SAMPLENUM_64_Val << ADC_AVGCTRL_SAMPLENUM_Pos) /**< (ADC_AVGCTRL) 64 samples Position */ -#define ADC_AVGCTRL_SAMPLENUM_128 (ADC_AVGCTRL_SAMPLENUM_128_Val << ADC_AVGCTRL_SAMPLENUM_Pos) /**< (ADC_AVGCTRL) 128 samples Position */ -#define ADC_AVGCTRL_SAMPLENUM_256 (ADC_AVGCTRL_SAMPLENUM_256_Val << ADC_AVGCTRL_SAMPLENUM_Pos) /**< (ADC_AVGCTRL) 256 samples Position */ -#define ADC_AVGCTRL_SAMPLENUM_512 (ADC_AVGCTRL_SAMPLENUM_512_Val << ADC_AVGCTRL_SAMPLENUM_Pos) /**< (ADC_AVGCTRL) 512 samples Position */ -#define ADC_AVGCTRL_SAMPLENUM_1024 (ADC_AVGCTRL_SAMPLENUM_1024_Val << ADC_AVGCTRL_SAMPLENUM_Pos) /**< (ADC_AVGCTRL) 1024 samples Position */ -#define ADC_AVGCTRL_ADJRES_Pos _U_(4) /**< (ADC_AVGCTRL) Adjusting Result / Division Coefficient Position */ -#define ADC_AVGCTRL_ADJRES_Msk (_U_(0x7) << ADC_AVGCTRL_ADJRES_Pos) /**< (ADC_AVGCTRL) Adjusting Result / Division Coefficient Mask */ -#define ADC_AVGCTRL_ADJRES(value) (ADC_AVGCTRL_ADJRES_Msk & ((value) << ADC_AVGCTRL_ADJRES_Pos)) -#define ADC_AVGCTRL_Msk _U_(0x7F) /**< (ADC_AVGCTRL) Register Mask */ - - -/* -------- ADC_SAMPCTRL : (ADC Offset: 0x0B) (R/W 8) Sample Time Control -------- */ -#define ADC_SAMPCTRL_RESETVALUE _U_(0x00) /**< (ADC_SAMPCTRL) Sample Time Control Reset Value */ - -#define ADC_SAMPCTRL_SAMPLEN_Pos _U_(0) /**< (ADC_SAMPCTRL) Sampling Time Length Position */ -#define ADC_SAMPCTRL_SAMPLEN_Msk (_U_(0x3F) << ADC_SAMPCTRL_SAMPLEN_Pos) /**< (ADC_SAMPCTRL) Sampling Time Length Mask */ -#define ADC_SAMPCTRL_SAMPLEN(value) (ADC_SAMPCTRL_SAMPLEN_Msk & ((value) << ADC_SAMPCTRL_SAMPLEN_Pos)) -#define ADC_SAMPCTRL_OFFCOMP_Pos _U_(7) /**< (ADC_SAMPCTRL) Comparator Offset Compensation Enable Position */ -#define ADC_SAMPCTRL_OFFCOMP_Msk (_U_(0x1) << ADC_SAMPCTRL_OFFCOMP_Pos) /**< (ADC_SAMPCTRL) Comparator Offset Compensation Enable Mask */ -#define ADC_SAMPCTRL_OFFCOMP(value) (ADC_SAMPCTRL_OFFCOMP_Msk & ((value) << ADC_SAMPCTRL_OFFCOMP_Pos)) -#define ADC_SAMPCTRL_Msk _U_(0xBF) /**< (ADC_SAMPCTRL) Register Mask */ - - -/* -------- ADC_WINLT : (ADC Offset: 0x0C) (R/W 16) Window Monitor Lower Threshold -------- */ -#define ADC_WINLT_RESETVALUE _U_(0x00) /**< (ADC_WINLT) Window Monitor Lower Threshold Reset Value */ - -#define ADC_WINLT_WINLT_Pos _U_(0) /**< (ADC_WINLT) Window Lower Threshold Position */ -#define ADC_WINLT_WINLT_Msk (_U_(0xFFFF) << ADC_WINLT_WINLT_Pos) /**< (ADC_WINLT) Window Lower Threshold Mask */ -#define ADC_WINLT_WINLT(value) (ADC_WINLT_WINLT_Msk & ((value) << ADC_WINLT_WINLT_Pos)) -#define ADC_WINLT_Msk _U_(0xFFFF) /**< (ADC_WINLT) Register Mask */ - - -/* -------- ADC_WINUT : (ADC Offset: 0x0E) (R/W 16) Window Monitor Upper Threshold -------- */ -#define ADC_WINUT_RESETVALUE _U_(0x00) /**< (ADC_WINUT) Window Monitor Upper Threshold Reset Value */ - -#define ADC_WINUT_WINUT_Pos _U_(0) /**< (ADC_WINUT) Window Upper Threshold Position */ -#define ADC_WINUT_WINUT_Msk (_U_(0xFFFF) << ADC_WINUT_WINUT_Pos) /**< (ADC_WINUT) Window Upper Threshold Mask */ -#define ADC_WINUT_WINUT(value) (ADC_WINUT_WINUT_Msk & ((value) << ADC_WINUT_WINUT_Pos)) -#define ADC_WINUT_Msk _U_(0xFFFF) /**< (ADC_WINUT) Register Mask */ - - -/* -------- ADC_GAINCORR : (ADC Offset: 0x10) (R/W 16) Gain Correction -------- */ -#define ADC_GAINCORR_RESETVALUE _U_(0x00) /**< (ADC_GAINCORR) Gain Correction Reset Value */ - -#define ADC_GAINCORR_GAINCORR_Pos _U_(0) /**< (ADC_GAINCORR) Gain Correction Value Position */ -#define ADC_GAINCORR_GAINCORR_Msk (_U_(0xFFF) << ADC_GAINCORR_GAINCORR_Pos) /**< (ADC_GAINCORR) Gain Correction Value Mask */ -#define ADC_GAINCORR_GAINCORR(value) (ADC_GAINCORR_GAINCORR_Msk & ((value) << ADC_GAINCORR_GAINCORR_Pos)) -#define ADC_GAINCORR_Msk _U_(0x0FFF) /**< (ADC_GAINCORR) Register Mask */ - - -/* -------- ADC_OFFSETCORR : (ADC Offset: 0x12) (R/W 16) Offset Correction -------- */ -#define ADC_OFFSETCORR_RESETVALUE _U_(0x00) /**< (ADC_OFFSETCORR) Offset Correction Reset Value */ - -#define ADC_OFFSETCORR_OFFSETCORR_Pos _U_(0) /**< (ADC_OFFSETCORR) Offset Correction Value Position */ -#define ADC_OFFSETCORR_OFFSETCORR_Msk (_U_(0xFFF) << ADC_OFFSETCORR_OFFSETCORR_Pos) /**< (ADC_OFFSETCORR) Offset Correction Value Mask */ -#define ADC_OFFSETCORR_OFFSETCORR(value) (ADC_OFFSETCORR_OFFSETCORR_Msk & ((value) << ADC_OFFSETCORR_OFFSETCORR_Pos)) -#define ADC_OFFSETCORR_Msk _U_(0x0FFF) /**< (ADC_OFFSETCORR) Register Mask */ - - -/* -------- ADC_SWTRIG : (ADC Offset: 0x14) (R/W 8) Software Trigger -------- */ -#define ADC_SWTRIG_RESETVALUE _U_(0x00) /**< (ADC_SWTRIG) Software Trigger Reset Value */ - -#define ADC_SWTRIG_FLUSH_Pos _U_(0) /**< (ADC_SWTRIG) ADC Conversion Flush Position */ -#define ADC_SWTRIG_FLUSH_Msk (_U_(0x1) << ADC_SWTRIG_FLUSH_Pos) /**< (ADC_SWTRIG) ADC Conversion Flush Mask */ -#define ADC_SWTRIG_FLUSH(value) (ADC_SWTRIG_FLUSH_Msk & ((value) << ADC_SWTRIG_FLUSH_Pos)) -#define ADC_SWTRIG_START_Pos _U_(1) /**< (ADC_SWTRIG) Start ADC Conversion Position */ -#define ADC_SWTRIG_START_Msk (_U_(0x1) << ADC_SWTRIG_START_Pos) /**< (ADC_SWTRIG) Start ADC Conversion Mask */ -#define ADC_SWTRIG_START(value) (ADC_SWTRIG_START_Msk & ((value) << ADC_SWTRIG_START_Pos)) -#define ADC_SWTRIG_Msk _U_(0x03) /**< (ADC_SWTRIG) Register Mask */ - - -/* -------- ADC_INTENCLR : (ADC Offset: 0x2C) (R/W 8) Interrupt Enable Clear -------- */ -#define ADC_INTENCLR_RESETVALUE _U_(0x00) /**< (ADC_INTENCLR) Interrupt Enable Clear Reset Value */ - -#define ADC_INTENCLR_RESRDY_Pos _U_(0) /**< (ADC_INTENCLR) Result Ready Interrupt Disable Position */ -#define ADC_INTENCLR_RESRDY_Msk (_U_(0x1) << ADC_INTENCLR_RESRDY_Pos) /**< (ADC_INTENCLR) Result Ready Interrupt Disable Mask */ -#define ADC_INTENCLR_RESRDY(value) (ADC_INTENCLR_RESRDY_Msk & ((value) << ADC_INTENCLR_RESRDY_Pos)) -#define ADC_INTENCLR_OVERRUN_Pos _U_(1) /**< (ADC_INTENCLR) Overrun Interrupt Disable Position */ -#define ADC_INTENCLR_OVERRUN_Msk (_U_(0x1) << ADC_INTENCLR_OVERRUN_Pos) /**< (ADC_INTENCLR) Overrun Interrupt Disable Mask */ -#define ADC_INTENCLR_OVERRUN(value) (ADC_INTENCLR_OVERRUN_Msk & ((value) << ADC_INTENCLR_OVERRUN_Pos)) -#define ADC_INTENCLR_WINMON_Pos _U_(2) /**< (ADC_INTENCLR) Window Monitor Interrupt Disable Position */ -#define ADC_INTENCLR_WINMON_Msk (_U_(0x1) << ADC_INTENCLR_WINMON_Pos) /**< (ADC_INTENCLR) Window Monitor Interrupt Disable Mask */ -#define ADC_INTENCLR_WINMON(value) (ADC_INTENCLR_WINMON_Msk & ((value) << ADC_INTENCLR_WINMON_Pos)) -#define ADC_INTENCLR_Msk _U_(0x07) /**< (ADC_INTENCLR) Register Mask */ - - -/* -------- ADC_INTENSET : (ADC Offset: 0x2D) (R/W 8) Interrupt Enable Set -------- */ -#define ADC_INTENSET_RESETVALUE _U_(0x00) /**< (ADC_INTENSET) Interrupt Enable Set Reset Value */ - -#define ADC_INTENSET_RESRDY_Pos _U_(0) /**< (ADC_INTENSET) Result Ready Interrupt Enable Position */ -#define ADC_INTENSET_RESRDY_Msk (_U_(0x1) << ADC_INTENSET_RESRDY_Pos) /**< (ADC_INTENSET) Result Ready Interrupt Enable Mask */ -#define ADC_INTENSET_RESRDY(value) (ADC_INTENSET_RESRDY_Msk & ((value) << ADC_INTENSET_RESRDY_Pos)) -#define ADC_INTENSET_OVERRUN_Pos _U_(1) /**< (ADC_INTENSET) Overrun Interrupt Enable Position */ -#define ADC_INTENSET_OVERRUN_Msk (_U_(0x1) << ADC_INTENSET_OVERRUN_Pos) /**< (ADC_INTENSET) Overrun Interrupt Enable Mask */ -#define ADC_INTENSET_OVERRUN(value) (ADC_INTENSET_OVERRUN_Msk & ((value) << ADC_INTENSET_OVERRUN_Pos)) -#define ADC_INTENSET_WINMON_Pos _U_(2) /**< (ADC_INTENSET) Window Monitor Interrupt Enable Position */ -#define ADC_INTENSET_WINMON_Msk (_U_(0x1) << ADC_INTENSET_WINMON_Pos) /**< (ADC_INTENSET) Window Monitor Interrupt Enable Mask */ -#define ADC_INTENSET_WINMON(value) (ADC_INTENSET_WINMON_Msk & ((value) << ADC_INTENSET_WINMON_Pos)) -#define ADC_INTENSET_Msk _U_(0x07) /**< (ADC_INTENSET) Register Mask */ - - -/* -------- ADC_INTFLAG : (ADC Offset: 0x2E) (R/W 8) Interrupt Flag Status and Clear -------- */ -#define ADC_INTFLAG_RESETVALUE _U_(0x00) /**< (ADC_INTFLAG) Interrupt Flag Status and Clear Reset Value */ - -#define ADC_INTFLAG_RESRDY_Pos _U_(0) /**< (ADC_INTFLAG) Result Ready Interrupt Flag Position */ -#define ADC_INTFLAG_RESRDY_Msk (_U_(0x1) << ADC_INTFLAG_RESRDY_Pos) /**< (ADC_INTFLAG) Result Ready Interrupt Flag Mask */ -#define ADC_INTFLAG_RESRDY(value) (ADC_INTFLAG_RESRDY_Msk & ((value) << ADC_INTFLAG_RESRDY_Pos)) -#define ADC_INTFLAG_OVERRUN_Pos _U_(1) /**< (ADC_INTFLAG) Overrun Interrupt Flag Position */ -#define ADC_INTFLAG_OVERRUN_Msk (_U_(0x1) << ADC_INTFLAG_OVERRUN_Pos) /**< (ADC_INTFLAG) Overrun Interrupt Flag Mask */ -#define ADC_INTFLAG_OVERRUN(value) (ADC_INTFLAG_OVERRUN_Msk & ((value) << ADC_INTFLAG_OVERRUN_Pos)) -#define ADC_INTFLAG_WINMON_Pos _U_(2) /**< (ADC_INTFLAG) Window Monitor Interrupt Flag Position */ -#define ADC_INTFLAG_WINMON_Msk (_U_(0x1) << ADC_INTFLAG_WINMON_Pos) /**< (ADC_INTFLAG) Window Monitor Interrupt Flag Mask */ -#define ADC_INTFLAG_WINMON(value) (ADC_INTFLAG_WINMON_Msk & ((value) << ADC_INTFLAG_WINMON_Pos)) -#define ADC_INTFLAG_Msk _U_(0x07) /**< (ADC_INTFLAG) Register Mask */ - - -/* -------- ADC_STATUS : (ADC Offset: 0x2F) ( R/ 8) Status -------- */ -#define ADC_STATUS_RESETVALUE _U_(0x00) /**< (ADC_STATUS) Status Reset Value */ - -#define ADC_STATUS_ADCBUSY_Pos _U_(0) /**< (ADC_STATUS) ADC Busy Status Position */ -#define ADC_STATUS_ADCBUSY_Msk (_U_(0x1) << ADC_STATUS_ADCBUSY_Pos) /**< (ADC_STATUS) ADC Busy Status Mask */ -#define ADC_STATUS_ADCBUSY(value) (ADC_STATUS_ADCBUSY_Msk & ((value) << ADC_STATUS_ADCBUSY_Pos)) -#define ADC_STATUS_WCC_Pos _U_(2) /**< (ADC_STATUS) Window Comparator Counter Position */ -#define ADC_STATUS_WCC_Msk (_U_(0x3F) << ADC_STATUS_WCC_Pos) /**< (ADC_STATUS) Window Comparator Counter Mask */ -#define ADC_STATUS_WCC(value) (ADC_STATUS_WCC_Msk & ((value) << ADC_STATUS_WCC_Pos)) -#define ADC_STATUS_Msk _U_(0xFD) /**< (ADC_STATUS) Register Mask */ - - -/* -------- ADC_SYNCBUSY : (ADC Offset: 0x30) ( R/ 32) Synchronization Busy -------- */ -#define ADC_SYNCBUSY_RESETVALUE _U_(0x00) /**< (ADC_SYNCBUSY) Synchronization Busy Reset Value */ - -#define ADC_SYNCBUSY_SWRST_Pos _U_(0) /**< (ADC_SYNCBUSY) SWRST Synchronization Busy Position */ -#define ADC_SYNCBUSY_SWRST_Msk (_U_(0x1) << ADC_SYNCBUSY_SWRST_Pos) /**< (ADC_SYNCBUSY) SWRST Synchronization Busy Mask */ -#define ADC_SYNCBUSY_SWRST(value) (ADC_SYNCBUSY_SWRST_Msk & ((value) << ADC_SYNCBUSY_SWRST_Pos)) -#define ADC_SYNCBUSY_ENABLE_Pos _U_(1) /**< (ADC_SYNCBUSY) ENABLE Synchronization Busy Position */ -#define ADC_SYNCBUSY_ENABLE_Msk (_U_(0x1) << ADC_SYNCBUSY_ENABLE_Pos) /**< (ADC_SYNCBUSY) ENABLE Synchronization Busy Mask */ -#define ADC_SYNCBUSY_ENABLE(value) (ADC_SYNCBUSY_ENABLE_Msk & ((value) << ADC_SYNCBUSY_ENABLE_Pos)) -#define ADC_SYNCBUSY_INPUTCTRL_Pos _U_(2) /**< (ADC_SYNCBUSY) Input Control Synchronization Busy Position */ -#define ADC_SYNCBUSY_INPUTCTRL_Msk (_U_(0x1) << ADC_SYNCBUSY_INPUTCTRL_Pos) /**< (ADC_SYNCBUSY) Input Control Synchronization Busy Mask */ -#define ADC_SYNCBUSY_INPUTCTRL(value) (ADC_SYNCBUSY_INPUTCTRL_Msk & ((value) << ADC_SYNCBUSY_INPUTCTRL_Pos)) -#define ADC_SYNCBUSY_CTRLB_Pos _U_(3) /**< (ADC_SYNCBUSY) Control B Synchronization Busy Position */ -#define ADC_SYNCBUSY_CTRLB_Msk (_U_(0x1) << ADC_SYNCBUSY_CTRLB_Pos) /**< (ADC_SYNCBUSY) Control B Synchronization Busy Mask */ -#define ADC_SYNCBUSY_CTRLB(value) (ADC_SYNCBUSY_CTRLB_Msk & ((value) << ADC_SYNCBUSY_CTRLB_Pos)) -#define ADC_SYNCBUSY_REFCTRL_Pos _U_(4) /**< (ADC_SYNCBUSY) Reference Control Synchronization Busy Position */ -#define ADC_SYNCBUSY_REFCTRL_Msk (_U_(0x1) << ADC_SYNCBUSY_REFCTRL_Pos) /**< (ADC_SYNCBUSY) Reference Control Synchronization Busy Mask */ -#define ADC_SYNCBUSY_REFCTRL(value) (ADC_SYNCBUSY_REFCTRL_Msk & ((value) << ADC_SYNCBUSY_REFCTRL_Pos)) -#define ADC_SYNCBUSY_AVGCTRL_Pos _U_(5) /**< (ADC_SYNCBUSY) Average Control Synchronization Busy Position */ -#define ADC_SYNCBUSY_AVGCTRL_Msk (_U_(0x1) << ADC_SYNCBUSY_AVGCTRL_Pos) /**< (ADC_SYNCBUSY) Average Control Synchronization Busy Mask */ -#define ADC_SYNCBUSY_AVGCTRL(value) (ADC_SYNCBUSY_AVGCTRL_Msk & ((value) << ADC_SYNCBUSY_AVGCTRL_Pos)) -#define ADC_SYNCBUSY_SAMPCTRL_Pos _U_(6) /**< (ADC_SYNCBUSY) Sampling Time Control Synchronization Busy Position */ -#define ADC_SYNCBUSY_SAMPCTRL_Msk (_U_(0x1) << ADC_SYNCBUSY_SAMPCTRL_Pos) /**< (ADC_SYNCBUSY) Sampling Time Control Synchronization Busy Mask */ -#define ADC_SYNCBUSY_SAMPCTRL(value) (ADC_SYNCBUSY_SAMPCTRL_Msk & ((value) << ADC_SYNCBUSY_SAMPCTRL_Pos)) -#define ADC_SYNCBUSY_WINLT_Pos _U_(7) /**< (ADC_SYNCBUSY) Window Monitor Lower Threshold Synchronization Busy Position */ -#define ADC_SYNCBUSY_WINLT_Msk (_U_(0x1) << ADC_SYNCBUSY_WINLT_Pos) /**< (ADC_SYNCBUSY) Window Monitor Lower Threshold Synchronization Busy Mask */ -#define ADC_SYNCBUSY_WINLT(value) (ADC_SYNCBUSY_WINLT_Msk & ((value) << ADC_SYNCBUSY_WINLT_Pos)) -#define ADC_SYNCBUSY_WINUT_Pos _U_(8) /**< (ADC_SYNCBUSY) Window Monitor Upper Threshold Synchronization Busy Position */ -#define ADC_SYNCBUSY_WINUT_Msk (_U_(0x1) << ADC_SYNCBUSY_WINUT_Pos) /**< (ADC_SYNCBUSY) Window Monitor Upper Threshold Synchronization Busy Mask */ -#define ADC_SYNCBUSY_WINUT(value) (ADC_SYNCBUSY_WINUT_Msk & ((value) << ADC_SYNCBUSY_WINUT_Pos)) -#define ADC_SYNCBUSY_GAINCORR_Pos _U_(9) /**< (ADC_SYNCBUSY) Gain Correction Synchronization Busy Position */ -#define ADC_SYNCBUSY_GAINCORR_Msk (_U_(0x1) << ADC_SYNCBUSY_GAINCORR_Pos) /**< (ADC_SYNCBUSY) Gain Correction Synchronization Busy Mask */ -#define ADC_SYNCBUSY_GAINCORR(value) (ADC_SYNCBUSY_GAINCORR_Msk & ((value) << ADC_SYNCBUSY_GAINCORR_Pos)) -#define ADC_SYNCBUSY_OFFSETCORR_Pos _U_(10) /**< (ADC_SYNCBUSY) Offset Correction Synchronization Busy Position */ -#define ADC_SYNCBUSY_OFFSETCORR_Msk (_U_(0x1) << ADC_SYNCBUSY_OFFSETCORR_Pos) /**< (ADC_SYNCBUSY) Offset Correction Synchronization Busy Mask */ -#define ADC_SYNCBUSY_OFFSETCORR(value) (ADC_SYNCBUSY_OFFSETCORR_Msk & ((value) << ADC_SYNCBUSY_OFFSETCORR_Pos)) -#define ADC_SYNCBUSY_SWTRIG_Pos _U_(11) /**< (ADC_SYNCBUSY) Software Trigger Synchronization Busy Position */ -#define ADC_SYNCBUSY_SWTRIG_Msk (_U_(0x1) << ADC_SYNCBUSY_SWTRIG_Pos) /**< (ADC_SYNCBUSY) Software Trigger Synchronization Busy Mask */ -#define ADC_SYNCBUSY_SWTRIG(value) (ADC_SYNCBUSY_SWTRIG_Msk & ((value) << ADC_SYNCBUSY_SWTRIG_Pos)) -#define ADC_SYNCBUSY_Msk _U_(0x00000FFF) /**< (ADC_SYNCBUSY) Register Mask */ - - -/* -------- ADC_DSEQDATA : (ADC Offset: 0x34) ( /W 32) DMA Sequencial Data -------- */ -#define ADC_DSEQDATA_RESETVALUE _U_(0x00) /**< (ADC_DSEQDATA) DMA Sequencial Data Reset Value */ - -#define ADC_DSEQDATA_DATA_Pos _U_(0) /**< (ADC_DSEQDATA) DMA Sequential Data Position */ -#define ADC_DSEQDATA_DATA_Msk (_U_(0xFFFFFFFF) << ADC_DSEQDATA_DATA_Pos) /**< (ADC_DSEQDATA) DMA Sequential Data Mask */ -#define ADC_DSEQDATA_DATA(value) (ADC_DSEQDATA_DATA_Msk & ((value) << ADC_DSEQDATA_DATA_Pos)) -#define ADC_DSEQDATA_Msk _U_(0xFFFFFFFF) /**< (ADC_DSEQDATA) Register Mask */ - - -/* -------- ADC_DSEQCTRL : (ADC Offset: 0x38) (R/W 32) DMA Sequential Control -------- */ -#define ADC_DSEQCTRL_RESETVALUE _U_(0x00) /**< (ADC_DSEQCTRL) DMA Sequential Control Reset Value */ - -#define ADC_DSEQCTRL_INPUTCTRL_Pos _U_(0) /**< (ADC_DSEQCTRL) Input Control Position */ -#define ADC_DSEQCTRL_INPUTCTRL_Msk (_U_(0x1) << ADC_DSEQCTRL_INPUTCTRL_Pos) /**< (ADC_DSEQCTRL) Input Control Mask */ -#define ADC_DSEQCTRL_INPUTCTRL(value) (ADC_DSEQCTRL_INPUTCTRL_Msk & ((value) << ADC_DSEQCTRL_INPUTCTRL_Pos)) -#define ADC_DSEQCTRL_CTRLB_Pos _U_(1) /**< (ADC_DSEQCTRL) Control B Position */ -#define ADC_DSEQCTRL_CTRLB_Msk (_U_(0x1) << ADC_DSEQCTRL_CTRLB_Pos) /**< (ADC_DSEQCTRL) Control B Mask */ -#define ADC_DSEQCTRL_CTRLB(value) (ADC_DSEQCTRL_CTRLB_Msk & ((value) << ADC_DSEQCTRL_CTRLB_Pos)) -#define ADC_DSEQCTRL_REFCTRL_Pos _U_(2) /**< (ADC_DSEQCTRL) Reference Control Position */ -#define ADC_DSEQCTRL_REFCTRL_Msk (_U_(0x1) << ADC_DSEQCTRL_REFCTRL_Pos) /**< (ADC_DSEQCTRL) Reference Control Mask */ -#define ADC_DSEQCTRL_REFCTRL(value) (ADC_DSEQCTRL_REFCTRL_Msk & ((value) << ADC_DSEQCTRL_REFCTRL_Pos)) -#define ADC_DSEQCTRL_AVGCTRL_Pos _U_(3) /**< (ADC_DSEQCTRL) Average Control Position */ -#define ADC_DSEQCTRL_AVGCTRL_Msk (_U_(0x1) << ADC_DSEQCTRL_AVGCTRL_Pos) /**< (ADC_DSEQCTRL) Average Control Mask */ -#define ADC_DSEQCTRL_AVGCTRL(value) (ADC_DSEQCTRL_AVGCTRL_Msk & ((value) << ADC_DSEQCTRL_AVGCTRL_Pos)) -#define ADC_DSEQCTRL_SAMPCTRL_Pos _U_(4) /**< (ADC_DSEQCTRL) Sampling Time Control Position */ -#define ADC_DSEQCTRL_SAMPCTRL_Msk (_U_(0x1) << ADC_DSEQCTRL_SAMPCTRL_Pos) /**< (ADC_DSEQCTRL) Sampling Time Control Mask */ -#define ADC_DSEQCTRL_SAMPCTRL(value) (ADC_DSEQCTRL_SAMPCTRL_Msk & ((value) << ADC_DSEQCTRL_SAMPCTRL_Pos)) -#define ADC_DSEQCTRL_WINLT_Pos _U_(5) /**< (ADC_DSEQCTRL) Window Monitor Lower Threshold Position */ -#define ADC_DSEQCTRL_WINLT_Msk (_U_(0x1) << ADC_DSEQCTRL_WINLT_Pos) /**< (ADC_DSEQCTRL) Window Monitor Lower Threshold Mask */ -#define ADC_DSEQCTRL_WINLT(value) (ADC_DSEQCTRL_WINLT_Msk & ((value) << ADC_DSEQCTRL_WINLT_Pos)) -#define ADC_DSEQCTRL_WINUT_Pos _U_(6) /**< (ADC_DSEQCTRL) Window Monitor Upper Threshold Position */ -#define ADC_DSEQCTRL_WINUT_Msk (_U_(0x1) << ADC_DSEQCTRL_WINUT_Pos) /**< (ADC_DSEQCTRL) Window Monitor Upper Threshold Mask */ -#define ADC_DSEQCTRL_WINUT(value) (ADC_DSEQCTRL_WINUT_Msk & ((value) << ADC_DSEQCTRL_WINUT_Pos)) -#define ADC_DSEQCTRL_GAINCORR_Pos _U_(7) /**< (ADC_DSEQCTRL) Gain Correction Position */ -#define ADC_DSEQCTRL_GAINCORR_Msk (_U_(0x1) << ADC_DSEQCTRL_GAINCORR_Pos) /**< (ADC_DSEQCTRL) Gain Correction Mask */ -#define ADC_DSEQCTRL_GAINCORR(value) (ADC_DSEQCTRL_GAINCORR_Msk & ((value) << ADC_DSEQCTRL_GAINCORR_Pos)) -#define ADC_DSEQCTRL_OFFSETCORR_Pos _U_(8) /**< (ADC_DSEQCTRL) Offset Correction Position */ -#define ADC_DSEQCTRL_OFFSETCORR_Msk (_U_(0x1) << ADC_DSEQCTRL_OFFSETCORR_Pos) /**< (ADC_DSEQCTRL) Offset Correction Mask */ -#define ADC_DSEQCTRL_OFFSETCORR(value) (ADC_DSEQCTRL_OFFSETCORR_Msk & ((value) << ADC_DSEQCTRL_OFFSETCORR_Pos)) -#define ADC_DSEQCTRL_AUTOSTART_Pos _U_(31) /**< (ADC_DSEQCTRL) ADC Auto-Start Conversion Position */ -#define ADC_DSEQCTRL_AUTOSTART_Msk (_U_(0x1) << ADC_DSEQCTRL_AUTOSTART_Pos) /**< (ADC_DSEQCTRL) ADC Auto-Start Conversion Mask */ -#define ADC_DSEQCTRL_AUTOSTART(value) (ADC_DSEQCTRL_AUTOSTART_Msk & ((value) << ADC_DSEQCTRL_AUTOSTART_Pos)) -#define ADC_DSEQCTRL_Msk _U_(0x800001FF) /**< (ADC_DSEQCTRL) Register Mask */ - - -/* -------- ADC_DSEQSTAT : (ADC Offset: 0x3C) ( R/ 32) DMA Sequencial Status -------- */ -#define ADC_DSEQSTAT_RESETVALUE _U_(0x00) /**< (ADC_DSEQSTAT) DMA Sequencial Status Reset Value */ - -#define ADC_DSEQSTAT_INPUTCTRL_Pos _U_(0) /**< (ADC_DSEQSTAT) Input Control Position */ -#define ADC_DSEQSTAT_INPUTCTRL_Msk (_U_(0x1) << ADC_DSEQSTAT_INPUTCTRL_Pos) /**< (ADC_DSEQSTAT) Input Control Mask */ -#define ADC_DSEQSTAT_INPUTCTRL(value) (ADC_DSEQSTAT_INPUTCTRL_Msk & ((value) << ADC_DSEQSTAT_INPUTCTRL_Pos)) -#define ADC_DSEQSTAT_CTRLB_Pos _U_(1) /**< (ADC_DSEQSTAT) Control B Position */ -#define ADC_DSEQSTAT_CTRLB_Msk (_U_(0x1) << ADC_DSEQSTAT_CTRLB_Pos) /**< (ADC_DSEQSTAT) Control B Mask */ -#define ADC_DSEQSTAT_CTRLB(value) (ADC_DSEQSTAT_CTRLB_Msk & ((value) << ADC_DSEQSTAT_CTRLB_Pos)) -#define ADC_DSEQSTAT_REFCTRL_Pos _U_(2) /**< (ADC_DSEQSTAT) Reference Control Position */ -#define ADC_DSEQSTAT_REFCTRL_Msk (_U_(0x1) << ADC_DSEQSTAT_REFCTRL_Pos) /**< (ADC_DSEQSTAT) Reference Control Mask */ -#define ADC_DSEQSTAT_REFCTRL(value) (ADC_DSEQSTAT_REFCTRL_Msk & ((value) << ADC_DSEQSTAT_REFCTRL_Pos)) -#define ADC_DSEQSTAT_AVGCTRL_Pos _U_(3) /**< (ADC_DSEQSTAT) Average Control Position */ -#define ADC_DSEQSTAT_AVGCTRL_Msk (_U_(0x1) << ADC_DSEQSTAT_AVGCTRL_Pos) /**< (ADC_DSEQSTAT) Average Control Mask */ -#define ADC_DSEQSTAT_AVGCTRL(value) (ADC_DSEQSTAT_AVGCTRL_Msk & ((value) << ADC_DSEQSTAT_AVGCTRL_Pos)) -#define ADC_DSEQSTAT_SAMPCTRL_Pos _U_(4) /**< (ADC_DSEQSTAT) Sampling Time Control Position */ -#define ADC_DSEQSTAT_SAMPCTRL_Msk (_U_(0x1) << ADC_DSEQSTAT_SAMPCTRL_Pos) /**< (ADC_DSEQSTAT) Sampling Time Control Mask */ -#define ADC_DSEQSTAT_SAMPCTRL(value) (ADC_DSEQSTAT_SAMPCTRL_Msk & ((value) << ADC_DSEQSTAT_SAMPCTRL_Pos)) -#define ADC_DSEQSTAT_WINLT_Pos _U_(5) /**< (ADC_DSEQSTAT) Window Monitor Lower Threshold Position */ -#define ADC_DSEQSTAT_WINLT_Msk (_U_(0x1) << ADC_DSEQSTAT_WINLT_Pos) /**< (ADC_DSEQSTAT) Window Monitor Lower Threshold Mask */ -#define ADC_DSEQSTAT_WINLT(value) (ADC_DSEQSTAT_WINLT_Msk & ((value) << ADC_DSEQSTAT_WINLT_Pos)) -#define ADC_DSEQSTAT_WINUT_Pos _U_(6) /**< (ADC_DSEQSTAT) Window Monitor Upper Threshold Position */ -#define ADC_DSEQSTAT_WINUT_Msk (_U_(0x1) << ADC_DSEQSTAT_WINUT_Pos) /**< (ADC_DSEQSTAT) Window Monitor Upper Threshold Mask */ -#define ADC_DSEQSTAT_WINUT(value) (ADC_DSEQSTAT_WINUT_Msk & ((value) << ADC_DSEQSTAT_WINUT_Pos)) -#define ADC_DSEQSTAT_GAINCORR_Pos _U_(7) /**< (ADC_DSEQSTAT) Gain Correction Position */ -#define ADC_DSEQSTAT_GAINCORR_Msk (_U_(0x1) << ADC_DSEQSTAT_GAINCORR_Pos) /**< (ADC_DSEQSTAT) Gain Correction Mask */ -#define ADC_DSEQSTAT_GAINCORR(value) (ADC_DSEQSTAT_GAINCORR_Msk & ((value) << ADC_DSEQSTAT_GAINCORR_Pos)) -#define ADC_DSEQSTAT_OFFSETCORR_Pos _U_(8) /**< (ADC_DSEQSTAT) Offset Correction Position */ -#define ADC_DSEQSTAT_OFFSETCORR_Msk (_U_(0x1) << ADC_DSEQSTAT_OFFSETCORR_Pos) /**< (ADC_DSEQSTAT) Offset Correction Mask */ -#define ADC_DSEQSTAT_OFFSETCORR(value) (ADC_DSEQSTAT_OFFSETCORR_Msk & ((value) << ADC_DSEQSTAT_OFFSETCORR_Pos)) -#define ADC_DSEQSTAT_BUSY_Pos _U_(31) /**< (ADC_DSEQSTAT) DMA Sequencing Busy Position */ -#define ADC_DSEQSTAT_BUSY_Msk (_U_(0x1) << ADC_DSEQSTAT_BUSY_Pos) /**< (ADC_DSEQSTAT) DMA Sequencing Busy Mask */ -#define ADC_DSEQSTAT_BUSY(value) (ADC_DSEQSTAT_BUSY_Msk & ((value) << ADC_DSEQSTAT_BUSY_Pos)) -#define ADC_DSEQSTAT_Msk _U_(0x800001FF) /**< (ADC_DSEQSTAT) Register Mask */ - - -/* -------- ADC_RESULT : (ADC Offset: 0x40) ( R/ 16) Result Conversion Value -------- */ -#define ADC_RESULT_RESETVALUE _U_(0x00) /**< (ADC_RESULT) Result Conversion Value Reset Value */ - -#define ADC_RESULT_RESULT_Pos _U_(0) /**< (ADC_RESULT) Result Conversion Value Position */ -#define ADC_RESULT_RESULT_Msk (_U_(0xFFFF) << ADC_RESULT_RESULT_Pos) /**< (ADC_RESULT) Result Conversion Value Mask */ -#define ADC_RESULT_RESULT(value) (ADC_RESULT_RESULT_Msk & ((value) << ADC_RESULT_RESULT_Pos)) -#define ADC_RESULT_Msk _U_(0xFFFF) /**< (ADC_RESULT) Register Mask */ - - -/* -------- ADC_RESS : (ADC Offset: 0x44) ( R/ 16) Last Sample Result -------- */ -#define ADC_RESS_RESETVALUE _U_(0x00) /**< (ADC_RESS) Last Sample Result Reset Value */ - -#define ADC_RESS_RESS_Pos _U_(0) /**< (ADC_RESS) Last ADC conversion result Position */ -#define ADC_RESS_RESS_Msk (_U_(0xFFFF) << ADC_RESS_RESS_Pos) /**< (ADC_RESS) Last ADC conversion result Mask */ -#define ADC_RESS_RESS(value) (ADC_RESS_RESS_Msk & ((value) << ADC_RESS_RESS_Pos)) -#define ADC_RESS_Msk _U_(0xFFFF) /**< (ADC_RESS) Register Mask */ - - -/* -------- ADC_CALIB : (ADC Offset: 0x48) (R/W 16) Calibration -------- */ -#define ADC_CALIB_RESETVALUE _U_(0x00) /**< (ADC_CALIB) Calibration Reset Value */ - -#define ADC_CALIB_BIASCOMP_Pos _U_(0) /**< (ADC_CALIB) Bias Comparator Scaling Position */ -#define ADC_CALIB_BIASCOMP_Msk (_U_(0x7) << ADC_CALIB_BIASCOMP_Pos) /**< (ADC_CALIB) Bias Comparator Scaling Mask */ -#define ADC_CALIB_BIASCOMP(value) (ADC_CALIB_BIASCOMP_Msk & ((value) << ADC_CALIB_BIASCOMP_Pos)) -#define ADC_CALIB_BIASR2R_Pos _U_(4) /**< (ADC_CALIB) Bias R2R Ampli scaling Position */ -#define ADC_CALIB_BIASR2R_Msk (_U_(0x7) << ADC_CALIB_BIASR2R_Pos) /**< (ADC_CALIB) Bias R2R Ampli scaling Mask */ -#define ADC_CALIB_BIASR2R(value) (ADC_CALIB_BIASR2R_Msk & ((value) << ADC_CALIB_BIASR2R_Pos)) -#define ADC_CALIB_BIASREFBUF_Pos _U_(8) /**< (ADC_CALIB) Bias Reference Buffer Scaling Position */ -#define ADC_CALIB_BIASREFBUF_Msk (_U_(0x7) << ADC_CALIB_BIASREFBUF_Pos) /**< (ADC_CALIB) Bias Reference Buffer Scaling Mask */ -#define ADC_CALIB_BIASREFBUF(value) (ADC_CALIB_BIASREFBUF_Msk & ((value) << ADC_CALIB_BIASREFBUF_Pos)) -#define ADC_CALIB_Msk _U_(0x0777) /**< (ADC_CALIB) Register Mask */ - - -/** \brief ADC register offsets definitions */ -#define ADC_CTRLA_REG_OFST (0x00) /**< (ADC_CTRLA) Control A Offset */ -#define ADC_EVCTRL_REG_OFST (0x02) /**< (ADC_EVCTRL) Event Control Offset */ -#define ADC_DBGCTRL_REG_OFST (0x03) /**< (ADC_DBGCTRL) Debug Control Offset */ -#define ADC_INPUTCTRL_REG_OFST (0x04) /**< (ADC_INPUTCTRL) Input Control Offset */ -#define ADC_CTRLB_REG_OFST (0x06) /**< (ADC_CTRLB) Control B Offset */ -#define ADC_REFCTRL_REG_OFST (0x08) /**< (ADC_REFCTRL) Reference Control Offset */ -#define ADC_AVGCTRL_REG_OFST (0x0A) /**< (ADC_AVGCTRL) Average Control Offset */ -#define ADC_SAMPCTRL_REG_OFST (0x0B) /**< (ADC_SAMPCTRL) Sample Time Control Offset */ -#define ADC_WINLT_REG_OFST (0x0C) /**< (ADC_WINLT) Window Monitor Lower Threshold Offset */ -#define ADC_WINUT_REG_OFST (0x0E) /**< (ADC_WINUT) Window Monitor Upper Threshold Offset */ -#define ADC_GAINCORR_REG_OFST (0x10) /**< (ADC_GAINCORR) Gain Correction Offset */ -#define ADC_OFFSETCORR_REG_OFST (0x12) /**< (ADC_OFFSETCORR) Offset Correction Offset */ -#define ADC_SWTRIG_REG_OFST (0x14) /**< (ADC_SWTRIG) Software Trigger Offset */ -#define ADC_INTENCLR_REG_OFST (0x2C) /**< (ADC_INTENCLR) Interrupt Enable Clear Offset */ -#define ADC_INTENSET_REG_OFST (0x2D) /**< (ADC_INTENSET) Interrupt Enable Set Offset */ -#define ADC_INTFLAG_REG_OFST (0x2E) /**< (ADC_INTFLAG) Interrupt Flag Status and Clear Offset */ -#define ADC_STATUS_REG_OFST (0x2F) /**< (ADC_STATUS) Status Offset */ -#define ADC_SYNCBUSY_REG_OFST (0x30) /**< (ADC_SYNCBUSY) Synchronization Busy Offset */ -#define ADC_DSEQDATA_REG_OFST (0x34) /**< (ADC_DSEQDATA) DMA Sequencial Data Offset */ -#define ADC_DSEQCTRL_REG_OFST (0x38) /**< (ADC_DSEQCTRL) DMA Sequential Control Offset */ -#define ADC_DSEQSTAT_REG_OFST (0x3C) /**< (ADC_DSEQSTAT) DMA Sequencial Status Offset */ -#define ADC_RESULT_REG_OFST (0x40) /**< (ADC_RESULT) Result Conversion Value Offset */ -#define ADC_RESS_REG_OFST (0x44) /**< (ADC_RESS) Last Sample Result Offset */ -#define ADC_CALIB_REG_OFST (0x48) /**< (ADC_CALIB) Calibration Offset */ - -#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) -/** \brief ADC register API structure */ -typedef struct -{ /* Analog Digital Converter */ - __IO uint16_t ADC_CTRLA; /**< Offset: 0x00 (R/W 16) Control A */ - __IO uint8_t ADC_EVCTRL; /**< Offset: 0x02 (R/W 8) Event Control */ - __IO uint8_t ADC_DBGCTRL; /**< Offset: 0x03 (R/W 8) Debug Control */ - __IO uint16_t ADC_INPUTCTRL; /**< Offset: 0x04 (R/W 16) Input Control */ - __IO uint16_t ADC_CTRLB; /**< Offset: 0x06 (R/W 16) Control B */ - __IO uint8_t ADC_REFCTRL; /**< Offset: 0x08 (R/W 8) Reference Control */ - __I uint8_t Reserved1[0x01]; - __IO uint8_t ADC_AVGCTRL; /**< Offset: 0x0A (R/W 8) Average Control */ - __IO uint8_t ADC_SAMPCTRL; /**< Offset: 0x0B (R/W 8) Sample Time Control */ - __IO uint16_t ADC_WINLT; /**< Offset: 0x0C (R/W 16) Window Monitor Lower Threshold */ - __IO uint16_t ADC_WINUT; /**< Offset: 0x0E (R/W 16) Window Monitor Upper Threshold */ - __IO uint16_t ADC_GAINCORR; /**< Offset: 0x10 (R/W 16) Gain Correction */ - __IO uint16_t ADC_OFFSETCORR; /**< Offset: 0x12 (R/W 16) Offset Correction */ - __IO uint8_t ADC_SWTRIG; /**< Offset: 0x14 (R/W 8) Software Trigger */ - __I uint8_t Reserved2[0x17]; - __IO uint8_t ADC_INTENCLR; /**< Offset: 0x2C (R/W 8) Interrupt Enable Clear */ - __IO uint8_t ADC_INTENSET; /**< Offset: 0x2D (R/W 8) Interrupt Enable Set */ - __IO uint8_t ADC_INTFLAG; /**< Offset: 0x2E (R/W 8) Interrupt Flag Status and Clear */ - __I uint8_t ADC_STATUS; /**< Offset: 0x2F (R/ 8) Status */ - __I uint32_t ADC_SYNCBUSY; /**< Offset: 0x30 (R/ 32) Synchronization Busy */ - __O uint32_t ADC_DSEQDATA; /**< Offset: 0x34 ( /W 32) DMA Sequencial Data */ - __IO uint32_t ADC_DSEQCTRL; /**< Offset: 0x38 (R/W 32) DMA Sequential Control */ - __I uint32_t ADC_DSEQSTAT; /**< Offset: 0x3C (R/ 32) DMA Sequencial Status */ - __I uint16_t ADC_RESULT; /**< Offset: 0x40 (R/ 16) Result Conversion Value */ - __I uint8_t Reserved3[0x02]; - __I uint16_t ADC_RESS; /**< Offset: 0x44 (R/ 16) Last Sample Result */ - __I uint8_t Reserved4[0x02]; - __IO uint16_t ADC_CALIB; /**< Offset: 0x48 (R/W 16) Calibration */ -} adc_registers_t; - - -#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ -#endif /* _SAME54_ADC_COMPONENT_H_ */ +/** + * \file + * + * \brief Component description for ADC + * + * Copyright (c) 2019 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAME54_ADC_COMPONENT_ +#define _SAME54_ADC_COMPONENT_ + +/* ========================================================================== */ +/** SOFTWARE API DEFINITION FOR ADC */ +/* ========================================================================== */ +/** \addtogroup SAME54_ADC Analog Digital Converter */ +/*@{*/ + +#define ADC_U2500 +#define REV_ADC 0x100 + +/* -------- ADC_CTRLA : (ADC Offset: 0x00) (R/W 16) Control A -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t SWRST:1; /*!< bit: 0 Software Reset */ + uint16_t ENABLE:1; /*!< bit: 1 Enable */ + uint16_t :1; /*!< bit: 2 Reserved */ + uint16_t DUALSEL:2; /*!< bit: 3.. 4 Dual Mode Trigger Selection */ + uint16_t SLAVEEN:1; /*!< bit: 5 Slave Enable */ + uint16_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */ + uint16_t ONDEMAND:1; /*!< bit: 7 On Demand Control */ + uint16_t PRESCALER:3; /*!< bit: 8..10 Prescaler Configuration */ + uint16_t :4; /*!< bit: 11..14 Reserved */ + uint16_t R2R:1; /*!< bit: 15 Rail to Rail Operation Enable */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} ADC_CTRLA_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_CTRLA_OFFSET 0x00 /**< \brief (ADC_CTRLA offset) Control A */ +#define ADC_CTRLA_RESETVALUE _U_(0x0000) /**< \brief (ADC_CTRLA reset_value) Control A */ + +#define ADC_CTRLA_SWRST_Pos 0 /**< \brief (ADC_CTRLA) Software Reset */ +#define ADC_CTRLA_SWRST (_U_(0x1) << ADC_CTRLA_SWRST_Pos) +#define ADC_CTRLA_ENABLE_Pos 1 /**< \brief (ADC_CTRLA) Enable */ +#define ADC_CTRLA_ENABLE (_U_(0x1) << ADC_CTRLA_ENABLE_Pos) +#define ADC_CTRLA_DUALSEL_Pos 3 /**< \brief (ADC_CTRLA) Dual Mode Trigger Selection */ +#define ADC_CTRLA_DUALSEL_Msk (_U_(0x3) << ADC_CTRLA_DUALSEL_Pos) +#define ADC_CTRLA_DUALSEL(value) (ADC_CTRLA_DUALSEL_Msk & ((value) << ADC_CTRLA_DUALSEL_Pos)) +#define ADC_CTRLA_DUALSEL_BOTH_Val _U_(0x0) /**< \brief (ADC_CTRLA) Start event or software trigger will start a conversion on both ADCs */ +#define ADC_CTRLA_DUALSEL_INTERLEAVE_Val _U_(0x1) /**< \brief (ADC_CTRLA) START event or software trigger will alternatingly start a conversion on ADC0 and ADC1 */ +#define ADC_CTRLA_DUALSEL_BOTH (ADC_CTRLA_DUALSEL_BOTH_Val << ADC_CTRLA_DUALSEL_Pos) +#define ADC_CTRLA_DUALSEL_INTERLEAVE (ADC_CTRLA_DUALSEL_INTERLEAVE_Val << ADC_CTRLA_DUALSEL_Pos) +#define ADC_CTRLA_SLAVEEN_Pos 5 /**< \brief (ADC_CTRLA) Slave Enable */ +#define ADC_CTRLA_SLAVEEN (_U_(0x1) << ADC_CTRLA_SLAVEEN_Pos) +#define ADC_CTRLA_RUNSTDBY_Pos 6 /**< \brief (ADC_CTRLA) Run in Standby */ +#define ADC_CTRLA_RUNSTDBY (_U_(0x1) << ADC_CTRLA_RUNSTDBY_Pos) +#define ADC_CTRLA_ONDEMAND_Pos 7 /**< \brief (ADC_CTRLA) On Demand Control */ +#define ADC_CTRLA_ONDEMAND (_U_(0x1) << ADC_CTRLA_ONDEMAND_Pos) +#define ADC_CTRLA_PRESCALER_Pos 8 /**< \brief (ADC_CTRLA) Prescaler Configuration */ +#define ADC_CTRLA_PRESCALER_Msk (_U_(0x7) << ADC_CTRLA_PRESCALER_Pos) +#define ADC_CTRLA_PRESCALER(value) (ADC_CTRLA_PRESCALER_Msk & ((value) << ADC_CTRLA_PRESCALER_Pos)) +#define ADC_CTRLA_PRESCALER_DIV2_Val _U_(0x0) /**< \brief (ADC_CTRLA) Peripheral clock divided by 2 */ +#define ADC_CTRLA_PRESCALER_DIV4_Val _U_(0x1) /**< \brief (ADC_CTRLA) Peripheral clock divided by 4 */ +#define ADC_CTRLA_PRESCALER_DIV8_Val _U_(0x2) /**< \brief (ADC_CTRLA) Peripheral clock divided by 8 */ +#define ADC_CTRLA_PRESCALER_DIV16_Val _U_(0x3) /**< \brief (ADC_CTRLA) Peripheral clock divided by 16 */ +#define ADC_CTRLA_PRESCALER_DIV32_Val _U_(0x4) /**< \brief (ADC_CTRLA) Peripheral clock divided by 32 */ +#define ADC_CTRLA_PRESCALER_DIV64_Val _U_(0x5) /**< \brief (ADC_CTRLA) Peripheral clock divided by 64 */ +#define ADC_CTRLA_PRESCALER_DIV128_Val _U_(0x6) /**< \brief (ADC_CTRLA) Peripheral clock divided by 128 */ +#define ADC_CTRLA_PRESCALER_DIV256_Val _U_(0x7) /**< \brief (ADC_CTRLA) Peripheral clock divided by 256 */ +#define ADC_CTRLA_PRESCALER_DIV2 (ADC_CTRLA_PRESCALER_DIV2_Val << ADC_CTRLA_PRESCALER_Pos) +#define ADC_CTRLA_PRESCALER_DIV4 (ADC_CTRLA_PRESCALER_DIV4_Val << ADC_CTRLA_PRESCALER_Pos) +#define ADC_CTRLA_PRESCALER_DIV8 (ADC_CTRLA_PRESCALER_DIV8_Val << ADC_CTRLA_PRESCALER_Pos) +#define ADC_CTRLA_PRESCALER_DIV16 (ADC_CTRLA_PRESCALER_DIV16_Val << ADC_CTRLA_PRESCALER_Pos) +#define ADC_CTRLA_PRESCALER_DIV32 (ADC_CTRLA_PRESCALER_DIV32_Val << ADC_CTRLA_PRESCALER_Pos) +#define ADC_CTRLA_PRESCALER_DIV64 (ADC_CTRLA_PRESCALER_DIV64_Val << ADC_CTRLA_PRESCALER_Pos) +#define ADC_CTRLA_PRESCALER_DIV128 (ADC_CTRLA_PRESCALER_DIV128_Val << ADC_CTRLA_PRESCALER_Pos) +#define ADC_CTRLA_PRESCALER_DIV256 (ADC_CTRLA_PRESCALER_DIV256_Val << ADC_CTRLA_PRESCALER_Pos) +#define ADC_CTRLA_R2R_Pos 15 /**< \brief (ADC_CTRLA) Rail to Rail Operation Enable */ +#define ADC_CTRLA_R2R (_U_(0x1) << ADC_CTRLA_R2R_Pos) +#define ADC_CTRLA_MASK _U_(0x87FB) /**< \brief (ADC_CTRLA) MASK Register */ + +/* -------- ADC_EVCTRL : (ADC Offset: 0x02) (R/W 8) Event Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t FLUSHEI:1; /*!< bit: 0 Flush Event Input Enable */ + uint8_t STARTEI:1; /*!< bit: 1 Start Conversion Event Input Enable */ + uint8_t FLUSHINV:1; /*!< bit: 2 Flush Event Invert Enable */ + uint8_t STARTINV:1; /*!< bit: 3 Start Conversion Event Invert Enable */ + uint8_t RESRDYEO:1; /*!< bit: 4 Result Ready Event Out */ + uint8_t WINMONEO:1; /*!< bit: 5 Window Monitor Event Out */ + uint8_t :2; /*!< bit: 6.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} ADC_EVCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_EVCTRL_OFFSET 0x02 /**< \brief (ADC_EVCTRL offset) Event Control */ +#define ADC_EVCTRL_RESETVALUE _U_(0x00) /**< \brief (ADC_EVCTRL reset_value) Event Control */ + +#define ADC_EVCTRL_FLUSHEI_Pos 0 /**< \brief (ADC_EVCTRL) Flush Event Input Enable */ +#define ADC_EVCTRL_FLUSHEI (_U_(0x1) << ADC_EVCTRL_FLUSHEI_Pos) +#define ADC_EVCTRL_STARTEI_Pos 1 /**< \brief (ADC_EVCTRL) Start Conversion Event Input Enable */ +#define ADC_EVCTRL_STARTEI (_U_(0x1) << ADC_EVCTRL_STARTEI_Pos) +#define ADC_EVCTRL_FLUSHINV_Pos 2 /**< \brief (ADC_EVCTRL) Flush Event Invert Enable */ +#define ADC_EVCTRL_FLUSHINV (_U_(0x1) << ADC_EVCTRL_FLUSHINV_Pos) +#define ADC_EVCTRL_STARTINV_Pos 3 /**< \brief (ADC_EVCTRL) Start Conversion Event Invert Enable */ +#define ADC_EVCTRL_STARTINV (_U_(0x1) << ADC_EVCTRL_STARTINV_Pos) +#define ADC_EVCTRL_RESRDYEO_Pos 4 /**< \brief (ADC_EVCTRL) Result Ready Event Out */ +#define ADC_EVCTRL_RESRDYEO (_U_(0x1) << ADC_EVCTRL_RESRDYEO_Pos) +#define ADC_EVCTRL_WINMONEO_Pos 5 /**< \brief (ADC_EVCTRL) Window Monitor Event Out */ +#define ADC_EVCTRL_WINMONEO (_U_(0x1) << ADC_EVCTRL_WINMONEO_Pos) +#define ADC_EVCTRL_MASK _U_(0x3F) /**< \brief (ADC_EVCTRL) MASK Register */ + +/* -------- ADC_DBGCTRL : (ADC Offset: 0x03) (R/W 8) Debug Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t DBGRUN:1; /*!< bit: 0 Debug Run */ + uint8_t :7; /*!< bit: 1.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} ADC_DBGCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_DBGCTRL_OFFSET 0x03 /**< \brief (ADC_DBGCTRL offset) Debug Control */ +#define ADC_DBGCTRL_RESETVALUE _U_(0x00) /**< \brief (ADC_DBGCTRL reset_value) Debug Control */ + +#define ADC_DBGCTRL_DBGRUN_Pos 0 /**< \brief (ADC_DBGCTRL) Debug Run */ +#define ADC_DBGCTRL_DBGRUN (_U_(0x1) << ADC_DBGCTRL_DBGRUN_Pos) +#define ADC_DBGCTRL_MASK _U_(0x01) /**< \brief (ADC_DBGCTRL) MASK Register */ + +/* -------- ADC_INPUTCTRL : (ADC Offset: 0x04) (R/W 16) Input Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t MUXPOS:5; /*!< bit: 0.. 4 Positive Mux Input Selection */ + uint16_t :2; /*!< bit: 5.. 6 Reserved */ + uint16_t DIFFMODE:1; /*!< bit: 7 Differential Mode */ + uint16_t MUXNEG:5; /*!< bit: 8..12 Negative Mux Input Selection */ + uint16_t :2; /*!< bit: 13..14 Reserved */ + uint16_t DSEQSTOP:1; /*!< bit: 15 Stop DMA Sequencing */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} ADC_INPUTCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_INPUTCTRL_OFFSET 0x04 /**< \brief (ADC_INPUTCTRL offset) Input Control */ +#define ADC_INPUTCTRL_RESETVALUE _U_(0x0000) /**< \brief (ADC_INPUTCTRL reset_value) Input Control */ + +#define ADC_INPUTCTRL_MUXPOS_Pos 0 /**< \brief (ADC_INPUTCTRL) Positive Mux Input Selection */ +#define ADC_INPUTCTRL_MUXPOS_Msk (_U_(0x1F) << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS(value) (ADC_INPUTCTRL_MUXPOS_Msk & ((value) << ADC_INPUTCTRL_MUXPOS_Pos)) +#define ADC_INPUTCTRL_MUXPOS_AIN0_Val _U_(0x0) /**< \brief (ADC_INPUTCTRL) ADC AIN0 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN1_Val _U_(0x1) /**< \brief (ADC_INPUTCTRL) ADC AIN1 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN2_Val _U_(0x2) /**< \brief (ADC_INPUTCTRL) ADC AIN2 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN3_Val _U_(0x3) /**< \brief (ADC_INPUTCTRL) ADC AIN3 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN4_Val _U_(0x4) /**< \brief (ADC_INPUTCTRL) ADC AIN4 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN5_Val _U_(0x5) /**< \brief (ADC_INPUTCTRL) ADC AIN5 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN6_Val _U_(0x6) /**< \brief (ADC_INPUTCTRL) ADC AIN6 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN7_Val _U_(0x7) /**< \brief (ADC_INPUTCTRL) ADC AIN7 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN8_Val _U_(0x8) /**< \brief (ADC_INPUTCTRL) ADC AIN8 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN9_Val _U_(0x9) /**< \brief (ADC_INPUTCTRL) ADC AIN9 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN10_Val _U_(0xA) /**< \brief (ADC_INPUTCTRL) ADC AIN10 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN11_Val _U_(0xB) /**< \brief (ADC_INPUTCTRL) ADC AIN11 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN12_Val _U_(0xC) /**< \brief (ADC_INPUTCTRL) ADC AIN12 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN13_Val _U_(0xD) /**< \brief (ADC_INPUTCTRL) ADC AIN13 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN14_Val _U_(0xE) /**< \brief (ADC_INPUTCTRL) ADC AIN14 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN15_Val _U_(0xF) /**< \brief (ADC_INPUTCTRL) ADC AIN15 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN16_Val _U_(0x10) /**< \brief (ADC_INPUTCTRL) ADC AIN16 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN17_Val _U_(0x11) /**< \brief (ADC_INPUTCTRL) ADC AIN17 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN18_Val _U_(0x12) /**< \brief (ADC_INPUTCTRL) ADC AIN18 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN19_Val _U_(0x13) /**< \brief (ADC_INPUTCTRL) ADC AIN19 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN20_Val _U_(0x14) /**< \brief (ADC_INPUTCTRL) ADC AIN20 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN21_Val _U_(0x15) /**< \brief (ADC_INPUTCTRL) ADC AIN21 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN22_Val _U_(0x16) /**< \brief (ADC_INPUTCTRL) ADC AIN22 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN23_Val _U_(0x17) /**< \brief (ADC_INPUTCTRL) ADC AIN23 Pin */ +#define ADC_INPUTCTRL_MUXPOS_SCALEDCOREVCC_Val _U_(0x18) /**< \brief (ADC_INPUTCTRL) 1/4 Scaled Core Supply */ +#define ADC_INPUTCTRL_MUXPOS_SCALEDVBAT_Val _U_(0x19) /**< \brief (ADC_INPUTCTRL) 1/4 Scaled VBAT Supply */ +#define ADC_INPUTCTRL_MUXPOS_SCALEDIOVCC_Val _U_(0x1A) /**< \brief (ADC_INPUTCTRL) 1/4 Scaled I/O Supply */ +#define ADC_INPUTCTRL_MUXPOS_BANDGAP_Val _U_(0x1B) /**< \brief (ADC_INPUTCTRL) Bandgap Voltage */ +#define ADC_INPUTCTRL_MUXPOS_PTAT_Val _U_(0x1C) /**< \brief (ADC_INPUTCTRL) Temperature Sensor */ +#define ADC_INPUTCTRL_MUXPOS_CTAT_Val _U_(0x1D) /**< \brief (ADC_INPUTCTRL) Temperature Sensor */ +#define ADC_INPUTCTRL_MUXPOS_DAC_Val _U_(0x1E) /**< \brief (ADC_INPUTCTRL) DAC Output */ +#define ADC_INPUTCTRL_MUXPOS_PTC_Val _U_(0x1F) /**< \brief (ADC_INPUTCTRL) PTC output (only on ADC0) */ +#define ADC_INPUTCTRL_MUXPOS_AIN0 (ADC_INPUTCTRL_MUXPOS_AIN0_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_AIN1 (ADC_INPUTCTRL_MUXPOS_AIN1_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_AIN2 (ADC_INPUTCTRL_MUXPOS_AIN2_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_AIN3 (ADC_INPUTCTRL_MUXPOS_AIN3_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_AIN4 (ADC_INPUTCTRL_MUXPOS_AIN4_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_AIN5 (ADC_INPUTCTRL_MUXPOS_AIN5_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_AIN6 (ADC_INPUTCTRL_MUXPOS_AIN6_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_AIN7 (ADC_INPUTCTRL_MUXPOS_AIN7_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_AIN8 (ADC_INPUTCTRL_MUXPOS_AIN8_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_AIN9 (ADC_INPUTCTRL_MUXPOS_AIN9_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_AIN10 (ADC_INPUTCTRL_MUXPOS_AIN10_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_AIN11 (ADC_INPUTCTRL_MUXPOS_AIN11_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_AIN12 (ADC_INPUTCTRL_MUXPOS_AIN12_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_AIN13 (ADC_INPUTCTRL_MUXPOS_AIN13_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_AIN14 (ADC_INPUTCTRL_MUXPOS_AIN14_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_AIN15 (ADC_INPUTCTRL_MUXPOS_AIN15_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_AIN16 (ADC_INPUTCTRL_MUXPOS_AIN16_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_AIN17 (ADC_INPUTCTRL_MUXPOS_AIN17_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_AIN18 (ADC_INPUTCTRL_MUXPOS_AIN18_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_AIN19 (ADC_INPUTCTRL_MUXPOS_AIN19_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_AIN20 (ADC_INPUTCTRL_MUXPOS_AIN20_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_AIN21 (ADC_INPUTCTRL_MUXPOS_AIN21_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_AIN22 (ADC_INPUTCTRL_MUXPOS_AIN22_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_AIN23 (ADC_INPUTCTRL_MUXPOS_AIN23_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_SCALEDCOREVCC (ADC_INPUTCTRL_MUXPOS_SCALEDCOREVCC_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_SCALEDVBAT (ADC_INPUTCTRL_MUXPOS_SCALEDVBAT_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_SCALEDIOVCC (ADC_INPUTCTRL_MUXPOS_SCALEDIOVCC_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_BANDGAP (ADC_INPUTCTRL_MUXPOS_BANDGAP_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_PTAT (ADC_INPUTCTRL_MUXPOS_PTAT_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_CTAT (ADC_INPUTCTRL_MUXPOS_CTAT_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_DAC (ADC_INPUTCTRL_MUXPOS_DAC_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_PTC (ADC_INPUTCTRL_MUXPOS_PTC_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_DIFFMODE_Pos 7 /**< \brief (ADC_INPUTCTRL) Differential Mode */ +#define ADC_INPUTCTRL_DIFFMODE (_U_(0x1) << ADC_INPUTCTRL_DIFFMODE_Pos) +#define ADC_INPUTCTRL_MUXNEG_Pos 8 /**< \brief (ADC_INPUTCTRL) Negative Mux Input Selection */ +#define ADC_INPUTCTRL_MUXNEG_Msk (_U_(0x1F) << ADC_INPUTCTRL_MUXNEG_Pos) +#define ADC_INPUTCTRL_MUXNEG(value) (ADC_INPUTCTRL_MUXNEG_Msk & ((value) << ADC_INPUTCTRL_MUXNEG_Pos)) +#define ADC_INPUTCTRL_MUXNEG_AIN0_Val _U_(0x0) /**< \brief (ADC_INPUTCTRL) ADC AIN0 Pin */ +#define ADC_INPUTCTRL_MUXNEG_AIN1_Val _U_(0x1) /**< \brief (ADC_INPUTCTRL) ADC AIN1 Pin */ +#define ADC_INPUTCTRL_MUXNEG_AIN2_Val _U_(0x2) /**< \brief (ADC_INPUTCTRL) ADC AIN2 Pin */ +#define ADC_INPUTCTRL_MUXNEG_AIN3_Val _U_(0x3) /**< \brief (ADC_INPUTCTRL) ADC AIN3 Pin */ +#define ADC_INPUTCTRL_MUXNEG_AIN4_Val _U_(0x4) /**< \brief (ADC_INPUTCTRL) ADC AIN4 Pin */ +#define ADC_INPUTCTRL_MUXNEG_AIN5_Val _U_(0x5) /**< \brief (ADC_INPUTCTRL) ADC AIN5 Pin */ +#define ADC_INPUTCTRL_MUXNEG_AIN6_Val _U_(0x6) /**< \brief (ADC_INPUTCTRL) ADC AIN6 Pin */ +#define ADC_INPUTCTRL_MUXNEG_AIN7_Val _U_(0x7) /**< \brief (ADC_INPUTCTRL) ADC AIN7 Pin */ +#define ADC_INPUTCTRL_MUXNEG_GND_Val _U_(0x18) /**< \brief (ADC_INPUTCTRL) Internal Ground */ +#define ADC_INPUTCTRL_MUXNEG_AIN0 (ADC_INPUTCTRL_MUXNEG_AIN0_Val << ADC_INPUTCTRL_MUXNEG_Pos) +#define ADC_INPUTCTRL_MUXNEG_AIN1 (ADC_INPUTCTRL_MUXNEG_AIN1_Val << ADC_INPUTCTRL_MUXNEG_Pos) +#define ADC_INPUTCTRL_MUXNEG_AIN2 (ADC_INPUTCTRL_MUXNEG_AIN2_Val << ADC_INPUTCTRL_MUXNEG_Pos) +#define ADC_INPUTCTRL_MUXNEG_AIN3 (ADC_INPUTCTRL_MUXNEG_AIN3_Val << ADC_INPUTCTRL_MUXNEG_Pos) +#define ADC_INPUTCTRL_MUXNEG_AIN4 (ADC_INPUTCTRL_MUXNEG_AIN4_Val << ADC_INPUTCTRL_MUXNEG_Pos) +#define ADC_INPUTCTRL_MUXNEG_AIN5 (ADC_INPUTCTRL_MUXNEG_AIN5_Val << ADC_INPUTCTRL_MUXNEG_Pos) +#define ADC_INPUTCTRL_MUXNEG_AIN6 (ADC_INPUTCTRL_MUXNEG_AIN6_Val << ADC_INPUTCTRL_MUXNEG_Pos) +#define ADC_INPUTCTRL_MUXNEG_AIN7 (ADC_INPUTCTRL_MUXNEG_AIN7_Val << ADC_INPUTCTRL_MUXNEG_Pos) +#define ADC_INPUTCTRL_MUXNEG_GND (ADC_INPUTCTRL_MUXNEG_GND_Val << ADC_INPUTCTRL_MUXNEG_Pos) +#define ADC_INPUTCTRL_DSEQSTOP_Pos 15 /**< \brief (ADC_INPUTCTRL) Stop DMA Sequencing */ +#define ADC_INPUTCTRL_DSEQSTOP (_U_(0x1) << ADC_INPUTCTRL_DSEQSTOP_Pos) +#define ADC_INPUTCTRL_MASK _U_(0x9F9F) /**< \brief (ADC_INPUTCTRL) MASK Register */ + +/* -------- ADC_CTRLB : (ADC Offset: 0x06) (R/W 16) Control B -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t LEFTADJ:1; /*!< bit: 0 Left-Adjusted Result */ + uint16_t FREERUN:1; /*!< bit: 1 Free Running Mode */ + uint16_t CORREN:1; /*!< bit: 2 Digital Correction Logic Enable */ + uint16_t RESSEL:2; /*!< bit: 3.. 4 Conversion Result Resolution */ + uint16_t :3; /*!< bit: 5.. 7 Reserved */ + uint16_t WINMODE:3; /*!< bit: 8..10 Window Monitor Mode */ + uint16_t WINSS:1; /*!< bit: 11 Window Single Sample */ + uint16_t :4; /*!< bit: 12..15 Reserved */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} ADC_CTRLB_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_CTRLB_OFFSET 0x06 /**< \brief (ADC_CTRLB offset) Control B */ +#define ADC_CTRLB_RESETVALUE _U_(0x0000) /**< \brief (ADC_CTRLB reset_value) Control B */ + +#define ADC_CTRLB_LEFTADJ_Pos 0 /**< \brief (ADC_CTRLB) Left-Adjusted Result */ +#define ADC_CTRLB_LEFTADJ (_U_(0x1) << ADC_CTRLB_LEFTADJ_Pos) +#define ADC_CTRLB_FREERUN_Pos 1 /**< \brief (ADC_CTRLB) Free Running Mode */ +#define ADC_CTRLB_FREERUN (_U_(0x1) << ADC_CTRLB_FREERUN_Pos) +#define ADC_CTRLB_CORREN_Pos 2 /**< \brief (ADC_CTRLB) Digital Correction Logic Enable */ +#define ADC_CTRLB_CORREN (_U_(0x1) << ADC_CTRLB_CORREN_Pos) +#define ADC_CTRLB_RESSEL_Pos 3 /**< \brief (ADC_CTRLB) Conversion Result Resolution */ +#define ADC_CTRLB_RESSEL_Msk (_U_(0x3) << ADC_CTRLB_RESSEL_Pos) +#define ADC_CTRLB_RESSEL(value) (ADC_CTRLB_RESSEL_Msk & ((value) << ADC_CTRLB_RESSEL_Pos)) +#define ADC_CTRLB_RESSEL_12BIT_Val _U_(0x0) /**< \brief (ADC_CTRLB) 12-bit result */ +#define ADC_CTRLB_RESSEL_16BIT_Val _U_(0x1) /**< \brief (ADC_CTRLB) For averaging mode output */ +#define ADC_CTRLB_RESSEL_10BIT_Val _U_(0x2) /**< \brief (ADC_CTRLB) 10-bit result */ +#define ADC_CTRLB_RESSEL_8BIT_Val _U_(0x3) /**< \brief (ADC_CTRLB) 8-bit result */ +#define ADC_CTRLB_RESSEL_12BIT (ADC_CTRLB_RESSEL_12BIT_Val << ADC_CTRLB_RESSEL_Pos) +#define ADC_CTRLB_RESSEL_16BIT (ADC_CTRLB_RESSEL_16BIT_Val << ADC_CTRLB_RESSEL_Pos) +#define ADC_CTRLB_RESSEL_10BIT (ADC_CTRLB_RESSEL_10BIT_Val << ADC_CTRLB_RESSEL_Pos) +#define ADC_CTRLB_RESSEL_8BIT (ADC_CTRLB_RESSEL_8BIT_Val << ADC_CTRLB_RESSEL_Pos) +#define ADC_CTRLB_WINMODE_Pos 8 /**< \brief (ADC_CTRLB) Window Monitor Mode */ +#define ADC_CTRLB_WINMODE_Msk (_U_(0x7) << ADC_CTRLB_WINMODE_Pos) +#define ADC_CTRLB_WINMODE(value) (ADC_CTRLB_WINMODE_Msk & ((value) << ADC_CTRLB_WINMODE_Pos)) +#define ADC_CTRLB_WINMODE_DISABLE_Val _U_(0x0) /**< \brief (ADC_CTRLB) No window mode (default) */ +#define ADC_CTRLB_WINMODE_MODE1_Val _U_(0x1) /**< \brief (ADC_CTRLB) RESULT > WINLT */ +#define ADC_CTRLB_WINMODE_MODE2_Val _U_(0x2) /**< \brief (ADC_CTRLB) RESULT < WINUT */ +#define ADC_CTRLB_WINMODE_MODE3_Val _U_(0x3) /**< \brief (ADC_CTRLB) WINLT < RESULT < WINUT */ +#define ADC_CTRLB_WINMODE_MODE4_Val _U_(0x4) /**< \brief (ADC_CTRLB) !(WINLT < RESULT < WINUT) */ +#define ADC_CTRLB_WINMODE_DISABLE (ADC_CTRLB_WINMODE_DISABLE_Val << ADC_CTRLB_WINMODE_Pos) +#define ADC_CTRLB_WINMODE_MODE1 (ADC_CTRLB_WINMODE_MODE1_Val << ADC_CTRLB_WINMODE_Pos) +#define ADC_CTRLB_WINMODE_MODE2 (ADC_CTRLB_WINMODE_MODE2_Val << ADC_CTRLB_WINMODE_Pos) +#define ADC_CTRLB_WINMODE_MODE3 (ADC_CTRLB_WINMODE_MODE3_Val << ADC_CTRLB_WINMODE_Pos) +#define ADC_CTRLB_WINMODE_MODE4 (ADC_CTRLB_WINMODE_MODE4_Val << ADC_CTRLB_WINMODE_Pos) +#define ADC_CTRLB_WINSS_Pos 11 /**< \brief (ADC_CTRLB) Window Single Sample */ +#define ADC_CTRLB_WINSS (_U_(0x1) << ADC_CTRLB_WINSS_Pos) +#define ADC_CTRLB_MASK _U_(0x0F1F) /**< \brief (ADC_CTRLB) MASK Register */ + +/* -------- ADC_REFCTRL : (ADC Offset: 0x08) (R/W 8) Reference Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t REFSEL:4; /*!< bit: 0.. 3 Reference Selection */ + uint8_t :3; /*!< bit: 4.. 6 Reserved */ + uint8_t REFCOMP:1; /*!< bit: 7 Reference Buffer Offset Compensation Enable */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} ADC_REFCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_REFCTRL_OFFSET 0x08 /**< \brief (ADC_REFCTRL offset) Reference Control */ +#define ADC_REFCTRL_RESETVALUE _U_(0x00) /**< \brief (ADC_REFCTRL reset_value) Reference Control */ + +#define ADC_REFCTRL_REFSEL_Pos 0 /**< \brief (ADC_REFCTRL) Reference Selection */ +#define ADC_REFCTRL_REFSEL_Msk (_U_(0xF) << ADC_REFCTRL_REFSEL_Pos) +#define ADC_REFCTRL_REFSEL(value) (ADC_REFCTRL_REFSEL_Msk & ((value) << ADC_REFCTRL_REFSEL_Pos)) +#define ADC_REFCTRL_REFSEL_INTREF_Val _U_(0x0) /**< \brief (ADC_REFCTRL) Internal Bandgap Reference */ +#define ADC_REFCTRL_REFSEL_INTVCC0_Val _U_(0x2) /**< \brief (ADC_REFCTRL) 1/2 VDDANA */ +#define ADC_REFCTRL_REFSEL_INTVCC1_Val _U_(0x3) /**< \brief (ADC_REFCTRL) VDDANA */ +#define ADC_REFCTRL_REFSEL_AREFA_Val _U_(0x4) /**< \brief (ADC_REFCTRL) External Reference */ +#define ADC_REFCTRL_REFSEL_AREFB_Val _U_(0x5) /**< \brief (ADC_REFCTRL) External Reference */ +#define ADC_REFCTRL_REFSEL_AREFC_Val _U_(0x6) /**< \brief (ADC_REFCTRL) External Reference (only on ADC1) */ +#define ADC_REFCTRL_REFSEL_INTREF (ADC_REFCTRL_REFSEL_INTREF_Val << ADC_REFCTRL_REFSEL_Pos) +#define ADC_REFCTRL_REFSEL_INTVCC0 (ADC_REFCTRL_REFSEL_INTVCC0_Val << ADC_REFCTRL_REFSEL_Pos) +#define ADC_REFCTRL_REFSEL_INTVCC1 (ADC_REFCTRL_REFSEL_INTVCC1_Val << ADC_REFCTRL_REFSEL_Pos) +#define ADC_REFCTRL_REFSEL_AREFA (ADC_REFCTRL_REFSEL_AREFA_Val << ADC_REFCTRL_REFSEL_Pos) +#define ADC_REFCTRL_REFSEL_AREFB (ADC_REFCTRL_REFSEL_AREFB_Val << ADC_REFCTRL_REFSEL_Pos) +#define ADC_REFCTRL_REFSEL_AREFC (ADC_REFCTRL_REFSEL_AREFC_Val << ADC_REFCTRL_REFSEL_Pos) +#define ADC_REFCTRL_REFCOMP_Pos 7 /**< \brief (ADC_REFCTRL) Reference Buffer Offset Compensation Enable */ +#define ADC_REFCTRL_REFCOMP (_U_(0x1) << ADC_REFCTRL_REFCOMP_Pos) +#define ADC_REFCTRL_MASK _U_(0x8F) /**< \brief (ADC_REFCTRL) MASK Register */ + +/* -------- ADC_AVGCTRL : (ADC Offset: 0x0A) (R/W 8) Average Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t SAMPLENUM:4; /*!< bit: 0.. 3 Number of Samples to be Collected */ + uint8_t ADJRES:3; /*!< bit: 4.. 6 Adjusting Result / Division Coefficient */ + uint8_t :1; /*!< bit: 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} ADC_AVGCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_AVGCTRL_OFFSET 0x0A /**< \brief (ADC_AVGCTRL offset) Average Control */ +#define ADC_AVGCTRL_RESETVALUE _U_(0x00) /**< \brief (ADC_AVGCTRL reset_value) Average Control */ + +#define ADC_AVGCTRL_SAMPLENUM_Pos 0 /**< \brief (ADC_AVGCTRL) Number of Samples to be Collected */ +#define ADC_AVGCTRL_SAMPLENUM_Msk (_U_(0xF) << ADC_AVGCTRL_SAMPLENUM_Pos) +#define ADC_AVGCTRL_SAMPLENUM(value) (ADC_AVGCTRL_SAMPLENUM_Msk & ((value) << ADC_AVGCTRL_SAMPLENUM_Pos)) +#define ADC_AVGCTRL_SAMPLENUM_1_Val _U_(0x0) /**< \brief (ADC_AVGCTRL) 1 sample */ +#define ADC_AVGCTRL_SAMPLENUM_2_Val _U_(0x1) /**< \brief (ADC_AVGCTRL) 2 samples */ +#define ADC_AVGCTRL_SAMPLENUM_4_Val _U_(0x2) /**< \brief (ADC_AVGCTRL) 4 samples */ +#define ADC_AVGCTRL_SAMPLENUM_8_Val _U_(0x3) /**< \brief (ADC_AVGCTRL) 8 samples */ +#define ADC_AVGCTRL_SAMPLENUM_16_Val _U_(0x4) /**< \brief (ADC_AVGCTRL) 16 samples */ +#define ADC_AVGCTRL_SAMPLENUM_32_Val _U_(0x5) /**< \brief (ADC_AVGCTRL) 32 samples */ +#define ADC_AVGCTRL_SAMPLENUM_64_Val _U_(0x6) /**< \brief (ADC_AVGCTRL) 64 samples */ +#define ADC_AVGCTRL_SAMPLENUM_128_Val _U_(0x7) /**< \brief (ADC_AVGCTRL) 128 samples */ +#define ADC_AVGCTRL_SAMPLENUM_256_Val _U_(0x8) /**< \brief (ADC_AVGCTRL) 256 samples */ +#define ADC_AVGCTRL_SAMPLENUM_512_Val _U_(0x9) /**< \brief (ADC_AVGCTRL) 512 samples */ +#define ADC_AVGCTRL_SAMPLENUM_1024_Val _U_(0xA) /**< \brief (ADC_AVGCTRL) 1024 samples */ +#define ADC_AVGCTRL_SAMPLENUM_1 (ADC_AVGCTRL_SAMPLENUM_1_Val << ADC_AVGCTRL_SAMPLENUM_Pos) +#define ADC_AVGCTRL_SAMPLENUM_2 (ADC_AVGCTRL_SAMPLENUM_2_Val << ADC_AVGCTRL_SAMPLENUM_Pos) +#define ADC_AVGCTRL_SAMPLENUM_4 (ADC_AVGCTRL_SAMPLENUM_4_Val << ADC_AVGCTRL_SAMPLENUM_Pos) +#define ADC_AVGCTRL_SAMPLENUM_8 (ADC_AVGCTRL_SAMPLENUM_8_Val << ADC_AVGCTRL_SAMPLENUM_Pos) +#define ADC_AVGCTRL_SAMPLENUM_16 (ADC_AVGCTRL_SAMPLENUM_16_Val << ADC_AVGCTRL_SAMPLENUM_Pos) +#define ADC_AVGCTRL_SAMPLENUM_32 (ADC_AVGCTRL_SAMPLENUM_32_Val << ADC_AVGCTRL_SAMPLENUM_Pos) +#define ADC_AVGCTRL_SAMPLENUM_64 (ADC_AVGCTRL_SAMPLENUM_64_Val << ADC_AVGCTRL_SAMPLENUM_Pos) +#define ADC_AVGCTRL_SAMPLENUM_128 (ADC_AVGCTRL_SAMPLENUM_128_Val << ADC_AVGCTRL_SAMPLENUM_Pos) +#define ADC_AVGCTRL_SAMPLENUM_256 (ADC_AVGCTRL_SAMPLENUM_256_Val << ADC_AVGCTRL_SAMPLENUM_Pos) +#define ADC_AVGCTRL_SAMPLENUM_512 (ADC_AVGCTRL_SAMPLENUM_512_Val << ADC_AVGCTRL_SAMPLENUM_Pos) +#define ADC_AVGCTRL_SAMPLENUM_1024 (ADC_AVGCTRL_SAMPLENUM_1024_Val << ADC_AVGCTRL_SAMPLENUM_Pos) +#define ADC_AVGCTRL_ADJRES_Pos 4 /**< \brief (ADC_AVGCTRL) Adjusting Result / Division Coefficient */ +#define ADC_AVGCTRL_ADJRES_Msk (_U_(0x7) << ADC_AVGCTRL_ADJRES_Pos) +#define ADC_AVGCTRL_ADJRES(value) (ADC_AVGCTRL_ADJRES_Msk & ((value) << ADC_AVGCTRL_ADJRES_Pos)) +#define ADC_AVGCTRL_MASK _U_(0x7F) /**< \brief (ADC_AVGCTRL) MASK Register */ + +/* -------- ADC_SAMPCTRL : (ADC Offset: 0x0B) (R/W 8) Sample Time Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t SAMPLEN:6; /*!< bit: 0.. 5 Sampling Time Length */ + uint8_t :1; /*!< bit: 6 Reserved */ + uint8_t OFFCOMP:1; /*!< bit: 7 Comparator Offset Compensation Enable */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} ADC_SAMPCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_SAMPCTRL_OFFSET 0x0B /**< \brief (ADC_SAMPCTRL offset) Sample Time Control */ +#define ADC_SAMPCTRL_RESETVALUE _U_(0x00) /**< \brief (ADC_SAMPCTRL reset_value) Sample Time Control */ + +#define ADC_SAMPCTRL_SAMPLEN_Pos 0 /**< \brief (ADC_SAMPCTRL) Sampling Time Length */ +#define ADC_SAMPCTRL_SAMPLEN_Msk (_U_(0x3F) << ADC_SAMPCTRL_SAMPLEN_Pos) +#define ADC_SAMPCTRL_SAMPLEN(value) (ADC_SAMPCTRL_SAMPLEN_Msk & ((value) << ADC_SAMPCTRL_SAMPLEN_Pos)) +#define ADC_SAMPCTRL_OFFCOMP_Pos 7 /**< \brief (ADC_SAMPCTRL) Comparator Offset Compensation Enable */ +#define ADC_SAMPCTRL_OFFCOMP (_U_(0x1) << ADC_SAMPCTRL_OFFCOMP_Pos) +#define ADC_SAMPCTRL_MASK _U_(0xBF) /**< \brief (ADC_SAMPCTRL) MASK Register */ + +/* -------- ADC_WINLT : (ADC Offset: 0x0C) (R/W 16) Window Monitor Lower Threshold -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t WINLT:16; /*!< bit: 0..15 Window Lower Threshold */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} ADC_WINLT_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_WINLT_OFFSET 0x0C /**< \brief (ADC_WINLT offset) Window Monitor Lower Threshold */ +#define ADC_WINLT_RESETVALUE _U_(0x0000) /**< \brief (ADC_WINLT reset_value) Window Monitor Lower Threshold */ + +#define ADC_WINLT_WINLT_Pos 0 /**< \brief (ADC_WINLT) Window Lower Threshold */ +#define ADC_WINLT_WINLT_Msk (_U_(0xFFFF) << ADC_WINLT_WINLT_Pos) +#define ADC_WINLT_WINLT(value) (ADC_WINLT_WINLT_Msk & ((value) << ADC_WINLT_WINLT_Pos)) +#define ADC_WINLT_MASK _U_(0xFFFF) /**< \brief (ADC_WINLT) MASK Register */ + +/* -------- ADC_WINUT : (ADC Offset: 0x0E) (R/W 16) Window Monitor Upper Threshold -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t WINUT:16; /*!< bit: 0..15 Window Upper Threshold */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} ADC_WINUT_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_WINUT_OFFSET 0x0E /**< \brief (ADC_WINUT offset) Window Monitor Upper Threshold */ +#define ADC_WINUT_RESETVALUE _U_(0x0000) /**< \brief (ADC_WINUT reset_value) Window Monitor Upper Threshold */ + +#define ADC_WINUT_WINUT_Pos 0 /**< \brief (ADC_WINUT) Window Upper Threshold */ +#define ADC_WINUT_WINUT_Msk (_U_(0xFFFF) << ADC_WINUT_WINUT_Pos) +#define ADC_WINUT_WINUT(value) (ADC_WINUT_WINUT_Msk & ((value) << ADC_WINUT_WINUT_Pos)) +#define ADC_WINUT_MASK _U_(0xFFFF) /**< \brief (ADC_WINUT) MASK Register */ + +/* -------- ADC_GAINCORR : (ADC Offset: 0x10) (R/W 16) Gain Correction -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t GAINCORR:12; /*!< bit: 0..11 Gain Correction Value */ + uint16_t :4; /*!< bit: 12..15 Reserved */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} ADC_GAINCORR_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_GAINCORR_OFFSET 0x10 /**< \brief (ADC_GAINCORR offset) Gain Correction */ +#define ADC_GAINCORR_RESETVALUE _U_(0x0000) /**< \brief (ADC_GAINCORR reset_value) Gain Correction */ + +#define ADC_GAINCORR_GAINCORR_Pos 0 /**< \brief (ADC_GAINCORR) Gain Correction Value */ +#define ADC_GAINCORR_GAINCORR_Msk (_U_(0xFFF) << ADC_GAINCORR_GAINCORR_Pos) +#define ADC_GAINCORR_GAINCORR(value) (ADC_GAINCORR_GAINCORR_Msk & ((value) << ADC_GAINCORR_GAINCORR_Pos)) +#define ADC_GAINCORR_MASK _U_(0x0FFF) /**< \brief (ADC_GAINCORR) MASK Register */ + +/* -------- ADC_OFFSETCORR : (ADC Offset: 0x12) (R/W 16) Offset Correction -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t OFFSETCORR:12; /*!< bit: 0..11 Offset Correction Value */ + uint16_t :4; /*!< bit: 12..15 Reserved */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} ADC_OFFSETCORR_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_OFFSETCORR_OFFSET 0x12 /**< \brief (ADC_OFFSETCORR offset) Offset Correction */ +#define ADC_OFFSETCORR_RESETVALUE _U_(0x0000) /**< \brief (ADC_OFFSETCORR reset_value) Offset Correction */ + +#define ADC_OFFSETCORR_OFFSETCORR_Pos 0 /**< \brief (ADC_OFFSETCORR) Offset Correction Value */ +#define ADC_OFFSETCORR_OFFSETCORR_Msk (_U_(0xFFF) << ADC_OFFSETCORR_OFFSETCORR_Pos) +#define ADC_OFFSETCORR_OFFSETCORR(value) (ADC_OFFSETCORR_OFFSETCORR_Msk & ((value) << ADC_OFFSETCORR_OFFSETCORR_Pos)) +#define ADC_OFFSETCORR_MASK _U_(0x0FFF) /**< \brief (ADC_OFFSETCORR) MASK Register */ + +/* -------- ADC_SWTRIG : (ADC Offset: 0x14) (R/W 8) Software Trigger -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t FLUSH:1; /*!< bit: 0 ADC Conversion Flush */ + uint8_t START:1; /*!< bit: 1 Start ADC Conversion */ + uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} ADC_SWTRIG_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_SWTRIG_OFFSET 0x14 /**< \brief (ADC_SWTRIG offset) Software Trigger */ +#define ADC_SWTRIG_RESETVALUE _U_(0x00) /**< \brief (ADC_SWTRIG reset_value) Software Trigger */ + +#define ADC_SWTRIG_FLUSH_Pos 0 /**< \brief (ADC_SWTRIG) ADC Conversion Flush */ +#define ADC_SWTRIG_FLUSH (_U_(0x1) << ADC_SWTRIG_FLUSH_Pos) +#define ADC_SWTRIG_START_Pos 1 /**< \brief (ADC_SWTRIG) Start ADC Conversion */ +#define ADC_SWTRIG_START (_U_(0x1) << ADC_SWTRIG_START_Pos) +#define ADC_SWTRIG_MASK _U_(0x03) /**< \brief (ADC_SWTRIG) MASK Register */ + +/* -------- ADC_INTENCLR : (ADC Offset: 0x2C) (R/W 8) Interrupt Enable Clear -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t RESRDY:1; /*!< bit: 0 Result Ready Interrupt Disable */ + uint8_t OVERRUN:1; /*!< bit: 1 Overrun Interrupt Disable */ + uint8_t WINMON:1; /*!< bit: 2 Window Monitor Interrupt Disable */ + uint8_t :5; /*!< bit: 3.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} ADC_INTENCLR_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_INTENCLR_OFFSET 0x2C /**< \brief (ADC_INTENCLR offset) Interrupt Enable Clear */ +#define ADC_INTENCLR_RESETVALUE _U_(0x00) /**< \brief (ADC_INTENCLR reset_value) Interrupt Enable Clear */ + +#define ADC_INTENCLR_RESRDY_Pos 0 /**< \brief (ADC_INTENCLR) Result Ready Interrupt Disable */ +#define ADC_INTENCLR_RESRDY (_U_(0x1) << ADC_INTENCLR_RESRDY_Pos) +#define ADC_INTENCLR_OVERRUN_Pos 1 /**< \brief (ADC_INTENCLR) Overrun Interrupt Disable */ +#define ADC_INTENCLR_OVERRUN (_U_(0x1) << ADC_INTENCLR_OVERRUN_Pos) +#define ADC_INTENCLR_WINMON_Pos 2 /**< \brief (ADC_INTENCLR) Window Monitor Interrupt Disable */ +#define ADC_INTENCLR_WINMON (_U_(0x1) << ADC_INTENCLR_WINMON_Pos) +#define ADC_INTENCLR_MASK _U_(0x07) /**< \brief (ADC_INTENCLR) MASK Register */ + +/* -------- ADC_INTENSET : (ADC Offset: 0x2D) (R/W 8) Interrupt Enable Set -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t RESRDY:1; /*!< bit: 0 Result Ready Interrupt Enable */ + uint8_t OVERRUN:1; /*!< bit: 1 Overrun Interrupt Enable */ + uint8_t WINMON:1; /*!< bit: 2 Window Monitor Interrupt Enable */ + uint8_t :5; /*!< bit: 3.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} ADC_INTENSET_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_INTENSET_OFFSET 0x2D /**< \brief (ADC_INTENSET offset) Interrupt Enable Set */ +#define ADC_INTENSET_RESETVALUE _U_(0x00) /**< \brief (ADC_INTENSET reset_value) Interrupt Enable Set */ + +#define ADC_INTENSET_RESRDY_Pos 0 /**< \brief (ADC_INTENSET) Result Ready Interrupt Enable */ +#define ADC_INTENSET_RESRDY (_U_(0x1) << ADC_INTENSET_RESRDY_Pos) +#define ADC_INTENSET_OVERRUN_Pos 1 /**< \brief (ADC_INTENSET) Overrun Interrupt Enable */ +#define ADC_INTENSET_OVERRUN (_U_(0x1) << ADC_INTENSET_OVERRUN_Pos) +#define ADC_INTENSET_WINMON_Pos 2 /**< \brief (ADC_INTENSET) Window Monitor Interrupt Enable */ +#define ADC_INTENSET_WINMON (_U_(0x1) << ADC_INTENSET_WINMON_Pos) +#define ADC_INTENSET_MASK _U_(0x07) /**< \brief (ADC_INTENSET) MASK Register */ + +/* -------- ADC_INTFLAG : (ADC Offset: 0x2E) (R/W 8) Interrupt Flag Status and Clear -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { // __I to avoid read-modify-write on write-to-clear register + struct { + __I uint8_t RESRDY:1; /*!< bit: 0 Result Ready Interrupt Flag */ + __I uint8_t OVERRUN:1; /*!< bit: 1 Overrun Interrupt Flag */ + __I uint8_t WINMON:1; /*!< bit: 2 Window Monitor Interrupt Flag */ + __I uint8_t :5; /*!< bit: 3.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} ADC_INTFLAG_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_INTFLAG_OFFSET 0x2E /**< \brief (ADC_INTFLAG offset) Interrupt Flag Status and Clear */ +#define ADC_INTFLAG_RESETVALUE _U_(0x00) /**< \brief (ADC_INTFLAG reset_value) Interrupt Flag Status and Clear */ + +#define ADC_INTFLAG_RESRDY_Pos 0 /**< \brief (ADC_INTFLAG) Result Ready Interrupt Flag */ +#define ADC_INTFLAG_RESRDY (_U_(0x1) << ADC_INTFLAG_RESRDY_Pos) +#define ADC_INTFLAG_OVERRUN_Pos 1 /**< \brief (ADC_INTFLAG) Overrun Interrupt Flag */ +#define ADC_INTFLAG_OVERRUN (_U_(0x1) << ADC_INTFLAG_OVERRUN_Pos) +#define ADC_INTFLAG_WINMON_Pos 2 /**< \brief (ADC_INTFLAG) Window Monitor Interrupt Flag */ +#define ADC_INTFLAG_WINMON (_U_(0x1) << ADC_INTFLAG_WINMON_Pos) +#define ADC_INTFLAG_MASK _U_(0x07) /**< \brief (ADC_INTFLAG) MASK Register */ + +/* -------- ADC_STATUS : (ADC Offset: 0x2F) (R/ 8) Status -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t ADCBUSY:1; /*!< bit: 0 ADC Busy Status */ + uint8_t :1; /*!< bit: 1 Reserved */ + uint8_t WCC:6; /*!< bit: 2.. 7 Window Comparator Counter */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} ADC_STATUS_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_STATUS_OFFSET 0x2F /**< \brief (ADC_STATUS offset) Status */ +#define ADC_STATUS_RESETVALUE _U_(0x00) /**< \brief (ADC_STATUS reset_value) Status */ + +#define ADC_STATUS_ADCBUSY_Pos 0 /**< \brief (ADC_STATUS) ADC Busy Status */ +#define ADC_STATUS_ADCBUSY (_U_(0x1) << ADC_STATUS_ADCBUSY_Pos) +#define ADC_STATUS_WCC_Pos 2 /**< \brief (ADC_STATUS) Window Comparator Counter */ +#define ADC_STATUS_WCC_Msk (_U_(0x3F) << ADC_STATUS_WCC_Pos) +#define ADC_STATUS_WCC(value) (ADC_STATUS_WCC_Msk & ((value) << ADC_STATUS_WCC_Pos)) +#define ADC_STATUS_MASK _U_(0xFD) /**< \brief (ADC_STATUS) MASK Register */ + +/* -------- ADC_SYNCBUSY : (ADC Offset: 0x30) (R/ 32) Synchronization Busy -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t SWRST:1; /*!< bit: 0 SWRST Synchronization Busy */ + uint32_t ENABLE:1; /*!< bit: 1 ENABLE Synchronization Busy */ + uint32_t INPUTCTRL:1; /*!< bit: 2 Input Control Synchronization Busy */ + uint32_t CTRLB:1; /*!< bit: 3 Control B Synchronization Busy */ + uint32_t REFCTRL:1; /*!< bit: 4 Reference Control Synchronization Busy */ + uint32_t AVGCTRL:1; /*!< bit: 5 Average Control Synchronization Busy */ + uint32_t SAMPCTRL:1; /*!< bit: 6 Sampling Time Control Synchronization Busy */ + uint32_t WINLT:1; /*!< bit: 7 Window Monitor Lower Threshold Synchronization Busy */ + uint32_t WINUT:1; /*!< bit: 8 Window Monitor Upper Threshold Synchronization Busy */ + uint32_t GAINCORR:1; /*!< bit: 9 Gain Correction Synchronization Busy */ + uint32_t OFFSETCORR:1; /*!< bit: 10 Offset Correction Synchronization Busy */ + uint32_t SWTRIG:1; /*!< bit: 11 Software Trigger Synchronization Busy */ + uint32_t :20; /*!< bit: 12..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} ADC_SYNCBUSY_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_SYNCBUSY_OFFSET 0x30 /**< \brief (ADC_SYNCBUSY offset) Synchronization Busy */ +#define ADC_SYNCBUSY_RESETVALUE _U_(0x00000000) /**< \brief (ADC_SYNCBUSY reset_value) Synchronization Busy */ + +#define ADC_SYNCBUSY_SWRST_Pos 0 /**< \brief (ADC_SYNCBUSY) SWRST Synchronization Busy */ +#define ADC_SYNCBUSY_SWRST (_U_(0x1) << ADC_SYNCBUSY_SWRST_Pos) +#define ADC_SYNCBUSY_ENABLE_Pos 1 /**< \brief (ADC_SYNCBUSY) ENABLE Synchronization Busy */ +#define ADC_SYNCBUSY_ENABLE (_U_(0x1) << ADC_SYNCBUSY_ENABLE_Pos) +#define ADC_SYNCBUSY_INPUTCTRL_Pos 2 /**< \brief (ADC_SYNCBUSY) Input Control Synchronization Busy */ +#define ADC_SYNCBUSY_INPUTCTRL (_U_(0x1) << ADC_SYNCBUSY_INPUTCTRL_Pos) +#define ADC_SYNCBUSY_CTRLB_Pos 3 /**< \brief (ADC_SYNCBUSY) Control B Synchronization Busy */ +#define ADC_SYNCBUSY_CTRLB (_U_(0x1) << ADC_SYNCBUSY_CTRLB_Pos) +#define ADC_SYNCBUSY_REFCTRL_Pos 4 /**< \brief (ADC_SYNCBUSY) Reference Control Synchronization Busy */ +#define ADC_SYNCBUSY_REFCTRL (_U_(0x1) << ADC_SYNCBUSY_REFCTRL_Pos) +#define ADC_SYNCBUSY_AVGCTRL_Pos 5 /**< \brief (ADC_SYNCBUSY) Average Control Synchronization Busy */ +#define ADC_SYNCBUSY_AVGCTRL (_U_(0x1) << ADC_SYNCBUSY_AVGCTRL_Pos) +#define ADC_SYNCBUSY_SAMPCTRL_Pos 6 /**< \brief (ADC_SYNCBUSY) Sampling Time Control Synchronization Busy */ +#define ADC_SYNCBUSY_SAMPCTRL (_U_(0x1) << ADC_SYNCBUSY_SAMPCTRL_Pos) +#define ADC_SYNCBUSY_WINLT_Pos 7 /**< \brief (ADC_SYNCBUSY) Window Monitor Lower Threshold Synchronization Busy */ +#define ADC_SYNCBUSY_WINLT (_U_(0x1) << ADC_SYNCBUSY_WINLT_Pos) +#define ADC_SYNCBUSY_WINUT_Pos 8 /**< \brief (ADC_SYNCBUSY) Window Monitor Upper Threshold Synchronization Busy */ +#define ADC_SYNCBUSY_WINUT (_U_(0x1) << ADC_SYNCBUSY_WINUT_Pos) +#define ADC_SYNCBUSY_GAINCORR_Pos 9 /**< \brief (ADC_SYNCBUSY) Gain Correction Synchronization Busy */ +#define ADC_SYNCBUSY_GAINCORR (_U_(0x1) << ADC_SYNCBUSY_GAINCORR_Pos) +#define ADC_SYNCBUSY_OFFSETCORR_Pos 10 /**< \brief (ADC_SYNCBUSY) Offset Correction Synchronization Busy */ +#define ADC_SYNCBUSY_OFFSETCORR (_U_(0x1) << ADC_SYNCBUSY_OFFSETCORR_Pos) +#define ADC_SYNCBUSY_SWTRIG_Pos 11 /**< \brief (ADC_SYNCBUSY) Software Trigger Synchronization Busy */ +#define ADC_SYNCBUSY_SWTRIG (_U_(0x1) << ADC_SYNCBUSY_SWTRIG_Pos) +#define ADC_SYNCBUSY_MASK _U_(0x00000FFF) /**< \brief (ADC_SYNCBUSY) MASK Register */ + +/* -------- ADC_DSEQDATA : (ADC Offset: 0x34) ( /W 32) DMA Sequencial Data -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t DATA:32; /*!< bit: 0..31 DMA Sequential Data */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} ADC_DSEQDATA_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_DSEQDATA_OFFSET 0x34 /**< \brief (ADC_DSEQDATA offset) DMA Sequencial Data */ +#define ADC_DSEQDATA_RESETVALUE _U_(0x00000000) /**< \brief (ADC_DSEQDATA reset_value) DMA Sequencial Data */ + +#define ADC_DSEQDATA_DATA_Pos 0 /**< \brief (ADC_DSEQDATA) DMA Sequential Data */ +#define ADC_DSEQDATA_DATA_Msk (_U_(0xFFFFFFFF) << ADC_DSEQDATA_DATA_Pos) +#define ADC_DSEQDATA_DATA(value) (ADC_DSEQDATA_DATA_Msk & ((value) << ADC_DSEQDATA_DATA_Pos)) +#define ADC_DSEQDATA_MASK _U_(0xFFFFFFFF) /**< \brief (ADC_DSEQDATA) MASK Register */ + +/* -------- ADC_DSEQCTRL : (ADC Offset: 0x38) (R/W 32) DMA Sequential Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t INPUTCTRL:1; /*!< bit: 0 Input Control */ + uint32_t CTRLB:1; /*!< bit: 1 Control B */ + uint32_t REFCTRL:1; /*!< bit: 2 Reference Control */ + uint32_t AVGCTRL:1; /*!< bit: 3 Average Control */ + uint32_t SAMPCTRL:1; /*!< bit: 4 Sampling Time Control */ + uint32_t WINLT:1; /*!< bit: 5 Window Monitor Lower Threshold */ + uint32_t WINUT:1; /*!< bit: 6 Window Monitor Upper Threshold */ + uint32_t GAINCORR:1; /*!< bit: 7 Gain Correction */ + uint32_t OFFSETCORR:1; /*!< bit: 8 Offset Correction */ + uint32_t :22; /*!< bit: 9..30 Reserved */ + uint32_t AUTOSTART:1; /*!< bit: 31 ADC Auto-Start Conversion */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} ADC_DSEQCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_DSEQCTRL_OFFSET 0x38 /**< \brief (ADC_DSEQCTRL offset) DMA Sequential Control */ +#define ADC_DSEQCTRL_RESETVALUE _U_(0x00000000) /**< \brief (ADC_DSEQCTRL reset_value) DMA Sequential Control */ + +#define ADC_DSEQCTRL_INPUTCTRL_Pos 0 /**< \brief (ADC_DSEQCTRL) Input Control */ +#define ADC_DSEQCTRL_INPUTCTRL (_U_(0x1) << ADC_DSEQCTRL_INPUTCTRL_Pos) +#define ADC_DSEQCTRL_CTRLB_Pos 1 /**< \brief (ADC_DSEQCTRL) Control B */ +#define ADC_DSEQCTRL_CTRLB (_U_(0x1) << ADC_DSEQCTRL_CTRLB_Pos) +#define ADC_DSEQCTRL_REFCTRL_Pos 2 /**< \brief (ADC_DSEQCTRL) Reference Control */ +#define ADC_DSEQCTRL_REFCTRL (_U_(0x1) << ADC_DSEQCTRL_REFCTRL_Pos) +#define ADC_DSEQCTRL_AVGCTRL_Pos 3 /**< \brief (ADC_DSEQCTRL) Average Control */ +#define ADC_DSEQCTRL_AVGCTRL (_U_(0x1) << ADC_DSEQCTRL_AVGCTRL_Pos) +#define ADC_DSEQCTRL_SAMPCTRL_Pos 4 /**< \brief (ADC_DSEQCTRL) Sampling Time Control */ +#define ADC_DSEQCTRL_SAMPCTRL (_U_(0x1) << ADC_DSEQCTRL_SAMPCTRL_Pos) +#define ADC_DSEQCTRL_WINLT_Pos 5 /**< \brief (ADC_DSEQCTRL) Window Monitor Lower Threshold */ +#define ADC_DSEQCTRL_WINLT (_U_(0x1) << ADC_DSEQCTRL_WINLT_Pos) +#define ADC_DSEQCTRL_WINUT_Pos 6 /**< \brief (ADC_DSEQCTRL) Window Monitor Upper Threshold */ +#define ADC_DSEQCTRL_WINUT (_U_(0x1) << ADC_DSEQCTRL_WINUT_Pos) +#define ADC_DSEQCTRL_GAINCORR_Pos 7 /**< \brief (ADC_DSEQCTRL) Gain Correction */ +#define ADC_DSEQCTRL_GAINCORR (_U_(0x1) << ADC_DSEQCTRL_GAINCORR_Pos) +#define ADC_DSEQCTRL_OFFSETCORR_Pos 8 /**< \brief (ADC_DSEQCTRL) Offset Correction */ +#define ADC_DSEQCTRL_OFFSETCORR (_U_(0x1) << ADC_DSEQCTRL_OFFSETCORR_Pos) +#define ADC_DSEQCTRL_AUTOSTART_Pos 31 /**< \brief (ADC_DSEQCTRL) ADC Auto-Start Conversion */ +#define ADC_DSEQCTRL_AUTOSTART (_U_(0x1) << ADC_DSEQCTRL_AUTOSTART_Pos) +#define ADC_DSEQCTRL_MASK _U_(0x800001FF) /**< \brief (ADC_DSEQCTRL) MASK Register */ + +/* -------- ADC_DSEQSTAT : (ADC Offset: 0x3C) (R/ 32) DMA Sequencial Status -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t INPUTCTRL:1; /*!< bit: 0 Input Control */ + uint32_t CTRLB:1; /*!< bit: 1 Control B */ + uint32_t REFCTRL:1; /*!< bit: 2 Reference Control */ + uint32_t AVGCTRL:1; /*!< bit: 3 Average Control */ + uint32_t SAMPCTRL:1; /*!< bit: 4 Sampling Time Control */ + uint32_t WINLT:1; /*!< bit: 5 Window Monitor Lower Threshold */ + uint32_t WINUT:1; /*!< bit: 6 Window Monitor Upper Threshold */ + uint32_t GAINCORR:1; /*!< bit: 7 Gain Correction */ + uint32_t OFFSETCORR:1; /*!< bit: 8 Offset Correction */ + uint32_t :22; /*!< bit: 9..30 Reserved */ + uint32_t BUSY:1; /*!< bit: 31 DMA Sequencing Busy */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} ADC_DSEQSTAT_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_DSEQSTAT_OFFSET 0x3C /**< \brief (ADC_DSEQSTAT offset) DMA Sequencial Status */ +#define ADC_DSEQSTAT_RESETVALUE _U_(0x00000000) /**< \brief (ADC_DSEQSTAT reset_value) DMA Sequencial Status */ + +#define ADC_DSEQSTAT_INPUTCTRL_Pos 0 /**< \brief (ADC_DSEQSTAT) Input Control */ +#define ADC_DSEQSTAT_INPUTCTRL (_U_(0x1) << ADC_DSEQSTAT_INPUTCTRL_Pos) +#define ADC_DSEQSTAT_CTRLB_Pos 1 /**< \brief (ADC_DSEQSTAT) Control B */ +#define ADC_DSEQSTAT_CTRLB (_U_(0x1) << ADC_DSEQSTAT_CTRLB_Pos) +#define ADC_DSEQSTAT_REFCTRL_Pos 2 /**< \brief (ADC_DSEQSTAT) Reference Control */ +#define ADC_DSEQSTAT_REFCTRL (_U_(0x1) << ADC_DSEQSTAT_REFCTRL_Pos) +#define ADC_DSEQSTAT_AVGCTRL_Pos 3 /**< \brief (ADC_DSEQSTAT) Average Control */ +#define ADC_DSEQSTAT_AVGCTRL (_U_(0x1) << ADC_DSEQSTAT_AVGCTRL_Pos) +#define ADC_DSEQSTAT_SAMPCTRL_Pos 4 /**< \brief (ADC_DSEQSTAT) Sampling Time Control */ +#define ADC_DSEQSTAT_SAMPCTRL (_U_(0x1) << ADC_DSEQSTAT_SAMPCTRL_Pos) +#define ADC_DSEQSTAT_WINLT_Pos 5 /**< \brief (ADC_DSEQSTAT) Window Monitor Lower Threshold */ +#define ADC_DSEQSTAT_WINLT (_U_(0x1) << ADC_DSEQSTAT_WINLT_Pos) +#define ADC_DSEQSTAT_WINUT_Pos 6 /**< \brief (ADC_DSEQSTAT) Window Monitor Upper Threshold */ +#define ADC_DSEQSTAT_WINUT (_U_(0x1) << ADC_DSEQSTAT_WINUT_Pos) +#define ADC_DSEQSTAT_GAINCORR_Pos 7 /**< \brief (ADC_DSEQSTAT) Gain Correction */ +#define ADC_DSEQSTAT_GAINCORR (_U_(0x1) << ADC_DSEQSTAT_GAINCORR_Pos) +#define ADC_DSEQSTAT_OFFSETCORR_Pos 8 /**< \brief (ADC_DSEQSTAT) Offset Correction */ +#define ADC_DSEQSTAT_OFFSETCORR (_U_(0x1) << ADC_DSEQSTAT_OFFSETCORR_Pos) +#define ADC_DSEQSTAT_BUSY_Pos 31 /**< \brief (ADC_DSEQSTAT) DMA Sequencing Busy */ +#define ADC_DSEQSTAT_BUSY (_U_(0x1) << ADC_DSEQSTAT_BUSY_Pos) +#define ADC_DSEQSTAT_MASK _U_(0x800001FF) /**< \brief (ADC_DSEQSTAT) MASK Register */ + +/* -------- ADC_RESULT : (ADC Offset: 0x40) (R/ 16) Result Conversion Value -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t RESULT:16; /*!< bit: 0..15 Result Conversion Value */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} ADC_RESULT_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_RESULT_OFFSET 0x40 /**< \brief (ADC_RESULT offset) Result Conversion Value */ +#define ADC_RESULT_RESETVALUE _U_(0x0000) /**< \brief (ADC_RESULT reset_value) Result Conversion Value */ + +#define ADC_RESULT_RESULT_Pos 0 /**< \brief (ADC_RESULT) Result Conversion Value */ +#define ADC_RESULT_RESULT_Msk (_U_(0xFFFF) << ADC_RESULT_RESULT_Pos) +#define ADC_RESULT_RESULT(value) (ADC_RESULT_RESULT_Msk & ((value) << ADC_RESULT_RESULT_Pos)) +#define ADC_RESULT_MASK _U_(0xFFFF) /**< \brief (ADC_RESULT) MASK Register */ + +/* -------- ADC_RESS : (ADC Offset: 0x44) (R/ 16) Last Sample Result -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t RESS:16; /*!< bit: 0..15 Last ADC conversion result */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} ADC_RESS_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_RESS_OFFSET 0x44 /**< \brief (ADC_RESS offset) Last Sample Result */ +#define ADC_RESS_RESETVALUE _U_(0x0000) /**< \brief (ADC_RESS reset_value) Last Sample Result */ + +#define ADC_RESS_RESS_Pos 0 /**< \brief (ADC_RESS) Last ADC conversion result */ +#define ADC_RESS_RESS_Msk (_U_(0xFFFF) << ADC_RESS_RESS_Pos) +#define ADC_RESS_RESS(value) (ADC_RESS_RESS_Msk & ((value) << ADC_RESS_RESS_Pos)) +#define ADC_RESS_MASK _U_(0xFFFF) /**< \brief (ADC_RESS) MASK Register */ + +/* -------- ADC_CALIB : (ADC Offset: 0x48) (R/W 16) Calibration -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t BIASCOMP:3; /*!< bit: 0.. 2 Bias Comparator Scaling */ + uint16_t :1; /*!< bit: 3 Reserved */ + uint16_t BIASR2R:3; /*!< bit: 4.. 6 Bias R2R Ampli scaling */ + uint16_t :1; /*!< bit: 7 Reserved */ + uint16_t BIASREFBUF:3; /*!< bit: 8..10 Bias Reference Buffer Scaling */ + uint16_t :5; /*!< bit: 11..15 Reserved */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} ADC_CALIB_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_CALIB_OFFSET 0x48 /**< \brief (ADC_CALIB offset) Calibration */ +#define ADC_CALIB_RESETVALUE _U_(0x0000) /**< \brief (ADC_CALIB reset_value) Calibration */ + +#define ADC_CALIB_BIASCOMP_Pos 0 /**< \brief (ADC_CALIB) Bias Comparator Scaling */ +#define ADC_CALIB_BIASCOMP_Msk (_U_(0x7) << ADC_CALIB_BIASCOMP_Pos) +#define ADC_CALIB_BIASCOMP(value) (ADC_CALIB_BIASCOMP_Msk & ((value) << ADC_CALIB_BIASCOMP_Pos)) +#define ADC_CALIB_BIASR2R_Pos 4 /**< \brief (ADC_CALIB) Bias R2R Ampli scaling */ +#define ADC_CALIB_BIASR2R_Msk (_U_(0x7) << ADC_CALIB_BIASR2R_Pos) +#define ADC_CALIB_BIASR2R(value) (ADC_CALIB_BIASR2R_Msk & ((value) << ADC_CALIB_BIASR2R_Pos)) +#define ADC_CALIB_BIASREFBUF_Pos 8 /**< \brief (ADC_CALIB) Bias Reference Buffer Scaling */ +#define ADC_CALIB_BIASREFBUF_Msk (_U_(0x7) << ADC_CALIB_BIASREFBUF_Pos) +#define ADC_CALIB_BIASREFBUF(value) (ADC_CALIB_BIASREFBUF_Msk & ((value) << ADC_CALIB_BIASREFBUF_Pos)) +#define ADC_CALIB_MASK _U_(0x0777) /**< \brief (ADC_CALIB) MASK Register */ + +/** \brief ADC hardware registers */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef struct { + __IO ADC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 16) Control A */ + __IO ADC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x02 (R/W 8) Event Control */ + __IO ADC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x03 (R/W 8) Debug Control */ + __IO ADC_INPUTCTRL_Type INPUTCTRL; /**< \brief Offset: 0x04 (R/W 16) Input Control */ + __IO ADC_CTRLB_Type CTRLB; /**< \brief Offset: 0x06 (R/W 16) Control B */ + __IO ADC_REFCTRL_Type REFCTRL; /**< \brief Offset: 0x08 (R/W 8) Reference Control */ + RoReg8 Reserved1[0x1]; + __IO ADC_AVGCTRL_Type AVGCTRL; /**< \brief Offset: 0x0A (R/W 8) Average Control */ + __IO ADC_SAMPCTRL_Type SAMPCTRL; /**< \brief Offset: 0x0B (R/W 8) Sample Time Control */ + __IO ADC_WINLT_Type WINLT; /**< \brief Offset: 0x0C (R/W 16) Window Monitor Lower Threshold */ + __IO ADC_WINUT_Type WINUT; /**< \brief Offset: 0x0E (R/W 16) Window Monitor Upper Threshold */ + __IO ADC_GAINCORR_Type GAINCORR; /**< \brief Offset: 0x10 (R/W 16) Gain Correction */ + __IO ADC_OFFSETCORR_Type OFFSETCORR; /**< \brief Offset: 0x12 (R/W 16) Offset Correction */ + __IO ADC_SWTRIG_Type SWTRIG; /**< \brief Offset: 0x14 (R/W 8) Software Trigger */ + RoReg8 Reserved2[0x17]; + __IO ADC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x2C (R/W 8) Interrupt Enable Clear */ + __IO ADC_INTENSET_Type INTENSET; /**< \brief Offset: 0x2D (R/W 8) Interrupt Enable Set */ + __IO ADC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x2E (R/W 8) Interrupt Flag Status and Clear */ + __I ADC_STATUS_Type STATUS; /**< \brief Offset: 0x2F (R/ 8) Status */ + __I ADC_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x30 (R/ 32) Synchronization Busy */ + __O ADC_DSEQDATA_Type DSEQDATA; /**< \brief Offset: 0x34 ( /W 32) DMA Sequencial Data */ + __IO ADC_DSEQCTRL_Type DSEQCTRL; /**< \brief Offset: 0x38 (R/W 32) DMA Sequential Control */ + __I ADC_DSEQSTAT_Type DSEQSTAT; /**< \brief Offset: 0x3C (R/ 32) DMA Sequencial Status */ + __I ADC_RESULT_Type RESULT; /**< \brief Offset: 0x40 (R/ 16) Result Conversion Value */ + RoReg8 Reserved3[0x2]; + __I ADC_RESS_Type RESS; /**< \brief Offset: 0x44 (R/ 16) Last Sample Result */ + RoReg8 Reserved4[0x2]; + __IO ADC_CALIB_Type CALIB; /**< \brief Offset: 0x48 (R/W 16) Calibration */ +} Adc; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/*@}*/ + +#endif /* _SAME54_ADC_COMPONENT_ */ diff --git a/arch/arm/SAME54/SAME54A/mcu/inc/component/aes.h b/arch/arm/SAME54/SAME54A/mcu/inc/component/aes.h index ed46fe47..2831d0db 100644 --- a/arch/arm/SAME54/SAME54A/mcu/inc/component/aes.h +++ b/arch/arm/SAME54/SAME54A/mcu/inc/component/aes.h @@ -1,276 +1,375 @@ -/** - * \brief Component description for AES - * - * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries. - * - * Subject to your compliance with these terms, you may use Microchip software and any derivatives - * exclusively with Microchip products. It is your responsibility to comply with third party license - * terms applicable to your use of third party software (including open source software) that may - * accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, - * APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND - * FITNESS FOR A PARTICULAR PURPOSE. - * - * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF - * MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT - * EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - */ - -/* file generated from device description version 2020-03-12T17:27:04Z */ -#ifndef _SAME54_AES_COMPONENT_H_ -#define _SAME54_AES_COMPONENT_H_ - -/* ************************************************************************** */ -/* SOFTWARE API DEFINITION FOR AES */ -/* ************************************************************************** */ - -/* -------- AES_CTRLA : (AES Offset: 0x00) (R/W 32) Control A -------- */ -#define AES_CTRLA_RESETVALUE _U_(0x00) /**< (AES_CTRLA) Control A Reset Value */ - -#define AES_CTRLA_SWRST_Pos _U_(0) /**< (AES_CTRLA) Software Reset Position */ -#define AES_CTRLA_SWRST_Msk (_U_(0x1) << AES_CTRLA_SWRST_Pos) /**< (AES_CTRLA) Software Reset Mask */ -#define AES_CTRLA_SWRST(value) (AES_CTRLA_SWRST_Msk & ((value) << AES_CTRLA_SWRST_Pos)) -#define AES_CTRLA_ENABLE_Pos _U_(1) /**< (AES_CTRLA) Enable Position */ -#define AES_CTRLA_ENABLE_Msk (_U_(0x1) << AES_CTRLA_ENABLE_Pos) /**< (AES_CTRLA) Enable Mask */ -#define AES_CTRLA_ENABLE(value) (AES_CTRLA_ENABLE_Msk & ((value) << AES_CTRLA_ENABLE_Pos)) -#define AES_CTRLA_AESMODE_Pos _U_(2) /**< (AES_CTRLA) AES Modes of operation Position */ -#define AES_CTRLA_AESMODE_Msk (_U_(0x7) << AES_CTRLA_AESMODE_Pos) /**< (AES_CTRLA) AES Modes of operation Mask */ -#define AES_CTRLA_AESMODE(value) (AES_CTRLA_AESMODE_Msk & ((value) << AES_CTRLA_AESMODE_Pos)) -#define AES_CTRLA_AESMODE_ECB_Val _U_(0x0) /**< (AES_CTRLA) Electronic code book mode */ -#define AES_CTRLA_AESMODE_CBC_Val _U_(0x1) /**< (AES_CTRLA) Cipher block chaining mode */ -#define AES_CTRLA_AESMODE_OFB_Val _U_(0x2) /**< (AES_CTRLA) Output feedback mode */ -#define AES_CTRLA_AESMODE_CFB_Val _U_(0x3) /**< (AES_CTRLA) Cipher feedback mode */ -#define AES_CTRLA_AESMODE_COUNTER_Val _U_(0x4) /**< (AES_CTRLA) Counter mode */ -#define AES_CTRLA_AESMODE_CCM_Val _U_(0x5) /**< (AES_CTRLA) CCM mode */ -#define AES_CTRLA_AESMODE_GCM_Val _U_(0x6) /**< (AES_CTRLA) Galois counter mode */ -#define AES_CTRLA_AESMODE_ECB (AES_CTRLA_AESMODE_ECB_Val << AES_CTRLA_AESMODE_Pos) /**< (AES_CTRLA) Electronic code book mode Position */ -#define AES_CTRLA_AESMODE_CBC (AES_CTRLA_AESMODE_CBC_Val << AES_CTRLA_AESMODE_Pos) /**< (AES_CTRLA) Cipher block chaining mode Position */ -#define AES_CTRLA_AESMODE_OFB (AES_CTRLA_AESMODE_OFB_Val << AES_CTRLA_AESMODE_Pos) /**< (AES_CTRLA) Output feedback mode Position */ -#define AES_CTRLA_AESMODE_CFB (AES_CTRLA_AESMODE_CFB_Val << AES_CTRLA_AESMODE_Pos) /**< (AES_CTRLA) Cipher feedback mode Position */ -#define AES_CTRLA_AESMODE_COUNTER (AES_CTRLA_AESMODE_COUNTER_Val << AES_CTRLA_AESMODE_Pos) /**< (AES_CTRLA) Counter mode Position */ -#define AES_CTRLA_AESMODE_CCM (AES_CTRLA_AESMODE_CCM_Val << AES_CTRLA_AESMODE_Pos) /**< (AES_CTRLA) CCM mode Position */ -#define AES_CTRLA_AESMODE_GCM (AES_CTRLA_AESMODE_GCM_Val << AES_CTRLA_AESMODE_Pos) /**< (AES_CTRLA) Galois counter mode Position */ -#define AES_CTRLA_CFBS_Pos _U_(5) /**< (AES_CTRLA) Cipher Feedback Block Size Position */ -#define AES_CTRLA_CFBS_Msk (_U_(0x7) << AES_CTRLA_CFBS_Pos) /**< (AES_CTRLA) Cipher Feedback Block Size Mask */ -#define AES_CTRLA_CFBS(value) (AES_CTRLA_CFBS_Msk & ((value) << AES_CTRLA_CFBS_Pos)) -#define AES_CTRLA_CFBS_128BIT_Val _U_(0x0) /**< (AES_CTRLA) 128-bit Input data block for Encryption/Decryption in Cipher Feedback mode */ -#define AES_CTRLA_CFBS_64BIT_Val _U_(0x1) /**< (AES_CTRLA) 64-bit Input data block for Encryption/Decryption in Cipher Feedback mode */ -#define AES_CTRLA_CFBS_32BIT_Val _U_(0x2) /**< (AES_CTRLA) 32-bit Input data block for Encryption/Decryption in Cipher Feedback mode */ -#define AES_CTRLA_CFBS_16BIT_Val _U_(0x3) /**< (AES_CTRLA) 16-bit Input data block for Encryption/Decryption in Cipher Feedback mode */ -#define AES_CTRLA_CFBS_8BIT_Val _U_(0x4) /**< (AES_CTRLA) 8-bit Input data block for Encryption/Decryption in Cipher Feedback mode */ -#define AES_CTRLA_CFBS_128BIT (AES_CTRLA_CFBS_128BIT_Val << AES_CTRLA_CFBS_Pos) /**< (AES_CTRLA) 128-bit Input data block for Encryption/Decryption in Cipher Feedback mode Position */ -#define AES_CTRLA_CFBS_64BIT (AES_CTRLA_CFBS_64BIT_Val << AES_CTRLA_CFBS_Pos) /**< (AES_CTRLA) 64-bit Input data block for Encryption/Decryption in Cipher Feedback mode Position */ -#define AES_CTRLA_CFBS_32BIT (AES_CTRLA_CFBS_32BIT_Val << AES_CTRLA_CFBS_Pos) /**< (AES_CTRLA) 32-bit Input data block for Encryption/Decryption in Cipher Feedback mode Position */ -#define AES_CTRLA_CFBS_16BIT (AES_CTRLA_CFBS_16BIT_Val << AES_CTRLA_CFBS_Pos) /**< (AES_CTRLA) 16-bit Input data block for Encryption/Decryption in Cipher Feedback mode Position */ -#define AES_CTRLA_CFBS_8BIT (AES_CTRLA_CFBS_8BIT_Val << AES_CTRLA_CFBS_Pos) /**< (AES_CTRLA) 8-bit Input data block for Encryption/Decryption in Cipher Feedback mode Position */ -#define AES_CTRLA_KEYSIZE_Pos _U_(8) /**< (AES_CTRLA) Encryption Key Size Position */ -#define AES_CTRLA_KEYSIZE_Msk (_U_(0x3) << AES_CTRLA_KEYSIZE_Pos) /**< (AES_CTRLA) Encryption Key Size Mask */ -#define AES_CTRLA_KEYSIZE(value) (AES_CTRLA_KEYSIZE_Msk & ((value) << AES_CTRLA_KEYSIZE_Pos)) -#define AES_CTRLA_KEYSIZE_128BIT_Val _U_(0x0) /**< (AES_CTRLA) 128-bit Key for Encryption / Decryption */ -#define AES_CTRLA_KEYSIZE_192BIT_Val _U_(0x1) /**< (AES_CTRLA) 192-bit Key for Encryption / Decryption */ -#define AES_CTRLA_KEYSIZE_256BIT_Val _U_(0x2) /**< (AES_CTRLA) 256-bit Key for Encryption / Decryption */ -#define AES_CTRLA_KEYSIZE_128BIT (AES_CTRLA_KEYSIZE_128BIT_Val << AES_CTRLA_KEYSIZE_Pos) /**< (AES_CTRLA) 128-bit Key for Encryption / Decryption Position */ -#define AES_CTRLA_KEYSIZE_192BIT (AES_CTRLA_KEYSIZE_192BIT_Val << AES_CTRLA_KEYSIZE_Pos) /**< (AES_CTRLA) 192-bit Key for Encryption / Decryption Position */ -#define AES_CTRLA_KEYSIZE_256BIT (AES_CTRLA_KEYSIZE_256BIT_Val << AES_CTRLA_KEYSIZE_Pos) /**< (AES_CTRLA) 256-bit Key for Encryption / Decryption Position */ -#define AES_CTRLA_CIPHER_Pos _U_(10) /**< (AES_CTRLA) Cipher Mode Position */ -#define AES_CTRLA_CIPHER_Msk (_U_(0x1) << AES_CTRLA_CIPHER_Pos) /**< (AES_CTRLA) Cipher Mode Mask */ -#define AES_CTRLA_CIPHER(value) (AES_CTRLA_CIPHER_Msk & ((value) << AES_CTRLA_CIPHER_Pos)) -#define AES_CTRLA_CIPHER_DEC_Val _U_(0x0) /**< (AES_CTRLA) Decryption */ -#define AES_CTRLA_CIPHER_ENC_Val _U_(0x1) /**< (AES_CTRLA) Encryption */ -#define AES_CTRLA_CIPHER_DEC (AES_CTRLA_CIPHER_DEC_Val << AES_CTRLA_CIPHER_Pos) /**< (AES_CTRLA) Decryption Position */ -#define AES_CTRLA_CIPHER_ENC (AES_CTRLA_CIPHER_ENC_Val << AES_CTRLA_CIPHER_Pos) /**< (AES_CTRLA) Encryption Position */ -#define AES_CTRLA_STARTMODE_Pos _U_(11) /**< (AES_CTRLA) Start Mode Select Position */ -#define AES_CTRLA_STARTMODE_Msk (_U_(0x1) << AES_CTRLA_STARTMODE_Pos) /**< (AES_CTRLA) Start Mode Select Mask */ -#define AES_CTRLA_STARTMODE(value) (AES_CTRLA_STARTMODE_Msk & ((value) << AES_CTRLA_STARTMODE_Pos)) -#define AES_CTRLA_STARTMODE_MANUAL_Val _U_(0x0) /**< (AES_CTRLA) Start Encryption / Decryption in Manual mode */ -#define AES_CTRLA_STARTMODE_AUTO_Val _U_(0x1) /**< (AES_CTRLA) Start Encryption / Decryption in Auto mode */ -#define AES_CTRLA_STARTMODE_MANUAL (AES_CTRLA_STARTMODE_MANUAL_Val << AES_CTRLA_STARTMODE_Pos) /**< (AES_CTRLA) Start Encryption / Decryption in Manual mode Position */ -#define AES_CTRLA_STARTMODE_AUTO (AES_CTRLA_STARTMODE_AUTO_Val << AES_CTRLA_STARTMODE_Pos) /**< (AES_CTRLA) Start Encryption / Decryption in Auto mode Position */ -#define AES_CTRLA_LOD_Pos _U_(12) /**< (AES_CTRLA) Last Output Data Mode Position */ -#define AES_CTRLA_LOD_Msk (_U_(0x1) << AES_CTRLA_LOD_Pos) /**< (AES_CTRLA) Last Output Data Mode Mask */ -#define AES_CTRLA_LOD(value) (AES_CTRLA_LOD_Msk & ((value) << AES_CTRLA_LOD_Pos)) -#define AES_CTRLA_LOD_NONE_Val _U_(0x0) /**< (AES_CTRLA) No effect */ -#define AES_CTRLA_LOD_LAST_Val _U_(0x1) /**< (AES_CTRLA) Start encryption in Last Output Data mode */ -#define AES_CTRLA_LOD_NONE (AES_CTRLA_LOD_NONE_Val << AES_CTRLA_LOD_Pos) /**< (AES_CTRLA) No effect Position */ -#define AES_CTRLA_LOD_LAST (AES_CTRLA_LOD_LAST_Val << AES_CTRLA_LOD_Pos) /**< (AES_CTRLA) Start encryption in Last Output Data mode Position */ -#define AES_CTRLA_KEYGEN_Pos _U_(13) /**< (AES_CTRLA) Last Key Generation Position */ -#define AES_CTRLA_KEYGEN_Msk (_U_(0x1) << AES_CTRLA_KEYGEN_Pos) /**< (AES_CTRLA) Last Key Generation Mask */ -#define AES_CTRLA_KEYGEN(value) (AES_CTRLA_KEYGEN_Msk & ((value) << AES_CTRLA_KEYGEN_Pos)) -#define AES_CTRLA_KEYGEN_NONE_Val _U_(0x0) /**< (AES_CTRLA) No effect */ -#define AES_CTRLA_KEYGEN_LAST_Val _U_(0x1) /**< (AES_CTRLA) Start Computation of the last NK words of the expanded key */ -#define AES_CTRLA_KEYGEN_NONE (AES_CTRLA_KEYGEN_NONE_Val << AES_CTRLA_KEYGEN_Pos) /**< (AES_CTRLA) No effect Position */ -#define AES_CTRLA_KEYGEN_LAST (AES_CTRLA_KEYGEN_LAST_Val << AES_CTRLA_KEYGEN_Pos) /**< (AES_CTRLA) Start Computation of the last NK words of the expanded key Position */ -#define AES_CTRLA_XORKEY_Pos _U_(14) /**< (AES_CTRLA) XOR Key Operation Position */ -#define AES_CTRLA_XORKEY_Msk (_U_(0x1) << AES_CTRLA_XORKEY_Pos) /**< (AES_CTRLA) XOR Key Operation Mask */ -#define AES_CTRLA_XORKEY(value) (AES_CTRLA_XORKEY_Msk & ((value) << AES_CTRLA_XORKEY_Pos)) -#define AES_CTRLA_XORKEY_NONE_Val _U_(0x0) /**< (AES_CTRLA) No effect */ -#define AES_CTRLA_XORKEY_XOR_Val _U_(0x1) /**< (AES_CTRLA) The user keyword gets XORed with the previous keyword register content. */ -#define AES_CTRLA_XORKEY_NONE (AES_CTRLA_XORKEY_NONE_Val << AES_CTRLA_XORKEY_Pos) /**< (AES_CTRLA) No effect Position */ -#define AES_CTRLA_XORKEY_XOR (AES_CTRLA_XORKEY_XOR_Val << AES_CTRLA_XORKEY_Pos) /**< (AES_CTRLA) The user keyword gets XORed with the previous keyword register content. Position */ -#define AES_CTRLA_CTYPE_Pos _U_(16) /**< (AES_CTRLA) Counter Measure Type Position */ -#define AES_CTRLA_CTYPE_Msk (_U_(0xF) << AES_CTRLA_CTYPE_Pos) /**< (AES_CTRLA) Counter Measure Type Mask */ -#define AES_CTRLA_CTYPE(value) (AES_CTRLA_CTYPE_Msk & ((value) << AES_CTRLA_CTYPE_Pos)) -#define AES_CTRLA_Msk _U_(0x000F7FFF) /**< (AES_CTRLA) Register Mask */ - - -/* -------- AES_CTRLB : (AES Offset: 0x04) (R/W 8) Control B -------- */ -#define AES_CTRLB_RESETVALUE _U_(0x00) /**< (AES_CTRLB) Control B Reset Value */ - -#define AES_CTRLB_START_Pos _U_(0) /**< (AES_CTRLB) Start Encryption/Decryption Position */ -#define AES_CTRLB_START_Msk (_U_(0x1) << AES_CTRLB_START_Pos) /**< (AES_CTRLB) Start Encryption/Decryption Mask */ -#define AES_CTRLB_START(value) (AES_CTRLB_START_Msk & ((value) << AES_CTRLB_START_Pos)) -#define AES_CTRLB_NEWMSG_Pos _U_(1) /**< (AES_CTRLB) New message Position */ -#define AES_CTRLB_NEWMSG_Msk (_U_(0x1) << AES_CTRLB_NEWMSG_Pos) /**< (AES_CTRLB) New message Mask */ -#define AES_CTRLB_NEWMSG(value) (AES_CTRLB_NEWMSG_Msk & ((value) << AES_CTRLB_NEWMSG_Pos)) -#define AES_CTRLB_EOM_Pos _U_(2) /**< (AES_CTRLB) End of message Position */ -#define AES_CTRLB_EOM_Msk (_U_(0x1) << AES_CTRLB_EOM_Pos) /**< (AES_CTRLB) End of message Mask */ -#define AES_CTRLB_EOM(value) (AES_CTRLB_EOM_Msk & ((value) << AES_CTRLB_EOM_Pos)) -#define AES_CTRLB_GFMUL_Pos _U_(3) /**< (AES_CTRLB) GF Multiplication Position */ -#define AES_CTRLB_GFMUL_Msk (_U_(0x1) << AES_CTRLB_GFMUL_Pos) /**< (AES_CTRLB) GF Multiplication Mask */ -#define AES_CTRLB_GFMUL(value) (AES_CTRLB_GFMUL_Msk & ((value) << AES_CTRLB_GFMUL_Pos)) -#define AES_CTRLB_Msk _U_(0x0F) /**< (AES_CTRLB) Register Mask */ - - -/* -------- AES_INTENCLR : (AES Offset: 0x05) (R/W 8) Interrupt Enable Clear -------- */ -#define AES_INTENCLR_RESETVALUE _U_(0x00) /**< (AES_INTENCLR) Interrupt Enable Clear Reset Value */ - -#define AES_INTENCLR_ENCCMP_Pos _U_(0) /**< (AES_INTENCLR) Encryption Complete Interrupt Enable Position */ -#define AES_INTENCLR_ENCCMP_Msk (_U_(0x1) << AES_INTENCLR_ENCCMP_Pos) /**< (AES_INTENCLR) Encryption Complete Interrupt Enable Mask */ -#define AES_INTENCLR_ENCCMP(value) (AES_INTENCLR_ENCCMP_Msk & ((value) << AES_INTENCLR_ENCCMP_Pos)) -#define AES_INTENCLR_GFMCMP_Pos _U_(1) /**< (AES_INTENCLR) GF Multiplication Complete Interrupt Enable Position */ -#define AES_INTENCLR_GFMCMP_Msk (_U_(0x1) << AES_INTENCLR_GFMCMP_Pos) /**< (AES_INTENCLR) GF Multiplication Complete Interrupt Enable Mask */ -#define AES_INTENCLR_GFMCMP(value) (AES_INTENCLR_GFMCMP_Msk & ((value) << AES_INTENCLR_GFMCMP_Pos)) -#define AES_INTENCLR_Msk _U_(0x03) /**< (AES_INTENCLR) Register Mask */ - - -/* -------- AES_INTENSET : (AES Offset: 0x06) (R/W 8) Interrupt Enable Set -------- */ -#define AES_INTENSET_RESETVALUE _U_(0x00) /**< (AES_INTENSET) Interrupt Enable Set Reset Value */ - -#define AES_INTENSET_ENCCMP_Pos _U_(0) /**< (AES_INTENSET) Encryption Complete Interrupt Enable Position */ -#define AES_INTENSET_ENCCMP_Msk (_U_(0x1) << AES_INTENSET_ENCCMP_Pos) /**< (AES_INTENSET) Encryption Complete Interrupt Enable Mask */ -#define AES_INTENSET_ENCCMP(value) (AES_INTENSET_ENCCMP_Msk & ((value) << AES_INTENSET_ENCCMP_Pos)) -#define AES_INTENSET_GFMCMP_Pos _U_(1) /**< (AES_INTENSET) GF Multiplication Complete Interrupt Enable Position */ -#define AES_INTENSET_GFMCMP_Msk (_U_(0x1) << AES_INTENSET_GFMCMP_Pos) /**< (AES_INTENSET) GF Multiplication Complete Interrupt Enable Mask */ -#define AES_INTENSET_GFMCMP(value) (AES_INTENSET_GFMCMP_Msk & ((value) << AES_INTENSET_GFMCMP_Pos)) -#define AES_INTENSET_Msk _U_(0x03) /**< (AES_INTENSET) Register Mask */ - - -/* -------- AES_INTFLAG : (AES Offset: 0x07) (R/W 8) Interrupt Flag Status -------- */ -#define AES_INTFLAG_RESETVALUE _U_(0x00) /**< (AES_INTFLAG) Interrupt Flag Status Reset Value */ - -#define AES_INTFLAG_ENCCMP_Pos _U_(0) /**< (AES_INTFLAG) Encryption Complete Position */ -#define AES_INTFLAG_ENCCMP_Msk (_U_(0x1) << AES_INTFLAG_ENCCMP_Pos) /**< (AES_INTFLAG) Encryption Complete Mask */ -#define AES_INTFLAG_ENCCMP(value) (AES_INTFLAG_ENCCMP_Msk & ((value) << AES_INTFLAG_ENCCMP_Pos)) -#define AES_INTFLAG_GFMCMP_Pos _U_(1) /**< (AES_INTFLAG) GF Multiplication Complete Position */ -#define AES_INTFLAG_GFMCMP_Msk (_U_(0x1) << AES_INTFLAG_GFMCMP_Pos) /**< (AES_INTFLAG) GF Multiplication Complete Mask */ -#define AES_INTFLAG_GFMCMP(value) (AES_INTFLAG_GFMCMP_Msk & ((value) << AES_INTFLAG_GFMCMP_Pos)) -#define AES_INTFLAG_Msk _U_(0x03) /**< (AES_INTFLAG) Register Mask */ - - -/* -------- AES_DATABUFPTR : (AES Offset: 0x08) (R/W 8) Data buffer pointer -------- */ -#define AES_DATABUFPTR_RESETVALUE _U_(0x00) /**< (AES_DATABUFPTR) Data buffer pointer Reset Value */ - -#define AES_DATABUFPTR_INDATAPTR_Pos _U_(0) /**< (AES_DATABUFPTR) Input Data Pointer Position */ -#define AES_DATABUFPTR_INDATAPTR_Msk (_U_(0x3) << AES_DATABUFPTR_INDATAPTR_Pos) /**< (AES_DATABUFPTR) Input Data Pointer Mask */ -#define AES_DATABUFPTR_INDATAPTR(value) (AES_DATABUFPTR_INDATAPTR_Msk & ((value) << AES_DATABUFPTR_INDATAPTR_Pos)) -#define AES_DATABUFPTR_Msk _U_(0x03) /**< (AES_DATABUFPTR) Register Mask */ - - -/* -------- AES_DBGCTRL : (AES Offset: 0x09) (R/W 8) Debug control -------- */ -#define AES_DBGCTRL_RESETVALUE _U_(0x00) /**< (AES_DBGCTRL) Debug control Reset Value */ - -#define AES_DBGCTRL_DBGRUN_Pos _U_(0) /**< (AES_DBGCTRL) Debug Run Position */ -#define AES_DBGCTRL_DBGRUN_Msk (_U_(0x1) << AES_DBGCTRL_DBGRUN_Pos) /**< (AES_DBGCTRL) Debug Run Mask */ -#define AES_DBGCTRL_DBGRUN(value) (AES_DBGCTRL_DBGRUN_Msk & ((value) << AES_DBGCTRL_DBGRUN_Pos)) -#define AES_DBGCTRL_Msk _U_(0x01) /**< (AES_DBGCTRL) Register Mask */ - - -/* -------- AES_KEYWORD : (AES Offset: 0x0C) ( /W 32) Keyword n -------- */ -#define AES_KEYWORD_RESETVALUE _U_(0x00) /**< (AES_KEYWORD) Keyword n Reset Value */ - -#define AES_KEYWORD_Msk _U_(0x00000000) /**< (AES_KEYWORD) Register Mask */ - - -/* -------- AES_INDATA : (AES Offset: 0x38) (R/W 32) Indata -------- */ -#define AES_INDATA_RESETVALUE _U_(0x00) /**< (AES_INDATA) Indata Reset Value */ - -#define AES_INDATA_Msk _U_(0x00000000) /**< (AES_INDATA) Register Mask */ - - -/* -------- AES_INTVECTV : (AES Offset: 0x3C) ( /W 32) Initialisation Vector n -------- */ -#define AES_INTVECTV_RESETVALUE _U_(0x00) /**< (AES_INTVECTV) Initialisation Vector n Reset Value */ - -#define AES_INTVECTV_Msk _U_(0x00000000) /**< (AES_INTVECTV) Register Mask */ - - -/* -------- AES_HASHKEY : (AES Offset: 0x5C) (R/W 32) Hash key n -------- */ -#define AES_HASHKEY_RESETVALUE _U_(0x00) /**< (AES_HASHKEY) Hash key n Reset Value */ - -#define AES_HASHKEY_Msk _U_(0x00000000) /**< (AES_HASHKEY) Register Mask */ - - -/* -------- AES_GHASH : (AES Offset: 0x6C) (R/W 32) Galois Hash n -------- */ -#define AES_GHASH_RESETVALUE _U_(0x00) /**< (AES_GHASH) Galois Hash n Reset Value */ - -#define AES_GHASH_Msk _U_(0x00000000) /**< (AES_GHASH) Register Mask */ - - -/* -------- AES_CIPLEN : (AES Offset: 0x80) (R/W 32) Cipher Length -------- */ -#define AES_CIPLEN_RESETVALUE _U_(0x00) /**< (AES_CIPLEN) Cipher Length Reset Value */ - -#define AES_CIPLEN_Msk _U_(0x00000000) /**< (AES_CIPLEN) Register Mask */ - - -/* -------- AES_RANDSEED : (AES Offset: 0x84) (R/W 32) Random Seed -------- */ -#define AES_RANDSEED_RESETVALUE _U_(0x00) /**< (AES_RANDSEED) Random Seed Reset Value */ - -#define AES_RANDSEED_Msk _U_(0x00000000) /**< (AES_RANDSEED) Register Mask */ - - -/** \brief AES register offsets definitions */ -#define AES_CTRLA_REG_OFST (0x00) /**< (AES_CTRLA) Control A Offset */ -#define AES_CTRLB_REG_OFST (0x04) /**< (AES_CTRLB) Control B Offset */ -#define AES_INTENCLR_REG_OFST (0x05) /**< (AES_INTENCLR) Interrupt Enable Clear Offset */ -#define AES_INTENSET_REG_OFST (0x06) /**< (AES_INTENSET) Interrupt Enable Set Offset */ -#define AES_INTFLAG_REG_OFST (0x07) /**< (AES_INTFLAG) Interrupt Flag Status Offset */ -#define AES_DATABUFPTR_REG_OFST (0x08) /**< (AES_DATABUFPTR) Data buffer pointer Offset */ -#define AES_DBGCTRL_REG_OFST (0x09) /**< (AES_DBGCTRL) Debug control Offset */ -#define AES_KEYWORD_REG_OFST (0x0C) /**< (AES_KEYWORD) Keyword n Offset */ -#define AES_INDATA_REG_OFST (0x38) /**< (AES_INDATA) Indata Offset */ -#define AES_INTVECTV_REG_OFST (0x3C) /**< (AES_INTVECTV) Initialisation Vector n Offset */ -#define AES_HASHKEY_REG_OFST (0x5C) /**< (AES_HASHKEY) Hash key n Offset */ -#define AES_GHASH_REG_OFST (0x6C) /**< (AES_GHASH) Galois Hash n Offset */ -#define AES_CIPLEN_REG_OFST (0x80) /**< (AES_CIPLEN) Cipher Length Offset */ -#define AES_RANDSEED_REG_OFST (0x84) /**< (AES_RANDSEED) Random Seed Offset */ - -#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) -/** \brief AES register API structure */ -typedef struct -{ /* Advanced Encryption Standard */ - __IO uint32_t AES_CTRLA; /**< Offset: 0x00 (R/W 32) Control A */ - __IO uint8_t AES_CTRLB; /**< Offset: 0x04 (R/W 8) Control B */ - __IO uint8_t AES_INTENCLR; /**< Offset: 0x05 (R/W 8) Interrupt Enable Clear */ - __IO uint8_t AES_INTENSET; /**< Offset: 0x06 (R/W 8) Interrupt Enable Set */ - __IO uint8_t AES_INTFLAG; /**< Offset: 0x07 (R/W 8) Interrupt Flag Status */ - __IO uint8_t AES_DATABUFPTR; /**< Offset: 0x08 (R/W 8) Data buffer pointer */ - __IO uint8_t AES_DBGCTRL; /**< Offset: 0x09 (R/W 8) Debug control */ - __I uint8_t Reserved1[0x02]; - __O uint32_t AES_KEYWORD[8]; /**< Offset: 0x0C ( /W 32) Keyword n */ - __I uint8_t Reserved2[0x0C]; - __IO uint32_t AES_INDATA; /**< Offset: 0x38 (R/W 32) Indata */ - __O uint32_t AES_INTVECTV[4]; /**< Offset: 0x3C ( /W 32) Initialisation Vector n */ - __I uint8_t Reserved3[0x10]; - __IO uint32_t AES_HASHKEY[4]; /**< Offset: 0x5C (R/W 32) Hash key n */ - __IO uint32_t AES_GHASH[4]; /**< Offset: 0x6C (R/W 32) Galois Hash n */ - __I uint8_t Reserved4[0x04]; - __IO uint32_t AES_CIPLEN; /**< Offset: 0x80 (R/W 32) Cipher Length */ - __IO uint32_t AES_RANDSEED; /**< Offset: 0x84 (R/W 32) Random Seed */ -} aes_registers_t; - - -#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ -#endif /* _SAME54_AES_COMPONENT_H_ */ +/** + * \file + * + * \brief Component description for AES + * + * Copyright (c) 2019 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAME54_AES_COMPONENT_ +#define _SAME54_AES_COMPONENT_ + +/* ========================================================================== */ +/** SOFTWARE API DEFINITION FOR AES */ +/* ========================================================================== */ +/** \addtogroup SAME54_AES Advanced Encryption Standard */ +/*@{*/ + +#define AES_U2238 +#define REV_AES 0x220 + +/* -------- AES_CTRLA : (AES Offset: 0x00) (R/W 32) Control A -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t SWRST:1; /*!< bit: 0 Software Reset */ + uint32_t ENABLE:1; /*!< bit: 1 Enable */ + uint32_t AESMODE:3; /*!< bit: 2.. 4 AES Modes of operation */ + uint32_t CFBS:3; /*!< bit: 5.. 7 Cipher Feedback Block Size */ + uint32_t KEYSIZE:2; /*!< bit: 8.. 9 Encryption Key Size */ + uint32_t CIPHER:1; /*!< bit: 10 Cipher Mode */ + uint32_t STARTMODE:1; /*!< bit: 11 Start Mode Select */ + uint32_t LOD:1; /*!< bit: 12 Last Output Data Mode */ + uint32_t KEYGEN:1; /*!< bit: 13 Last Key Generation */ + uint32_t XORKEY:1; /*!< bit: 14 XOR Key Operation */ + uint32_t :1; /*!< bit: 15 Reserved */ + uint32_t CTYPE:4; /*!< bit: 16..19 Counter Measure Type */ + uint32_t :12; /*!< bit: 20..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} AES_CTRLA_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AES_CTRLA_OFFSET 0x00 /**< \brief (AES_CTRLA offset) Control A */ +#define AES_CTRLA_RESETVALUE _U_(0x00000000) /**< \brief (AES_CTRLA reset_value) Control A */ + +#define AES_CTRLA_SWRST_Pos 0 /**< \brief (AES_CTRLA) Software Reset */ +#define AES_CTRLA_SWRST (_U_(0x1) << AES_CTRLA_SWRST_Pos) +#define AES_CTRLA_ENABLE_Pos 1 /**< \brief (AES_CTRLA) Enable */ +#define AES_CTRLA_ENABLE (_U_(0x1) << AES_CTRLA_ENABLE_Pos) +#define AES_CTRLA_AESMODE_Pos 2 /**< \brief (AES_CTRLA) AES Modes of operation */ +#define AES_CTRLA_AESMODE_Msk (_U_(0x7) << AES_CTRLA_AESMODE_Pos) +#define AES_CTRLA_AESMODE(value) (AES_CTRLA_AESMODE_Msk & ((value) << AES_CTRLA_AESMODE_Pos)) +#define AES_CTRLA_AESMODE_ECB_Val _U_(0x0) /**< \brief (AES_CTRLA) Electronic code book mode */ +#define AES_CTRLA_AESMODE_CBC_Val _U_(0x1) /**< \brief (AES_CTRLA) Cipher block chaining mode */ +#define AES_CTRLA_AESMODE_OFB_Val _U_(0x2) /**< \brief (AES_CTRLA) Output feedback mode */ +#define AES_CTRLA_AESMODE_CFB_Val _U_(0x3) /**< \brief (AES_CTRLA) Cipher feedback mode */ +#define AES_CTRLA_AESMODE_COUNTER_Val _U_(0x4) /**< \brief (AES_CTRLA) Counter mode */ +#define AES_CTRLA_AESMODE_CCM_Val _U_(0x5) /**< \brief (AES_CTRLA) CCM mode */ +#define AES_CTRLA_AESMODE_GCM_Val _U_(0x6) /**< \brief (AES_CTRLA) Galois counter mode */ +#define AES_CTRLA_AESMODE_ECB (AES_CTRLA_AESMODE_ECB_Val << AES_CTRLA_AESMODE_Pos) +#define AES_CTRLA_AESMODE_CBC (AES_CTRLA_AESMODE_CBC_Val << AES_CTRLA_AESMODE_Pos) +#define AES_CTRLA_AESMODE_OFB (AES_CTRLA_AESMODE_OFB_Val << AES_CTRLA_AESMODE_Pos) +#define AES_CTRLA_AESMODE_CFB (AES_CTRLA_AESMODE_CFB_Val << AES_CTRLA_AESMODE_Pos) +#define AES_CTRLA_AESMODE_COUNTER (AES_CTRLA_AESMODE_COUNTER_Val << AES_CTRLA_AESMODE_Pos) +#define AES_CTRLA_AESMODE_CCM (AES_CTRLA_AESMODE_CCM_Val << AES_CTRLA_AESMODE_Pos) +#define AES_CTRLA_AESMODE_GCM (AES_CTRLA_AESMODE_GCM_Val << AES_CTRLA_AESMODE_Pos) +#define AES_CTRLA_CFBS_Pos 5 /**< \brief (AES_CTRLA) Cipher Feedback Block Size */ +#define AES_CTRLA_CFBS_Msk (_U_(0x7) << AES_CTRLA_CFBS_Pos) +#define AES_CTRLA_CFBS(value) (AES_CTRLA_CFBS_Msk & ((value) << AES_CTRLA_CFBS_Pos)) +#define AES_CTRLA_CFBS_128BIT_Val _U_(0x0) /**< \brief (AES_CTRLA) 128-bit Input data block for Encryption/Decryption in Cipher Feedback mode */ +#define AES_CTRLA_CFBS_64BIT_Val _U_(0x1) /**< \brief (AES_CTRLA) 64-bit Input data block for Encryption/Decryption in Cipher Feedback mode */ +#define AES_CTRLA_CFBS_32BIT_Val _U_(0x2) /**< \brief (AES_CTRLA) 32-bit Input data block for Encryption/Decryption in Cipher Feedback mode */ +#define AES_CTRLA_CFBS_16BIT_Val _U_(0x3) /**< \brief (AES_CTRLA) 16-bit Input data block for Encryption/Decryption in Cipher Feedback mode */ +#define AES_CTRLA_CFBS_8BIT_Val _U_(0x4) /**< \brief (AES_CTRLA) 8-bit Input data block for Encryption/Decryption in Cipher Feedback mode */ +#define AES_CTRLA_CFBS_128BIT (AES_CTRLA_CFBS_128BIT_Val << AES_CTRLA_CFBS_Pos) +#define AES_CTRLA_CFBS_64BIT (AES_CTRLA_CFBS_64BIT_Val << AES_CTRLA_CFBS_Pos) +#define AES_CTRLA_CFBS_32BIT (AES_CTRLA_CFBS_32BIT_Val << AES_CTRLA_CFBS_Pos) +#define AES_CTRLA_CFBS_16BIT (AES_CTRLA_CFBS_16BIT_Val << AES_CTRLA_CFBS_Pos) +#define AES_CTRLA_CFBS_8BIT (AES_CTRLA_CFBS_8BIT_Val << AES_CTRLA_CFBS_Pos) +#define AES_CTRLA_KEYSIZE_Pos 8 /**< \brief (AES_CTRLA) Encryption Key Size */ +#define AES_CTRLA_KEYSIZE_Msk (_U_(0x3) << AES_CTRLA_KEYSIZE_Pos) +#define AES_CTRLA_KEYSIZE(value) (AES_CTRLA_KEYSIZE_Msk & ((value) << AES_CTRLA_KEYSIZE_Pos)) +#define AES_CTRLA_KEYSIZE_128BIT_Val _U_(0x0) /**< \brief (AES_CTRLA) 128-bit Key for Encryption / Decryption */ +#define AES_CTRLA_KEYSIZE_192BIT_Val _U_(0x1) /**< \brief (AES_CTRLA) 192-bit Key for Encryption / Decryption */ +#define AES_CTRLA_KEYSIZE_256BIT_Val _U_(0x2) /**< \brief (AES_CTRLA) 256-bit Key for Encryption / Decryption */ +#define AES_CTRLA_KEYSIZE_128BIT (AES_CTRLA_KEYSIZE_128BIT_Val << AES_CTRLA_KEYSIZE_Pos) +#define AES_CTRLA_KEYSIZE_192BIT (AES_CTRLA_KEYSIZE_192BIT_Val << AES_CTRLA_KEYSIZE_Pos) +#define AES_CTRLA_KEYSIZE_256BIT (AES_CTRLA_KEYSIZE_256BIT_Val << AES_CTRLA_KEYSIZE_Pos) +#define AES_CTRLA_CIPHER_Pos 10 /**< \brief (AES_CTRLA) Cipher Mode */ +#define AES_CTRLA_CIPHER (_U_(0x1) << AES_CTRLA_CIPHER_Pos) +#define AES_CTRLA_CIPHER_DEC_Val _U_(0x0) /**< \brief (AES_CTRLA) Decryption */ +#define AES_CTRLA_CIPHER_ENC_Val _U_(0x1) /**< \brief (AES_CTRLA) Encryption */ +#define AES_CTRLA_CIPHER_DEC (AES_CTRLA_CIPHER_DEC_Val << AES_CTRLA_CIPHER_Pos) +#define AES_CTRLA_CIPHER_ENC (AES_CTRLA_CIPHER_ENC_Val << AES_CTRLA_CIPHER_Pos) +#define AES_CTRLA_STARTMODE_Pos 11 /**< \brief (AES_CTRLA) Start Mode Select */ +#define AES_CTRLA_STARTMODE (_U_(0x1) << AES_CTRLA_STARTMODE_Pos) +#define AES_CTRLA_STARTMODE_MANUAL_Val _U_(0x0) /**< \brief (AES_CTRLA) Start Encryption / Decryption in Manual mode */ +#define AES_CTRLA_STARTMODE_AUTO_Val _U_(0x1) /**< \brief (AES_CTRLA) Start Encryption / Decryption in Auto mode */ +#define AES_CTRLA_STARTMODE_MANUAL (AES_CTRLA_STARTMODE_MANUAL_Val << AES_CTRLA_STARTMODE_Pos) +#define AES_CTRLA_STARTMODE_AUTO (AES_CTRLA_STARTMODE_AUTO_Val << AES_CTRLA_STARTMODE_Pos) +#define AES_CTRLA_LOD_Pos 12 /**< \brief (AES_CTRLA) Last Output Data Mode */ +#define AES_CTRLA_LOD (_U_(0x1) << AES_CTRLA_LOD_Pos) +#define AES_CTRLA_LOD_NONE_Val _U_(0x0) /**< \brief (AES_CTRLA) No effect */ +#define AES_CTRLA_LOD_LAST_Val _U_(0x1) /**< \brief (AES_CTRLA) Start encryption in Last Output Data mode */ +#define AES_CTRLA_LOD_NONE (AES_CTRLA_LOD_NONE_Val << AES_CTRLA_LOD_Pos) +#define AES_CTRLA_LOD_LAST (AES_CTRLA_LOD_LAST_Val << AES_CTRLA_LOD_Pos) +#define AES_CTRLA_KEYGEN_Pos 13 /**< \brief (AES_CTRLA) Last Key Generation */ +#define AES_CTRLA_KEYGEN (_U_(0x1) << AES_CTRLA_KEYGEN_Pos) +#define AES_CTRLA_KEYGEN_NONE_Val _U_(0x0) /**< \brief (AES_CTRLA) No effect */ +#define AES_CTRLA_KEYGEN_LAST_Val _U_(0x1) /**< \brief (AES_CTRLA) Start Computation of the last NK words of the expanded key */ +#define AES_CTRLA_KEYGEN_NONE (AES_CTRLA_KEYGEN_NONE_Val << AES_CTRLA_KEYGEN_Pos) +#define AES_CTRLA_KEYGEN_LAST (AES_CTRLA_KEYGEN_LAST_Val << AES_CTRLA_KEYGEN_Pos) +#define AES_CTRLA_XORKEY_Pos 14 /**< \brief (AES_CTRLA) XOR Key Operation */ +#define AES_CTRLA_XORKEY (_U_(0x1) << AES_CTRLA_XORKEY_Pos) +#define AES_CTRLA_XORKEY_NONE_Val _U_(0x0) /**< \brief (AES_CTRLA) No effect */ +#define AES_CTRLA_XORKEY_XOR_Val _U_(0x1) /**< \brief (AES_CTRLA) The user keyword gets XORed with the previous keyword register content. */ +#define AES_CTRLA_XORKEY_NONE (AES_CTRLA_XORKEY_NONE_Val << AES_CTRLA_XORKEY_Pos) +#define AES_CTRLA_XORKEY_XOR (AES_CTRLA_XORKEY_XOR_Val << AES_CTRLA_XORKEY_Pos) +#define AES_CTRLA_CTYPE_Pos 16 /**< \brief (AES_CTRLA) Counter Measure Type */ +#define AES_CTRLA_CTYPE_Msk (_U_(0xF) << AES_CTRLA_CTYPE_Pos) +#define AES_CTRLA_CTYPE(value) (AES_CTRLA_CTYPE_Msk & ((value) << AES_CTRLA_CTYPE_Pos)) +#define AES_CTRLA_MASK _U_(0x000F7FFF) /**< \brief (AES_CTRLA) MASK Register */ + +/* -------- AES_CTRLB : (AES Offset: 0x04) (R/W 8) Control B -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t START:1; /*!< bit: 0 Start Encryption/Decryption */ + uint8_t NEWMSG:1; /*!< bit: 1 New message */ + uint8_t EOM:1; /*!< bit: 2 End of message */ + uint8_t GFMUL:1; /*!< bit: 3 GF Multiplication */ + uint8_t :4; /*!< bit: 4.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} AES_CTRLB_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AES_CTRLB_OFFSET 0x04 /**< \brief (AES_CTRLB offset) Control B */ +#define AES_CTRLB_RESETVALUE _U_(0x00) /**< \brief (AES_CTRLB reset_value) Control B */ + +#define AES_CTRLB_START_Pos 0 /**< \brief (AES_CTRLB) Start Encryption/Decryption */ +#define AES_CTRLB_START (_U_(0x1) << AES_CTRLB_START_Pos) +#define AES_CTRLB_NEWMSG_Pos 1 /**< \brief (AES_CTRLB) New message */ +#define AES_CTRLB_NEWMSG (_U_(0x1) << AES_CTRLB_NEWMSG_Pos) +#define AES_CTRLB_EOM_Pos 2 /**< \brief (AES_CTRLB) End of message */ +#define AES_CTRLB_EOM (_U_(0x1) << AES_CTRLB_EOM_Pos) +#define AES_CTRLB_GFMUL_Pos 3 /**< \brief (AES_CTRLB) GF Multiplication */ +#define AES_CTRLB_GFMUL (_U_(0x1) << AES_CTRLB_GFMUL_Pos) +#define AES_CTRLB_MASK _U_(0x0F) /**< \brief (AES_CTRLB) MASK Register */ + +/* -------- AES_INTENCLR : (AES Offset: 0x05) (R/W 8) Interrupt Enable Clear -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t ENCCMP:1; /*!< bit: 0 Encryption Complete Interrupt Enable */ + uint8_t GFMCMP:1; /*!< bit: 1 GF Multiplication Complete Interrupt Enable */ + uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} AES_INTENCLR_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AES_INTENCLR_OFFSET 0x05 /**< \brief (AES_INTENCLR offset) Interrupt Enable Clear */ +#define AES_INTENCLR_RESETVALUE _U_(0x00) /**< \brief (AES_INTENCLR reset_value) Interrupt Enable Clear */ + +#define AES_INTENCLR_ENCCMP_Pos 0 /**< \brief (AES_INTENCLR) Encryption Complete Interrupt Enable */ +#define AES_INTENCLR_ENCCMP (_U_(0x1) << AES_INTENCLR_ENCCMP_Pos) +#define AES_INTENCLR_GFMCMP_Pos 1 /**< \brief (AES_INTENCLR) GF Multiplication Complete Interrupt Enable */ +#define AES_INTENCLR_GFMCMP (_U_(0x1) << AES_INTENCLR_GFMCMP_Pos) +#define AES_INTENCLR_MASK _U_(0x03) /**< \brief (AES_INTENCLR) MASK Register */ + +/* -------- AES_INTENSET : (AES Offset: 0x06) (R/W 8) Interrupt Enable Set -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t ENCCMP:1; /*!< bit: 0 Encryption Complete Interrupt Enable */ + uint8_t GFMCMP:1; /*!< bit: 1 GF Multiplication Complete Interrupt Enable */ + uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} AES_INTENSET_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AES_INTENSET_OFFSET 0x06 /**< \brief (AES_INTENSET offset) Interrupt Enable Set */ +#define AES_INTENSET_RESETVALUE _U_(0x00) /**< \brief (AES_INTENSET reset_value) Interrupt Enable Set */ + +#define AES_INTENSET_ENCCMP_Pos 0 /**< \brief (AES_INTENSET) Encryption Complete Interrupt Enable */ +#define AES_INTENSET_ENCCMP (_U_(0x1) << AES_INTENSET_ENCCMP_Pos) +#define AES_INTENSET_GFMCMP_Pos 1 /**< \brief (AES_INTENSET) GF Multiplication Complete Interrupt Enable */ +#define AES_INTENSET_GFMCMP (_U_(0x1) << AES_INTENSET_GFMCMP_Pos) +#define AES_INTENSET_MASK _U_(0x03) /**< \brief (AES_INTENSET) MASK Register */ + +/* -------- AES_INTFLAG : (AES Offset: 0x07) (R/W 8) Interrupt Flag Status -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { // __I to avoid read-modify-write on write-to-clear register + struct { + __I uint8_t ENCCMP:1; /*!< bit: 0 Encryption Complete */ + __I uint8_t GFMCMP:1; /*!< bit: 1 GF Multiplication Complete */ + __I uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} AES_INTFLAG_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AES_INTFLAG_OFFSET 0x07 /**< \brief (AES_INTFLAG offset) Interrupt Flag Status */ +#define AES_INTFLAG_RESETVALUE _U_(0x00) /**< \brief (AES_INTFLAG reset_value) Interrupt Flag Status */ + +#define AES_INTFLAG_ENCCMP_Pos 0 /**< \brief (AES_INTFLAG) Encryption Complete */ +#define AES_INTFLAG_ENCCMP (_U_(0x1) << AES_INTFLAG_ENCCMP_Pos) +#define AES_INTFLAG_GFMCMP_Pos 1 /**< \brief (AES_INTFLAG) GF Multiplication Complete */ +#define AES_INTFLAG_GFMCMP (_U_(0x1) << AES_INTFLAG_GFMCMP_Pos) +#define AES_INTFLAG_MASK _U_(0x03) /**< \brief (AES_INTFLAG) MASK Register */ + +/* -------- AES_DATABUFPTR : (AES Offset: 0x08) (R/W 8) Data buffer pointer -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t INDATAPTR:2; /*!< bit: 0.. 1 Input Data Pointer */ + uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} AES_DATABUFPTR_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AES_DATABUFPTR_OFFSET 0x08 /**< \brief (AES_DATABUFPTR offset) Data buffer pointer */ +#define AES_DATABUFPTR_RESETVALUE _U_(0x00) /**< \brief (AES_DATABUFPTR reset_value) Data buffer pointer */ + +#define AES_DATABUFPTR_INDATAPTR_Pos 0 /**< \brief (AES_DATABUFPTR) Input Data Pointer */ +#define AES_DATABUFPTR_INDATAPTR_Msk (_U_(0x3) << AES_DATABUFPTR_INDATAPTR_Pos) +#define AES_DATABUFPTR_INDATAPTR(value) (AES_DATABUFPTR_INDATAPTR_Msk & ((value) << AES_DATABUFPTR_INDATAPTR_Pos)) +#define AES_DATABUFPTR_MASK _U_(0x03) /**< \brief (AES_DATABUFPTR) MASK Register */ + +/* -------- AES_DBGCTRL : (AES Offset: 0x09) (R/W 8) Debug control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t DBGRUN:1; /*!< bit: 0 Debug Run */ + uint8_t :7; /*!< bit: 1.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} AES_DBGCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AES_DBGCTRL_OFFSET 0x09 /**< \brief (AES_DBGCTRL offset) Debug control */ +#define AES_DBGCTRL_RESETVALUE _U_(0x00) /**< \brief (AES_DBGCTRL reset_value) Debug control */ + +#define AES_DBGCTRL_DBGRUN_Pos 0 /**< \brief (AES_DBGCTRL) Debug Run */ +#define AES_DBGCTRL_DBGRUN (_U_(0x1) << AES_DBGCTRL_DBGRUN_Pos) +#define AES_DBGCTRL_MASK _U_(0x01) /**< \brief (AES_DBGCTRL) MASK Register */ + +/* -------- AES_KEYWORD : (AES Offset: 0x0C) ( /W 32) Keyword n -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + uint32_t reg; /*!< Type used for register access */ +} AES_KEYWORD_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AES_KEYWORD_OFFSET 0x0C /**< \brief (AES_KEYWORD offset) Keyword n */ +#define AES_KEYWORD_RESETVALUE _U_(0x00000000) /**< \brief (AES_KEYWORD reset_value) Keyword n */ +#define AES_KEYWORD_MASK _U_(0xFFFFFFFF) /**< \brief (AES_KEYWORD) MASK Register */ + +/* -------- AES_INDATA : (AES Offset: 0x38) (R/W 32) Indata -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + uint32_t reg; /*!< Type used for register access */ +} AES_INDATA_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AES_INDATA_OFFSET 0x38 /**< \brief (AES_INDATA offset) Indata */ +#define AES_INDATA_RESETVALUE _U_(0x00000000) /**< \brief (AES_INDATA reset_value) Indata */ +#define AES_INDATA_MASK _U_(0xFFFFFFFF) /**< \brief (AES_INDATA) MASK Register */ + +/* -------- AES_INTVECTV : (AES Offset: 0x3C) ( /W 32) Initialisation Vector n -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + uint32_t reg; /*!< Type used for register access */ +} AES_INTVECTV_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AES_INTVECTV_OFFSET 0x3C /**< \brief (AES_INTVECTV offset) Initialisation Vector n */ +#define AES_INTVECTV_RESETVALUE _U_(0x00000000) /**< \brief (AES_INTVECTV reset_value) Initialisation Vector n */ +#define AES_INTVECTV_MASK _U_(0xFFFFFFFF) /**< \brief (AES_INTVECTV) MASK Register */ + +/* -------- AES_HASHKEY : (AES Offset: 0x5C) (R/W 32) Hash key n -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + uint32_t reg; /*!< Type used for register access */ +} AES_HASHKEY_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AES_HASHKEY_OFFSET 0x5C /**< \brief (AES_HASHKEY offset) Hash key n */ +#define AES_HASHKEY_RESETVALUE _U_(0x00000000) /**< \brief (AES_HASHKEY reset_value) Hash key n */ +#define AES_HASHKEY_MASK _U_(0xFFFFFFFF) /**< \brief (AES_HASHKEY) MASK Register */ + +/* -------- AES_GHASH : (AES Offset: 0x6C) (R/W 32) Galois Hash n -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + uint32_t reg; /*!< Type used for register access */ +} AES_GHASH_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AES_GHASH_OFFSET 0x6C /**< \brief (AES_GHASH offset) Galois Hash n */ +#define AES_GHASH_RESETVALUE _U_(0x00000000) /**< \brief (AES_GHASH reset_value) Galois Hash n */ +#define AES_GHASH_MASK _U_(0xFFFFFFFF) /**< \brief (AES_GHASH) MASK Register */ + +/* -------- AES_CIPLEN : (AES Offset: 0x80) (R/W 32) Cipher Length -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + uint32_t reg; /*!< Type used for register access */ +} AES_CIPLEN_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AES_CIPLEN_OFFSET 0x80 /**< \brief (AES_CIPLEN offset) Cipher Length */ +#define AES_CIPLEN_RESETVALUE _U_(0x00000000) /**< \brief (AES_CIPLEN reset_value) Cipher Length */ +#define AES_CIPLEN_MASK _U_(0xFFFFFFFF) /**< \brief (AES_CIPLEN) MASK Register */ + +/* -------- AES_RANDSEED : (AES Offset: 0x84) (R/W 32) Random Seed -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + uint32_t reg; /*!< Type used for register access */ +} AES_RANDSEED_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AES_RANDSEED_OFFSET 0x84 /**< \brief (AES_RANDSEED offset) Random Seed */ +#define AES_RANDSEED_RESETVALUE _U_(0x00000000) /**< \brief (AES_RANDSEED reset_value) Random Seed */ +#define AES_RANDSEED_MASK _U_(0xFFFFFFFF) /**< \brief (AES_RANDSEED) MASK Register */ + +/** \brief AES hardware registers */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef struct { + __IO AES_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) Control A */ + __IO AES_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 8) Control B */ + __IO AES_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x05 (R/W 8) Interrupt Enable Clear */ + __IO AES_INTENSET_Type INTENSET; /**< \brief Offset: 0x06 (R/W 8) Interrupt Enable Set */ + __IO AES_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x07 (R/W 8) Interrupt Flag Status */ + __IO AES_DATABUFPTR_Type DATABUFPTR; /**< \brief Offset: 0x08 (R/W 8) Data buffer pointer */ + __IO AES_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x09 (R/W 8) Debug control */ + RoReg8 Reserved1[0x2]; + __O AES_KEYWORD_Type KEYWORD[8]; /**< \brief Offset: 0x0C ( /W 32) Keyword n */ + RoReg8 Reserved2[0xC]; + __IO AES_INDATA_Type INDATA; /**< \brief Offset: 0x38 (R/W 32) Indata */ + __O AES_INTVECTV_Type INTVECTV[4]; /**< \brief Offset: 0x3C ( /W 32) Initialisation Vector n */ + RoReg8 Reserved3[0x10]; + __IO AES_HASHKEY_Type HASHKEY[4]; /**< \brief Offset: 0x5C (R/W 32) Hash key n */ + __IO AES_GHASH_Type GHASH[4]; /**< \brief Offset: 0x6C (R/W 32) Galois Hash n */ + RoReg8 Reserved4[0x4]; + __IO AES_CIPLEN_Type CIPLEN; /**< \brief Offset: 0x80 (R/W 32) Cipher Length */ + __IO AES_RANDSEED_Type RANDSEED; /**< \brief Offset: 0x84 (R/W 32) Random Seed */ +} Aes; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/*@}*/ + +#endif /* _SAME54_AES_COMPONENT_ */ diff --git a/arch/arm/SAME54/SAME54A/mcu/inc/component/can.h b/arch/arm/SAME54/SAME54A/mcu/inc/component/can.h index 970b5f37..48b3cab5 100644 --- a/arch/arm/SAME54/SAME54A/mcu/inc/component/can.h +++ b/arch/arm/SAME54/SAME54A/mcu/inc/component/can.h @@ -1,2527 +1,3187 @@ -/** - * \brief Component description for CAN - * - * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries. - * - * Subject to your compliance with these terms, you may use Microchip software and any derivatives - * exclusively with Microchip products. It is your responsibility to comply with third party license - * terms applicable to your use of third party software (including open source software) that may - * accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, - * APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND - * FITNESS FOR A PARTICULAR PURPOSE. - * - * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF - * MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT - * EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - */ - -/* file generated from device description version 2020-03-12T17:27:04Z */ -#ifndef _SAME54_CAN_COMPONENT_H_ -#define _SAME54_CAN_COMPONENT_H_ - -/* ************************************************************************** */ -/* SOFTWARE API DEFINITION FOR CAN */ -/* ************************************************************************** */ - -/* -------- CAN_RXBE_0 : (CAN Offset: 0x00) (R/W 32) Rx Buffer Element 0 -------- */ -#define CAN_RXBE_0_ID_Pos _U_(0) /**< (CAN_RXBE_0) Identifier Position */ -#define CAN_RXBE_0_ID_Msk (_U_(0x1FFFFFFF) << CAN_RXBE_0_ID_Pos) /**< (CAN_RXBE_0) Identifier Mask */ -#define CAN_RXBE_0_ID(value) (CAN_RXBE_0_ID_Msk & ((value) << CAN_RXBE_0_ID_Pos)) -#define CAN_RXBE_0_RTR_Pos _U_(29) /**< (CAN_RXBE_0) Remote Transmission Request Position */ -#define CAN_RXBE_0_RTR_Msk (_U_(0x1) << CAN_RXBE_0_RTR_Pos) /**< (CAN_RXBE_0) Remote Transmission Request Mask */ -#define CAN_RXBE_0_RTR(value) (CAN_RXBE_0_RTR_Msk & ((value) << CAN_RXBE_0_RTR_Pos)) -#define CAN_RXBE_0_XTD_Pos _U_(30) /**< (CAN_RXBE_0) Extended Identifier Position */ -#define CAN_RXBE_0_XTD_Msk (_U_(0x1) << CAN_RXBE_0_XTD_Pos) /**< (CAN_RXBE_0) Extended Identifier Mask */ -#define CAN_RXBE_0_XTD(value) (CAN_RXBE_0_XTD_Msk & ((value) << CAN_RXBE_0_XTD_Pos)) -#define CAN_RXBE_0_ESI_Pos _U_(31) /**< (CAN_RXBE_0) Error State Indicator Position */ -#define CAN_RXBE_0_ESI_Msk (_U_(0x1) << CAN_RXBE_0_ESI_Pos) /**< (CAN_RXBE_0) Error State Indicator Mask */ -#define CAN_RXBE_0_ESI(value) (CAN_RXBE_0_ESI_Msk & ((value) << CAN_RXBE_0_ESI_Pos)) -#define CAN_RXBE_0_Msk _U_(0xFFFFFFFF) /**< (CAN_RXBE_0) Register Mask */ - - -/* -------- CAN_RXBE_1 : (CAN Offset: 0x04) (R/W 32) Rx Buffer Element 1 -------- */ -#define CAN_RXBE_1_RXTS_Pos _U_(0) /**< (CAN_RXBE_1) Rx Timestamp Position */ -#define CAN_RXBE_1_RXTS_Msk (_U_(0xFFFF) << CAN_RXBE_1_RXTS_Pos) /**< (CAN_RXBE_1) Rx Timestamp Mask */ -#define CAN_RXBE_1_RXTS(value) (CAN_RXBE_1_RXTS_Msk & ((value) << CAN_RXBE_1_RXTS_Pos)) -#define CAN_RXBE_1_DLC_Pos _U_(16) /**< (CAN_RXBE_1) Data Length Code Position */ -#define CAN_RXBE_1_DLC_Msk (_U_(0xF) << CAN_RXBE_1_DLC_Pos) /**< (CAN_RXBE_1) Data Length Code Mask */ -#define CAN_RXBE_1_DLC(value) (CAN_RXBE_1_DLC_Msk & ((value) << CAN_RXBE_1_DLC_Pos)) -#define CAN_RXBE_1_BRS_Pos _U_(20) /**< (CAN_RXBE_1) Bit Rate Switch Position */ -#define CAN_RXBE_1_BRS_Msk (_U_(0x1) << CAN_RXBE_1_BRS_Pos) /**< (CAN_RXBE_1) Bit Rate Switch Mask */ -#define CAN_RXBE_1_BRS(value) (CAN_RXBE_1_BRS_Msk & ((value) << CAN_RXBE_1_BRS_Pos)) -#define CAN_RXBE_1_FDF_Pos _U_(21) /**< (CAN_RXBE_1) FD Format Position */ -#define CAN_RXBE_1_FDF_Msk (_U_(0x1) << CAN_RXBE_1_FDF_Pos) /**< (CAN_RXBE_1) FD Format Mask */ -#define CAN_RXBE_1_FDF(value) (CAN_RXBE_1_FDF_Msk & ((value) << CAN_RXBE_1_FDF_Pos)) -#define CAN_RXBE_1_FIDX_Pos _U_(24) /**< (CAN_RXBE_1) Filter Index Position */ -#define CAN_RXBE_1_FIDX_Msk (_U_(0x7F) << CAN_RXBE_1_FIDX_Pos) /**< (CAN_RXBE_1) Filter Index Mask */ -#define CAN_RXBE_1_FIDX(value) (CAN_RXBE_1_FIDX_Msk & ((value) << CAN_RXBE_1_FIDX_Pos)) -#define CAN_RXBE_1_ANMF_Pos _U_(31) /**< (CAN_RXBE_1) Accepted Non-matching Frame Position */ -#define CAN_RXBE_1_ANMF_Msk (_U_(0x1) << CAN_RXBE_1_ANMF_Pos) /**< (CAN_RXBE_1) Accepted Non-matching Frame Mask */ -#define CAN_RXBE_1_ANMF(value) (CAN_RXBE_1_ANMF_Msk & ((value) << CAN_RXBE_1_ANMF_Pos)) -#define CAN_RXBE_1_Msk _U_(0xFF3FFFFF) /**< (CAN_RXBE_1) Register Mask */ - - -/* -------- CAN_RXBE_DATA : (CAN Offset: 0x08) (R/W 32) Rx Buffer Element Data -------- */ -#define CAN_RXBE_DATA_DB0_Pos _U_(0) /**< (CAN_RXBE_DATA) Data Byte 0 Position */ -#define CAN_RXBE_DATA_DB0_Msk (_U_(0xFF) << CAN_RXBE_DATA_DB0_Pos) /**< (CAN_RXBE_DATA) Data Byte 0 Mask */ -#define CAN_RXBE_DATA_DB0(value) (CAN_RXBE_DATA_DB0_Msk & ((value) << CAN_RXBE_DATA_DB0_Pos)) -#define CAN_RXBE_DATA_DB1_Pos _U_(8) /**< (CAN_RXBE_DATA) Data Byte 1 Position */ -#define CAN_RXBE_DATA_DB1_Msk (_U_(0xFF) << CAN_RXBE_DATA_DB1_Pos) /**< (CAN_RXBE_DATA) Data Byte 1 Mask */ -#define CAN_RXBE_DATA_DB1(value) (CAN_RXBE_DATA_DB1_Msk & ((value) << CAN_RXBE_DATA_DB1_Pos)) -#define CAN_RXBE_DATA_DB2_Pos _U_(16) /**< (CAN_RXBE_DATA) Data Byte 2 Position */ -#define CAN_RXBE_DATA_DB2_Msk (_U_(0xFF) << CAN_RXBE_DATA_DB2_Pos) /**< (CAN_RXBE_DATA) Data Byte 2 Mask */ -#define CAN_RXBE_DATA_DB2(value) (CAN_RXBE_DATA_DB2_Msk & ((value) << CAN_RXBE_DATA_DB2_Pos)) -#define CAN_RXBE_DATA_DB3_Pos _U_(24) /**< (CAN_RXBE_DATA) Data Byte 3 Position */ -#define CAN_RXBE_DATA_DB3_Msk (_U_(0xFF) << CAN_RXBE_DATA_DB3_Pos) /**< (CAN_RXBE_DATA) Data Byte 3 Mask */ -#define CAN_RXBE_DATA_DB3(value) (CAN_RXBE_DATA_DB3_Msk & ((value) << CAN_RXBE_DATA_DB3_Pos)) -#define CAN_RXBE_DATA_Msk _U_(0xFFFFFFFF) /**< (CAN_RXBE_DATA) Register Mask */ - - -/* -------- CAN_RXF0E_0 : (CAN Offset: 0x00) (R/W 32) Rx FIFO 0 Element 0 -------- */ -#define CAN_RXF0E_0_ID_Pos _U_(0) /**< (CAN_RXF0E_0) Identifier Position */ -#define CAN_RXF0E_0_ID_Msk (_U_(0x1FFFFFFF) << CAN_RXF0E_0_ID_Pos) /**< (CAN_RXF0E_0) Identifier Mask */ -#define CAN_RXF0E_0_ID(value) (CAN_RXF0E_0_ID_Msk & ((value) << CAN_RXF0E_0_ID_Pos)) -#define CAN_RXF0E_0_RTR_Pos _U_(29) /**< (CAN_RXF0E_0) Remote Transmission Request Position */ -#define CAN_RXF0E_0_RTR_Msk (_U_(0x1) << CAN_RXF0E_0_RTR_Pos) /**< (CAN_RXF0E_0) Remote Transmission Request Mask */ -#define CAN_RXF0E_0_RTR(value) (CAN_RXF0E_0_RTR_Msk & ((value) << CAN_RXF0E_0_RTR_Pos)) -#define CAN_RXF0E_0_XTD_Pos _U_(30) /**< (CAN_RXF0E_0) Extended Identifier Position */ -#define CAN_RXF0E_0_XTD_Msk (_U_(0x1) << CAN_RXF0E_0_XTD_Pos) /**< (CAN_RXF0E_0) Extended Identifier Mask */ -#define CAN_RXF0E_0_XTD(value) (CAN_RXF0E_0_XTD_Msk & ((value) << CAN_RXF0E_0_XTD_Pos)) -#define CAN_RXF0E_0_ESI_Pos _U_(31) /**< (CAN_RXF0E_0) Error State Indicator Position */ -#define CAN_RXF0E_0_ESI_Msk (_U_(0x1) << CAN_RXF0E_0_ESI_Pos) /**< (CAN_RXF0E_0) Error State Indicator Mask */ -#define CAN_RXF0E_0_ESI(value) (CAN_RXF0E_0_ESI_Msk & ((value) << CAN_RXF0E_0_ESI_Pos)) -#define CAN_RXF0E_0_Msk _U_(0xFFFFFFFF) /**< (CAN_RXF0E_0) Register Mask */ - - -/* -------- CAN_RXF0E_1 : (CAN Offset: 0x04) (R/W 32) Rx FIFO 0 Element 1 -------- */ -#define CAN_RXF0E_1_RXTS_Pos _U_(0) /**< (CAN_RXF0E_1) Rx Timestamp Position */ -#define CAN_RXF0E_1_RXTS_Msk (_U_(0xFFFF) << CAN_RXF0E_1_RXTS_Pos) /**< (CAN_RXF0E_1) Rx Timestamp Mask */ -#define CAN_RXF0E_1_RXTS(value) (CAN_RXF0E_1_RXTS_Msk & ((value) << CAN_RXF0E_1_RXTS_Pos)) -#define CAN_RXF0E_1_DLC_Pos _U_(16) /**< (CAN_RXF0E_1) Data Length Code Position */ -#define CAN_RXF0E_1_DLC_Msk (_U_(0xF) << CAN_RXF0E_1_DLC_Pos) /**< (CAN_RXF0E_1) Data Length Code Mask */ -#define CAN_RXF0E_1_DLC(value) (CAN_RXF0E_1_DLC_Msk & ((value) << CAN_RXF0E_1_DLC_Pos)) -#define CAN_RXF0E_1_BRS_Pos _U_(20) /**< (CAN_RXF0E_1) Bit Rate Switch Position */ -#define CAN_RXF0E_1_BRS_Msk (_U_(0x1) << CAN_RXF0E_1_BRS_Pos) /**< (CAN_RXF0E_1) Bit Rate Switch Mask */ -#define CAN_RXF0E_1_BRS(value) (CAN_RXF0E_1_BRS_Msk & ((value) << CAN_RXF0E_1_BRS_Pos)) -#define CAN_RXF0E_1_FDF_Pos _U_(21) /**< (CAN_RXF0E_1) FD Format Position */ -#define CAN_RXF0E_1_FDF_Msk (_U_(0x1) << CAN_RXF0E_1_FDF_Pos) /**< (CAN_RXF0E_1) FD Format Mask */ -#define CAN_RXF0E_1_FDF(value) (CAN_RXF0E_1_FDF_Msk & ((value) << CAN_RXF0E_1_FDF_Pos)) -#define CAN_RXF0E_1_FIDX_Pos _U_(24) /**< (CAN_RXF0E_1) Filter Index Position */ -#define CAN_RXF0E_1_FIDX_Msk (_U_(0x7F) << CAN_RXF0E_1_FIDX_Pos) /**< (CAN_RXF0E_1) Filter Index Mask */ -#define CAN_RXF0E_1_FIDX(value) (CAN_RXF0E_1_FIDX_Msk & ((value) << CAN_RXF0E_1_FIDX_Pos)) -#define CAN_RXF0E_1_ANMF_Pos _U_(31) /**< (CAN_RXF0E_1) Accepted Non-matching Frame Position */ -#define CAN_RXF0E_1_ANMF_Msk (_U_(0x1) << CAN_RXF0E_1_ANMF_Pos) /**< (CAN_RXF0E_1) Accepted Non-matching Frame Mask */ -#define CAN_RXF0E_1_ANMF(value) (CAN_RXF0E_1_ANMF_Msk & ((value) << CAN_RXF0E_1_ANMF_Pos)) -#define CAN_RXF0E_1_Msk _U_(0xFF3FFFFF) /**< (CAN_RXF0E_1) Register Mask */ - - -/* -------- CAN_RXF0E_DATA : (CAN Offset: 0x08) (R/W 32) Rx FIFO 0 Element Data -------- */ -#define CAN_RXF0E_DATA_DB0_Pos _U_(0) /**< (CAN_RXF0E_DATA) Data Byte 0 Position */ -#define CAN_RXF0E_DATA_DB0_Msk (_U_(0xFF) << CAN_RXF0E_DATA_DB0_Pos) /**< (CAN_RXF0E_DATA) Data Byte 0 Mask */ -#define CAN_RXF0E_DATA_DB0(value) (CAN_RXF0E_DATA_DB0_Msk & ((value) << CAN_RXF0E_DATA_DB0_Pos)) -#define CAN_RXF0E_DATA_DB1_Pos _U_(8) /**< (CAN_RXF0E_DATA) Data Byte 1 Position */ -#define CAN_RXF0E_DATA_DB1_Msk (_U_(0xFF) << CAN_RXF0E_DATA_DB1_Pos) /**< (CAN_RXF0E_DATA) Data Byte 1 Mask */ -#define CAN_RXF0E_DATA_DB1(value) (CAN_RXF0E_DATA_DB1_Msk & ((value) << CAN_RXF0E_DATA_DB1_Pos)) -#define CAN_RXF0E_DATA_DB2_Pos _U_(16) /**< (CAN_RXF0E_DATA) Data Byte 2 Position */ -#define CAN_RXF0E_DATA_DB2_Msk (_U_(0xFF) << CAN_RXF0E_DATA_DB2_Pos) /**< (CAN_RXF0E_DATA) Data Byte 2 Mask */ -#define CAN_RXF0E_DATA_DB2(value) (CAN_RXF0E_DATA_DB2_Msk & ((value) << CAN_RXF0E_DATA_DB2_Pos)) -#define CAN_RXF0E_DATA_DB3_Pos _U_(24) /**< (CAN_RXF0E_DATA) Data Byte 3 Position */ -#define CAN_RXF0E_DATA_DB3_Msk (_U_(0xFF) << CAN_RXF0E_DATA_DB3_Pos) /**< (CAN_RXF0E_DATA) Data Byte 3 Mask */ -#define CAN_RXF0E_DATA_DB3(value) (CAN_RXF0E_DATA_DB3_Msk & ((value) << CAN_RXF0E_DATA_DB3_Pos)) -#define CAN_RXF0E_DATA_Msk _U_(0xFFFFFFFF) /**< (CAN_RXF0E_DATA) Register Mask */ - - -/* -------- CAN_RXF1E_0 : (CAN Offset: 0x00) (R/W 32) Rx FIFO 1 Element 0 -------- */ -#define CAN_RXF1E_0_ID_Pos _U_(0) /**< (CAN_RXF1E_0) Identifier Position */ -#define CAN_RXF1E_0_ID_Msk (_U_(0x1FFFFFFF) << CAN_RXF1E_0_ID_Pos) /**< (CAN_RXF1E_0) Identifier Mask */ -#define CAN_RXF1E_0_ID(value) (CAN_RXF1E_0_ID_Msk & ((value) << CAN_RXF1E_0_ID_Pos)) -#define CAN_RXF1E_0_RTR_Pos _U_(29) /**< (CAN_RXF1E_0) Remote Transmission Request Position */ -#define CAN_RXF1E_0_RTR_Msk (_U_(0x1) << CAN_RXF1E_0_RTR_Pos) /**< (CAN_RXF1E_0) Remote Transmission Request Mask */ -#define CAN_RXF1E_0_RTR(value) (CAN_RXF1E_0_RTR_Msk & ((value) << CAN_RXF1E_0_RTR_Pos)) -#define CAN_RXF1E_0_XTD_Pos _U_(30) /**< (CAN_RXF1E_0) Extended Identifier Position */ -#define CAN_RXF1E_0_XTD_Msk (_U_(0x1) << CAN_RXF1E_0_XTD_Pos) /**< (CAN_RXF1E_0) Extended Identifier Mask */ -#define CAN_RXF1E_0_XTD(value) (CAN_RXF1E_0_XTD_Msk & ((value) << CAN_RXF1E_0_XTD_Pos)) -#define CAN_RXF1E_0_ESI_Pos _U_(31) /**< (CAN_RXF1E_0) Error State Indicator Position */ -#define CAN_RXF1E_0_ESI_Msk (_U_(0x1) << CAN_RXF1E_0_ESI_Pos) /**< (CAN_RXF1E_0) Error State Indicator Mask */ -#define CAN_RXF1E_0_ESI(value) (CAN_RXF1E_0_ESI_Msk & ((value) << CAN_RXF1E_0_ESI_Pos)) -#define CAN_RXF1E_0_Msk _U_(0xFFFFFFFF) /**< (CAN_RXF1E_0) Register Mask */ - - -/* -------- CAN_RXF1E_1 : (CAN Offset: 0x04) (R/W 32) Rx FIFO 1 Element 1 -------- */ -#define CAN_RXF1E_1_RXTS_Pos _U_(0) /**< (CAN_RXF1E_1) Rx Timestamp Position */ -#define CAN_RXF1E_1_RXTS_Msk (_U_(0xFFFF) << CAN_RXF1E_1_RXTS_Pos) /**< (CAN_RXF1E_1) Rx Timestamp Mask */ -#define CAN_RXF1E_1_RXTS(value) (CAN_RXF1E_1_RXTS_Msk & ((value) << CAN_RXF1E_1_RXTS_Pos)) -#define CAN_RXF1E_1_DLC_Pos _U_(16) /**< (CAN_RXF1E_1) Data Length Code Position */ -#define CAN_RXF1E_1_DLC_Msk (_U_(0xF) << CAN_RXF1E_1_DLC_Pos) /**< (CAN_RXF1E_1) Data Length Code Mask */ -#define CAN_RXF1E_1_DLC(value) (CAN_RXF1E_1_DLC_Msk & ((value) << CAN_RXF1E_1_DLC_Pos)) -#define CAN_RXF1E_1_BRS_Pos _U_(20) /**< (CAN_RXF1E_1) Bit Rate Switch Position */ -#define CAN_RXF1E_1_BRS_Msk (_U_(0x1) << CAN_RXF1E_1_BRS_Pos) /**< (CAN_RXF1E_1) Bit Rate Switch Mask */ -#define CAN_RXF1E_1_BRS(value) (CAN_RXF1E_1_BRS_Msk & ((value) << CAN_RXF1E_1_BRS_Pos)) -#define CAN_RXF1E_1_FDF_Pos _U_(21) /**< (CAN_RXF1E_1) FD Format Position */ -#define CAN_RXF1E_1_FDF_Msk (_U_(0x1) << CAN_RXF1E_1_FDF_Pos) /**< (CAN_RXF1E_1) FD Format Mask */ -#define CAN_RXF1E_1_FDF(value) (CAN_RXF1E_1_FDF_Msk & ((value) << CAN_RXF1E_1_FDF_Pos)) -#define CAN_RXF1E_1_FIDX_Pos _U_(24) /**< (CAN_RXF1E_1) Filter Index Position */ -#define CAN_RXF1E_1_FIDX_Msk (_U_(0x7F) << CAN_RXF1E_1_FIDX_Pos) /**< (CAN_RXF1E_1) Filter Index Mask */ -#define CAN_RXF1E_1_FIDX(value) (CAN_RXF1E_1_FIDX_Msk & ((value) << CAN_RXF1E_1_FIDX_Pos)) -#define CAN_RXF1E_1_ANMF_Pos _U_(31) /**< (CAN_RXF1E_1) Accepted Non-matching Frame Position */ -#define CAN_RXF1E_1_ANMF_Msk (_U_(0x1) << CAN_RXF1E_1_ANMF_Pos) /**< (CAN_RXF1E_1) Accepted Non-matching Frame Mask */ -#define CAN_RXF1E_1_ANMF(value) (CAN_RXF1E_1_ANMF_Msk & ((value) << CAN_RXF1E_1_ANMF_Pos)) -#define CAN_RXF1E_1_Msk _U_(0xFF3FFFFF) /**< (CAN_RXF1E_1) Register Mask */ - - -/* -------- CAN_RXF1E_DATA : (CAN Offset: 0x08) (R/W 32) Rx FIFO 1 Element Data -------- */ -#define CAN_RXF1E_DATA_DB0_Pos _U_(0) /**< (CAN_RXF1E_DATA) Data Byte 0 Position */ -#define CAN_RXF1E_DATA_DB0_Msk (_U_(0xFF) << CAN_RXF1E_DATA_DB0_Pos) /**< (CAN_RXF1E_DATA) Data Byte 0 Mask */ -#define CAN_RXF1E_DATA_DB0(value) (CAN_RXF1E_DATA_DB0_Msk & ((value) << CAN_RXF1E_DATA_DB0_Pos)) -#define CAN_RXF1E_DATA_DB1_Pos _U_(8) /**< (CAN_RXF1E_DATA) Data Byte 1 Position */ -#define CAN_RXF1E_DATA_DB1_Msk (_U_(0xFF) << CAN_RXF1E_DATA_DB1_Pos) /**< (CAN_RXF1E_DATA) Data Byte 1 Mask */ -#define CAN_RXF1E_DATA_DB1(value) (CAN_RXF1E_DATA_DB1_Msk & ((value) << CAN_RXF1E_DATA_DB1_Pos)) -#define CAN_RXF1E_DATA_DB2_Pos _U_(16) /**< (CAN_RXF1E_DATA) Data Byte 2 Position */ -#define CAN_RXF1E_DATA_DB2_Msk (_U_(0xFF) << CAN_RXF1E_DATA_DB2_Pos) /**< (CAN_RXF1E_DATA) Data Byte 2 Mask */ -#define CAN_RXF1E_DATA_DB2(value) (CAN_RXF1E_DATA_DB2_Msk & ((value) << CAN_RXF1E_DATA_DB2_Pos)) -#define CAN_RXF1E_DATA_DB3_Pos _U_(24) /**< (CAN_RXF1E_DATA) Data Byte 3 Position */ -#define CAN_RXF1E_DATA_DB3_Msk (_U_(0xFF) << CAN_RXF1E_DATA_DB3_Pos) /**< (CAN_RXF1E_DATA) Data Byte 3 Mask */ -#define CAN_RXF1E_DATA_DB3(value) (CAN_RXF1E_DATA_DB3_Msk & ((value) << CAN_RXF1E_DATA_DB3_Pos)) -#define CAN_RXF1E_DATA_Msk _U_(0xFFFFFFFF) /**< (CAN_RXF1E_DATA) Register Mask */ - - -/* -------- CAN_TXBE_0 : (CAN Offset: 0x00) (R/W 32) Tx Buffer Element 0 -------- */ -#define CAN_TXBE_0_ID_Pos _U_(0) /**< (CAN_TXBE_0) Identifier Position */ -#define CAN_TXBE_0_ID_Msk (_U_(0x1FFFFFFF) << CAN_TXBE_0_ID_Pos) /**< (CAN_TXBE_0) Identifier Mask */ -#define CAN_TXBE_0_ID(value) (CAN_TXBE_0_ID_Msk & ((value) << CAN_TXBE_0_ID_Pos)) -#define CAN_TXBE_0_RTR_Pos _U_(29) /**< (CAN_TXBE_0) Remote Transmission Request Position */ -#define CAN_TXBE_0_RTR_Msk (_U_(0x1) << CAN_TXBE_0_RTR_Pos) /**< (CAN_TXBE_0) Remote Transmission Request Mask */ -#define CAN_TXBE_0_RTR(value) (CAN_TXBE_0_RTR_Msk & ((value) << CAN_TXBE_0_RTR_Pos)) -#define CAN_TXBE_0_XTD_Pos _U_(30) /**< (CAN_TXBE_0) Extended Identifier Position */ -#define CAN_TXBE_0_XTD_Msk (_U_(0x1) << CAN_TXBE_0_XTD_Pos) /**< (CAN_TXBE_0) Extended Identifier Mask */ -#define CAN_TXBE_0_XTD(value) (CAN_TXBE_0_XTD_Msk & ((value) << CAN_TXBE_0_XTD_Pos)) -#define CAN_TXBE_0_ESI_Pos _U_(31) /**< (CAN_TXBE_0) Error State Indicator Position */ -#define CAN_TXBE_0_ESI_Msk (_U_(0x1) << CAN_TXBE_0_ESI_Pos) /**< (CAN_TXBE_0) Error State Indicator Mask */ -#define CAN_TXBE_0_ESI(value) (CAN_TXBE_0_ESI_Msk & ((value) << CAN_TXBE_0_ESI_Pos)) -#define CAN_TXBE_0_Msk _U_(0xFFFFFFFF) /**< (CAN_TXBE_0) Register Mask */ - - -/* -------- CAN_TXBE_1 : (CAN Offset: 0x04) (R/W 32) Tx Buffer Element 1 -------- */ -#define CAN_TXBE_1_DLC_Pos _U_(16) /**< (CAN_TXBE_1) Data Length Code Position */ -#define CAN_TXBE_1_DLC_Msk (_U_(0xF) << CAN_TXBE_1_DLC_Pos) /**< (CAN_TXBE_1) Data Length Code Mask */ -#define CAN_TXBE_1_DLC(value) (CAN_TXBE_1_DLC_Msk & ((value) << CAN_TXBE_1_DLC_Pos)) -#define CAN_TXBE_1_BRS_Pos _U_(20) /**< (CAN_TXBE_1) Bit Rate Switch Position */ -#define CAN_TXBE_1_BRS_Msk (_U_(0x1) << CAN_TXBE_1_BRS_Pos) /**< (CAN_TXBE_1) Bit Rate Switch Mask */ -#define CAN_TXBE_1_BRS(value) (CAN_TXBE_1_BRS_Msk & ((value) << CAN_TXBE_1_BRS_Pos)) -#define CAN_TXBE_1_FDF_Pos _U_(21) /**< (CAN_TXBE_1) FD Format Position */ -#define CAN_TXBE_1_FDF_Msk (_U_(0x1) << CAN_TXBE_1_FDF_Pos) /**< (CAN_TXBE_1) FD Format Mask */ -#define CAN_TXBE_1_FDF(value) (CAN_TXBE_1_FDF_Msk & ((value) << CAN_TXBE_1_FDF_Pos)) -#define CAN_TXBE_1_EFC_Pos _U_(23) /**< (CAN_TXBE_1) Event FIFO Control Position */ -#define CAN_TXBE_1_EFC_Msk (_U_(0x1) << CAN_TXBE_1_EFC_Pos) /**< (CAN_TXBE_1) Event FIFO Control Mask */ -#define CAN_TXBE_1_EFC(value) (CAN_TXBE_1_EFC_Msk & ((value) << CAN_TXBE_1_EFC_Pos)) -#define CAN_TXBE_1_MM_Pos _U_(24) /**< (CAN_TXBE_1) Message Marker Position */ -#define CAN_TXBE_1_MM_Msk (_U_(0xFF) << CAN_TXBE_1_MM_Pos) /**< (CAN_TXBE_1) Message Marker Mask */ -#define CAN_TXBE_1_MM(value) (CAN_TXBE_1_MM_Msk & ((value) << CAN_TXBE_1_MM_Pos)) -#define CAN_TXBE_1_Msk _U_(0xFFBF0000) /**< (CAN_TXBE_1) Register Mask */ - - -/* -------- CAN_TXBE_DATA : (CAN Offset: 0x08) (R/W 32) Tx Buffer Element Data -------- */ -#define CAN_TXBE_DATA_DB0_Pos _U_(0) /**< (CAN_TXBE_DATA) Data Byte 0 Position */ -#define CAN_TXBE_DATA_DB0_Msk (_U_(0xFF) << CAN_TXBE_DATA_DB0_Pos) /**< (CAN_TXBE_DATA) Data Byte 0 Mask */ -#define CAN_TXBE_DATA_DB0(value) (CAN_TXBE_DATA_DB0_Msk & ((value) << CAN_TXBE_DATA_DB0_Pos)) -#define CAN_TXBE_DATA_DB1_Pos _U_(8) /**< (CAN_TXBE_DATA) Data Byte 1 Position */ -#define CAN_TXBE_DATA_DB1_Msk (_U_(0xFF) << CAN_TXBE_DATA_DB1_Pos) /**< (CAN_TXBE_DATA) Data Byte 1 Mask */ -#define CAN_TXBE_DATA_DB1(value) (CAN_TXBE_DATA_DB1_Msk & ((value) << CAN_TXBE_DATA_DB1_Pos)) -#define CAN_TXBE_DATA_DB2_Pos _U_(16) /**< (CAN_TXBE_DATA) Data Byte 2 Position */ -#define CAN_TXBE_DATA_DB2_Msk (_U_(0xFF) << CAN_TXBE_DATA_DB2_Pos) /**< (CAN_TXBE_DATA) Data Byte 2 Mask */ -#define CAN_TXBE_DATA_DB2(value) (CAN_TXBE_DATA_DB2_Msk & ((value) << CAN_TXBE_DATA_DB2_Pos)) -#define CAN_TXBE_DATA_DB3_Pos _U_(24) /**< (CAN_TXBE_DATA) Data Byte 3 Position */ -#define CAN_TXBE_DATA_DB3_Msk (_U_(0xFF) << CAN_TXBE_DATA_DB3_Pos) /**< (CAN_TXBE_DATA) Data Byte 3 Mask */ -#define CAN_TXBE_DATA_DB3(value) (CAN_TXBE_DATA_DB3_Msk & ((value) << CAN_TXBE_DATA_DB3_Pos)) -#define CAN_TXBE_DATA_Msk _U_(0xFFFFFFFF) /**< (CAN_TXBE_DATA) Register Mask */ - - -/* -------- CAN_TXEFE_0 : (CAN Offset: 0x00) (R/W 32) Tx Event FIFO Element 0 -------- */ -#define CAN_TXEFE_0_ID_Pos _U_(0) /**< (CAN_TXEFE_0) Identifier Position */ -#define CAN_TXEFE_0_ID_Msk (_U_(0x1FFFFFFF) << CAN_TXEFE_0_ID_Pos) /**< (CAN_TXEFE_0) Identifier Mask */ -#define CAN_TXEFE_0_ID(value) (CAN_TXEFE_0_ID_Msk & ((value) << CAN_TXEFE_0_ID_Pos)) -#define CAN_TXEFE_0_RTR_Pos _U_(29) /**< (CAN_TXEFE_0) Remote Transmission Request Position */ -#define CAN_TXEFE_0_RTR_Msk (_U_(0x1) << CAN_TXEFE_0_RTR_Pos) /**< (CAN_TXEFE_0) Remote Transmission Request Mask */ -#define CAN_TXEFE_0_RTR(value) (CAN_TXEFE_0_RTR_Msk & ((value) << CAN_TXEFE_0_RTR_Pos)) -#define CAN_TXEFE_0_XTD_Pos _U_(30) /**< (CAN_TXEFE_0) Extended Identifier Position */ -#define CAN_TXEFE_0_XTD_Msk (_U_(0x1) << CAN_TXEFE_0_XTD_Pos) /**< (CAN_TXEFE_0) Extended Identifier Mask */ -#define CAN_TXEFE_0_XTD(value) (CAN_TXEFE_0_XTD_Msk & ((value) << CAN_TXEFE_0_XTD_Pos)) -#define CAN_TXEFE_0_ESI_Pos _U_(31) /**< (CAN_TXEFE_0) Error State Indicator Position */ -#define CAN_TXEFE_0_ESI_Msk (_U_(0x1) << CAN_TXEFE_0_ESI_Pos) /**< (CAN_TXEFE_0) Error State Indicator Mask */ -#define CAN_TXEFE_0_ESI(value) (CAN_TXEFE_0_ESI_Msk & ((value) << CAN_TXEFE_0_ESI_Pos)) -#define CAN_TXEFE_0_Msk _U_(0xFFFFFFFF) /**< (CAN_TXEFE_0) Register Mask */ - - -/* -------- CAN_TXEFE_1 : (CAN Offset: 0x04) (R/W 32) Tx Event FIFO Element 1 -------- */ -#define CAN_TXEFE_1_TXTS_Pos _U_(0) /**< (CAN_TXEFE_1) Tx Timestamp Position */ -#define CAN_TXEFE_1_TXTS_Msk (_U_(0xFFFF) << CAN_TXEFE_1_TXTS_Pos) /**< (CAN_TXEFE_1) Tx Timestamp Mask */ -#define CAN_TXEFE_1_TXTS(value) (CAN_TXEFE_1_TXTS_Msk & ((value) << CAN_TXEFE_1_TXTS_Pos)) -#define CAN_TXEFE_1_DLC_Pos _U_(16) /**< (CAN_TXEFE_1) Data Length Code Position */ -#define CAN_TXEFE_1_DLC_Msk (_U_(0xF) << CAN_TXEFE_1_DLC_Pos) /**< (CAN_TXEFE_1) Data Length Code Mask */ -#define CAN_TXEFE_1_DLC(value) (CAN_TXEFE_1_DLC_Msk & ((value) << CAN_TXEFE_1_DLC_Pos)) -#define CAN_TXEFE_1_BRS_Pos _U_(20) /**< (CAN_TXEFE_1) Bit Rate Switch Position */ -#define CAN_TXEFE_1_BRS_Msk (_U_(0x1) << CAN_TXEFE_1_BRS_Pos) /**< (CAN_TXEFE_1) Bit Rate Switch Mask */ -#define CAN_TXEFE_1_BRS(value) (CAN_TXEFE_1_BRS_Msk & ((value) << CAN_TXEFE_1_BRS_Pos)) -#define CAN_TXEFE_1_FDF_Pos _U_(21) /**< (CAN_TXEFE_1) FD Format Position */ -#define CAN_TXEFE_1_FDF_Msk (_U_(0x1) << CAN_TXEFE_1_FDF_Pos) /**< (CAN_TXEFE_1) FD Format Mask */ -#define CAN_TXEFE_1_FDF(value) (CAN_TXEFE_1_FDF_Msk & ((value) << CAN_TXEFE_1_FDF_Pos)) -#define CAN_TXEFE_1_ET_Pos _U_(22) /**< (CAN_TXEFE_1) Event Type Position */ -#define CAN_TXEFE_1_ET_Msk (_U_(0x3) << CAN_TXEFE_1_ET_Pos) /**< (CAN_TXEFE_1) Event Type Mask */ -#define CAN_TXEFE_1_ET(value) (CAN_TXEFE_1_ET_Msk & ((value) << CAN_TXEFE_1_ET_Pos)) -#define CAN_TXEFE_1_ET_TXE_Val _U_(0x1) /**< (CAN_TXEFE_1) Tx event */ -#define CAN_TXEFE_1_ET_TXC_Val _U_(0x2) /**< (CAN_TXEFE_1) Transmission in spite of cancellation */ -#define CAN_TXEFE_1_ET_TXE (CAN_TXEFE_1_ET_TXE_Val << CAN_TXEFE_1_ET_Pos) /**< (CAN_TXEFE_1) Tx event Position */ -#define CAN_TXEFE_1_ET_TXC (CAN_TXEFE_1_ET_TXC_Val << CAN_TXEFE_1_ET_Pos) /**< (CAN_TXEFE_1) Transmission in spite of cancellation Position */ -#define CAN_TXEFE_1_MM_Pos _U_(24) /**< (CAN_TXEFE_1) Message Marker Position */ -#define CAN_TXEFE_1_MM_Msk (_U_(0xFF) << CAN_TXEFE_1_MM_Pos) /**< (CAN_TXEFE_1) Message Marker Mask */ -#define CAN_TXEFE_1_MM(value) (CAN_TXEFE_1_MM_Msk & ((value) << CAN_TXEFE_1_MM_Pos)) -#define CAN_TXEFE_1_Msk _U_(0xFFFFFFFF) /**< (CAN_TXEFE_1) Register Mask */ - - -/* -------- CAN_SIDFE_0 : (CAN Offset: 0x00) (R/W 32) Standard Message ID Filter Element 0 -------- */ -#define CAN_SIDFE_0_SFID2_Pos _U_(0) /**< (CAN_SIDFE_0) Standard Filter ID 2 Position */ -#define CAN_SIDFE_0_SFID2_Msk (_U_(0x7FF) << CAN_SIDFE_0_SFID2_Pos) /**< (CAN_SIDFE_0) Standard Filter ID 2 Mask */ -#define CAN_SIDFE_0_SFID2(value) (CAN_SIDFE_0_SFID2_Msk & ((value) << CAN_SIDFE_0_SFID2_Pos)) -#define CAN_SIDFE_0_SFID1_Pos _U_(16) /**< (CAN_SIDFE_0) Standard Filter ID 1 Position */ -#define CAN_SIDFE_0_SFID1_Msk (_U_(0x7FF) << CAN_SIDFE_0_SFID1_Pos) /**< (CAN_SIDFE_0) Standard Filter ID 1 Mask */ -#define CAN_SIDFE_0_SFID1(value) (CAN_SIDFE_0_SFID1_Msk & ((value) << CAN_SIDFE_0_SFID1_Pos)) -#define CAN_SIDFE_0_SFEC_Pos _U_(27) /**< (CAN_SIDFE_0) Standard Filter Element Configuration Position */ -#define CAN_SIDFE_0_SFEC_Msk (_U_(0x7) << CAN_SIDFE_0_SFEC_Pos) /**< (CAN_SIDFE_0) Standard Filter Element Configuration Mask */ -#define CAN_SIDFE_0_SFEC(value) (CAN_SIDFE_0_SFEC_Msk & ((value) << CAN_SIDFE_0_SFEC_Pos)) -#define CAN_SIDFE_0_SFEC_DISABLE_Val _U_(0x0) /**< (CAN_SIDFE_0) Disable filter element */ -#define CAN_SIDFE_0_SFEC_STF0M_Val _U_(0x1) /**< (CAN_SIDFE_0) Store in Rx FIFO 0 if filter match */ -#define CAN_SIDFE_0_SFEC_STF1M_Val _U_(0x2) /**< (CAN_SIDFE_0) Store in Rx FIFO 1 if filter match */ -#define CAN_SIDFE_0_SFEC_REJECT_Val _U_(0x3) /**< (CAN_SIDFE_0) Reject ID if filter match */ -#define CAN_SIDFE_0_SFEC_PRIORITY_Val _U_(0x4) /**< (CAN_SIDFE_0) Set priority if filter match */ -#define CAN_SIDFE_0_SFEC_PRIF0M_Val _U_(0x5) /**< (CAN_SIDFE_0) Set priority and store in FIFO 0 if filter match */ -#define CAN_SIDFE_0_SFEC_PRIF1M_Val _U_(0x6) /**< (CAN_SIDFE_0) Set priority and store in FIFO 1 if filter match */ -#define CAN_SIDFE_0_SFEC_STRXBUF_Val _U_(0x7) /**< (CAN_SIDFE_0) Store into Rx Buffer */ -#define CAN_SIDFE_0_SFEC_DISABLE (CAN_SIDFE_0_SFEC_DISABLE_Val << CAN_SIDFE_0_SFEC_Pos) /**< (CAN_SIDFE_0) Disable filter element Position */ -#define CAN_SIDFE_0_SFEC_STF0M (CAN_SIDFE_0_SFEC_STF0M_Val << CAN_SIDFE_0_SFEC_Pos) /**< (CAN_SIDFE_0) Store in Rx FIFO 0 if filter match Position */ -#define CAN_SIDFE_0_SFEC_STF1M (CAN_SIDFE_0_SFEC_STF1M_Val << CAN_SIDFE_0_SFEC_Pos) /**< (CAN_SIDFE_0) Store in Rx FIFO 1 if filter match Position */ -#define CAN_SIDFE_0_SFEC_REJECT (CAN_SIDFE_0_SFEC_REJECT_Val << CAN_SIDFE_0_SFEC_Pos) /**< (CAN_SIDFE_0) Reject ID if filter match Position */ -#define CAN_SIDFE_0_SFEC_PRIORITY (CAN_SIDFE_0_SFEC_PRIORITY_Val << CAN_SIDFE_0_SFEC_Pos) /**< (CAN_SIDFE_0) Set priority if filter match Position */ -#define CAN_SIDFE_0_SFEC_PRIF0M (CAN_SIDFE_0_SFEC_PRIF0M_Val << CAN_SIDFE_0_SFEC_Pos) /**< (CAN_SIDFE_0) Set priority and store in FIFO 0 if filter match Position */ -#define CAN_SIDFE_0_SFEC_PRIF1M (CAN_SIDFE_0_SFEC_PRIF1M_Val << CAN_SIDFE_0_SFEC_Pos) /**< (CAN_SIDFE_0) Set priority and store in FIFO 1 if filter match Position */ -#define CAN_SIDFE_0_SFEC_STRXBUF (CAN_SIDFE_0_SFEC_STRXBUF_Val << CAN_SIDFE_0_SFEC_Pos) /**< (CAN_SIDFE_0) Store into Rx Buffer Position */ -#define CAN_SIDFE_0_SFT_Pos _U_(30) /**< (CAN_SIDFE_0) Standard Filter Type Position */ -#define CAN_SIDFE_0_SFT_Msk (_U_(0x3) << CAN_SIDFE_0_SFT_Pos) /**< (CAN_SIDFE_0) Standard Filter Type Mask */ -#define CAN_SIDFE_0_SFT(value) (CAN_SIDFE_0_SFT_Msk & ((value) << CAN_SIDFE_0_SFT_Pos)) -#define CAN_SIDFE_0_SFT_RANGE_Val _U_(0x0) /**< (CAN_SIDFE_0) Range filter from SFID1 to SFID2 */ -#define CAN_SIDFE_0_SFT_DUAL_Val _U_(0x1) /**< (CAN_SIDFE_0) Dual ID filter for SFID1 or SFID2 */ -#define CAN_SIDFE_0_SFT_CLASSIC_Val _U_(0x2) /**< (CAN_SIDFE_0) Classic filter */ -#define CAN_SIDFE_0_SFT_RANGE (CAN_SIDFE_0_SFT_RANGE_Val << CAN_SIDFE_0_SFT_Pos) /**< (CAN_SIDFE_0) Range filter from SFID1 to SFID2 Position */ -#define CAN_SIDFE_0_SFT_DUAL (CAN_SIDFE_0_SFT_DUAL_Val << CAN_SIDFE_0_SFT_Pos) /**< (CAN_SIDFE_0) Dual ID filter for SFID1 or SFID2 Position */ -#define CAN_SIDFE_0_SFT_CLASSIC (CAN_SIDFE_0_SFT_CLASSIC_Val << CAN_SIDFE_0_SFT_Pos) /**< (CAN_SIDFE_0) Classic filter Position */ -#define CAN_SIDFE_0_Msk _U_(0xFFFF07FF) /**< (CAN_SIDFE_0) Register Mask */ - - -/* -------- CAN_XIDFE_0 : (CAN Offset: 0x00) (R/W 32) Extended Message ID Filter Element 0 -------- */ -#define CAN_XIDFE_0_EFID1_Pos _U_(0) /**< (CAN_XIDFE_0) Extended Filter ID 1 Position */ -#define CAN_XIDFE_0_EFID1_Msk (_U_(0x1FFFFFFF) << CAN_XIDFE_0_EFID1_Pos) /**< (CAN_XIDFE_0) Extended Filter ID 1 Mask */ -#define CAN_XIDFE_0_EFID1(value) (CAN_XIDFE_0_EFID1_Msk & ((value) << CAN_XIDFE_0_EFID1_Pos)) -#define CAN_XIDFE_0_EFEC_Pos _U_(29) /**< (CAN_XIDFE_0) Extended Filter Element Configuration Position */ -#define CAN_XIDFE_0_EFEC_Msk (_U_(0x7) << CAN_XIDFE_0_EFEC_Pos) /**< (CAN_XIDFE_0) Extended Filter Element Configuration Mask */ -#define CAN_XIDFE_0_EFEC(value) (CAN_XIDFE_0_EFEC_Msk & ((value) << CAN_XIDFE_0_EFEC_Pos)) -#define CAN_XIDFE_0_EFEC_DISABLE_Val _U_(0x0) /**< (CAN_XIDFE_0) Disable filter element */ -#define CAN_XIDFE_0_EFEC_STF0M_Val _U_(0x1) /**< (CAN_XIDFE_0) Store in Rx FIFO 0 if filter match */ -#define CAN_XIDFE_0_EFEC_STF1M_Val _U_(0x2) /**< (CAN_XIDFE_0) Store in Rx FIFO 1 if filter match */ -#define CAN_XIDFE_0_EFEC_REJECT_Val _U_(0x3) /**< (CAN_XIDFE_0) Reject ID if filter match */ -#define CAN_XIDFE_0_EFEC_PRIORITY_Val _U_(0x4) /**< (CAN_XIDFE_0) Set priority if filter match */ -#define CAN_XIDFE_0_EFEC_PRIF0M_Val _U_(0x5) /**< (CAN_XIDFE_0) Set priority and store in FIFO 0 if filter match */ -#define CAN_XIDFE_0_EFEC_PRIF1M_Val _U_(0x6) /**< (CAN_XIDFE_0) Set priority and store in FIFO 1 if filter match */ -#define CAN_XIDFE_0_EFEC_STRXBUF_Val _U_(0x7) /**< (CAN_XIDFE_0) Store into Rx Buffer */ -#define CAN_XIDFE_0_EFEC_DISABLE (CAN_XIDFE_0_EFEC_DISABLE_Val << CAN_XIDFE_0_EFEC_Pos) /**< (CAN_XIDFE_0) Disable filter element Position */ -#define CAN_XIDFE_0_EFEC_STF0M (CAN_XIDFE_0_EFEC_STF0M_Val << CAN_XIDFE_0_EFEC_Pos) /**< (CAN_XIDFE_0) Store in Rx FIFO 0 if filter match Position */ -#define CAN_XIDFE_0_EFEC_STF1M (CAN_XIDFE_0_EFEC_STF1M_Val << CAN_XIDFE_0_EFEC_Pos) /**< (CAN_XIDFE_0) Store in Rx FIFO 1 if filter match Position */ -#define CAN_XIDFE_0_EFEC_REJECT (CAN_XIDFE_0_EFEC_REJECT_Val << CAN_XIDFE_0_EFEC_Pos) /**< (CAN_XIDFE_0) Reject ID if filter match Position */ -#define CAN_XIDFE_0_EFEC_PRIORITY (CAN_XIDFE_0_EFEC_PRIORITY_Val << CAN_XIDFE_0_EFEC_Pos) /**< (CAN_XIDFE_0) Set priority if filter match Position */ -#define CAN_XIDFE_0_EFEC_PRIF0M (CAN_XIDFE_0_EFEC_PRIF0M_Val << CAN_XIDFE_0_EFEC_Pos) /**< (CAN_XIDFE_0) Set priority and store in FIFO 0 if filter match Position */ -#define CAN_XIDFE_0_EFEC_PRIF1M (CAN_XIDFE_0_EFEC_PRIF1M_Val << CAN_XIDFE_0_EFEC_Pos) /**< (CAN_XIDFE_0) Set priority and store in FIFO 1 if filter match Position */ -#define CAN_XIDFE_0_EFEC_STRXBUF (CAN_XIDFE_0_EFEC_STRXBUF_Val << CAN_XIDFE_0_EFEC_Pos) /**< (CAN_XIDFE_0) Store into Rx Buffer Position */ -#define CAN_XIDFE_0_Msk _U_(0xFFFFFFFF) /**< (CAN_XIDFE_0) Register Mask */ - - -/* -------- CAN_XIDFE_1 : (CAN Offset: 0x04) (R/W 32) Extended Message ID Filter Element 1 -------- */ -#define CAN_XIDFE_1_EFID2_Pos _U_(0) /**< (CAN_XIDFE_1) Extended Filter ID 2 Position */ -#define CAN_XIDFE_1_EFID2_Msk (_U_(0x1FFFFFFF) << CAN_XIDFE_1_EFID2_Pos) /**< (CAN_XIDFE_1) Extended Filter ID 2 Mask */ -#define CAN_XIDFE_1_EFID2(value) (CAN_XIDFE_1_EFID2_Msk & ((value) << CAN_XIDFE_1_EFID2_Pos)) -#define CAN_XIDFE_1_EFT_Pos _U_(30) /**< (CAN_XIDFE_1) Extended Filter Type Position */ -#define CAN_XIDFE_1_EFT_Msk (_U_(0x3) << CAN_XIDFE_1_EFT_Pos) /**< (CAN_XIDFE_1) Extended Filter Type Mask */ -#define CAN_XIDFE_1_EFT(value) (CAN_XIDFE_1_EFT_Msk & ((value) << CAN_XIDFE_1_EFT_Pos)) -#define CAN_XIDFE_1_EFT_RANGEM_Val _U_(0x0) /**< (CAN_XIDFE_1) Range filter from EFID1 to EFID2 */ -#define CAN_XIDFE_1_EFT_DUAL_Val _U_(0x1) /**< (CAN_XIDFE_1) Dual ID filter for EFID1 or EFID2 */ -#define CAN_XIDFE_1_EFT_CLASSIC_Val _U_(0x2) /**< (CAN_XIDFE_1) Classic filter */ -#define CAN_XIDFE_1_EFT_RANGE_Val _U_(0x3) /**< (CAN_XIDFE_1) Range filter from EFID1 to EFID2 with no XIDAM mask */ -#define CAN_XIDFE_1_EFT_RANGEM (CAN_XIDFE_1_EFT_RANGEM_Val << CAN_XIDFE_1_EFT_Pos) /**< (CAN_XIDFE_1) Range filter from EFID1 to EFID2 Position */ -#define CAN_XIDFE_1_EFT_DUAL (CAN_XIDFE_1_EFT_DUAL_Val << CAN_XIDFE_1_EFT_Pos) /**< (CAN_XIDFE_1) Dual ID filter for EFID1 or EFID2 Position */ -#define CAN_XIDFE_1_EFT_CLASSIC (CAN_XIDFE_1_EFT_CLASSIC_Val << CAN_XIDFE_1_EFT_Pos) /**< (CAN_XIDFE_1) Classic filter Position */ -#define CAN_XIDFE_1_EFT_RANGE (CAN_XIDFE_1_EFT_RANGE_Val << CAN_XIDFE_1_EFT_Pos) /**< (CAN_XIDFE_1) Range filter from EFID1 to EFID2 with no XIDAM mask Position */ -#define CAN_XIDFE_1_Msk _U_(0xDFFFFFFF) /**< (CAN_XIDFE_1) Register Mask */ - - -/* -------- CAN_CREL : (CAN Offset: 0x00) ( R/ 32) Core Release -------- */ -#define CAN_CREL_RESETVALUE _U_(0x32100000) /**< (CAN_CREL) Core Release Reset Value */ - -#define CAN_CREL_SUBSTEP_Pos _U_(20) /**< (CAN_CREL) Sub-step of Core Release Position */ -#define CAN_CREL_SUBSTEP_Msk (_U_(0xF) << CAN_CREL_SUBSTEP_Pos) /**< (CAN_CREL) Sub-step of Core Release Mask */ -#define CAN_CREL_SUBSTEP(value) (CAN_CREL_SUBSTEP_Msk & ((value) << CAN_CREL_SUBSTEP_Pos)) -#define CAN_CREL_STEP_Pos _U_(24) /**< (CAN_CREL) Step of Core Release Position */ -#define CAN_CREL_STEP_Msk (_U_(0xF) << CAN_CREL_STEP_Pos) /**< (CAN_CREL) Step of Core Release Mask */ -#define CAN_CREL_STEP(value) (CAN_CREL_STEP_Msk & ((value) << CAN_CREL_STEP_Pos)) -#define CAN_CREL_REL_Pos _U_(28) /**< (CAN_CREL) Core Release Position */ -#define CAN_CREL_REL_Msk (_U_(0xF) << CAN_CREL_REL_Pos) /**< (CAN_CREL) Core Release Mask */ -#define CAN_CREL_REL(value) (CAN_CREL_REL_Msk & ((value) << CAN_CREL_REL_Pos)) -#define CAN_CREL_Msk _U_(0xFFF00000) /**< (CAN_CREL) Register Mask */ - - -/* -------- CAN_ENDN : (CAN Offset: 0x04) ( R/ 32) Endian -------- */ -#define CAN_ENDN_RESETVALUE _U_(0x87654321) /**< (CAN_ENDN) Endian Reset Value */ - -#define CAN_ENDN_ETV_Pos _U_(0) /**< (CAN_ENDN) Endianness Test Value Position */ -#define CAN_ENDN_ETV_Msk (_U_(0xFFFFFFFF) << CAN_ENDN_ETV_Pos) /**< (CAN_ENDN) Endianness Test Value Mask */ -#define CAN_ENDN_ETV(value) (CAN_ENDN_ETV_Msk & ((value) << CAN_ENDN_ETV_Pos)) -#define CAN_ENDN_Msk _U_(0xFFFFFFFF) /**< (CAN_ENDN) Register Mask */ - - -/* -------- CAN_MRCFG : (CAN Offset: 0x08) (R/W 32) Message RAM Configuration -------- */ -#define CAN_MRCFG_RESETVALUE _U_(0x02) /**< (CAN_MRCFG) Message RAM Configuration Reset Value */ - -#define CAN_MRCFG_QOS_Pos _U_(0) /**< (CAN_MRCFG) Quality of Service Position */ -#define CAN_MRCFG_QOS_Msk (_U_(0x3) << CAN_MRCFG_QOS_Pos) /**< (CAN_MRCFG) Quality of Service Mask */ -#define CAN_MRCFG_QOS(value) (CAN_MRCFG_QOS_Msk & ((value) << CAN_MRCFG_QOS_Pos)) -#define CAN_MRCFG_QOS_DISABLE_Val _U_(0x0) /**< (CAN_MRCFG) Background (no sensitive operation) */ -#define CAN_MRCFG_QOS_LOW_Val _U_(0x1) /**< (CAN_MRCFG) Sensitive Bandwidth */ -#define CAN_MRCFG_QOS_MEDIUM_Val _U_(0x2) /**< (CAN_MRCFG) Sensitive Latency */ -#define CAN_MRCFG_QOS_HIGH_Val _U_(0x3) /**< (CAN_MRCFG) Critical Latency */ -#define CAN_MRCFG_QOS_DISABLE (CAN_MRCFG_QOS_DISABLE_Val << CAN_MRCFG_QOS_Pos) /**< (CAN_MRCFG) Background (no sensitive operation) Position */ -#define CAN_MRCFG_QOS_LOW (CAN_MRCFG_QOS_LOW_Val << CAN_MRCFG_QOS_Pos) /**< (CAN_MRCFG) Sensitive Bandwidth Position */ -#define CAN_MRCFG_QOS_MEDIUM (CAN_MRCFG_QOS_MEDIUM_Val << CAN_MRCFG_QOS_Pos) /**< (CAN_MRCFG) Sensitive Latency Position */ -#define CAN_MRCFG_QOS_HIGH (CAN_MRCFG_QOS_HIGH_Val << CAN_MRCFG_QOS_Pos) /**< (CAN_MRCFG) Critical Latency Position */ -#define CAN_MRCFG_Msk _U_(0x00000003) /**< (CAN_MRCFG) Register Mask */ - - -/* -------- CAN_DBTP : (CAN Offset: 0x0C) (R/W 32) Fast Bit Timing and Prescaler -------- */ -#define CAN_DBTP_RESETVALUE _U_(0xA33) /**< (CAN_DBTP) Fast Bit Timing and Prescaler Reset Value */ - -#define CAN_DBTP_DSJW_Pos _U_(0) /**< (CAN_DBTP) Data (Re)Synchronization Jump Width Position */ -#define CAN_DBTP_DSJW_Msk (_U_(0xF) << CAN_DBTP_DSJW_Pos) /**< (CAN_DBTP) Data (Re)Synchronization Jump Width Mask */ -#define CAN_DBTP_DSJW(value) (CAN_DBTP_DSJW_Msk & ((value) << CAN_DBTP_DSJW_Pos)) -#define CAN_DBTP_DTSEG2_Pos _U_(4) /**< (CAN_DBTP) Data time segment after sample point Position */ -#define CAN_DBTP_DTSEG2_Msk (_U_(0xF) << CAN_DBTP_DTSEG2_Pos) /**< (CAN_DBTP) Data time segment after sample point Mask */ -#define CAN_DBTP_DTSEG2(value) (CAN_DBTP_DTSEG2_Msk & ((value) << CAN_DBTP_DTSEG2_Pos)) -#define CAN_DBTP_DTSEG1_Pos _U_(8) /**< (CAN_DBTP) Data time segment before sample point Position */ -#define CAN_DBTP_DTSEG1_Msk (_U_(0x1F) << CAN_DBTP_DTSEG1_Pos) /**< (CAN_DBTP) Data time segment before sample point Mask */ -#define CAN_DBTP_DTSEG1(value) (CAN_DBTP_DTSEG1_Msk & ((value) << CAN_DBTP_DTSEG1_Pos)) -#define CAN_DBTP_DBRP_Pos _U_(16) /**< (CAN_DBTP) Data Baud Rate Prescaler Position */ -#define CAN_DBTP_DBRP_Msk (_U_(0x1F) << CAN_DBTP_DBRP_Pos) /**< (CAN_DBTP) Data Baud Rate Prescaler Mask */ -#define CAN_DBTP_DBRP(value) (CAN_DBTP_DBRP_Msk & ((value) << CAN_DBTP_DBRP_Pos)) -#define CAN_DBTP_TDC_Pos _U_(23) /**< (CAN_DBTP) Tranceiver Delay Compensation Position */ -#define CAN_DBTP_TDC_Msk (_U_(0x1) << CAN_DBTP_TDC_Pos) /**< (CAN_DBTP) Tranceiver Delay Compensation Mask */ -#define CAN_DBTP_TDC(value) (CAN_DBTP_TDC_Msk & ((value) << CAN_DBTP_TDC_Pos)) -#define CAN_DBTP_Msk _U_(0x009F1FFF) /**< (CAN_DBTP) Register Mask */ - - -/* -------- CAN_TEST : (CAN Offset: 0x10) (R/W 32) Test -------- */ -#define CAN_TEST_RESETVALUE _U_(0x00) /**< (CAN_TEST) Test Reset Value */ - -#define CAN_TEST_LBCK_Pos _U_(4) /**< (CAN_TEST) Loop Back Mode Position */ -#define CAN_TEST_LBCK_Msk (_U_(0x1) << CAN_TEST_LBCK_Pos) /**< (CAN_TEST) Loop Back Mode Mask */ -#define CAN_TEST_LBCK(value) (CAN_TEST_LBCK_Msk & ((value) << CAN_TEST_LBCK_Pos)) -#define CAN_TEST_TX_Pos _U_(5) /**< (CAN_TEST) Control of Transmit Pin Position */ -#define CAN_TEST_TX_Msk (_U_(0x3) << CAN_TEST_TX_Pos) /**< (CAN_TEST) Control of Transmit Pin Mask */ -#define CAN_TEST_TX(value) (CAN_TEST_TX_Msk & ((value) << CAN_TEST_TX_Pos)) -#define CAN_TEST_TX_CORE_Val _U_(0x0) /**< (CAN_TEST) TX controlled by CAN core */ -#define CAN_TEST_TX_SAMPLE_Val _U_(0x1) /**< (CAN_TEST) TX monitoring sample point */ -#define CAN_TEST_TX_DOMINANT_Val _U_(0x2) /**< (CAN_TEST) Dominant (0) level at pin CAN_TX */ -#define CAN_TEST_TX_RECESSIVE_Val _U_(0x3) /**< (CAN_TEST) Recessive (1) level at pin CAN_TX */ -#define CAN_TEST_TX_CORE (CAN_TEST_TX_CORE_Val << CAN_TEST_TX_Pos) /**< (CAN_TEST) TX controlled by CAN core Position */ -#define CAN_TEST_TX_SAMPLE (CAN_TEST_TX_SAMPLE_Val << CAN_TEST_TX_Pos) /**< (CAN_TEST) TX monitoring sample point Position */ -#define CAN_TEST_TX_DOMINANT (CAN_TEST_TX_DOMINANT_Val << CAN_TEST_TX_Pos) /**< (CAN_TEST) Dominant (0) level at pin CAN_TX Position */ -#define CAN_TEST_TX_RECESSIVE (CAN_TEST_TX_RECESSIVE_Val << CAN_TEST_TX_Pos) /**< (CAN_TEST) Recessive (1) level at pin CAN_TX Position */ -#define CAN_TEST_RX_Pos _U_(7) /**< (CAN_TEST) Receive Pin Position */ -#define CAN_TEST_RX_Msk (_U_(0x1) << CAN_TEST_RX_Pos) /**< (CAN_TEST) Receive Pin Mask */ -#define CAN_TEST_RX(value) (CAN_TEST_RX_Msk & ((value) << CAN_TEST_RX_Pos)) -#define CAN_TEST_Msk _U_(0x000000F0) /**< (CAN_TEST) Register Mask */ - - -/* -------- CAN_RWD : (CAN Offset: 0x14) (R/W 32) RAM Watchdog -------- */ -#define CAN_RWD_RESETVALUE _U_(0x00) /**< (CAN_RWD) RAM Watchdog Reset Value */ - -#define CAN_RWD_WDC_Pos _U_(0) /**< (CAN_RWD) Watchdog Configuration Position */ -#define CAN_RWD_WDC_Msk (_U_(0xFF) << CAN_RWD_WDC_Pos) /**< (CAN_RWD) Watchdog Configuration Mask */ -#define CAN_RWD_WDC(value) (CAN_RWD_WDC_Msk & ((value) << CAN_RWD_WDC_Pos)) -#define CAN_RWD_WDV_Pos _U_(8) /**< (CAN_RWD) Watchdog Value Position */ -#define CAN_RWD_WDV_Msk (_U_(0xFF) << CAN_RWD_WDV_Pos) /**< (CAN_RWD) Watchdog Value Mask */ -#define CAN_RWD_WDV(value) (CAN_RWD_WDV_Msk & ((value) << CAN_RWD_WDV_Pos)) -#define CAN_RWD_Msk _U_(0x0000FFFF) /**< (CAN_RWD) Register Mask */ - - -/* -------- CAN_CCCR : (CAN Offset: 0x18) (R/W 32) CC Control -------- */ -#define CAN_CCCR_RESETVALUE _U_(0x01) /**< (CAN_CCCR) CC Control Reset Value */ - -#define CAN_CCCR_INIT_Pos _U_(0) /**< (CAN_CCCR) Initialization Position */ -#define CAN_CCCR_INIT_Msk (_U_(0x1) << CAN_CCCR_INIT_Pos) /**< (CAN_CCCR) Initialization Mask */ -#define CAN_CCCR_INIT(value) (CAN_CCCR_INIT_Msk & ((value) << CAN_CCCR_INIT_Pos)) -#define CAN_CCCR_CCE_Pos _U_(1) /**< (CAN_CCCR) Configuration Change Enable Position */ -#define CAN_CCCR_CCE_Msk (_U_(0x1) << CAN_CCCR_CCE_Pos) /**< (CAN_CCCR) Configuration Change Enable Mask */ -#define CAN_CCCR_CCE(value) (CAN_CCCR_CCE_Msk & ((value) << CAN_CCCR_CCE_Pos)) -#define CAN_CCCR_ASM_Pos _U_(2) /**< (CAN_CCCR) ASM Restricted Operation Mode Position */ -#define CAN_CCCR_ASM_Msk (_U_(0x1) << CAN_CCCR_ASM_Pos) /**< (CAN_CCCR) ASM Restricted Operation Mode Mask */ -#define CAN_CCCR_ASM(value) (CAN_CCCR_ASM_Msk & ((value) << CAN_CCCR_ASM_Pos)) -#define CAN_CCCR_CSA_Pos _U_(3) /**< (CAN_CCCR) Clock Stop Acknowledge Position */ -#define CAN_CCCR_CSA_Msk (_U_(0x1) << CAN_CCCR_CSA_Pos) /**< (CAN_CCCR) Clock Stop Acknowledge Mask */ -#define CAN_CCCR_CSA(value) (CAN_CCCR_CSA_Msk & ((value) << CAN_CCCR_CSA_Pos)) -#define CAN_CCCR_CSR_Pos _U_(4) /**< (CAN_CCCR) Clock Stop Request Position */ -#define CAN_CCCR_CSR_Msk (_U_(0x1) << CAN_CCCR_CSR_Pos) /**< (CAN_CCCR) Clock Stop Request Mask */ -#define CAN_CCCR_CSR(value) (CAN_CCCR_CSR_Msk & ((value) << CAN_CCCR_CSR_Pos)) -#define CAN_CCCR_MON_Pos _U_(5) /**< (CAN_CCCR) Bus Monitoring Mode Position */ -#define CAN_CCCR_MON_Msk (_U_(0x1) << CAN_CCCR_MON_Pos) /**< (CAN_CCCR) Bus Monitoring Mode Mask */ -#define CAN_CCCR_MON(value) (CAN_CCCR_MON_Msk & ((value) << CAN_CCCR_MON_Pos)) -#define CAN_CCCR_DAR_Pos _U_(6) /**< (CAN_CCCR) Disable Automatic Retransmission Position */ -#define CAN_CCCR_DAR_Msk (_U_(0x1) << CAN_CCCR_DAR_Pos) /**< (CAN_CCCR) Disable Automatic Retransmission Mask */ -#define CAN_CCCR_DAR(value) (CAN_CCCR_DAR_Msk & ((value) << CAN_CCCR_DAR_Pos)) -#define CAN_CCCR_TEST_Pos _U_(7) /**< (CAN_CCCR) Test Mode Enable Position */ -#define CAN_CCCR_TEST_Msk (_U_(0x1) << CAN_CCCR_TEST_Pos) /**< (CAN_CCCR) Test Mode Enable Mask */ -#define CAN_CCCR_TEST(value) (CAN_CCCR_TEST_Msk & ((value) << CAN_CCCR_TEST_Pos)) -#define CAN_CCCR_FDOE_Pos _U_(8) /**< (CAN_CCCR) FD Operation Enable Position */ -#define CAN_CCCR_FDOE_Msk (_U_(0x1) << CAN_CCCR_FDOE_Pos) /**< (CAN_CCCR) FD Operation Enable Mask */ -#define CAN_CCCR_FDOE(value) (CAN_CCCR_FDOE_Msk & ((value) << CAN_CCCR_FDOE_Pos)) -#define CAN_CCCR_BRSE_Pos _U_(9) /**< (CAN_CCCR) Bit Rate Switch Enable Position */ -#define CAN_CCCR_BRSE_Msk (_U_(0x1) << CAN_CCCR_BRSE_Pos) /**< (CAN_CCCR) Bit Rate Switch Enable Mask */ -#define CAN_CCCR_BRSE(value) (CAN_CCCR_BRSE_Msk & ((value) << CAN_CCCR_BRSE_Pos)) -#define CAN_CCCR_PXHD_Pos _U_(12) /**< (CAN_CCCR) Protocol Exception Handling Disable Position */ -#define CAN_CCCR_PXHD_Msk (_U_(0x1) << CAN_CCCR_PXHD_Pos) /**< (CAN_CCCR) Protocol Exception Handling Disable Mask */ -#define CAN_CCCR_PXHD(value) (CAN_CCCR_PXHD_Msk & ((value) << CAN_CCCR_PXHD_Pos)) -#define CAN_CCCR_EFBI_Pos _U_(13) /**< (CAN_CCCR) Edge Filtering during Bus Integration Position */ -#define CAN_CCCR_EFBI_Msk (_U_(0x1) << CAN_CCCR_EFBI_Pos) /**< (CAN_CCCR) Edge Filtering during Bus Integration Mask */ -#define CAN_CCCR_EFBI(value) (CAN_CCCR_EFBI_Msk & ((value) << CAN_CCCR_EFBI_Pos)) -#define CAN_CCCR_TXP_Pos _U_(14) /**< (CAN_CCCR) Transmit Pause Position */ -#define CAN_CCCR_TXP_Msk (_U_(0x1) << CAN_CCCR_TXP_Pos) /**< (CAN_CCCR) Transmit Pause Mask */ -#define CAN_CCCR_TXP(value) (CAN_CCCR_TXP_Msk & ((value) << CAN_CCCR_TXP_Pos)) -#define CAN_CCCR_NISO_Pos _U_(15) /**< (CAN_CCCR) Non ISO Operation Position */ -#define CAN_CCCR_NISO_Msk (_U_(0x1) << CAN_CCCR_NISO_Pos) /**< (CAN_CCCR) Non ISO Operation Mask */ -#define CAN_CCCR_NISO(value) (CAN_CCCR_NISO_Msk & ((value) << CAN_CCCR_NISO_Pos)) -#define CAN_CCCR_Msk _U_(0x0000F3FF) /**< (CAN_CCCR) Register Mask */ - - -/* -------- CAN_NBTP : (CAN Offset: 0x1C) (R/W 32) Nominal Bit Timing and Prescaler -------- */ -#define CAN_NBTP_RESETVALUE _U_(0x6000A03) /**< (CAN_NBTP) Nominal Bit Timing and Prescaler Reset Value */ - -#define CAN_NBTP_NTSEG2_Pos _U_(0) /**< (CAN_NBTP) Nominal Time segment after sample point Position */ -#define CAN_NBTP_NTSEG2_Msk (_U_(0x7F) << CAN_NBTP_NTSEG2_Pos) /**< (CAN_NBTP) Nominal Time segment after sample point Mask */ -#define CAN_NBTP_NTSEG2(value) (CAN_NBTP_NTSEG2_Msk & ((value) << CAN_NBTP_NTSEG2_Pos)) -#define CAN_NBTP_NTSEG1_Pos _U_(8) /**< (CAN_NBTP) Nominal Time segment before sample point Position */ -#define CAN_NBTP_NTSEG1_Msk (_U_(0xFF) << CAN_NBTP_NTSEG1_Pos) /**< (CAN_NBTP) Nominal Time segment before sample point Mask */ -#define CAN_NBTP_NTSEG1(value) (CAN_NBTP_NTSEG1_Msk & ((value) << CAN_NBTP_NTSEG1_Pos)) -#define CAN_NBTP_NBRP_Pos _U_(16) /**< (CAN_NBTP) Nominal Baud Rate Prescaler Position */ -#define CAN_NBTP_NBRP_Msk (_U_(0x1FF) << CAN_NBTP_NBRP_Pos) /**< (CAN_NBTP) Nominal Baud Rate Prescaler Mask */ -#define CAN_NBTP_NBRP(value) (CAN_NBTP_NBRP_Msk & ((value) << CAN_NBTP_NBRP_Pos)) -#define CAN_NBTP_NSJW_Pos _U_(25) /**< (CAN_NBTP) Nominal (Re)Synchronization Jump Width Position */ -#define CAN_NBTP_NSJW_Msk (_U_(0x7F) << CAN_NBTP_NSJW_Pos) /**< (CAN_NBTP) Nominal (Re)Synchronization Jump Width Mask */ -#define CAN_NBTP_NSJW(value) (CAN_NBTP_NSJW_Msk & ((value) << CAN_NBTP_NSJW_Pos)) -#define CAN_NBTP_Msk _U_(0xFFFFFF7F) /**< (CAN_NBTP) Register Mask */ - - -/* -------- CAN_TSCC : (CAN Offset: 0x20) (R/W 32) Timestamp Counter Configuration -------- */ -#define CAN_TSCC_RESETVALUE _U_(0x00) /**< (CAN_TSCC) Timestamp Counter Configuration Reset Value */ - -#define CAN_TSCC_TSS_Pos _U_(0) /**< (CAN_TSCC) Timestamp Select Position */ -#define CAN_TSCC_TSS_Msk (_U_(0x3) << CAN_TSCC_TSS_Pos) /**< (CAN_TSCC) Timestamp Select Mask */ -#define CAN_TSCC_TSS(value) (CAN_TSCC_TSS_Msk & ((value) << CAN_TSCC_TSS_Pos)) -#define CAN_TSCC_TSS_ZERO_Val _U_(0x0) /**< (CAN_TSCC) Timestamp counter value always 0x0000 */ -#define CAN_TSCC_TSS_INC_Val _U_(0x1) /**< (CAN_TSCC) Timestamp counter value incremented by TCP */ -#define CAN_TSCC_TSS_EXT_Val _U_(0x2) /**< (CAN_TSCC) External timestamp counter value used */ -#define CAN_TSCC_TSS_ZERO (CAN_TSCC_TSS_ZERO_Val << CAN_TSCC_TSS_Pos) /**< (CAN_TSCC) Timestamp counter value always 0x0000 Position */ -#define CAN_TSCC_TSS_INC (CAN_TSCC_TSS_INC_Val << CAN_TSCC_TSS_Pos) /**< (CAN_TSCC) Timestamp counter value incremented by TCP Position */ -#define CAN_TSCC_TSS_EXT (CAN_TSCC_TSS_EXT_Val << CAN_TSCC_TSS_Pos) /**< (CAN_TSCC) External timestamp counter value used Position */ -#define CAN_TSCC_TCP_Pos _U_(16) /**< (CAN_TSCC) Timestamp Counter Prescaler Position */ -#define CAN_TSCC_TCP_Msk (_U_(0xF) << CAN_TSCC_TCP_Pos) /**< (CAN_TSCC) Timestamp Counter Prescaler Mask */ -#define CAN_TSCC_TCP(value) (CAN_TSCC_TCP_Msk & ((value) << CAN_TSCC_TCP_Pos)) -#define CAN_TSCC_Msk _U_(0x000F0003) /**< (CAN_TSCC) Register Mask */ - - -/* -------- CAN_TSCV : (CAN Offset: 0x24) ( R/ 32) Timestamp Counter Value -------- */ -#define CAN_TSCV_RESETVALUE _U_(0x00) /**< (CAN_TSCV) Timestamp Counter Value Reset Value */ - -#define CAN_TSCV_TSC_Pos _U_(0) /**< (CAN_TSCV) Timestamp Counter Position */ -#define CAN_TSCV_TSC_Msk (_U_(0xFFFF) << CAN_TSCV_TSC_Pos) /**< (CAN_TSCV) Timestamp Counter Mask */ -#define CAN_TSCV_TSC(value) (CAN_TSCV_TSC_Msk & ((value) << CAN_TSCV_TSC_Pos)) -#define CAN_TSCV_Msk _U_(0x0000FFFF) /**< (CAN_TSCV) Register Mask */ - - -/* -------- CAN_TOCC : (CAN Offset: 0x28) (R/W 32) Timeout Counter Configuration -------- */ -#define CAN_TOCC_RESETVALUE _U_(0xFFFF0000) /**< (CAN_TOCC) Timeout Counter Configuration Reset Value */ - -#define CAN_TOCC_ETOC_Pos _U_(0) /**< (CAN_TOCC) Enable Timeout Counter Position */ -#define CAN_TOCC_ETOC_Msk (_U_(0x1) << CAN_TOCC_ETOC_Pos) /**< (CAN_TOCC) Enable Timeout Counter Mask */ -#define CAN_TOCC_ETOC(value) (CAN_TOCC_ETOC_Msk & ((value) << CAN_TOCC_ETOC_Pos)) -#define CAN_TOCC_TOS_Pos _U_(1) /**< (CAN_TOCC) Timeout Select Position */ -#define CAN_TOCC_TOS_Msk (_U_(0x3) << CAN_TOCC_TOS_Pos) /**< (CAN_TOCC) Timeout Select Mask */ -#define CAN_TOCC_TOS(value) (CAN_TOCC_TOS_Msk & ((value) << CAN_TOCC_TOS_Pos)) -#define CAN_TOCC_TOS_CONT_Val _U_(0x0) /**< (CAN_TOCC) Continuout operation */ -#define CAN_TOCC_TOS_TXEF_Val _U_(0x1) /**< (CAN_TOCC) Timeout controlled by TX Event FIFO */ -#define CAN_TOCC_TOS_RXF0_Val _U_(0x2) /**< (CAN_TOCC) Timeout controlled by Rx FIFO 0 */ -#define CAN_TOCC_TOS_RXF1_Val _U_(0x3) /**< (CAN_TOCC) Timeout controlled by Rx FIFO 1 */ -#define CAN_TOCC_TOS_CONT (CAN_TOCC_TOS_CONT_Val << CAN_TOCC_TOS_Pos) /**< (CAN_TOCC) Continuout operation Position */ -#define CAN_TOCC_TOS_TXEF (CAN_TOCC_TOS_TXEF_Val << CAN_TOCC_TOS_Pos) /**< (CAN_TOCC) Timeout controlled by TX Event FIFO Position */ -#define CAN_TOCC_TOS_RXF0 (CAN_TOCC_TOS_RXF0_Val << CAN_TOCC_TOS_Pos) /**< (CAN_TOCC) Timeout controlled by Rx FIFO 0 Position */ -#define CAN_TOCC_TOS_RXF1 (CAN_TOCC_TOS_RXF1_Val << CAN_TOCC_TOS_Pos) /**< (CAN_TOCC) Timeout controlled by Rx FIFO 1 Position */ -#define CAN_TOCC_TOP_Pos _U_(16) /**< (CAN_TOCC) Timeout Period Position */ -#define CAN_TOCC_TOP_Msk (_U_(0xFFFF) << CAN_TOCC_TOP_Pos) /**< (CAN_TOCC) Timeout Period Mask */ -#define CAN_TOCC_TOP(value) (CAN_TOCC_TOP_Msk & ((value) << CAN_TOCC_TOP_Pos)) -#define CAN_TOCC_Msk _U_(0xFFFF0007) /**< (CAN_TOCC) Register Mask */ - - -/* -------- CAN_TOCV : (CAN Offset: 0x2C) (R/W 32) Timeout Counter Value -------- */ -#define CAN_TOCV_RESETVALUE _U_(0xFFFF) /**< (CAN_TOCV) Timeout Counter Value Reset Value */ - -#define CAN_TOCV_TOC_Pos _U_(0) /**< (CAN_TOCV) Timeout Counter Position */ -#define CAN_TOCV_TOC_Msk (_U_(0xFFFF) << CAN_TOCV_TOC_Pos) /**< (CAN_TOCV) Timeout Counter Mask */ -#define CAN_TOCV_TOC(value) (CAN_TOCV_TOC_Msk & ((value) << CAN_TOCV_TOC_Pos)) -#define CAN_TOCV_Msk _U_(0x0000FFFF) /**< (CAN_TOCV) Register Mask */ - - -/* -------- CAN_ECR : (CAN Offset: 0x40) ( R/ 32) Error Counter -------- */ -#define CAN_ECR_RESETVALUE _U_(0x00) /**< (CAN_ECR) Error Counter Reset Value */ - -#define CAN_ECR_TEC_Pos _U_(0) /**< (CAN_ECR) Transmit Error Counter Position */ -#define CAN_ECR_TEC_Msk (_U_(0xFF) << CAN_ECR_TEC_Pos) /**< (CAN_ECR) Transmit Error Counter Mask */ -#define CAN_ECR_TEC(value) (CAN_ECR_TEC_Msk & ((value) << CAN_ECR_TEC_Pos)) -#define CAN_ECR_REC_Pos _U_(8) /**< (CAN_ECR) Receive Error Counter Position */ -#define CAN_ECR_REC_Msk (_U_(0x7F) << CAN_ECR_REC_Pos) /**< (CAN_ECR) Receive Error Counter Mask */ -#define CAN_ECR_REC(value) (CAN_ECR_REC_Msk & ((value) << CAN_ECR_REC_Pos)) -#define CAN_ECR_RP_Pos _U_(15) /**< (CAN_ECR) Receive Error Passive Position */ -#define CAN_ECR_RP_Msk (_U_(0x1) << CAN_ECR_RP_Pos) /**< (CAN_ECR) Receive Error Passive Mask */ -#define CAN_ECR_RP(value) (CAN_ECR_RP_Msk & ((value) << CAN_ECR_RP_Pos)) -#define CAN_ECR_CEL_Pos _U_(16) /**< (CAN_ECR) CAN Error Logging Position */ -#define CAN_ECR_CEL_Msk (_U_(0xFF) << CAN_ECR_CEL_Pos) /**< (CAN_ECR) CAN Error Logging Mask */ -#define CAN_ECR_CEL(value) (CAN_ECR_CEL_Msk & ((value) << CAN_ECR_CEL_Pos)) -#define CAN_ECR_Msk _U_(0x00FFFFFF) /**< (CAN_ECR) Register Mask */ - - -/* -------- CAN_PSR : (CAN Offset: 0x44) ( R/ 32) Protocol Status -------- */ -#define CAN_PSR_RESETVALUE _U_(0x707) /**< (CAN_PSR) Protocol Status Reset Value */ - -#define CAN_PSR_LEC_Pos _U_(0) /**< (CAN_PSR) Last Error Code Position */ -#define CAN_PSR_LEC_Msk (_U_(0x7) << CAN_PSR_LEC_Pos) /**< (CAN_PSR) Last Error Code Mask */ -#define CAN_PSR_LEC(value) (CAN_PSR_LEC_Msk & ((value) << CAN_PSR_LEC_Pos)) -#define CAN_PSR_LEC_NONE_Val _U_(0x0) /**< (CAN_PSR) No Error */ -#define CAN_PSR_LEC_STUFF_Val _U_(0x1) /**< (CAN_PSR) Stuff Error */ -#define CAN_PSR_LEC_FORM_Val _U_(0x2) /**< (CAN_PSR) Form Error */ -#define CAN_PSR_LEC_ACK_Val _U_(0x3) /**< (CAN_PSR) Ack Error */ -#define CAN_PSR_LEC_BIT1_Val _U_(0x4) /**< (CAN_PSR) Bit1 Error */ -#define CAN_PSR_LEC_BIT0_Val _U_(0x5) /**< (CAN_PSR) Bit0 Error */ -#define CAN_PSR_LEC_CRC_Val _U_(0x6) /**< (CAN_PSR) CRC Error */ -#define CAN_PSR_LEC_NC_Val _U_(0x7) /**< (CAN_PSR) No Change */ -#define CAN_PSR_LEC_NONE (CAN_PSR_LEC_NONE_Val << CAN_PSR_LEC_Pos) /**< (CAN_PSR) No Error Position */ -#define CAN_PSR_LEC_STUFF (CAN_PSR_LEC_STUFF_Val << CAN_PSR_LEC_Pos) /**< (CAN_PSR) Stuff Error Position */ -#define CAN_PSR_LEC_FORM (CAN_PSR_LEC_FORM_Val << CAN_PSR_LEC_Pos) /**< (CAN_PSR) Form Error Position */ -#define CAN_PSR_LEC_ACK (CAN_PSR_LEC_ACK_Val << CAN_PSR_LEC_Pos) /**< (CAN_PSR) Ack Error Position */ -#define CAN_PSR_LEC_BIT1 (CAN_PSR_LEC_BIT1_Val << CAN_PSR_LEC_Pos) /**< (CAN_PSR) Bit1 Error Position */ -#define CAN_PSR_LEC_BIT0 (CAN_PSR_LEC_BIT0_Val << CAN_PSR_LEC_Pos) /**< (CAN_PSR) Bit0 Error Position */ -#define CAN_PSR_LEC_CRC (CAN_PSR_LEC_CRC_Val << CAN_PSR_LEC_Pos) /**< (CAN_PSR) CRC Error Position */ -#define CAN_PSR_LEC_NC (CAN_PSR_LEC_NC_Val << CAN_PSR_LEC_Pos) /**< (CAN_PSR) No Change Position */ -#define CAN_PSR_ACT_Pos _U_(3) /**< (CAN_PSR) Activity Position */ -#define CAN_PSR_ACT_Msk (_U_(0x3) << CAN_PSR_ACT_Pos) /**< (CAN_PSR) Activity Mask */ -#define CAN_PSR_ACT(value) (CAN_PSR_ACT_Msk & ((value) << CAN_PSR_ACT_Pos)) -#define CAN_PSR_ACT_SYNC_Val _U_(0x0) /**< (CAN_PSR) Node is synchronizing on CAN communication */ -#define CAN_PSR_ACT_IDLE_Val _U_(0x1) /**< (CAN_PSR) Node is neither receiver nor transmitter */ -#define CAN_PSR_ACT_RX_Val _U_(0x2) /**< (CAN_PSR) Node is operating as receiver */ -#define CAN_PSR_ACT_TX_Val _U_(0x3) /**< (CAN_PSR) Node is operating as transmitter */ -#define CAN_PSR_ACT_SYNC (CAN_PSR_ACT_SYNC_Val << CAN_PSR_ACT_Pos) /**< (CAN_PSR) Node is synchronizing on CAN communication Position */ -#define CAN_PSR_ACT_IDLE (CAN_PSR_ACT_IDLE_Val << CAN_PSR_ACT_Pos) /**< (CAN_PSR) Node is neither receiver nor transmitter Position */ -#define CAN_PSR_ACT_RX (CAN_PSR_ACT_RX_Val << CAN_PSR_ACT_Pos) /**< (CAN_PSR) Node is operating as receiver Position */ -#define CAN_PSR_ACT_TX (CAN_PSR_ACT_TX_Val << CAN_PSR_ACT_Pos) /**< (CAN_PSR) Node is operating as transmitter Position */ -#define CAN_PSR_EP_Pos _U_(5) /**< (CAN_PSR) Error Passive Position */ -#define CAN_PSR_EP_Msk (_U_(0x1) << CAN_PSR_EP_Pos) /**< (CAN_PSR) Error Passive Mask */ -#define CAN_PSR_EP(value) (CAN_PSR_EP_Msk & ((value) << CAN_PSR_EP_Pos)) -#define CAN_PSR_EW_Pos _U_(6) /**< (CAN_PSR) Warning Status Position */ -#define CAN_PSR_EW_Msk (_U_(0x1) << CAN_PSR_EW_Pos) /**< (CAN_PSR) Warning Status Mask */ -#define CAN_PSR_EW(value) (CAN_PSR_EW_Msk & ((value) << CAN_PSR_EW_Pos)) -#define CAN_PSR_BO_Pos _U_(7) /**< (CAN_PSR) Bus_Off Status Position */ -#define CAN_PSR_BO_Msk (_U_(0x1) << CAN_PSR_BO_Pos) /**< (CAN_PSR) Bus_Off Status Mask */ -#define CAN_PSR_BO(value) (CAN_PSR_BO_Msk & ((value) << CAN_PSR_BO_Pos)) -#define CAN_PSR_DLEC_Pos _U_(8) /**< (CAN_PSR) Data Phase Last Error Code Position */ -#define CAN_PSR_DLEC_Msk (_U_(0x7) << CAN_PSR_DLEC_Pos) /**< (CAN_PSR) Data Phase Last Error Code Mask */ -#define CAN_PSR_DLEC(value) (CAN_PSR_DLEC_Msk & ((value) << CAN_PSR_DLEC_Pos)) -#define CAN_PSR_DLEC_NONE_Val _U_(0x0) /**< (CAN_PSR) No Error */ -#define CAN_PSR_DLEC_STUFF_Val _U_(0x1) /**< (CAN_PSR) Stuff Error */ -#define CAN_PSR_DLEC_FORM_Val _U_(0x2) /**< (CAN_PSR) Form Error */ -#define CAN_PSR_DLEC_ACK_Val _U_(0x3) /**< (CAN_PSR) Ack Error */ -#define CAN_PSR_DLEC_BIT1_Val _U_(0x4) /**< (CAN_PSR) Bit1 Error */ -#define CAN_PSR_DLEC_BIT0_Val _U_(0x5) /**< (CAN_PSR) Bit0 Error */ -#define CAN_PSR_DLEC_CRC_Val _U_(0x6) /**< (CAN_PSR) CRC Error */ -#define CAN_PSR_DLEC_NC_Val _U_(0x7) /**< (CAN_PSR) No Change */ -#define CAN_PSR_DLEC_NONE (CAN_PSR_DLEC_NONE_Val << CAN_PSR_DLEC_Pos) /**< (CAN_PSR) No Error Position */ -#define CAN_PSR_DLEC_STUFF (CAN_PSR_DLEC_STUFF_Val << CAN_PSR_DLEC_Pos) /**< (CAN_PSR) Stuff Error Position */ -#define CAN_PSR_DLEC_FORM (CAN_PSR_DLEC_FORM_Val << CAN_PSR_DLEC_Pos) /**< (CAN_PSR) Form Error Position */ -#define CAN_PSR_DLEC_ACK (CAN_PSR_DLEC_ACK_Val << CAN_PSR_DLEC_Pos) /**< (CAN_PSR) Ack Error Position */ -#define CAN_PSR_DLEC_BIT1 (CAN_PSR_DLEC_BIT1_Val << CAN_PSR_DLEC_Pos) /**< (CAN_PSR) Bit1 Error Position */ -#define CAN_PSR_DLEC_BIT0 (CAN_PSR_DLEC_BIT0_Val << CAN_PSR_DLEC_Pos) /**< (CAN_PSR) Bit0 Error Position */ -#define CAN_PSR_DLEC_CRC (CAN_PSR_DLEC_CRC_Val << CAN_PSR_DLEC_Pos) /**< (CAN_PSR) CRC Error Position */ -#define CAN_PSR_DLEC_NC (CAN_PSR_DLEC_NC_Val << CAN_PSR_DLEC_Pos) /**< (CAN_PSR) No Change Position */ -#define CAN_PSR_RESI_Pos _U_(11) /**< (CAN_PSR) ESI flag of last received CAN FD Message Position */ -#define CAN_PSR_RESI_Msk (_U_(0x1) << CAN_PSR_RESI_Pos) /**< (CAN_PSR) ESI flag of last received CAN FD Message Mask */ -#define CAN_PSR_RESI(value) (CAN_PSR_RESI_Msk & ((value) << CAN_PSR_RESI_Pos)) -#define CAN_PSR_RBRS_Pos _U_(12) /**< (CAN_PSR) BRS flag of last received CAN FD Message Position */ -#define CAN_PSR_RBRS_Msk (_U_(0x1) << CAN_PSR_RBRS_Pos) /**< (CAN_PSR) BRS flag of last received CAN FD Message Mask */ -#define CAN_PSR_RBRS(value) (CAN_PSR_RBRS_Msk & ((value) << CAN_PSR_RBRS_Pos)) -#define CAN_PSR_RFDF_Pos _U_(13) /**< (CAN_PSR) Received a CAN FD Message Position */ -#define CAN_PSR_RFDF_Msk (_U_(0x1) << CAN_PSR_RFDF_Pos) /**< (CAN_PSR) Received a CAN FD Message Mask */ -#define CAN_PSR_RFDF(value) (CAN_PSR_RFDF_Msk & ((value) << CAN_PSR_RFDF_Pos)) -#define CAN_PSR_PXE_Pos _U_(14) /**< (CAN_PSR) Protocol Exception Event Position */ -#define CAN_PSR_PXE_Msk (_U_(0x1) << CAN_PSR_PXE_Pos) /**< (CAN_PSR) Protocol Exception Event Mask */ -#define CAN_PSR_PXE(value) (CAN_PSR_PXE_Msk & ((value) << CAN_PSR_PXE_Pos)) -#define CAN_PSR_TDCV_Pos _U_(16) /**< (CAN_PSR) Transmitter Delay Compensation Value Position */ -#define CAN_PSR_TDCV_Msk (_U_(0x7F) << CAN_PSR_TDCV_Pos) /**< (CAN_PSR) Transmitter Delay Compensation Value Mask */ -#define CAN_PSR_TDCV(value) (CAN_PSR_TDCV_Msk & ((value) << CAN_PSR_TDCV_Pos)) -#define CAN_PSR_Msk _U_(0x007F7FFF) /**< (CAN_PSR) Register Mask */ - - -/* -------- CAN_TDCR : (CAN Offset: 0x48) (R/W 32) Extended ID Filter Configuration -------- */ -#define CAN_TDCR_RESETVALUE _U_(0x00) /**< (CAN_TDCR) Extended ID Filter Configuration Reset Value */ - -#define CAN_TDCR_TDCF_Pos _U_(0) /**< (CAN_TDCR) Transmitter Delay Compensation Filter Length Position */ -#define CAN_TDCR_TDCF_Msk (_U_(0x7F) << CAN_TDCR_TDCF_Pos) /**< (CAN_TDCR) Transmitter Delay Compensation Filter Length Mask */ -#define CAN_TDCR_TDCF(value) (CAN_TDCR_TDCF_Msk & ((value) << CAN_TDCR_TDCF_Pos)) -#define CAN_TDCR_TDCO_Pos _U_(8) /**< (CAN_TDCR) Transmitter Delay Compensation Offset Position */ -#define CAN_TDCR_TDCO_Msk (_U_(0x7F) << CAN_TDCR_TDCO_Pos) /**< (CAN_TDCR) Transmitter Delay Compensation Offset Mask */ -#define CAN_TDCR_TDCO(value) (CAN_TDCR_TDCO_Msk & ((value) << CAN_TDCR_TDCO_Pos)) -#define CAN_TDCR_Msk _U_(0x00007F7F) /**< (CAN_TDCR) Register Mask */ - - -/* -------- CAN_IR : (CAN Offset: 0x50) (R/W 32) Interrupt -------- */ -#define CAN_IR_RESETVALUE _U_(0x00) /**< (CAN_IR) Interrupt Reset Value */ - -#define CAN_IR_RF0N_Pos _U_(0) /**< (CAN_IR) Rx FIFO 0 New Message Position */ -#define CAN_IR_RF0N_Msk (_U_(0x1) << CAN_IR_RF0N_Pos) /**< (CAN_IR) Rx FIFO 0 New Message Mask */ -#define CAN_IR_RF0N(value) (CAN_IR_RF0N_Msk & ((value) << CAN_IR_RF0N_Pos)) -#define CAN_IR_RF0W_Pos _U_(1) /**< (CAN_IR) Rx FIFO 0 Watermark Reached Position */ -#define CAN_IR_RF0W_Msk (_U_(0x1) << CAN_IR_RF0W_Pos) /**< (CAN_IR) Rx FIFO 0 Watermark Reached Mask */ -#define CAN_IR_RF0W(value) (CAN_IR_RF0W_Msk & ((value) << CAN_IR_RF0W_Pos)) -#define CAN_IR_RF0F_Pos _U_(2) /**< (CAN_IR) Rx FIFO 0 Full Position */ -#define CAN_IR_RF0F_Msk (_U_(0x1) << CAN_IR_RF0F_Pos) /**< (CAN_IR) Rx FIFO 0 Full Mask */ -#define CAN_IR_RF0F(value) (CAN_IR_RF0F_Msk & ((value) << CAN_IR_RF0F_Pos)) -#define CAN_IR_RF0L_Pos _U_(3) /**< (CAN_IR) Rx FIFO 0 Message Lost Position */ -#define CAN_IR_RF0L_Msk (_U_(0x1) << CAN_IR_RF0L_Pos) /**< (CAN_IR) Rx FIFO 0 Message Lost Mask */ -#define CAN_IR_RF0L(value) (CAN_IR_RF0L_Msk & ((value) << CAN_IR_RF0L_Pos)) -#define CAN_IR_RF1N_Pos _U_(4) /**< (CAN_IR) Rx FIFO 1 New Message Position */ -#define CAN_IR_RF1N_Msk (_U_(0x1) << CAN_IR_RF1N_Pos) /**< (CAN_IR) Rx FIFO 1 New Message Mask */ -#define CAN_IR_RF1N(value) (CAN_IR_RF1N_Msk & ((value) << CAN_IR_RF1N_Pos)) -#define CAN_IR_RF1W_Pos _U_(5) /**< (CAN_IR) Rx FIFO 1 Watermark Reached Position */ -#define CAN_IR_RF1W_Msk (_U_(0x1) << CAN_IR_RF1W_Pos) /**< (CAN_IR) Rx FIFO 1 Watermark Reached Mask */ -#define CAN_IR_RF1W(value) (CAN_IR_RF1W_Msk & ((value) << CAN_IR_RF1W_Pos)) -#define CAN_IR_RF1F_Pos _U_(6) /**< (CAN_IR) Rx FIFO 1 FIFO Full Position */ -#define CAN_IR_RF1F_Msk (_U_(0x1) << CAN_IR_RF1F_Pos) /**< (CAN_IR) Rx FIFO 1 FIFO Full Mask */ -#define CAN_IR_RF1F(value) (CAN_IR_RF1F_Msk & ((value) << CAN_IR_RF1F_Pos)) -#define CAN_IR_RF1L_Pos _U_(7) /**< (CAN_IR) Rx FIFO 1 Message Lost Position */ -#define CAN_IR_RF1L_Msk (_U_(0x1) << CAN_IR_RF1L_Pos) /**< (CAN_IR) Rx FIFO 1 Message Lost Mask */ -#define CAN_IR_RF1L(value) (CAN_IR_RF1L_Msk & ((value) << CAN_IR_RF1L_Pos)) -#define CAN_IR_HPM_Pos _U_(8) /**< (CAN_IR) High Priority Message Position */ -#define CAN_IR_HPM_Msk (_U_(0x1) << CAN_IR_HPM_Pos) /**< (CAN_IR) High Priority Message Mask */ -#define CAN_IR_HPM(value) (CAN_IR_HPM_Msk & ((value) << CAN_IR_HPM_Pos)) -#define CAN_IR_TC_Pos _U_(9) /**< (CAN_IR) Timestamp Completed Position */ -#define CAN_IR_TC_Msk (_U_(0x1) << CAN_IR_TC_Pos) /**< (CAN_IR) Timestamp Completed Mask */ -#define CAN_IR_TC(value) (CAN_IR_TC_Msk & ((value) << CAN_IR_TC_Pos)) -#define CAN_IR_TCF_Pos _U_(10) /**< (CAN_IR) Transmission Cancellation Finished Position */ -#define CAN_IR_TCF_Msk (_U_(0x1) << CAN_IR_TCF_Pos) /**< (CAN_IR) Transmission Cancellation Finished Mask */ -#define CAN_IR_TCF(value) (CAN_IR_TCF_Msk & ((value) << CAN_IR_TCF_Pos)) -#define CAN_IR_TFE_Pos _U_(11) /**< (CAN_IR) Tx FIFO Empty Position */ -#define CAN_IR_TFE_Msk (_U_(0x1) << CAN_IR_TFE_Pos) /**< (CAN_IR) Tx FIFO Empty Mask */ -#define CAN_IR_TFE(value) (CAN_IR_TFE_Msk & ((value) << CAN_IR_TFE_Pos)) -#define CAN_IR_TEFN_Pos _U_(12) /**< (CAN_IR) Tx Event FIFO New Entry Position */ -#define CAN_IR_TEFN_Msk (_U_(0x1) << CAN_IR_TEFN_Pos) /**< (CAN_IR) Tx Event FIFO New Entry Mask */ -#define CAN_IR_TEFN(value) (CAN_IR_TEFN_Msk & ((value) << CAN_IR_TEFN_Pos)) -#define CAN_IR_TEFW_Pos _U_(13) /**< (CAN_IR) Tx Event FIFO Watermark Reached Position */ -#define CAN_IR_TEFW_Msk (_U_(0x1) << CAN_IR_TEFW_Pos) /**< (CAN_IR) Tx Event FIFO Watermark Reached Mask */ -#define CAN_IR_TEFW(value) (CAN_IR_TEFW_Msk & ((value) << CAN_IR_TEFW_Pos)) -#define CAN_IR_TEFF_Pos _U_(14) /**< (CAN_IR) Tx Event FIFO Full Position */ -#define CAN_IR_TEFF_Msk (_U_(0x1) << CAN_IR_TEFF_Pos) /**< (CAN_IR) Tx Event FIFO Full Mask */ -#define CAN_IR_TEFF(value) (CAN_IR_TEFF_Msk & ((value) << CAN_IR_TEFF_Pos)) -#define CAN_IR_TEFL_Pos _U_(15) /**< (CAN_IR) Tx Event FIFO Element Lost Position */ -#define CAN_IR_TEFL_Msk (_U_(0x1) << CAN_IR_TEFL_Pos) /**< (CAN_IR) Tx Event FIFO Element Lost Mask */ -#define CAN_IR_TEFL(value) (CAN_IR_TEFL_Msk & ((value) << CAN_IR_TEFL_Pos)) -#define CAN_IR_TSW_Pos _U_(16) /**< (CAN_IR) Timestamp Wraparound Position */ -#define CAN_IR_TSW_Msk (_U_(0x1) << CAN_IR_TSW_Pos) /**< (CAN_IR) Timestamp Wraparound Mask */ -#define CAN_IR_TSW(value) (CAN_IR_TSW_Msk & ((value) << CAN_IR_TSW_Pos)) -#define CAN_IR_MRAF_Pos _U_(17) /**< (CAN_IR) Message RAM Access Failure Position */ -#define CAN_IR_MRAF_Msk (_U_(0x1) << CAN_IR_MRAF_Pos) /**< (CAN_IR) Message RAM Access Failure Mask */ -#define CAN_IR_MRAF(value) (CAN_IR_MRAF_Msk & ((value) << CAN_IR_MRAF_Pos)) -#define CAN_IR_TOO_Pos _U_(18) /**< (CAN_IR) Timeout Occurred Position */ -#define CAN_IR_TOO_Msk (_U_(0x1) << CAN_IR_TOO_Pos) /**< (CAN_IR) Timeout Occurred Mask */ -#define CAN_IR_TOO(value) (CAN_IR_TOO_Msk & ((value) << CAN_IR_TOO_Pos)) -#define CAN_IR_DRX_Pos _U_(19) /**< (CAN_IR) Message stored to Dedicated Rx Buffer Position */ -#define CAN_IR_DRX_Msk (_U_(0x1) << CAN_IR_DRX_Pos) /**< (CAN_IR) Message stored to Dedicated Rx Buffer Mask */ -#define CAN_IR_DRX(value) (CAN_IR_DRX_Msk & ((value) << CAN_IR_DRX_Pos)) -#define CAN_IR_BEC_Pos _U_(20) /**< (CAN_IR) Bit Error Corrected Position */ -#define CAN_IR_BEC_Msk (_U_(0x1) << CAN_IR_BEC_Pos) /**< (CAN_IR) Bit Error Corrected Mask */ -#define CAN_IR_BEC(value) (CAN_IR_BEC_Msk & ((value) << CAN_IR_BEC_Pos)) -#define CAN_IR_BEU_Pos _U_(21) /**< (CAN_IR) Bit Error Uncorrected Position */ -#define CAN_IR_BEU_Msk (_U_(0x1) << CAN_IR_BEU_Pos) /**< (CAN_IR) Bit Error Uncorrected Mask */ -#define CAN_IR_BEU(value) (CAN_IR_BEU_Msk & ((value) << CAN_IR_BEU_Pos)) -#define CAN_IR_ELO_Pos _U_(22) /**< (CAN_IR) Error Logging Overflow Position */ -#define CAN_IR_ELO_Msk (_U_(0x1) << CAN_IR_ELO_Pos) /**< (CAN_IR) Error Logging Overflow Mask */ -#define CAN_IR_ELO(value) (CAN_IR_ELO_Msk & ((value) << CAN_IR_ELO_Pos)) -#define CAN_IR_EP_Pos _U_(23) /**< (CAN_IR) Error Passive Position */ -#define CAN_IR_EP_Msk (_U_(0x1) << CAN_IR_EP_Pos) /**< (CAN_IR) Error Passive Mask */ -#define CAN_IR_EP(value) (CAN_IR_EP_Msk & ((value) << CAN_IR_EP_Pos)) -#define CAN_IR_EW_Pos _U_(24) /**< (CAN_IR) Warning Status Position */ -#define CAN_IR_EW_Msk (_U_(0x1) << CAN_IR_EW_Pos) /**< (CAN_IR) Warning Status Mask */ -#define CAN_IR_EW(value) (CAN_IR_EW_Msk & ((value) << CAN_IR_EW_Pos)) -#define CAN_IR_BO_Pos _U_(25) /**< (CAN_IR) Bus_Off Status Position */ -#define CAN_IR_BO_Msk (_U_(0x1) << CAN_IR_BO_Pos) /**< (CAN_IR) Bus_Off Status Mask */ -#define CAN_IR_BO(value) (CAN_IR_BO_Msk & ((value) << CAN_IR_BO_Pos)) -#define CAN_IR_WDI_Pos _U_(26) /**< (CAN_IR) Watchdog Interrupt Position */ -#define CAN_IR_WDI_Msk (_U_(0x1) << CAN_IR_WDI_Pos) /**< (CAN_IR) Watchdog Interrupt Mask */ -#define CAN_IR_WDI(value) (CAN_IR_WDI_Msk & ((value) << CAN_IR_WDI_Pos)) -#define CAN_IR_PEA_Pos _U_(27) /**< (CAN_IR) Protocol Error in Arbitration Phase Position */ -#define CAN_IR_PEA_Msk (_U_(0x1) << CAN_IR_PEA_Pos) /**< (CAN_IR) Protocol Error in Arbitration Phase Mask */ -#define CAN_IR_PEA(value) (CAN_IR_PEA_Msk & ((value) << CAN_IR_PEA_Pos)) -#define CAN_IR_PED_Pos _U_(28) /**< (CAN_IR) Protocol Error in Data Phase Position */ -#define CAN_IR_PED_Msk (_U_(0x1) << CAN_IR_PED_Pos) /**< (CAN_IR) Protocol Error in Data Phase Mask */ -#define CAN_IR_PED(value) (CAN_IR_PED_Msk & ((value) << CAN_IR_PED_Pos)) -#define CAN_IR_ARA_Pos _U_(29) /**< (CAN_IR) Access to Reserved Address Position */ -#define CAN_IR_ARA_Msk (_U_(0x1) << CAN_IR_ARA_Pos) /**< (CAN_IR) Access to Reserved Address Mask */ -#define CAN_IR_ARA(value) (CAN_IR_ARA_Msk & ((value) << CAN_IR_ARA_Pos)) -#define CAN_IR_Msk _U_(0x3FFFFFFF) /**< (CAN_IR) Register Mask */ - - -/* -------- CAN_IE : (CAN Offset: 0x54) (R/W 32) Interrupt Enable -------- */ -#define CAN_IE_RESETVALUE _U_(0x00) /**< (CAN_IE) Interrupt Enable Reset Value */ - -#define CAN_IE_RF0NE_Pos _U_(0) /**< (CAN_IE) Rx FIFO 0 New Message Interrupt Enable Position */ -#define CAN_IE_RF0NE_Msk (_U_(0x1) << CAN_IE_RF0NE_Pos) /**< (CAN_IE) Rx FIFO 0 New Message Interrupt Enable Mask */ -#define CAN_IE_RF0NE(value) (CAN_IE_RF0NE_Msk & ((value) << CAN_IE_RF0NE_Pos)) -#define CAN_IE_RF0WE_Pos _U_(1) /**< (CAN_IE) Rx FIFO 0 Watermark Reached Interrupt Enable Position */ -#define CAN_IE_RF0WE_Msk (_U_(0x1) << CAN_IE_RF0WE_Pos) /**< (CAN_IE) Rx FIFO 0 Watermark Reached Interrupt Enable Mask */ -#define CAN_IE_RF0WE(value) (CAN_IE_RF0WE_Msk & ((value) << CAN_IE_RF0WE_Pos)) -#define CAN_IE_RF0FE_Pos _U_(2) /**< (CAN_IE) Rx FIFO 0 Full Interrupt Enable Position */ -#define CAN_IE_RF0FE_Msk (_U_(0x1) << CAN_IE_RF0FE_Pos) /**< (CAN_IE) Rx FIFO 0 Full Interrupt Enable Mask */ -#define CAN_IE_RF0FE(value) (CAN_IE_RF0FE_Msk & ((value) << CAN_IE_RF0FE_Pos)) -#define CAN_IE_RF0LE_Pos _U_(3) /**< (CAN_IE) Rx FIFO 0 Message Lost Interrupt Enable Position */ -#define CAN_IE_RF0LE_Msk (_U_(0x1) << CAN_IE_RF0LE_Pos) /**< (CAN_IE) Rx FIFO 0 Message Lost Interrupt Enable Mask */ -#define CAN_IE_RF0LE(value) (CAN_IE_RF0LE_Msk & ((value) << CAN_IE_RF0LE_Pos)) -#define CAN_IE_RF1NE_Pos _U_(4) /**< (CAN_IE) Rx FIFO 1 New Message Interrupt Enable Position */ -#define CAN_IE_RF1NE_Msk (_U_(0x1) << CAN_IE_RF1NE_Pos) /**< (CAN_IE) Rx FIFO 1 New Message Interrupt Enable Mask */ -#define CAN_IE_RF1NE(value) (CAN_IE_RF1NE_Msk & ((value) << CAN_IE_RF1NE_Pos)) -#define CAN_IE_RF1WE_Pos _U_(5) /**< (CAN_IE) Rx FIFO 1 Watermark Reached Interrupt Enable Position */ -#define CAN_IE_RF1WE_Msk (_U_(0x1) << CAN_IE_RF1WE_Pos) /**< (CAN_IE) Rx FIFO 1 Watermark Reached Interrupt Enable Mask */ -#define CAN_IE_RF1WE(value) (CAN_IE_RF1WE_Msk & ((value) << CAN_IE_RF1WE_Pos)) -#define CAN_IE_RF1FE_Pos _U_(6) /**< (CAN_IE) Rx FIFO 1 FIFO Full Interrupt Enable Position */ -#define CAN_IE_RF1FE_Msk (_U_(0x1) << CAN_IE_RF1FE_Pos) /**< (CAN_IE) Rx FIFO 1 FIFO Full Interrupt Enable Mask */ -#define CAN_IE_RF1FE(value) (CAN_IE_RF1FE_Msk & ((value) << CAN_IE_RF1FE_Pos)) -#define CAN_IE_RF1LE_Pos _U_(7) /**< (CAN_IE) Rx FIFO 1 Message Lost Interrupt Enable Position */ -#define CAN_IE_RF1LE_Msk (_U_(0x1) << CAN_IE_RF1LE_Pos) /**< (CAN_IE) Rx FIFO 1 Message Lost Interrupt Enable Mask */ -#define CAN_IE_RF1LE(value) (CAN_IE_RF1LE_Msk & ((value) << CAN_IE_RF1LE_Pos)) -#define CAN_IE_HPME_Pos _U_(8) /**< (CAN_IE) High Priority Message Interrupt Enable Position */ -#define CAN_IE_HPME_Msk (_U_(0x1) << CAN_IE_HPME_Pos) /**< (CAN_IE) High Priority Message Interrupt Enable Mask */ -#define CAN_IE_HPME(value) (CAN_IE_HPME_Msk & ((value) << CAN_IE_HPME_Pos)) -#define CAN_IE_TCE_Pos _U_(9) /**< (CAN_IE) Timestamp Completed Interrupt Enable Position */ -#define CAN_IE_TCE_Msk (_U_(0x1) << CAN_IE_TCE_Pos) /**< (CAN_IE) Timestamp Completed Interrupt Enable Mask */ -#define CAN_IE_TCE(value) (CAN_IE_TCE_Msk & ((value) << CAN_IE_TCE_Pos)) -#define CAN_IE_TCFE_Pos _U_(10) /**< (CAN_IE) Transmission Cancellation Finished Interrupt Enable Position */ -#define CAN_IE_TCFE_Msk (_U_(0x1) << CAN_IE_TCFE_Pos) /**< (CAN_IE) Transmission Cancellation Finished Interrupt Enable Mask */ -#define CAN_IE_TCFE(value) (CAN_IE_TCFE_Msk & ((value) << CAN_IE_TCFE_Pos)) -#define CAN_IE_TFEE_Pos _U_(11) /**< (CAN_IE) Tx FIFO Empty Interrupt Enable Position */ -#define CAN_IE_TFEE_Msk (_U_(0x1) << CAN_IE_TFEE_Pos) /**< (CAN_IE) Tx FIFO Empty Interrupt Enable Mask */ -#define CAN_IE_TFEE(value) (CAN_IE_TFEE_Msk & ((value) << CAN_IE_TFEE_Pos)) -#define CAN_IE_TEFNE_Pos _U_(12) /**< (CAN_IE) Tx Event FIFO New Entry Interrupt Enable Position */ -#define CAN_IE_TEFNE_Msk (_U_(0x1) << CAN_IE_TEFNE_Pos) /**< (CAN_IE) Tx Event FIFO New Entry Interrupt Enable Mask */ -#define CAN_IE_TEFNE(value) (CAN_IE_TEFNE_Msk & ((value) << CAN_IE_TEFNE_Pos)) -#define CAN_IE_TEFWE_Pos _U_(13) /**< (CAN_IE) Tx Event FIFO Watermark Reached Interrupt Enable Position */ -#define CAN_IE_TEFWE_Msk (_U_(0x1) << CAN_IE_TEFWE_Pos) /**< (CAN_IE) Tx Event FIFO Watermark Reached Interrupt Enable Mask */ -#define CAN_IE_TEFWE(value) (CAN_IE_TEFWE_Msk & ((value) << CAN_IE_TEFWE_Pos)) -#define CAN_IE_TEFFE_Pos _U_(14) /**< (CAN_IE) Tx Event FIFO Full Interrupt Enable Position */ -#define CAN_IE_TEFFE_Msk (_U_(0x1) << CAN_IE_TEFFE_Pos) /**< (CAN_IE) Tx Event FIFO Full Interrupt Enable Mask */ -#define CAN_IE_TEFFE(value) (CAN_IE_TEFFE_Msk & ((value) << CAN_IE_TEFFE_Pos)) -#define CAN_IE_TEFLE_Pos _U_(15) /**< (CAN_IE) Tx Event FIFO Element Lost Interrupt Enable Position */ -#define CAN_IE_TEFLE_Msk (_U_(0x1) << CAN_IE_TEFLE_Pos) /**< (CAN_IE) Tx Event FIFO Element Lost Interrupt Enable Mask */ -#define CAN_IE_TEFLE(value) (CAN_IE_TEFLE_Msk & ((value) << CAN_IE_TEFLE_Pos)) -#define CAN_IE_TSWE_Pos _U_(16) /**< (CAN_IE) Timestamp Wraparound Interrupt Enable Position */ -#define CAN_IE_TSWE_Msk (_U_(0x1) << CAN_IE_TSWE_Pos) /**< (CAN_IE) Timestamp Wraparound Interrupt Enable Mask */ -#define CAN_IE_TSWE(value) (CAN_IE_TSWE_Msk & ((value) << CAN_IE_TSWE_Pos)) -#define CAN_IE_MRAFE_Pos _U_(17) /**< (CAN_IE) Message RAM Access Failure Interrupt Enable Position */ -#define CAN_IE_MRAFE_Msk (_U_(0x1) << CAN_IE_MRAFE_Pos) /**< (CAN_IE) Message RAM Access Failure Interrupt Enable Mask */ -#define CAN_IE_MRAFE(value) (CAN_IE_MRAFE_Msk & ((value) << CAN_IE_MRAFE_Pos)) -#define CAN_IE_TOOE_Pos _U_(18) /**< (CAN_IE) Timeout Occurred Interrupt Enable Position */ -#define CAN_IE_TOOE_Msk (_U_(0x1) << CAN_IE_TOOE_Pos) /**< (CAN_IE) Timeout Occurred Interrupt Enable Mask */ -#define CAN_IE_TOOE(value) (CAN_IE_TOOE_Msk & ((value) << CAN_IE_TOOE_Pos)) -#define CAN_IE_DRXE_Pos _U_(19) /**< (CAN_IE) Message stored to Dedicated Rx Buffer Interrupt Enable Position */ -#define CAN_IE_DRXE_Msk (_U_(0x1) << CAN_IE_DRXE_Pos) /**< (CAN_IE) Message stored to Dedicated Rx Buffer Interrupt Enable Mask */ -#define CAN_IE_DRXE(value) (CAN_IE_DRXE_Msk & ((value) << CAN_IE_DRXE_Pos)) -#define CAN_IE_BECE_Pos _U_(20) /**< (CAN_IE) Bit Error Corrected Interrupt Enable Position */ -#define CAN_IE_BECE_Msk (_U_(0x1) << CAN_IE_BECE_Pos) /**< (CAN_IE) Bit Error Corrected Interrupt Enable Mask */ -#define CAN_IE_BECE(value) (CAN_IE_BECE_Msk & ((value) << CAN_IE_BECE_Pos)) -#define CAN_IE_BEUE_Pos _U_(21) /**< (CAN_IE) Bit Error Uncorrected Interrupt Enable Position */ -#define CAN_IE_BEUE_Msk (_U_(0x1) << CAN_IE_BEUE_Pos) /**< (CAN_IE) Bit Error Uncorrected Interrupt Enable Mask */ -#define CAN_IE_BEUE(value) (CAN_IE_BEUE_Msk & ((value) << CAN_IE_BEUE_Pos)) -#define CAN_IE_ELOE_Pos _U_(22) /**< (CAN_IE) Error Logging Overflow Interrupt Enable Position */ -#define CAN_IE_ELOE_Msk (_U_(0x1) << CAN_IE_ELOE_Pos) /**< (CAN_IE) Error Logging Overflow Interrupt Enable Mask */ -#define CAN_IE_ELOE(value) (CAN_IE_ELOE_Msk & ((value) << CAN_IE_ELOE_Pos)) -#define CAN_IE_EPE_Pos _U_(23) /**< (CAN_IE) Error Passive Interrupt Enable Position */ -#define CAN_IE_EPE_Msk (_U_(0x1) << CAN_IE_EPE_Pos) /**< (CAN_IE) Error Passive Interrupt Enable Mask */ -#define CAN_IE_EPE(value) (CAN_IE_EPE_Msk & ((value) << CAN_IE_EPE_Pos)) -#define CAN_IE_EWE_Pos _U_(24) /**< (CAN_IE) Warning Status Interrupt Enable Position */ -#define CAN_IE_EWE_Msk (_U_(0x1) << CAN_IE_EWE_Pos) /**< (CAN_IE) Warning Status Interrupt Enable Mask */ -#define CAN_IE_EWE(value) (CAN_IE_EWE_Msk & ((value) << CAN_IE_EWE_Pos)) -#define CAN_IE_BOE_Pos _U_(25) /**< (CAN_IE) Bus_Off Status Interrupt Enable Position */ -#define CAN_IE_BOE_Msk (_U_(0x1) << CAN_IE_BOE_Pos) /**< (CAN_IE) Bus_Off Status Interrupt Enable Mask */ -#define CAN_IE_BOE(value) (CAN_IE_BOE_Msk & ((value) << CAN_IE_BOE_Pos)) -#define CAN_IE_WDIE_Pos _U_(26) /**< (CAN_IE) Watchdog Interrupt Interrupt Enable Position */ -#define CAN_IE_WDIE_Msk (_U_(0x1) << CAN_IE_WDIE_Pos) /**< (CAN_IE) Watchdog Interrupt Interrupt Enable Mask */ -#define CAN_IE_WDIE(value) (CAN_IE_WDIE_Msk & ((value) << CAN_IE_WDIE_Pos)) -#define CAN_IE_PEAE_Pos _U_(27) /**< (CAN_IE) Protocol Error in Arbitration Phase Enable Position */ -#define CAN_IE_PEAE_Msk (_U_(0x1) << CAN_IE_PEAE_Pos) /**< (CAN_IE) Protocol Error in Arbitration Phase Enable Mask */ -#define CAN_IE_PEAE(value) (CAN_IE_PEAE_Msk & ((value) << CAN_IE_PEAE_Pos)) -#define CAN_IE_PEDE_Pos _U_(28) /**< (CAN_IE) Protocol Error in Data Phase Enable Position */ -#define CAN_IE_PEDE_Msk (_U_(0x1) << CAN_IE_PEDE_Pos) /**< (CAN_IE) Protocol Error in Data Phase Enable Mask */ -#define CAN_IE_PEDE(value) (CAN_IE_PEDE_Msk & ((value) << CAN_IE_PEDE_Pos)) -#define CAN_IE_ARAE_Pos _U_(29) /**< (CAN_IE) Access to Reserved Address Enable Position */ -#define CAN_IE_ARAE_Msk (_U_(0x1) << CAN_IE_ARAE_Pos) /**< (CAN_IE) Access to Reserved Address Enable Mask */ -#define CAN_IE_ARAE(value) (CAN_IE_ARAE_Msk & ((value) << CAN_IE_ARAE_Pos)) -#define CAN_IE_Msk _U_(0x3FFFFFFF) /**< (CAN_IE) Register Mask */ - - -/* -------- CAN_ILS : (CAN Offset: 0x58) (R/W 32) Interrupt Line Select -------- */ -#define CAN_ILS_RESETVALUE _U_(0x00) /**< (CAN_ILS) Interrupt Line Select Reset Value */ - -#define CAN_ILS_RF0NL_Pos _U_(0) /**< (CAN_ILS) Rx FIFO 0 New Message Interrupt Line Position */ -#define CAN_ILS_RF0NL_Msk (_U_(0x1) << CAN_ILS_RF0NL_Pos) /**< (CAN_ILS) Rx FIFO 0 New Message Interrupt Line Mask */ -#define CAN_ILS_RF0NL(value) (CAN_ILS_RF0NL_Msk & ((value) << CAN_ILS_RF0NL_Pos)) -#define CAN_ILS_RF0WL_Pos _U_(1) /**< (CAN_ILS) Rx FIFO 0 Watermark Reached Interrupt Line Position */ -#define CAN_ILS_RF0WL_Msk (_U_(0x1) << CAN_ILS_RF0WL_Pos) /**< (CAN_ILS) Rx FIFO 0 Watermark Reached Interrupt Line Mask */ -#define CAN_ILS_RF0WL(value) (CAN_ILS_RF0WL_Msk & ((value) << CAN_ILS_RF0WL_Pos)) -#define CAN_ILS_RF0FL_Pos _U_(2) /**< (CAN_ILS) Rx FIFO 0 Full Interrupt Line Position */ -#define CAN_ILS_RF0FL_Msk (_U_(0x1) << CAN_ILS_RF0FL_Pos) /**< (CAN_ILS) Rx FIFO 0 Full Interrupt Line Mask */ -#define CAN_ILS_RF0FL(value) (CAN_ILS_RF0FL_Msk & ((value) << CAN_ILS_RF0FL_Pos)) -#define CAN_ILS_RF0LL_Pos _U_(3) /**< (CAN_ILS) Rx FIFO 0 Message Lost Interrupt Line Position */ -#define CAN_ILS_RF0LL_Msk (_U_(0x1) << CAN_ILS_RF0LL_Pos) /**< (CAN_ILS) Rx FIFO 0 Message Lost Interrupt Line Mask */ -#define CAN_ILS_RF0LL(value) (CAN_ILS_RF0LL_Msk & ((value) << CAN_ILS_RF0LL_Pos)) -#define CAN_ILS_RF1NL_Pos _U_(4) /**< (CAN_ILS) Rx FIFO 1 New Message Interrupt Line Position */ -#define CAN_ILS_RF1NL_Msk (_U_(0x1) << CAN_ILS_RF1NL_Pos) /**< (CAN_ILS) Rx FIFO 1 New Message Interrupt Line Mask */ -#define CAN_ILS_RF1NL(value) (CAN_ILS_RF1NL_Msk & ((value) << CAN_ILS_RF1NL_Pos)) -#define CAN_ILS_RF1WL_Pos _U_(5) /**< (CAN_ILS) Rx FIFO 1 Watermark Reached Interrupt Line Position */ -#define CAN_ILS_RF1WL_Msk (_U_(0x1) << CAN_ILS_RF1WL_Pos) /**< (CAN_ILS) Rx FIFO 1 Watermark Reached Interrupt Line Mask */ -#define CAN_ILS_RF1WL(value) (CAN_ILS_RF1WL_Msk & ((value) << CAN_ILS_RF1WL_Pos)) -#define CAN_ILS_RF1FL_Pos _U_(6) /**< (CAN_ILS) Rx FIFO 1 FIFO Full Interrupt Line Position */ -#define CAN_ILS_RF1FL_Msk (_U_(0x1) << CAN_ILS_RF1FL_Pos) /**< (CAN_ILS) Rx FIFO 1 FIFO Full Interrupt Line Mask */ -#define CAN_ILS_RF1FL(value) (CAN_ILS_RF1FL_Msk & ((value) << CAN_ILS_RF1FL_Pos)) -#define CAN_ILS_RF1LL_Pos _U_(7) /**< (CAN_ILS) Rx FIFO 1 Message Lost Interrupt Line Position */ -#define CAN_ILS_RF1LL_Msk (_U_(0x1) << CAN_ILS_RF1LL_Pos) /**< (CAN_ILS) Rx FIFO 1 Message Lost Interrupt Line Mask */ -#define CAN_ILS_RF1LL(value) (CAN_ILS_RF1LL_Msk & ((value) << CAN_ILS_RF1LL_Pos)) -#define CAN_ILS_HPML_Pos _U_(8) /**< (CAN_ILS) High Priority Message Interrupt Line Position */ -#define CAN_ILS_HPML_Msk (_U_(0x1) << CAN_ILS_HPML_Pos) /**< (CAN_ILS) High Priority Message Interrupt Line Mask */ -#define CAN_ILS_HPML(value) (CAN_ILS_HPML_Msk & ((value) << CAN_ILS_HPML_Pos)) -#define CAN_ILS_TCL_Pos _U_(9) /**< (CAN_ILS) Timestamp Completed Interrupt Line Position */ -#define CAN_ILS_TCL_Msk (_U_(0x1) << CAN_ILS_TCL_Pos) /**< (CAN_ILS) Timestamp Completed Interrupt Line Mask */ -#define CAN_ILS_TCL(value) (CAN_ILS_TCL_Msk & ((value) << CAN_ILS_TCL_Pos)) -#define CAN_ILS_TCFL_Pos _U_(10) /**< (CAN_ILS) Transmission Cancellation Finished Interrupt Line Position */ -#define CAN_ILS_TCFL_Msk (_U_(0x1) << CAN_ILS_TCFL_Pos) /**< (CAN_ILS) Transmission Cancellation Finished Interrupt Line Mask */ -#define CAN_ILS_TCFL(value) (CAN_ILS_TCFL_Msk & ((value) << CAN_ILS_TCFL_Pos)) -#define CAN_ILS_TFEL_Pos _U_(11) /**< (CAN_ILS) Tx FIFO Empty Interrupt Line Position */ -#define CAN_ILS_TFEL_Msk (_U_(0x1) << CAN_ILS_TFEL_Pos) /**< (CAN_ILS) Tx FIFO Empty Interrupt Line Mask */ -#define CAN_ILS_TFEL(value) (CAN_ILS_TFEL_Msk & ((value) << CAN_ILS_TFEL_Pos)) -#define CAN_ILS_TEFNL_Pos _U_(12) /**< (CAN_ILS) Tx Event FIFO New Entry Interrupt Line Position */ -#define CAN_ILS_TEFNL_Msk (_U_(0x1) << CAN_ILS_TEFNL_Pos) /**< (CAN_ILS) Tx Event FIFO New Entry Interrupt Line Mask */ -#define CAN_ILS_TEFNL(value) (CAN_ILS_TEFNL_Msk & ((value) << CAN_ILS_TEFNL_Pos)) -#define CAN_ILS_TEFWL_Pos _U_(13) /**< (CAN_ILS) Tx Event FIFO Watermark Reached Interrupt Line Position */ -#define CAN_ILS_TEFWL_Msk (_U_(0x1) << CAN_ILS_TEFWL_Pos) /**< (CAN_ILS) Tx Event FIFO Watermark Reached Interrupt Line Mask */ -#define CAN_ILS_TEFWL(value) (CAN_ILS_TEFWL_Msk & ((value) << CAN_ILS_TEFWL_Pos)) -#define CAN_ILS_TEFFL_Pos _U_(14) /**< (CAN_ILS) Tx Event FIFO Full Interrupt Line Position */ -#define CAN_ILS_TEFFL_Msk (_U_(0x1) << CAN_ILS_TEFFL_Pos) /**< (CAN_ILS) Tx Event FIFO Full Interrupt Line Mask */ -#define CAN_ILS_TEFFL(value) (CAN_ILS_TEFFL_Msk & ((value) << CAN_ILS_TEFFL_Pos)) -#define CAN_ILS_TEFLL_Pos _U_(15) /**< (CAN_ILS) Tx Event FIFO Element Lost Interrupt Line Position */ -#define CAN_ILS_TEFLL_Msk (_U_(0x1) << CAN_ILS_TEFLL_Pos) /**< (CAN_ILS) Tx Event FIFO Element Lost Interrupt Line Mask */ -#define CAN_ILS_TEFLL(value) (CAN_ILS_TEFLL_Msk & ((value) << CAN_ILS_TEFLL_Pos)) -#define CAN_ILS_TSWL_Pos _U_(16) /**< (CAN_ILS) Timestamp Wraparound Interrupt Line Position */ -#define CAN_ILS_TSWL_Msk (_U_(0x1) << CAN_ILS_TSWL_Pos) /**< (CAN_ILS) Timestamp Wraparound Interrupt Line Mask */ -#define CAN_ILS_TSWL(value) (CAN_ILS_TSWL_Msk & ((value) << CAN_ILS_TSWL_Pos)) -#define CAN_ILS_MRAFL_Pos _U_(17) /**< (CAN_ILS) Message RAM Access Failure Interrupt Line Position */ -#define CAN_ILS_MRAFL_Msk (_U_(0x1) << CAN_ILS_MRAFL_Pos) /**< (CAN_ILS) Message RAM Access Failure Interrupt Line Mask */ -#define CAN_ILS_MRAFL(value) (CAN_ILS_MRAFL_Msk & ((value) << CAN_ILS_MRAFL_Pos)) -#define CAN_ILS_TOOL_Pos _U_(18) /**< (CAN_ILS) Timeout Occurred Interrupt Line Position */ -#define CAN_ILS_TOOL_Msk (_U_(0x1) << CAN_ILS_TOOL_Pos) /**< (CAN_ILS) Timeout Occurred Interrupt Line Mask */ -#define CAN_ILS_TOOL(value) (CAN_ILS_TOOL_Msk & ((value) << CAN_ILS_TOOL_Pos)) -#define CAN_ILS_DRXL_Pos _U_(19) /**< (CAN_ILS) Message stored to Dedicated Rx Buffer Interrupt Line Position */ -#define CAN_ILS_DRXL_Msk (_U_(0x1) << CAN_ILS_DRXL_Pos) /**< (CAN_ILS) Message stored to Dedicated Rx Buffer Interrupt Line Mask */ -#define CAN_ILS_DRXL(value) (CAN_ILS_DRXL_Msk & ((value) << CAN_ILS_DRXL_Pos)) -#define CAN_ILS_BECL_Pos _U_(20) /**< (CAN_ILS) Bit Error Corrected Interrupt Line Position */ -#define CAN_ILS_BECL_Msk (_U_(0x1) << CAN_ILS_BECL_Pos) /**< (CAN_ILS) Bit Error Corrected Interrupt Line Mask */ -#define CAN_ILS_BECL(value) (CAN_ILS_BECL_Msk & ((value) << CAN_ILS_BECL_Pos)) -#define CAN_ILS_BEUL_Pos _U_(21) /**< (CAN_ILS) Bit Error Uncorrected Interrupt Line Position */ -#define CAN_ILS_BEUL_Msk (_U_(0x1) << CAN_ILS_BEUL_Pos) /**< (CAN_ILS) Bit Error Uncorrected Interrupt Line Mask */ -#define CAN_ILS_BEUL(value) (CAN_ILS_BEUL_Msk & ((value) << CAN_ILS_BEUL_Pos)) -#define CAN_ILS_ELOL_Pos _U_(22) /**< (CAN_ILS) Error Logging Overflow Interrupt Line Position */ -#define CAN_ILS_ELOL_Msk (_U_(0x1) << CAN_ILS_ELOL_Pos) /**< (CAN_ILS) Error Logging Overflow Interrupt Line Mask */ -#define CAN_ILS_ELOL(value) (CAN_ILS_ELOL_Msk & ((value) << CAN_ILS_ELOL_Pos)) -#define CAN_ILS_EPL_Pos _U_(23) /**< (CAN_ILS) Error Passive Interrupt Line Position */ -#define CAN_ILS_EPL_Msk (_U_(0x1) << CAN_ILS_EPL_Pos) /**< (CAN_ILS) Error Passive Interrupt Line Mask */ -#define CAN_ILS_EPL(value) (CAN_ILS_EPL_Msk & ((value) << CAN_ILS_EPL_Pos)) -#define CAN_ILS_EWL_Pos _U_(24) /**< (CAN_ILS) Warning Status Interrupt Line Position */ -#define CAN_ILS_EWL_Msk (_U_(0x1) << CAN_ILS_EWL_Pos) /**< (CAN_ILS) Warning Status Interrupt Line Mask */ -#define CAN_ILS_EWL(value) (CAN_ILS_EWL_Msk & ((value) << CAN_ILS_EWL_Pos)) -#define CAN_ILS_BOL_Pos _U_(25) /**< (CAN_ILS) Bus_Off Status Interrupt Line Position */ -#define CAN_ILS_BOL_Msk (_U_(0x1) << CAN_ILS_BOL_Pos) /**< (CAN_ILS) Bus_Off Status Interrupt Line Mask */ -#define CAN_ILS_BOL(value) (CAN_ILS_BOL_Msk & ((value) << CAN_ILS_BOL_Pos)) -#define CAN_ILS_WDIL_Pos _U_(26) /**< (CAN_ILS) Watchdog Interrupt Interrupt Line Position */ -#define CAN_ILS_WDIL_Msk (_U_(0x1) << CAN_ILS_WDIL_Pos) /**< (CAN_ILS) Watchdog Interrupt Interrupt Line Mask */ -#define CAN_ILS_WDIL(value) (CAN_ILS_WDIL_Msk & ((value) << CAN_ILS_WDIL_Pos)) -#define CAN_ILS_PEAL_Pos _U_(27) /**< (CAN_ILS) Protocol Error in Arbitration Phase Line Position */ -#define CAN_ILS_PEAL_Msk (_U_(0x1) << CAN_ILS_PEAL_Pos) /**< (CAN_ILS) Protocol Error in Arbitration Phase Line Mask */ -#define CAN_ILS_PEAL(value) (CAN_ILS_PEAL_Msk & ((value) << CAN_ILS_PEAL_Pos)) -#define CAN_ILS_PEDL_Pos _U_(28) /**< (CAN_ILS) Protocol Error in Data Phase Line Position */ -#define CAN_ILS_PEDL_Msk (_U_(0x1) << CAN_ILS_PEDL_Pos) /**< (CAN_ILS) Protocol Error in Data Phase Line Mask */ -#define CAN_ILS_PEDL(value) (CAN_ILS_PEDL_Msk & ((value) << CAN_ILS_PEDL_Pos)) -#define CAN_ILS_ARAL_Pos _U_(29) /**< (CAN_ILS) Access to Reserved Address Line Position */ -#define CAN_ILS_ARAL_Msk (_U_(0x1) << CAN_ILS_ARAL_Pos) /**< (CAN_ILS) Access to Reserved Address Line Mask */ -#define CAN_ILS_ARAL(value) (CAN_ILS_ARAL_Msk & ((value) << CAN_ILS_ARAL_Pos)) -#define CAN_ILS_Msk _U_(0x3FFFFFFF) /**< (CAN_ILS) Register Mask */ - - -/* -------- CAN_ILE : (CAN Offset: 0x5C) (R/W 32) Interrupt Line Enable -------- */ -#define CAN_ILE_RESETVALUE _U_(0x00) /**< (CAN_ILE) Interrupt Line Enable Reset Value */ - -#define CAN_ILE_EINT0_Pos _U_(0) /**< (CAN_ILE) Enable Interrupt Line 0 Position */ -#define CAN_ILE_EINT0_Msk (_U_(0x1) << CAN_ILE_EINT0_Pos) /**< (CAN_ILE) Enable Interrupt Line 0 Mask */ -#define CAN_ILE_EINT0(value) (CAN_ILE_EINT0_Msk & ((value) << CAN_ILE_EINT0_Pos)) -#define CAN_ILE_EINT1_Pos _U_(1) /**< (CAN_ILE) Enable Interrupt Line 1 Position */ -#define CAN_ILE_EINT1_Msk (_U_(0x1) << CAN_ILE_EINT1_Pos) /**< (CAN_ILE) Enable Interrupt Line 1 Mask */ -#define CAN_ILE_EINT1(value) (CAN_ILE_EINT1_Msk & ((value) << CAN_ILE_EINT1_Pos)) -#define CAN_ILE_Msk _U_(0x00000003) /**< (CAN_ILE) Register Mask */ - -#define CAN_ILE_EINT_Pos _U_(0) /**< (CAN_ILE Position) Enable Interrupt Line x */ -#define CAN_ILE_EINT_Msk (_U_(0x3) << CAN_ILE_EINT_Pos) /**< (CAN_ILE Mask) EINT */ -#define CAN_ILE_EINT(value) (CAN_ILE_EINT_Msk & ((value) << CAN_ILE_EINT_Pos)) - -/* -------- CAN_GFC : (CAN Offset: 0x80) (R/W 32) Global Filter Configuration -------- */ -#define CAN_GFC_RESETVALUE _U_(0x00) /**< (CAN_GFC) Global Filter Configuration Reset Value */ - -#define CAN_GFC_RRFE_Pos _U_(0) /**< (CAN_GFC) Reject Remote Frames Extended Position */ -#define CAN_GFC_RRFE_Msk (_U_(0x1) << CAN_GFC_RRFE_Pos) /**< (CAN_GFC) Reject Remote Frames Extended Mask */ -#define CAN_GFC_RRFE(value) (CAN_GFC_RRFE_Msk & ((value) << CAN_GFC_RRFE_Pos)) -#define CAN_GFC_RRFS_Pos _U_(1) /**< (CAN_GFC) Reject Remote Frames Standard Position */ -#define CAN_GFC_RRFS_Msk (_U_(0x1) << CAN_GFC_RRFS_Pos) /**< (CAN_GFC) Reject Remote Frames Standard Mask */ -#define CAN_GFC_RRFS(value) (CAN_GFC_RRFS_Msk & ((value) << CAN_GFC_RRFS_Pos)) -#define CAN_GFC_ANFE_Pos _U_(2) /**< (CAN_GFC) Accept Non-matching Frames Extended Position */ -#define CAN_GFC_ANFE_Msk (_U_(0x3) << CAN_GFC_ANFE_Pos) /**< (CAN_GFC) Accept Non-matching Frames Extended Mask */ -#define CAN_GFC_ANFE(value) (CAN_GFC_ANFE_Msk & ((value) << CAN_GFC_ANFE_Pos)) -#define CAN_GFC_ANFE_RXF0_Val _U_(0x0) /**< (CAN_GFC) Accept in Rx FIFO 0 */ -#define CAN_GFC_ANFE_RXF1_Val _U_(0x1) /**< (CAN_GFC) Accept in Rx FIFO 1 */ -#define CAN_GFC_ANFE_REJECT_Val _U_(0x2) /**< (CAN_GFC) Reject */ -#define CAN_GFC_ANFE_RXF0 (CAN_GFC_ANFE_RXF0_Val << CAN_GFC_ANFE_Pos) /**< (CAN_GFC) Accept in Rx FIFO 0 Position */ -#define CAN_GFC_ANFE_RXF1 (CAN_GFC_ANFE_RXF1_Val << CAN_GFC_ANFE_Pos) /**< (CAN_GFC) Accept in Rx FIFO 1 Position */ -#define CAN_GFC_ANFE_REJECT (CAN_GFC_ANFE_REJECT_Val << CAN_GFC_ANFE_Pos) /**< (CAN_GFC) Reject Position */ -#define CAN_GFC_ANFS_Pos _U_(4) /**< (CAN_GFC) Accept Non-matching Frames Standard Position */ -#define CAN_GFC_ANFS_Msk (_U_(0x3) << CAN_GFC_ANFS_Pos) /**< (CAN_GFC) Accept Non-matching Frames Standard Mask */ -#define CAN_GFC_ANFS(value) (CAN_GFC_ANFS_Msk & ((value) << CAN_GFC_ANFS_Pos)) -#define CAN_GFC_ANFS_RXF0_Val _U_(0x0) /**< (CAN_GFC) Accept in Rx FIFO 0 */ -#define CAN_GFC_ANFS_RXF1_Val _U_(0x1) /**< (CAN_GFC) Accept in Rx FIFO 1 */ -#define CAN_GFC_ANFS_REJECT_Val _U_(0x2) /**< (CAN_GFC) Reject */ -#define CAN_GFC_ANFS_RXF0 (CAN_GFC_ANFS_RXF0_Val << CAN_GFC_ANFS_Pos) /**< (CAN_GFC) Accept in Rx FIFO 0 Position */ -#define CAN_GFC_ANFS_RXF1 (CAN_GFC_ANFS_RXF1_Val << CAN_GFC_ANFS_Pos) /**< (CAN_GFC) Accept in Rx FIFO 1 Position */ -#define CAN_GFC_ANFS_REJECT (CAN_GFC_ANFS_REJECT_Val << CAN_GFC_ANFS_Pos) /**< (CAN_GFC) Reject Position */ -#define CAN_GFC_Msk _U_(0x0000003F) /**< (CAN_GFC) Register Mask */ - - -/* -------- CAN_SIDFC : (CAN Offset: 0x84) (R/W 32) Standard ID Filter Configuration -------- */ -#define CAN_SIDFC_RESETVALUE _U_(0x00) /**< (CAN_SIDFC) Standard ID Filter Configuration Reset Value */ - -#define CAN_SIDFC_FLSSA_Pos _U_(0) /**< (CAN_SIDFC) Filter List Standard Start Address Position */ -#define CAN_SIDFC_FLSSA_Msk (_U_(0xFFFF) << CAN_SIDFC_FLSSA_Pos) /**< (CAN_SIDFC) Filter List Standard Start Address Mask */ -#define CAN_SIDFC_FLSSA(value) (CAN_SIDFC_FLSSA_Msk & ((value) << CAN_SIDFC_FLSSA_Pos)) -#define CAN_SIDFC_LSS_Pos _U_(16) /**< (CAN_SIDFC) List Size Standard Position */ -#define CAN_SIDFC_LSS_Msk (_U_(0xFF) << CAN_SIDFC_LSS_Pos) /**< (CAN_SIDFC) List Size Standard Mask */ -#define CAN_SIDFC_LSS(value) (CAN_SIDFC_LSS_Msk & ((value) << CAN_SIDFC_LSS_Pos)) -#define CAN_SIDFC_Msk _U_(0x00FFFFFF) /**< (CAN_SIDFC) Register Mask */ - - -/* -------- CAN_XIDFC : (CAN Offset: 0x88) (R/W 32) Extended ID Filter Configuration -------- */ -#define CAN_XIDFC_RESETVALUE _U_(0x00) /**< (CAN_XIDFC) Extended ID Filter Configuration Reset Value */ - -#define CAN_XIDFC_FLESA_Pos _U_(0) /**< (CAN_XIDFC) Filter List Extended Start Address Position */ -#define CAN_XIDFC_FLESA_Msk (_U_(0xFFFF) << CAN_XIDFC_FLESA_Pos) /**< (CAN_XIDFC) Filter List Extended Start Address Mask */ -#define CAN_XIDFC_FLESA(value) (CAN_XIDFC_FLESA_Msk & ((value) << CAN_XIDFC_FLESA_Pos)) -#define CAN_XIDFC_LSE_Pos _U_(16) /**< (CAN_XIDFC) List Size Extended Position */ -#define CAN_XIDFC_LSE_Msk (_U_(0x7F) << CAN_XIDFC_LSE_Pos) /**< (CAN_XIDFC) List Size Extended Mask */ -#define CAN_XIDFC_LSE(value) (CAN_XIDFC_LSE_Msk & ((value) << CAN_XIDFC_LSE_Pos)) -#define CAN_XIDFC_Msk _U_(0x007FFFFF) /**< (CAN_XIDFC) Register Mask */ - - -/* -------- CAN_XIDAM : (CAN Offset: 0x90) (R/W 32) Extended ID AND Mask -------- */ -#define CAN_XIDAM_RESETVALUE _U_(0x1FFFFFFF) /**< (CAN_XIDAM) Extended ID AND Mask Reset Value */ - -#define CAN_XIDAM_EIDM_Pos _U_(0) /**< (CAN_XIDAM) Extended ID Mask Position */ -#define CAN_XIDAM_EIDM_Msk (_U_(0x1FFFFFFF) << CAN_XIDAM_EIDM_Pos) /**< (CAN_XIDAM) Extended ID Mask Mask */ -#define CAN_XIDAM_EIDM(value) (CAN_XIDAM_EIDM_Msk & ((value) << CAN_XIDAM_EIDM_Pos)) -#define CAN_XIDAM_Msk _U_(0x1FFFFFFF) /**< (CAN_XIDAM) Register Mask */ - - -/* -------- CAN_HPMS : (CAN Offset: 0x94) ( R/ 32) High Priority Message Status -------- */ -#define CAN_HPMS_RESETVALUE _U_(0x00) /**< (CAN_HPMS) High Priority Message Status Reset Value */ - -#define CAN_HPMS_BIDX_Pos _U_(0) /**< (CAN_HPMS) Buffer Index Position */ -#define CAN_HPMS_BIDX_Msk (_U_(0x3F) << CAN_HPMS_BIDX_Pos) /**< (CAN_HPMS) Buffer Index Mask */ -#define CAN_HPMS_BIDX(value) (CAN_HPMS_BIDX_Msk & ((value) << CAN_HPMS_BIDX_Pos)) -#define CAN_HPMS_MSI_Pos _U_(6) /**< (CAN_HPMS) Message Storage Indicator Position */ -#define CAN_HPMS_MSI_Msk (_U_(0x3) << CAN_HPMS_MSI_Pos) /**< (CAN_HPMS) Message Storage Indicator Mask */ -#define CAN_HPMS_MSI(value) (CAN_HPMS_MSI_Msk & ((value) << CAN_HPMS_MSI_Pos)) -#define CAN_HPMS_MSI_NONE_Val _U_(0x0) /**< (CAN_HPMS) No FIFO selected */ -#define CAN_HPMS_MSI_LOST_Val _U_(0x1) /**< (CAN_HPMS) FIFO message lost */ -#define CAN_HPMS_MSI_FIFO0_Val _U_(0x2) /**< (CAN_HPMS) Message stored in FIFO 0 */ -#define CAN_HPMS_MSI_FIFO1_Val _U_(0x3) /**< (CAN_HPMS) Message stored in FIFO 1 */ -#define CAN_HPMS_MSI_NONE (CAN_HPMS_MSI_NONE_Val << CAN_HPMS_MSI_Pos) /**< (CAN_HPMS) No FIFO selected Position */ -#define CAN_HPMS_MSI_LOST (CAN_HPMS_MSI_LOST_Val << CAN_HPMS_MSI_Pos) /**< (CAN_HPMS) FIFO message lost Position */ -#define CAN_HPMS_MSI_FIFO0 (CAN_HPMS_MSI_FIFO0_Val << CAN_HPMS_MSI_Pos) /**< (CAN_HPMS) Message stored in FIFO 0 Position */ -#define CAN_HPMS_MSI_FIFO1 (CAN_HPMS_MSI_FIFO1_Val << CAN_HPMS_MSI_Pos) /**< (CAN_HPMS) Message stored in FIFO 1 Position */ -#define CAN_HPMS_FIDX_Pos _U_(8) /**< (CAN_HPMS) Filter Index Position */ -#define CAN_HPMS_FIDX_Msk (_U_(0x7F) << CAN_HPMS_FIDX_Pos) /**< (CAN_HPMS) Filter Index Mask */ -#define CAN_HPMS_FIDX(value) (CAN_HPMS_FIDX_Msk & ((value) << CAN_HPMS_FIDX_Pos)) -#define CAN_HPMS_FLST_Pos _U_(15) /**< (CAN_HPMS) Filter List Position */ -#define CAN_HPMS_FLST_Msk (_U_(0x1) << CAN_HPMS_FLST_Pos) /**< (CAN_HPMS) Filter List Mask */ -#define CAN_HPMS_FLST(value) (CAN_HPMS_FLST_Msk & ((value) << CAN_HPMS_FLST_Pos)) -#define CAN_HPMS_Msk _U_(0x0000FFFF) /**< (CAN_HPMS) Register Mask */ - - -/* -------- CAN_NDAT1 : (CAN Offset: 0x98) (R/W 32) New Data 1 -------- */ -#define CAN_NDAT1_RESETVALUE _U_(0x00) /**< (CAN_NDAT1) New Data 1 Reset Value */ - -#define CAN_NDAT1_ND0_Pos _U_(0) /**< (CAN_NDAT1) New Data 0 Position */ -#define CAN_NDAT1_ND0_Msk (_U_(0x1) << CAN_NDAT1_ND0_Pos) /**< (CAN_NDAT1) New Data 0 Mask */ -#define CAN_NDAT1_ND0(value) (CAN_NDAT1_ND0_Msk & ((value) << CAN_NDAT1_ND0_Pos)) -#define CAN_NDAT1_ND1_Pos _U_(1) /**< (CAN_NDAT1) New Data 1 Position */ -#define CAN_NDAT1_ND1_Msk (_U_(0x1) << CAN_NDAT1_ND1_Pos) /**< (CAN_NDAT1) New Data 1 Mask */ -#define CAN_NDAT1_ND1(value) (CAN_NDAT1_ND1_Msk & ((value) << CAN_NDAT1_ND1_Pos)) -#define CAN_NDAT1_ND2_Pos _U_(2) /**< (CAN_NDAT1) New Data 2 Position */ -#define CAN_NDAT1_ND2_Msk (_U_(0x1) << CAN_NDAT1_ND2_Pos) /**< (CAN_NDAT1) New Data 2 Mask */ -#define CAN_NDAT1_ND2(value) (CAN_NDAT1_ND2_Msk & ((value) << CAN_NDAT1_ND2_Pos)) -#define CAN_NDAT1_ND3_Pos _U_(3) /**< (CAN_NDAT1) New Data 3 Position */ -#define CAN_NDAT1_ND3_Msk (_U_(0x1) << CAN_NDAT1_ND3_Pos) /**< (CAN_NDAT1) New Data 3 Mask */ -#define CAN_NDAT1_ND3(value) (CAN_NDAT1_ND3_Msk & ((value) << CAN_NDAT1_ND3_Pos)) -#define CAN_NDAT1_ND4_Pos _U_(4) /**< (CAN_NDAT1) New Data 4 Position */ -#define CAN_NDAT1_ND4_Msk (_U_(0x1) << CAN_NDAT1_ND4_Pos) /**< (CAN_NDAT1) New Data 4 Mask */ -#define CAN_NDAT1_ND4(value) (CAN_NDAT1_ND4_Msk & ((value) << CAN_NDAT1_ND4_Pos)) -#define CAN_NDAT1_ND5_Pos _U_(5) /**< (CAN_NDAT1) New Data 5 Position */ -#define CAN_NDAT1_ND5_Msk (_U_(0x1) << CAN_NDAT1_ND5_Pos) /**< (CAN_NDAT1) New Data 5 Mask */ -#define CAN_NDAT1_ND5(value) (CAN_NDAT1_ND5_Msk & ((value) << CAN_NDAT1_ND5_Pos)) -#define CAN_NDAT1_ND6_Pos _U_(6) /**< (CAN_NDAT1) New Data 6 Position */ -#define CAN_NDAT1_ND6_Msk (_U_(0x1) << CAN_NDAT1_ND6_Pos) /**< (CAN_NDAT1) New Data 6 Mask */ -#define CAN_NDAT1_ND6(value) (CAN_NDAT1_ND6_Msk & ((value) << CAN_NDAT1_ND6_Pos)) -#define CAN_NDAT1_ND7_Pos _U_(7) /**< (CAN_NDAT1) New Data 7 Position */ -#define CAN_NDAT1_ND7_Msk (_U_(0x1) << CAN_NDAT1_ND7_Pos) /**< (CAN_NDAT1) New Data 7 Mask */ -#define CAN_NDAT1_ND7(value) (CAN_NDAT1_ND7_Msk & ((value) << CAN_NDAT1_ND7_Pos)) -#define CAN_NDAT1_ND8_Pos _U_(8) /**< (CAN_NDAT1) New Data 8 Position */ -#define CAN_NDAT1_ND8_Msk (_U_(0x1) << CAN_NDAT1_ND8_Pos) /**< (CAN_NDAT1) New Data 8 Mask */ -#define CAN_NDAT1_ND8(value) (CAN_NDAT1_ND8_Msk & ((value) << CAN_NDAT1_ND8_Pos)) -#define CAN_NDAT1_ND9_Pos _U_(9) /**< (CAN_NDAT1) New Data 9 Position */ -#define CAN_NDAT1_ND9_Msk (_U_(0x1) << CAN_NDAT1_ND9_Pos) /**< (CAN_NDAT1) New Data 9 Mask */ -#define CAN_NDAT1_ND9(value) (CAN_NDAT1_ND9_Msk & ((value) << CAN_NDAT1_ND9_Pos)) -#define CAN_NDAT1_ND10_Pos _U_(10) /**< (CAN_NDAT1) New Data 10 Position */ -#define CAN_NDAT1_ND10_Msk (_U_(0x1) << CAN_NDAT1_ND10_Pos) /**< (CAN_NDAT1) New Data 10 Mask */ -#define CAN_NDAT1_ND10(value) (CAN_NDAT1_ND10_Msk & ((value) << CAN_NDAT1_ND10_Pos)) -#define CAN_NDAT1_ND11_Pos _U_(11) /**< (CAN_NDAT1) New Data 11 Position */ -#define CAN_NDAT1_ND11_Msk (_U_(0x1) << CAN_NDAT1_ND11_Pos) /**< (CAN_NDAT1) New Data 11 Mask */ -#define CAN_NDAT1_ND11(value) (CAN_NDAT1_ND11_Msk & ((value) << CAN_NDAT1_ND11_Pos)) -#define CAN_NDAT1_ND12_Pos _U_(12) /**< (CAN_NDAT1) New Data 12 Position */ -#define CAN_NDAT1_ND12_Msk (_U_(0x1) << CAN_NDAT1_ND12_Pos) /**< (CAN_NDAT1) New Data 12 Mask */ -#define CAN_NDAT1_ND12(value) (CAN_NDAT1_ND12_Msk & ((value) << CAN_NDAT1_ND12_Pos)) -#define CAN_NDAT1_ND13_Pos _U_(13) /**< (CAN_NDAT1) New Data 13 Position */ -#define CAN_NDAT1_ND13_Msk (_U_(0x1) << CAN_NDAT1_ND13_Pos) /**< (CAN_NDAT1) New Data 13 Mask */ -#define CAN_NDAT1_ND13(value) (CAN_NDAT1_ND13_Msk & ((value) << CAN_NDAT1_ND13_Pos)) -#define CAN_NDAT1_ND14_Pos _U_(14) /**< (CAN_NDAT1) New Data 14 Position */ -#define CAN_NDAT1_ND14_Msk (_U_(0x1) << CAN_NDAT1_ND14_Pos) /**< (CAN_NDAT1) New Data 14 Mask */ -#define CAN_NDAT1_ND14(value) (CAN_NDAT1_ND14_Msk & ((value) << CAN_NDAT1_ND14_Pos)) -#define CAN_NDAT1_ND15_Pos _U_(15) /**< (CAN_NDAT1) New Data 15 Position */ -#define CAN_NDAT1_ND15_Msk (_U_(0x1) << CAN_NDAT1_ND15_Pos) /**< (CAN_NDAT1) New Data 15 Mask */ -#define CAN_NDAT1_ND15(value) (CAN_NDAT1_ND15_Msk & ((value) << CAN_NDAT1_ND15_Pos)) -#define CAN_NDAT1_ND16_Pos _U_(16) /**< (CAN_NDAT1) New Data 16 Position */ -#define CAN_NDAT1_ND16_Msk (_U_(0x1) << CAN_NDAT1_ND16_Pos) /**< (CAN_NDAT1) New Data 16 Mask */ -#define CAN_NDAT1_ND16(value) (CAN_NDAT1_ND16_Msk & ((value) << CAN_NDAT1_ND16_Pos)) -#define CAN_NDAT1_ND17_Pos _U_(17) /**< (CAN_NDAT1) New Data 17 Position */ -#define CAN_NDAT1_ND17_Msk (_U_(0x1) << CAN_NDAT1_ND17_Pos) /**< (CAN_NDAT1) New Data 17 Mask */ -#define CAN_NDAT1_ND17(value) (CAN_NDAT1_ND17_Msk & ((value) << CAN_NDAT1_ND17_Pos)) -#define CAN_NDAT1_ND18_Pos _U_(18) /**< (CAN_NDAT1) New Data 18 Position */ -#define CAN_NDAT1_ND18_Msk (_U_(0x1) << CAN_NDAT1_ND18_Pos) /**< (CAN_NDAT1) New Data 18 Mask */ -#define CAN_NDAT1_ND18(value) (CAN_NDAT1_ND18_Msk & ((value) << CAN_NDAT1_ND18_Pos)) -#define CAN_NDAT1_ND19_Pos _U_(19) /**< (CAN_NDAT1) New Data 19 Position */ -#define CAN_NDAT1_ND19_Msk (_U_(0x1) << CAN_NDAT1_ND19_Pos) /**< (CAN_NDAT1) New Data 19 Mask */ -#define CAN_NDAT1_ND19(value) (CAN_NDAT1_ND19_Msk & ((value) << CAN_NDAT1_ND19_Pos)) -#define CAN_NDAT1_ND20_Pos _U_(20) /**< (CAN_NDAT1) New Data 20 Position */ -#define CAN_NDAT1_ND20_Msk (_U_(0x1) << CAN_NDAT1_ND20_Pos) /**< (CAN_NDAT1) New Data 20 Mask */ -#define CAN_NDAT1_ND20(value) (CAN_NDAT1_ND20_Msk & ((value) << CAN_NDAT1_ND20_Pos)) -#define CAN_NDAT1_ND21_Pos _U_(21) /**< (CAN_NDAT1) New Data 21 Position */ -#define CAN_NDAT1_ND21_Msk (_U_(0x1) << CAN_NDAT1_ND21_Pos) /**< (CAN_NDAT1) New Data 21 Mask */ -#define CAN_NDAT1_ND21(value) (CAN_NDAT1_ND21_Msk & ((value) << CAN_NDAT1_ND21_Pos)) -#define CAN_NDAT1_ND22_Pos _U_(22) /**< (CAN_NDAT1) New Data 22 Position */ -#define CAN_NDAT1_ND22_Msk (_U_(0x1) << CAN_NDAT1_ND22_Pos) /**< (CAN_NDAT1) New Data 22 Mask */ -#define CAN_NDAT1_ND22(value) (CAN_NDAT1_ND22_Msk & ((value) << CAN_NDAT1_ND22_Pos)) -#define CAN_NDAT1_ND23_Pos _U_(23) /**< (CAN_NDAT1) New Data 23 Position */ -#define CAN_NDAT1_ND23_Msk (_U_(0x1) << CAN_NDAT1_ND23_Pos) /**< (CAN_NDAT1) New Data 23 Mask */ -#define CAN_NDAT1_ND23(value) (CAN_NDAT1_ND23_Msk & ((value) << CAN_NDAT1_ND23_Pos)) -#define CAN_NDAT1_ND24_Pos _U_(24) /**< (CAN_NDAT1) New Data 24 Position */ -#define CAN_NDAT1_ND24_Msk (_U_(0x1) << CAN_NDAT1_ND24_Pos) /**< (CAN_NDAT1) New Data 24 Mask */ -#define CAN_NDAT1_ND24(value) (CAN_NDAT1_ND24_Msk & ((value) << CAN_NDAT1_ND24_Pos)) -#define CAN_NDAT1_ND25_Pos _U_(25) /**< (CAN_NDAT1) New Data 25 Position */ -#define CAN_NDAT1_ND25_Msk (_U_(0x1) << CAN_NDAT1_ND25_Pos) /**< (CAN_NDAT1) New Data 25 Mask */ -#define CAN_NDAT1_ND25(value) (CAN_NDAT1_ND25_Msk & ((value) << CAN_NDAT1_ND25_Pos)) -#define CAN_NDAT1_ND26_Pos _U_(26) /**< (CAN_NDAT1) New Data 26 Position */ -#define CAN_NDAT1_ND26_Msk (_U_(0x1) << CAN_NDAT1_ND26_Pos) /**< (CAN_NDAT1) New Data 26 Mask */ -#define CAN_NDAT1_ND26(value) (CAN_NDAT1_ND26_Msk & ((value) << CAN_NDAT1_ND26_Pos)) -#define CAN_NDAT1_ND27_Pos _U_(27) /**< (CAN_NDAT1) New Data 27 Position */ -#define CAN_NDAT1_ND27_Msk (_U_(0x1) << CAN_NDAT1_ND27_Pos) /**< (CAN_NDAT1) New Data 27 Mask */ -#define CAN_NDAT1_ND27(value) (CAN_NDAT1_ND27_Msk & ((value) << CAN_NDAT1_ND27_Pos)) -#define CAN_NDAT1_ND28_Pos _U_(28) /**< (CAN_NDAT1) New Data 28 Position */ -#define CAN_NDAT1_ND28_Msk (_U_(0x1) << CAN_NDAT1_ND28_Pos) /**< (CAN_NDAT1) New Data 28 Mask */ -#define CAN_NDAT1_ND28(value) (CAN_NDAT1_ND28_Msk & ((value) << CAN_NDAT1_ND28_Pos)) -#define CAN_NDAT1_ND29_Pos _U_(29) /**< (CAN_NDAT1) New Data 29 Position */ -#define CAN_NDAT1_ND29_Msk (_U_(0x1) << CAN_NDAT1_ND29_Pos) /**< (CAN_NDAT1) New Data 29 Mask */ -#define CAN_NDAT1_ND29(value) (CAN_NDAT1_ND29_Msk & ((value) << CAN_NDAT1_ND29_Pos)) -#define CAN_NDAT1_ND30_Pos _U_(30) /**< (CAN_NDAT1) New Data 30 Position */ -#define CAN_NDAT1_ND30_Msk (_U_(0x1) << CAN_NDAT1_ND30_Pos) /**< (CAN_NDAT1) New Data 30 Mask */ -#define CAN_NDAT1_ND30(value) (CAN_NDAT1_ND30_Msk & ((value) << CAN_NDAT1_ND30_Pos)) -#define CAN_NDAT1_ND31_Pos _U_(31) /**< (CAN_NDAT1) New Data 31 Position */ -#define CAN_NDAT1_ND31_Msk (_U_(0x1) << CAN_NDAT1_ND31_Pos) /**< (CAN_NDAT1) New Data 31 Mask */ -#define CAN_NDAT1_ND31(value) (CAN_NDAT1_ND31_Msk & ((value) << CAN_NDAT1_ND31_Pos)) -#define CAN_NDAT1_Msk _U_(0xFFFFFFFF) /**< (CAN_NDAT1) Register Mask */ - -#define CAN_NDAT1_ND_Pos _U_(0) /**< (CAN_NDAT1 Position) New Data 3x */ -#define CAN_NDAT1_ND_Msk (_U_(0xFFFFFFFF) << CAN_NDAT1_ND_Pos) /**< (CAN_NDAT1 Mask) ND */ -#define CAN_NDAT1_ND(value) (CAN_NDAT1_ND_Msk & ((value) << CAN_NDAT1_ND_Pos)) - -/* -------- CAN_NDAT2 : (CAN Offset: 0x9C) (R/W 32) New Data 2 -------- */ -#define CAN_NDAT2_RESETVALUE _U_(0x00) /**< (CAN_NDAT2) New Data 2 Reset Value */ - -#define CAN_NDAT2_ND32_Pos _U_(0) /**< (CAN_NDAT2) New Data 32 Position */ -#define CAN_NDAT2_ND32_Msk (_U_(0x1) << CAN_NDAT2_ND32_Pos) /**< (CAN_NDAT2) New Data 32 Mask */ -#define CAN_NDAT2_ND32(value) (CAN_NDAT2_ND32_Msk & ((value) << CAN_NDAT2_ND32_Pos)) -#define CAN_NDAT2_ND33_Pos _U_(1) /**< (CAN_NDAT2) New Data 33 Position */ -#define CAN_NDAT2_ND33_Msk (_U_(0x1) << CAN_NDAT2_ND33_Pos) /**< (CAN_NDAT2) New Data 33 Mask */ -#define CAN_NDAT2_ND33(value) (CAN_NDAT2_ND33_Msk & ((value) << CAN_NDAT2_ND33_Pos)) -#define CAN_NDAT2_ND34_Pos _U_(2) /**< (CAN_NDAT2) New Data 34 Position */ -#define CAN_NDAT2_ND34_Msk (_U_(0x1) << CAN_NDAT2_ND34_Pos) /**< (CAN_NDAT2) New Data 34 Mask */ -#define CAN_NDAT2_ND34(value) (CAN_NDAT2_ND34_Msk & ((value) << CAN_NDAT2_ND34_Pos)) -#define CAN_NDAT2_ND35_Pos _U_(3) /**< (CAN_NDAT2) New Data 35 Position */ -#define CAN_NDAT2_ND35_Msk (_U_(0x1) << CAN_NDAT2_ND35_Pos) /**< (CAN_NDAT2) New Data 35 Mask */ -#define CAN_NDAT2_ND35(value) (CAN_NDAT2_ND35_Msk & ((value) << CAN_NDAT2_ND35_Pos)) -#define CAN_NDAT2_ND36_Pos _U_(4) /**< (CAN_NDAT2) New Data 36 Position */ -#define CAN_NDAT2_ND36_Msk (_U_(0x1) << CAN_NDAT2_ND36_Pos) /**< (CAN_NDAT2) New Data 36 Mask */ -#define CAN_NDAT2_ND36(value) (CAN_NDAT2_ND36_Msk & ((value) << CAN_NDAT2_ND36_Pos)) -#define CAN_NDAT2_ND37_Pos _U_(5) /**< (CAN_NDAT2) New Data 37 Position */ -#define CAN_NDAT2_ND37_Msk (_U_(0x1) << CAN_NDAT2_ND37_Pos) /**< (CAN_NDAT2) New Data 37 Mask */ -#define CAN_NDAT2_ND37(value) (CAN_NDAT2_ND37_Msk & ((value) << CAN_NDAT2_ND37_Pos)) -#define CAN_NDAT2_ND38_Pos _U_(6) /**< (CAN_NDAT2) New Data 38 Position */ -#define CAN_NDAT2_ND38_Msk (_U_(0x1) << CAN_NDAT2_ND38_Pos) /**< (CAN_NDAT2) New Data 38 Mask */ -#define CAN_NDAT2_ND38(value) (CAN_NDAT2_ND38_Msk & ((value) << CAN_NDAT2_ND38_Pos)) -#define CAN_NDAT2_ND39_Pos _U_(7) /**< (CAN_NDAT2) New Data 39 Position */ -#define CAN_NDAT2_ND39_Msk (_U_(0x1) << CAN_NDAT2_ND39_Pos) /**< (CAN_NDAT2) New Data 39 Mask */ -#define CAN_NDAT2_ND39(value) (CAN_NDAT2_ND39_Msk & ((value) << CAN_NDAT2_ND39_Pos)) -#define CAN_NDAT2_ND40_Pos _U_(8) /**< (CAN_NDAT2) New Data 40 Position */ -#define CAN_NDAT2_ND40_Msk (_U_(0x1) << CAN_NDAT2_ND40_Pos) /**< (CAN_NDAT2) New Data 40 Mask */ -#define CAN_NDAT2_ND40(value) (CAN_NDAT2_ND40_Msk & ((value) << CAN_NDAT2_ND40_Pos)) -#define CAN_NDAT2_ND41_Pos _U_(9) /**< (CAN_NDAT2) New Data 41 Position */ -#define CAN_NDAT2_ND41_Msk (_U_(0x1) << CAN_NDAT2_ND41_Pos) /**< (CAN_NDAT2) New Data 41 Mask */ -#define CAN_NDAT2_ND41(value) (CAN_NDAT2_ND41_Msk & ((value) << CAN_NDAT2_ND41_Pos)) -#define CAN_NDAT2_ND42_Pos _U_(10) /**< (CAN_NDAT2) New Data 42 Position */ -#define CAN_NDAT2_ND42_Msk (_U_(0x1) << CAN_NDAT2_ND42_Pos) /**< (CAN_NDAT2) New Data 42 Mask */ -#define CAN_NDAT2_ND42(value) (CAN_NDAT2_ND42_Msk & ((value) << CAN_NDAT2_ND42_Pos)) -#define CAN_NDAT2_ND43_Pos _U_(11) /**< (CAN_NDAT2) New Data 43 Position */ -#define CAN_NDAT2_ND43_Msk (_U_(0x1) << CAN_NDAT2_ND43_Pos) /**< (CAN_NDAT2) New Data 43 Mask */ -#define CAN_NDAT2_ND43(value) (CAN_NDAT2_ND43_Msk & ((value) << CAN_NDAT2_ND43_Pos)) -#define CAN_NDAT2_ND44_Pos _U_(12) /**< (CAN_NDAT2) New Data 44 Position */ -#define CAN_NDAT2_ND44_Msk (_U_(0x1) << CAN_NDAT2_ND44_Pos) /**< (CAN_NDAT2) New Data 44 Mask */ -#define CAN_NDAT2_ND44(value) (CAN_NDAT2_ND44_Msk & ((value) << CAN_NDAT2_ND44_Pos)) -#define CAN_NDAT2_ND45_Pos _U_(13) /**< (CAN_NDAT2) New Data 45 Position */ -#define CAN_NDAT2_ND45_Msk (_U_(0x1) << CAN_NDAT2_ND45_Pos) /**< (CAN_NDAT2) New Data 45 Mask */ -#define CAN_NDAT2_ND45(value) (CAN_NDAT2_ND45_Msk & ((value) << CAN_NDAT2_ND45_Pos)) -#define CAN_NDAT2_ND46_Pos _U_(14) /**< (CAN_NDAT2) New Data 46 Position */ -#define CAN_NDAT2_ND46_Msk (_U_(0x1) << CAN_NDAT2_ND46_Pos) /**< (CAN_NDAT2) New Data 46 Mask */ -#define CAN_NDAT2_ND46(value) (CAN_NDAT2_ND46_Msk & ((value) << CAN_NDAT2_ND46_Pos)) -#define CAN_NDAT2_ND47_Pos _U_(15) /**< (CAN_NDAT2) New Data 47 Position */ -#define CAN_NDAT2_ND47_Msk (_U_(0x1) << CAN_NDAT2_ND47_Pos) /**< (CAN_NDAT2) New Data 47 Mask */ -#define CAN_NDAT2_ND47(value) (CAN_NDAT2_ND47_Msk & ((value) << CAN_NDAT2_ND47_Pos)) -#define CAN_NDAT2_ND48_Pos _U_(16) /**< (CAN_NDAT2) New Data 48 Position */ -#define CAN_NDAT2_ND48_Msk (_U_(0x1) << CAN_NDAT2_ND48_Pos) /**< (CAN_NDAT2) New Data 48 Mask */ -#define CAN_NDAT2_ND48(value) (CAN_NDAT2_ND48_Msk & ((value) << CAN_NDAT2_ND48_Pos)) -#define CAN_NDAT2_ND49_Pos _U_(17) /**< (CAN_NDAT2) New Data 49 Position */ -#define CAN_NDAT2_ND49_Msk (_U_(0x1) << CAN_NDAT2_ND49_Pos) /**< (CAN_NDAT2) New Data 49 Mask */ -#define CAN_NDAT2_ND49(value) (CAN_NDAT2_ND49_Msk & ((value) << CAN_NDAT2_ND49_Pos)) -#define CAN_NDAT2_ND50_Pos _U_(18) /**< (CAN_NDAT2) New Data 50 Position */ -#define CAN_NDAT2_ND50_Msk (_U_(0x1) << CAN_NDAT2_ND50_Pos) /**< (CAN_NDAT2) New Data 50 Mask */ -#define CAN_NDAT2_ND50(value) (CAN_NDAT2_ND50_Msk & ((value) << CAN_NDAT2_ND50_Pos)) -#define CAN_NDAT2_ND51_Pos _U_(19) /**< (CAN_NDAT2) New Data 51 Position */ -#define CAN_NDAT2_ND51_Msk (_U_(0x1) << CAN_NDAT2_ND51_Pos) /**< (CAN_NDAT2) New Data 51 Mask */ -#define CAN_NDAT2_ND51(value) (CAN_NDAT2_ND51_Msk & ((value) << CAN_NDAT2_ND51_Pos)) -#define CAN_NDAT2_ND52_Pos _U_(20) /**< (CAN_NDAT2) New Data 52 Position */ -#define CAN_NDAT2_ND52_Msk (_U_(0x1) << CAN_NDAT2_ND52_Pos) /**< (CAN_NDAT2) New Data 52 Mask */ -#define CAN_NDAT2_ND52(value) (CAN_NDAT2_ND52_Msk & ((value) << CAN_NDAT2_ND52_Pos)) -#define CAN_NDAT2_ND53_Pos _U_(21) /**< (CAN_NDAT2) New Data 53 Position */ -#define CAN_NDAT2_ND53_Msk (_U_(0x1) << CAN_NDAT2_ND53_Pos) /**< (CAN_NDAT2) New Data 53 Mask */ -#define CAN_NDAT2_ND53(value) (CAN_NDAT2_ND53_Msk & ((value) << CAN_NDAT2_ND53_Pos)) -#define CAN_NDAT2_ND54_Pos _U_(22) /**< (CAN_NDAT2) New Data 54 Position */ -#define CAN_NDAT2_ND54_Msk (_U_(0x1) << CAN_NDAT2_ND54_Pos) /**< (CAN_NDAT2) New Data 54 Mask */ -#define CAN_NDAT2_ND54(value) (CAN_NDAT2_ND54_Msk & ((value) << CAN_NDAT2_ND54_Pos)) -#define CAN_NDAT2_ND55_Pos _U_(23) /**< (CAN_NDAT2) New Data 55 Position */ -#define CAN_NDAT2_ND55_Msk (_U_(0x1) << CAN_NDAT2_ND55_Pos) /**< (CAN_NDAT2) New Data 55 Mask */ -#define CAN_NDAT2_ND55(value) (CAN_NDAT2_ND55_Msk & ((value) << CAN_NDAT2_ND55_Pos)) -#define CAN_NDAT2_ND56_Pos _U_(24) /**< (CAN_NDAT2) New Data 56 Position */ -#define CAN_NDAT2_ND56_Msk (_U_(0x1) << CAN_NDAT2_ND56_Pos) /**< (CAN_NDAT2) New Data 56 Mask */ -#define CAN_NDAT2_ND56(value) (CAN_NDAT2_ND56_Msk & ((value) << CAN_NDAT2_ND56_Pos)) -#define CAN_NDAT2_ND57_Pos _U_(25) /**< (CAN_NDAT2) New Data 57 Position */ -#define CAN_NDAT2_ND57_Msk (_U_(0x1) << CAN_NDAT2_ND57_Pos) /**< (CAN_NDAT2) New Data 57 Mask */ -#define CAN_NDAT2_ND57(value) (CAN_NDAT2_ND57_Msk & ((value) << CAN_NDAT2_ND57_Pos)) -#define CAN_NDAT2_ND58_Pos _U_(26) /**< (CAN_NDAT2) New Data 58 Position */ -#define CAN_NDAT2_ND58_Msk (_U_(0x1) << CAN_NDAT2_ND58_Pos) /**< (CAN_NDAT2) New Data 58 Mask */ -#define CAN_NDAT2_ND58(value) (CAN_NDAT2_ND58_Msk & ((value) << CAN_NDAT2_ND58_Pos)) -#define CAN_NDAT2_ND59_Pos _U_(27) /**< (CAN_NDAT2) New Data 59 Position */ -#define CAN_NDAT2_ND59_Msk (_U_(0x1) << CAN_NDAT2_ND59_Pos) /**< (CAN_NDAT2) New Data 59 Mask */ -#define CAN_NDAT2_ND59(value) (CAN_NDAT2_ND59_Msk & ((value) << CAN_NDAT2_ND59_Pos)) -#define CAN_NDAT2_ND60_Pos _U_(28) /**< (CAN_NDAT2) New Data 60 Position */ -#define CAN_NDAT2_ND60_Msk (_U_(0x1) << CAN_NDAT2_ND60_Pos) /**< (CAN_NDAT2) New Data 60 Mask */ -#define CAN_NDAT2_ND60(value) (CAN_NDAT2_ND60_Msk & ((value) << CAN_NDAT2_ND60_Pos)) -#define CAN_NDAT2_ND61_Pos _U_(29) /**< (CAN_NDAT2) New Data 61 Position */ -#define CAN_NDAT2_ND61_Msk (_U_(0x1) << CAN_NDAT2_ND61_Pos) /**< (CAN_NDAT2) New Data 61 Mask */ -#define CAN_NDAT2_ND61(value) (CAN_NDAT2_ND61_Msk & ((value) << CAN_NDAT2_ND61_Pos)) -#define CAN_NDAT2_ND62_Pos _U_(30) /**< (CAN_NDAT2) New Data 62 Position */ -#define CAN_NDAT2_ND62_Msk (_U_(0x1) << CAN_NDAT2_ND62_Pos) /**< (CAN_NDAT2) New Data 62 Mask */ -#define CAN_NDAT2_ND62(value) (CAN_NDAT2_ND62_Msk & ((value) << CAN_NDAT2_ND62_Pos)) -#define CAN_NDAT2_ND63_Pos _U_(31) /**< (CAN_NDAT2) New Data 63 Position */ -#define CAN_NDAT2_ND63_Msk (_U_(0x1) << CAN_NDAT2_ND63_Pos) /**< (CAN_NDAT2) New Data 63 Mask */ -#define CAN_NDAT2_ND63(value) (CAN_NDAT2_ND63_Msk & ((value) << CAN_NDAT2_ND63_Pos)) -#define CAN_NDAT2_Msk _U_(0xFFFFFFFF) /**< (CAN_NDAT2) Register Mask */ - -#define CAN_NDAT2_ND_Pos _U_(0) /**< (CAN_NDAT2 Position) New Data 63 */ -#define CAN_NDAT2_ND_Msk (_U_(0xFFFFFFFF) << CAN_NDAT2_ND_Pos) /**< (CAN_NDAT2 Mask) ND */ -#define CAN_NDAT2_ND(value) (CAN_NDAT2_ND_Msk & ((value) << CAN_NDAT2_ND_Pos)) - -/* -------- CAN_RXF0C : (CAN Offset: 0xA0) (R/W 32) Rx FIFO 0 Configuration -------- */ -#define CAN_RXF0C_RESETVALUE _U_(0x00) /**< (CAN_RXF0C) Rx FIFO 0 Configuration Reset Value */ - -#define CAN_RXF0C_F0SA_Pos _U_(0) /**< (CAN_RXF0C) Rx FIFO 0 Start Address Position */ -#define CAN_RXF0C_F0SA_Msk (_U_(0xFFFF) << CAN_RXF0C_F0SA_Pos) /**< (CAN_RXF0C) Rx FIFO 0 Start Address Mask */ -#define CAN_RXF0C_F0SA(value) (CAN_RXF0C_F0SA_Msk & ((value) << CAN_RXF0C_F0SA_Pos)) -#define CAN_RXF0C_F0S_Pos _U_(16) /**< (CAN_RXF0C) Rx FIFO 0 Size Position */ -#define CAN_RXF0C_F0S_Msk (_U_(0x7F) << CAN_RXF0C_F0S_Pos) /**< (CAN_RXF0C) Rx FIFO 0 Size Mask */ -#define CAN_RXF0C_F0S(value) (CAN_RXF0C_F0S_Msk & ((value) << CAN_RXF0C_F0S_Pos)) -#define CAN_RXF0C_F0WM_Pos _U_(24) /**< (CAN_RXF0C) Rx FIFO 0 Watermark Position */ -#define CAN_RXF0C_F0WM_Msk (_U_(0x7F) << CAN_RXF0C_F0WM_Pos) /**< (CAN_RXF0C) Rx FIFO 0 Watermark Mask */ -#define CAN_RXF0C_F0WM(value) (CAN_RXF0C_F0WM_Msk & ((value) << CAN_RXF0C_F0WM_Pos)) -#define CAN_RXF0C_F0OM_Pos _U_(31) /**< (CAN_RXF0C) FIFO 0 Operation Mode Position */ -#define CAN_RXF0C_F0OM_Msk (_U_(0x1) << CAN_RXF0C_F0OM_Pos) /**< (CAN_RXF0C) FIFO 0 Operation Mode Mask */ -#define CAN_RXF0C_F0OM(value) (CAN_RXF0C_F0OM_Msk & ((value) << CAN_RXF0C_F0OM_Pos)) -#define CAN_RXF0C_Msk _U_(0xFF7FFFFF) /**< (CAN_RXF0C) Register Mask */ - - -/* -------- CAN_RXF0S : (CAN Offset: 0xA4) ( R/ 32) Rx FIFO 0 Status -------- */ -#define CAN_RXF0S_RESETVALUE _U_(0x00) /**< (CAN_RXF0S) Rx FIFO 0 Status Reset Value */ - -#define CAN_RXF0S_F0FL_Pos _U_(0) /**< (CAN_RXF0S) Rx FIFO 0 Fill Level Position */ -#define CAN_RXF0S_F0FL_Msk (_U_(0x7F) << CAN_RXF0S_F0FL_Pos) /**< (CAN_RXF0S) Rx FIFO 0 Fill Level Mask */ -#define CAN_RXF0S_F0FL(value) (CAN_RXF0S_F0FL_Msk & ((value) << CAN_RXF0S_F0FL_Pos)) -#define CAN_RXF0S_F0GI_Pos _U_(8) /**< (CAN_RXF0S) Rx FIFO 0 Get Index Position */ -#define CAN_RXF0S_F0GI_Msk (_U_(0x3F) << CAN_RXF0S_F0GI_Pos) /**< (CAN_RXF0S) Rx FIFO 0 Get Index Mask */ -#define CAN_RXF0S_F0GI(value) (CAN_RXF0S_F0GI_Msk & ((value) << CAN_RXF0S_F0GI_Pos)) -#define CAN_RXF0S_F0PI_Pos _U_(16) /**< (CAN_RXF0S) Rx FIFO 0 Put Index Position */ -#define CAN_RXF0S_F0PI_Msk (_U_(0x3F) << CAN_RXF0S_F0PI_Pos) /**< (CAN_RXF0S) Rx FIFO 0 Put Index Mask */ -#define CAN_RXF0S_F0PI(value) (CAN_RXF0S_F0PI_Msk & ((value) << CAN_RXF0S_F0PI_Pos)) -#define CAN_RXF0S_F0F_Pos _U_(24) /**< (CAN_RXF0S) Rx FIFO 0 Full Position */ -#define CAN_RXF0S_F0F_Msk (_U_(0x1) << CAN_RXF0S_F0F_Pos) /**< (CAN_RXF0S) Rx FIFO 0 Full Mask */ -#define CAN_RXF0S_F0F(value) (CAN_RXF0S_F0F_Msk & ((value) << CAN_RXF0S_F0F_Pos)) -#define CAN_RXF0S_RF0L_Pos _U_(25) /**< (CAN_RXF0S) Rx FIFO 0 Message Lost Position */ -#define CAN_RXF0S_RF0L_Msk (_U_(0x1) << CAN_RXF0S_RF0L_Pos) /**< (CAN_RXF0S) Rx FIFO 0 Message Lost Mask */ -#define CAN_RXF0S_RF0L(value) (CAN_RXF0S_RF0L_Msk & ((value) << CAN_RXF0S_RF0L_Pos)) -#define CAN_RXF0S_Msk _U_(0x033F3F7F) /**< (CAN_RXF0S) Register Mask */ - - -/* -------- CAN_RXF0A : (CAN Offset: 0xA8) (R/W 32) Rx FIFO 0 Acknowledge -------- */ -#define CAN_RXF0A_RESETVALUE _U_(0x00) /**< (CAN_RXF0A) Rx FIFO 0 Acknowledge Reset Value */ - -#define CAN_RXF0A_F0AI_Pos _U_(0) /**< (CAN_RXF0A) Rx FIFO 0 Acknowledge Index Position */ -#define CAN_RXF0A_F0AI_Msk (_U_(0x3F) << CAN_RXF0A_F0AI_Pos) /**< (CAN_RXF0A) Rx FIFO 0 Acknowledge Index Mask */ -#define CAN_RXF0A_F0AI(value) (CAN_RXF0A_F0AI_Msk & ((value) << CAN_RXF0A_F0AI_Pos)) -#define CAN_RXF0A_Msk _U_(0x0000003F) /**< (CAN_RXF0A) Register Mask */ - - -/* -------- CAN_RXBC : (CAN Offset: 0xAC) (R/W 32) Rx Buffer Configuration -------- */ -#define CAN_RXBC_RESETVALUE _U_(0x00) /**< (CAN_RXBC) Rx Buffer Configuration Reset Value */ - -#define CAN_RXBC_RBSA_Pos _U_(0) /**< (CAN_RXBC) Rx Buffer Start Address Position */ -#define CAN_RXBC_RBSA_Msk (_U_(0xFFFF) << CAN_RXBC_RBSA_Pos) /**< (CAN_RXBC) Rx Buffer Start Address Mask */ -#define CAN_RXBC_RBSA(value) (CAN_RXBC_RBSA_Msk & ((value) << CAN_RXBC_RBSA_Pos)) -#define CAN_RXBC_Msk _U_(0x0000FFFF) /**< (CAN_RXBC) Register Mask */ - - -/* -------- CAN_RXF1C : (CAN Offset: 0xB0) (R/W 32) Rx FIFO 1 Configuration -------- */ -#define CAN_RXF1C_RESETVALUE _U_(0x00) /**< (CAN_RXF1C) Rx FIFO 1 Configuration Reset Value */ - -#define CAN_RXF1C_F1SA_Pos _U_(0) /**< (CAN_RXF1C) Rx FIFO 1 Start Address Position */ -#define CAN_RXF1C_F1SA_Msk (_U_(0xFFFF) << CAN_RXF1C_F1SA_Pos) /**< (CAN_RXF1C) Rx FIFO 1 Start Address Mask */ -#define CAN_RXF1C_F1SA(value) (CAN_RXF1C_F1SA_Msk & ((value) << CAN_RXF1C_F1SA_Pos)) -#define CAN_RXF1C_F1S_Pos _U_(16) /**< (CAN_RXF1C) Rx FIFO 1 Size Position */ -#define CAN_RXF1C_F1S_Msk (_U_(0x7F) << CAN_RXF1C_F1S_Pos) /**< (CAN_RXF1C) Rx FIFO 1 Size Mask */ -#define CAN_RXF1C_F1S(value) (CAN_RXF1C_F1S_Msk & ((value) << CAN_RXF1C_F1S_Pos)) -#define CAN_RXF1C_F1WM_Pos _U_(24) /**< (CAN_RXF1C) Rx FIFO 1 Watermark Position */ -#define CAN_RXF1C_F1WM_Msk (_U_(0x7F) << CAN_RXF1C_F1WM_Pos) /**< (CAN_RXF1C) Rx FIFO 1 Watermark Mask */ -#define CAN_RXF1C_F1WM(value) (CAN_RXF1C_F1WM_Msk & ((value) << CAN_RXF1C_F1WM_Pos)) -#define CAN_RXF1C_F1OM_Pos _U_(31) /**< (CAN_RXF1C) FIFO 1 Operation Mode Position */ -#define CAN_RXF1C_F1OM_Msk (_U_(0x1) << CAN_RXF1C_F1OM_Pos) /**< (CAN_RXF1C) FIFO 1 Operation Mode Mask */ -#define CAN_RXF1C_F1OM(value) (CAN_RXF1C_F1OM_Msk & ((value) << CAN_RXF1C_F1OM_Pos)) -#define CAN_RXF1C_Msk _U_(0xFF7FFFFF) /**< (CAN_RXF1C) Register Mask */ - - -/* -------- CAN_RXF1S : (CAN Offset: 0xB4) ( R/ 32) Rx FIFO 1 Status -------- */ -#define CAN_RXF1S_RESETVALUE _U_(0x00) /**< (CAN_RXF1S) Rx FIFO 1 Status Reset Value */ - -#define CAN_RXF1S_F1FL_Pos _U_(0) /**< (CAN_RXF1S) Rx FIFO 1 Fill Level Position */ -#define CAN_RXF1S_F1FL_Msk (_U_(0x7F) << CAN_RXF1S_F1FL_Pos) /**< (CAN_RXF1S) Rx FIFO 1 Fill Level Mask */ -#define CAN_RXF1S_F1FL(value) (CAN_RXF1S_F1FL_Msk & ((value) << CAN_RXF1S_F1FL_Pos)) -#define CAN_RXF1S_F1GI_Pos _U_(8) /**< (CAN_RXF1S) Rx FIFO 1 Get Index Position */ -#define CAN_RXF1S_F1GI_Msk (_U_(0x3F) << CAN_RXF1S_F1GI_Pos) /**< (CAN_RXF1S) Rx FIFO 1 Get Index Mask */ -#define CAN_RXF1S_F1GI(value) (CAN_RXF1S_F1GI_Msk & ((value) << CAN_RXF1S_F1GI_Pos)) -#define CAN_RXF1S_F1PI_Pos _U_(16) /**< (CAN_RXF1S) Rx FIFO 1 Put Index Position */ -#define CAN_RXF1S_F1PI_Msk (_U_(0x3F) << CAN_RXF1S_F1PI_Pos) /**< (CAN_RXF1S) Rx FIFO 1 Put Index Mask */ -#define CAN_RXF1S_F1PI(value) (CAN_RXF1S_F1PI_Msk & ((value) << CAN_RXF1S_F1PI_Pos)) -#define CAN_RXF1S_F1F_Pos _U_(24) /**< (CAN_RXF1S) Rx FIFO 1 Full Position */ -#define CAN_RXF1S_F1F_Msk (_U_(0x1) << CAN_RXF1S_F1F_Pos) /**< (CAN_RXF1S) Rx FIFO 1 Full Mask */ -#define CAN_RXF1S_F1F(value) (CAN_RXF1S_F1F_Msk & ((value) << CAN_RXF1S_F1F_Pos)) -#define CAN_RXF1S_RF1L_Pos _U_(25) /**< (CAN_RXF1S) Rx FIFO 1 Message Lost Position */ -#define CAN_RXF1S_RF1L_Msk (_U_(0x1) << CAN_RXF1S_RF1L_Pos) /**< (CAN_RXF1S) Rx FIFO 1 Message Lost Mask */ -#define CAN_RXF1S_RF1L(value) (CAN_RXF1S_RF1L_Msk & ((value) << CAN_RXF1S_RF1L_Pos)) -#define CAN_RXF1S_DMS_Pos _U_(30) /**< (CAN_RXF1S) Debug Message Status Position */ -#define CAN_RXF1S_DMS_Msk (_U_(0x3) << CAN_RXF1S_DMS_Pos) /**< (CAN_RXF1S) Debug Message Status Mask */ -#define CAN_RXF1S_DMS(value) (CAN_RXF1S_DMS_Msk & ((value) << CAN_RXF1S_DMS_Pos)) -#define CAN_RXF1S_DMS_IDLE_Val _U_(0x0) /**< (CAN_RXF1S) Idle state */ -#define CAN_RXF1S_DMS_DBGA_Val _U_(0x1) /**< (CAN_RXF1S) Debug message A received */ -#define CAN_RXF1S_DMS_DBGB_Val _U_(0x2) /**< (CAN_RXF1S) Debug message A/B received */ -#define CAN_RXF1S_DMS_DBGC_Val _U_(0x3) /**< (CAN_RXF1S) Debug message A/B/C received, DMA request set */ -#define CAN_RXF1S_DMS_IDLE (CAN_RXF1S_DMS_IDLE_Val << CAN_RXF1S_DMS_Pos) /**< (CAN_RXF1S) Idle state Position */ -#define CAN_RXF1S_DMS_DBGA (CAN_RXF1S_DMS_DBGA_Val << CAN_RXF1S_DMS_Pos) /**< (CAN_RXF1S) Debug message A received Position */ -#define CAN_RXF1S_DMS_DBGB (CAN_RXF1S_DMS_DBGB_Val << CAN_RXF1S_DMS_Pos) /**< (CAN_RXF1S) Debug message A/B received Position */ -#define CAN_RXF1S_DMS_DBGC (CAN_RXF1S_DMS_DBGC_Val << CAN_RXF1S_DMS_Pos) /**< (CAN_RXF1S) Debug message A/B/C received, DMA request set Position */ -#define CAN_RXF1S_Msk _U_(0xC33F3F7F) /**< (CAN_RXF1S) Register Mask */ - - -/* -------- CAN_RXF1A : (CAN Offset: 0xB8) (R/W 32) Rx FIFO 1 Acknowledge -------- */ -#define CAN_RXF1A_RESETVALUE _U_(0x00) /**< (CAN_RXF1A) Rx FIFO 1 Acknowledge Reset Value */ - -#define CAN_RXF1A_F1AI_Pos _U_(0) /**< (CAN_RXF1A) Rx FIFO 1 Acknowledge Index Position */ -#define CAN_RXF1A_F1AI_Msk (_U_(0x3F) << CAN_RXF1A_F1AI_Pos) /**< (CAN_RXF1A) Rx FIFO 1 Acknowledge Index Mask */ -#define CAN_RXF1A_F1AI(value) (CAN_RXF1A_F1AI_Msk & ((value) << CAN_RXF1A_F1AI_Pos)) -#define CAN_RXF1A_Msk _U_(0x0000003F) /**< (CAN_RXF1A) Register Mask */ - - -/* -------- CAN_RXESC : (CAN Offset: 0xBC) (R/W 32) Rx Buffer / FIFO Element Size Configuration -------- */ -#define CAN_RXESC_RESETVALUE _U_(0x00) /**< (CAN_RXESC) Rx Buffer / FIFO Element Size Configuration Reset Value */ - -#define CAN_RXESC_F0DS_Pos _U_(0) /**< (CAN_RXESC) Rx FIFO 0 Data Field Size Position */ -#define CAN_RXESC_F0DS_Msk (_U_(0x7) << CAN_RXESC_F0DS_Pos) /**< (CAN_RXESC) Rx FIFO 0 Data Field Size Mask */ -#define CAN_RXESC_F0DS(value) (CAN_RXESC_F0DS_Msk & ((value) << CAN_RXESC_F0DS_Pos)) -#define CAN_RXESC_F0DS_DATA8_Val _U_(0x0) /**< (CAN_RXESC) 8 byte data field */ -#define CAN_RXESC_F0DS_DATA12_Val _U_(0x1) /**< (CAN_RXESC) 12 byte data field */ -#define CAN_RXESC_F0DS_DATA16_Val _U_(0x2) /**< (CAN_RXESC) 16 byte data field */ -#define CAN_RXESC_F0DS_DATA20_Val _U_(0x3) /**< (CAN_RXESC) 20 byte data field */ -#define CAN_RXESC_F0DS_DATA24_Val _U_(0x4) /**< (CAN_RXESC) 24 byte data field */ -#define CAN_RXESC_F0DS_DATA32_Val _U_(0x5) /**< (CAN_RXESC) 32 byte data field */ -#define CAN_RXESC_F0DS_DATA48_Val _U_(0x6) /**< (CAN_RXESC) 48 byte data field */ -#define CAN_RXESC_F0DS_DATA64_Val _U_(0x7) /**< (CAN_RXESC) 64 byte data field */ -#define CAN_RXESC_F0DS_DATA8 (CAN_RXESC_F0DS_DATA8_Val << CAN_RXESC_F0DS_Pos) /**< (CAN_RXESC) 8 byte data field Position */ -#define CAN_RXESC_F0DS_DATA12 (CAN_RXESC_F0DS_DATA12_Val << CAN_RXESC_F0DS_Pos) /**< (CAN_RXESC) 12 byte data field Position */ -#define CAN_RXESC_F0DS_DATA16 (CAN_RXESC_F0DS_DATA16_Val << CAN_RXESC_F0DS_Pos) /**< (CAN_RXESC) 16 byte data field Position */ -#define CAN_RXESC_F0DS_DATA20 (CAN_RXESC_F0DS_DATA20_Val << CAN_RXESC_F0DS_Pos) /**< (CAN_RXESC) 20 byte data field Position */ -#define CAN_RXESC_F0DS_DATA24 (CAN_RXESC_F0DS_DATA24_Val << CAN_RXESC_F0DS_Pos) /**< (CAN_RXESC) 24 byte data field Position */ -#define CAN_RXESC_F0DS_DATA32 (CAN_RXESC_F0DS_DATA32_Val << CAN_RXESC_F0DS_Pos) /**< (CAN_RXESC) 32 byte data field Position */ -#define CAN_RXESC_F0DS_DATA48 (CAN_RXESC_F0DS_DATA48_Val << CAN_RXESC_F0DS_Pos) /**< (CAN_RXESC) 48 byte data field Position */ -#define CAN_RXESC_F0DS_DATA64 (CAN_RXESC_F0DS_DATA64_Val << CAN_RXESC_F0DS_Pos) /**< (CAN_RXESC) 64 byte data field Position */ -#define CAN_RXESC_F1DS_Pos _U_(4) /**< (CAN_RXESC) Rx FIFO 1 Data Field Size Position */ -#define CAN_RXESC_F1DS_Msk (_U_(0x7) << CAN_RXESC_F1DS_Pos) /**< (CAN_RXESC) Rx FIFO 1 Data Field Size Mask */ -#define CAN_RXESC_F1DS(value) (CAN_RXESC_F1DS_Msk & ((value) << CAN_RXESC_F1DS_Pos)) -#define CAN_RXESC_F1DS_DATA8_Val _U_(0x0) /**< (CAN_RXESC) 8 byte data field */ -#define CAN_RXESC_F1DS_DATA12_Val _U_(0x1) /**< (CAN_RXESC) 12 byte data field */ -#define CAN_RXESC_F1DS_DATA16_Val _U_(0x2) /**< (CAN_RXESC) 16 byte data field */ -#define CAN_RXESC_F1DS_DATA20_Val _U_(0x3) /**< (CAN_RXESC) 20 byte data field */ -#define CAN_RXESC_F1DS_DATA24_Val _U_(0x4) /**< (CAN_RXESC) 24 byte data field */ -#define CAN_RXESC_F1DS_DATA32_Val _U_(0x5) /**< (CAN_RXESC) 32 byte data field */ -#define CAN_RXESC_F1DS_DATA48_Val _U_(0x6) /**< (CAN_RXESC) 48 byte data field */ -#define CAN_RXESC_F1DS_DATA64_Val _U_(0x7) /**< (CAN_RXESC) 64 byte data field */ -#define CAN_RXESC_F1DS_DATA8 (CAN_RXESC_F1DS_DATA8_Val << CAN_RXESC_F1DS_Pos) /**< (CAN_RXESC) 8 byte data field Position */ -#define CAN_RXESC_F1DS_DATA12 (CAN_RXESC_F1DS_DATA12_Val << CAN_RXESC_F1DS_Pos) /**< (CAN_RXESC) 12 byte data field Position */ -#define CAN_RXESC_F1DS_DATA16 (CAN_RXESC_F1DS_DATA16_Val << CAN_RXESC_F1DS_Pos) /**< (CAN_RXESC) 16 byte data field Position */ -#define CAN_RXESC_F1DS_DATA20 (CAN_RXESC_F1DS_DATA20_Val << CAN_RXESC_F1DS_Pos) /**< (CAN_RXESC) 20 byte data field Position */ -#define CAN_RXESC_F1DS_DATA24 (CAN_RXESC_F1DS_DATA24_Val << CAN_RXESC_F1DS_Pos) /**< (CAN_RXESC) 24 byte data field Position */ -#define CAN_RXESC_F1DS_DATA32 (CAN_RXESC_F1DS_DATA32_Val << CAN_RXESC_F1DS_Pos) /**< (CAN_RXESC) 32 byte data field Position */ -#define CAN_RXESC_F1DS_DATA48 (CAN_RXESC_F1DS_DATA48_Val << CAN_RXESC_F1DS_Pos) /**< (CAN_RXESC) 48 byte data field Position */ -#define CAN_RXESC_F1DS_DATA64 (CAN_RXESC_F1DS_DATA64_Val << CAN_RXESC_F1DS_Pos) /**< (CAN_RXESC) 64 byte data field Position */ -#define CAN_RXESC_RBDS_Pos _U_(8) /**< (CAN_RXESC) Rx Buffer Data Field Size Position */ -#define CAN_RXESC_RBDS_Msk (_U_(0x7) << CAN_RXESC_RBDS_Pos) /**< (CAN_RXESC) Rx Buffer Data Field Size Mask */ -#define CAN_RXESC_RBDS(value) (CAN_RXESC_RBDS_Msk & ((value) << CAN_RXESC_RBDS_Pos)) -#define CAN_RXESC_RBDS_DATA8_Val _U_(0x0) /**< (CAN_RXESC) 8 byte data field */ -#define CAN_RXESC_RBDS_DATA12_Val _U_(0x1) /**< (CAN_RXESC) 12 byte data field */ -#define CAN_RXESC_RBDS_DATA16_Val _U_(0x2) /**< (CAN_RXESC) 16 byte data field */ -#define CAN_RXESC_RBDS_DATA20_Val _U_(0x3) /**< (CAN_RXESC) 20 byte data field */ -#define CAN_RXESC_RBDS_DATA24_Val _U_(0x4) /**< (CAN_RXESC) 24 byte data field */ -#define CAN_RXESC_RBDS_DATA32_Val _U_(0x5) /**< (CAN_RXESC) 32 byte data field */ -#define CAN_RXESC_RBDS_DATA48_Val _U_(0x6) /**< (CAN_RXESC) 48 byte data field */ -#define CAN_RXESC_RBDS_DATA64_Val _U_(0x7) /**< (CAN_RXESC) 64 byte data field */ -#define CAN_RXESC_RBDS_DATA8 (CAN_RXESC_RBDS_DATA8_Val << CAN_RXESC_RBDS_Pos) /**< (CAN_RXESC) 8 byte data field Position */ -#define CAN_RXESC_RBDS_DATA12 (CAN_RXESC_RBDS_DATA12_Val << CAN_RXESC_RBDS_Pos) /**< (CAN_RXESC) 12 byte data field Position */ -#define CAN_RXESC_RBDS_DATA16 (CAN_RXESC_RBDS_DATA16_Val << CAN_RXESC_RBDS_Pos) /**< (CAN_RXESC) 16 byte data field Position */ -#define CAN_RXESC_RBDS_DATA20 (CAN_RXESC_RBDS_DATA20_Val << CAN_RXESC_RBDS_Pos) /**< (CAN_RXESC) 20 byte data field Position */ -#define CAN_RXESC_RBDS_DATA24 (CAN_RXESC_RBDS_DATA24_Val << CAN_RXESC_RBDS_Pos) /**< (CAN_RXESC) 24 byte data field Position */ -#define CAN_RXESC_RBDS_DATA32 (CAN_RXESC_RBDS_DATA32_Val << CAN_RXESC_RBDS_Pos) /**< (CAN_RXESC) 32 byte data field Position */ -#define CAN_RXESC_RBDS_DATA48 (CAN_RXESC_RBDS_DATA48_Val << CAN_RXESC_RBDS_Pos) /**< (CAN_RXESC) 48 byte data field Position */ -#define CAN_RXESC_RBDS_DATA64 (CAN_RXESC_RBDS_DATA64_Val << CAN_RXESC_RBDS_Pos) /**< (CAN_RXESC) 64 byte data field Position */ -#define CAN_RXESC_Msk _U_(0x00000777) /**< (CAN_RXESC) Register Mask */ - - -/* -------- CAN_TXBC : (CAN Offset: 0xC0) (R/W 32) Tx Buffer Configuration -------- */ -#define CAN_TXBC_RESETVALUE _U_(0x00) /**< (CAN_TXBC) Tx Buffer Configuration Reset Value */ - -#define CAN_TXBC_TBSA_Pos _U_(0) /**< (CAN_TXBC) Tx Buffers Start Address Position */ -#define CAN_TXBC_TBSA_Msk (_U_(0xFFFF) << CAN_TXBC_TBSA_Pos) /**< (CAN_TXBC) Tx Buffers Start Address Mask */ -#define CAN_TXBC_TBSA(value) (CAN_TXBC_TBSA_Msk & ((value) << CAN_TXBC_TBSA_Pos)) -#define CAN_TXBC_NDTB_Pos _U_(16) /**< (CAN_TXBC) Number of Dedicated Transmit Buffers Position */ -#define CAN_TXBC_NDTB_Msk (_U_(0x3F) << CAN_TXBC_NDTB_Pos) /**< (CAN_TXBC) Number of Dedicated Transmit Buffers Mask */ -#define CAN_TXBC_NDTB(value) (CAN_TXBC_NDTB_Msk & ((value) << CAN_TXBC_NDTB_Pos)) -#define CAN_TXBC_TFQS_Pos _U_(24) /**< (CAN_TXBC) Transmit FIFO/Queue Size Position */ -#define CAN_TXBC_TFQS_Msk (_U_(0x3F) << CAN_TXBC_TFQS_Pos) /**< (CAN_TXBC) Transmit FIFO/Queue Size Mask */ -#define CAN_TXBC_TFQS(value) (CAN_TXBC_TFQS_Msk & ((value) << CAN_TXBC_TFQS_Pos)) -#define CAN_TXBC_TFQM_Pos _U_(30) /**< (CAN_TXBC) Tx FIFO/Queue Mode Position */ -#define CAN_TXBC_TFQM_Msk (_U_(0x1) << CAN_TXBC_TFQM_Pos) /**< (CAN_TXBC) Tx FIFO/Queue Mode Mask */ -#define CAN_TXBC_TFQM(value) (CAN_TXBC_TFQM_Msk & ((value) << CAN_TXBC_TFQM_Pos)) -#define CAN_TXBC_Msk _U_(0x7F3FFFFF) /**< (CAN_TXBC) Register Mask */ - - -/* -------- CAN_TXFQS : (CAN Offset: 0xC4) ( R/ 32) Tx FIFO / Queue Status -------- */ -#define CAN_TXFQS_RESETVALUE _U_(0x00) /**< (CAN_TXFQS) Tx FIFO / Queue Status Reset Value */ - -#define CAN_TXFQS_TFFL_Pos _U_(0) /**< (CAN_TXFQS) Tx FIFO Free Level Position */ -#define CAN_TXFQS_TFFL_Msk (_U_(0x3F) << CAN_TXFQS_TFFL_Pos) /**< (CAN_TXFQS) Tx FIFO Free Level Mask */ -#define CAN_TXFQS_TFFL(value) (CAN_TXFQS_TFFL_Msk & ((value) << CAN_TXFQS_TFFL_Pos)) -#define CAN_TXFQS_TFGI_Pos _U_(8) /**< (CAN_TXFQS) Tx FIFO Get Index Position */ -#define CAN_TXFQS_TFGI_Msk (_U_(0x1F) << CAN_TXFQS_TFGI_Pos) /**< (CAN_TXFQS) Tx FIFO Get Index Mask */ -#define CAN_TXFQS_TFGI(value) (CAN_TXFQS_TFGI_Msk & ((value) << CAN_TXFQS_TFGI_Pos)) -#define CAN_TXFQS_TFQPI_Pos _U_(16) /**< (CAN_TXFQS) Tx FIFO/Queue Put Index Position */ -#define CAN_TXFQS_TFQPI_Msk (_U_(0x1F) << CAN_TXFQS_TFQPI_Pos) /**< (CAN_TXFQS) Tx FIFO/Queue Put Index Mask */ -#define CAN_TXFQS_TFQPI(value) (CAN_TXFQS_TFQPI_Msk & ((value) << CAN_TXFQS_TFQPI_Pos)) -#define CAN_TXFQS_TFQF_Pos _U_(21) /**< (CAN_TXFQS) Tx FIFO/Queue Full Position */ -#define CAN_TXFQS_TFQF_Msk (_U_(0x1) << CAN_TXFQS_TFQF_Pos) /**< (CAN_TXFQS) Tx FIFO/Queue Full Mask */ -#define CAN_TXFQS_TFQF(value) (CAN_TXFQS_TFQF_Msk & ((value) << CAN_TXFQS_TFQF_Pos)) -#define CAN_TXFQS_Msk _U_(0x003F1F3F) /**< (CAN_TXFQS) Register Mask */ - - -/* -------- CAN_TXESC : (CAN Offset: 0xC8) (R/W 32) Tx Buffer Element Size Configuration -------- */ -#define CAN_TXESC_RESETVALUE _U_(0x00) /**< (CAN_TXESC) Tx Buffer Element Size Configuration Reset Value */ - -#define CAN_TXESC_TBDS_Pos _U_(0) /**< (CAN_TXESC) Tx Buffer Data Field Size Position */ -#define CAN_TXESC_TBDS_Msk (_U_(0x7) << CAN_TXESC_TBDS_Pos) /**< (CAN_TXESC) Tx Buffer Data Field Size Mask */ -#define CAN_TXESC_TBDS(value) (CAN_TXESC_TBDS_Msk & ((value) << CAN_TXESC_TBDS_Pos)) -#define CAN_TXESC_TBDS_DATA8_Val _U_(0x0) /**< (CAN_TXESC) 8 byte data field */ -#define CAN_TXESC_TBDS_DATA12_Val _U_(0x1) /**< (CAN_TXESC) 12 byte data field */ -#define CAN_TXESC_TBDS_DATA16_Val _U_(0x2) /**< (CAN_TXESC) 16 byte data field */ -#define CAN_TXESC_TBDS_DATA20_Val _U_(0x3) /**< (CAN_TXESC) 20 byte data field */ -#define CAN_TXESC_TBDS_DATA24_Val _U_(0x4) /**< (CAN_TXESC) 24 byte data field */ -#define CAN_TXESC_TBDS_DATA32_Val _U_(0x5) /**< (CAN_TXESC) 32 byte data field */ -#define CAN_TXESC_TBDS_DATA48_Val _U_(0x6) /**< (CAN_TXESC) 48 byte data field */ -#define CAN_TXESC_TBDS_DATA64_Val _U_(0x7) /**< (CAN_TXESC) 64 byte data field */ -#define CAN_TXESC_TBDS_DATA8 (CAN_TXESC_TBDS_DATA8_Val << CAN_TXESC_TBDS_Pos) /**< (CAN_TXESC) 8 byte data field Position */ -#define CAN_TXESC_TBDS_DATA12 (CAN_TXESC_TBDS_DATA12_Val << CAN_TXESC_TBDS_Pos) /**< (CAN_TXESC) 12 byte data field Position */ -#define CAN_TXESC_TBDS_DATA16 (CAN_TXESC_TBDS_DATA16_Val << CAN_TXESC_TBDS_Pos) /**< (CAN_TXESC) 16 byte data field Position */ -#define CAN_TXESC_TBDS_DATA20 (CAN_TXESC_TBDS_DATA20_Val << CAN_TXESC_TBDS_Pos) /**< (CAN_TXESC) 20 byte data field Position */ -#define CAN_TXESC_TBDS_DATA24 (CAN_TXESC_TBDS_DATA24_Val << CAN_TXESC_TBDS_Pos) /**< (CAN_TXESC) 24 byte data field Position */ -#define CAN_TXESC_TBDS_DATA32 (CAN_TXESC_TBDS_DATA32_Val << CAN_TXESC_TBDS_Pos) /**< (CAN_TXESC) 32 byte data field Position */ -#define CAN_TXESC_TBDS_DATA48 (CAN_TXESC_TBDS_DATA48_Val << CAN_TXESC_TBDS_Pos) /**< (CAN_TXESC) 48 byte data field Position */ -#define CAN_TXESC_TBDS_DATA64 (CAN_TXESC_TBDS_DATA64_Val << CAN_TXESC_TBDS_Pos) /**< (CAN_TXESC) 64 byte data field Position */ -#define CAN_TXESC_Msk _U_(0x00000007) /**< (CAN_TXESC) Register Mask */ - - -/* -------- CAN_TXBRP : (CAN Offset: 0xCC) ( R/ 32) Tx Buffer Request Pending -------- */ -#define CAN_TXBRP_RESETVALUE _U_(0x00) /**< (CAN_TXBRP) Tx Buffer Request Pending Reset Value */ - -#define CAN_TXBRP_TRP0_Pos _U_(0) /**< (CAN_TXBRP) Transmission Request Pending 0 Position */ -#define CAN_TXBRP_TRP0_Msk (_U_(0x1) << CAN_TXBRP_TRP0_Pos) /**< (CAN_TXBRP) Transmission Request Pending 0 Mask */ -#define CAN_TXBRP_TRP0(value) (CAN_TXBRP_TRP0_Msk & ((value) << CAN_TXBRP_TRP0_Pos)) -#define CAN_TXBRP_TRP1_Pos _U_(1) /**< (CAN_TXBRP) Transmission Request Pending 1 Position */ -#define CAN_TXBRP_TRP1_Msk (_U_(0x1) << CAN_TXBRP_TRP1_Pos) /**< (CAN_TXBRP) Transmission Request Pending 1 Mask */ -#define CAN_TXBRP_TRP1(value) (CAN_TXBRP_TRP1_Msk & ((value) << CAN_TXBRP_TRP1_Pos)) -#define CAN_TXBRP_TRP2_Pos _U_(2) /**< (CAN_TXBRP) Transmission Request Pending 2 Position */ -#define CAN_TXBRP_TRP2_Msk (_U_(0x1) << CAN_TXBRP_TRP2_Pos) /**< (CAN_TXBRP) Transmission Request Pending 2 Mask */ -#define CAN_TXBRP_TRP2(value) (CAN_TXBRP_TRP2_Msk & ((value) << CAN_TXBRP_TRP2_Pos)) -#define CAN_TXBRP_TRP3_Pos _U_(3) /**< (CAN_TXBRP) Transmission Request Pending 3 Position */ -#define CAN_TXBRP_TRP3_Msk (_U_(0x1) << CAN_TXBRP_TRP3_Pos) /**< (CAN_TXBRP) Transmission Request Pending 3 Mask */ -#define CAN_TXBRP_TRP3(value) (CAN_TXBRP_TRP3_Msk & ((value) << CAN_TXBRP_TRP3_Pos)) -#define CAN_TXBRP_TRP4_Pos _U_(4) /**< (CAN_TXBRP) Transmission Request Pending 4 Position */ -#define CAN_TXBRP_TRP4_Msk (_U_(0x1) << CAN_TXBRP_TRP4_Pos) /**< (CAN_TXBRP) Transmission Request Pending 4 Mask */ -#define CAN_TXBRP_TRP4(value) (CAN_TXBRP_TRP4_Msk & ((value) << CAN_TXBRP_TRP4_Pos)) -#define CAN_TXBRP_TRP5_Pos _U_(5) /**< (CAN_TXBRP) Transmission Request Pending 5 Position */ -#define CAN_TXBRP_TRP5_Msk (_U_(0x1) << CAN_TXBRP_TRP5_Pos) /**< (CAN_TXBRP) Transmission Request Pending 5 Mask */ -#define CAN_TXBRP_TRP5(value) (CAN_TXBRP_TRP5_Msk & ((value) << CAN_TXBRP_TRP5_Pos)) -#define CAN_TXBRP_TRP6_Pos _U_(6) /**< (CAN_TXBRP) Transmission Request Pending 6 Position */ -#define CAN_TXBRP_TRP6_Msk (_U_(0x1) << CAN_TXBRP_TRP6_Pos) /**< (CAN_TXBRP) Transmission Request Pending 6 Mask */ -#define CAN_TXBRP_TRP6(value) (CAN_TXBRP_TRP6_Msk & ((value) << CAN_TXBRP_TRP6_Pos)) -#define CAN_TXBRP_TRP7_Pos _U_(7) /**< (CAN_TXBRP) Transmission Request Pending 7 Position */ -#define CAN_TXBRP_TRP7_Msk (_U_(0x1) << CAN_TXBRP_TRP7_Pos) /**< (CAN_TXBRP) Transmission Request Pending 7 Mask */ -#define CAN_TXBRP_TRP7(value) (CAN_TXBRP_TRP7_Msk & ((value) << CAN_TXBRP_TRP7_Pos)) -#define CAN_TXBRP_TRP8_Pos _U_(8) /**< (CAN_TXBRP) Transmission Request Pending 8 Position */ -#define CAN_TXBRP_TRP8_Msk (_U_(0x1) << CAN_TXBRP_TRP8_Pos) /**< (CAN_TXBRP) Transmission Request Pending 8 Mask */ -#define CAN_TXBRP_TRP8(value) (CAN_TXBRP_TRP8_Msk & ((value) << CAN_TXBRP_TRP8_Pos)) -#define CAN_TXBRP_TRP9_Pos _U_(9) /**< (CAN_TXBRP) Transmission Request Pending 9 Position */ -#define CAN_TXBRP_TRP9_Msk (_U_(0x1) << CAN_TXBRP_TRP9_Pos) /**< (CAN_TXBRP) Transmission Request Pending 9 Mask */ -#define CAN_TXBRP_TRP9(value) (CAN_TXBRP_TRP9_Msk & ((value) << CAN_TXBRP_TRP9_Pos)) -#define CAN_TXBRP_TRP10_Pos _U_(10) /**< (CAN_TXBRP) Transmission Request Pending 10 Position */ -#define CAN_TXBRP_TRP10_Msk (_U_(0x1) << CAN_TXBRP_TRP10_Pos) /**< (CAN_TXBRP) Transmission Request Pending 10 Mask */ -#define CAN_TXBRP_TRP10(value) (CAN_TXBRP_TRP10_Msk & ((value) << CAN_TXBRP_TRP10_Pos)) -#define CAN_TXBRP_TRP11_Pos _U_(11) /**< (CAN_TXBRP) Transmission Request Pending 11 Position */ -#define CAN_TXBRP_TRP11_Msk (_U_(0x1) << CAN_TXBRP_TRP11_Pos) /**< (CAN_TXBRP) Transmission Request Pending 11 Mask */ -#define CAN_TXBRP_TRP11(value) (CAN_TXBRP_TRP11_Msk & ((value) << CAN_TXBRP_TRP11_Pos)) -#define CAN_TXBRP_TRP12_Pos _U_(12) /**< (CAN_TXBRP) Transmission Request Pending 12 Position */ -#define CAN_TXBRP_TRP12_Msk (_U_(0x1) << CAN_TXBRP_TRP12_Pos) /**< (CAN_TXBRP) Transmission Request Pending 12 Mask */ -#define CAN_TXBRP_TRP12(value) (CAN_TXBRP_TRP12_Msk & ((value) << CAN_TXBRP_TRP12_Pos)) -#define CAN_TXBRP_TRP13_Pos _U_(13) /**< (CAN_TXBRP) Transmission Request Pending 13 Position */ -#define CAN_TXBRP_TRP13_Msk (_U_(0x1) << CAN_TXBRP_TRP13_Pos) /**< (CAN_TXBRP) Transmission Request Pending 13 Mask */ -#define CAN_TXBRP_TRP13(value) (CAN_TXBRP_TRP13_Msk & ((value) << CAN_TXBRP_TRP13_Pos)) -#define CAN_TXBRP_TRP14_Pos _U_(14) /**< (CAN_TXBRP) Transmission Request Pending 14 Position */ -#define CAN_TXBRP_TRP14_Msk (_U_(0x1) << CAN_TXBRP_TRP14_Pos) /**< (CAN_TXBRP) Transmission Request Pending 14 Mask */ -#define CAN_TXBRP_TRP14(value) (CAN_TXBRP_TRP14_Msk & ((value) << CAN_TXBRP_TRP14_Pos)) -#define CAN_TXBRP_TRP15_Pos _U_(15) /**< (CAN_TXBRP) Transmission Request Pending 15 Position */ -#define CAN_TXBRP_TRP15_Msk (_U_(0x1) << CAN_TXBRP_TRP15_Pos) /**< (CAN_TXBRP) Transmission Request Pending 15 Mask */ -#define CAN_TXBRP_TRP15(value) (CAN_TXBRP_TRP15_Msk & ((value) << CAN_TXBRP_TRP15_Pos)) -#define CAN_TXBRP_TRP16_Pos _U_(16) /**< (CAN_TXBRP) Transmission Request Pending 16 Position */ -#define CAN_TXBRP_TRP16_Msk (_U_(0x1) << CAN_TXBRP_TRP16_Pos) /**< (CAN_TXBRP) Transmission Request Pending 16 Mask */ -#define CAN_TXBRP_TRP16(value) (CAN_TXBRP_TRP16_Msk & ((value) << CAN_TXBRP_TRP16_Pos)) -#define CAN_TXBRP_TRP17_Pos _U_(17) /**< (CAN_TXBRP) Transmission Request Pending 17 Position */ -#define CAN_TXBRP_TRP17_Msk (_U_(0x1) << CAN_TXBRP_TRP17_Pos) /**< (CAN_TXBRP) Transmission Request Pending 17 Mask */ -#define CAN_TXBRP_TRP17(value) (CAN_TXBRP_TRP17_Msk & ((value) << CAN_TXBRP_TRP17_Pos)) -#define CAN_TXBRP_TRP18_Pos _U_(18) /**< (CAN_TXBRP) Transmission Request Pending 18 Position */ -#define CAN_TXBRP_TRP18_Msk (_U_(0x1) << CAN_TXBRP_TRP18_Pos) /**< (CAN_TXBRP) Transmission Request Pending 18 Mask */ -#define CAN_TXBRP_TRP18(value) (CAN_TXBRP_TRP18_Msk & ((value) << CAN_TXBRP_TRP18_Pos)) -#define CAN_TXBRP_TRP19_Pos _U_(19) /**< (CAN_TXBRP) Transmission Request Pending 19 Position */ -#define CAN_TXBRP_TRP19_Msk (_U_(0x1) << CAN_TXBRP_TRP19_Pos) /**< (CAN_TXBRP) Transmission Request Pending 19 Mask */ -#define CAN_TXBRP_TRP19(value) (CAN_TXBRP_TRP19_Msk & ((value) << CAN_TXBRP_TRP19_Pos)) -#define CAN_TXBRP_TRP20_Pos _U_(20) /**< (CAN_TXBRP) Transmission Request Pending 20 Position */ -#define CAN_TXBRP_TRP20_Msk (_U_(0x1) << CAN_TXBRP_TRP20_Pos) /**< (CAN_TXBRP) Transmission Request Pending 20 Mask */ -#define CAN_TXBRP_TRP20(value) (CAN_TXBRP_TRP20_Msk & ((value) << CAN_TXBRP_TRP20_Pos)) -#define CAN_TXBRP_TRP21_Pos _U_(21) /**< (CAN_TXBRP) Transmission Request Pending 21 Position */ -#define CAN_TXBRP_TRP21_Msk (_U_(0x1) << CAN_TXBRP_TRP21_Pos) /**< (CAN_TXBRP) Transmission Request Pending 21 Mask */ -#define CAN_TXBRP_TRP21(value) (CAN_TXBRP_TRP21_Msk & ((value) << CAN_TXBRP_TRP21_Pos)) -#define CAN_TXBRP_TRP22_Pos _U_(22) /**< (CAN_TXBRP) Transmission Request Pending 22 Position */ -#define CAN_TXBRP_TRP22_Msk (_U_(0x1) << CAN_TXBRP_TRP22_Pos) /**< (CAN_TXBRP) Transmission Request Pending 22 Mask */ -#define CAN_TXBRP_TRP22(value) (CAN_TXBRP_TRP22_Msk & ((value) << CAN_TXBRP_TRP22_Pos)) -#define CAN_TXBRP_TRP23_Pos _U_(23) /**< (CAN_TXBRP) Transmission Request Pending 23 Position */ -#define CAN_TXBRP_TRP23_Msk (_U_(0x1) << CAN_TXBRP_TRP23_Pos) /**< (CAN_TXBRP) Transmission Request Pending 23 Mask */ -#define CAN_TXBRP_TRP23(value) (CAN_TXBRP_TRP23_Msk & ((value) << CAN_TXBRP_TRP23_Pos)) -#define CAN_TXBRP_TRP24_Pos _U_(24) /**< (CAN_TXBRP) Transmission Request Pending 24 Position */ -#define CAN_TXBRP_TRP24_Msk (_U_(0x1) << CAN_TXBRP_TRP24_Pos) /**< (CAN_TXBRP) Transmission Request Pending 24 Mask */ -#define CAN_TXBRP_TRP24(value) (CAN_TXBRP_TRP24_Msk & ((value) << CAN_TXBRP_TRP24_Pos)) -#define CAN_TXBRP_TRP25_Pos _U_(25) /**< (CAN_TXBRP) Transmission Request Pending 25 Position */ -#define CAN_TXBRP_TRP25_Msk (_U_(0x1) << CAN_TXBRP_TRP25_Pos) /**< (CAN_TXBRP) Transmission Request Pending 25 Mask */ -#define CAN_TXBRP_TRP25(value) (CAN_TXBRP_TRP25_Msk & ((value) << CAN_TXBRP_TRP25_Pos)) -#define CAN_TXBRP_TRP26_Pos _U_(26) /**< (CAN_TXBRP) Transmission Request Pending 26 Position */ -#define CAN_TXBRP_TRP26_Msk (_U_(0x1) << CAN_TXBRP_TRP26_Pos) /**< (CAN_TXBRP) Transmission Request Pending 26 Mask */ -#define CAN_TXBRP_TRP26(value) (CAN_TXBRP_TRP26_Msk & ((value) << CAN_TXBRP_TRP26_Pos)) -#define CAN_TXBRP_TRP27_Pos _U_(27) /**< (CAN_TXBRP) Transmission Request Pending 27 Position */ -#define CAN_TXBRP_TRP27_Msk (_U_(0x1) << CAN_TXBRP_TRP27_Pos) /**< (CAN_TXBRP) Transmission Request Pending 27 Mask */ -#define CAN_TXBRP_TRP27(value) (CAN_TXBRP_TRP27_Msk & ((value) << CAN_TXBRP_TRP27_Pos)) -#define CAN_TXBRP_TRP28_Pos _U_(28) /**< (CAN_TXBRP) Transmission Request Pending 28 Position */ -#define CAN_TXBRP_TRP28_Msk (_U_(0x1) << CAN_TXBRP_TRP28_Pos) /**< (CAN_TXBRP) Transmission Request Pending 28 Mask */ -#define CAN_TXBRP_TRP28(value) (CAN_TXBRP_TRP28_Msk & ((value) << CAN_TXBRP_TRP28_Pos)) -#define CAN_TXBRP_TRP29_Pos _U_(29) /**< (CAN_TXBRP) Transmission Request Pending 29 Position */ -#define CAN_TXBRP_TRP29_Msk (_U_(0x1) << CAN_TXBRP_TRP29_Pos) /**< (CAN_TXBRP) Transmission Request Pending 29 Mask */ -#define CAN_TXBRP_TRP29(value) (CAN_TXBRP_TRP29_Msk & ((value) << CAN_TXBRP_TRP29_Pos)) -#define CAN_TXBRP_TRP30_Pos _U_(30) /**< (CAN_TXBRP) Transmission Request Pending 30 Position */ -#define CAN_TXBRP_TRP30_Msk (_U_(0x1) << CAN_TXBRP_TRP30_Pos) /**< (CAN_TXBRP) Transmission Request Pending 30 Mask */ -#define CAN_TXBRP_TRP30(value) (CAN_TXBRP_TRP30_Msk & ((value) << CAN_TXBRP_TRP30_Pos)) -#define CAN_TXBRP_TRP31_Pos _U_(31) /**< (CAN_TXBRP) Transmission Request Pending 31 Position */ -#define CAN_TXBRP_TRP31_Msk (_U_(0x1) << CAN_TXBRP_TRP31_Pos) /**< (CAN_TXBRP) Transmission Request Pending 31 Mask */ -#define CAN_TXBRP_TRP31(value) (CAN_TXBRP_TRP31_Msk & ((value) << CAN_TXBRP_TRP31_Pos)) -#define CAN_TXBRP_Msk _U_(0xFFFFFFFF) /**< (CAN_TXBRP) Register Mask */ - -#define CAN_TXBRP_TRP_Pos _U_(0) /**< (CAN_TXBRP Position) Transmission Request Pending 3x */ -#define CAN_TXBRP_TRP_Msk (_U_(0xFFFFFFFF) << CAN_TXBRP_TRP_Pos) /**< (CAN_TXBRP Mask) TRP */ -#define CAN_TXBRP_TRP(value) (CAN_TXBRP_TRP_Msk & ((value) << CAN_TXBRP_TRP_Pos)) - -/* -------- CAN_TXBAR : (CAN Offset: 0xD0) (R/W 32) Tx Buffer Add Request -------- */ -#define CAN_TXBAR_RESETVALUE _U_(0x00) /**< (CAN_TXBAR) Tx Buffer Add Request Reset Value */ - -#define CAN_TXBAR_AR0_Pos _U_(0) /**< (CAN_TXBAR) Add Request 0 Position */ -#define CAN_TXBAR_AR0_Msk (_U_(0x1) << CAN_TXBAR_AR0_Pos) /**< (CAN_TXBAR) Add Request 0 Mask */ -#define CAN_TXBAR_AR0(value) (CAN_TXBAR_AR0_Msk & ((value) << CAN_TXBAR_AR0_Pos)) -#define CAN_TXBAR_AR1_Pos _U_(1) /**< (CAN_TXBAR) Add Request 1 Position */ -#define CAN_TXBAR_AR1_Msk (_U_(0x1) << CAN_TXBAR_AR1_Pos) /**< (CAN_TXBAR) Add Request 1 Mask */ -#define CAN_TXBAR_AR1(value) (CAN_TXBAR_AR1_Msk & ((value) << CAN_TXBAR_AR1_Pos)) -#define CAN_TXBAR_AR2_Pos _U_(2) /**< (CAN_TXBAR) Add Request 2 Position */ -#define CAN_TXBAR_AR2_Msk (_U_(0x1) << CAN_TXBAR_AR2_Pos) /**< (CAN_TXBAR) Add Request 2 Mask */ -#define CAN_TXBAR_AR2(value) (CAN_TXBAR_AR2_Msk & ((value) << CAN_TXBAR_AR2_Pos)) -#define CAN_TXBAR_AR3_Pos _U_(3) /**< (CAN_TXBAR) Add Request 3 Position */ -#define CAN_TXBAR_AR3_Msk (_U_(0x1) << CAN_TXBAR_AR3_Pos) /**< (CAN_TXBAR) Add Request 3 Mask */ -#define CAN_TXBAR_AR3(value) (CAN_TXBAR_AR3_Msk & ((value) << CAN_TXBAR_AR3_Pos)) -#define CAN_TXBAR_AR4_Pos _U_(4) /**< (CAN_TXBAR) Add Request 4 Position */ -#define CAN_TXBAR_AR4_Msk (_U_(0x1) << CAN_TXBAR_AR4_Pos) /**< (CAN_TXBAR) Add Request 4 Mask */ -#define CAN_TXBAR_AR4(value) (CAN_TXBAR_AR4_Msk & ((value) << CAN_TXBAR_AR4_Pos)) -#define CAN_TXBAR_AR5_Pos _U_(5) /**< (CAN_TXBAR) Add Request 5 Position */ -#define CAN_TXBAR_AR5_Msk (_U_(0x1) << CAN_TXBAR_AR5_Pos) /**< (CAN_TXBAR) Add Request 5 Mask */ -#define CAN_TXBAR_AR5(value) (CAN_TXBAR_AR5_Msk & ((value) << CAN_TXBAR_AR5_Pos)) -#define CAN_TXBAR_AR6_Pos _U_(6) /**< (CAN_TXBAR) Add Request 6 Position */ -#define CAN_TXBAR_AR6_Msk (_U_(0x1) << CAN_TXBAR_AR6_Pos) /**< (CAN_TXBAR) Add Request 6 Mask */ -#define CAN_TXBAR_AR6(value) (CAN_TXBAR_AR6_Msk & ((value) << CAN_TXBAR_AR6_Pos)) -#define CAN_TXBAR_AR7_Pos _U_(7) /**< (CAN_TXBAR) Add Request 7 Position */ -#define CAN_TXBAR_AR7_Msk (_U_(0x1) << CAN_TXBAR_AR7_Pos) /**< (CAN_TXBAR) Add Request 7 Mask */ -#define CAN_TXBAR_AR7(value) (CAN_TXBAR_AR7_Msk & ((value) << CAN_TXBAR_AR7_Pos)) -#define CAN_TXBAR_AR8_Pos _U_(8) /**< (CAN_TXBAR) Add Request 8 Position */ -#define CAN_TXBAR_AR8_Msk (_U_(0x1) << CAN_TXBAR_AR8_Pos) /**< (CAN_TXBAR) Add Request 8 Mask */ -#define CAN_TXBAR_AR8(value) (CAN_TXBAR_AR8_Msk & ((value) << CAN_TXBAR_AR8_Pos)) -#define CAN_TXBAR_AR9_Pos _U_(9) /**< (CAN_TXBAR) Add Request 9 Position */ -#define CAN_TXBAR_AR9_Msk (_U_(0x1) << CAN_TXBAR_AR9_Pos) /**< (CAN_TXBAR) Add Request 9 Mask */ -#define CAN_TXBAR_AR9(value) (CAN_TXBAR_AR9_Msk & ((value) << CAN_TXBAR_AR9_Pos)) -#define CAN_TXBAR_AR10_Pos _U_(10) /**< (CAN_TXBAR) Add Request 10 Position */ -#define CAN_TXBAR_AR10_Msk (_U_(0x1) << CAN_TXBAR_AR10_Pos) /**< (CAN_TXBAR) Add Request 10 Mask */ -#define CAN_TXBAR_AR10(value) (CAN_TXBAR_AR10_Msk & ((value) << CAN_TXBAR_AR10_Pos)) -#define CAN_TXBAR_AR11_Pos _U_(11) /**< (CAN_TXBAR) Add Request 11 Position */ -#define CAN_TXBAR_AR11_Msk (_U_(0x1) << CAN_TXBAR_AR11_Pos) /**< (CAN_TXBAR) Add Request 11 Mask */ -#define CAN_TXBAR_AR11(value) (CAN_TXBAR_AR11_Msk & ((value) << CAN_TXBAR_AR11_Pos)) -#define CAN_TXBAR_AR12_Pos _U_(12) /**< (CAN_TXBAR) Add Request 12 Position */ -#define CAN_TXBAR_AR12_Msk (_U_(0x1) << CAN_TXBAR_AR12_Pos) /**< (CAN_TXBAR) Add Request 12 Mask */ -#define CAN_TXBAR_AR12(value) (CAN_TXBAR_AR12_Msk & ((value) << CAN_TXBAR_AR12_Pos)) -#define CAN_TXBAR_AR13_Pos _U_(13) /**< (CAN_TXBAR) Add Request 13 Position */ -#define CAN_TXBAR_AR13_Msk (_U_(0x1) << CAN_TXBAR_AR13_Pos) /**< (CAN_TXBAR) Add Request 13 Mask */ -#define CAN_TXBAR_AR13(value) (CAN_TXBAR_AR13_Msk & ((value) << CAN_TXBAR_AR13_Pos)) -#define CAN_TXBAR_AR14_Pos _U_(14) /**< (CAN_TXBAR) Add Request 14 Position */ -#define CAN_TXBAR_AR14_Msk (_U_(0x1) << CAN_TXBAR_AR14_Pos) /**< (CAN_TXBAR) Add Request 14 Mask */ -#define CAN_TXBAR_AR14(value) (CAN_TXBAR_AR14_Msk & ((value) << CAN_TXBAR_AR14_Pos)) -#define CAN_TXBAR_AR15_Pos _U_(15) /**< (CAN_TXBAR) Add Request 15 Position */ -#define CAN_TXBAR_AR15_Msk (_U_(0x1) << CAN_TXBAR_AR15_Pos) /**< (CAN_TXBAR) Add Request 15 Mask */ -#define CAN_TXBAR_AR15(value) (CAN_TXBAR_AR15_Msk & ((value) << CAN_TXBAR_AR15_Pos)) -#define CAN_TXBAR_AR16_Pos _U_(16) /**< (CAN_TXBAR) Add Request 16 Position */ -#define CAN_TXBAR_AR16_Msk (_U_(0x1) << CAN_TXBAR_AR16_Pos) /**< (CAN_TXBAR) Add Request 16 Mask */ -#define CAN_TXBAR_AR16(value) (CAN_TXBAR_AR16_Msk & ((value) << CAN_TXBAR_AR16_Pos)) -#define CAN_TXBAR_AR17_Pos _U_(17) /**< (CAN_TXBAR) Add Request 17 Position */ -#define CAN_TXBAR_AR17_Msk (_U_(0x1) << CAN_TXBAR_AR17_Pos) /**< (CAN_TXBAR) Add Request 17 Mask */ -#define CAN_TXBAR_AR17(value) (CAN_TXBAR_AR17_Msk & ((value) << CAN_TXBAR_AR17_Pos)) -#define CAN_TXBAR_AR18_Pos _U_(18) /**< (CAN_TXBAR) Add Request 18 Position */ -#define CAN_TXBAR_AR18_Msk (_U_(0x1) << CAN_TXBAR_AR18_Pos) /**< (CAN_TXBAR) Add Request 18 Mask */ -#define CAN_TXBAR_AR18(value) (CAN_TXBAR_AR18_Msk & ((value) << CAN_TXBAR_AR18_Pos)) -#define CAN_TXBAR_AR19_Pos _U_(19) /**< (CAN_TXBAR) Add Request 19 Position */ -#define CAN_TXBAR_AR19_Msk (_U_(0x1) << CAN_TXBAR_AR19_Pos) /**< (CAN_TXBAR) Add Request 19 Mask */ -#define CAN_TXBAR_AR19(value) (CAN_TXBAR_AR19_Msk & ((value) << CAN_TXBAR_AR19_Pos)) -#define CAN_TXBAR_AR20_Pos _U_(20) /**< (CAN_TXBAR) Add Request 20 Position */ -#define CAN_TXBAR_AR20_Msk (_U_(0x1) << CAN_TXBAR_AR20_Pos) /**< (CAN_TXBAR) Add Request 20 Mask */ -#define CAN_TXBAR_AR20(value) (CAN_TXBAR_AR20_Msk & ((value) << CAN_TXBAR_AR20_Pos)) -#define CAN_TXBAR_AR21_Pos _U_(21) /**< (CAN_TXBAR) Add Request 21 Position */ -#define CAN_TXBAR_AR21_Msk (_U_(0x1) << CAN_TXBAR_AR21_Pos) /**< (CAN_TXBAR) Add Request 21 Mask */ -#define CAN_TXBAR_AR21(value) (CAN_TXBAR_AR21_Msk & ((value) << CAN_TXBAR_AR21_Pos)) -#define CAN_TXBAR_AR22_Pos _U_(22) /**< (CAN_TXBAR) Add Request 22 Position */ -#define CAN_TXBAR_AR22_Msk (_U_(0x1) << CAN_TXBAR_AR22_Pos) /**< (CAN_TXBAR) Add Request 22 Mask */ -#define CAN_TXBAR_AR22(value) (CAN_TXBAR_AR22_Msk & ((value) << CAN_TXBAR_AR22_Pos)) -#define CAN_TXBAR_AR23_Pos _U_(23) /**< (CAN_TXBAR) Add Request 23 Position */ -#define CAN_TXBAR_AR23_Msk (_U_(0x1) << CAN_TXBAR_AR23_Pos) /**< (CAN_TXBAR) Add Request 23 Mask */ -#define CAN_TXBAR_AR23(value) (CAN_TXBAR_AR23_Msk & ((value) << CAN_TXBAR_AR23_Pos)) -#define CAN_TXBAR_AR24_Pos _U_(24) /**< (CAN_TXBAR) Add Request 24 Position */ -#define CAN_TXBAR_AR24_Msk (_U_(0x1) << CAN_TXBAR_AR24_Pos) /**< (CAN_TXBAR) Add Request 24 Mask */ -#define CAN_TXBAR_AR24(value) (CAN_TXBAR_AR24_Msk & ((value) << CAN_TXBAR_AR24_Pos)) -#define CAN_TXBAR_AR25_Pos _U_(25) /**< (CAN_TXBAR) Add Request 25 Position */ -#define CAN_TXBAR_AR25_Msk (_U_(0x1) << CAN_TXBAR_AR25_Pos) /**< (CAN_TXBAR) Add Request 25 Mask */ -#define CAN_TXBAR_AR25(value) (CAN_TXBAR_AR25_Msk & ((value) << CAN_TXBAR_AR25_Pos)) -#define CAN_TXBAR_AR26_Pos _U_(26) /**< (CAN_TXBAR) Add Request 26 Position */ -#define CAN_TXBAR_AR26_Msk (_U_(0x1) << CAN_TXBAR_AR26_Pos) /**< (CAN_TXBAR) Add Request 26 Mask */ -#define CAN_TXBAR_AR26(value) (CAN_TXBAR_AR26_Msk & ((value) << CAN_TXBAR_AR26_Pos)) -#define CAN_TXBAR_AR27_Pos _U_(27) /**< (CAN_TXBAR) Add Request 27 Position */ -#define CAN_TXBAR_AR27_Msk (_U_(0x1) << CAN_TXBAR_AR27_Pos) /**< (CAN_TXBAR) Add Request 27 Mask */ -#define CAN_TXBAR_AR27(value) (CAN_TXBAR_AR27_Msk & ((value) << CAN_TXBAR_AR27_Pos)) -#define CAN_TXBAR_AR28_Pos _U_(28) /**< (CAN_TXBAR) Add Request 28 Position */ -#define CAN_TXBAR_AR28_Msk (_U_(0x1) << CAN_TXBAR_AR28_Pos) /**< (CAN_TXBAR) Add Request 28 Mask */ -#define CAN_TXBAR_AR28(value) (CAN_TXBAR_AR28_Msk & ((value) << CAN_TXBAR_AR28_Pos)) -#define CAN_TXBAR_AR29_Pos _U_(29) /**< (CAN_TXBAR) Add Request 29 Position */ -#define CAN_TXBAR_AR29_Msk (_U_(0x1) << CAN_TXBAR_AR29_Pos) /**< (CAN_TXBAR) Add Request 29 Mask */ -#define CAN_TXBAR_AR29(value) (CAN_TXBAR_AR29_Msk & ((value) << CAN_TXBAR_AR29_Pos)) -#define CAN_TXBAR_AR30_Pos _U_(30) /**< (CAN_TXBAR) Add Request 30 Position */ -#define CAN_TXBAR_AR30_Msk (_U_(0x1) << CAN_TXBAR_AR30_Pos) /**< (CAN_TXBAR) Add Request 30 Mask */ -#define CAN_TXBAR_AR30(value) (CAN_TXBAR_AR30_Msk & ((value) << CAN_TXBAR_AR30_Pos)) -#define CAN_TXBAR_AR31_Pos _U_(31) /**< (CAN_TXBAR) Add Request 31 Position */ -#define CAN_TXBAR_AR31_Msk (_U_(0x1) << CAN_TXBAR_AR31_Pos) /**< (CAN_TXBAR) Add Request 31 Mask */ -#define CAN_TXBAR_AR31(value) (CAN_TXBAR_AR31_Msk & ((value) << CAN_TXBAR_AR31_Pos)) -#define CAN_TXBAR_Msk _U_(0xFFFFFFFF) /**< (CAN_TXBAR) Register Mask */ - -#define CAN_TXBAR_AR_Pos _U_(0) /**< (CAN_TXBAR Position) Add Request 3x */ -#define CAN_TXBAR_AR_Msk (_U_(0xFFFFFFFF) << CAN_TXBAR_AR_Pos) /**< (CAN_TXBAR Mask) AR */ -#define CAN_TXBAR_AR(value) (CAN_TXBAR_AR_Msk & ((value) << CAN_TXBAR_AR_Pos)) - -/* -------- CAN_TXBCR : (CAN Offset: 0xD4) (R/W 32) Tx Buffer Cancellation Request -------- */ -#define CAN_TXBCR_RESETVALUE _U_(0x00) /**< (CAN_TXBCR) Tx Buffer Cancellation Request Reset Value */ - -#define CAN_TXBCR_CR0_Pos _U_(0) /**< (CAN_TXBCR) Cancellation Request 0 Position */ -#define CAN_TXBCR_CR0_Msk (_U_(0x1) << CAN_TXBCR_CR0_Pos) /**< (CAN_TXBCR) Cancellation Request 0 Mask */ -#define CAN_TXBCR_CR0(value) (CAN_TXBCR_CR0_Msk & ((value) << CAN_TXBCR_CR0_Pos)) -#define CAN_TXBCR_CR1_Pos _U_(1) /**< (CAN_TXBCR) Cancellation Request 1 Position */ -#define CAN_TXBCR_CR1_Msk (_U_(0x1) << CAN_TXBCR_CR1_Pos) /**< (CAN_TXBCR) Cancellation Request 1 Mask */ -#define CAN_TXBCR_CR1(value) (CAN_TXBCR_CR1_Msk & ((value) << CAN_TXBCR_CR1_Pos)) -#define CAN_TXBCR_CR2_Pos _U_(2) /**< (CAN_TXBCR) Cancellation Request 2 Position */ -#define CAN_TXBCR_CR2_Msk (_U_(0x1) << CAN_TXBCR_CR2_Pos) /**< (CAN_TXBCR) Cancellation Request 2 Mask */ -#define CAN_TXBCR_CR2(value) (CAN_TXBCR_CR2_Msk & ((value) << CAN_TXBCR_CR2_Pos)) -#define CAN_TXBCR_CR3_Pos _U_(3) /**< (CAN_TXBCR) Cancellation Request 3 Position */ -#define CAN_TXBCR_CR3_Msk (_U_(0x1) << CAN_TXBCR_CR3_Pos) /**< (CAN_TXBCR) Cancellation Request 3 Mask */ -#define CAN_TXBCR_CR3(value) (CAN_TXBCR_CR3_Msk & ((value) << CAN_TXBCR_CR3_Pos)) -#define CAN_TXBCR_CR4_Pos _U_(4) /**< (CAN_TXBCR) Cancellation Request 4 Position */ -#define CAN_TXBCR_CR4_Msk (_U_(0x1) << CAN_TXBCR_CR4_Pos) /**< (CAN_TXBCR) Cancellation Request 4 Mask */ -#define CAN_TXBCR_CR4(value) (CAN_TXBCR_CR4_Msk & ((value) << CAN_TXBCR_CR4_Pos)) -#define CAN_TXBCR_CR5_Pos _U_(5) /**< (CAN_TXBCR) Cancellation Request 5 Position */ -#define CAN_TXBCR_CR5_Msk (_U_(0x1) << CAN_TXBCR_CR5_Pos) /**< (CAN_TXBCR) Cancellation Request 5 Mask */ -#define CAN_TXBCR_CR5(value) (CAN_TXBCR_CR5_Msk & ((value) << CAN_TXBCR_CR5_Pos)) -#define CAN_TXBCR_CR6_Pos _U_(6) /**< (CAN_TXBCR) Cancellation Request 6 Position */ -#define CAN_TXBCR_CR6_Msk (_U_(0x1) << CAN_TXBCR_CR6_Pos) /**< (CAN_TXBCR) Cancellation Request 6 Mask */ -#define CAN_TXBCR_CR6(value) (CAN_TXBCR_CR6_Msk & ((value) << CAN_TXBCR_CR6_Pos)) -#define CAN_TXBCR_CR7_Pos _U_(7) /**< (CAN_TXBCR) Cancellation Request 7 Position */ -#define CAN_TXBCR_CR7_Msk (_U_(0x1) << CAN_TXBCR_CR7_Pos) /**< (CAN_TXBCR) Cancellation Request 7 Mask */ -#define CAN_TXBCR_CR7(value) (CAN_TXBCR_CR7_Msk & ((value) << CAN_TXBCR_CR7_Pos)) -#define CAN_TXBCR_CR8_Pos _U_(8) /**< (CAN_TXBCR) Cancellation Request 8 Position */ -#define CAN_TXBCR_CR8_Msk (_U_(0x1) << CAN_TXBCR_CR8_Pos) /**< (CAN_TXBCR) Cancellation Request 8 Mask */ -#define CAN_TXBCR_CR8(value) (CAN_TXBCR_CR8_Msk & ((value) << CAN_TXBCR_CR8_Pos)) -#define CAN_TXBCR_CR9_Pos _U_(9) /**< (CAN_TXBCR) Cancellation Request 9 Position */ -#define CAN_TXBCR_CR9_Msk (_U_(0x1) << CAN_TXBCR_CR9_Pos) /**< (CAN_TXBCR) Cancellation Request 9 Mask */ -#define CAN_TXBCR_CR9(value) (CAN_TXBCR_CR9_Msk & ((value) << CAN_TXBCR_CR9_Pos)) -#define CAN_TXBCR_CR10_Pos _U_(10) /**< (CAN_TXBCR) Cancellation Request 10 Position */ -#define CAN_TXBCR_CR10_Msk (_U_(0x1) << CAN_TXBCR_CR10_Pos) /**< (CAN_TXBCR) Cancellation Request 10 Mask */ -#define CAN_TXBCR_CR10(value) (CAN_TXBCR_CR10_Msk & ((value) << CAN_TXBCR_CR10_Pos)) -#define CAN_TXBCR_CR11_Pos _U_(11) /**< (CAN_TXBCR) Cancellation Request 11 Position */ -#define CAN_TXBCR_CR11_Msk (_U_(0x1) << CAN_TXBCR_CR11_Pos) /**< (CAN_TXBCR) Cancellation Request 11 Mask */ -#define CAN_TXBCR_CR11(value) (CAN_TXBCR_CR11_Msk & ((value) << CAN_TXBCR_CR11_Pos)) -#define CAN_TXBCR_CR12_Pos _U_(12) /**< (CAN_TXBCR) Cancellation Request 12 Position */ -#define CAN_TXBCR_CR12_Msk (_U_(0x1) << CAN_TXBCR_CR12_Pos) /**< (CAN_TXBCR) Cancellation Request 12 Mask */ -#define CAN_TXBCR_CR12(value) (CAN_TXBCR_CR12_Msk & ((value) << CAN_TXBCR_CR12_Pos)) -#define CAN_TXBCR_CR13_Pos _U_(13) /**< (CAN_TXBCR) Cancellation Request 13 Position */ -#define CAN_TXBCR_CR13_Msk (_U_(0x1) << CAN_TXBCR_CR13_Pos) /**< (CAN_TXBCR) Cancellation Request 13 Mask */ -#define CAN_TXBCR_CR13(value) (CAN_TXBCR_CR13_Msk & ((value) << CAN_TXBCR_CR13_Pos)) -#define CAN_TXBCR_CR14_Pos _U_(14) /**< (CAN_TXBCR) Cancellation Request 14 Position */ -#define CAN_TXBCR_CR14_Msk (_U_(0x1) << CAN_TXBCR_CR14_Pos) /**< (CAN_TXBCR) Cancellation Request 14 Mask */ -#define CAN_TXBCR_CR14(value) (CAN_TXBCR_CR14_Msk & ((value) << CAN_TXBCR_CR14_Pos)) -#define CAN_TXBCR_CR15_Pos _U_(15) /**< (CAN_TXBCR) Cancellation Request 15 Position */ -#define CAN_TXBCR_CR15_Msk (_U_(0x1) << CAN_TXBCR_CR15_Pos) /**< (CAN_TXBCR) Cancellation Request 15 Mask */ -#define CAN_TXBCR_CR15(value) (CAN_TXBCR_CR15_Msk & ((value) << CAN_TXBCR_CR15_Pos)) -#define CAN_TXBCR_CR16_Pos _U_(16) /**< (CAN_TXBCR) Cancellation Request 16 Position */ -#define CAN_TXBCR_CR16_Msk (_U_(0x1) << CAN_TXBCR_CR16_Pos) /**< (CAN_TXBCR) Cancellation Request 16 Mask */ -#define CAN_TXBCR_CR16(value) (CAN_TXBCR_CR16_Msk & ((value) << CAN_TXBCR_CR16_Pos)) -#define CAN_TXBCR_CR17_Pos _U_(17) /**< (CAN_TXBCR) Cancellation Request 17 Position */ -#define CAN_TXBCR_CR17_Msk (_U_(0x1) << CAN_TXBCR_CR17_Pos) /**< (CAN_TXBCR) Cancellation Request 17 Mask */ -#define CAN_TXBCR_CR17(value) (CAN_TXBCR_CR17_Msk & ((value) << CAN_TXBCR_CR17_Pos)) -#define CAN_TXBCR_CR18_Pos _U_(18) /**< (CAN_TXBCR) Cancellation Request 18 Position */ -#define CAN_TXBCR_CR18_Msk (_U_(0x1) << CAN_TXBCR_CR18_Pos) /**< (CAN_TXBCR) Cancellation Request 18 Mask */ -#define CAN_TXBCR_CR18(value) (CAN_TXBCR_CR18_Msk & ((value) << CAN_TXBCR_CR18_Pos)) -#define CAN_TXBCR_CR19_Pos _U_(19) /**< (CAN_TXBCR) Cancellation Request 19 Position */ -#define CAN_TXBCR_CR19_Msk (_U_(0x1) << CAN_TXBCR_CR19_Pos) /**< (CAN_TXBCR) Cancellation Request 19 Mask */ -#define CAN_TXBCR_CR19(value) (CAN_TXBCR_CR19_Msk & ((value) << CAN_TXBCR_CR19_Pos)) -#define CAN_TXBCR_CR20_Pos _U_(20) /**< (CAN_TXBCR) Cancellation Request 20 Position */ -#define CAN_TXBCR_CR20_Msk (_U_(0x1) << CAN_TXBCR_CR20_Pos) /**< (CAN_TXBCR) Cancellation Request 20 Mask */ -#define CAN_TXBCR_CR20(value) (CAN_TXBCR_CR20_Msk & ((value) << CAN_TXBCR_CR20_Pos)) -#define CAN_TXBCR_CR21_Pos _U_(21) /**< (CAN_TXBCR) Cancellation Request 21 Position */ -#define CAN_TXBCR_CR21_Msk (_U_(0x1) << CAN_TXBCR_CR21_Pos) /**< (CAN_TXBCR) Cancellation Request 21 Mask */ -#define CAN_TXBCR_CR21(value) (CAN_TXBCR_CR21_Msk & ((value) << CAN_TXBCR_CR21_Pos)) -#define CAN_TXBCR_CR22_Pos _U_(22) /**< (CAN_TXBCR) Cancellation Request 22 Position */ -#define CAN_TXBCR_CR22_Msk (_U_(0x1) << CAN_TXBCR_CR22_Pos) /**< (CAN_TXBCR) Cancellation Request 22 Mask */ -#define CAN_TXBCR_CR22(value) (CAN_TXBCR_CR22_Msk & ((value) << CAN_TXBCR_CR22_Pos)) -#define CAN_TXBCR_CR23_Pos _U_(23) /**< (CAN_TXBCR) Cancellation Request 23 Position */ -#define CAN_TXBCR_CR23_Msk (_U_(0x1) << CAN_TXBCR_CR23_Pos) /**< (CAN_TXBCR) Cancellation Request 23 Mask */ -#define CAN_TXBCR_CR23(value) (CAN_TXBCR_CR23_Msk & ((value) << CAN_TXBCR_CR23_Pos)) -#define CAN_TXBCR_CR24_Pos _U_(24) /**< (CAN_TXBCR) Cancellation Request 24 Position */ -#define CAN_TXBCR_CR24_Msk (_U_(0x1) << CAN_TXBCR_CR24_Pos) /**< (CAN_TXBCR) Cancellation Request 24 Mask */ -#define CAN_TXBCR_CR24(value) (CAN_TXBCR_CR24_Msk & ((value) << CAN_TXBCR_CR24_Pos)) -#define CAN_TXBCR_CR25_Pos _U_(25) /**< (CAN_TXBCR) Cancellation Request 25 Position */ -#define CAN_TXBCR_CR25_Msk (_U_(0x1) << CAN_TXBCR_CR25_Pos) /**< (CAN_TXBCR) Cancellation Request 25 Mask */ -#define CAN_TXBCR_CR25(value) (CAN_TXBCR_CR25_Msk & ((value) << CAN_TXBCR_CR25_Pos)) -#define CAN_TXBCR_CR26_Pos _U_(26) /**< (CAN_TXBCR) Cancellation Request 26 Position */ -#define CAN_TXBCR_CR26_Msk (_U_(0x1) << CAN_TXBCR_CR26_Pos) /**< (CAN_TXBCR) Cancellation Request 26 Mask */ -#define CAN_TXBCR_CR26(value) (CAN_TXBCR_CR26_Msk & ((value) << CAN_TXBCR_CR26_Pos)) -#define CAN_TXBCR_CR27_Pos _U_(27) /**< (CAN_TXBCR) Cancellation Request 27 Position */ -#define CAN_TXBCR_CR27_Msk (_U_(0x1) << CAN_TXBCR_CR27_Pos) /**< (CAN_TXBCR) Cancellation Request 27 Mask */ -#define CAN_TXBCR_CR27(value) (CAN_TXBCR_CR27_Msk & ((value) << CAN_TXBCR_CR27_Pos)) -#define CAN_TXBCR_CR28_Pos _U_(28) /**< (CAN_TXBCR) Cancellation Request 28 Position */ -#define CAN_TXBCR_CR28_Msk (_U_(0x1) << CAN_TXBCR_CR28_Pos) /**< (CAN_TXBCR) Cancellation Request 28 Mask */ -#define CAN_TXBCR_CR28(value) (CAN_TXBCR_CR28_Msk & ((value) << CAN_TXBCR_CR28_Pos)) -#define CAN_TXBCR_CR29_Pos _U_(29) /**< (CAN_TXBCR) Cancellation Request 29 Position */ -#define CAN_TXBCR_CR29_Msk (_U_(0x1) << CAN_TXBCR_CR29_Pos) /**< (CAN_TXBCR) Cancellation Request 29 Mask */ -#define CAN_TXBCR_CR29(value) (CAN_TXBCR_CR29_Msk & ((value) << CAN_TXBCR_CR29_Pos)) -#define CAN_TXBCR_CR30_Pos _U_(30) /**< (CAN_TXBCR) Cancellation Request 30 Position */ -#define CAN_TXBCR_CR30_Msk (_U_(0x1) << CAN_TXBCR_CR30_Pos) /**< (CAN_TXBCR) Cancellation Request 30 Mask */ -#define CAN_TXBCR_CR30(value) (CAN_TXBCR_CR30_Msk & ((value) << CAN_TXBCR_CR30_Pos)) -#define CAN_TXBCR_CR31_Pos _U_(31) /**< (CAN_TXBCR) Cancellation Request 31 Position */ -#define CAN_TXBCR_CR31_Msk (_U_(0x1) << CAN_TXBCR_CR31_Pos) /**< (CAN_TXBCR) Cancellation Request 31 Mask */ -#define CAN_TXBCR_CR31(value) (CAN_TXBCR_CR31_Msk & ((value) << CAN_TXBCR_CR31_Pos)) -#define CAN_TXBCR_Msk _U_(0xFFFFFFFF) /**< (CAN_TXBCR) Register Mask */ - -#define CAN_TXBCR_CR_Pos _U_(0) /**< (CAN_TXBCR Position) Cancellation Request 3x */ -#define CAN_TXBCR_CR_Msk (_U_(0xFFFFFFFF) << CAN_TXBCR_CR_Pos) /**< (CAN_TXBCR Mask) CR */ -#define CAN_TXBCR_CR(value) (CAN_TXBCR_CR_Msk & ((value) << CAN_TXBCR_CR_Pos)) - -/* -------- CAN_TXBTO : (CAN Offset: 0xD8) ( R/ 32) Tx Buffer Transmission Occurred -------- */ -#define CAN_TXBTO_RESETVALUE _U_(0x00) /**< (CAN_TXBTO) Tx Buffer Transmission Occurred Reset Value */ - -#define CAN_TXBTO_TO0_Pos _U_(0) /**< (CAN_TXBTO) Transmission Occurred 0 Position */ -#define CAN_TXBTO_TO0_Msk (_U_(0x1) << CAN_TXBTO_TO0_Pos) /**< (CAN_TXBTO) Transmission Occurred 0 Mask */ -#define CAN_TXBTO_TO0(value) (CAN_TXBTO_TO0_Msk & ((value) << CAN_TXBTO_TO0_Pos)) -#define CAN_TXBTO_TO1_Pos _U_(1) /**< (CAN_TXBTO) Transmission Occurred 1 Position */ -#define CAN_TXBTO_TO1_Msk (_U_(0x1) << CAN_TXBTO_TO1_Pos) /**< (CAN_TXBTO) Transmission Occurred 1 Mask */ -#define CAN_TXBTO_TO1(value) (CAN_TXBTO_TO1_Msk & ((value) << CAN_TXBTO_TO1_Pos)) -#define CAN_TXBTO_TO2_Pos _U_(2) /**< (CAN_TXBTO) Transmission Occurred 2 Position */ -#define CAN_TXBTO_TO2_Msk (_U_(0x1) << CAN_TXBTO_TO2_Pos) /**< (CAN_TXBTO) Transmission Occurred 2 Mask */ -#define CAN_TXBTO_TO2(value) (CAN_TXBTO_TO2_Msk & ((value) << CAN_TXBTO_TO2_Pos)) -#define CAN_TXBTO_TO3_Pos _U_(3) /**< (CAN_TXBTO) Transmission Occurred 3 Position */ -#define CAN_TXBTO_TO3_Msk (_U_(0x1) << CAN_TXBTO_TO3_Pos) /**< (CAN_TXBTO) Transmission Occurred 3 Mask */ -#define CAN_TXBTO_TO3(value) (CAN_TXBTO_TO3_Msk & ((value) << CAN_TXBTO_TO3_Pos)) -#define CAN_TXBTO_TO4_Pos _U_(4) /**< (CAN_TXBTO) Transmission Occurred 4 Position */ -#define CAN_TXBTO_TO4_Msk (_U_(0x1) << CAN_TXBTO_TO4_Pos) /**< (CAN_TXBTO) Transmission Occurred 4 Mask */ -#define CAN_TXBTO_TO4(value) (CAN_TXBTO_TO4_Msk & ((value) << CAN_TXBTO_TO4_Pos)) -#define CAN_TXBTO_TO5_Pos _U_(5) /**< (CAN_TXBTO) Transmission Occurred 5 Position */ -#define CAN_TXBTO_TO5_Msk (_U_(0x1) << CAN_TXBTO_TO5_Pos) /**< (CAN_TXBTO) Transmission Occurred 5 Mask */ -#define CAN_TXBTO_TO5(value) (CAN_TXBTO_TO5_Msk & ((value) << CAN_TXBTO_TO5_Pos)) -#define CAN_TXBTO_TO6_Pos _U_(6) /**< (CAN_TXBTO) Transmission Occurred 6 Position */ -#define CAN_TXBTO_TO6_Msk (_U_(0x1) << CAN_TXBTO_TO6_Pos) /**< (CAN_TXBTO) Transmission Occurred 6 Mask */ -#define CAN_TXBTO_TO6(value) (CAN_TXBTO_TO6_Msk & ((value) << CAN_TXBTO_TO6_Pos)) -#define CAN_TXBTO_TO7_Pos _U_(7) /**< (CAN_TXBTO) Transmission Occurred 7 Position */ -#define CAN_TXBTO_TO7_Msk (_U_(0x1) << CAN_TXBTO_TO7_Pos) /**< (CAN_TXBTO) Transmission Occurred 7 Mask */ -#define CAN_TXBTO_TO7(value) (CAN_TXBTO_TO7_Msk & ((value) << CAN_TXBTO_TO7_Pos)) -#define CAN_TXBTO_TO8_Pos _U_(8) /**< (CAN_TXBTO) Transmission Occurred 8 Position */ -#define CAN_TXBTO_TO8_Msk (_U_(0x1) << CAN_TXBTO_TO8_Pos) /**< (CAN_TXBTO) Transmission Occurred 8 Mask */ -#define CAN_TXBTO_TO8(value) (CAN_TXBTO_TO8_Msk & ((value) << CAN_TXBTO_TO8_Pos)) -#define CAN_TXBTO_TO9_Pos _U_(9) /**< (CAN_TXBTO) Transmission Occurred 9 Position */ -#define CAN_TXBTO_TO9_Msk (_U_(0x1) << CAN_TXBTO_TO9_Pos) /**< (CAN_TXBTO) Transmission Occurred 9 Mask */ -#define CAN_TXBTO_TO9(value) (CAN_TXBTO_TO9_Msk & ((value) << CAN_TXBTO_TO9_Pos)) -#define CAN_TXBTO_TO10_Pos _U_(10) /**< (CAN_TXBTO) Transmission Occurred 10 Position */ -#define CAN_TXBTO_TO10_Msk (_U_(0x1) << CAN_TXBTO_TO10_Pos) /**< (CAN_TXBTO) Transmission Occurred 10 Mask */ -#define CAN_TXBTO_TO10(value) (CAN_TXBTO_TO10_Msk & ((value) << CAN_TXBTO_TO10_Pos)) -#define CAN_TXBTO_TO11_Pos _U_(11) /**< (CAN_TXBTO) Transmission Occurred 11 Position */ -#define CAN_TXBTO_TO11_Msk (_U_(0x1) << CAN_TXBTO_TO11_Pos) /**< (CAN_TXBTO) Transmission Occurred 11 Mask */ -#define CAN_TXBTO_TO11(value) (CAN_TXBTO_TO11_Msk & ((value) << CAN_TXBTO_TO11_Pos)) -#define CAN_TXBTO_TO12_Pos _U_(12) /**< (CAN_TXBTO) Transmission Occurred 12 Position */ -#define CAN_TXBTO_TO12_Msk (_U_(0x1) << CAN_TXBTO_TO12_Pos) /**< (CAN_TXBTO) Transmission Occurred 12 Mask */ -#define CAN_TXBTO_TO12(value) (CAN_TXBTO_TO12_Msk & ((value) << CAN_TXBTO_TO12_Pos)) -#define CAN_TXBTO_TO13_Pos _U_(13) /**< (CAN_TXBTO) Transmission Occurred 13 Position */ -#define CAN_TXBTO_TO13_Msk (_U_(0x1) << CAN_TXBTO_TO13_Pos) /**< (CAN_TXBTO) Transmission Occurred 13 Mask */ -#define CAN_TXBTO_TO13(value) (CAN_TXBTO_TO13_Msk & ((value) << CAN_TXBTO_TO13_Pos)) -#define CAN_TXBTO_TO14_Pos _U_(14) /**< (CAN_TXBTO) Transmission Occurred 14 Position */ -#define CAN_TXBTO_TO14_Msk (_U_(0x1) << CAN_TXBTO_TO14_Pos) /**< (CAN_TXBTO) Transmission Occurred 14 Mask */ -#define CAN_TXBTO_TO14(value) (CAN_TXBTO_TO14_Msk & ((value) << CAN_TXBTO_TO14_Pos)) -#define CAN_TXBTO_TO15_Pos _U_(15) /**< (CAN_TXBTO) Transmission Occurred 15 Position */ -#define CAN_TXBTO_TO15_Msk (_U_(0x1) << CAN_TXBTO_TO15_Pos) /**< (CAN_TXBTO) Transmission Occurred 15 Mask */ -#define CAN_TXBTO_TO15(value) (CAN_TXBTO_TO15_Msk & ((value) << CAN_TXBTO_TO15_Pos)) -#define CAN_TXBTO_TO16_Pos _U_(16) /**< (CAN_TXBTO) Transmission Occurred 16 Position */ -#define CAN_TXBTO_TO16_Msk (_U_(0x1) << CAN_TXBTO_TO16_Pos) /**< (CAN_TXBTO) Transmission Occurred 16 Mask */ -#define CAN_TXBTO_TO16(value) (CAN_TXBTO_TO16_Msk & ((value) << CAN_TXBTO_TO16_Pos)) -#define CAN_TXBTO_TO17_Pos _U_(17) /**< (CAN_TXBTO) Transmission Occurred 17 Position */ -#define CAN_TXBTO_TO17_Msk (_U_(0x1) << CAN_TXBTO_TO17_Pos) /**< (CAN_TXBTO) Transmission Occurred 17 Mask */ -#define CAN_TXBTO_TO17(value) (CAN_TXBTO_TO17_Msk & ((value) << CAN_TXBTO_TO17_Pos)) -#define CAN_TXBTO_TO18_Pos _U_(18) /**< (CAN_TXBTO) Transmission Occurred 18 Position */ -#define CAN_TXBTO_TO18_Msk (_U_(0x1) << CAN_TXBTO_TO18_Pos) /**< (CAN_TXBTO) Transmission Occurred 18 Mask */ -#define CAN_TXBTO_TO18(value) (CAN_TXBTO_TO18_Msk & ((value) << CAN_TXBTO_TO18_Pos)) -#define CAN_TXBTO_TO19_Pos _U_(19) /**< (CAN_TXBTO) Transmission Occurred 19 Position */ -#define CAN_TXBTO_TO19_Msk (_U_(0x1) << CAN_TXBTO_TO19_Pos) /**< (CAN_TXBTO) Transmission Occurred 19 Mask */ -#define CAN_TXBTO_TO19(value) (CAN_TXBTO_TO19_Msk & ((value) << CAN_TXBTO_TO19_Pos)) -#define CAN_TXBTO_TO20_Pos _U_(20) /**< (CAN_TXBTO) Transmission Occurred 20 Position */ -#define CAN_TXBTO_TO20_Msk (_U_(0x1) << CAN_TXBTO_TO20_Pos) /**< (CAN_TXBTO) Transmission Occurred 20 Mask */ -#define CAN_TXBTO_TO20(value) (CAN_TXBTO_TO20_Msk & ((value) << CAN_TXBTO_TO20_Pos)) -#define CAN_TXBTO_TO21_Pos _U_(21) /**< (CAN_TXBTO) Transmission Occurred 21 Position */ -#define CAN_TXBTO_TO21_Msk (_U_(0x1) << CAN_TXBTO_TO21_Pos) /**< (CAN_TXBTO) Transmission Occurred 21 Mask */ -#define CAN_TXBTO_TO21(value) (CAN_TXBTO_TO21_Msk & ((value) << CAN_TXBTO_TO21_Pos)) -#define CAN_TXBTO_TO22_Pos _U_(22) /**< (CAN_TXBTO) Transmission Occurred 22 Position */ -#define CAN_TXBTO_TO22_Msk (_U_(0x1) << CAN_TXBTO_TO22_Pos) /**< (CAN_TXBTO) Transmission Occurred 22 Mask */ -#define CAN_TXBTO_TO22(value) (CAN_TXBTO_TO22_Msk & ((value) << CAN_TXBTO_TO22_Pos)) -#define CAN_TXBTO_TO23_Pos _U_(23) /**< (CAN_TXBTO) Transmission Occurred 23 Position */ -#define CAN_TXBTO_TO23_Msk (_U_(0x1) << CAN_TXBTO_TO23_Pos) /**< (CAN_TXBTO) Transmission Occurred 23 Mask */ -#define CAN_TXBTO_TO23(value) (CAN_TXBTO_TO23_Msk & ((value) << CAN_TXBTO_TO23_Pos)) -#define CAN_TXBTO_TO24_Pos _U_(24) /**< (CAN_TXBTO) Transmission Occurred 24 Position */ -#define CAN_TXBTO_TO24_Msk (_U_(0x1) << CAN_TXBTO_TO24_Pos) /**< (CAN_TXBTO) Transmission Occurred 24 Mask */ -#define CAN_TXBTO_TO24(value) (CAN_TXBTO_TO24_Msk & ((value) << CAN_TXBTO_TO24_Pos)) -#define CAN_TXBTO_TO25_Pos _U_(25) /**< (CAN_TXBTO) Transmission Occurred 25 Position */ -#define CAN_TXBTO_TO25_Msk (_U_(0x1) << CAN_TXBTO_TO25_Pos) /**< (CAN_TXBTO) Transmission Occurred 25 Mask */ -#define CAN_TXBTO_TO25(value) (CAN_TXBTO_TO25_Msk & ((value) << CAN_TXBTO_TO25_Pos)) -#define CAN_TXBTO_TO26_Pos _U_(26) /**< (CAN_TXBTO) Transmission Occurred 26 Position */ -#define CAN_TXBTO_TO26_Msk (_U_(0x1) << CAN_TXBTO_TO26_Pos) /**< (CAN_TXBTO) Transmission Occurred 26 Mask */ -#define CAN_TXBTO_TO26(value) (CAN_TXBTO_TO26_Msk & ((value) << CAN_TXBTO_TO26_Pos)) -#define CAN_TXBTO_TO27_Pos _U_(27) /**< (CAN_TXBTO) Transmission Occurred 27 Position */ -#define CAN_TXBTO_TO27_Msk (_U_(0x1) << CAN_TXBTO_TO27_Pos) /**< (CAN_TXBTO) Transmission Occurred 27 Mask */ -#define CAN_TXBTO_TO27(value) (CAN_TXBTO_TO27_Msk & ((value) << CAN_TXBTO_TO27_Pos)) -#define CAN_TXBTO_TO28_Pos _U_(28) /**< (CAN_TXBTO) Transmission Occurred 28 Position */ -#define CAN_TXBTO_TO28_Msk (_U_(0x1) << CAN_TXBTO_TO28_Pos) /**< (CAN_TXBTO) Transmission Occurred 28 Mask */ -#define CAN_TXBTO_TO28(value) (CAN_TXBTO_TO28_Msk & ((value) << CAN_TXBTO_TO28_Pos)) -#define CAN_TXBTO_TO29_Pos _U_(29) /**< (CAN_TXBTO) Transmission Occurred 29 Position */ -#define CAN_TXBTO_TO29_Msk (_U_(0x1) << CAN_TXBTO_TO29_Pos) /**< (CAN_TXBTO) Transmission Occurred 29 Mask */ -#define CAN_TXBTO_TO29(value) (CAN_TXBTO_TO29_Msk & ((value) << CAN_TXBTO_TO29_Pos)) -#define CAN_TXBTO_TO30_Pos _U_(30) /**< (CAN_TXBTO) Transmission Occurred 30 Position */ -#define CAN_TXBTO_TO30_Msk (_U_(0x1) << CAN_TXBTO_TO30_Pos) /**< (CAN_TXBTO) Transmission Occurred 30 Mask */ -#define CAN_TXBTO_TO30(value) (CAN_TXBTO_TO30_Msk & ((value) << CAN_TXBTO_TO30_Pos)) -#define CAN_TXBTO_TO31_Pos _U_(31) /**< (CAN_TXBTO) Transmission Occurred 31 Position */ -#define CAN_TXBTO_TO31_Msk (_U_(0x1) << CAN_TXBTO_TO31_Pos) /**< (CAN_TXBTO) Transmission Occurred 31 Mask */ -#define CAN_TXBTO_TO31(value) (CAN_TXBTO_TO31_Msk & ((value) << CAN_TXBTO_TO31_Pos)) -#define CAN_TXBTO_Msk _U_(0xFFFFFFFF) /**< (CAN_TXBTO) Register Mask */ - -#define CAN_TXBTO_TO_Pos _U_(0) /**< (CAN_TXBTO Position) Transmission Occurred 3x */ -#define CAN_TXBTO_TO_Msk (_U_(0xFFFFFFFF) << CAN_TXBTO_TO_Pos) /**< (CAN_TXBTO Mask) TO */ -#define CAN_TXBTO_TO(value) (CAN_TXBTO_TO_Msk & ((value) << CAN_TXBTO_TO_Pos)) - -/* -------- CAN_TXBCF : (CAN Offset: 0xDC) ( R/ 32) Tx Buffer Cancellation Finished -------- */ -#define CAN_TXBCF_RESETVALUE _U_(0x00) /**< (CAN_TXBCF) Tx Buffer Cancellation Finished Reset Value */ - -#define CAN_TXBCF_CF0_Pos _U_(0) /**< (CAN_TXBCF) Tx Buffer Cancellation Finished 0 Position */ -#define CAN_TXBCF_CF0_Msk (_U_(0x1) << CAN_TXBCF_CF0_Pos) /**< (CAN_TXBCF) Tx Buffer Cancellation Finished 0 Mask */ -#define CAN_TXBCF_CF0(value) (CAN_TXBCF_CF0_Msk & ((value) << CAN_TXBCF_CF0_Pos)) -#define CAN_TXBCF_CF1_Pos _U_(1) /**< (CAN_TXBCF) Tx Buffer Cancellation Finished 1 Position */ -#define CAN_TXBCF_CF1_Msk (_U_(0x1) << CAN_TXBCF_CF1_Pos) /**< (CAN_TXBCF) Tx Buffer Cancellation Finished 1 Mask */ -#define CAN_TXBCF_CF1(value) (CAN_TXBCF_CF1_Msk & ((value) << CAN_TXBCF_CF1_Pos)) -#define CAN_TXBCF_CF2_Pos _U_(2) /**< (CAN_TXBCF) Tx Buffer Cancellation Finished 2 Position */ -#define CAN_TXBCF_CF2_Msk (_U_(0x1) << CAN_TXBCF_CF2_Pos) /**< (CAN_TXBCF) Tx Buffer Cancellation Finished 2 Mask */ -#define CAN_TXBCF_CF2(value) (CAN_TXBCF_CF2_Msk & ((value) << CAN_TXBCF_CF2_Pos)) -#define CAN_TXBCF_CF3_Pos _U_(3) /**< (CAN_TXBCF) Tx Buffer Cancellation Finished 3 Position */ -#define CAN_TXBCF_CF3_Msk (_U_(0x1) << CAN_TXBCF_CF3_Pos) /**< (CAN_TXBCF) Tx Buffer Cancellation Finished 3 Mask */ -#define CAN_TXBCF_CF3(value) (CAN_TXBCF_CF3_Msk & ((value) << CAN_TXBCF_CF3_Pos)) -#define CAN_TXBCF_CF4_Pos _U_(4) /**< (CAN_TXBCF) Tx Buffer Cancellation Finished 4 Position */ -#define CAN_TXBCF_CF4_Msk (_U_(0x1) << CAN_TXBCF_CF4_Pos) /**< (CAN_TXBCF) Tx Buffer Cancellation Finished 4 Mask */ -#define CAN_TXBCF_CF4(value) (CAN_TXBCF_CF4_Msk & ((value) << CAN_TXBCF_CF4_Pos)) -#define CAN_TXBCF_CF5_Pos _U_(5) /**< (CAN_TXBCF) Tx Buffer Cancellation Finished 5 Position */ -#define CAN_TXBCF_CF5_Msk (_U_(0x1) << CAN_TXBCF_CF5_Pos) /**< (CAN_TXBCF) Tx Buffer Cancellation Finished 5 Mask */ -#define CAN_TXBCF_CF5(value) (CAN_TXBCF_CF5_Msk & ((value) << CAN_TXBCF_CF5_Pos)) -#define CAN_TXBCF_CF6_Pos _U_(6) /**< (CAN_TXBCF) Tx Buffer Cancellation Finished 6 Position */ -#define CAN_TXBCF_CF6_Msk (_U_(0x1) << CAN_TXBCF_CF6_Pos) /**< (CAN_TXBCF) Tx Buffer Cancellation Finished 6 Mask */ -#define CAN_TXBCF_CF6(value) (CAN_TXBCF_CF6_Msk & ((value) << CAN_TXBCF_CF6_Pos)) -#define CAN_TXBCF_CF7_Pos _U_(7) /**< (CAN_TXBCF) Tx Buffer Cancellation Finished 7 Position */ -#define CAN_TXBCF_CF7_Msk (_U_(0x1) << CAN_TXBCF_CF7_Pos) /**< (CAN_TXBCF) Tx Buffer Cancellation Finished 7 Mask */ -#define CAN_TXBCF_CF7(value) (CAN_TXBCF_CF7_Msk & ((value) << CAN_TXBCF_CF7_Pos)) -#define CAN_TXBCF_CF8_Pos _U_(8) /**< (CAN_TXBCF) Tx Buffer Cancellation Finished 8 Position */ -#define CAN_TXBCF_CF8_Msk (_U_(0x1) << CAN_TXBCF_CF8_Pos) /**< (CAN_TXBCF) Tx Buffer Cancellation Finished 8 Mask */ -#define CAN_TXBCF_CF8(value) (CAN_TXBCF_CF8_Msk & ((value) << CAN_TXBCF_CF8_Pos)) -#define CAN_TXBCF_CF9_Pos _U_(9) /**< (CAN_TXBCF) Tx Buffer Cancellation Finished 9 Position */ -#define CAN_TXBCF_CF9_Msk (_U_(0x1) << CAN_TXBCF_CF9_Pos) /**< (CAN_TXBCF) Tx Buffer Cancellation Finished 9 Mask */ -#define CAN_TXBCF_CF9(value) (CAN_TXBCF_CF9_Msk & ((value) << CAN_TXBCF_CF9_Pos)) -#define CAN_TXBCF_CF10_Pos _U_(10) /**< (CAN_TXBCF) Tx Buffer Cancellation Finished 10 Position */ -#define CAN_TXBCF_CF10_Msk (_U_(0x1) << CAN_TXBCF_CF10_Pos) /**< (CAN_TXBCF) Tx Buffer Cancellation Finished 10 Mask */ -#define CAN_TXBCF_CF10(value) (CAN_TXBCF_CF10_Msk & ((value) << CAN_TXBCF_CF10_Pos)) -#define CAN_TXBCF_CF11_Pos _U_(11) /**< (CAN_TXBCF) Tx Buffer Cancellation Finished 11 Position */ -#define CAN_TXBCF_CF11_Msk (_U_(0x1) << CAN_TXBCF_CF11_Pos) /**< (CAN_TXBCF) Tx Buffer Cancellation Finished 11 Mask */ -#define CAN_TXBCF_CF11(value) (CAN_TXBCF_CF11_Msk & ((value) << CAN_TXBCF_CF11_Pos)) -#define CAN_TXBCF_CF12_Pos _U_(12) /**< (CAN_TXBCF) Tx Buffer Cancellation Finished 12 Position */ -#define CAN_TXBCF_CF12_Msk (_U_(0x1) << CAN_TXBCF_CF12_Pos) /**< (CAN_TXBCF) Tx Buffer Cancellation Finished 12 Mask */ -#define CAN_TXBCF_CF12(value) (CAN_TXBCF_CF12_Msk & ((value) << CAN_TXBCF_CF12_Pos)) -#define CAN_TXBCF_CF13_Pos _U_(13) /**< (CAN_TXBCF) Tx Buffer Cancellation Finished 13 Position */ -#define CAN_TXBCF_CF13_Msk (_U_(0x1) << CAN_TXBCF_CF13_Pos) /**< (CAN_TXBCF) Tx Buffer Cancellation Finished 13 Mask */ -#define CAN_TXBCF_CF13(value) (CAN_TXBCF_CF13_Msk & ((value) << CAN_TXBCF_CF13_Pos)) -#define CAN_TXBCF_CF14_Pos _U_(14) /**< (CAN_TXBCF) Tx Buffer Cancellation Finished 14 Position */ -#define CAN_TXBCF_CF14_Msk (_U_(0x1) << CAN_TXBCF_CF14_Pos) /**< (CAN_TXBCF) Tx Buffer Cancellation Finished 14 Mask */ -#define CAN_TXBCF_CF14(value) (CAN_TXBCF_CF14_Msk & ((value) << CAN_TXBCF_CF14_Pos)) -#define CAN_TXBCF_CF15_Pos _U_(15) /**< (CAN_TXBCF) Tx Buffer Cancellation Finished 15 Position */ -#define CAN_TXBCF_CF15_Msk (_U_(0x1) << CAN_TXBCF_CF15_Pos) /**< (CAN_TXBCF) Tx Buffer Cancellation Finished 15 Mask */ -#define CAN_TXBCF_CF15(value) (CAN_TXBCF_CF15_Msk & ((value) << CAN_TXBCF_CF15_Pos)) -#define CAN_TXBCF_CF16_Pos _U_(16) /**< (CAN_TXBCF) Tx Buffer Cancellation Finished 16 Position */ -#define CAN_TXBCF_CF16_Msk (_U_(0x1) << CAN_TXBCF_CF16_Pos) /**< (CAN_TXBCF) Tx Buffer Cancellation Finished 16 Mask */ -#define CAN_TXBCF_CF16(value) (CAN_TXBCF_CF16_Msk & ((value) << CAN_TXBCF_CF16_Pos)) -#define CAN_TXBCF_CF17_Pos _U_(17) /**< (CAN_TXBCF) Tx Buffer Cancellation Finished 17 Position */ -#define CAN_TXBCF_CF17_Msk (_U_(0x1) << CAN_TXBCF_CF17_Pos) /**< (CAN_TXBCF) Tx Buffer Cancellation Finished 17 Mask */ -#define CAN_TXBCF_CF17(value) (CAN_TXBCF_CF17_Msk & ((value) << CAN_TXBCF_CF17_Pos)) -#define CAN_TXBCF_CF18_Pos _U_(18) /**< (CAN_TXBCF) Tx Buffer Cancellation Finished 18 Position */ -#define CAN_TXBCF_CF18_Msk (_U_(0x1) << CAN_TXBCF_CF18_Pos) /**< (CAN_TXBCF) Tx Buffer Cancellation Finished 18 Mask */ -#define CAN_TXBCF_CF18(value) (CAN_TXBCF_CF18_Msk & ((value) << CAN_TXBCF_CF18_Pos)) -#define CAN_TXBCF_CF19_Pos _U_(19) /**< (CAN_TXBCF) Tx Buffer Cancellation Finished 19 Position */ -#define CAN_TXBCF_CF19_Msk (_U_(0x1) << CAN_TXBCF_CF19_Pos) /**< (CAN_TXBCF) Tx Buffer Cancellation Finished 19 Mask */ -#define CAN_TXBCF_CF19(value) (CAN_TXBCF_CF19_Msk & ((value) << CAN_TXBCF_CF19_Pos)) -#define CAN_TXBCF_CF20_Pos _U_(20) /**< (CAN_TXBCF) Tx Buffer Cancellation Finished 20 Position */ -#define CAN_TXBCF_CF20_Msk (_U_(0x1) << CAN_TXBCF_CF20_Pos) /**< (CAN_TXBCF) Tx Buffer Cancellation Finished 20 Mask */ -#define CAN_TXBCF_CF20(value) (CAN_TXBCF_CF20_Msk & ((value) << CAN_TXBCF_CF20_Pos)) -#define CAN_TXBCF_CF21_Pos _U_(21) /**< (CAN_TXBCF) Tx Buffer Cancellation Finished 21 Position */ -#define CAN_TXBCF_CF21_Msk (_U_(0x1) << CAN_TXBCF_CF21_Pos) /**< (CAN_TXBCF) Tx Buffer Cancellation Finished 21 Mask */ -#define CAN_TXBCF_CF21(value) (CAN_TXBCF_CF21_Msk & ((value) << CAN_TXBCF_CF21_Pos)) -#define CAN_TXBCF_CF22_Pos _U_(22) /**< (CAN_TXBCF) Tx Buffer Cancellation Finished 22 Position */ -#define CAN_TXBCF_CF22_Msk (_U_(0x1) << CAN_TXBCF_CF22_Pos) /**< (CAN_TXBCF) Tx Buffer Cancellation Finished 22 Mask */ -#define CAN_TXBCF_CF22(value) (CAN_TXBCF_CF22_Msk & ((value) << CAN_TXBCF_CF22_Pos)) -#define CAN_TXBCF_CF23_Pos _U_(23) /**< (CAN_TXBCF) Tx Buffer Cancellation Finished 23 Position */ -#define CAN_TXBCF_CF23_Msk (_U_(0x1) << CAN_TXBCF_CF23_Pos) /**< (CAN_TXBCF) Tx Buffer Cancellation Finished 23 Mask */ -#define CAN_TXBCF_CF23(value) (CAN_TXBCF_CF23_Msk & ((value) << CAN_TXBCF_CF23_Pos)) -#define CAN_TXBCF_CF24_Pos _U_(24) /**< (CAN_TXBCF) Tx Buffer Cancellation Finished 24 Position */ -#define CAN_TXBCF_CF24_Msk (_U_(0x1) << CAN_TXBCF_CF24_Pos) /**< (CAN_TXBCF) Tx Buffer Cancellation Finished 24 Mask */ -#define CAN_TXBCF_CF24(value) (CAN_TXBCF_CF24_Msk & ((value) << CAN_TXBCF_CF24_Pos)) -#define CAN_TXBCF_CF25_Pos _U_(25) /**< (CAN_TXBCF) Tx Buffer Cancellation Finished 25 Position */ -#define CAN_TXBCF_CF25_Msk (_U_(0x1) << CAN_TXBCF_CF25_Pos) /**< (CAN_TXBCF) Tx Buffer Cancellation Finished 25 Mask */ -#define CAN_TXBCF_CF25(value) (CAN_TXBCF_CF25_Msk & ((value) << CAN_TXBCF_CF25_Pos)) -#define CAN_TXBCF_CF26_Pos _U_(26) /**< (CAN_TXBCF) Tx Buffer Cancellation Finished 26 Position */ -#define CAN_TXBCF_CF26_Msk (_U_(0x1) << CAN_TXBCF_CF26_Pos) /**< (CAN_TXBCF) Tx Buffer Cancellation Finished 26 Mask */ -#define CAN_TXBCF_CF26(value) (CAN_TXBCF_CF26_Msk & ((value) << CAN_TXBCF_CF26_Pos)) -#define CAN_TXBCF_CF27_Pos _U_(27) /**< (CAN_TXBCF) Tx Buffer Cancellation Finished 27 Position */ -#define CAN_TXBCF_CF27_Msk (_U_(0x1) << CAN_TXBCF_CF27_Pos) /**< (CAN_TXBCF) Tx Buffer Cancellation Finished 27 Mask */ -#define CAN_TXBCF_CF27(value) (CAN_TXBCF_CF27_Msk & ((value) << CAN_TXBCF_CF27_Pos)) -#define CAN_TXBCF_CF28_Pos _U_(28) /**< (CAN_TXBCF) Tx Buffer Cancellation Finished 28 Position */ -#define CAN_TXBCF_CF28_Msk (_U_(0x1) << CAN_TXBCF_CF28_Pos) /**< (CAN_TXBCF) Tx Buffer Cancellation Finished 28 Mask */ -#define CAN_TXBCF_CF28(value) (CAN_TXBCF_CF28_Msk & ((value) << CAN_TXBCF_CF28_Pos)) -#define CAN_TXBCF_CF29_Pos _U_(29) /**< (CAN_TXBCF) Tx Buffer Cancellation Finished 29 Position */ -#define CAN_TXBCF_CF29_Msk (_U_(0x1) << CAN_TXBCF_CF29_Pos) /**< (CAN_TXBCF) Tx Buffer Cancellation Finished 29 Mask */ -#define CAN_TXBCF_CF29(value) (CAN_TXBCF_CF29_Msk & ((value) << CAN_TXBCF_CF29_Pos)) -#define CAN_TXBCF_CF30_Pos _U_(30) /**< (CAN_TXBCF) Tx Buffer Cancellation Finished 30 Position */ -#define CAN_TXBCF_CF30_Msk (_U_(0x1) << CAN_TXBCF_CF30_Pos) /**< (CAN_TXBCF) Tx Buffer Cancellation Finished 30 Mask */ -#define CAN_TXBCF_CF30(value) (CAN_TXBCF_CF30_Msk & ((value) << CAN_TXBCF_CF30_Pos)) -#define CAN_TXBCF_CF31_Pos _U_(31) /**< (CAN_TXBCF) Tx Buffer Cancellation Finished 31 Position */ -#define CAN_TXBCF_CF31_Msk (_U_(0x1) << CAN_TXBCF_CF31_Pos) /**< (CAN_TXBCF) Tx Buffer Cancellation Finished 31 Mask */ -#define CAN_TXBCF_CF31(value) (CAN_TXBCF_CF31_Msk & ((value) << CAN_TXBCF_CF31_Pos)) -#define CAN_TXBCF_Msk _U_(0xFFFFFFFF) /**< (CAN_TXBCF) Register Mask */ - -#define CAN_TXBCF_CF_Pos _U_(0) /**< (CAN_TXBCF Position) Tx Buffer Cancellation Finished 3x */ -#define CAN_TXBCF_CF_Msk (_U_(0xFFFFFFFF) << CAN_TXBCF_CF_Pos) /**< (CAN_TXBCF Mask) CF */ -#define CAN_TXBCF_CF(value) (CAN_TXBCF_CF_Msk & ((value) << CAN_TXBCF_CF_Pos)) - -/* -------- CAN_TXBTIE : (CAN Offset: 0xE0) (R/W 32) Tx Buffer Transmission Interrupt Enable -------- */ -#define CAN_TXBTIE_RESETVALUE _U_(0x00) /**< (CAN_TXBTIE) Tx Buffer Transmission Interrupt Enable Reset Value */ - -#define CAN_TXBTIE_TIE0_Pos _U_(0) /**< (CAN_TXBTIE) Transmission Interrupt Enable 0 Position */ -#define CAN_TXBTIE_TIE0_Msk (_U_(0x1) << CAN_TXBTIE_TIE0_Pos) /**< (CAN_TXBTIE) Transmission Interrupt Enable 0 Mask */ -#define CAN_TXBTIE_TIE0(value) (CAN_TXBTIE_TIE0_Msk & ((value) << CAN_TXBTIE_TIE0_Pos)) -#define CAN_TXBTIE_TIE1_Pos _U_(1) /**< (CAN_TXBTIE) Transmission Interrupt Enable 1 Position */ -#define CAN_TXBTIE_TIE1_Msk (_U_(0x1) << CAN_TXBTIE_TIE1_Pos) /**< (CAN_TXBTIE) Transmission Interrupt Enable 1 Mask */ -#define CAN_TXBTIE_TIE1(value) (CAN_TXBTIE_TIE1_Msk & ((value) << CAN_TXBTIE_TIE1_Pos)) -#define CAN_TXBTIE_TIE2_Pos _U_(2) /**< (CAN_TXBTIE) Transmission Interrupt Enable 2 Position */ -#define CAN_TXBTIE_TIE2_Msk (_U_(0x1) << CAN_TXBTIE_TIE2_Pos) /**< (CAN_TXBTIE) Transmission Interrupt Enable 2 Mask */ -#define CAN_TXBTIE_TIE2(value) (CAN_TXBTIE_TIE2_Msk & ((value) << CAN_TXBTIE_TIE2_Pos)) -#define CAN_TXBTIE_TIE3_Pos _U_(3) /**< (CAN_TXBTIE) Transmission Interrupt Enable 3 Position */ -#define CAN_TXBTIE_TIE3_Msk (_U_(0x1) << CAN_TXBTIE_TIE3_Pos) /**< (CAN_TXBTIE) Transmission Interrupt Enable 3 Mask */ -#define CAN_TXBTIE_TIE3(value) (CAN_TXBTIE_TIE3_Msk & ((value) << CAN_TXBTIE_TIE3_Pos)) -#define CAN_TXBTIE_TIE4_Pos _U_(4) /**< (CAN_TXBTIE) Transmission Interrupt Enable 4 Position */ -#define CAN_TXBTIE_TIE4_Msk (_U_(0x1) << CAN_TXBTIE_TIE4_Pos) /**< (CAN_TXBTIE) Transmission Interrupt Enable 4 Mask */ -#define CAN_TXBTIE_TIE4(value) (CAN_TXBTIE_TIE4_Msk & ((value) << CAN_TXBTIE_TIE4_Pos)) -#define CAN_TXBTIE_TIE5_Pos _U_(5) /**< (CAN_TXBTIE) Transmission Interrupt Enable 5 Position */ -#define CAN_TXBTIE_TIE5_Msk (_U_(0x1) << CAN_TXBTIE_TIE5_Pos) /**< (CAN_TXBTIE) Transmission Interrupt Enable 5 Mask */ -#define CAN_TXBTIE_TIE5(value) (CAN_TXBTIE_TIE5_Msk & ((value) << CAN_TXBTIE_TIE5_Pos)) -#define CAN_TXBTIE_TIE6_Pos _U_(6) /**< (CAN_TXBTIE) Transmission Interrupt Enable 6 Position */ -#define CAN_TXBTIE_TIE6_Msk (_U_(0x1) << CAN_TXBTIE_TIE6_Pos) /**< (CAN_TXBTIE) Transmission Interrupt Enable 6 Mask */ -#define CAN_TXBTIE_TIE6(value) (CAN_TXBTIE_TIE6_Msk & ((value) << CAN_TXBTIE_TIE6_Pos)) -#define CAN_TXBTIE_TIE7_Pos _U_(7) /**< (CAN_TXBTIE) Transmission Interrupt Enable 7 Position */ -#define CAN_TXBTIE_TIE7_Msk (_U_(0x1) << CAN_TXBTIE_TIE7_Pos) /**< (CAN_TXBTIE) Transmission Interrupt Enable 7 Mask */ -#define CAN_TXBTIE_TIE7(value) (CAN_TXBTIE_TIE7_Msk & ((value) << CAN_TXBTIE_TIE7_Pos)) -#define CAN_TXBTIE_TIE8_Pos _U_(8) /**< (CAN_TXBTIE) Transmission Interrupt Enable 8 Position */ -#define CAN_TXBTIE_TIE8_Msk (_U_(0x1) << CAN_TXBTIE_TIE8_Pos) /**< (CAN_TXBTIE) Transmission Interrupt Enable 8 Mask */ -#define CAN_TXBTIE_TIE8(value) (CAN_TXBTIE_TIE8_Msk & ((value) << CAN_TXBTIE_TIE8_Pos)) -#define CAN_TXBTIE_TIE9_Pos _U_(9) /**< (CAN_TXBTIE) Transmission Interrupt Enable 9 Position */ -#define CAN_TXBTIE_TIE9_Msk (_U_(0x1) << CAN_TXBTIE_TIE9_Pos) /**< (CAN_TXBTIE) Transmission Interrupt Enable 9 Mask */ -#define CAN_TXBTIE_TIE9(value) (CAN_TXBTIE_TIE9_Msk & ((value) << CAN_TXBTIE_TIE9_Pos)) -#define CAN_TXBTIE_TIE10_Pos _U_(10) /**< (CAN_TXBTIE) Transmission Interrupt Enable 10 Position */ -#define CAN_TXBTIE_TIE10_Msk (_U_(0x1) << CAN_TXBTIE_TIE10_Pos) /**< (CAN_TXBTIE) Transmission Interrupt Enable 10 Mask */ -#define CAN_TXBTIE_TIE10(value) (CAN_TXBTIE_TIE10_Msk & ((value) << CAN_TXBTIE_TIE10_Pos)) -#define CAN_TXBTIE_TIE11_Pos _U_(11) /**< (CAN_TXBTIE) Transmission Interrupt Enable 11 Position */ -#define CAN_TXBTIE_TIE11_Msk (_U_(0x1) << CAN_TXBTIE_TIE11_Pos) /**< (CAN_TXBTIE) Transmission Interrupt Enable 11 Mask */ -#define CAN_TXBTIE_TIE11(value) (CAN_TXBTIE_TIE11_Msk & ((value) << CAN_TXBTIE_TIE11_Pos)) -#define CAN_TXBTIE_TIE12_Pos _U_(12) /**< (CAN_TXBTIE) Transmission Interrupt Enable 12 Position */ -#define CAN_TXBTIE_TIE12_Msk (_U_(0x1) << CAN_TXBTIE_TIE12_Pos) /**< (CAN_TXBTIE) Transmission Interrupt Enable 12 Mask */ -#define CAN_TXBTIE_TIE12(value) (CAN_TXBTIE_TIE12_Msk & ((value) << CAN_TXBTIE_TIE12_Pos)) -#define CAN_TXBTIE_TIE13_Pos _U_(13) /**< (CAN_TXBTIE) Transmission Interrupt Enable 13 Position */ -#define CAN_TXBTIE_TIE13_Msk (_U_(0x1) << CAN_TXBTIE_TIE13_Pos) /**< (CAN_TXBTIE) Transmission Interrupt Enable 13 Mask */ -#define CAN_TXBTIE_TIE13(value) (CAN_TXBTIE_TIE13_Msk & ((value) << CAN_TXBTIE_TIE13_Pos)) -#define CAN_TXBTIE_TIE14_Pos _U_(14) /**< (CAN_TXBTIE) Transmission Interrupt Enable 14 Position */ -#define CAN_TXBTIE_TIE14_Msk (_U_(0x1) << CAN_TXBTIE_TIE14_Pos) /**< (CAN_TXBTIE) Transmission Interrupt Enable 14 Mask */ -#define CAN_TXBTIE_TIE14(value) (CAN_TXBTIE_TIE14_Msk & ((value) << CAN_TXBTIE_TIE14_Pos)) -#define CAN_TXBTIE_TIE15_Pos _U_(15) /**< (CAN_TXBTIE) Transmission Interrupt Enable 15 Position */ -#define CAN_TXBTIE_TIE15_Msk (_U_(0x1) << CAN_TXBTIE_TIE15_Pos) /**< (CAN_TXBTIE) Transmission Interrupt Enable 15 Mask */ -#define CAN_TXBTIE_TIE15(value) (CAN_TXBTIE_TIE15_Msk & ((value) << CAN_TXBTIE_TIE15_Pos)) -#define CAN_TXBTIE_TIE16_Pos _U_(16) /**< (CAN_TXBTIE) Transmission Interrupt Enable 16 Position */ -#define CAN_TXBTIE_TIE16_Msk (_U_(0x1) << CAN_TXBTIE_TIE16_Pos) /**< (CAN_TXBTIE) Transmission Interrupt Enable 16 Mask */ -#define CAN_TXBTIE_TIE16(value) (CAN_TXBTIE_TIE16_Msk & ((value) << CAN_TXBTIE_TIE16_Pos)) -#define CAN_TXBTIE_TIE17_Pos _U_(17) /**< (CAN_TXBTIE) Transmission Interrupt Enable 17 Position */ -#define CAN_TXBTIE_TIE17_Msk (_U_(0x1) << CAN_TXBTIE_TIE17_Pos) /**< (CAN_TXBTIE) Transmission Interrupt Enable 17 Mask */ -#define CAN_TXBTIE_TIE17(value) (CAN_TXBTIE_TIE17_Msk & ((value) << CAN_TXBTIE_TIE17_Pos)) -#define CAN_TXBTIE_TIE18_Pos _U_(18) /**< (CAN_TXBTIE) Transmission Interrupt Enable 18 Position */ -#define CAN_TXBTIE_TIE18_Msk (_U_(0x1) << CAN_TXBTIE_TIE18_Pos) /**< (CAN_TXBTIE) Transmission Interrupt Enable 18 Mask */ -#define CAN_TXBTIE_TIE18(value) (CAN_TXBTIE_TIE18_Msk & ((value) << CAN_TXBTIE_TIE18_Pos)) -#define CAN_TXBTIE_TIE19_Pos _U_(19) /**< (CAN_TXBTIE) Transmission Interrupt Enable 19 Position */ -#define CAN_TXBTIE_TIE19_Msk (_U_(0x1) << CAN_TXBTIE_TIE19_Pos) /**< (CAN_TXBTIE) Transmission Interrupt Enable 19 Mask */ -#define CAN_TXBTIE_TIE19(value) (CAN_TXBTIE_TIE19_Msk & ((value) << CAN_TXBTIE_TIE19_Pos)) -#define CAN_TXBTIE_TIE20_Pos _U_(20) /**< (CAN_TXBTIE) Transmission Interrupt Enable 20 Position */ -#define CAN_TXBTIE_TIE20_Msk (_U_(0x1) << CAN_TXBTIE_TIE20_Pos) /**< (CAN_TXBTIE) Transmission Interrupt Enable 20 Mask */ -#define CAN_TXBTIE_TIE20(value) (CAN_TXBTIE_TIE20_Msk & ((value) << CAN_TXBTIE_TIE20_Pos)) -#define CAN_TXBTIE_TIE21_Pos _U_(21) /**< (CAN_TXBTIE) Transmission Interrupt Enable 21 Position */ -#define CAN_TXBTIE_TIE21_Msk (_U_(0x1) << CAN_TXBTIE_TIE21_Pos) /**< (CAN_TXBTIE) Transmission Interrupt Enable 21 Mask */ -#define CAN_TXBTIE_TIE21(value) (CAN_TXBTIE_TIE21_Msk & ((value) << CAN_TXBTIE_TIE21_Pos)) -#define CAN_TXBTIE_TIE22_Pos _U_(22) /**< (CAN_TXBTIE) Transmission Interrupt Enable 22 Position */ -#define CAN_TXBTIE_TIE22_Msk (_U_(0x1) << CAN_TXBTIE_TIE22_Pos) /**< (CAN_TXBTIE) Transmission Interrupt Enable 22 Mask */ -#define CAN_TXBTIE_TIE22(value) (CAN_TXBTIE_TIE22_Msk & ((value) << CAN_TXBTIE_TIE22_Pos)) -#define CAN_TXBTIE_TIE23_Pos _U_(23) /**< (CAN_TXBTIE) Transmission Interrupt Enable 23 Position */ -#define CAN_TXBTIE_TIE23_Msk (_U_(0x1) << CAN_TXBTIE_TIE23_Pos) /**< (CAN_TXBTIE) Transmission Interrupt Enable 23 Mask */ -#define CAN_TXBTIE_TIE23(value) (CAN_TXBTIE_TIE23_Msk & ((value) << CAN_TXBTIE_TIE23_Pos)) -#define CAN_TXBTIE_TIE24_Pos _U_(24) /**< (CAN_TXBTIE) Transmission Interrupt Enable 24 Position */ -#define CAN_TXBTIE_TIE24_Msk (_U_(0x1) << CAN_TXBTIE_TIE24_Pos) /**< (CAN_TXBTIE) Transmission Interrupt Enable 24 Mask */ -#define CAN_TXBTIE_TIE24(value) (CAN_TXBTIE_TIE24_Msk & ((value) << CAN_TXBTIE_TIE24_Pos)) -#define CAN_TXBTIE_TIE25_Pos _U_(25) /**< (CAN_TXBTIE) Transmission Interrupt Enable 25 Position */ -#define CAN_TXBTIE_TIE25_Msk (_U_(0x1) << CAN_TXBTIE_TIE25_Pos) /**< (CAN_TXBTIE) Transmission Interrupt Enable 25 Mask */ -#define CAN_TXBTIE_TIE25(value) (CAN_TXBTIE_TIE25_Msk & ((value) << CAN_TXBTIE_TIE25_Pos)) -#define CAN_TXBTIE_TIE26_Pos _U_(26) /**< (CAN_TXBTIE) Transmission Interrupt Enable 26 Position */ -#define CAN_TXBTIE_TIE26_Msk (_U_(0x1) << CAN_TXBTIE_TIE26_Pos) /**< (CAN_TXBTIE) Transmission Interrupt Enable 26 Mask */ -#define CAN_TXBTIE_TIE26(value) (CAN_TXBTIE_TIE26_Msk & ((value) << CAN_TXBTIE_TIE26_Pos)) -#define CAN_TXBTIE_TIE27_Pos _U_(27) /**< (CAN_TXBTIE) Transmission Interrupt Enable 27 Position */ -#define CAN_TXBTIE_TIE27_Msk (_U_(0x1) << CAN_TXBTIE_TIE27_Pos) /**< (CAN_TXBTIE) Transmission Interrupt Enable 27 Mask */ -#define CAN_TXBTIE_TIE27(value) (CAN_TXBTIE_TIE27_Msk & ((value) << CAN_TXBTIE_TIE27_Pos)) -#define CAN_TXBTIE_TIE28_Pos _U_(28) /**< (CAN_TXBTIE) Transmission Interrupt Enable 28 Position */ -#define CAN_TXBTIE_TIE28_Msk (_U_(0x1) << CAN_TXBTIE_TIE28_Pos) /**< (CAN_TXBTIE) Transmission Interrupt Enable 28 Mask */ -#define CAN_TXBTIE_TIE28(value) (CAN_TXBTIE_TIE28_Msk & ((value) << CAN_TXBTIE_TIE28_Pos)) -#define CAN_TXBTIE_TIE29_Pos _U_(29) /**< (CAN_TXBTIE) Transmission Interrupt Enable 29 Position */ -#define CAN_TXBTIE_TIE29_Msk (_U_(0x1) << CAN_TXBTIE_TIE29_Pos) /**< (CAN_TXBTIE) Transmission Interrupt Enable 29 Mask */ -#define CAN_TXBTIE_TIE29(value) (CAN_TXBTIE_TIE29_Msk & ((value) << CAN_TXBTIE_TIE29_Pos)) -#define CAN_TXBTIE_TIE30_Pos _U_(30) /**< (CAN_TXBTIE) Transmission Interrupt Enable 30 Position */ -#define CAN_TXBTIE_TIE30_Msk (_U_(0x1) << CAN_TXBTIE_TIE30_Pos) /**< (CAN_TXBTIE) Transmission Interrupt Enable 30 Mask */ -#define CAN_TXBTIE_TIE30(value) (CAN_TXBTIE_TIE30_Msk & ((value) << CAN_TXBTIE_TIE30_Pos)) -#define CAN_TXBTIE_TIE31_Pos _U_(31) /**< (CAN_TXBTIE) Transmission Interrupt Enable 31 Position */ -#define CAN_TXBTIE_TIE31_Msk (_U_(0x1) << CAN_TXBTIE_TIE31_Pos) /**< (CAN_TXBTIE) Transmission Interrupt Enable 31 Mask */ -#define CAN_TXBTIE_TIE31(value) (CAN_TXBTIE_TIE31_Msk & ((value) << CAN_TXBTIE_TIE31_Pos)) -#define CAN_TXBTIE_Msk _U_(0xFFFFFFFF) /**< (CAN_TXBTIE) Register Mask */ - -#define CAN_TXBTIE_TIE_Pos _U_(0) /**< (CAN_TXBTIE Position) Transmission Interrupt Enable 3x */ -#define CAN_TXBTIE_TIE_Msk (_U_(0xFFFFFFFF) << CAN_TXBTIE_TIE_Pos) /**< (CAN_TXBTIE Mask) TIE */ -#define CAN_TXBTIE_TIE(value) (CAN_TXBTIE_TIE_Msk & ((value) << CAN_TXBTIE_TIE_Pos)) - -/* -------- CAN_TXBCIE : (CAN Offset: 0xE4) (R/W 32) Tx Buffer Cancellation Finished Interrupt Enable -------- */ -#define CAN_TXBCIE_RESETVALUE _U_(0x00) /**< (CAN_TXBCIE) Tx Buffer Cancellation Finished Interrupt Enable Reset Value */ - -#define CAN_TXBCIE_CFIE0_Pos _U_(0) /**< (CAN_TXBCIE) Cancellation Finished Interrupt Enable 0 Position */ -#define CAN_TXBCIE_CFIE0_Msk (_U_(0x1) << CAN_TXBCIE_CFIE0_Pos) /**< (CAN_TXBCIE) Cancellation Finished Interrupt Enable 0 Mask */ -#define CAN_TXBCIE_CFIE0(value) (CAN_TXBCIE_CFIE0_Msk & ((value) << CAN_TXBCIE_CFIE0_Pos)) -#define CAN_TXBCIE_CFIE1_Pos _U_(1) /**< (CAN_TXBCIE) Cancellation Finished Interrupt Enable 1 Position */ -#define CAN_TXBCIE_CFIE1_Msk (_U_(0x1) << CAN_TXBCIE_CFIE1_Pos) /**< (CAN_TXBCIE) Cancellation Finished Interrupt Enable 1 Mask */ -#define CAN_TXBCIE_CFIE1(value) (CAN_TXBCIE_CFIE1_Msk & ((value) << CAN_TXBCIE_CFIE1_Pos)) -#define CAN_TXBCIE_CFIE2_Pos _U_(2) /**< (CAN_TXBCIE) Cancellation Finished Interrupt Enable 2 Position */ -#define CAN_TXBCIE_CFIE2_Msk (_U_(0x1) << CAN_TXBCIE_CFIE2_Pos) /**< (CAN_TXBCIE) Cancellation Finished Interrupt Enable 2 Mask */ -#define CAN_TXBCIE_CFIE2(value) (CAN_TXBCIE_CFIE2_Msk & ((value) << CAN_TXBCIE_CFIE2_Pos)) -#define CAN_TXBCIE_CFIE3_Pos _U_(3) /**< (CAN_TXBCIE) Cancellation Finished Interrupt Enable 3 Position */ -#define CAN_TXBCIE_CFIE3_Msk (_U_(0x1) << CAN_TXBCIE_CFIE3_Pos) /**< (CAN_TXBCIE) Cancellation Finished Interrupt Enable 3 Mask */ -#define CAN_TXBCIE_CFIE3(value) (CAN_TXBCIE_CFIE3_Msk & ((value) << CAN_TXBCIE_CFIE3_Pos)) -#define CAN_TXBCIE_CFIE4_Pos _U_(4) /**< (CAN_TXBCIE) Cancellation Finished Interrupt Enable 4 Position */ -#define CAN_TXBCIE_CFIE4_Msk (_U_(0x1) << CAN_TXBCIE_CFIE4_Pos) /**< (CAN_TXBCIE) Cancellation Finished Interrupt Enable 4 Mask */ -#define CAN_TXBCIE_CFIE4(value) (CAN_TXBCIE_CFIE4_Msk & ((value) << CAN_TXBCIE_CFIE4_Pos)) -#define CAN_TXBCIE_CFIE5_Pos _U_(5) /**< (CAN_TXBCIE) Cancellation Finished Interrupt Enable 5 Position */ -#define CAN_TXBCIE_CFIE5_Msk (_U_(0x1) << CAN_TXBCIE_CFIE5_Pos) /**< (CAN_TXBCIE) Cancellation Finished Interrupt Enable 5 Mask */ -#define CAN_TXBCIE_CFIE5(value) (CAN_TXBCIE_CFIE5_Msk & ((value) << CAN_TXBCIE_CFIE5_Pos)) -#define CAN_TXBCIE_CFIE6_Pos _U_(6) /**< (CAN_TXBCIE) Cancellation Finished Interrupt Enable 6 Position */ -#define CAN_TXBCIE_CFIE6_Msk (_U_(0x1) << CAN_TXBCIE_CFIE6_Pos) /**< (CAN_TXBCIE) Cancellation Finished Interrupt Enable 6 Mask */ -#define CAN_TXBCIE_CFIE6(value) (CAN_TXBCIE_CFIE6_Msk & ((value) << CAN_TXBCIE_CFIE6_Pos)) -#define CAN_TXBCIE_CFIE7_Pos _U_(7) /**< (CAN_TXBCIE) Cancellation Finished Interrupt Enable 7 Position */ -#define CAN_TXBCIE_CFIE7_Msk (_U_(0x1) << CAN_TXBCIE_CFIE7_Pos) /**< (CAN_TXBCIE) Cancellation Finished Interrupt Enable 7 Mask */ -#define CAN_TXBCIE_CFIE7(value) (CAN_TXBCIE_CFIE7_Msk & ((value) << CAN_TXBCIE_CFIE7_Pos)) -#define CAN_TXBCIE_CFIE8_Pos _U_(8) /**< (CAN_TXBCIE) Cancellation Finished Interrupt Enable 8 Position */ -#define CAN_TXBCIE_CFIE8_Msk (_U_(0x1) << CAN_TXBCIE_CFIE8_Pos) /**< (CAN_TXBCIE) Cancellation Finished Interrupt Enable 8 Mask */ -#define CAN_TXBCIE_CFIE8(value) (CAN_TXBCIE_CFIE8_Msk & ((value) << CAN_TXBCIE_CFIE8_Pos)) -#define CAN_TXBCIE_CFIE9_Pos _U_(9) /**< (CAN_TXBCIE) Cancellation Finished Interrupt Enable 9 Position */ -#define CAN_TXBCIE_CFIE9_Msk (_U_(0x1) << CAN_TXBCIE_CFIE9_Pos) /**< (CAN_TXBCIE) Cancellation Finished Interrupt Enable 9 Mask */ -#define CAN_TXBCIE_CFIE9(value) (CAN_TXBCIE_CFIE9_Msk & ((value) << CAN_TXBCIE_CFIE9_Pos)) -#define CAN_TXBCIE_CFIE10_Pos _U_(10) /**< (CAN_TXBCIE) Cancellation Finished Interrupt Enable 10 Position */ -#define CAN_TXBCIE_CFIE10_Msk (_U_(0x1) << CAN_TXBCIE_CFIE10_Pos) /**< (CAN_TXBCIE) Cancellation Finished Interrupt Enable 10 Mask */ -#define CAN_TXBCIE_CFIE10(value) (CAN_TXBCIE_CFIE10_Msk & ((value) << CAN_TXBCIE_CFIE10_Pos)) -#define CAN_TXBCIE_CFIE11_Pos _U_(11) /**< (CAN_TXBCIE) Cancellation Finished Interrupt Enable 11 Position */ -#define CAN_TXBCIE_CFIE11_Msk (_U_(0x1) << CAN_TXBCIE_CFIE11_Pos) /**< (CAN_TXBCIE) Cancellation Finished Interrupt Enable 11 Mask */ -#define CAN_TXBCIE_CFIE11(value) (CAN_TXBCIE_CFIE11_Msk & ((value) << CAN_TXBCIE_CFIE11_Pos)) -#define CAN_TXBCIE_CFIE12_Pos _U_(12) /**< (CAN_TXBCIE) Cancellation Finished Interrupt Enable 12 Position */ -#define CAN_TXBCIE_CFIE12_Msk (_U_(0x1) << CAN_TXBCIE_CFIE12_Pos) /**< (CAN_TXBCIE) Cancellation Finished Interrupt Enable 12 Mask */ -#define CAN_TXBCIE_CFIE12(value) (CAN_TXBCIE_CFIE12_Msk & ((value) << CAN_TXBCIE_CFIE12_Pos)) -#define CAN_TXBCIE_CFIE13_Pos _U_(13) /**< (CAN_TXBCIE) Cancellation Finished Interrupt Enable 13 Position */ -#define CAN_TXBCIE_CFIE13_Msk (_U_(0x1) << CAN_TXBCIE_CFIE13_Pos) /**< (CAN_TXBCIE) Cancellation Finished Interrupt Enable 13 Mask */ -#define CAN_TXBCIE_CFIE13(value) (CAN_TXBCIE_CFIE13_Msk & ((value) << CAN_TXBCIE_CFIE13_Pos)) -#define CAN_TXBCIE_CFIE14_Pos _U_(14) /**< (CAN_TXBCIE) Cancellation Finished Interrupt Enable 14 Position */ -#define CAN_TXBCIE_CFIE14_Msk (_U_(0x1) << CAN_TXBCIE_CFIE14_Pos) /**< (CAN_TXBCIE) Cancellation Finished Interrupt Enable 14 Mask */ -#define CAN_TXBCIE_CFIE14(value) (CAN_TXBCIE_CFIE14_Msk & ((value) << CAN_TXBCIE_CFIE14_Pos)) -#define CAN_TXBCIE_CFIE15_Pos _U_(15) /**< (CAN_TXBCIE) Cancellation Finished Interrupt Enable 15 Position */ -#define CAN_TXBCIE_CFIE15_Msk (_U_(0x1) << CAN_TXBCIE_CFIE15_Pos) /**< (CAN_TXBCIE) Cancellation Finished Interrupt Enable 15 Mask */ -#define CAN_TXBCIE_CFIE15(value) (CAN_TXBCIE_CFIE15_Msk & ((value) << CAN_TXBCIE_CFIE15_Pos)) -#define CAN_TXBCIE_CFIE16_Pos _U_(16) /**< (CAN_TXBCIE) Cancellation Finished Interrupt Enable 16 Position */ -#define CAN_TXBCIE_CFIE16_Msk (_U_(0x1) << CAN_TXBCIE_CFIE16_Pos) /**< (CAN_TXBCIE) Cancellation Finished Interrupt Enable 16 Mask */ -#define CAN_TXBCIE_CFIE16(value) (CAN_TXBCIE_CFIE16_Msk & ((value) << CAN_TXBCIE_CFIE16_Pos)) -#define CAN_TXBCIE_CFIE17_Pos _U_(17) /**< (CAN_TXBCIE) Cancellation Finished Interrupt Enable 17 Position */ -#define CAN_TXBCIE_CFIE17_Msk (_U_(0x1) << CAN_TXBCIE_CFIE17_Pos) /**< (CAN_TXBCIE) Cancellation Finished Interrupt Enable 17 Mask */ -#define CAN_TXBCIE_CFIE17(value) (CAN_TXBCIE_CFIE17_Msk & ((value) << CAN_TXBCIE_CFIE17_Pos)) -#define CAN_TXBCIE_CFIE18_Pos _U_(18) /**< (CAN_TXBCIE) Cancellation Finished Interrupt Enable 18 Position */ -#define CAN_TXBCIE_CFIE18_Msk (_U_(0x1) << CAN_TXBCIE_CFIE18_Pos) /**< (CAN_TXBCIE) Cancellation Finished Interrupt Enable 18 Mask */ -#define CAN_TXBCIE_CFIE18(value) (CAN_TXBCIE_CFIE18_Msk & ((value) << CAN_TXBCIE_CFIE18_Pos)) -#define CAN_TXBCIE_CFIE19_Pos _U_(19) /**< (CAN_TXBCIE) Cancellation Finished Interrupt Enable 19 Position */ -#define CAN_TXBCIE_CFIE19_Msk (_U_(0x1) << CAN_TXBCIE_CFIE19_Pos) /**< (CAN_TXBCIE) Cancellation Finished Interrupt Enable 19 Mask */ -#define CAN_TXBCIE_CFIE19(value) (CAN_TXBCIE_CFIE19_Msk & ((value) << CAN_TXBCIE_CFIE19_Pos)) -#define CAN_TXBCIE_CFIE20_Pos _U_(20) /**< (CAN_TXBCIE) Cancellation Finished Interrupt Enable 20 Position */ -#define CAN_TXBCIE_CFIE20_Msk (_U_(0x1) << CAN_TXBCIE_CFIE20_Pos) /**< (CAN_TXBCIE) Cancellation Finished Interrupt Enable 20 Mask */ -#define CAN_TXBCIE_CFIE20(value) (CAN_TXBCIE_CFIE20_Msk & ((value) << CAN_TXBCIE_CFIE20_Pos)) -#define CAN_TXBCIE_CFIE21_Pos _U_(21) /**< (CAN_TXBCIE) Cancellation Finished Interrupt Enable 21 Position */ -#define CAN_TXBCIE_CFIE21_Msk (_U_(0x1) << CAN_TXBCIE_CFIE21_Pos) /**< (CAN_TXBCIE) Cancellation Finished Interrupt Enable 21 Mask */ -#define CAN_TXBCIE_CFIE21(value) (CAN_TXBCIE_CFIE21_Msk & ((value) << CAN_TXBCIE_CFIE21_Pos)) -#define CAN_TXBCIE_CFIE22_Pos _U_(22) /**< (CAN_TXBCIE) Cancellation Finished Interrupt Enable 22 Position */ -#define CAN_TXBCIE_CFIE22_Msk (_U_(0x1) << CAN_TXBCIE_CFIE22_Pos) /**< (CAN_TXBCIE) Cancellation Finished Interrupt Enable 22 Mask */ -#define CAN_TXBCIE_CFIE22(value) (CAN_TXBCIE_CFIE22_Msk & ((value) << CAN_TXBCIE_CFIE22_Pos)) -#define CAN_TXBCIE_CFIE23_Pos _U_(23) /**< (CAN_TXBCIE) Cancellation Finished Interrupt Enable 23 Position */ -#define CAN_TXBCIE_CFIE23_Msk (_U_(0x1) << CAN_TXBCIE_CFIE23_Pos) /**< (CAN_TXBCIE) Cancellation Finished Interrupt Enable 23 Mask */ -#define CAN_TXBCIE_CFIE23(value) (CAN_TXBCIE_CFIE23_Msk & ((value) << CAN_TXBCIE_CFIE23_Pos)) -#define CAN_TXBCIE_CFIE24_Pos _U_(24) /**< (CAN_TXBCIE) Cancellation Finished Interrupt Enable 24 Position */ -#define CAN_TXBCIE_CFIE24_Msk (_U_(0x1) << CAN_TXBCIE_CFIE24_Pos) /**< (CAN_TXBCIE) Cancellation Finished Interrupt Enable 24 Mask */ -#define CAN_TXBCIE_CFIE24(value) (CAN_TXBCIE_CFIE24_Msk & ((value) << CAN_TXBCIE_CFIE24_Pos)) -#define CAN_TXBCIE_CFIE25_Pos _U_(25) /**< (CAN_TXBCIE) Cancellation Finished Interrupt Enable 25 Position */ -#define CAN_TXBCIE_CFIE25_Msk (_U_(0x1) << CAN_TXBCIE_CFIE25_Pos) /**< (CAN_TXBCIE) Cancellation Finished Interrupt Enable 25 Mask */ -#define CAN_TXBCIE_CFIE25(value) (CAN_TXBCIE_CFIE25_Msk & ((value) << CAN_TXBCIE_CFIE25_Pos)) -#define CAN_TXBCIE_CFIE26_Pos _U_(26) /**< (CAN_TXBCIE) Cancellation Finished Interrupt Enable 26 Position */ -#define CAN_TXBCIE_CFIE26_Msk (_U_(0x1) << CAN_TXBCIE_CFIE26_Pos) /**< (CAN_TXBCIE) Cancellation Finished Interrupt Enable 26 Mask */ -#define CAN_TXBCIE_CFIE26(value) (CAN_TXBCIE_CFIE26_Msk & ((value) << CAN_TXBCIE_CFIE26_Pos)) -#define CAN_TXBCIE_CFIE27_Pos _U_(27) /**< (CAN_TXBCIE) Cancellation Finished Interrupt Enable 27 Position */ -#define CAN_TXBCIE_CFIE27_Msk (_U_(0x1) << CAN_TXBCIE_CFIE27_Pos) /**< (CAN_TXBCIE) Cancellation Finished Interrupt Enable 27 Mask */ -#define CAN_TXBCIE_CFIE27(value) (CAN_TXBCIE_CFIE27_Msk & ((value) << CAN_TXBCIE_CFIE27_Pos)) -#define CAN_TXBCIE_CFIE28_Pos _U_(28) /**< (CAN_TXBCIE) Cancellation Finished Interrupt Enable 28 Position */ -#define CAN_TXBCIE_CFIE28_Msk (_U_(0x1) << CAN_TXBCIE_CFIE28_Pos) /**< (CAN_TXBCIE) Cancellation Finished Interrupt Enable 28 Mask */ -#define CAN_TXBCIE_CFIE28(value) (CAN_TXBCIE_CFIE28_Msk & ((value) << CAN_TXBCIE_CFIE28_Pos)) -#define CAN_TXBCIE_CFIE29_Pos _U_(29) /**< (CAN_TXBCIE) Cancellation Finished Interrupt Enable 29 Position */ -#define CAN_TXBCIE_CFIE29_Msk (_U_(0x1) << CAN_TXBCIE_CFIE29_Pos) /**< (CAN_TXBCIE) Cancellation Finished Interrupt Enable 29 Mask */ -#define CAN_TXBCIE_CFIE29(value) (CAN_TXBCIE_CFIE29_Msk & ((value) << CAN_TXBCIE_CFIE29_Pos)) -#define CAN_TXBCIE_CFIE30_Pos _U_(30) /**< (CAN_TXBCIE) Cancellation Finished Interrupt Enable 30 Position */ -#define CAN_TXBCIE_CFIE30_Msk (_U_(0x1) << CAN_TXBCIE_CFIE30_Pos) /**< (CAN_TXBCIE) Cancellation Finished Interrupt Enable 30 Mask */ -#define CAN_TXBCIE_CFIE30(value) (CAN_TXBCIE_CFIE30_Msk & ((value) << CAN_TXBCIE_CFIE30_Pos)) -#define CAN_TXBCIE_CFIE31_Pos _U_(31) /**< (CAN_TXBCIE) Cancellation Finished Interrupt Enable 31 Position */ -#define CAN_TXBCIE_CFIE31_Msk (_U_(0x1) << CAN_TXBCIE_CFIE31_Pos) /**< (CAN_TXBCIE) Cancellation Finished Interrupt Enable 31 Mask */ -#define CAN_TXBCIE_CFIE31(value) (CAN_TXBCIE_CFIE31_Msk & ((value) << CAN_TXBCIE_CFIE31_Pos)) -#define CAN_TXBCIE_Msk _U_(0xFFFFFFFF) /**< (CAN_TXBCIE) Register Mask */ - -#define CAN_TXBCIE_CFIE_Pos _U_(0) /**< (CAN_TXBCIE Position) Cancellation Finished Interrupt Enable 3x */ -#define CAN_TXBCIE_CFIE_Msk (_U_(0xFFFFFFFF) << CAN_TXBCIE_CFIE_Pos) /**< (CAN_TXBCIE Mask) CFIE */ -#define CAN_TXBCIE_CFIE(value) (CAN_TXBCIE_CFIE_Msk & ((value) << CAN_TXBCIE_CFIE_Pos)) - -/* -------- CAN_TXEFC : (CAN Offset: 0xF0) (R/W 32) Tx Event FIFO Configuration -------- */ -#define CAN_TXEFC_RESETVALUE _U_(0x00) /**< (CAN_TXEFC) Tx Event FIFO Configuration Reset Value */ - -#define CAN_TXEFC_EFSA_Pos _U_(0) /**< (CAN_TXEFC) Event FIFO Start Address Position */ -#define CAN_TXEFC_EFSA_Msk (_U_(0xFFFF) << CAN_TXEFC_EFSA_Pos) /**< (CAN_TXEFC) Event FIFO Start Address Mask */ -#define CAN_TXEFC_EFSA(value) (CAN_TXEFC_EFSA_Msk & ((value) << CAN_TXEFC_EFSA_Pos)) -#define CAN_TXEFC_EFS_Pos _U_(16) /**< (CAN_TXEFC) Event FIFO Size Position */ -#define CAN_TXEFC_EFS_Msk (_U_(0x3F) << CAN_TXEFC_EFS_Pos) /**< (CAN_TXEFC) Event FIFO Size Mask */ -#define CAN_TXEFC_EFS(value) (CAN_TXEFC_EFS_Msk & ((value) << CAN_TXEFC_EFS_Pos)) -#define CAN_TXEFC_EFWM_Pos _U_(24) /**< (CAN_TXEFC) Event FIFO Watermark Position */ -#define CAN_TXEFC_EFWM_Msk (_U_(0x3F) << CAN_TXEFC_EFWM_Pos) /**< (CAN_TXEFC) Event FIFO Watermark Mask */ -#define CAN_TXEFC_EFWM(value) (CAN_TXEFC_EFWM_Msk & ((value) << CAN_TXEFC_EFWM_Pos)) -#define CAN_TXEFC_Msk _U_(0x3F3FFFFF) /**< (CAN_TXEFC) Register Mask */ - - -/* -------- CAN_TXEFS : (CAN Offset: 0xF4) ( R/ 32) Tx Event FIFO Status -------- */ -#define CAN_TXEFS_RESETVALUE _U_(0x00) /**< (CAN_TXEFS) Tx Event FIFO Status Reset Value */ - -#define CAN_TXEFS_EFFL_Pos _U_(0) /**< (CAN_TXEFS) Event FIFO Fill Level Position */ -#define CAN_TXEFS_EFFL_Msk (_U_(0x3F) << CAN_TXEFS_EFFL_Pos) /**< (CAN_TXEFS) Event FIFO Fill Level Mask */ -#define CAN_TXEFS_EFFL(value) (CAN_TXEFS_EFFL_Msk & ((value) << CAN_TXEFS_EFFL_Pos)) -#define CAN_TXEFS_EFGI_Pos _U_(8) /**< (CAN_TXEFS) Event FIFO Get Index Position */ -#define CAN_TXEFS_EFGI_Msk (_U_(0x1F) << CAN_TXEFS_EFGI_Pos) /**< (CAN_TXEFS) Event FIFO Get Index Mask */ -#define CAN_TXEFS_EFGI(value) (CAN_TXEFS_EFGI_Msk & ((value) << CAN_TXEFS_EFGI_Pos)) -#define CAN_TXEFS_EFPI_Pos _U_(16) /**< (CAN_TXEFS) Event FIFO Put Index Position */ -#define CAN_TXEFS_EFPI_Msk (_U_(0x1F) << CAN_TXEFS_EFPI_Pos) /**< (CAN_TXEFS) Event FIFO Put Index Mask */ -#define CAN_TXEFS_EFPI(value) (CAN_TXEFS_EFPI_Msk & ((value) << CAN_TXEFS_EFPI_Pos)) -#define CAN_TXEFS_EFF_Pos _U_(24) /**< (CAN_TXEFS) Event FIFO Full Position */ -#define CAN_TXEFS_EFF_Msk (_U_(0x1) << CAN_TXEFS_EFF_Pos) /**< (CAN_TXEFS) Event FIFO Full Mask */ -#define CAN_TXEFS_EFF(value) (CAN_TXEFS_EFF_Msk & ((value) << CAN_TXEFS_EFF_Pos)) -#define CAN_TXEFS_TEFL_Pos _U_(25) /**< (CAN_TXEFS) Tx Event FIFO Element Lost Position */ -#define CAN_TXEFS_TEFL_Msk (_U_(0x1) << CAN_TXEFS_TEFL_Pos) /**< (CAN_TXEFS) Tx Event FIFO Element Lost Mask */ -#define CAN_TXEFS_TEFL(value) (CAN_TXEFS_TEFL_Msk & ((value) << CAN_TXEFS_TEFL_Pos)) -#define CAN_TXEFS_Msk _U_(0x031F1F3F) /**< (CAN_TXEFS) Register Mask */ - - -/* -------- CAN_TXEFA : (CAN Offset: 0xF8) (R/W 32) Tx Event FIFO Acknowledge -------- */ -#define CAN_TXEFA_RESETVALUE _U_(0x00) /**< (CAN_TXEFA) Tx Event FIFO Acknowledge Reset Value */ - -#define CAN_TXEFA_EFAI_Pos _U_(0) /**< (CAN_TXEFA) Event FIFO Acknowledge Index Position */ -#define CAN_TXEFA_EFAI_Msk (_U_(0x1F) << CAN_TXEFA_EFAI_Pos) /**< (CAN_TXEFA) Event FIFO Acknowledge Index Mask */ -#define CAN_TXEFA_EFAI(value) (CAN_TXEFA_EFAI_Msk & ((value) << CAN_TXEFA_EFAI_Pos)) -#define CAN_TXEFA_Msk _U_(0x0000001F) /**< (CAN_TXEFA) Register Mask */ - - -/** \brief CAN register offsets definitions */ -#define CAN_RXBE_0_REG_OFST (0x00) /**< (CAN_RXBE_0) Rx Buffer Element 0 Offset */ -#define CAN_RXBE_1_REG_OFST (0x04) /**< (CAN_RXBE_1) Rx Buffer Element 1 Offset */ -#define CAN_RXBE_DATA_REG_OFST (0x08) /**< (CAN_RXBE_DATA) Rx Buffer Element Data Offset */ -#define CAN_RXF0E_0_REG_OFST (0x00) /**< (CAN_RXF0E_0) Rx FIFO 0 Element 0 Offset */ -#define CAN_RXF0E_1_REG_OFST (0x04) /**< (CAN_RXF0E_1) Rx FIFO 0 Element 1 Offset */ -#define CAN_RXF0E_DATA_REG_OFST (0x08) /**< (CAN_RXF0E_DATA) Rx FIFO 0 Element Data Offset */ -#define CAN_RXF1E_0_REG_OFST (0x00) /**< (CAN_RXF1E_0) Rx FIFO 1 Element 0 Offset */ -#define CAN_RXF1E_1_REG_OFST (0x04) /**< (CAN_RXF1E_1) Rx FIFO 1 Element 1 Offset */ -#define CAN_RXF1E_DATA_REG_OFST (0x08) /**< (CAN_RXF1E_DATA) Rx FIFO 1 Element Data Offset */ -#define CAN_TXBE_0_REG_OFST (0x00) /**< (CAN_TXBE_0) Tx Buffer Element 0 Offset */ -#define CAN_TXBE_1_REG_OFST (0x04) /**< (CAN_TXBE_1) Tx Buffer Element 1 Offset */ -#define CAN_TXBE_DATA_REG_OFST (0x08) /**< (CAN_TXBE_DATA) Tx Buffer Element Data Offset */ -#define CAN_TXEFE_0_REG_OFST (0x00) /**< (CAN_TXEFE_0) Tx Event FIFO Element 0 Offset */ -#define CAN_TXEFE_1_REG_OFST (0x04) /**< (CAN_TXEFE_1) Tx Event FIFO Element 1 Offset */ -#define CAN_SIDFE_0_REG_OFST (0x00) /**< (CAN_SIDFE_0) Standard Message ID Filter Element 0 Offset */ -#define CAN_XIDFE_0_REG_OFST (0x00) /**< (CAN_XIDFE_0) Extended Message ID Filter Element 0 Offset */ -#define CAN_XIDFE_1_REG_OFST (0x04) /**< (CAN_XIDFE_1) Extended Message ID Filter Element 1 Offset */ -#define CAN_CREL_REG_OFST (0x00) /**< (CAN_CREL) Core Release Offset */ -#define CAN_ENDN_REG_OFST (0x04) /**< (CAN_ENDN) Endian Offset */ -#define CAN_MRCFG_REG_OFST (0x08) /**< (CAN_MRCFG) Message RAM Configuration Offset */ -#define CAN_DBTP_REG_OFST (0x0C) /**< (CAN_DBTP) Fast Bit Timing and Prescaler Offset */ -#define CAN_TEST_REG_OFST (0x10) /**< (CAN_TEST) Test Offset */ -#define CAN_RWD_REG_OFST (0x14) /**< (CAN_RWD) RAM Watchdog Offset */ -#define CAN_CCCR_REG_OFST (0x18) /**< (CAN_CCCR) CC Control Offset */ -#define CAN_NBTP_REG_OFST (0x1C) /**< (CAN_NBTP) Nominal Bit Timing and Prescaler Offset */ -#define CAN_TSCC_REG_OFST (0x20) /**< (CAN_TSCC) Timestamp Counter Configuration Offset */ -#define CAN_TSCV_REG_OFST (0x24) /**< (CAN_TSCV) Timestamp Counter Value Offset */ -#define CAN_TOCC_REG_OFST (0x28) /**< (CAN_TOCC) Timeout Counter Configuration Offset */ -#define CAN_TOCV_REG_OFST (0x2C) /**< (CAN_TOCV) Timeout Counter Value Offset */ -#define CAN_ECR_REG_OFST (0x40) /**< (CAN_ECR) Error Counter Offset */ -#define CAN_PSR_REG_OFST (0x44) /**< (CAN_PSR) Protocol Status Offset */ -#define CAN_TDCR_REG_OFST (0x48) /**< (CAN_TDCR) Extended ID Filter Configuration Offset */ -#define CAN_IR_REG_OFST (0x50) /**< (CAN_IR) Interrupt Offset */ -#define CAN_IE_REG_OFST (0x54) /**< (CAN_IE) Interrupt Enable Offset */ -#define CAN_ILS_REG_OFST (0x58) /**< (CAN_ILS) Interrupt Line Select Offset */ -#define CAN_ILE_REG_OFST (0x5C) /**< (CAN_ILE) Interrupt Line Enable Offset */ -#define CAN_GFC_REG_OFST (0x80) /**< (CAN_GFC) Global Filter Configuration Offset */ -#define CAN_SIDFC_REG_OFST (0x84) /**< (CAN_SIDFC) Standard ID Filter Configuration Offset */ -#define CAN_XIDFC_REG_OFST (0x88) /**< (CAN_XIDFC) Extended ID Filter Configuration Offset */ -#define CAN_XIDAM_REG_OFST (0x90) /**< (CAN_XIDAM) Extended ID AND Mask Offset */ -#define CAN_HPMS_REG_OFST (0x94) /**< (CAN_HPMS) High Priority Message Status Offset */ -#define CAN_NDAT1_REG_OFST (0x98) /**< (CAN_NDAT1) New Data 1 Offset */ -#define CAN_NDAT2_REG_OFST (0x9C) /**< (CAN_NDAT2) New Data 2 Offset */ -#define CAN_RXF0C_REG_OFST (0xA0) /**< (CAN_RXF0C) Rx FIFO 0 Configuration Offset */ -#define CAN_RXF0S_REG_OFST (0xA4) /**< (CAN_RXF0S) Rx FIFO 0 Status Offset */ -#define CAN_RXF0A_REG_OFST (0xA8) /**< (CAN_RXF0A) Rx FIFO 0 Acknowledge Offset */ -#define CAN_RXBC_REG_OFST (0xAC) /**< (CAN_RXBC) Rx Buffer Configuration Offset */ -#define CAN_RXF1C_REG_OFST (0xB0) /**< (CAN_RXF1C) Rx FIFO 1 Configuration Offset */ -#define CAN_RXF1S_REG_OFST (0xB4) /**< (CAN_RXF1S) Rx FIFO 1 Status Offset */ -#define CAN_RXF1A_REG_OFST (0xB8) /**< (CAN_RXF1A) Rx FIFO 1 Acknowledge Offset */ -#define CAN_RXESC_REG_OFST (0xBC) /**< (CAN_RXESC) Rx Buffer / FIFO Element Size Configuration Offset */ -#define CAN_TXBC_REG_OFST (0xC0) /**< (CAN_TXBC) Tx Buffer Configuration Offset */ -#define CAN_TXFQS_REG_OFST (0xC4) /**< (CAN_TXFQS) Tx FIFO / Queue Status Offset */ -#define CAN_TXESC_REG_OFST (0xC8) /**< (CAN_TXESC) Tx Buffer Element Size Configuration Offset */ -#define CAN_TXBRP_REG_OFST (0xCC) /**< (CAN_TXBRP) Tx Buffer Request Pending Offset */ -#define CAN_TXBAR_REG_OFST (0xD0) /**< (CAN_TXBAR) Tx Buffer Add Request Offset */ -#define CAN_TXBCR_REG_OFST (0xD4) /**< (CAN_TXBCR) Tx Buffer Cancellation Request Offset */ -#define CAN_TXBTO_REG_OFST (0xD8) /**< (CAN_TXBTO) Tx Buffer Transmission Occurred Offset */ -#define CAN_TXBCF_REG_OFST (0xDC) /**< (CAN_TXBCF) Tx Buffer Cancellation Finished Offset */ -#define CAN_TXBTIE_REG_OFST (0xE0) /**< (CAN_TXBTIE) Tx Buffer Transmission Interrupt Enable Offset */ -#define CAN_TXBCIE_REG_OFST (0xE4) /**< (CAN_TXBCIE) Tx Buffer Cancellation Finished Interrupt Enable Offset */ -#define CAN_TXEFC_REG_OFST (0xF0) /**< (CAN_TXEFC) Tx Event FIFO Configuration Offset */ -#define CAN_TXEFS_REG_OFST (0xF4) /**< (CAN_TXEFS) Tx Event FIFO Status Offset */ -#define CAN_TXEFA_REG_OFST (0xF8) /**< (CAN_TXEFA) Tx Event FIFO Acknowledge Offset */ - -#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) -/** \brief CAN_RXBE register API structure */ -typedef struct -{ /* Rx Buffer Element */ - __IO uint32_t CAN_RXBE_0; /**< Offset: 0x00 (R/W 32) Rx Buffer Element 0 */ - __IO uint32_t CAN_RXBE_1; /**< Offset: 0x04 (R/W 32) Rx Buffer Element 1 */ - __IO uint32_t CAN_RXBE_DATA; /**< Offset: 0x08 (R/W 32) Rx Buffer Element Data */ -} can_rxbe_registers_t -#ifdef __GNUC__ - __attribute__ ((aligned (4))) -#endif -; - -/** \brief CAN_RXF0E register API structure */ -typedef struct -{ /* Rx FIFO 0 Element */ - __IO uint32_t CAN_RXF0E_0; /**< Offset: 0x00 (R/W 32) Rx FIFO 0 Element 0 */ - __IO uint32_t CAN_RXF0E_1; /**< Offset: 0x04 (R/W 32) Rx FIFO 0 Element 1 */ - __IO uint32_t CAN_RXF0E_DATA; /**< Offset: 0x08 (R/W 32) Rx FIFO 0 Element Data */ -} can_rxf0e_registers_t -#ifdef __GNUC__ - __attribute__ ((aligned (4))) -#endif -; - -/** \brief CAN_RXF1E register API structure */ -typedef struct -{ /* Rx FIFO 1 Element */ - __IO uint32_t CAN_RXF1E_0; /**< Offset: 0x00 (R/W 32) Rx FIFO 1 Element 0 */ - __IO uint32_t CAN_RXF1E_1; /**< Offset: 0x04 (R/W 32) Rx FIFO 1 Element 1 */ - __IO uint32_t CAN_RXF1E_DATA; /**< Offset: 0x08 (R/W 32) Rx FIFO 1 Element Data */ -} can_rxf1e_registers_t -#ifdef __GNUC__ - __attribute__ ((aligned (4))) -#endif -; - -/** \brief CAN_TXBE register API structure */ -typedef struct -{ /* Tx Buffer Element */ - __IO uint32_t CAN_TXBE_0; /**< Offset: 0x00 (R/W 32) Tx Buffer Element 0 */ - __IO uint32_t CAN_TXBE_1; /**< Offset: 0x04 (R/W 32) Tx Buffer Element 1 */ - __IO uint32_t CAN_TXBE_DATA; /**< Offset: 0x08 (R/W 32) Tx Buffer Element Data */ -} can_txbe_registers_t -#ifdef __GNUC__ - __attribute__ ((aligned (4))) -#endif -; - -/** \brief CAN_TXEFE register API structure */ -typedef struct -{ /* Tx Event FIFO Element */ - __IO uint32_t CAN_TXEFE_0; /**< Offset: 0x00 (R/W 32) Tx Event FIFO Element 0 */ - __IO uint32_t CAN_TXEFE_1; /**< Offset: 0x04 (R/W 32) Tx Event FIFO Element 1 */ -} can_txefe_registers_t -#ifdef __GNUC__ - __attribute__ ((aligned (4))) -#endif -; - -/** \brief CAN_SIDFE register API structure */ -typedef struct -{ /* Standard Message ID Filter Element */ - __IO uint32_t CAN_SIDFE_0; /**< Offset: 0x00 (R/W 32) Standard Message ID Filter Element 0 */ -} can_sidfe_registers_t -#ifdef __GNUC__ - __attribute__ ((aligned (4))) -#endif -; - -/** \brief CAN_XIDFE register API structure */ -typedef struct -{ /* Extended Message ID Filter Element */ - __IO uint32_t CAN_XIDFE_0; /**< Offset: 0x00 (R/W 32) Extended Message ID Filter Element 0 */ - __IO uint32_t CAN_XIDFE_1; /**< Offset: 0x04 (R/W 32) Extended Message ID Filter Element 1 */ -} can_xidfe_registers_t -#ifdef __GNUC__ - __attribute__ ((aligned (4))) -#endif -; - -/** \brief CAN register API structure */ -typedef struct -{ /* Control Area Network */ - __I uint32_t CAN_CREL; /**< Offset: 0x00 (R/ 32) Core Release */ - __I uint32_t CAN_ENDN; /**< Offset: 0x04 (R/ 32) Endian */ - __IO uint32_t CAN_MRCFG; /**< Offset: 0x08 (R/W 32) Message RAM Configuration */ - __IO uint32_t CAN_DBTP; /**< Offset: 0x0C (R/W 32) Fast Bit Timing and Prescaler */ - __IO uint32_t CAN_TEST; /**< Offset: 0x10 (R/W 32) Test */ - __IO uint32_t CAN_RWD; /**< Offset: 0x14 (R/W 32) RAM Watchdog */ - __IO uint32_t CAN_CCCR; /**< Offset: 0x18 (R/W 32) CC Control */ - __IO uint32_t CAN_NBTP; /**< Offset: 0x1C (R/W 32) Nominal Bit Timing and Prescaler */ - __IO uint32_t CAN_TSCC; /**< Offset: 0x20 (R/W 32) Timestamp Counter Configuration */ - __I uint32_t CAN_TSCV; /**< Offset: 0x24 (R/ 32) Timestamp Counter Value */ - __IO uint32_t CAN_TOCC; /**< Offset: 0x28 (R/W 32) Timeout Counter Configuration */ - __IO uint32_t CAN_TOCV; /**< Offset: 0x2C (R/W 32) Timeout Counter Value */ - __I uint8_t Reserved1[0x10]; - __I uint32_t CAN_ECR; /**< Offset: 0x40 (R/ 32) Error Counter */ - __I uint32_t CAN_PSR; /**< Offset: 0x44 (R/ 32) Protocol Status */ - __IO uint32_t CAN_TDCR; /**< Offset: 0x48 (R/W 32) Extended ID Filter Configuration */ - __I uint8_t Reserved2[0x04]; - __IO uint32_t CAN_IR; /**< Offset: 0x50 (R/W 32) Interrupt */ - __IO uint32_t CAN_IE; /**< Offset: 0x54 (R/W 32) Interrupt Enable */ - __IO uint32_t CAN_ILS; /**< Offset: 0x58 (R/W 32) Interrupt Line Select */ - __IO uint32_t CAN_ILE; /**< Offset: 0x5C (R/W 32) Interrupt Line Enable */ - __I uint8_t Reserved3[0x20]; - __IO uint32_t CAN_GFC; /**< Offset: 0x80 (R/W 32) Global Filter Configuration */ - __IO uint32_t CAN_SIDFC; /**< Offset: 0x84 (R/W 32) Standard ID Filter Configuration */ - __IO uint32_t CAN_XIDFC; /**< Offset: 0x88 (R/W 32) Extended ID Filter Configuration */ - __I uint8_t Reserved4[0x04]; - __IO uint32_t CAN_XIDAM; /**< Offset: 0x90 (R/W 32) Extended ID AND Mask */ - __I uint32_t CAN_HPMS; /**< Offset: 0x94 (R/ 32) High Priority Message Status */ - __IO uint32_t CAN_NDAT1; /**< Offset: 0x98 (R/W 32) New Data 1 */ - __IO uint32_t CAN_NDAT2; /**< Offset: 0x9C (R/W 32) New Data 2 */ - __IO uint32_t CAN_RXF0C; /**< Offset: 0xA0 (R/W 32) Rx FIFO 0 Configuration */ - __I uint32_t CAN_RXF0S; /**< Offset: 0xA4 (R/ 32) Rx FIFO 0 Status */ - __IO uint32_t CAN_RXF0A; /**< Offset: 0xA8 (R/W 32) Rx FIFO 0 Acknowledge */ - __IO uint32_t CAN_RXBC; /**< Offset: 0xAC (R/W 32) Rx Buffer Configuration */ - __IO uint32_t CAN_RXF1C; /**< Offset: 0xB0 (R/W 32) Rx FIFO 1 Configuration */ - __I uint32_t CAN_RXF1S; /**< Offset: 0xB4 (R/ 32) Rx FIFO 1 Status */ - __IO uint32_t CAN_RXF1A; /**< Offset: 0xB8 (R/W 32) Rx FIFO 1 Acknowledge */ - __IO uint32_t CAN_RXESC; /**< Offset: 0xBC (R/W 32) Rx Buffer / FIFO Element Size Configuration */ - __IO uint32_t CAN_TXBC; /**< Offset: 0xC0 (R/W 32) Tx Buffer Configuration */ - __I uint32_t CAN_TXFQS; /**< Offset: 0xC4 (R/ 32) Tx FIFO / Queue Status */ - __IO uint32_t CAN_TXESC; /**< Offset: 0xC8 (R/W 32) Tx Buffer Element Size Configuration */ - __I uint32_t CAN_TXBRP; /**< Offset: 0xCC (R/ 32) Tx Buffer Request Pending */ - __IO uint32_t CAN_TXBAR; /**< Offset: 0xD0 (R/W 32) Tx Buffer Add Request */ - __IO uint32_t CAN_TXBCR; /**< Offset: 0xD4 (R/W 32) Tx Buffer Cancellation Request */ - __I uint32_t CAN_TXBTO; /**< Offset: 0xD8 (R/ 32) Tx Buffer Transmission Occurred */ - __I uint32_t CAN_TXBCF; /**< Offset: 0xDC (R/ 32) Tx Buffer Cancellation Finished */ - __IO uint32_t CAN_TXBTIE; /**< Offset: 0xE0 (R/W 32) Tx Buffer Transmission Interrupt Enable */ - __IO uint32_t CAN_TXBCIE; /**< Offset: 0xE4 (R/W 32) Tx Buffer Cancellation Finished Interrupt Enable */ - __I uint8_t Reserved5[0x08]; - __IO uint32_t CAN_TXEFC; /**< Offset: 0xF0 (R/W 32) Tx Event FIFO Configuration */ - __I uint32_t CAN_TXEFS; /**< Offset: 0xF4 (R/ 32) Tx Event FIFO Status */ - __IO uint32_t CAN_TXEFA; /**< Offset: 0xF8 (R/W 32) Tx Event FIFO Acknowledge */ -} can_registers_t; - - -#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ -#endif /* _SAME54_CAN_COMPONENT_H_ */ +/** + * \file + * + * \brief Component description for CAN + * + * Copyright (c) 2019 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAME54_CAN_COMPONENT_ +#define _SAME54_CAN_COMPONENT_ + +/* ========================================================================== */ +/** SOFTWARE API DEFINITION FOR CAN */ +/* ========================================================================== */ +/** \addtogroup SAME54_CAN Control Area Network */ +/*@{*/ + +#define CAN_U2003 +#define REV_CAN 0x321 + +/* -------- CAN_CREL : (CAN Offset: 0x00) (R/ 32) Core Release -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t :20; /*!< bit: 0..19 Reserved */ + uint32_t SUBSTEP:4; /*!< bit: 20..23 Sub-step of Core Release */ + uint32_t STEP:4; /*!< bit: 24..27 Step of Core Release */ + uint32_t REL:4; /*!< bit: 28..31 Core Release */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_CREL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_CREL_OFFSET 0x00 /**< \brief (CAN_CREL offset) Core Release */ +#define CAN_CREL_RESETVALUE _U_(0x32100000) /**< \brief (CAN_CREL reset_value) Core Release */ + +#define CAN_CREL_SUBSTEP_Pos 20 /**< \brief (CAN_CREL) Sub-step of Core Release */ +#define CAN_CREL_SUBSTEP_Msk (_U_(0xF) << CAN_CREL_SUBSTEP_Pos) +#define CAN_CREL_SUBSTEP(value) (CAN_CREL_SUBSTEP_Msk & ((value) << CAN_CREL_SUBSTEP_Pos)) +#define CAN_CREL_STEP_Pos 24 /**< \brief (CAN_CREL) Step of Core Release */ +#define CAN_CREL_STEP_Msk (_U_(0xF) << CAN_CREL_STEP_Pos) +#define CAN_CREL_STEP(value) (CAN_CREL_STEP_Msk & ((value) << CAN_CREL_STEP_Pos)) +#define CAN_CREL_REL_Pos 28 /**< \brief (CAN_CREL) Core Release */ +#define CAN_CREL_REL_Msk (_U_(0xF) << CAN_CREL_REL_Pos) +#define CAN_CREL_REL(value) (CAN_CREL_REL_Msk & ((value) << CAN_CREL_REL_Pos)) +#define CAN_CREL_MASK _U_(0xFFF00000) /**< \brief (CAN_CREL) MASK Register */ + +/* -------- CAN_ENDN : (CAN Offset: 0x04) (R/ 32) Endian -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t ETV:32; /*!< bit: 0..31 Endianness Test Value */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_ENDN_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_ENDN_OFFSET 0x04 /**< \brief (CAN_ENDN offset) Endian */ +#define CAN_ENDN_RESETVALUE _U_(0x87654321) /**< \brief (CAN_ENDN reset_value) Endian */ + +#define CAN_ENDN_ETV_Pos 0 /**< \brief (CAN_ENDN) Endianness Test Value */ +#define CAN_ENDN_ETV_Msk (_U_(0xFFFFFFFF) << CAN_ENDN_ETV_Pos) +#define CAN_ENDN_ETV(value) (CAN_ENDN_ETV_Msk & ((value) << CAN_ENDN_ETV_Pos)) +#define CAN_ENDN_MASK _U_(0xFFFFFFFF) /**< \brief (CAN_ENDN) MASK Register */ + +/* -------- CAN_MRCFG : (CAN Offset: 0x08) (R/W 32) Message RAM Configuration -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t QOS:2; /*!< bit: 0.. 1 Quality of Service */ + uint32_t :30; /*!< bit: 2..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_MRCFG_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_MRCFG_OFFSET 0x08 /**< \brief (CAN_MRCFG offset) Message RAM Configuration */ +#define CAN_MRCFG_RESETVALUE _U_(0x00000002) /**< \brief (CAN_MRCFG reset_value) Message RAM Configuration */ + +#define CAN_MRCFG_QOS_Pos 0 /**< \brief (CAN_MRCFG) Quality of Service */ +#define CAN_MRCFG_QOS_Msk (_U_(0x3) << CAN_MRCFG_QOS_Pos) +#define CAN_MRCFG_QOS(value) (CAN_MRCFG_QOS_Msk & ((value) << CAN_MRCFG_QOS_Pos)) +#define CAN_MRCFG_QOS_DISABLE_Val _U_(0x0) /**< \brief (CAN_MRCFG) Background (no sensitive operation) */ +#define CAN_MRCFG_QOS_LOW_Val _U_(0x1) /**< \brief (CAN_MRCFG) Sensitive Bandwidth */ +#define CAN_MRCFG_QOS_MEDIUM_Val _U_(0x2) /**< \brief (CAN_MRCFG) Sensitive Latency */ +#define CAN_MRCFG_QOS_HIGH_Val _U_(0x3) /**< \brief (CAN_MRCFG) Critical Latency */ +#define CAN_MRCFG_QOS_DISABLE (CAN_MRCFG_QOS_DISABLE_Val << CAN_MRCFG_QOS_Pos) +#define CAN_MRCFG_QOS_LOW (CAN_MRCFG_QOS_LOW_Val << CAN_MRCFG_QOS_Pos) +#define CAN_MRCFG_QOS_MEDIUM (CAN_MRCFG_QOS_MEDIUM_Val << CAN_MRCFG_QOS_Pos) +#define CAN_MRCFG_QOS_HIGH (CAN_MRCFG_QOS_HIGH_Val << CAN_MRCFG_QOS_Pos) +#define CAN_MRCFG_MASK _U_(0x00000003) /**< \brief (CAN_MRCFG) MASK Register */ + +/* -------- CAN_DBTP : (CAN Offset: 0x0C) (R/W 32) Fast Bit Timing and Prescaler -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t DSJW:4; /*!< bit: 0.. 3 Data (Re)Synchronization Jump Width */ + uint32_t DTSEG2:4; /*!< bit: 4.. 7 Data time segment after sample point */ + uint32_t DTSEG1:5; /*!< bit: 8..12 Data time segment before sample point */ + uint32_t :3; /*!< bit: 13..15 Reserved */ + uint32_t DBRP:5; /*!< bit: 16..20 Data Baud Rate Prescaler */ + uint32_t :2; /*!< bit: 21..22 Reserved */ + uint32_t TDC:1; /*!< bit: 23 Tranceiver Delay Compensation */ + uint32_t :8; /*!< bit: 24..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_DBTP_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_DBTP_OFFSET 0x0C /**< \brief (CAN_DBTP offset) Fast Bit Timing and Prescaler */ +#define CAN_DBTP_RESETVALUE _U_(0x00000A33) /**< \brief (CAN_DBTP reset_value) Fast Bit Timing and Prescaler */ + +#define CAN_DBTP_DSJW_Pos 0 /**< \brief (CAN_DBTP) Data (Re)Synchronization Jump Width */ +#define CAN_DBTP_DSJW_Msk (_U_(0xF) << CAN_DBTP_DSJW_Pos) +#define CAN_DBTP_DSJW(value) (CAN_DBTP_DSJW_Msk & ((value) << CAN_DBTP_DSJW_Pos)) +#define CAN_DBTP_DTSEG2_Pos 4 /**< \brief (CAN_DBTP) Data time segment after sample point */ +#define CAN_DBTP_DTSEG2_Msk (_U_(0xF) << CAN_DBTP_DTSEG2_Pos) +#define CAN_DBTP_DTSEG2(value) (CAN_DBTP_DTSEG2_Msk & ((value) << CAN_DBTP_DTSEG2_Pos)) +#define CAN_DBTP_DTSEG1_Pos 8 /**< \brief (CAN_DBTP) Data time segment before sample point */ +#define CAN_DBTP_DTSEG1_Msk (_U_(0x1F) << CAN_DBTP_DTSEG1_Pos) +#define CAN_DBTP_DTSEG1(value) (CAN_DBTP_DTSEG1_Msk & ((value) << CAN_DBTP_DTSEG1_Pos)) +#define CAN_DBTP_DBRP_Pos 16 /**< \brief (CAN_DBTP) Data Baud Rate Prescaler */ +#define CAN_DBTP_DBRP_Msk (_U_(0x1F) << CAN_DBTP_DBRP_Pos) +#define CAN_DBTP_DBRP(value) (CAN_DBTP_DBRP_Msk & ((value) << CAN_DBTP_DBRP_Pos)) +#define CAN_DBTP_TDC_Pos 23 /**< \brief (CAN_DBTP) Tranceiver Delay Compensation */ +#define CAN_DBTP_TDC (_U_(0x1) << CAN_DBTP_TDC_Pos) +#define CAN_DBTP_MASK _U_(0x009F1FFF) /**< \brief (CAN_DBTP) MASK Register */ + +/* -------- CAN_TEST : (CAN Offset: 0x10) (R/W 32) Test -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t :4; /*!< bit: 0.. 3 Reserved */ + uint32_t LBCK:1; /*!< bit: 4 Loop Back Mode */ + uint32_t TX:2; /*!< bit: 5.. 6 Control of Transmit Pin */ + uint32_t RX:1; /*!< bit: 7 Receive Pin */ + uint32_t :24; /*!< bit: 8..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_TEST_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_TEST_OFFSET 0x10 /**< \brief (CAN_TEST offset) Test */ +#define CAN_TEST_RESETVALUE _U_(0x00000000) /**< \brief (CAN_TEST reset_value) Test */ + +#define CAN_TEST_LBCK_Pos 4 /**< \brief (CAN_TEST) Loop Back Mode */ +#define CAN_TEST_LBCK (_U_(0x1) << CAN_TEST_LBCK_Pos) +#define CAN_TEST_TX_Pos 5 /**< \brief (CAN_TEST) Control of Transmit Pin */ +#define CAN_TEST_TX_Msk (_U_(0x3) << CAN_TEST_TX_Pos) +#define CAN_TEST_TX(value) (CAN_TEST_TX_Msk & ((value) << CAN_TEST_TX_Pos)) +#define CAN_TEST_TX_CORE_Val _U_(0x0) /**< \brief (CAN_TEST) TX controlled by CAN core */ +#define CAN_TEST_TX_SAMPLE_Val _U_(0x1) /**< \brief (CAN_TEST) TX monitoring sample point */ +#define CAN_TEST_TX_DOMINANT_Val _U_(0x2) /**< \brief (CAN_TEST) Dominant (0) level at pin CAN_TX */ +#define CAN_TEST_TX_RECESSIVE_Val _U_(0x3) /**< \brief (CAN_TEST) Recessive (1) level at pin CAN_TX */ +#define CAN_TEST_TX_CORE (CAN_TEST_TX_CORE_Val << CAN_TEST_TX_Pos) +#define CAN_TEST_TX_SAMPLE (CAN_TEST_TX_SAMPLE_Val << CAN_TEST_TX_Pos) +#define CAN_TEST_TX_DOMINANT (CAN_TEST_TX_DOMINANT_Val << CAN_TEST_TX_Pos) +#define CAN_TEST_TX_RECESSIVE (CAN_TEST_TX_RECESSIVE_Val << CAN_TEST_TX_Pos) +#define CAN_TEST_RX_Pos 7 /**< \brief (CAN_TEST) Receive Pin */ +#define CAN_TEST_RX (_U_(0x1) << CAN_TEST_RX_Pos) +#define CAN_TEST_MASK _U_(0x000000F0) /**< \brief (CAN_TEST) MASK Register */ + +/* -------- CAN_RWD : (CAN Offset: 0x14) (R/W 32) RAM Watchdog -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t WDC:8; /*!< bit: 0.. 7 Watchdog Configuration */ + uint32_t WDV:8; /*!< bit: 8..15 Watchdog Value */ + uint32_t :16; /*!< bit: 16..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_RWD_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_RWD_OFFSET 0x14 /**< \brief (CAN_RWD offset) RAM Watchdog */ +#define CAN_RWD_RESETVALUE _U_(0x00000000) /**< \brief (CAN_RWD reset_value) RAM Watchdog */ + +#define CAN_RWD_WDC_Pos 0 /**< \brief (CAN_RWD) Watchdog Configuration */ +#define CAN_RWD_WDC_Msk (_U_(0xFF) << CAN_RWD_WDC_Pos) +#define CAN_RWD_WDC(value) (CAN_RWD_WDC_Msk & ((value) << CAN_RWD_WDC_Pos)) +#define CAN_RWD_WDV_Pos 8 /**< \brief (CAN_RWD) Watchdog Value */ +#define CAN_RWD_WDV_Msk (_U_(0xFF) << CAN_RWD_WDV_Pos) +#define CAN_RWD_WDV(value) (CAN_RWD_WDV_Msk & ((value) << CAN_RWD_WDV_Pos)) +#define CAN_RWD_MASK _U_(0x0000FFFF) /**< \brief (CAN_RWD) MASK Register */ + +/* -------- CAN_CCCR : (CAN Offset: 0x18) (R/W 32) CC Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t INIT:1; /*!< bit: 0 Initialization */ + uint32_t CCE:1; /*!< bit: 1 Configuration Change Enable */ + uint32_t ASM:1; /*!< bit: 2 ASM Restricted Operation Mode */ + uint32_t CSA:1; /*!< bit: 3 Clock Stop Acknowledge */ + uint32_t CSR:1; /*!< bit: 4 Clock Stop Request */ + uint32_t MON:1; /*!< bit: 5 Bus Monitoring Mode */ + uint32_t DAR:1; /*!< bit: 6 Disable Automatic Retransmission */ + uint32_t TEST:1; /*!< bit: 7 Test Mode Enable */ + uint32_t FDOE:1; /*!< bit: 8 FD Operation Enable */ + uint32_t BRSE:1; /*!< bit: 9 Bit Rate Switch Enable */ + uint32_t :2; /*!< bit: 10..11 Reserved */ + uint32_t PXHD:1; /*!< bit: 12 Protocol Exception Handling Disable */ + uint32_t EFBI:1; /*!< bit: 13 Edge Filtering during Bus Integration */ + uint32_t TXP:1; /*!< bit: 14 Transmit Pause */ + uint32_t NISO:1; /*!< bit: 15 Non ISO Operation */ + uint32_t :16; /*!< bit: 16..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_CCCR_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_CCCR_OFFSET 0x18 /**< \brief (CAN_CCCR offset) CC Control */ +#define CAN_CCCR_RESETVALUE _U_(0x00000001) /**< \brief (CAN_CCCR reset_value) CC Control */ + +#define CAN_CCCR_INIT_Pos 0 /**< \brief (CAN_CCCR) Initialization */ +#define CAN_CCCR_INIT (_U_(0x1) << CAN_CCCR_INIT_Pos) +#define CAN_CCCR_CCE_Pos 1 /**< \brief (CAN_CCCR) Configuration Change Enable */ +#define CAN_CCCR_CCE (_U_(0x1) << CAN_CCCR_CCE_Pos) +#define CAN_CCCR_ASM_Pos 2 /**< \brief (CAN_CCCR) ASM Restricted Operation Mode */ +#define CAN_CCCR_ASM (_U_(0x1) << CAN_CCCR_ASM_Pos) +#define CAN_CCCR_CSA_Pos 3 /**< \brief (CAN_CCCR) Clock Stop Acknowledge */ +#define CAN_CCCR_CSA (_U_(0x1) << CAN_CCCR_CSA_Pos) +#define CAN_CCCR_CSR_Pos 4 /**< \brief (CAN_CCCR) Clock Stop Request */ +#define CAN_CCCR_CSR (_U_(0x1) << CAN_CCCR_CSR_Pos) +#define CAN_CCCR_MON_Pos 5 /**< \brief (CAN_CCCR) Bus Monitoring Mode */ +#define CAN_CCCR_MON (_U_(0x1) << CAN_CCCR_MON_Pos) +#define CAN_CCCR_DAR_Pos 6 /**< \brief (CAN_CCCR) Disable Automatic Retransmission */ +#define CAN_CCCR_DAR (_U_(0x1) << CAN_CCCR_DAR_Pos) +#define CAN_CCCR_TEST_Pos 7 /**< \brief (CAN_CCCR) Test Mode Enable */ +#define CAN_CCCR_TEST (_U_(0x1) << CAN_CCCR_TEST_Pos) +#define CAN_CCCR_FDOE_Pos 8 /**< \brief (CAN_CCCR) FD Operation Enable */ +#define CAN_CCCR_FDOE (_U_(0x1) << CAN_CCCR_FDOE_Pos) +#define CAN_CCCR_BRSE_Pos 9 /**< \brief (CAN_CCCR) Bit Rate Switch Enable */ +#define CAN_CCCR_BRSE (_U_(0x1) << CAN_CCCR_BRSE_Pos) +#define CAN_CCCR_PXHD_Pos 12 /**< \brief (CAN_CCCR) Protocol Exception Handling Disable */ +#define CAN_CCCR_PXHD (_U_(0x1) << CAN_CCCR_PXHD_Pos) +#define CAN_CCCR_EFBI_Pos 13 /**< \brief (CAN_CCCR) Edge Filtering during Bus Integration */ +#define CAN_CCCR_EFBI (_U_(0x1) << CAN_CCCR_EFBI_Pos) +#define CAN_CCCR_TXP_Pos 14 /**< \brief (CAN_CCCR) Transmit Pause */ +#define CAN_CCCR_TXP (_U_(0x1) << CAN_CCCR_TXP_Pos) +#define CAN_CCCR_NISO_Pos 15 /**< \brief (CAN_CCCR) Non ISO Operation */ +#define CAN_CCCR_NISO (_U_(0x1) << CAN_CCCR_NISO_Pos) +#define CAN_CCCR_MASK _U_(0x0000F3FF) /**< \brief (CAN_CCCR) MASK Register */ + +/* -------- CAN_NBTP : (CAN Offset: 0x1C) (R/W 32) Nominal Bit Timing and Prescaler -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t NTSEG2:7; /*!< bit: 0.. 6 Nominal Time segment after sample point */ + uint32_t :1; /*!< bit: 7 Reserved */ + uint32_t NTSEG1:8; /*!< bit: 8..15 Nominal Time segment before sample point */ + uint32_t NBRP:9; /*!< bit: 16..24 Nominal Baud Rate Prescaler */ + uint32_t NSJW:7; /*!< bit: 25..31 Nominal (Re)Synchronization Jump Width */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_NBTP_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_NBTP_OFFSET 0x1C /**< \brief (CAN_NBTP offset) Nominal Bit Timing and Prescaler */ +#define CAN_NBTP_RESETVALUE _U_(0x06000A03) /**< \brief (CAN_NBTP reset_value) Nominal Bit Timing and Prescaler */ + +#define CAN_NBTP_NTSEG2_Pos 0 /**< \brief (CAN_NBTP) Nominal Time segment after sample point */ +#define CAN_NBTP_NTSEG2_Msk (_U_(0x7F) << CAN_NBTP_NTSEG2_Pos) +#define CAN_NBTP_NTSEG2(value) (CAN_NBTP_NTSEG2_Msk & ((value) << CAN_NBTP_NTSEG2_Pos)) +#define CAN_NBTP_NTSEG1_Pos 8 /**< \brief (CAN_NBTP) Nominal Time segment before sample point */ +#define CAN_NBTP_NTSEG1_Msk (_U_(0xFF) << CAN_NBTP_NTSEG1_Pos) +#define CAN_NBTP_NTSEG1(value) (CAN_NBTP_NTSEG1_Msk & ((value) << CAN_NBTP_NTSEG1_Pos)) +#define CAN_NBTP_NBRP_Pos 16 /**< \brief (CAN_NBTP) Nominal Baud Rate Prescaler */ +#define CAN_NBTP_NBRP_Msk (_U_(0x1FF) << CAN_NBTP_NBRP_Pos) +#define CAN_NBTP_NBRP(value) (CAN_NBTP_NBRP_Msk & ((value) << CAN_NBTP_NBRP_Pos)) +#define CAN_NBTP_NSJW_Pos 25 /**< \brief (CAN_NBTP) Nominal (Re)Synchronization Jump Width */ +#define CAN_NBTP_NSJW_Msk (_U_(0x7F) << CAN_NBTP_NSJW_Pos) +#define CAN_NBTP_NSJW(value) (CAN_NBTP_NSJW_Msk & ((value) << CAN_NBTP_NSJW_Pos)) +#define CAN_NBTP_MASK _U_(0xFFFFFF7F) /**< \brief (CAN_NBTP) MASK Register */ + +/* -------- CAN_TSCC : (CAN Offset: 0x20) (R/W 32) Timestamp Counter Configuration -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t TSS:2; /*!< bit: 0.. 1 Timestamp Select */ + uint32_t :14; /*!< bit: 2..15 Reserved */ + uint32_t TCP:4; /*!< bit: 16..19 Timestamp Counter Prescaler */ + uint32_t :12; /*!< bit: 20..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_TSCC_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_TSCC_OFFSET 0x20 /**< \brief (CAN_TSCC offset) Timestamp Counter Configuration */ +#define CAN_TSCC_RESETVALUE _U_(0x00000000) /**< \brief (CAN_TSCC reset_value) Timestamp Counter Configuration */ + +#define CAN_TSCC_TSS_Pos 0 /**< \brief (CAN_TSCC) Timestamp Select */ +#define CAN_TSCC_TSS_Msk (_U_(0x3) << CAN_TSCC_TSS_Pos) +#define CAN_TSCC_TSS(value) (CAN_TSCC_TSS_Msk & ((value) << CAN_TSCC_TSS_Pos)) +#define CAN_TSCC_TSS_ZERO_Val _U_(0x0) /**< \brief (CAN_TSCC) Timestamp counter value always 0x0000 */ +#define CAN_TSCC_TSS_INC_Val _U_(0x1) /**< \brief (CAN_TSCC) Timestamp counter value incremented by TCP */ +#define CAN_TSCC_TSS_EXT_Val _U_(0x2) /**< \brief (CAN_TSCC) External timestamp counter value used */ +#define CAN_TSCC_TSS_ZERO (CAN_TSCC_TSS_ZERO_Val << CAN_TSCC_TSS_Pos) +#define CAN_TSCC_TSS_INC (CAN_TSCC_TSS_INC_Val << CAN_TSCC_TSS_Pos) +#define CAN_TSCC_TSS_EXT (CAN_TSCC_TSS_EXT_Val << CAN_TSCC_TSS_Pos) +#define CAN_TSCC_TCP_Pos 16 /**< \brief (CAN_TSCC) Timestamp Counter Prescaler */ +#define CAN_TSCC_TCP_Msk (_U_(0xF) << CAN_TSCC_TCP_Pos) +#define CAN_TSCC_TCP(value) (CAN_TSCC_TCP_Msk & ((value) << CAN_TSCC_TCP_Pos)) +#define CAN_TSCC_MASK _U_(0x000F0003) /**< \brief (CAN_TSCC) MASK Register */ + +/* -------- CAN_TSCV : (CAN Offset: 0x24) (R/ 32) Timestamp Counter Value -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t TSC:16; /*!< bit: 0..15 Timestamp Counter */ + uint32_t :16; /*!< bit: 16..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_TSCV_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_TSCV_OFFSET 0x24 /**< \brief (CAN_TSCV offset) Timestamp Counter Value */ +#define CAN_TSCV_RESETVALUE _U_(0x00000000) /**< \brief (CAN_TSCV reset_value) Timestamp Counter Value */ + +#define CAN_TSCV_TSC_Pos 0 /**< \brief (CAN_TSCV) Timestamp Counter */ +#define CAN_TSCV_TSC_Msk (_U_(0xFFFF) << CAN_TSCV_TSC_Pos) +#define CAN_TSCV_TSC(value) (CAN_TSCV_TSC_Msk & ((value) << CAN_TSCV_TSC_Pos)) +#define CAN_TSCV_MASK _U_(0x0000FFFF) /**< \brief (CAN_TSCV) MASK Register */ + +/* -------- CAN_TOCC : (CAN Offset: 0x28) (R/W 32) Timeout Counter Configuration -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t ETOC:1; /*!< bit: 0 Enable Timeout Counter */ + uint32_t TOS:2; /*!< bit: 1.. 2 Timeout Select */ + uint32_t :13; /*!< bit: 3..15 Reserved */ + uint32_t TOP:16; /*!< bit: 16..31 Timeout Period */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_TOCC_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_TOCC_OFFSET 0x28 /**< \brief (CAN_TOCC offset) Timeout Counter Configuration */ +#define CAN_TOCC_RESETVALUE _U_(0xFFFF0000) /**< \brief (CAN_TOCC reset_value) Timeout Counter Configuration */ + +#define CAN_TOCC_ETOC_Pos 0 /**< \brief (CAN_TOCC) Enable Timeout Counter */ +#define CAN_TOCC_ETOC (_U_(0x1) << CAN_TOCC_ETOC_Pos) +#define CAN_TOCC_TOS_Pos 1 /**< \brief (CAN_TOCC) Timeout Select */ +#define CAN_TOCC_TOS_Msk (_U_(0x3) << CAN_TOCC_TOS_Pos) +#define CAN_TOCC_TOS(value) (CAN_TOCC_TOS_Msk & ((value) << CAN_TOCC_TOS_Pos)) +#define CAN_TOCC_TOS_CONT_Val _U_(0x0) /**< \brief (CAN_TOCC) Continuout operation */ +#define CAN_TOCC_TOS_TXEF_Val _U_(0x1) /**< \brief (CAN_TOCC) Timeout controlled by TX Event FIFO */ +#define CAN_TOCC_TOS_RXF0_Val _U_(0x2) /**< \brief (CAN_TOCC) Timeout controlled by Rx FIFO 0 */ +#define CAN_TOCC_TOS_RXF1_Val _U_(0x3) /**< \brief (CAN_TOCC) Timeout controlled by Rx FIFO 1 */ +#define CAN_TOCC_TOS_CONT (CAN_TOCC_TOS_CONT_Val << CAN_TOCC_TOS_Pos) +#define CAN_TOCC_TOS_TXEF (CAN_TOCC_TOS_TXEF_Val << CAN_TOCC_TOS_Pos) +#define CAN_TOCC_TOS_RXF0 (CAN_TOCC_TOS_RXF0_Val << CAN_TOCC_TOS_Pos) +#define CAN_TOCC_TOS_RXF1 (CAN_TOCC_TOS_RXF1_Val << CAN_TOCC_TOS_Pos) +#define CAN_TOCC_TOP_Pos 16 /**< \brief (CAN_TOCC) Timeout Period */ +#define CAN_TOCC_TOP_Msk (_U_(0xFFFF) << CAN_TOCC_TOP_Pos) +#define CAN_TOCC_TOP(value) (CAN_TOCC_TOP_Msk & ((value) << CAN_TOCC_TOP_Pos)) +#define CAN_TOCC_MASK _U_(0xFFFF0007) /**< \brief (CAN_TOCC) MASK Register */ + +/* -------- CAN_TOCV : (CAN Offset: 0x2C) (R/W 32) Timeout Counter Value -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t TOC:16; /*!< bit: 0..15 Timeout Counter */ + uint32_t :16; /*!< bit: 16..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_TOCV_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_TOCV_OFFSET 0x2C /**< \brief (CAN_TOCV offset) Timeout Counter Value */ +#define CAN_TOCV_RESETVALUE _U_(0x0000FFFF) /**< \brief (CAN_TOCV reset_value) Timeout Counter Value */ + +#define CAN_TOCV_TOC_Pos 0 /**< \brief (CAN_TOCV) Timeout Counter */ +#define CAN_TOCV_TOC_Msk (_U_(0xFFFF) << CAN_TOCV_TOC_Pos) +#define CAN_TOCV_TOC(value) (CAN_TOCV_TOC_Msk & ((value) << CAN_TOCV_TOC_Pos)) +#define CAN_TOCV_MASK _U_(0x0000FFFF) /**< \brief (CAN_TOCV) MASK Register */ + +/* -------- CAN_ECR : (CAN Offset: 0x40) (R/ 32) Error Counter -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t TEC:8; /*!< bit: 0.. 7 Transmit Error Counter */ + uint32_t REC:7; /*!< bit: 8..14 Receive Error Counter */ + uint32_t RP:1; /*!< bit: 15 Receive Error Passive */ + uint32_t CEL:8; /*!< bit: 16..23 CAN Error Logging */ + uint32_t :8; /*!< bit: 24..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_ECR_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_ECR_OFFSET 0x40 /**< \brief (CAN_ECR offset) Error Counter */ +#define CAN_ECR_RESETVALUE _U_(0x00000000) /**< \brief (CAN_ECR reset_value) Error Counter */ + +#define CAN_ECR_TEC_Pos 0 /**< \brief (CAN_ECR) Transmit Error Counter */ +#define CAN_ECR_TEC_Msk (_U_(0xFF) << CAN_ECR_TEC_Pos) +#define CAN_ECR_TEC(value) (CAN_ECR_TEC_Msk & ((value) << CAN_ECR_TEC_Pos)) +#define CAN_ECR_REC_Pos 8 /**< \brief (CAN_ECR) Receive Error Counter */ +#define CAN_ECR_REC_Msk (_U_(0x7F) << CAN_ECR_REC_Pos) +#define CAN_ECR_REC(value) (CAN_ECR_REC_Msk & ((value) << CAN_ECR_REC_Pos)) +#define CAN_ECR_RP_Pos 15 /**< \brief (CAN_ECR) Receive Error Passive */ +#define CAN_ECR_RP (_U_(0x1) << CAN_ECR_RP_Pos) +#define CAN_ECR_CEL_Pos 16 /**< \brief (CAN_ECR) CAN Error Logging */ +#define CAN_ECR_CEL_Msk (_U_(0xFF) << CAN_ECR_CEL_Pos) +#define CAN_ECR_CEL(value) (CAN_ECR_CEL_Msk & ((value) << CAN_ECR_CEL_Pos)) +#define CAN_ECR_MASK _U_(0x00FFFFFF) /**< \brief (CAN_ECR) MASK Register */ + +/* -------- CAN_PSR : (CAN Offset: 0x44) (R/ 32) Protocol Status -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t LEC:3; /*!< bit: 0.. 2 Last Error Code */ + uint32_t ACT:2; /*!< bit: 3.. 4 Activity */ + uint32_t EP:1; /*!< bit: 5 Error Passive */ + uint32_t EW:1; /*!< bit: 6 Warning Status */ + uint32_t BO:1; /*!< bit: 7 Bus_Off Status */ + uint32_t DLEC:3; /*!< bit: 8..10 Data Phase Last Error Code */ + uint32_t RESI:1; /*!< bit: 11 ESI flag of last received CAN FD Message */ + uint32_t RBRS:1; /*!< bit: 12 BRS flag of last received CAN FD Message */ + uint32_t RFDF:1; /*!< bit: 13 Received a CAN FD Message */ + uint32_t PXE:1; /*!< bit: 14 Protocol Exception Event */ + uint32_t :1; /*!< bit: 15 Reserved */ + uint32_t TDCV:7; /*!< bit: 16..22 Transmitter Delay Compensation Value */ + uint32_t :9; /*!< bit: 23..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_PSR_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_PSR_OFFSET 0x44 /**< \brief (CAN_PSR offset) Protocol Status */ +#define CAN_PSR_RESETVALUE _U_(0x00000707) /**< \brief (CAN_PSR reset_value) Protocol Status */ + +#define CAN_PSR_LEC_Pos 0 /**< \brief (CAN_PSR) Last Error Code */ +#define CAN_PSR_LEC_Msk (_U_(0x7) << CAN_PSR_LEC_Pos) +#define CAN_PSR_LEC(value) (CAN_PSR_LEC_Msk & ((value) << CAN_PSR_LEC_Pos)) +#define CAN_PSR_LEC_NONE_Val _U_(0x0) /**< \brief (CAN_PSR) No Error */ +#define CAN_PSR_LEC_STUFF_Val _U_(0x1) /**< \brief (CAN_PSR) Stuff Error */ +#define CAN_PSR_LEC_FORM_Val _U_(0x2) /**< \brief (CAN_PSR) Form Error */ +#define CAN_PSR_LEC_ACK_Val _U_(0x3) /**< \brief (CAN_PSR) Ack Error */ +#define CAN_PSR_LEC_BIT1_Val _U_(0x4) /**< \brief (CAN_PSR) Bit1 Error */ +#define CAN_PSR_LEC_BIT0_Val _U_(0x5) /**< \brief (CAN_PSR) Bit0 Error */ +#define CAN_PSR_LEC_CRC_Val _U_(0x6) /**< \brief (CAN_PSR) CRC Error */ +#define CAN_PSR_LEC_NC_Val _U_(0x7) /**< \brief (CAN_PSR) No Change */ +#define CAN_PSR_LEC_NONE (CAN_PSR_LEC_NONE_Val << CAN_PSR_LEC_Pos) +#define CAN_PSR_LEC_STUFF (CAN_PSR_LEC_STUFF_Val << CAN_PSR_LEC_Pos) +#define CAN_PSR_LEC_FORM (CAN_PSR_LEC_FORM_Val << CAN_PSR_LEC_Pos) +#define CAN_PSR_LEC_ACK (CAN_PSR_LEC_ACK_Val << CAN_PSR_LEC_Pos) +#define CAN_PSR_LEC_BIT1 (CAN_PSR_LEC_BIT1_Val << CAN_PSR_LEC_Pos) +#define CAN_PSR_LEC_BIT0 (CAN_PSR_LEC_BIT0_Val << CAN_PSR_LEC_Pos) +#define CAN_PSR_LEC_CRC (CAN_PSR_LEC_CRC_Val << CAN_PSR_LEC_Pos) +#define CAN_PSR_LEC_NC (CAN_PSR_LEC_NC_Val << CAN_PSR_LEC_Pos) +#define CAN_PSR_ACT_Pos 3 /**< \brief (CAN_PSR) Activity */ +#define CAN_PSR_ACT_Msk (_U_(0x3) << CAN_PSR_ACT_Pos) +#define CAN_PSR_ACT(value) (CAN_PSR_ACT_Msk & ((value) << CAN_PSR_ACT_Pos)) +#define CAN_PSR_ACT_SYNC_Val _U_(0x0) /**< \brief (CAN_PSR) Node is synchronizing on CAN communication */ +#define CAN_PSR_ACT_IDLE_Val _U_(0x1) /**< \brief (CAN_PSR) Node is neither receiver nor transmitter */ +#define CAN_PSR_ACT_RX_Val _U_(0x2) /**< \brief (CAN_PSR) Node is operating as receiver */ +#define CAN_PSR_ACT_TX_Val _U_(0x3) /**< \brief (CAN_PSR) Node is operating as transmitter */ +#define CAN_PSR_ACT_SYNC (CAN_PSR_ACT_SYNC_Val << CAN_PSR_ACT_Pos) +#define CAN_PSR_ACT_IDLE (CAN_PSR_ACT_IDLE_Val << CAN_PSR_ACT_Pos) +#define CAN_PSR_ACT_RX (CAN_PSR_ACT_RX_Val << CAN_PSR_ACT_Pos) +#define CAN_PSR_ACT_TX (CAN_PSR_ACT_TX_Val << CAN_PSR_ACT_Pos) +#define CAN_PSR_EP_Pos 5 /**< \brief (CAN_PSR) Error Passive */ +#define CAN_PSR_EP (_U_(0x1) << CAN_PSR_EP_Pos) +#define CAN_PSR_EW_Pos 6 /**< \brief (CAN_PSR) Warning Status */ +#define CAN_PSR_EW (_U_(0x1) << CAN_PSR_EW_Pos) +#define CAN_PSR_BO_Pos 7 /**< \brief (CAN_PSR) Bus_Off Status */ +#define CAN_PSR_BO (_U_(0x1) << CAN_PSR_BO_Pos) +#define CAN_PSR_DLEC_Pos 8 /**< \brief (CAN_PSR) Data Phase Last Error Code */ +#define CAN_PSR_DLEC_Msk (_U_(0x7) << CAN_PSR_DLEC_Pos) +#define CAN_PSR_DLEC(value) (CAN_PSR_DLEC_Msk & ((value) << CAN_PSR_DLEC_Pos)) +#define CAN_PSR_DLEC_NONE_Val _U_(0x0) /**< \brief (CAN_PSR) No Error */ +#define CAN_PSR_DLEC_STUFF_Val _U_(0x1) /**< \brief (CAN_PSR) Stuff Error */ +#define CAN_PSR_DLEC_FORM_Val _U_(0x2) /**< \brief (CAN_PSR) Form Error */ +#define CAN_PSR_DLEC_ACK_Val _U_(0x3) /**< \brief (CAN_PSR) Ack Error */ +#define CAN_PSR_DLEC_BIT1_Val _U_(0x4) /**< \brief (CAN_PSR) Bit1 Error */ +#define CAN_PSR_DLEC_BIT0_Val _U_(0x5) /**< \brief (CAN_PSR) Bit0 Error */ +#define CAN_PSR_DLEC_CRC_Val _U_(0x6) /**< \brief (CAN_PSR) CRC Error */ +#define CAN_PSR_DLEC_NC_Val _U_(0x7) /**< \brief (CAN_PSR) No Change */ +#define CAN_PSR_DLEC_NONE (CAN_PSR_DLEC_NONE_Val << CAN_PSR_DLEC_Pos) +#define CAN_PSR_DLEC_STUFF (CAN_PSR_DLEC_STUFF_Val << CAN_PSR_DLEC_Pos) +#define CAN_PSR_DLEC_FORM (CAN_PSR_DLEC_FORM_Val << CAN_PSR_DLEC_Pos) +#define CAN_PSR_DLEC_ACK (CAN_PSR_DLEC_ACK_Val << CAN_PSR_DLEC_Pos) +#define CAN_PSR_DLEC_BIT1 (CAN_PSR_DLEC_BIT1_Val << CAN_PSR_DLEC_Pos) +#define CAN_PSR_DLEC_BIT0 (CAN_PSR_DLEC_BIT0_Val << CAN_PSR_DLEC_Pos) +#define CAN_PSR_DLEC_CRC (CAN_PSR_DLEC_CRC_Val << CAN_PSR_DLEC_Pos) +#define CAN_PSR_DLEC_NC (CAN_PSR_DLEC_NC_Val << CAN_PSR_DLEC_Pos) +#define CAN_PSR_RESI_Pos 11 /**< \brief (CAN_PSR) ESI flag of last received CAN FD Message */ +#define CAN_PSR_RESI (_U_(0x1) << CAN_PSR_RESI_Pos) +#define CAN_PSR_RBRS_Pos 12 /**< \brief (CAN_PSR) BRS flag of last received CAN FD Message */ +#define CAN_PSR_RBRS (_U_(0x1) << CAN_PSR_RBRS_Pos) +#define CAN_PSR_RFDF_Pos 13 /**< \brief (CAN_PSR) Received a CAN FD Message */ +#define CAN_PSR_RFDF (_U_(0x1) << CAN_PSR_RFDF_Pos) +#define CAN_PSR_PXE_Pos 14 /**< \brief (CAN_PSR) Protocol Exception Event */ +#define CAN_PSR_PXE (_U_(0x1) << CAN_PSR_PXE_Pos) +#define CAN_PSR_TDCV_Pos 16 /**< \brief (CAN_PSR) Transmitter Delay Compensation Value */ +#define CAN_PSR_TDCV_Msk (_U_(0x7F) << CAN_PSR_TDCV_Pos) +#define CAN_PSR_TDCV(value) (CAN_PSR_TDCV_Msk & ((value) << CAN_PSR_TDCV_Pos)) +#define CAN_PSR_MASK _U_(0x007F7FFF) /**< \brief (CAN_PSR) MASK Register */ + +/* -------- CAN_TDCR : (CAN Offset: 0x48) (R/W 32) Extended ID Filter Configuration -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t TDCF:7; /*!< bit: 0.. 6 Transmitter Delay Compensation Filter Length */ + uint32_t :1; /*!< bit: 7 Reserved */ + uint32_t TDCO:7; /*!< bit: 8..14 Transmitter Delay Compensation Offset */ + uint32_t :17; /*!< bit: 15..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_TDCR_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_TDCR_OFFSET 0x48 /**< \brief (CAN_TDCR offset) Extended ID Filter Configuration */ +#define CAN_TDCR_RESETVALUE _U_(0x00000000) /**< \brief (CAN_TDCR reset_value) Extended ID Filter Configuration */ + +#define CAN_TDCR_TDCF_Pos 0 /**< \brief (CAN_TDCR) Transmitter Delay Compensation Filter Length */ +#define CAN_TDCR_TDCF_Msk (_U_(0x7F) << CAN_TDCR_TDCF_Pos) +#define CAN_TDCR_TDCF(value) (CAN_TDCR_TDCF_Msk & ((value) << CAN_TDCR_TDCF_Pos)) +#define CAN_TDCR_TDCO_Pos 8 /**< \brief (CAN_TDCR) Transmitter Delay Compensation Offset */ +#define CAN_TDCR_TDCO_Msk (_U_(0x7F) << CAN_TDCR_TDCO_Pos) +#define CAN_TDCR_TDCO(value) (CAN_TDCR_TDCO_Msk & ((value) << CAN_TDCR_TDCO_Pos)) +#define CAN_TDCR_MASK _U_(0x00007F7F) /**< \brief (CAN_TDCR) MASK Register */ + +/* -------- CAN_IR : (CAN Offset: 0x50) (R/W 32) Interrupt -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t RF0N:1; /*!< bit: 0 Rx FIFO 0 New Message */ + uint32_t RF0W:1; /*!< bit: 1 Rx FIFO 0 Watermark Reached */ + uint32_t RF0F:1; /*!< bit: 2 Rx FIFO 0 Full */ + uint32_t RF0L:1; /*!< bit: 3 Rx FIFO 0 Message Lost */ + uint32_t RF1N:1; /*!< bit: 4 Rx FIFO 1 New Message */ + uint32_t RF1W:1; /*!< bit: 5 Rx FIFO 1 Watermark Reached */ + uint32_t RF1F:1; /*!< bit: 6 Rx FIFO 1 FIFO Full */ + uint32_t RF1L:1; /*!< bit: 7 Rx FIFO 1 Message Lost */ + uint32_t HPM:1; /*!< bit: 8 High Priority Message */ + uint32_t TC:1; /*!< bit: 9 Timestamp Completed */ + uint32_t TCF:1; /*!< bit: 10 Transmission Cancellation Finished */ + uint32_t TFE:1; /*!< bit: 11 Tx FIFO Empty */ + uint32_t TEFN:1; /*!< bit: 12 Tx Event FIFO New Entry */ + uint32_t TEFW:1; /*!< bit: 13 Tx Event FIFO Watermark Reached */ + uint32_t TEFF:1; /*!< bit: 14 Tx Event FIFO Full */ + uint32_t TEFL:1; /*!< bit: 15 Tx Event FIFO Element Lost */ + uint32_t TSW:1; /*!< bit: 16 Timestamp Wraparound */ + uint32_t MRAF:1; /*!< bit: 17 Message RAM Access Failure */ + uint32_t TOO:1; /*!< bit: 18 Timeout Occurred */ + uint32_t DRX:1; /*!< bit: 19 Message stored to Dedicated Rx Buffer */ + uint32_t BEC:1; /*!< bit: 20 Bit Error Corrected */ + uint32_t BEU:1; /*!< bit: 21 Bit Error Uncorrected */ + uint32_t ELO:1; /*!< bit: 22 Error Logging Overflow */ + uint32_t EP:1; /*!< bit: 23 Error Passive */ + uint32_t EW:1; /*!< bit: 24 Warning Status */ + uint32_t BO:1; /*!< bit: 25 Bus_Off Status */ + uint32_t WDI:1; /*!< bit: 26 Watchdog Interrupt */ + uint32_t PEA:1; /*!< bit: 27 Protocol Error in Arbitration Phase */ + uint32_t PED:1; /*!< bit: 28 Protocol Error in Data Phase */ + uint32_t ARA:1; /*!< bit: 29 Access to Reserved Address */ + uint32_t :2; /*!< bit: 30..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_IR_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_IR_OFFSET 0x50 /**< \brief (CAN_IR offset) Interrupt */ +#define CAN_IR_RESETVALUE _U_(0x00000000) /**< \brief (CAN_IR reset_value) Interrupt */ + +#define CAN_IR_RF0N_Pos 0 /**< \brief (CAN_IR) Rx FIFO 0 New Message */ +#define CAN_IR_RF0N (_U_(0x1) << CAN_IR_RF0N_Pos) +#define CAN_IR_RF0W_Pos 1 /**< \brief (CAN_IR) Rx FIFO 0 Watermark Reached */ +#define CAN_IR_RF0W (_U_(0x1) << CAN_IR_RF0W_Pos) +#define CAN_IR_RF0F_Pos 2 /**< \brief (CAN_IR) Rx FIFO 0 Full */ +#define CAN_IR_RF0F (_U_(0x1) << CAN_IR_RF0F_Pos) +#define CAN_IR_RF0L_Pos 3 /**< \brief (CAN_IR) Rx FIFO 0 Message Lost */ +#define CAN_IR_RF0L (_U_(0x1) << CAN_IR_RF0L_Pos) +#define CAN_IR_RF1N_Pos 4 /**< \brief (CAN_IR) Rx FIFO 1 New Message */ +#define CAN_IR_RF1N (_U_(0x1) << CAN_IR_RF1N_Pos) +#define CAN_IR_RF1W_Pos 5 /**< \brief (CAN_IR) Rx FIFO 1 Watermark Reached */ +#define CAN_IR_RF1W (_U_(0x1) << CAN_IR_RF1W_Pos) +#define CAN_IR_RF1F_Pos 6 /**< \brief (CAN_IR) Rx FIFO 1 FIFO Full */ +#define CAN_IR_RF1F (_U_(0x1) << CAN_IR_RF1F_Pos) +#define CAN_IR_RF1L_Pos 7 /**< \brief (CAN_IR) Rx FIFO 1 Message Lost */ +#define CAN_IR_RF1L (_U_(0x1) << CAN_IR_RF1L_Pos) +#define CAN_IR_HPM_Pos 8 /**< \brief (CAN_IR) High Priority Message */ +#define CAN_IR_HPM (_U_(0x1) << CAN_IR_HPM_Pos) +#define CAN_IR_TC_Pos 9 /**< \brief (CAN_IR) Timestamp Completed */ +#define CAN_IR_TC (_U_(0x1) << CAN_IR_TC_Pos) +#define CAN_IR_TCF_Pos 10 /**< \brief (CAN_IR) Transmission Cancellation Finished */ +#define CAN_IR_TCF (_U_(0x1) << CAN_IR_TCF_Pos) +#define CAN_IR_TFE_Pos 11 /**< \brief (CAN_IR) Tx FIFO Empty */ +#define CAN_IR_TFE (_U_(0x1) << CAN_IR_TFE_Pos) +#define CAN_IR_TEFN_Pos 12 /**< \brief (CAN_IR) Tx Event FIFO New Entry */ +#define CAN_IR_TEFN (_U_(0x1) << CAN_IR_TEFN_Pos) +#define CAN_IR_TEFW_Pos 13 /**< \brief (CAN_IR) Tx Event FIFO Watermark Reached */ +#define CAN_IR_TEFW (_U_(0x1) << CAN_IR_TEFW_Pos) +#define CAN_IR_TEFF_Pos 14 /**< \brief (CAN_IR) Tx Event FIFO Full */ +#define CAN_IR_TEFF (_U_(0x1) << CAN_IR_TEFF_Pos) +#define CAN_IR_TEFL_Pos 15 /**< \brief (CAN_IR) Tx Event FIFO Element Lost */ +#define CAN_IR_TEFL (_U_(0x1) << CAN_IR_TEFL_Pos) +#define CAN_IR_TSW_Pos 16 /**< \brief (CAN_IR) Timestamp Wraparound */ +#define CAN_IR_TSW (_U_(0x1) << CAN_IR_TSW_Pos) +#define CAN_IR_MRAF_Pos 17 /**< \brief (CAN_IR) Message RAM Access Failure */ +#define CAN_IR_MRAF (_U_(0x1) << CAN_IR_MRAF_Pos) +#define CAN_IR_TOO_Pos 18 /**< \brief (CAN_IR) Timeout Occurred */ +#define CAN_IR_TOO (_U_(0x1) << CAN_IR_TOO_Pos) +#define CAN_IR_DRX_Pos 19 /**< \brief (CAN_IR) Message stored to Dedicated Rx Buffer */ +#define CAN_IR_DRX (_U_(0x1) << CAN_IR_DRX_Pos) +#define CAN_IR_BEC_Pos 20 /**< \brief (CAN_IR) Bit Error Corrected */ +#define CAN_IR_BEC (_U_(0x1) << CAN_IR_BEC_Pos) +#define CAN_IR_BEU_Pos 21 /**< \brief (CAN_IR) Bit Error Uncorrected */ +#define CAN_IR_BEU (_U_(0x1) << CAN_IR_BEU_Pos) +#define CAN_IR_ELO_Pos 22 /**< \brief (CAN_IR) Error Logging Overflow */ +#define CAN_IR_ELO (_U_(0x1) << CAN_IR_ELO_Pos) +#define CAN_IR_EP_Pos 23 /**< \brief (CAN_IR) Error Passive */ +#define CAN_IR_EP (_U_(0x1) << CAN_IR_EP_Pos) +#define CAN_IR_EW_Pos 24 /**< \brief (CAN_IR) Warning Status */ +#define CAN_IR_EW (_U_(0x1) << CAN_IR_EW_Pos) +#define CAN_IR_BO_Pos 25 /**< \brief (CAN_IR) Bus_Off Status */ +#define CAN_IR_BO (_U_(0x1) << CAN_IR_BO_Pos) +#define CAN_IR_WDI_Pos 26 /**< \brief (CAN_IR) Watchdog Interrupt */ +#define CAN_IR_WDI (_U_(0x1) << CAN_IR_WDI_Pos) +#define CAN_IR_PEA_Pos 27 /**< \brief (CAN_IR) Protocol Error in Arbitration Phase */ +#define CAN_IR_PEA (_U_(0x1) << CAN_IR_PEA_Pos) +#define CAN_IR_PED_Pos 28 /**< \brief (CAN_IR) Protocol Error in Data Phase */ +#define CAN_IR_PED (_U_(0x1) << CAN_IR_PED_Pos) +#define CAN_IR_ARA_Pos 29 /**< \brief (CAN_IR) Access to Reserved Address */ +#define CAN_IR_ARA (_U_(0x1) << CAN_IR_ARA_Pos) +#define CAN_IR_MASK _U_(0x3FFFFFFF) /**< \brief (CAN_IR) MASK Register */ + +/* -------- CAN_IE : (CAN Offset: 0x54) (R/W 32) Interrupt Enable -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t RF0NE:1; /*!< bit: 0 Rx FIFO 0 New Message Interrupt Enable */ + uint32_t RF0WE:1; /*!< bit: 1 Rx FIFO 0 Watermark Reached Interrupt Enable */ + uint32_t RF0FE:1; /*!< bit: 2 Rx FIFO 0 Full Interrupt Enable */ + uint32_t RF0LE:1; /*!< bit: 3 Rx FIFO 0 Message Lost Interrupt Enable */ + uint32_t RF1NE:1; /*!< bit: 4 Rx FIFO 1 New Message Interrupt Enable */ + uint32_t RF1WE:1; /*!< bit: 5 Rx FIFO 1 Watermark Reached Interrupt Enable */ + uint32_t RF1FE:1; /*!< bit: 6 Rx FIFO 1 FIFO Full Interrupt Enable */ + uint32_t RF1LE:1; /*!< bit: 7 Rx FIFO 1 Message Lost Interrupt Enable */ + uint32_t HPME:1; /*!< bit: 8 High Priority Message Interrupt Enable */ + uint32_t TCE:1; /*!< bit: 9 Timestamp Completed Interrupt Enable */ + uint32_t TCFE:1; /*!< bit: 10 Transmission Cancellation Finished Interrupt Enable */ + uint32_t TFEE:1; /*!< bit: 11 Tx FIFO Empty Interrupt Enable */ + uint32_t TEFNE:1; /*!< bit: 12 Tx Event FIFO New Entry Interrupt Enable */ + uint32_t TEFWE:1; /*!< bit: 13 Tx Event FIFO Watermark Reached Interrupt Enable */ + uint32_t TEFFE:1; /*!< bit: 14 Tx Event FIFO Full Interrupt Enable */ + uint32_t TEFLE:1; /*!< bit: 15 Tx Event FIFO Element Lost Interrupt Enable */ + uint32_t TSWE:1; /*!< bit: 16 Timestamp Wraparound Interrupt Enable */ + uint32_t MRAFE:1; /*!< bit: 17 Message RAM Access Failure Interrupt Enable */ + uint32_t TOOE:1; /*!< bit: 18 Timeout Occurred Interrupt Enable */ + uint32_t DRXE:1; /*!< bit: 19 Message stored to Dedicated Rx Buffer Interrupt Enable */ + uint32_t BECE:1; /*!< bit: 20 Bit Error Corrected Interrupt Enable */ + uint32_t BEUE:1; /*!< bit: 21 Bit Error Uncorrected Interrupt Enable */ + uint32_t ELOE:1; /*!< bit: 22 Error Logging Overflow Interrupt Enable */ + uint32_t EPE:1; /*!< bit: 23 Error Passive Interrupt Enable */ + uint32_t EWE:1; /*!< bit: 24 Warning Status Interrupt Enable */ + uint32_t BOE:1; /*!< bit: 25 Bus_Off Status Interrupt Enable */ + uint32_t WDIE:1; /*!< bit: 26 Watchdog Interrupt Interrupt Enable */ + uint32_t PEAE:1; /*!< bit: 27 Protocol Error in Arbitration Phase Enable */ + uint32_t PEDE:1; /*!< bit: 28 Protocol Error in Data Phase Enable */ + uint32_t ARAE:1; /*!< bit: 29 Access to Reserved Address Enable */ + uint32_t :2; /*!< bit: 30..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_IE_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_IE_OFFSET 0x54 /**< \brief (CAN_IE offset) Interrupt Enable */ +#define CAN_IE_RESETVALUE _U_(0x00000000) /**< \brief (CAN_IE reset_value) Interrupt Enable */ + +#define CAN_IE_RF0NE_Pos 0 /**< \brief (CAN_IE) Rx FIFO 0 New Message Interrupt Enable */ +#define CAN_IE_RF0NE (_U_(0x1) << CAN_IE_RF0NE_Pos) +#define CAN_IE_RF0WE_Pos 1 /**< \brief (CAN_IE) Rx FIFO 0 Watermark Reached Interrupt Enable */ +#define CAN_IE_RF0WE (_U_(0x1) << CAN_IE_RF0WE_Pos) +#define CAN_IE_RF0FE_Pos 2 /**< \brief (CAN_IE) Rx FIFO 0 Full Interrupt Enable */ +#define CAN_IE_RF0FE (_U_(0x1) << CAN_IE_RF0FE_Pos) +#define CAN_IE_RF0LE_Pos 3 /**< \brief (CAN_IE) Rx FIFO 0 Message Lost Interrupt Enable */ +#define CAN_IE_RF0LE (_U_(0x1) << CAN_IE_RF0LE_Pos) +#define CAN_IE_RF1NE_Pos 4 /**< \brief (CAN_IE) Rx FIFO 1 New Message Interrupt Enable */ +#define CAN_IE_RF1NE (_U_(0x1) << CAN_IE_RF1NE_Pos) +#define CAN_IE_RF1WE_Pos 5 /**< \brief (CAN_IE) Rx FIFO 1 Watermark Reached Interrupt Enable */ +#define CAN_IE_RF1WE (_U_(0x1) << CAN_IE_RF1WE_Pos) +#define CAN_IE_RF1FE_Pos 6 /**< \brief (CAN_IE) Rx FIFO 1 FIFO Full Interrupt Enable */ +#define CAN_IE_RF1FE (_U_(0x1) << CAN_IE_RF1FE_Pos) +#define CAN_IE_RF1LE_Pos 7 /**< \brief (CAN_IE) Rx FIFO 1 Message Lost Interrupt Enable */ +#define CAN_IE_RF1LE (_U_(0x1) << CAN_IE_RF1LE_Pos) +#define CAN_IE_HPME_Pos 8 /**< \brief (CAN_IE) High Priority Message Interrupt Enable */ +#define CAN_IE_HPME (_U_(0x1) << CAN_IE_HPME_Pos) +#define CAN_IE_TCE_Pos 9 /**< \brief (CAN_IE) Timestamp Completed Interrupt Enable */ +#define CAN_IE_TCE (_U_(0x1) << CAN_IE_TCE_Pos) +#define CAN_IE_TCFE_Pos 10 /**< \brief (CAN_IE) Transmission Cancellation Finished Interrupt Enable */ +#define CAN_IE_TCFE (_U_(0x1) << CAN_IE_TCFE_Pos) +#define CAN_IE_TFEE_Pos 11 /**< \brief (CAN_IE) Tx FIFO Empty Interrupt Enable */ +#define CAN_IE_TFEE (_U_(0x1) << CAN_IE_TFEE_Pos) +#define CAN_IE_TEFNE_Pos 12 /**< \brief (CAN_IE) Tx Event FIFO New Entry Interrupt Enable */ +#define CAN_IE_TEFNE (_U_(0x1) << CAN_IE_TEFNE_Pos) +#define CAN_IE_TEFWE_Pos 13 /**< \brief (CAN_IE) Tx Event FIFO Watermark Reached Interrupt Enable */ +#define CAN_IE_TEFWE (_U_(0x1) << CAN_IE_TEFWE_Pos) +#define CAN_IE_TEFFE_Pos 14 /**< \brief (CAN_IE) Tx Event FIFO Full Interrupt Enable */ +#define CAN_IE_TEFFE (_U_(0x1) << CAN_IE_TEFFE_Pos) +#define CAN_IE_TEFLE_Pos 15 /**< \brief (CAN_IE) Tx Event FIFO Element Lost Interrupt Enable */ +#define CAN_IE_TEFLE (_U_(0x1) << CAN_IE_TEFLE_Pos) +#define CAN_IE_TSWE_Pos 16 /**< \brief (CAN_IE) Timestamp Wraparound Interrupt Enable */ +#define CAN_IE_TSWE (_U_(0x1) << CAN_IE_TSWE_Pos) +#define CAN_IE_MRAFE_Pos 17 /**< \brief (CAN_IE) Message RAM Access Failure Interrupt Enable */ +#define CAN_IE_MRAFE (_U_(0x1) << CAN_IE_MRAFE_Pos) +#define CAN_IE_TOOE_Pos 18 /**< \brief (CAN_IE) Timeout Occurred Interrupt Enable */ +#define CAN_IE_TOOE (_U_(0x1) << CAN_IE_TOOE_Pos) +#define CAN_IE_DRXE_Pos 19 /**< \brief (CAN_IE) Message stored to Dedicated Rx Buffer Interrupt Enable */ +#define CAN_IE_DRXE (_U_(0x1) << CAN_IE_DRXE_Pos) +#define CAN_IE_BECE_Pos 20 /**< \brief (CAN_IE) Bit Error Corrected Interrupt Enable */ +#define CAN_IE_BECE (_U_(0x1) << CAN_IE_BECE_Pos) +#define CAN_IE_BEUE_Pos 21 /**< \brief (CAN_IE) Bit Error Uncorrected Interrupt Enable */ +#define CAN_IE_BEUE (_U_(0x1) << CAN_IE_BEUE_Pos) +#define CAN_IE_ELOE_Pos 22 /**< \brief (CAN_IE) Error Logging Overflow Interrupt Enable */ +#define CAN_IE_ELOE (_U_(0x1) << CAN_IE_ELOE_Pos) +#define CAN_IE_EPE_Pos 23 /**< \brief (CAN_IE) Error Passive Interrupt Enable */ +#define CAN_IE_EPE (_U_(0x1) << CAN_IE_EPE_Pos) +#define CAN_IE_EWE_Pos 24 /**< \brief (CAN_IE) Warning Status Interrupt Enable */ +#define CAN_IE_EWE (_U_(0x1) << CAN_IE_EWE_Pos) +#define CAN_IE_BOE_Pos 25 /**< \brief (CAN_IE) Bus_Off Status Interrupt Enable */ +#define CAN_IE_BOE (_U_(0x1) << CAN_IE_BOE_Pos) +#define CAN_IE_WDIE_Pos 26 /**< \brief (CAN_IE) Watchdog Interrupt Interrupt Enable */ +#define CAN_IE_WDIE (_U_(0x1) << CAN_IE_WDIE_Pos) +#define CAN_IE_PEAE_Pos 27 /**< \brief (CAN_IE) Protocol Error in Arbitration Phase Enable */ +#define CAN_IE_PEAE (_U_(0x1) << CAN_IE_PEAE_Pos) +#define CAN_IE_PEDE_Pos 28 /**< \brief (CAN_IE) Protocol Error in Data Phase Enable */ +#define CAN_IE_PEDE (_U_(0x1) << CAN_IE_PEDE_Pos) +#define CAN_IE_ARAE_Pos 29 /**< \brief (CAN_IE) Access to Reserved Address Enable */ +#define CAN_IE_ARAE (_U_(0x1) << CAN_IE_ARAE_Pos) +#define CAN_IE_MASK _U_(0x3FFFFFFF) /**< \brief (CAN_IE) MASK Register */ + +/* -------- CAN_ILS : (CAN Offset: 0x58) (R/W 32) Interrupt Line Select -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t RF0NL:1; /*!< bit: 0 Rx FIFO 0 New Message Interrupt Line */ + uint32_t RF0WL:1; /*!< bit: 1 Rx FIFO 0 Watermark Reached Interrupt Line */ + uint32_t RF0FL:1; /*!< bit: 2 Rx FIFO 0 Full Interrupt Line */ + uint32_t RF0LL:1; /*!< bit: 3 Rx FIFO 0 Message Lost Interrupt Line */ + uint32_t RF1NL:1; /*!< bit: 4 Rx FIFO 1 New Message Interrupt Line */ + uint32_t RF1WL:1; /*!< bit: 5 Rx FIFO 1 Watermark Reached Interrupt Line */ + uint32_t RF1FL:1; /*!< bit: 6 Rx FIFO 1 FIFO Full Interrupt Line */ + uint32_t RF1LL:1; /*!< bit: 7 Rx FIFO 1 Message Lost Interrupt Line */ + uint32_t HPML:1; /*!< bit: 8 High Priority Message Interrupt Line */ + uint32_t TCL:1; /*!< bit: 9 Timestamp Completed Interrupt Line */ + uint32_t TCFL:1; /*!< bit: 10 Transmission Cancellation Finished Interrupt Line */ + uint32_t TFEL:1; /*!< bit: 11 Tx FIFO Empty Interrupt Line */ + uint32_t TEFNL:1; /*!< bit: 12 Tx Event FIFO New Entry Interrupt Line */ + uint32_t TEFWL:1; /*!< bit: 13 Tx Event FIFO Watermark Reached Interrupt Line */ + uint32_t TEFFL:1; /*!< bit: 14 Tx Event FIFO Full Interrupt Line */ + uint32_t TEFLL:1; /*!< bit: 15 Tx Event FIFO Element Lost Interrupt Line */ + uint32_t TSWL:1; /*!< bit: 16 Timestamp Wraparound Interrupt Line */ + uint32_t MRAFL:1; /*!< bit: 17 Message RAM Access Failure Interrupt Line */ + uint32_t TOOL:1; /*!< bit: 18 Timeout Occurred Interrupt Line */ + uint32_t DRXL:1; /*!< bit: 19 Message stored to Dedicated Rx Buffer Interrupt Line */ + uint32_t BECL:1; /*!< bit: 20 Bit Error Corrected Interrupt Line */ + uint32_t BEUL:1; /*!< bit: 21 Bit Error Uncorrected Interrupt Line */ + uint32_t ELOL:1; /*!< bit: 22 Error Logging Overflow Interrupt Line */ + uint32_t EPL:1; /*!< bit: 23 Error Passive Interrupt Line */ + uint32_t EWL:1; /*!< bit: 24 Warning Status Interrupt Line */ + uint32_t BOL:1; /*!< bit: 25 Bus_Off Status Interrupt Line */ + uint32_t WDIL:1; /*!< bit: 26 Watchdog Interrupt Interrupt Line */ + uint32_t PEAL:1; /*!< bit: 27 Protocol Error in Arbitration Phase Line */ + uint32_t PEDL:1; /*!< bit: 28 Protocol Error in Data Phase Line */ + uint32_t ARAL:1; /*!< bit: 29 Access to Reserved Address Line */ + uint32_t :2; /*!< bit: 30..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_ILS_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_ILS_OFFSET 0x58 /**< \brief (CAN_ILS offset) Interrupt Line Select */ +#define CAN_ILS_RESETVALUE _U_(0x00000000) /**< \brief (CAN_ILS reset_value) Interrupt Line Select */ + +#define CAN_ILS_RF0NL_Pos 0 /**< \brief (CAN_ILS) Rx FIFO 0 New Message Interrupt Line */ +#define CAN_ILS_RF0NL (_U_(0x1) << CAN_ILS_RF0NL_Pos) +#define CAN_ILS_RF0WL_Pos 1 /**< \brief (CAN_ILS) Rx FIFO 0 Watermark Reached Interrupt Line */ +#define CAN_ILS_RF0WL (_U_(0x1) << CAN_ILS_RF0WL_Pos) +#define CAN_ILS_RF0FL_Pos 2 /**< \brief (CAN_ILS) Rx FIFO 0 Full Interrupt Line */ +#define CAN_ILS_RF0FL (_U_(0x1) << CAN_ILS_RF0FL_Pos) +#define CAN_ILS_RF0LL_Pos 3 /**< \brief (CAN_ILS) Rx FIFO 0 Message Lost Interrupt Line */ +#define CAN_ILS_RF0LL (_U_(0x1) << CAN_ILS_RF0LL_Pos) +#define CAN_ILS_RF1NL_Pos 4 /**< \brief (CAN_ILS) Rx FIFO 1 New Message Interrupt Line */ +#define CAN_ILS_RF1NL (_U_(0x1) << CAN_ILS_RF1NL_Pos) +#define CAN_ILS_RF1WL_Pos 5 /**< \brief (CAN_ILS) Rx FIFO 1 Watermark Reached Interrupt Line */ +#define CAN_ILS_RF1WL (_U_(0x1) << CAN_ILS_RF1WL_Pos) +#define CAN_ILS_RF1FL_Pos 6 /**< \brief (CAN_ILS) Rx FIFO 1 FIFO Full Interrupt Line */ +#define CAN_ILS_RF1FL (_U_(0x1) << CAN_ILS_RF1FL_Pos) +#define CAN_ILS_RF1LL_Pos 7 /**< \brief (CAN_ILS) Rx FIFO 1 Message Lost Interrupt Line */ +#define CAN_ILS_RF1LL (_U_(0x1) << CAN_ILS_RF1LL_Pos) +#define CAN_ILS_HPML_Pos 8 /**< \brief (CAN_ILS) High Priority Message Interrupt Line */ +#define CAN_ILS_HPML (_U_(0x1) << CAN_ILS_HPML_Pos) +#define CAN_ILS_TCL_Pos 9 /**< \brief (CAN_ILS) Timestamp Completed Interrupt Line */ +#define CAN_ILS_TCL (_U_(0x1) << CAN_ILS_TCL_Pos) +#define CAN_ILS_TCFL_Pos 10 /**< \brief (CAN_ILS) Transmission Cancellation Finished Interrupt Line */ +#define CAN_ILS_TCFL (_U_(0x1) << CAN_ILS_TCFL_Pos) +#define CAN_ILS_TFEL_Pos 11 /**< \brief (CAN_ILS) Tx FIFO Empty Interrupt Line */ +#define CAN_ILS_TFEL (_U_(0x1) << CAN_ILS_TFEL_Pos) +#define CAN_ILS_TEFNL_Pos 12 /**< \brief (CAN_ILS) Tx Event FIFO New Entry Interrupt Line */ +#define CAN_ILS_TEFNL (_U_(0x1) << CAN_ILS_TEFNL_Pos) +#define CAN_ILS_TEFWL_Pos 13 /**< \brief (CAN_ILS) Tx Event FIFO Watermark Reached Interrupt Line */ +#define CAN_ILS_TEFWL (_U_(0x1) << CAN_ILS_TEFWL_Pos) +#define CAN_ILS_TEFFL_Pos 14 /**< \brief (CAN_ILS) Tx Event FIFO Full Interrupt Line */ +#define CAN_ILS_TEFFL (_U_(0x1) << CAN_ILS_TEFFL_Pos) +#define CAN_ILS_TEFLL_Pos 15 /**< \brief (CAN_ILS) Tx Event FIFO Element Lost Interrupt Line */ +#define CAN_ILS_TEFLL (_U_(0x1) << CAN_ILS_TEFLL_Pos) +#define CAN_ILS_TSWL_Pos 16 /**< \brief (CAN_ILS) Timestamp Wraparound Interrupt Line */ +#define CAN_ILS_TSWL (_U_(0x1) << CAN_ILS_TSWL_Pos) +#define CAN_ILS_MRAFL_Pos 17 /**< \brief (CAN_ILS) Message RAM Access Failure Interrupt Line */ +#define CAN_ILS_MRAFL (_U_(0x1) << CAN_ILS_MRAFL_Pos) +#define CAN_ILS_TOOL_Pos 18 /**< \brief (CAN_ILS) Timeout Occurred Interrupt Line */ +#define CAN_ILS_TOOL (_U_(0x1) << CAN_ILS_TOOL_Pos) +#define CAN_ILS_DRXL_Pos 19 /**< \brief (CAN_ILS) Message stored to Dedicated Rx Buffer Interrupt Line */ +#define CAN_ILS_DRXL (_U_(0x1) << CAN_ILS_DRXL_Pos) +#define CAN_ILS_BECL_Pos 20 /**< \brief (CAN_ILS) Bit Error Corrected Interrupt Line */ +#define CAN_ILS_BECL (_U_(0x1) << CAN_ILS_BECL_Pos) +#define CAN_ILS_BEUL_Pos 21 /**< \brief (CAN_ILS) Bit Error Uncorrected Interrupt Line */ +#define CAN_ILS_BEUL (_U_(0x1) << CAN_ILS_BEUL_Pos) +#define CAN_ILS_ELOL_Pos 22 /**< \brief (CAN_ILS) Error Logging Overflow Interrupt Line */ +#define CAN_ILS_ELOL (_U_(0x1) << CAN_ILS_ELOL_Pos) +#define CAN_ILS_EPL_Pos 23 /**< \brief (CAN_ILS) Error Passive Interrupt Line */ +#define CAN_ILS_EPL (_U_(0x1) << CAN_ILS_EPL_Pos) +#define CAN_ILS_EWL_Pos 24 /**< \brief (CAN_ILS) Warning Status Interrupt Line */ +#define CAN_ILS_EWL (_U_(0x1) << CAN_ILS_EWL_Pos) +#define CAN_ILS_BOL_Pos 25 /**< \brief (CAN_ILS) Bus_Off Status Interrupt Line */ +#define CAN_ILS_BOL (_U_(0x1) << CAN_ILS_BOL_Pos) +#define CAN_ILS_WDIL_Pos 26 /**< \brief (CAN_ILS) Watchdog Interrupt Interrupt Line */ +#define CAN_ILS_WDIL (_U_(0x1) << CAN_ILS_WDIL_Pos) +#define CAN_ILS_PEAL_Pos 27 /**< \brief (CAN_ILS) Protocol Error in Arbitration Phase Line */ +#define CAN_ILS_PEAL (_U_(0x1) << CAN_ILS_PEAL_Pos) +#define CAN_ILS_PEDL_Pos 28 /**< \brief (CAN_ILS) Protocol Error in Data Phase Line */ +#define CAN_ILS_PEDL (_U_(0x1) << CAN_ILS_PEDL_Pos) +#define CAN_ILS_ARAL_Pos 29 /**< \brief (CAN_ILS) Access to Reserved Address Line */ +#define CAN_ILS_ARAL (_U_(0x1) << CAN_ILS_ARAL_Pos) +#define CAN_ILS_MASK _U_(0x3FFFFFFF) /**< \brief (CAN_ILS) MASK Register */ + +/* -------- CAN_ILE : (CAN Offset: 0x5C) (R/W 32) Interrupt Line Enable -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t EINT0:1; /*!< bit: 0 Enable Interrupt Line 0 */ + uint32_t EINT1:1; /*!< bit: 1 Enable Interrupt Line 1 */ + uint32_t :30; /*!< bit: 2..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_ILE_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_ILE_OFFSET 0x5C /**< \brief (CAN_ILE offset) Interrupt Line Enable */ +#define CAN_ILE_RESETVALUE _U_(0x00000000) /**< \brief (CAN_ILE reset_value) Interrupt Line Enable */ + +#define CAN_ILE_EINT0_Pos 0 /**< \brief (CAN_ILE) Enable Interrupt Line 0 */ +#define CAN_ILE_EINT0 (_U_(0x1) << CAN_ILE_EINT0_Pos) +#define CAN_ILE_EINT1_Pos 1 /**< \brief (CAN_ILE) Enable Interrupt Line 1 */ +#define CAN_ILE_EINT1 (_U_(0x1) << CAN_ILE_EINT1_Pos) +#define CAN_ILE_MASK _U_(0x00000003) /**< \brief (CAN_ILE) MASK Register */ + +/* -------- CAN_GFC : (CAN Offset: 0x80) (R/W 32) Global Filter Configuration -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t RRFE:1; /*!< bit: 0 Reject Remote Frames Extended */ + uint32_t RRFS:1; /*!< bit: 1 Reject Remote Frames Standard */ + uint32_t ANFE:2; /*!< bit: 2.. 3 Accept Non-matching Frames Extended */ + uint32_t ANFS:2; /*!< bit: 4.. 5 Accept Non-matching Frames Standard */ + uint32_t :26; /*!< bit: 6..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_GFC_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_GFC_OFFSET 0x80 /**< \brief (CAN_GFC offset) Global Filter Configuration */ +#define CAN_GFC_RESETVALUE _U_(0x00000000) /**< \brief (CAN_GFC reset_value) Global Filter Configuration */ + +#define CAN_GFC_RRFE_Pos 0 /**< \brief (CAN_GFC) Reject Remote Frames Extended */ +#define CAN_GFC_RRFE (_U_(0x1) << CAN_GFC_RRFE_Pos) +#define CAN_GFC_RRFS_Pos 1 /**< \brief (CAN_GFC) Reject Remote Frames Standard */ +#define CAN_GFC_RRFS (_U_(0x1) << CAN_GFC_RRFS_Pos) +#define CAN_GFC_ANFE_Pos 2 /**< \brief (CAN_GFC) Accept Non-matching Frames Extended */ +#define CAN_GFC_ANFE_Msk (_U_(0x3) << CAN_GFC_ANFE_Pos) +#define CAN_GFC_ANFE(value) (CAN_GFC_ANFE_Msk & ((value) << CAN_GFC_ANFE_Pos)) +#define CAN_GFC_ANFE_RXF0_Val _U_(0x0) /**< \brief (CAN_GFC) Accept in Rx FIFO 0 */ +#define CAN_GFC_ANFE_RXF1_Val _U_(0x1) /**< \brief (CAN_GFC) Accept in Rx FIFO 1 */ +#define CAN_GFC_ANFE_REJECT_Val _U_(0x2) /**< \brief (CAN_GFC) Reject */ +#define CAN_GFC_ANFE_RXF0 (CAN_GFC_ANFE_RXF0_Val << CAN_GFC_ANFE_Pos) +#define CAN_GFC_ANFE_RXF1 (CAN_GFC_ANFE_RXF1_Val << CAN_GFC_ANFE_Pos) +#define CAN_GFC_ANFE_REJECT (CAN_GFC_ANFE_REJECT_Val << CAN_GFC_ANFE_Pos) +#define CAN_GFC_ANFS_Pos 4 /**< \brief (CAN_GFC) Accept Non-matching Frames Standard */ +#define CAN_GFC_ANFS_Msk (_U_(0x3) << CAN_GFC_ANFS_Pos) +#define CAN_GFC_ANFS(value) (CAN_GFC_ANFS_Msk & ((value) << CAN_GFC_ANFS_Pos)) +#define CAN_GFC_ANFS_RXF0_Val _U_(0x0) /**< \brief (CAN_GFC) Accept in Rx FIFO 0 */ +#define CAN_GFC_ANFS_RXF1_Val _U_(0x1) /**< \brief (CAN_GFC) Accept in Rx FIFO 1 */ +#define CAN_GFC_ANFS_REJECT_Val _U_(0x2) /**< \brief (CAN_GFC) Reject */ +#define CAN_GFC_ANFS_RXF0 (CAN_GFC_ANFS_RXF0_Val << CAN_GFC_ANFS_Pos) +#define CAN_GFC_ANFS_RXF1 (CAN_GFC_ANFS_RXF1_Val << CAN_GFC_ANFS_Pos) +#define CAN_GFC_ANFS_REJECT (CAN_GFC_ANFS_REJECT_Val << CAN_GFC_ANFS_Pos) +#define CAN_GFC_MASK _U_(0x0000003F) /**< \brief (CAN_GFC) MASK Register */ + +/* -------- CAN_SIDFC : (CAN Offset: 0x84) (R/W 32) Standard ID Filter Configuration -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t FLSSA:16; /*!< bit: 0..15 Filter List Standard Start Address */ + uint32_t LSS:8; /*!< bit: 16..23 List Size Standard */ + uint32_t :8; /*!< bit: 24..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_SIDFC_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_SIDFC_OFFSET 0x84 /**< \brief (CAN_SIDFC offset) Standard ID Filter Configuration */ +#define CAN_SIDFC_RESETVALUE _U_(0x00000000) /**< \brief (CAN_SIDFC reset_value) Standard ID Filter Configuration */ + +#define CAN_SIDFC_FLSSA_Pos 0 /**< \brief (CAN_SIDFC) Filter List Standard Start Address */ +#define CAN_SIDFC_FLSSA_Msk (_U_(0xFFFF) << CAN_SIDFC_FLSSA_Pos) +#define CAN_SIDFC_FLSSA(value) (CAN_SIDFC_FLSSA_Msk & ((value) << CAN_SIDFC_FLSSA_Pos)) +#define CAN_SIDFC_LSS_Pos 16 /**< \brief (CAN_SIDFC) List Size Standard */ +#define CAN_SIDFC_LSS_Msk (_U_(0xFF) << CAN_SIDFC_LSS_Pos) +#define CAN_SIDFC_LSS(value) (CAN_SIDFC_LSS_Msk & ((value) << CAN_SIDFC_LSS_Pos)) +#define CAN_SIDFC_MASK _U_(0x00FFFFFF) /**< \brief (CAN_SIDFC) MASK Register */ + +/* -------- CAN_XIDFC : (CAN Offset: 0x88) (R/W 32) Extended ID Filter Configuration -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t FLESA:16; /*!< bit: 0..15 Filter List Extended Start Address */ + uint32_t LSE:7; /*!< bit: 16..22 List Size Extended */ + uint32_t :9; /*!< bit: 23..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_XIDFC_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_XIDFC_OFFSET 0x88 /**< \brief (CAN_XIDFC offset) Extended ID Filter Configuration */ +#define CAN_XIDFC_RESETVALUE _U_(0x00000000) /**< \brief (CAN_XIDFC reset_value) Extended ID Filter Configuration */ + +#define CAN_XIDFC_FLESA_Pos 0 /**< \brief (CAN_XIDFC) Filter List Extended Start Address */ +#define CAN_XIDFC_FLESA_Msk (_U_(0xFFFF) << CAN_XIDFC_FLESA_Pos) +#define CAN_XIDFC_FLESA(value) (CAN_XIDFC_FLESA_Msk & ((value) << CAN_XIDFC_FLESA_Pos)) +#define CAN_XIDFC_LSE_Pos 16 /**< \brief (CAN_XIDFC) List Size Extended */ +#define CAN_XIDFC_LSE_Msk (_U_(0x7F) << CAN_XIDFC_LSE_Pos) +#define CAN_XIDFC_LSE(value) (CAN_XIDFC_LSE_Msk & ((value) << CAN_XIDFC_LSE_Pos)) +#define CAN_XIDFC_MASK _U_(0x007FFFFF) /**< \brief (CAN_XIDFC) MASK Register */ + +/* -------- CAN_XIDAM : (CAN Offset: 0x90) (R/W 32) Extended ID AND Mask -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t EIDM:29; /*!< bit: 0..28 Extended ID Mask */ + uint32_t :3; /*!< bit: 29..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_XIDAM_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_XIDAM_OFFSET 0x90 /**< \brief (CAN_XIDAM offset) Extended ID AND Mask */ +#define CAN_XIDAM_RESETVALUE _U_(0x1FFFFFFF) /**< \brief (CAN_XIDAM reset_value) Extended ID AND Mask */ + +#define CAN_XIDAM_EIDM_Pos 0 /**< \brief (CAN_XIDAM) Extended ID Mask */ +#define CAN_XIDAM_EIDM_Msk (_U_(0x1FFFFFFF) << CAN_XIDAM_EIDM_Pos) +#define CAN_XIDAM_EIDM(value) (CAN_XIDAM_EIDM_Msk & ((value) << CAN_XIDAM_EIDM_Pos)) +#define CAN_XIDAM_MASK _U_(0x1FFFFFFF) /**< \brief (CAN_XIDAM) MASK Register */ + +/* -------- CAN_HPMS : (CAN Offset: 0x94) (R/ 32) High Priority Message Status -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t BIDX:6; /*!< bit: 0.. 5 Buffer Index */ + uint32_t MSI:2; /*!< bit: 6.. 7 Message Storage Indicator */ + uint32_t FIDX:7; /*!< bit: 8..14 Filter Index */ + uint32_t FLST:1; /*!< bit: 15 Filter List */ + uint32_t :16; /*!< bit: 16..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_HPMS_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_HPMS_OFFSET 0x94 /**< \brief (CAN_HPMS offset) High Priority Message Status */ +#define CAN_HPMS_RESETVALUE _U_(0x00000000) /**< \brief (CAN_HPMS reset_value) High Priority Message Status */ + +#define CAN_HPMS_BIDX_Pos 0 /**< \brief (CAN_HPMS) Buffer Index */ +#define CAN_HPMS_BIDX_Msk (_U_(0x3F) << CAN_HPMS_BIDX_Pos) +#define CAN_HPMS_BIDX(value) (CAN_HPMS_BIDX_Msk & ((value) << CAN_HPMS_BIDX_Pos)) +#define CAN_HPMS_MSI_Pos 6 /**< \brief (CAN_HPMS) Message Storage Indicator */ +#define CAN_HPMS_MSI_Msk (_U_(0x3) << CAN_HPMS_MSI_Pos) +#define CAN_HPMS_MSI(value) (CAN_HPMS_MSI_Msk & ((value) << CAN_HPMS_MSI_Pos)) +#define CAN_HPMS_MSI_NONE_Val _U_(0x0) /**< \brief (CAN_HPMS) No FIFO selected */ +#define CAN_HPMS_MSI_LOST_Val _U_(0x1) /**< \brief (CAN_HPMS) FIFO message lost */ +#define CAN_HPMS_MSI_FIFO0_Val _U_(0x2) /**< \brief (CAN_HPMS) Message stored in FIFO 0 */ +#define CAN_HPMS_MSI_FIFO1_Val _U_(0x3) /**< \brief (CAN_HPMS) Message stored in FIFO 1 */ +#define CAN_HPMS_MSI_NONE (CAN_HPMS_MSI_NONE_Val << CAN_HPMS_MSI_Pos) +#define CAN_HPMS_MSI_LOST (CAN_HPMS_MSI_LOST_Val << CAN_HPMS_MSI_Pos) +#define CAN_HPMS_MSI_FIFO0 (CAN_HPMS_MSI_FIFO0_Val << CAN_HPMS_MSI_Pos) +#define CAN_HPMS_MSI_FIFO1 (CAN_HPMS_MSI_FIFO1_Val << CAN_HPMS_MSI_Pos) +#define CAN_HPMS_FIDX_Pos 8 /**< \brief (CAN_HPMS) Filter Index */ +#define CAN_HPMS_FIDX_Msk (_U_(0x7F) << CAN_HPMS_FIDX_Pos) +#define CAN_HPMS_FIDX(value) (CAN_HPMS_FIDX_Msk & ((value) << CAN_HPMS_FIDX_Pos)) +#define CAN_HPMS_FLST_Pos 15 /**< \brief (CAN_HPMS) Filter List */ +#define CAN_HPMS_FLST (_U_(0x1) << CAN_HPMS_FLST_Pos) +#define CAN_HPMS_MASK _U_(0x0000FFFF) /**< \brief (CAN_HPMS) MASK Register */ + +/* -------- CAN_NDAT1 : (CAN Offset: 0x98) (R/W 32) New Data 1 -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t ND0:1; /*!< bit: 0 New Data 0 */ + uint32_t ND1:1; /*!< bit: 1 New Data 1 */ + uint32_t ND2:1; /*!< bit: 2 New Data 2 */ + uint32_t ND3:1; /*!< bit: 3 New Data 3 */ + uint32_t ND4:1; /*!< bit: 4 New Data 4 */ + uint32_t ND5:1; /*!< bit: 5 New Data 5 */ + uint32_t ND6:1; /*!< bit: 6 New Data 6 */ + uint32_t ND7:1; /*!< bit: 7 New Data 7 */ + uint32_t ND8:1; /*!< bit: 8 New Data 8 */ + uint32_t ND9:1; /*!< bit: 9 New Data 9 */ + uint32_t ND10:1; /*!< bit: 10 New Data 10 */ + uint32_t ND11:1; /*!< bit: 11 New Data 11 */ + uint32_t ND12:1; /*!< bit: 12 New Data 12 */ + uint32_t ND13:1; /*!< bit: 13 New Data 13 */ + uint32_t ND14:1; /*!< bit: 14 New Data 14 */ + uint32_t ND15:1; /*!< bit: 15 New Data 15 */ + uint32_t ND16:1; /*!< bit: 16 New Data 16 */ + uint32_t ND17:1; /*!< bit: 17 New Data 17 */ + uint32_t ND18:1; /*!< bit: 18 New Data 18 */ + uint32_t ND19:1; /*!< bit: 19 New Data 19 */ + uint32_t ND20:1; /*!< bit: 20 New Data 20 */ + uint32_t ND21:1; /*!< bit: 21 New Data 21 */ + uint32_t ND22:1; /*!< bit: 22 New Data 22 */ + uint32_t ND23:1; /*!< bit: 23 New Data 23 */ + uint32_t ND24:1; /*!< bit: 24 New Data 24 */ + uint32_t ND25:1; /*!< bit: 25 New Data 25 */ + uint32_t ND26:1; /*!< bit: 26 New Data 26 */ + uint32_t ND27:1; /*!< bit: 27 New Data 27 */ + uint32_t ND28:1; /*!< bit: 28 New Data 28 */ + uint32_t ND29:1; /*!< bit: 29 New Data 29 */ + uint32_t ND30:1; /*!< bit: 30 New Data 30 */ + uint32_t ND31:1; /*!< bit: 31 New Data 31 */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_NDAT1_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_NDAT1_OFFSET 0x98 /**< \brief (CAN_NDAT1 offset) New Data 1 */ +#define CAN_NDAT1_RESETVALUE _U_(0x00000000) /**< \brief (CAN_NDAT1 reset_value) New Data 1 */ + +#define CAN_NDAT1_ND0_Pos 0 /**< \brief (CAN_NDAT1) New Data 0 */ +#define CAN_NDAT1_ND0 (_U_(0x1) << CAN_NDAT1_ND0_Pos) +#define CAN_NDAT1_ND1_Pos 1 /**< \brief (CAN_NDAT1) New Data 1 */ +#define CAN_NDAT1_ND1 (_U_(0x1) << CAN_NDAT1_ND1_Pos) +#define CAN_NDAT1_ND2_Pos 2 /**< \brief (CAN_NDAT1) New Data 2 */ +#define CAN_NDAT1_ND2 (_U_(0x1) << CAN_NDAT1_ND2_Pos) +#define CAN_NDAT1_ND3_Pos 3 /**< \brief (CAN_NDAT1) New Data 3 */ +#define CAN_NDAT1_ND3 (_U_(0x1) << CAN_NDAT1_ND3_Pos) +#define CAN_NDAT1_ND4_Pos 4 /**< \brief (CAN_NDAT1) New Data 4 */ +#define CAN_NDAT1_ND4 (_U_(0x1) << CAN_NDAT1_ND4_Pos) +#define CAN_NDAT1_ND5_Pos 5 /**< \brief (CAN_NDAT1) New Data 5 */ +#define CAN_NDAT1_ND5 (_U_(0x1) << CAN_NDAT1_ND5_Pos) +#define CAN_NDAT1_ND6_Pos 6 /**< \brief (CAN_NDAT1) New Data 6 */ +#define CAN_NDAT1_ND6 (_U_(0x1) << CAN_NDAT1_ND6_Pos) +#define CAN_NDAT1_ND7_Pos 7 /**< \brief (CAN_NDAT1) New Data 7 */ +#define CAN_NDAT1_ND7 (_U_(0x1) << CAN_NDAT1_ND7_Pos) +#define CAN_NDAT1_ND8_Pos 8 /**< \brief (CAN_NDAT1) New Data 8 */ +#define CAN_NDAT1_ND8 (_U_(0x1) << CAN_NDAT1_ND8_Pos) +#define CAN_NDAT1_ND9_Pos 9 /**< \brief (CAN_NDAT1) New Data 9 */ +#define CAN_NDAT1_ND9 (_U_(0x1) << CAN_NDAT1_ND9_Pos) +#define CAN_NDAT1_ND10_Pos 10 /**< \brief (CAN_NDAT1) New Data 10 */ +#define CAN_NDAT1_ND10 (_U_(0x1) << CAN_NDAT1_ND10_Pos) +#define CAN_NDAT1_ND11_Pos 11 /**< \brief (CAN_NDAT1) New Data 11 */ +#define CAN_NDAT1_ND11 (_U_(0x1) << CAN_NDAT1_ND11_Pos) +#define CAN_NDAT1_ND12_Pos 12 /**< \brief (CAN_NDAT1) New Data 12 */ +#define CAN_NDAT1_ND12 (_U_(0x1) << CAN_NDAT1_ND12_Pos) +#define CAN_NDAT1_ND13_Pos 13 /**< \brief (CAN_NDAT1) New Data 13 */ +#define CAN_NDAT1_ND13 (_U_(0x1) << CAN_NDAT1_ND13_Pos) +#define CAN_NDAT1_ND14_Pos 14 /**< \brief (CAN_NDAT1) New Data 14 */ +#define CAN_NDAT1_ND14 (_U_(0x1) << CAN_NDAT1_ND14_Pos) +#define CAN_NDAT1_ND15_Pos 15 /**< \brief (CAN_NDAT1) New Data 15 */ +#define CAN_NDAT1_ND15 (_U_(0x1) << CAN_NDAT1_ND15_Pos) +#define CAN_NDAT1_ND16_Pos 16 /**< \brief (CAN_NDAT1) New Data 16 */ +#define CAN_NDAT1_ND16 (_U_(0x1) << CAN_NDAT1_ND16_Pos) +#define CAN_NDAT1_ND17_Pos 17 /**< \brief (CAN_NDAT1) New Data 17 */ +#define CAN_NDAT1_ND17 (_U_(0x1) << CAN_NDAT1_ND17_Pos) +#define CAN_NDAT1_ND18_Pos 18 /**< \brief (CAN_NDAT1) New Data 18 */ +#define CAN_NDAT1_ND18 (_U_(0x1) << CAN_NDAT1_ND18_Pos) +#define CAN_NDAT1_ND19_Pos 19 /**< \brief (CAN_NDAT1) New Data 19 */ +#define CAN_NDAT1_ND19 (_U_(0x1) << CAN_NDAT1_ND19_Pos) +#define CAN_NDAT1_ND20_Pos 20 /**< \brief (CAN_NDAT1) New Data 20 */ +#define CAN_NDAT1_ND20 (_U_(0x1) << CAN_NDAT1_ND20_Pos) +#define CAN_NDAT1_ND21_Pos 21 /**< \brief (CAN_NDAT1) New Data 21 */ +#define CAN_NDAT1_ND21 (_U_(0x1) << CAN_NDAT1_ND21_Pos) +#define CAN_NDAT1_ND22_Pos 22 /**< \brief (CAN_NDAT1) New Data 22 */ +#define CAN_NDAT1_ND22 (_U_(0x1) << CAN_NDAT1_ND22_Pos) +#define CAN_NDAT1_ND23_Pos 23 /**< \brief (CAN_NDAT1) New Data 23 */ +#define CAN_NDAT1_ND23 (_U_(0x1) << CAN_NDAT1_ND23_Pos) +#define CAN_NDAT1_ND24_Pos 24 /**< \brief (CAN_NDAT1) New Data 24 */ +#define CAN_NDAT1_ND24 (_U_(0x1) << CAN_NDAT1_ND24_Pos) +#define CAN_NDAT1_ND25_Pos 25 /**< \brief (CAN_NDAT1) New Data 25 */ +#define CAN_NDAT1_ND25 (_U_(0x1) << CAN_NDAT1_ND25_Pos) +#define CAN_NDAT1_ND26_Pos 26 /**< \brief (CAN_NDAT1) New Data 26 */ +#define CAN_NDAT1_ND26 (_U_(0x1) << CAN_NDAT1_ND26_Pos) +#define CAN_NDAT1_ND27_Pos 27 /**< \brief (CAN_NDAT1) New Data 27 */ +#define CAN_NDAT1_ND27 (_U_(0x1) << CAN_NDAT1_ND27_Pos) +#define CAN_NDAT1_ND28_Pos 28 /**< \brief (CAN_NDAT1) New Data 28 */ +#define CAN_NDAT1_ND28 (_U_(0x1) << CAN_NDAT1_ND28_Pos) +#define CAN_NDAT1_ND29_Pos 29 /**< \brief (CAN_NDAT1) New Data 29 */ +#define CAN_NDAT1_ND29 (_U_(0x1) << CAN_NDAT1_ND29_Pos) +#define CAN_NDAT1_ND30_Pos 30 /**< \brief (CAN_NDAT1) New Data 30 */ +#define CAN_NDAT1_ND30 (_U_(0x1) << CAN_NDAT1_ND30_Pos) +#define CAN_NDAT1_ND31_Pos 31 /**< \brief (CAN_NDAT1) New Data 31 */ +#define CAN_NDAT1_ND31 (_U_(0x1) << CAN_NDAT1_ND31_Pos) +#define CAN_NDAT1_MASK _U_(0xFFFFFFFF) /**< \brief (CAN_NDAT1) MASK Register */ + +/* -------- CAN_NDAT2 : (CAN Offset: 0x9C) (R/W 32) New Data 2 -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t ND32:1; /*!< bit: 0 New Data 32 */ + uint32_t ND33:1; /*!< bit: 1 New Data 33 */ + uint32_t ND34:1; /*!< bit: 2 New Data 34 */ + uint32_t ND35:1; /*!< bit: 3 New Data 35 */ + uint32_t ND36:1; /*!< bit: 4 New Data 36 */ + uint32_t ND37:1; /*!< bit: 5 New Data 37 */ + uint32_t ND38:1; /*!< bit: 6 New Data 38 */ + uint32_t ND39:1; /*!< bit: 7 New Data 39 */ + uint32_t ND40:1; /*!< bit: 8 New Data 40 */ + uint32_t ND41:1; /*!< bit: 9 New Data 41 */ + uint32_t ND42:1; /*!< bit: 10 New Data 42 */ + uint32_t ND43:1; /*!< bit: 11 New Data 43 */ + uint32_t ND44:1; /*!< bit: 12 New Data 44 */ + uint32_t ND45:1; /*!< bit: 13 New Data 45 */ + uint32_t ND46:1; /*!< bit: 14 New Data 46 */ + uint32_t ND47:1; /*!< bit: 15 New Data 47 */ + uint32_t ND48:1; /*!< bit: 16 New Data 48 */ + uint32_t ND49:1; /*!< bit: 17 New Data 49 */ + uint32_t ND50:1; /*!< bit: 18 New Data 50 */ + uint32_t ND51:1; /*!< bit: 19 New Data 51 */ + uint32_t ND52:1; /*!< bit: 20 New Data 52 */ + uint32_t ND53:1; /*!< bit: 21 New Data 53 */ + uint32_t ND54:1; /*!< bit: 22 New Data 54 */ + uint32_t ND55:1; /*!< bit: 23 New Data 55 */ + uint32_t ND56:1; /*!< bit: 24 New Data 56 */ + uint32_t ND57:1; /*!< bit: 25 New Data 57 */ + uint32_t ND58:1; /*!< bit: 26 New Data 58 */ + uint32_t ND59:1; /*!< bit: 27 New Data 59 */ + uint32_t ND60:1; /*!< bit: 28 New Data 60 */ + uint32_t ND61:1; /*!< bit: 29 New Data 61 */ + uint32_t ND62:1; /*!< bit: 30 New Data 62 */ + uint32_t ND63:1; /*!< bit: 31 New Data 63 */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_NDAT2_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_NDAT2_OFFSET 0x9C /**< \brief (CAN_NDAT2 offset) New Data 2 */ +#define CAN_NDAT2_RESETVALUE _U_(0x00000000) /**< \brief (CAN_NDAT2 reset_value) New Data 2 */ + +#define CAN_NDAT2_ND32_Pos 0 /**< \brief (CAN_NDAT2) New Data 32 */ +#define CAN_NDAT2_ND32 (_U_(0x1) << CAN_NDAT2_ND32_Pos) +#define CAN_NDAT2_ND33_Pos 1 /**< \brief (CAN_NDAT2) New Data 33 */ +#define CAN_NDAT2_ND33 (_U_(0x1) << CAN_NDAT2_ND33_Pos) +#define CAN_NDAT2_ND34_Pos 2 /**< \brief (CAN_NDAT2) New Data 34 */ +#define CAN_NDAT2_ND34 (_U_(0x1) << CAN_NDAT2_ND34_Pos) +#define CAN_NDAT2_ND35_Pos 3 /**< \brief (CAN_NDAT2) New Data 35 */ +#define CAN_NDAT2_ND35 (_U_(0x1) << CAN_NDAT2_ND35_Pos) +#define CAN_NDAT2_ND36_Pos 4 /**< \brief (CAN_NDAT2) New Data 36 */ +#define CAN_NDAT2_ND36 (_U_(0x1) << CAN_NDAT2_ND36_Pos) +#define CAN_NDAT2_ND37_Pos 5 /**< \brief (CAN_NDAT2) New Data 37 */ +#define CAN_NDAT2_ND37 (_U_(0x1) << CAN_NDAT2_ND37_Pos) +#define CAN_NDAT2_ND38_Pos 6 /**< \brief (CAN_NDAT2) New Data 38 */ +#define CAN_NDAT2_ND38 (_U_(0x1) << CAN_NDAT2_ND38_Pos) +#define CAN_NDAT2_ND39_Pos 7 /**< \brief (CAN_NDAT2) New Data 39 */ +#define CAN_NDAT2_ND39 (_U_(0x1) << CAN_NDAT2_ND39_Pos) +#define CAN_NDAT2_ND40_Pos 8 /**< \brief (CAN_NDAT2) New Data 40 */ +#define CAN_NDAT2_ND40 (_U_(0x1) << CAN_NDAT2_ND40_Pos) +#define CAN_NDAT2_ND41_Pos 9 /**< \brief (CAN_NDAT2) New Data 41 */ +#define CAN_NDAT2_ND41 (_U_(0x1) << CAN_NDAT2_ND41_Pos) +#define CAN_NDAT2_ND42_Pos 10 /**< \brief (CAN_NDAT2) New Data 42 */ +#define CAN_NDAT2_ND42 (_U_(0x1) << CAN_NDAT2_ND42_Pos) +#define CAN_NDAT2_ND43_Pos 11 /**< \brief (CAN_NDAT2) New Data 43 */ +#define CAN_NDAT2_ND43 (_U_(0x1) << CAN_NDAT2_ND43_Pos) +#define CAN_NDAT2_ND44_Pos 12 /**< \brief (CAN_NDAT2) New Data 44 */ +#define CAN_NDAT2_ND44 (_U_(0x1) << CAN_NDAT2_ND44_Pos) +#define CAN_NDAT2_ND45_Pos 13 /**< \brief (CAN_NDAT2) New Data 45 */ +#define CAN_NDAT2_ND45 (_U_(0x1) << CAN_NDAT2_ND45_Pos) +#define CAN_NDAT2_ND46_Pos 14 /**< \brief (CAN_NDAT2) New Data 46 */ +#define CAN_NDAT2_ND46 (_U_(0x1) << CAN_NDAT2_ND46_Pos) +#define CAN_NDAT2_ND47_Pos 15 /**< \brief (CAN_NDAT2) New Data 47 */ +#define CAN_NDAT2_ND47 (_U_(0x1) << CAN_NDAT2_ND47_Pos) +#define CAN_NDAT2_ND48_Pos 16 /**< \brief (CAN_NDAT2) New Data 48 */ +#define CAN_NDAT2_ND48 (_U_(0x1) << CAN_NDAT2_ND48_Pos) +#define CAN_NDAT2_ND49_Pos 17 /**< \brief (CAN_NDAT2) New Data 49 */ +#define CAN_NDAT2_ND49 (_U_(0x1) << CAN_NDAT2_ND49_Pos) +#define CAN_NDAT2_ND50_Pos 18 /**< \brief (CAN_NDAT2) New Data 50 */ +#define CAN_NDAT2_ND50 (_U_(0x1) << CAN_NDAT2_ND50_Pos) +#define CAN_NDAT2_ND51_Pos 19 /**< \brief (CAN_NDAT2) New Data 51 */ +#define CAN_NDAT2_ND51 (_U_(0x1) << CAN_NDAT2_ND51_Pos) +#define CAN_NDAT2_ND52_Pos 20 /**< \brief (CAN_NDAT2) New Data 52 */ +#define CAN_NDAT2_ND52 (_U_(0x1) << CAN_NDAT2_ND52_Pos) +#define CAN_NDAT2_ND53_Pos 21 /**< \brief (CAN_NDAT2) New Data 53 */ +#define CAN_NDAT2_ND53 (_U_(0x1) << CAN_NDAT2_ND53_Pos) +#define CAN_NDAT2_ND54_Pos 22 /**< \brief (CAN_NDAT2) New Data 54 */ +#define CAN_NDAT2_ND54 (_U_(0x1) << CAN_NDAT2_ND54_Pos) +#define CAN_NDAT2_ND55_Pos 23 /**< \brief (CAN_NDAT2) New Data 55 */ +#define CAN_NDAT2_ND55 (_U_(0x1) << CAN_NDAT2_ND55_Pos) +#define CAN_NDAT2_ND56_Pos 24 /**< \brief (CAN_NDAT2) New Data 56 */ +#define CAN_NDAT2_ND56 (_U_(0x1) << CAN_NDAT2_ND56_Pos) +#define CAN_NDAT2_ND57_Pos 25 /**< \brief (CAN_NDAT2) New Data 57 */ +#define CAN_NDAT2_ND57 (_U_(0x1) << CAN_NDAT2_ND57_Pos) +#define CAN_NDAT2_ND58_Pos 26 /**< \brief (CAN_NDAT2) New Data 58 */ +#define CAN_NDAT2_ND58 (_U_(0x1) << CAN_NDAT2_ND58_Pos) +#define CAN_NDAT2_ND59_Pos 27 /**< \brief (CAN_NDAT2) New Data 59 */ +#define CAN_NDAT2_ND59 (_U_(0x1) << CAN_NDAT2_ND59_Pos) +#define CAN_NDAT2_ND60_Pos 28 /**< \brief (CAN_NDAT2) New Data 60 */ +#define CAN_NDAT2_ND60 (_U_(0x1) << CAN_NDAT2_ND60_Pos) +#define CAN_NDAT2_ND61_Pos 29 /**< \brief (CAN_NDAT2) New Data 61 */ +#define CAN_NDAT2_ND61 (_U_(0x1) << CAN_NDAT2_ND61_Pos) +#define CAN_NDAT2_ND62_Pos 30 /**< \brief (CAN_NDAT2) New Data 62 */ +#define CAN_NDAT2_ND62 (_U_(0x1) << CAN_NDAT2_ND62_Pos) +#define CAN_NDAT2_ND63_Pos 31 /**< \brief (CAN_NDAT2) New Data 63 */ +#define CAN_NDAT2_ND63 (_U_(0x1) << CAN_NDAT2_ND63_Pos) +#define CAN_NDAT2_MASK _U_(0xFFFFFFFF) /**< \brief (CAN_NDAT2) MASK Register */ + +/* -------- CAN_RXF0C : (CAN Offset: 0xA0) (R/W 32) Rx FIFO 0 Configuration -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t F0SA:16; /*!< bit: 0..15 Rx FIFO 0 Start Address */ + uint32_t F0S:7; /*!< bit: 16..22 Rx FIFO 0 Size */ + uint32_t :1; /*!< bit: 23 Reserved */ + uint32_t F0WM:7; /*!< bit: 24..30 Rx FIFO 0 Watermark */ + uint32_t F0OM:1; /*!< bit: 31 FIFO 0 Operation Mode */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_RXF0C_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_RXF0C_OFFSET 0xA0 /**< \brief (CAN_RXF0C offset) Rx FIFO 0 Configuration */ +#define CAN_RXF0C_RESETVALUE _U_(0x00000000) /**< \brief (CAN_RXF0C reset_value) Rx FIFO 0 Configuration */ + +#define CAN_RXF0C_F0SA_Pos 0 /**< \brief (CAN_RXF0C) Rx FIFO 0 Start Address */ +#define CAN_RXF0C_F0SA_Msk (_U_(0xFFFF) << CAN_RXF0C_F0SA_Pos) +#define CAN_RXF0C_F0SA(value) (CAN_RXF0C_F0SA_Msk & ((value) << CAN_RXF0C_F0SA_Pos)) +#define CAN_RXF0C_F0S_Pos 16 /**< \brief (CAN_RXF0C) Rx FIFO 0 Size */ +#define CAN_RXF0C_F0S_Msk (_U_(0x7F) << CAN_RXF0C_F0S_Pos) +#define CAN_RXF0C_F0S(value) (CAN_RXF0C_F0S_Msk & ((value) << CAN_RXF0C_F0S_Pos)) +#define CAN_RXF0C_F0WM_Pos 24 /**< \brief (CAN_RXF0C) Rx FIFO 0 Watermark */ +#define CAN_RXF0C_F0WM_Msk (_U_(0x7F) << CAN_RXF0C_F0WM_Pos) +#define CAN_RXF0C_F0WM(value) (CAN_RXF0C_F0WM_Msk & ((value) << CAN_RXF0C_F0WM_Pos)) +#define CAN_RXF0C_F0OM_Pos 31 /**< \brief (CAN_RXF0C) FIFO 0 Operation Mode */ +#define CAN_RXF0C_F0OM (_U_(0x1) << CAN_RXF0C_F0OM_Pos) +#define CAN_RXF0C_MASK _U_(0xFF7FFFFF) /**< \brief (CAN_RXF0C) MASK Register */ + +/* -------- CAN_RXF0S : (CAN Offset: 0xA4) (R/ 32) Rx FIFO 0 Status -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t F0FL:7; /*!< bit: 0.. 6 Rx FIFO 0 Fill Level */ + uint32_t :1; /*!< bit: 7 Reserved */ + uint32_t F0GI:6; /*!< bit: 8..13 Rx FIFO 0 Get Index */ + uint32_t :2; /*!< bit: 14..15 Reserved */ + uint32_t F0PI:6; /*!< bit: 16..21 Rx FIFO 0 Put Index */ + uint32_t :2; /*!< bit: 22..23 Reserved */ + uint32_t F0F:1; /*!< bit: 24 Rx FIFO 0 Full */ + uint32_t RF0L:1; /*!< bit: 25 Rx FIFO 0 Message Lost */ + uint32_t :6; /*!< bit: 26..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_RXF0S_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_RXF0S_OFFSET 0xA4 /**< \brief (CAN_RXF0S offset) Rx FIFO 0 Status */ +#define CAN_RXF0S_RESETVALUE _U_(0x00000000) /**< \brief (CAN_RXF0S reset_value) Rx FIFO 0 Status */ + +#define CAN_RXF0S_F0FL_Pos 0 /**< \brief (CAN_RXF0S) Rx FIFO 0 Fill Level */ +#define CAN_RXF0S_F0FL_Msk (_U_(0x7F) << CAN_RXF0S_F0FL_Pos) +#define CAN_RXF0S_F0FL(value) (CAN_RXF0S_F0FL_Msk & ((value) << CAN_RXF0S_F0FL_Pos)) +#define CAN_RXF0S_F0GI_Pos 8 /**< \brief (CAN_RXF0S) Rx FIFO 0 Get Index */ +#define CAN_RXF0S_F0GI_Msk (_U_(0x3F) << CAN_RXF0S_F0GI_Pos) +#define CAN_RXF0S_F0GI(value) (CAN_RXF0S_F0GI_Msk & ((value) << CAN_RXF0S_F0GI_Pos)) +#define CAN_RXF0S_F0PI_Pos 16 /**< \brief (CAN_RXF0S) Rx FIFO 0 Put Index */ +#define CAN_RXF0S_F0PI_Msk (_U_(0x3F) << CAN_RXF0S_F0PI_Pos) +#define CAN_RXF0S_F0PI(value) (CAN_RXF0S_F0PI_Msk & ((value) << CAN_RXF0S_F0PI_Pos)) +#define CAN_RXF0S_F0F_Pos 24 /**< \brief (CAN_RXF0S) Rx FIFO 0 Full */ +#define CAN_RXF0S_F0F (_U_(0x1) << CAN_RXF0S_F0F_Pos) +#define CAN_RXF0S_RF0L_Pos 25 /**< \brief (CAN_RXF0S) Rx FIFO 0 Message Lost */ +#define CAN_RXF0S_RF0L (_U_(0x1) << CAN_RXF0S_RF0L_Pos) +#define CAN_RXF0S_MASK _U_(0x033F3F7F) /**< \brief (CAN_RXF0S) MASK Register */ + +/* -------- CAN_RXF0A : (CAN Offset: 0xA8) (R/W 32) Rx FIFO 0 Acknowledge -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t F0AI:6; /*!< bit: 0.. 5 Rx FIFO 0 Acknowledge Index */ + uint32_t :26; /*!< bit: 6..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_RXF0A_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_RXF0A_OFFSET 0xA8 /**< \brief (CAN_RXF0A offset) Rx FIFO 0 Acknowledge */ +#define CAN_RXF0A_RESETVALUE _U_(0x00000000) /**< \brief (CAN_RXF0A reset_value) Rx FIFO 0 Acknowledge */ + +#define CAN_RXF0A_F0AI_Pos 0 /**< \brief (CAN_RXF0A) Rx FIFO 0 Acknowledge Index */ +#define CAN_RXF0A_F0AI_Msk (_U_(0x3F) << CAN_RXF0A_F0AI_Pos) +#define CAN_RXF0A_F0AI(value) (CAN_RXF0A_F0AI_Msk & ((value) << CAN_RXF0A_F0AI_Pos)) +#define CAN_RXF0A_MASK _U_(0x0000003F) /**< \brief (CAN_RXF0A) MASK Register */ + +/* -------- CAN_RXBC : (CAN Offset: 0xAC) (R/W 32) Rx Buffer Configuration -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t RBSA:16; /*!< bit: 0..15 Rx Buffer Start Address */ + uint32_t :16; /*!< bit: 16..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_RXBC_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_RXBC_OFFSET 0xAC /**< \brief (CAN_RXBC offset) Rx Buffer Configuration */ +#define CAN_RXBC_RESETVALUE _U_(0x00000000) /**< \brief (CAN_RXBC reset_value) Rx Buffer Configuration */ + +#define CAN_RXBC_RBSA_Pos 0 /**< \brief (CAN_RXBC) Rx Buffer Start Address */ +#define CAN_RXBC_RBSA_Msk (_U_(0xFFFF) << CAN_RXBC_RBSA_Pos) +#define CAN_RXBC_RBSA(value) (CAN_RXBC_RBSA_Msk & ((value) << CAN_RXBC_RBSA_Pos)) +#define CAN_RXBC_MASK _U_(0x0000FFFF) /**< \brief (CAN_RXBC) MASK Register */ + +/* -------- CAN_RXF1C : (CAN Offset: 0xB0) (R/W 32) Rx FIFO 1 Configuration -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t F1SA:16; /*!< bit: 0..15 Rx FIFO 1 Start Address */ + uint32_t F1S:7; /*!< bit: 16..22 Rx FIFO 1 Size */ + uint32_t :1; /*!< bit: 23 Reserved */ + uint32_t F1WM:7; /*!< bit: 24..30 Rx FIFO 1 Watermark */ + uint32_t F1OM:1; /*!< bit: 31 FIFO 1 Operation Mode */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_RXF1C_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_RXF1C_OFFSET 0xB0 /**< \brief (CAN_RXF1C offset) Rx FIFO 1 Configuration */ +#define CAN_RXF1C_RESETVALUE _U_(0x00000000) /**< \brief (CAN_RXF1C reset_value) Rx FIFO 1 Configuration */ + +#define CAN_RXF1C_F1SA_Pos 0 /**< \brief (CAN_RXF1C) Rx FIFO 1 Start Address */ +#define CAN_RXF1C_F1SA_Msk (_U_(0xFFFF) << CAN_RXF1C_F1SA_Pos) +#define CAN_RXF1C_F1SA(value) (CAN_RXF1C_F1SA_Msk & ((value) << CAN_RXF1C_F1SA_Pos)) +#define CAN_RXF1C_F1S_Pos 16 /**< \brief (CAN_RXF1C) Rx FIFO 1 Size */ +#define CAN_RXF1C_F1S_Msk (_U_(0x7F) << CAN_RXF1C_F1S_Pos) +#define CAN_RXF1C_F1S(value) (CAN_RXF1C_F1S_Msk & ((value) << CAN_RXF1C_F1S_Pos)) +#define CAN_RXF1C_F1WM_Pos 24 /**< \brief (CAN_RXF1C) Rx FIFO 1 Watermark */ +#define CAN_RXF1C_F1WM_Msk (_U_(0x7F) << CAN_RXF1C_F1WM_Pos) +#define CAN_RXF1C_F1WM(value) (CAN_RXF1C_F1WM_Msk & ((value) << CAN_RXF1C_F1WM_Pos)) +#define CAN_RXF1C_F1OM_Pos 31 /**< \brief (CAN_RXF1C) FIFO 1 Operation Mode */ +#define CAN_RXF1C_F1OM (_U_(0x1) << CAN_RXF1C_F1OM_Pos) +#define CAN_RXF1C_MASK _U_(0xFF7FFFFF) /**< \brief (CAN_RXF1C) MASK Register */ + +/* -------- CAN_RXF1S : (CAN Offset: 0xB4) (R/ 32) Rx FIFO 1 Status -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t F1FL:7; /*!< bit: 0.. 6 Rx FIFO 1 Fill Level */ + uint32_t :1; /*!< bit: 7 Reserved */ + uint32_t F1GI:6; /*!< bit: 8..13 Rx FIFO 1 Get Index */ + uint32_t :2; /*!< bit: 14..15 Reserved */ + uint32_t F1PI:6; /*!< bit: 16..21 Rx FIFO 1 Put Index */ + uint32_t :2; /*!< bit: 22..23 Reserved */ + uint32_t F1F:1; /*!< bit: 24 Rx FIFO 1 Full */ + uint32_t RF1L:1; /*!< bit: 25 Rx FIFO 1 Message Lost */ + uint32_t :4; /*!< bit: 26..29 Reserved */ + uint32_t DMS:2; /*!< bit: 30..31 Debug Message Status */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_RXF1S_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_RXF1S_OFFSET 0xB4 /**< \brief (CAN_RXF1S offset) Rx FIFO 1 Status */ +#define CAN_RXF1S_RESETVALUE _U_(0x00000000) /**< \brief (CAN_RXF1S reset_value) Rx FIFO 1 Status */ + +#define CAN_RXF1S_F1FL_Pos 0 /**< \brief (CAN_RXF1S) Rx FIFO 1 Fill Level */ +#define CAN_RXF1S_F1FL_Msk (_U_(0x7F) << CAN_RXF1S_F1FL_Pos) +#define CAN_RXF1S_F1FL(value) (CAN_RXF1S_F1FL_Msk & ((value) << CAN_RXF1S_F1FL_Pos)) +#define CAN_RXF1S_F1GI_Pos 8 /**< \brief (CAN_RXF1S) Rx FIFO 1 Get Index */ +#define CAN_RXF1S_F1GI_Msk (_U_(0x3F) << CAN_RXF1S_F1GI_Pos) +#define CAN_RXF1S_F1GI(value) (CAN_RXF1S_F1GI_Msk & ((value) << CAN_RXF1S_F1GI_Pos)) +#define CAN_RXF1S_F1PI_Pos 16 /**< \brief (CAN_RXF1S) Rx FIFO 1 Put Index */ +#define CAN_RXF1S_F1PI_Msk (_U_(0x3F) << CAN_RXF1S_F1PI_Pos) +#define CAN_RXF1S_F1PI(value) (CAN_RXF1S_F1PI_Msk & ((value) << CAN_RXF1S_F1PI_Pos)) +#define CAN_RXF1S_F1F_Pos 24 /**< \brief (CAN_RXF1S) Rx FIFO 1 Full */ +#define CAN_RXF1S_F1F (_U_(0x1) << CAN_RXF1S_F1F_Pos) +#define CAN_RXF1S_RF1L_Pos 25 /**< \brief (CAN_RXF1S) Rx FIFO 1 Message Lost */ +#define CAN_RXF1S_RF1L (_U_(0x1) << CAN_RXF1S_RF1L_Pos) +#define CAN_RXF1S_DMS_Pos 30 /**< \brief (CAN_RXF1S) Debug Message Status */ +#define CAN_RXF1S_DMS_Msk (_U_(0x3) << CAN_RXF1S_DMS_Pos) +#define CAN_RXF1S_DMS(value) (CAN_RXF1S_DMS_Msk & ((value) << CAN_RXF1S_DMS_Pos)) +#define CAN_RXF1S_DMS_IDLE_Val _U_(0x0) /**< \brief (CAN_RXF1S) Idle state */ +#define CAN_RXF1S_DMS_DBGA_Val _U_(0x1) /**< \brief (CAN_RXF1S) Debug message A received */ +#define CAN_RXF1S_DMS_DBGB_Val _U_(0x2) /**< \brief (CAN_RXF1S) Debug message A/B received */ +#define CAN_RXF1S_DMS_DBGC_Val _U_(0x3) /**< \brief (CAN_RXF1S) Debug message A/B/C received, DMA request set */ +#define CAN_RXF1S_DMS_IDLE (CAN_RXF1S_DMS_IDLE_Val << CAN_RXF1S_DMS_Pos) +#define CAN_RXF1S_DMS_DBGA (CAN_RXF1S_DMS_DBGA_Val << CAN_RXF1S_DMS_Pos) +#define CAN_RXF1S_DMS_DBGB (CAN_RXF1S_DMS_DBGB_Val << CAN_RXF1S_DMS_Pos) +#define CAN_RXF1S_DMS_DBGC (CAN_RXF1S_DMS_DBGC_Val << CAN_RXF1S_DMS_Pos) +#define CAN_RXF1S_MASK _U_(0xC33F3F7F) /**< \brief (CAN_RXF1S) MASK Register */ + +/* -------- CAN_RXF1A : (CAN Offset: 0xB8) (R/W 32) Rx FIFO 1 Acknowledge -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t F1AI:6; /*!< bit: 0.. 5 Rx FIFO 1 Acknowledge Index */ + uint32_t :26; /*!< bit: 6..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_RXF1A_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_RXF1A_OFFSET 0xB8 /**< \brief (CAN_RXF1A offset) Rx FIFO 1 Acknowledge */ +#define CAN_RXF1A_RESETVALUE _U_(0x00000000) /**< \brief (CAN_RXF1A reset_value) Rx FIFO 1 Acknowledge */ + +#define CAN_RXF1A_F1AI_Pos 0 /**< \brief (CAN_RXF1A) Rx FIFO 1 Acknowledge Index */ +#define CAN_RXF1A_F1AI_Msk (_U_(0x3F) << CAN_RXF1A_F1AI_Pos) +#define CAN_RXF1A_F1AI(value) (CAN_RXF1A_F1AI_Msk & ((value) << CAN_RXF1A_F1AI_Pos)) +#define CAN_RXF1A_MASK _U_(0x0000003F) /**< \brief (CAN_RXF1A) MASK Register */ + +/* -------- CAN_RXESC : (CAN Offset: 0xBC) (R/W 32) Rx Buffer / FIFO Element Size Configuration -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t F0DS:3; /*!< bit: 0.. 2 Rx FIFO 0 Data Field Size */ + uint32_t :1; /*!< bit: 3 Reserved */ + uint32_t F1DS:3; /*!< bit: 4.. 6 Rx FIFO 1 Data Field Size */ + uint32_t :1; /*!< bit: 7 Reserved */ + uint32_t RBDS:3; /*!< bit: 8..10 Rx Buffer Data Field Size */ + uint32_t :21; /*!< bit: 11..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_RXESC_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_RXESC_OFFSET 0xBC /**< \brief (CAN_RXESC offset) Rx Buffer / FIFO Element Size Configuration */ +#define CAN_RXESC_RESETVALUE _U_(0x00000000) /**< \brief (CAN_RXESC reset_value) Rx Buffer / FIFO Element Size Configuration */ + +#define CAN_RXESC_F0DS_Pos 0 /**< \brief (CAN_RXESC) Rx FIFO 0 Data Field Size */ +#define CAN_RXESC_F0DS_Msk (_U_(0x7) << CAN_RXESC_F0DS_Pos) +#define CAN_RXESC_F0DS(value) (CAN_RXESC_F0DS_Msk & ((value) << CAN_RXESC_F0DS_Pos)) +#define CAN_RXESC_F0DS_DATA8_Val _U_(0x0) /**< \brief (CAN_RXESC) 8 byte data field */ +#define CAN_RXESC_F0DS_DATA12_Val _U_(0x1) /**< \brief (CAN_RXESC) 12 byte data field */ +#define CAN_RXESC_F0DS_DATA16_Val _U_(0x2) /**< \brief (CAN_RXESC) 16 byte data field */ +#define CAN_RXESC_F0DS_DATA20_Val _U_(0x3) /**< \brief (CAN_RXESC) 20 byte data field */ +#define CAN_RXESC_F0DS_DATA24_Val _U_(0x4) /**< \brief (CAN_RXESC) 24 byte data field */ +#define CAN_RXESC_F0DS_DATA32_Val _U_(0x5) /**< \brief (CAN_RXESC) 32 byte data field */ +#define CAN_RXESC_F0DS_DATA48_Val _U_(0x6) /**< \brief (CAN_RXESC) 48 byte data field */ +#define CAN_RXESC_F0DS_DATA64_Val _U_(0x7) /**< \brief (CAN_RXESC) 64 byte data field */ +#define CAN_RXESC_F0DS_DATA8 (CAN_RXESC_F0DS_DATA8_Val << CAN_RXESC_F0DS_Pos) +#define CAN_RXESC_F0DS_DATA12 (CAN_RXESC_F0DS_DATA12_Val << CAN_RXESC_F0DS_Pos) +#define CAN_RXESC_F0DS_DATA16 (CAN_RXESC_F0DS_DATA16_Val << CAN_RXESC_F0DS_Pos) +#define CAN_RXESC_F0DS_DATA20 (CAN_RXESC_F0DS_DATA20_Val << CAN_RXESC_F0DS_Pos) +#define CAN_RXESC_F0DS_DATA24 (CAN_RXESC_F0DS_DATA24_Val << CAN_RXESC_F0DS_Pos) +#define CAN_RXESC_F0DS_DATA32 (CAN_RXESC_F0DS_DATA32_Val << CAN_RXESC_F0DS_Pos) +#define CAN_RXESC_F0DS_DATA48 (CAN_RXESC_F0DS_DATA48_Val << CAN_RXESC_F0DS_Pos) +#define CAN_RXESC_F0DS_DATA64 (CAN_RXESC_F0DS_DATA64_Val << CAN_RXESC_F0DS_Pos) +#define CAN_RXESC_F1DS_Pos 4 /**< \brief (CAN_RXESC) Rx FIFO 1 Data Field Size */ +#define CAN_RXESC_F1DS_Msk (_U_(0x7) << CAN_RXESC_F1DS_Pos) +#define CAN_RXESC_F1DS(value) (CAN_RXESC_F1DS_Msk & ((value) << CAN_RXESC_F1DS_Pos)) +#define CAN_RXESC_F1DS_DATA8_Val _U_(0x0) /**< \brief (CAN_RXESC) 8 byte data field */ +#define CAN_RXESC_F1DS_DATA12_Val _U_(0x1) /**< \brief (CAN_RXESC) 12 byte data field */ +#define CAN_RXESC_F1DS_DATA16_Val _U_(0x2) /**< \brief (CAN_RXESC) 16 byte data field */ +#define CAN_RXESC_F1DS_DATA20_Val _U_(0x3) /**< \brief (CAN_RXESC) 20 byte data field */ +#define CAN_RXESC_F1DS_DATA24_Val _U_(0x4) /**< \brief (CAN_RXESC) 24 byte data field */ +#define CAN_RXESC_F1DS_DATA32_Val _U_(0x5) /**< \brief (CAN_RXESC) 32 byte data field */ +#define CAN_RXESC_F1DS_DATA48_Val _U_(0x6) /**< \brief (CAN_RXESC) 48 byte data field */ +#define CAN_RXESC_F1DS_DATA64_Val _U_(0x7) /**< \brief (CAN_RXESC) 64 byte data field */ +#define CAN_RXESC_F1DS_DATA8 (CAN_RXESC_F1DS_DATA8_Val << CAN_RXESC_F1DS_Pos) +#define CAN_RXESC_F1DS_DATA12 (CAN_RXESC_F1DS_DATA12_Val << CAN_RXESC_F1DS_Pos) +#define CAN_RXESC_F1DS_DATA16 (CAN_RXESC_F1DS_DATA16_Val << CAN_RXESC_F1DS_Pos) +#define CAN_RXESC_F1DS_DATA20 (CAN_RXESC_F1DS_DATA20_Val << CAN_RXESC_F1DS_Pos) +#define CAN_RXESC_F1DS_DATA24 (CAN_RXESC_F1DS_DATA24_Val << CAN_RXESC_F1DS_Pos) +#define CAN_RXESC_F1DS_DATA32 (CAN_RXESC_F1DS_DATA32_Val << CAN_RXESC_F1DS_Pos) +#define CAN_RXESC_F1DS_DATA48 (CAN_RXESC_F1DS_DATA48_Val << CAN_RXESC_F1DS_Pos) +#define CAN_RXESC_F1DS_DATA64 (CAN_RXESC_F1DS_DATA64_Val << CAN_RXESC_F1DS_Pos) +#define CAN_RXESC_RBDS_Pos 8 /**< \brief (CAN_RXESC) Rx Buffer Data Field Size */ +#define CAN_RXESC_RBDS_Msk (_U_(0x7) << CAN_RXESC_RBDS_Pos) +#define CAN_RXESC_RBDS(value) (CAN_RXESC_RBDS_Msk & ((value) << CAN_RXESC_RBDS_Pos)) +#define CAN_RXESC_RBDS_DATA8_Val _U_(0x0) /**< \brief (CAN_RXESC) 8 byte data field */ +#define CAN_RXESC_RBDS_DATA12_Val _U_(0x1) /**< \brief (CAN_RXESC) 12 byte data field */ +#define CAN_RXESC_RBDS_DATA16_Val _U_(0x2) /**< \brief (CAN_RXESC) 16 byte data field */ +#define CAN_RXESC_RBDS_DATA20_Val _U_(0x3) /**< \brief (CAN_RXESC) 20 byte data field */ +#define CAN_RXESC_RBDS_DATA24_Val _U_(0x4) /**< \brief (CAN_RXESC) 24 byte data field */ +#define CAN_RXESC_RBDS_DATA32_Val _U_(0x5) /**< \brief (CAN_RXESC) 32 byte data field */ +#define CAN_RXESC_RBDS_DATA48_Val _U_(0x6) /**< \brief (CAN_RXESC) 48 byte data field */ +#define CAN_RXESC_RBDS_DATA64_Val _U_(0x7) /**< \brief (CAN_RXESC) 64 byte data field */ +#define CAN_RXESC_RBDS_DATA8 (CAN_RXESC_RBDS_DATA8_Val << CAN_RXESC_RBDS_Pos) +#define CAN_RXESC_RBDS_DATA12 (CAN_RXESC_RBDS_DATA12_Val << CAN_RXESC_RBDS_Pos) +#define CAN_RXESC_RBDS_DATA16 (CAN_RXESC_RBDS_DATA16_Val << CAN_RXESC_RBDS_Pos) +#define CAN_RXESC_RBDS_DATA20 (CAN_RXESC_RBDS_DATA20_Val << CAN_RXESC_RBDS_Pos) +#define CAN_RXESC_RBDS_DATA24 (CAN_RXESC_RBDS_DATA24_Val << CAN_RXESC_RBDS_Pos) +#define CAN_RXESC_RBDS_DATA32 (CAN_RXESC_RBDS_DATA32_Val << CAN_RXESC_RBDS_Pos) +#define CAN_RXESC_RBDS_DATA48 (CAN_RXESC_RBDS_DATA48_Val << CAN_RXESC_RBDS_Pos) +#define CAN_RXESC_RBDS_DATA64 (CAN_RXESC_RBDS_DATA64_Val << CAN_RXESC_RBDS_Pos) +#define CAN_RXESC_MASK _U_(0x00000777) /**< \brief (CAN_RXESC) MASK Register */ + +/* -------- CAN_TXBC : (CAN Offset: 0xC0) (R/W 32) Tx Buffer Configuration -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t TBSA:16; /*!< bit: 0..15 Tx Buffers Start Address */ + uint32_t NDTB:6; /*!< bit: 16..21 Number of Dedicated Transmit Buffers */ + uint32_t :2; /*!< bit: 22..23 Reserved */ + uint32_t TFQS:6; /*!< bit: 24..29 Transmit FIFO/Queue Size */ + uint32_t TFQM:1; /*!< bit: 30 Tx FIFO/Queue Mode */ + uint32_t :1; /*!< bit: 31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_TXBC_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_TXBC_OFFSET 0xC0 /**< \brief (CAN_TXBC offset) Tx Buffer Configuration */ +#define CAN_TXBC_RESETVALUE _U_(0x00000000) /**< \brief (CAN_TXBC reset_value) Tx Buffer Configuration */ + +#define CAN_TXBC_TBSA_Pos 0 /**< \brief (CAN_TXBC) Tx Buffers Start Address */ +#define CAN_TXBC_TBSA_Msk (_U_(0xFFFF) << CAN_TXBC_TBSA_Pos) +#define CAN_TXBC_TBSA(value) (CAN_TXBC_TBSA_Msk & ((value) << CAN_TXBC_TBSA_Pos)) +#define CAN_TXBC_NDTB_Pos 16 /**< \brief (CAN_TXBC) Number of Dedicated Transmit Buffers */ +#define CAN_TXBC_NDTB_Msk (_U_(0x3F) << CAN_TXBC_NDTB_Pos) +#define CAN_TXBC_NDTB(value) (CAN_TXBC_NDTB_Msk & ((value) << CAN_TXBC_NDTB_Pos)) +#define CAN_TXBC_TFQS_Pos 24 /**< \brief (CAN_TXBC) Transmit FIFO/Queue Size */ +#define CAN_TXBC_TFQS_Msk (_U_(0x3F) << CAN_TXBC_TFQS_Pos) +#define CAN_TXBC_TFQS(value) (CAN_TXBC_TFQS_Msk & ((value) << CAN_TXBC_TFQS_Pos)) +#define CAN_TXBC_TFQM_Pos 30 /**< \brief (CAN_TXBC) Tx FIFO/Queue Mode */ +#define CAN_TXBC_TFQM (_U_(0x1) << CAN_TXBC_TFQM_Pos) +#define CAN_TXBC_MASK _U_(0x7F3FFFFF) /**< \brief (CAN_TXBC) MASK Register */ + +/* -------- CAN_TXFQS : (CAN Offset: 0xC4) (R/ 32) Tx FIFO / Queue Status -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t TFFL:6; /*!< bit: 0.. 5 Tx FIFO Free Level */ + uint32_t :2; /*!< bit: 6.. 7 Reserved */ + uint32_t TFGI:5; /*!< bit: 8..12 Tx FIFO Get Index */ + uint32_t :3; /*!< bit: 13..15 Reserved */ + uint32_t TFQPI:5; /*!< bit: 16..20 Tx FIFO/Queue Put Index */ + uint32_t TFQF:1; /*!< bit: 21 Tx FIFO/Queue Full */ + uint32_t :10; /*!< bit: 22..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_TXFQS_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_TXFQS_OFFSET 0xC4 /**< \brief (CAN_TXFQS offset) Tx FIFO / Queue Status */ +#define CAN_TXFQS_RESETVALUE _U_(0x00000000) /**< \brief (CAN_TXFQS reset_value) Tx FIFO / Queue Status */ + +#define CAN_TXFQS_TFFL_Pos 0 /**< \brief (CAN_TXFQS) Tx FIFO Free Level */ +#define CAN_TXFQS_TFFL_Msk (_U_(0x3F) << CAN_TXFQS_TFFL_Pos) +#define CAN_TXFQS_TFFL(value) (CAN_TXFQS_TFFL_Msk & ((value) << CAN_TXFQS_TFFL_Pos)) +#define CAN_TXFQS_TFGI_Pos 8 /**< \brief (CAN_TXFQS) Tx FIFO Get Index */ +#define CAN_TXFQS_TFGI_Msk (_U_(0x1F) << CAN_TXFQS_TFGI_Pos) +#define CAN_TXFQS_TFGI(value) (CAN_TXFQS_TFGI_Msk & ((value) << CAN_TXFQS_TFGI_Pos)) +#define CAN_TXFQS_TFQPI_Pos 16 /**< \brief (CAN_TXFQS) Tx FIFO/Queue Put Index */ +#define CAN_TXFQS_TFQPI_Msk (_U_(0x1F) << CAN_TXFQS_TFQPI_Pos) +#define CAN_TXFQS_TFQPI(value) (CAN_TXFQS_TFQPI_Msk & ((value) << CAN_TXFQS_TFQPI_Pos)) +#define CAN_TXFQS_TFQF_Pos 21 /**< \brief (CAN_TXFQS) Tx FIFO/Queue Full */ +#define CAN_TXFQS_TFQF (_U_(0x1) << CAN_TXFQS_TFQF_Pos) +#define CAN_TXFQS_MASK _U_(0x003F1F3F) /**< \brief (CAN_TXFQS) MASK Register */ + +/* -------- CAN_TXESC : (CAN Offset: 0xC8) (R/W 32) Tx Buffer Element Size Configuration -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t TBDS:3; /*!< bit: 0.. 2 Tx Buffer Data Field Size */ + uint32_t :29; /*!< bit: 3..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_TXESC_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_TXESC_OFFSET 0xC8 /**< \brief (CAN_TXESC offset) Tx Buffer Element Size Configuration */ +#define CAN_TXESC_RESETVALUE _U_(0x00000000) /**< \brief (CAN_TXESC reset_value) Tx Buffer Element Size Configuration */ + +#define CAN_TXESC_TBDS_Pos 0 /**< \brief (CAN_TXESC) Tx Buffer Data Field Size */ +#define CAN_TXESC_TBDS_Msk (_U_(0x7) << CAN_TXESC_TBDS_Pos) +#define CAN_TXESC_TBDS(value) (CAN_TXESC_TBDS_Msk & ((value) << CAN_TXESC_TBDS_Pos)) +#define CAN_TXESC_TBDS_DATA8_Val _U_(0x0) /**< \brief (CAN_TXESC) 8 byte data field */ +#define CAN_TXESC_TBDS_DATA12_Val _U_(0x1) /**< \brief (CAN_TXESC) 12 byte data field */ +#define CAN_TXESC_TBDS_DATA16_Val _U_(0x2) /**< \brief (CAN_TXESC) 16 byte data field */ +#define CAN_TXESC_TBDS_DATA20_Val _U_(0x3) /**< \brief (CAN_TXESC) 20 byte data field */ +#define CAN_TXESC_TBDS_DATA24_Val _U_(0x4) /**< \brief (CAN_TXESC) 24 byte data field */ +#define CAN_TXESC_TBDS_DATA32_Val _U_(0x5) /**< \brief (CAN_TXESC) 32 byte data field */ +#define CAN_TXESC_TBDS_DATA48_Val _U_(0x6) /**< \brief (CAN_TXESC) 48 byte data field */ +#define CAN_TXESC_TBDS_DATA64_Val _U_(0x7) /**< \brief (CAN_TXESC) 64 byte data field */ +#define CAN_TXESC_TBDS_DATA8 (CAN_TXESC_TBDS_DATA8_Val << CAN_TXESC_TBDS_Pos) +#define CAN_TXESC_TBDS_DATA12 (CAN_TXESC_TBDS_DATA12_Val << CAN_TXESC_TBDS_Pos) +#define CAN_TXESC_TBDS_DATA16 (CAN_TXESC_TBDS_DATA16_Val << CAN_TXESC_TBDS_Pos) +#define CAN_TXESC_TBDS_DATA20 (CAN_TXESC_TBDS_DATA20_Val << CAN_TXESC_TBDS_Pos) +#define CAN_TXESC_TBDS_DATA24 (CAN_TXESC_TBDS_DATA24_Val << CAN_TXESC_TBDS_Pos) +#define CAN_TXESC_TBDS_DATA32 (CAN_TXESC_TBDS_DATA32_Val << CAN_TXESC_TBDS_Pos) +#define CAN_TXESC_TBDS_DATA48 (CAN_TXESC_TBDS_DATA48_Val << CAN_TXESC_TBDS_Pos) +#define CAN_TXESC_TBDS_DATA64 (CAN_TXESC_TBDS_DATA64_Val << CAN_TXESC_TBDS_Pos) +#define CAN_TXESC_MASK _U_(0x00000007) /**< \brief (CAN_TXESC) MASK Register */ + +/* -------- CAN_TXBRP : (CAN Offset: 0xCC) (R/ 32) Tx Buffer Request Pending -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t TRP0:1; /*!< bit: 0 Transmission Request Pending 0 */ + uint32_t TRP1:1; /*!< bit: 1 Transmission Request Pending 1 */ + uint32_t TRP2:1; /*!< bit: 2 Transmission Request Pending 2 */ + uint32_t TRP3:1; /*!< bit: 3 Transmission Request Pending 3 */ + uint32_t TRP4:1; /*!< bit: 4 Transmission Request Pending 4 */ + uint32_t TRP5:1; /*!< bit: 5 Transmission Request Pending 5 */ + uint32_t TRP6:1; /*!< bit: 6 Transmission Request Pending 6 */ + uint32_t TRP7:1; /*!< bit: 7 Transmission Request Pending 7 */ + uint32_t TRP8:1; /*!< bit: 8 Transmission Request Pending 8 */ + uint32_t TRP9:1; /*!< bit: 9 Transmission Request Pending 9 */ + uint32_t TRP10:1; /*!< bit: 10 Transmission Request Pending 10 */ + uint32_t TRP11:1; /*!< bit: 11 Transmission Request Pending 11 */ + uint32_t TRP12:1; /*!< bit: 12 Transmission Request Pending 12 */ + uint32_t TRP13:1; /*!< bit: 13 Transmission Request Pending 13 */ + uint32_t TRP14:1; /*!< bit: 14 Transmission Request Pending 14 */ + uint32_t TRP15:1; /*!< bit: 15 Transmission Request Pending 15 */ + uint32_t TRP16:1; /*!< bit: 16 Transmission Request Pending 16 */ + uint32_t TRP17:1; /*!< bit: 17 Transmission Request Pending 17 */ + uint32_t TRP18:1; /*!< bit: 18 Transmission Request Pending 18 */ + uint32_t TRP19:1; /*!< bit: 19 Transmission Request Pending 19 */ + uint32_t TRP20:1; /*!< bit: 20 Transmission Request Pending 20 */ + uint32_t TRP21:1; /*!< bit: 21 Transmission Request Pending 21 */ + uint32_t TRP22:1; /*!< bit: 22 Transmission Request Pending 22 */ + uint32_t TRP23:1; /*!< bit: 23 Transmission Request Pending 23 */ + uint32_t TRP24:1; /*!< bit: 24 Transmission Request Pending 24 */ + uint32_t TRP25:1; /*!< bit: 25 Transmission Request Pending 25 */ + uint32_t TRP26:1; /*!< bit: 26 Transmission Request Pending 26 */ + uint32_t TRP27:1; /*!< bit: 27 Transmission Request Pending 27 */ + uint32_t TRP28:1; /*!< bit: 28 Transmission Request Pending 28 */ + uint32_t TRP29:1; /*!< bit: 29 Transmission Request Pending 29 */ + uint32_t TRP30:1; /*!< bit: 30 Transmission Request Pending 30 */ + uint32_t TRP31:1; /*!< bit: 31 Transmission Request Pending 31 */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_TXBRP_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_TXBRP_OFFSET 0xCC /**< \brief (CAN_TXBRP offset) Tx Buffer Request Pending */ +#define CAN_TXBRP_RESETVALUE _U_(0x00000000) /**< \brief (CAN_TXBRP reset_value) Tx Buffer Request Pending */ + +#define CAN_TXBRP_TRP0_Pos 0 /**< \brief (CAN_TXBRP) Transmission Request Pending 0 */ +#define CAN_TXBRP_TRP0 (_U_(0x1) << CAN_TXBRP_TRP0_Pos) +#define CAN_TXBRP_TRP1_Pos 1 /**< \brief (CAN_TXBRP) Transmission Request Pending 1 */ +#define CAN_TXBRP_TRP1 (_U_(0x1) << CAN_TXBRP_TRP1_Pos) +#define CAN_TXBRP_TRP2_Pos 2 /**< \brief (CAN_TXBRP) Transmission Request Pending 2 */ +#define CAN_TXBRP_TRP2 (_U_(0x1) << CAN_TXBRP_TRP2_Pos) +#define CAN_TXBRP_TRP3_Pos 3 /**< \brief (CAN_TXBRP) Transmission Request Pending 3 */ +#define CAN_TXBRP_TRP3 (_U_(0x1) << CAN_TXBRP_TRP3_Pos) +#define CAN_TXBRP_TRP4_Pos 4 /**< \brief (CAN_TXBRP) Transmission Request Pending 4 */ +#define CAN_TXBRP_TRP4 (_U_(0x1) << CAN_TXBRP_TRP4_Pos) +#define CAN_TXBRP_TRP5_Pos 5 /**< \brief (CAN_TXBRP) Transmission Request Pending 5 */ +#define CAN_TXBRP_TRP5 (_U_(0x1) << CAN_TXBRP_TRP5_Pos) +#define CAN_TXBRP_TRP6_Pos 6 /**< \brief (CAN_TXBRP) Transmission Request Pending 6 */ +#define CAN_TXBRP_TRP6 (_U_(0x1) << CAN_TXBRP_TRP6_Pos) +#define CAN_TXBRP_TRP7_Pos 7 /**< \brief (CAN_TXBRP) Transmission Request Pending 7 */ +#define CAN_TXBRP_TRP7 (_U_(0x1) << CAN_TXBRP_TRP7_Pos) +#define CAN_TXBRP_TRP8_Pos 8 /**< \brief (CAN_TXBRP) Transmission Request Pending 8 */ +#define CAN_TXBRP_TRP8 (_U_(0x1) << CAN_TXBRP_TRP8_Pos) +#define CAN_TXBRP_TRP9_Pos 9 /**< \brief (CAN_TXBRP) Transmission Request Pending 9 */ +#define CAN_TXBRP_TRP9 (_U_(0x1) << CAN_TXBRP_TRP9_Pos) +#define CAN_TXBRP_TRP10_Pos 10 /**< \brief (CAN_TXBRP) Transmission Request Pending 10 */ +#define CAN_TXBRP_TRP10 (_U_(0x1) << CAN_TXBRP_TRP10_Pos) +#define CAN_TXBRP_TRP11_Pos 11 /**< \brief (CAN_TXBRP) Transmission Request Pending 11 */ +#define CAN_TXBRP_TRP11 (_U_(0x1) << CAN_TXBRP_TRP11_Pos) +#define CAN_TXBRP_TRP12_Pos 12 /**< \brief (CAN_TXBRP) Transmission Request Pending 12 */ +#define CAN_TXBRP_TRP12 (_U_(0x1) << CAN_TXBRP_TRP12_Pos) +#define CAN_TXBRP_TRP13_Pos 13 /**< \brief (CAN_TXBRP) Transmission Request Pending 13 */ +#define CAN_TXBRP_TRP13 (_U_(0x1) << CAN_TXBRP_TRP13_Pos) +#define CAN_TXBRP_TRP14_Pos 14 /**< \brief (CAN_TXBRP) Transmission Request Pending 14 */ +#define CAN_TXBRP_TRP14 (_U_(0x1) << CAN_TXBRP_TRP14_Pos) +#define CAN_TXBRP_TRP15_Pos 15 /**< \brief (CAN_TXBRP) Transmission Request Pending 15 */ +#define CAN_TXBRP_TRP15 (_U_(0x1) << CAN_TXBRP_TRP15_Pos) +#define CAN_TXBRP_TRP16_Pos 16 /**< \brief (CAN_TXBRP) Transmission Request Pending 16 */ +#define CAN_TXBRP_TRP16 (_U_(0x1) << CAN_TXBRP_TRP16_Pos) +#define CAN_TXBRP_TRP17_Pos 17 /**< \brief (CAN_TXBRP) Transmission Request Pending 17 */ +#define CAN_TXBRP_TRP17 (_U_(0x1) << CAN_TXBRP_TRP17_Pos) +#define CAN_TXBRP_TRP18_Pos 18 /**< \brief (CAN_TXBRP) Transmission Request Pending 18 */ +#define CAN_TXBRP_TRP18 (_U_(0x1) << CAN_TXBRP_TRP18_Pos) +#define CAN_TXBRP_TRP19_Pos 19 /**< \brief (CAN_TXBRP) Transmission Request Pending 19 */ +#define CAN_TXBRP_TRP19 (_U_(0x1) << CAN_TXBRP_TRP19_Pos) +#define CAN_TXBRP_TRP20_Pos 20 /**< \brief (CAN_TXBRP) Transmission Request Pending 20 */ +#define CAN_TXBRP_TRP20 (_U_(0x1) << CAN_TXBRP_TRP20_Pos) +#define CAN_TXBRP_TRP21_Pos 21 /**< \brief (CAN_TXBRP) Transmission Request Pending 21 */ +#define CAN_TXBRP_TRP21 (_U_(0x1) << CAN_TXBRP_TRP21_Pos) +#define CAN_TXBRP_TRP22_Pos 22 /**< \brief (CAN_TXBRP) Transmission Request Pending 22 */ +#define CAN_TXBRP_TRP22 (_U_(0x1) << CAN_TXBRP_TRP22_Pos) +#define CAN_TXBRP_TRP23_Pos 23 /**< \brief (CAN_TXBRP) Transmission Request Pending 23 */ +#define CAN_TXBRP_TRP23 (_U_(0x1) << CAN_TXBRP_TRP23_Pos) +#define CAN_TXBRP_TRP24_Pos 24 /**< \brief (CAN_TXBRP) Transmission Request Pending 24 */ +#define CAN_TXBRP_TRP24 (_U_(0x1) << CAN_TXBRP_TRP24_Pos) +#define CAN_TXBRP_TRP25_Pos 25 /**< \brief (CAN_TXBRP) Transmission Request Pending 25 */ +#define CAN_TXBRP_TRP25 (_U_(0x1) << CAN_TXBRP_TRP25_Pos) +#define CAN_TXBRP_TRP26_Pos 26 /**< \brief (CAN_TXBRP) Transmission Request Pending 26 */ +#define CAN_TXBRP_TRP26 (_U_(0x1) << CAN_TXBRP_TRP26_Pos) +#define CAN_TXBRP_TRP27_Pos 27 /**< \brief (CAN_TXBRP) Transmission Request Pending 27 */ +#define CAN_TXBRP_TRP27 (_U_(0x1) << CAN_TXBRP_TRP27_Pos) +#define CAN_TXBRP_TRP28_Pos 28 /**< \brief (CAN_TXBRP) Transmission Request Pending 28 */ +#define CAN_TXBRP_TRP28 (_U_(0x1) << CAN_TXBRP_TRP28_Pos) +#define CAN_TXBRP_TRP29_Pos 29 /**< \brief (CAN_TXBRP) Transmission Request Pending 29 */ +#define CAN_TXBRP_TRP29 (_U_(0x1) << CAN_TXBRP_TRP29_Pos) +#define CAN_TXBRP_TRP30_Pos 30 /**< \brief (CAN_TXBRP) Transmission Request Pending 30 */ +#define CAN_TXBRP_TRP30 (_U_(0x1) << CAN_TXBRP_TRP30_Pos) +#define CAN_TXBRP_TRP31_Pos 31 /**< \brief (CAN_TXBRP) Transmission Request Pending 31 */ +#define CAN_TXBRP_TRP31 (_U_(0x1) << CAN_TXBRP_TRP31_Pos) +#define CAN_TXBRP_MASK _U_(0xFFFFFFFF) /**< \brief (CAN_TXBRP) MASK Register */ + +/* -------- CAN_TXBAR : (CAN Offset: 0xD0) (R/W 32) Tx Buffer Add Request -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t AR0:1; /*!< bit: 0 Add Request 0 */ + uint32_t AR1:1; /*!< bit: 1 Add Request 1 */ + uint32_t AR2:1; /*!< bit: 2 Add Request 2 */ + uint32_t AR3:1; /*!< bit: 3 Add Request 3 */ + uint32_t AR4:1; /*!< bit: 4 Add Request 4 */ + uint32_t AR5:1; /*!< bit: 5 Add Request 5 */ + uint32_t AR6:1; /*!< bit: 6 Add Request 6 */ + uint32_t AR7:1; /*!< bit: 7 Add Request 7 */ + uint32_t AR8:1; /*!< bit: 8 Add Request 8 */ + uint32_t AR9:1; /*!< bit: 9 Add Request 9 */ + uint32_t AR10:1; /*!< bit: 10 Add Request 10 */ + uint32_t AR11:1; /*!< bit: 11 Add Request 11 */ + uint32_t AR12:1; /*!< bit: 12 Add Request 12 */ + uint32_t AR13:1; /*!< bit: 13 Add Request 13 */ + uint32_t AR14:1; /*!< bit: 14 Add Request 14 */ + uint32_t AR15:1; /*!< bit: 15 Add Request 15 */ + uint32_t AR16:1; /*!< bit: 16 Add Request 16 */ + uint32_t AR17:1; /*!< bit: 17 Add Request 17 */ + uint32_t AR18:1; /*!< bit: 18 Add Request 18 */ + uint32_t AR19:1; /*!< bit: 19 Add Request 19 */ + uint32_t AR20:1; /*!< bit: 20 Add Request 20 */ + uint32_t AR21:1; /*!< bit: 21 Add Request 21 */ + uint32_t AR22:1; /*!< bit: 22 Add Request 22 */ + uint32_t AR23:1; /*!< bit: 23 Add Request 23 */ + uint32_t AR24:1; /*!< bit: 24 Add Request 24 */ + uint32_t AR25:1; /*!< bit: 25 Add Request 25 */ + uint32_t AR26:1; /*!< bit: 26 Add Request 26 */ + uint32_t AR27:1; /*!< bit: 27 Add Request 27 */ + uint32_t AR28:1; /*!< bit: 28 Add Request 28 */ + uint32_t AR29:1; /*!< bit: 29 Add Request 29 */ + uint32_t AR30:1; /*!< bit: 30 Add Request 30 */ + uint32_t AR31:1; /*!< bit: 31 Add Request 31 */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_TXBAR_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_TXBAR_OFFSET 0xD0 /**< \brief (CAN_TXBAR offset) Tx Buffer Add Request */ +#define CAN_TXBAR_RESETVALUE _U_(0x00000000) /**< \brief (CAN_TXBAR reset_value) Tx Buffer Add Request */ + +#define CAN_TXBAR_AR0_Pos 0 /**< \brief (CAN_TXBAR) Add Request 0 */ +#define CAN_TXBAR_AR0 (_U_(0x1) << CAN_TXBAR_AR0_Pos) +#define CAN_TXBAR_AR1_Pos 1 /**< \brief (CAN_TXBAR) Add Request 1 */ +#define CAN_TXBAR_AR1 (_U_(0x1) << CAN_TXBAR_AR1_Pos) +#define CAN_TXBAR_AR2_Pos 2 /**< \brief (CAN_TXBAR) Add Request 2 */ +#define CAN_TXBAR_AR2 (_U_(0x1) << CAN_TXBAR_AR2_Pos) +#define CAN_TXBAR_AR3_Pos 3 /**< \brief (CAN_TXBAR) Add Request 3 */ +#define CAN_TXBAR_AR3 (_U_(0x1) << CAN_TXBAR_AR3_Pos) +#define CAN_TXBAR_AR4_Pos 4 /**< \brief (CAN_TXBAR) Add Request 4 */ +#define CAN_TXBAR_AR4 (_U_(0x1) << CAN_TXBAR_AR4_Pos) +#define CAN_TXBAR_AR5_Pos 5 /**< \brief (CAN_TXBAR) Add Request 5 */ +#define CAN_TXBAR_AR5 (_U_(0x1) << CAN_TXBAR_AR5_Pos) +#define CAN_TXBAR_AR6_Pos 6 /**< \brief (CAN_TXBAR) Add Request 6 */ +#define CAN_TXBAR_AR6 (_U_(0x1) << CAN_TXBAR_AR6_Pos) +#define CAN_TXBAR_AR7_Pos 7 /**< \brief (CAN_TXBAR) Add Request 7 */ +#define CAN_TXBAR_AR7 (_U_(0x1) << CAN_TXBAR_AR7_Pos) +#define CAN_TXBAR_AR8_Pos 8 /**< \brief (CAN_TXBAR) Add Request 8 */ +#define CAN_TXBAR_AR8 (_U_(0x1) << CAN_TXBAR_AR8_Pos) +#define CAN_TXBAR_AR9_Pos 9 /**< \brief (CAN_TXBAR) Add Request 9 */ +#define CAN_TXBAR_AR9 (_U_(0x1) << CAN_TXBAR_AR9_Pos) +#define CAN_TXBAR_AR10_Pos 10 /**< \brief (CAN_TXBAR) Add Request 10 */ +#define CAN_TXBAR_AR10 (_U_(0x1) << CAN_TXBAR_AR10_Pos) +#define CAN_TXBAR_AR11_Pos 11 /**< \brief (CAN_TXBAR) Add Request 11 */ +#define CAN_TXBAR_AR11 (_U_(0x1) << CAN_TXBAR_AR11_Pos) +#define CAN_TXBAR_AR12_Pos 12 /**< \brief (CAN_TXBAR) Add Request 12 */ +#define CAN_TXBAR_AR12 (_U_(0x1) << CAN_TXBAR_AR12_Pos) +#define CAN_TXBAR_AR13_Pos 13 /**< \brief (CAN_TXBAR) Add Request 13 */ +#define CAN_TXBAR_AR13 (_U_(0x1) << CAN_TXBAR_AR13_Pos) +#define CAN_TXBAR_AR14_Pos 14 /**< \brief (CAN_TXBAR) Add Request 14 */ +#define CAN_TXBAR_AR14 (_U_(0x1) << CAN_TXBAR_AR14_Pos) +#define CAN_TXBAR_AR15_Pos 15 /**< \brief (CAN_TXBAR) Add Request 15 */ +#define CAN_TXBAR_AR15 (_U_(0x1) << CAN_TXBAR_AR15_Pos) +#define CAN_TXBAR_AR16_Pos 16 /**< \brief (CAN_TXBAR) Add Request 16 */ +#define CAN_TXBAR_AR16 (_U_(0x1) << CAN_TXBAR_AR16_Pos) +#define CAN_TXBAR_AR17_Pos 17 /**< \brief (CAN_TXBAR) Add Request 17 */ +#define CAN_TXBAR_AR17 (_U_(0x1) << CAN_TXBAR_AR17_Pos) +#define CAN_TXBAR_AR18_Pos 18 /**< \brief (CAN_TXBAR) Add Request 18 */ +#define CAN_TXBAR_AR18 (_U_(0x1) << CAN_TXBAR_AR18_Pos) +#define CAN_TXBAR_AR19_Pos 19 /**< \brief (CAN_TXBAR) Add Request 19 */ +#define CAN_TXBAR_AR19 (_U_(0x1) << CAN_TXBAR_AR19_Pos) +#define CAN_TXBAR_AR20_Pos 20 /**< \brief (CAN_TXBAR) Add Request 20 */ +#define CAN_TXBAR_AR20 (_U_(0x1) << CAN_TXBAR_AR20_Pos) +#define CAN_TXBAR_AR21_Pos 21 /**< \brief (CAN_TXBAR) Add Request 21 */ +#define CAN_TXBAR_AR21 (_U_(0x1) << CAN_TXBAR_AR21_Pos) +#define CAN_TXBAR_AR22_Pos 22 /**< \brief (CAN_TXBAR) Add Request 22 */ +#define CAN_TXBAR_AR22 (_U_(0x1) << CAN_TXBAR_AR22_Pos) +#define CAN_TXBAR_AR23_Pos 23 /**< \brief (CAN_TXBAR) Add Request 23 */ +#define CAN_TXBAR_AR23 (_U_(0x1) << CAN_TXBAR_AR23_Pos) +#define CAN_TXBAR_AR24_Pos 24 /**< \brief (CAN_TXBAR) Add Request 24 */ +#define CAN_TXBAR_AR24 (_U_(0x1) << CAN_TXBAR_AR24_Pos) +#define CAN_TXBAR_AR25_Pos 25 /**< \brief (CAN_TXBAR) Add Request 25 */ +#define CAN_TXBAR_AR25 (_U_(0x1) << CAN_TXBAR_AR25_Pos) +#define CAN_TXBAR_AR26_Pos 26 /**< \brief (CAN_TXBAR) Add Request 26 */ +#define CAN_TXBAR_AR26 (_U_(0x1) << CAN_TXBAR_AR26_Pos) +#define CAN_TXBAR_AR27_Pos 27 /**< \brief (CAN_TXBAR) Add Request 27 */ +#define CAN_TXBAR_AR27 (_U_(0x1) << CAN_TXBAR_AR27_Pos) +#define CAN_TXBAR_AR28_Pos 28 /**< \brief (CAN_TXBAR) Add Request 28 */ +#define CAN_TXBAR_AR28 (_U_(0x1) << CAN_TXBAR_AR28_Pos) +#define CAN_TXBAR_AR29_Pos 29 /**< \brief (CAN_TXBAR) Add Request 29 */ +#define CAN_TXBAR_AR29 (_U_(0x1) << CAN_TXBAR_AR29_Pos) +#define CAN_TXBAR_AR30_Pos 30 /**< \brief (CAN_TXBAR) Add Request 30 */ +#define CAN_TXBAR_AR30 (_U_(0x1) << CAN_TXBAR_AR30_Pos) +#define CAN_TXBAR_AR31_Pos 31 /**< \brief (CAN_TXBAR) Add Request 31 */ +#define CAN_TXBAR_AR31 (_U_(0x1) << CAN_TXBAR_AR31_Pos) +#define CAN_TXBAR_MASK _U_(0xFFFFFFFF) /**< \brief (CAN_TXBAR) MASK Register */ + +/* -------- CAN_TXBCR : (CAN Offset: 0xD4) (R/W 32) Tx Buffer Cancellation Request -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t CR0:1; /*!< bit: 0 Cancellation Request 0 */ + uint32_t CR1:1; /*!< bit: 1 Cancellation Request 1 */ + uint32_t CR2:1; /*!< bit: 2 Cancellation Request 2 */ + uint32_t CR3:1; /*!< bit: 3 Cancellation Request 3 */ + uint32_t CR4:1; /*!< bit: 4 Cancellation Request 4 */ + uint32_t CR5:1; /*!< bit: 5 Cancellation Request 5 */ + uint32_t CR6:1; /*!< bit: 6 Cancellation Request 6 */ + uint32_t CR7:1; /*!< bit: 7 Cancellation Request 7 */ + uint32_t CR8:1; /*!< bit: 8 Cancellation Request 8 */ + uint32_t CR9:1; /*!< bit: 9 Cancellation Request 9 */ + uint32_t CR10:1; /*!< bit: 10 Cancellation Request 10 */ + uint32_t CR11:1; /*!< bit: 11 Cancellation Request 11 */ + uint32_t CR12:1; /*!< bit: 12 Cancellation Request 12 */ + uint32_t CR13:1; /*!< bit: 13 Cancellation Request 13 */ + uint32_t CR14:1; /*!< bit: 14 Cancellation Request 14 */ + uint32_t CR15:1; /*!< bit: 15 Cancellation Request 15 */ + uint32_t CR16:1; /*!< bit: 16 Cancellation Request 16 */ + uint32_t CR17:1; /*!< bit: 17 Cancellation Request 17 */ + uint32_t CR18:1; /*!< bit: 18 Cancellation Request 18 */ + uint32_t CR19:1; /*!< bit: 19 Cancellation Request 19 */ + uint32_t CR20:1; /*!< bit: 20 Cancellation Request 20 */ + uint32_t CR21:1; /*!< bit: 21 Cancellation Request 21 */ + uint32_t CR22:1; /*!< bit: 22 Cancellation Request 22 */ + uint32_t CR23:1; /*!< bit: 23 Cancellation Request 23 */ + uint32_t CR24:1; /*!< bit: 24 Cancellation Request 24 */ + uint32_t CR25:1; /*!< bit: 25 Cancellation Request 25 */ + uint32_t CR26:1; /*!< bit: 26 Cancellation Request 26 */ + uint32_t CR27:1; /*!< bit: 27 Cancellation Request 27 */ + uint32_t CR28:1; /*!< bit: 28 Cancellation Request 28 */ + uint32_t CR29:1; /*!< bit: 29 Cancellation Request 29 */ + uint32_t CR30:1; /*!< bit: 30 Cancellation Request 30 */ + uint32_t CR31:1; /*!< bit: 31 Cancellation Request 31 */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_TXBCR_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_TXBCR_OFFSET 0xD4 /**< \brief (CAN_TXBCR offset) Tx Buffer Cancellation Request */ +#define CAN_TXBCR_RESETVALUE _U_(0x00000000) /**< \brief (CAN_TXBCR reset_value) Tx Buffer Cancellation Request */ + +#define CAN_TXBCR_CR0_Pos 0 /**< \brief (CAN_TXBCR) Cancellation Request 0 */ +#define CAN_TXBCR_CR0 (_U_(0x1) << CAN_TXBCR_CR0_Pos) +#define CAN_TXBCR_CR1_Pos 1 /**< \brief (CAN_TXBCR) Cancellation Request 1 */ +#define CAN_TXBCR_CR1 (_U_(0x1) << CAN_TXBCR_CR1_Pos) +#define CAN_TXBCR_CR2_Pos 2 /**< \brief (CAN_TXBCR) Cancellation Request 2 */ +#define CAN_TXBCR_CR2 (_U_(0x1) << CAN_TXBCR_CR2_Pos) +#define CAN_TXBCR_CR3_Pos 3 /**< \brief (CAN_TXBCR) Cancellation Request 3 */ +#define CAN_TXBCR_CR3 (_U_(0x1) << CAN_TXBCR_CR3_Pos) +#define CAN_TXBCR_CR4_Pos 4 /**< \brief (CAN_TXBCR) Cancellation Request 4 */ +#define CAN_TXBCR_CR4 (_U_(0x1) << CAN_TXBCR_CR4_Pos) +#define CAN_TXBCR_CR5_Pos 5 /**< \brief (CAN_TXBCR) Cancellation Request 5 */ +#define CAN_TXBCR_CR5 (_U_(0x1) << CAN_TXBCR_CR5_Pos) +#define CAN_TXBCR_CR6_Pos 6 /**< \brief (CAN_TXBCR) Cancellation Request 6 */ +#define CAN_TXBCR_CR6 (_U_(0x1) << CAN_TXBCR_CR6_Pos) +#define CAN_TXBCR_CR7_Pos 7 /**< \brief (CAN_TXBCR) Cancellation Request 7 */ +#define CAN_TXBCR_CR7 (_U_(0x1) << CAN_TXBCR_CR7_Pos) +#define CAN_TXBCR_CR8_Pos 8 /**< \brief (CAN_TXBCR) Cancellation Request 8 */ +#define CAN_TXBCR_CR8 (_U_(0x1) << CAN_TXBCR_CR8_Pos) +#define CAN_TXBCR_CR9_Pos 9 /**< \brief (CAN_TXBCR) Cancellation Request 9 */ +#define CAN_TXBCR_CR9 (_U_(0x1) << CAN_TXBCR_CR9_Pos) +#define CAN_TXBCR_CR10_Pos 10 /**< \brief (CAN_TXBCR) Cancellation Request 10 */ +#define CAN_TXBCR_CR10 (_U_(0x1) << CAN_TXBCR_CR10_Pos) +#define CAN_TXBCR_CR11_Pos 11 /**< \brief (CAN_TXBCR) Cancellation Request 11 */ +#define CAN_TXBCR_CR11 (_U_(0x1) << CAN_TXBCR_CR11_Pos) +#define CAN_TXBCR_CR12_Pos 12 /**< \brief (CAN_TXBCR) Cancellation Request 12 */ +#define CAN_TXBCR_CR12 (_U_(0x1) << CAN_TXBCR_CR12_Pos) +#define CAN_TXBCR_CR13_Pos 13 /**< \brief (CAN_TXBCR) Cancellation Request 13 */ +#define CAN_TXBCR_CR13 (_U_(0x1) << CAN_TXBCR_CR13_Pos) +#define CAN_TXBCR_CR14_Pos 14 /**< \brief (CAN_TXBCR) Cancellation Request 14 */ +#define CAN_TXBCR_CR14 (_U_(0x1) << CAN_TXBCR_CR14_Pos) +#define CAN_TXBCR_CR15_Pos 15 /**< \brief (CAN_TXBCR) Cancellation Request 15 */ +#define CAN_TXBCR_CR15 (_U_(0x1) << CAN_TXBCR_CR15_Pos) +#define CAN_TXBCR_CR16_Pos 16 /**< \brief (CAN_TXBCR) Cancellation Request 16 */ +#define CAN_TXBCR_CR16 (_U_(0x1) << CAN_TXBCR_CR16_Pos) +#define CAN_TXBCR_CR17_Pos 17 /**< \brief (CAN_TXBCR) Cancellation Request 17 */ +#define CAN_TXBCR_CR17 (_U_(0x1) << CAN_TXBCR_CR17_Pos) +#define CAN_TXBCR_CR18_Pos 18 /**< \brief (CAN_TXBCR) Cancellation Request 18 */ +#define CAN_TXBCR_CR18 (_U_(0x1) << CAN_TXBCR_CR18_Pos) +#define CAN_TXBCR_CR19_Pos 19 /**< \brief (CAN_TXBCR) Cancellation Request 19 */ +#define CAN_TXBCR_CR19 (_U_(0x1) << CAN_TXBCR_CR19_Pos) +#define CAN_TXBCR_CR20_Pos 20 /**< \brief (CAN_TXBCR) Cancellation Request 20 */ +#define CAN_TXBCR_CR20 (_U_(0x1) << CAN_TXBCR_CR20_Pos) +#define CAN_TXBCR_CR21_Pos 21 /**< \brief (CAN_TXBCR) Cancellation Request 21 */ +#define CAN_TXBCR_CR21 (_U_(0x1) << CAN_TXBCR_CR21_Pos) +#define CAN_TXBCR_CR22_Pos 22 /**< \brief (CAN_TXBCR) Cancellation Request 22 */ +#define CAN_TXBCR_CR22 (_U_(0x1) << CAN_TXBCR_CR22_Pos) +#define CAN_TXBCR_CR23_Pos 23 /**< \brief (CAN_TXBCR) Cancellation Request 23 */ +#define CAN_TXBCR_CR23 (_U_(0x1) << CAN_TXBCR_CR23_Pos) +#define CAN_TXBCR_CR24_Pos 24 /**< \brief (CAN_TXBCR) Cancellation Request 24 */ +#define CAN_TXBCR_CR24 (_U_(0x1) << CAN_TXBCR_CR24_Pos) +#define CAN_TXBCR_CR25_Pos 25 /**< \brief (CAN_TXBCR) Cancellation Request 25 */ +#define CAN_TXBCR_CR25 (_U_(0x1) << CAN_TXBCR_CR25_Pos) +#define CAN_TXBCR_CR26_Pos 26 /**< \brief (CAN_TXBCR) Cancellation Request 26 */ +#define CAN_TXBCR_CR26 (_U_(0x1) << CAN_TXBCR_CR26_Pos) +#define CAN_TXBCR_CR27_Pos 27 /**< \brief (CAN_TXBCR) Cancellation Request 27 */ +#define CAN_TXBCR_CR27 (_U_(0x1) << CAN_TXBCR_CR27_Pos) +#define CAN_TXBCR_CR28_Pos 28 /**< \brief (CAN_TXBCR) Cancellation Request 28 */ +#define CAN_TXBCR_CR28 (_U_(0x1) << CAN_TXBCR_CR28_Pos) +#define CAN_TXBCR_CR29_Pos 29 /**< \brief (CAN_TXBCR) Cancellation Request 29 */ +#define CAN_TXBCR_CR29 (_U_(0x1) << CAN_TXBCR_CR29_Pos) +#define CAN_TXBCR_CR30_Pos 30 /**< \brief (CAN_TXBCR) Cancellation Request 30 */ +#define CAN_TXBCR_CR30 (_U_(0x1) << CAN_TXBCR_CR30_Pos) +#define CAN_TXBCR_CR31_Pos 31 /**< \brief (CAN_TXBCR) Cancellation Request 31 */ +#define CAN_TXBCR_CR31 (_U_(0x1) << CAN_TXBCR_CR31_Pos) +#define CAN_TXBCR_MASK _U_(0xFFFFFFFF) /**< \brief (CAN_TXBCR) MASK Register */ + +/* -------- CAN_TXBTO : (CAN Offset: 0xD8) (R/ 32) Tx Buffer Transmission Occurred -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t TO0:1; /*!< bit: 0 Transmission Occurred 0 */ + uint32_t TO1:1; /*!< bit: 1 Transmission Occurred 1 */ + uint32_t TO2:1; /*!< bit: 2 Transmission Occurred 2 */ + uint32_t TO3:1; /*!< bit: 3 Transmission Occurred 3 */ + uint32_t TO4:1; /*!< bit: 4 Transmission Occurred 4 */ + uint32_t TO5:1; /*!< bit: 5 Transmission Occurred 5 */ + uint32_t TO6:1; /*!< bit: 6 Transmission Occurred 6 */ + uint32_t TO7:1; /*!< bit: 7 Transmission Occurred 7 */ + uint32_t TO8:1; /*!< bit: 8 Transmission Occurred 8 */ + uint32_t TO9:1; /*!< bit: 9 Transmission Occurred 9 */ + uint32_t TO10:1; /*!< bit: 10 Transmission Occurred 10 */ + uint32_t TO11:1; /*!< bit: 11 Transmission Occurred 11 */ + uint32_t TO12:1; /*!< bit: 12 Transmission Occurred 12 */ + uint32_t TO13:1; /*!< bit: 13 Transmission Occurred 13 */ + uint32_t TO14:1; /*!< bit: 14 Transmission Occurred 14 */ + uint32_t TO15:1; /*!< bit: 15 Transmission Occurred 15 */ + uint32_t TO16:1; /*!< bit: 16 Transmission Occurred 16 */ + uint32_t TO17:1; /*!< bit: 17 Transmission Occurred 17 */ + uint32_t TO18:1; /*!< bit: 18 Transmission Occurred 18 */ + uint32_t TO19:1; /*!< bit: 19 Transmission Occurred 19 */ + uint32_t TO20:1; /*!< bit: 20 Transmission Occurred 20 */ + uint32_t TO21:1; /*!< bit: 21 Transmission Occurred 21 */ + uint32_t TO22:1; /*!< bit: 22 Transmission Occurred 22 */ + uint32_t TO23:1; /*!< bit: 23 Transmission Occurred 23 */ + uint32_t TO24:1; /*!< bit: 24 Transmission Occurred 24 */ + uint32_t TO25:1; /*!< bit: 25 Transmission Occurred 25 */ + uint32_t TO26:1; /*!< bit: 26 Transmission Occurred 26 */ + uint32_t TO27:1; /*!< bit: 27 Transmission Occurred 27 */ + uint32_t TO28:1; /*!< bit: 28 Transmission Occurred 28 */ + uint32_t TO29:1; /*!< bit: 29 Transmission Occurred 29 */ + uint32_t TO30:1; /*!< bit: 30 Transmission Occurred 30 */ + uint32_t TO31:1; /*!< bit: 31 Transmission Occurred 31 */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_TXBTO_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_TXBTO_OFFSET 0xD8 /**< \brief (CAN_TXBTO offset) Tx Buffer Transmission Occurred */ +#define CAN_TXBTO_RESETVALUE _U_(0x00000000) /**< \brief (CAN_TXBTO reset_value) Tx Buffer Transmission Occurred */ + +#define CAN_TXBTO_TO0_Pos 0 /**< \brief (CAN_TXBTO) Transmission Occurred 0 */ +#define CAN_TXBTO_TO0 (_U_(0x1) << CAN_TXBTO_TO0_Pos) +#define CAN_TXBTO_TO1_Pos 1 /**< \brief (CAN_TXBTO) Transmission Occurred 1 */ +#define CAN_TXBTO_TO1 (_U_(0x1) << CAN_TXBTO_TO1_Pos) +#define CAN_TXBTO_TO2_Pos 2 /**< \brief (CAN_TXBTO) Transmission Occurred 2 */ +#define CAN_TXBTO_TO2 (_U_(0x1) << CAN_TXBTO_TO2_Pos) +#define CAN_TXBTO_TO3_Pos 3 /**< \brief (CAN_TXBTO) Transmission Occurred 3 */ +#define CAN_TXBTO_TO3 (_U_(0x1) << CAN_TXBTO_TO3_Pos) +#define CAN_TXBTO_TO4_Pos 4 /**< \brief (CAN_TXBTO) Transmission Occurred 4 */ +#define CAN_TXBTO_TO4 (_U_(0x1) << CAN_TXBTO_TO4_Pos) +#define CAN_TXBTO_TO5_Pos 5 /**< \brief (CAN_TXBTO) Transmission Occurred 5 */ +#define CAN_TXBTO_TO5 (_U_(0x1) << CAN_TXBTO_TO5_Pos) +#define CAN_TXBTO_TO6_Pos 6 /**< \brief (CAN_TXBTO) Transmission Occurred 6 */ +#define CAN_TXBTO_TO6 (_U_(0x1) << CAN_TXBTO_TO6_Pos) +#define CAN_TXBTO_TO7_Pos 7 /**< \brief (CAN_TXBTO) Transmission Occurred 7 */ +#define CAN_TXBTO_TO7 (_U_(0x1) << CAN_TXBTO_TO7_Pos) +#define CAN_TXBTO_TO8_Pos 8 /**< \brief (CAN_TXBTO) Transmission Occurred 8 */ +#define CAN_TXBTO_TO8 (_U_(0x1) << CAN_TXBTO_TO8_Pos) +#define CAN_TXBTO_TO9_Pos 9 /**< \brief (CAN_TXBTO) Transmission Occurred 9 */ +#define CAN_TXBTO_TO9 (_U_(0x1) << CAN_TXBTO_TO9_Pos) +#define CAN_TXBTO_TO10_Pos 10 /**< \brief (CAN_TXBTO) Transmission Occurred 10 */ +#define CAN_TXBTO_TO10 (_U_(0x1) << CAN_TXBTO_TO10_Pos) +#define CAN_TXBTO_TO11_Pos 11 /**< \brief (CAN_TXBTO) Transmission Occurred 11 */ +#define CAN_TXBTO_TO11 (_U_(0x1) << CAN_TXBTO_TO11_Pos) +#define CAN_TXBTO_TO12_Pos 12 /**< \brief (CAN_TXBTO) Transmission Occurred 12 */ +#define CAN_TXBTO_TO12 (_U_(0x1) << CAN_TXBTO_TO12_Pos) +#define CAN_TXBTO_TO13_Pos 13 /**< \brief (CAN_TXBTO) Transmission Occurred 13 */ +#define CAN_TXBTO_TO13 (_U_(0x1) << CAN_TXBTO_TO13_Pos) +#define CAN_TXBTO_TO14_Pos 14 /**< \brief (CAN_TXBTO) Transmission Occurred 14 */ +#define CAN_TXBTO_TO14 (_U_(0x1) << CAN_TXBTO_TO14_Pos) +#define CAN_TXBTO_TO15_Pos 15 /**< \brief (CAN_TXBTO) Transmission Occurred 15 */ +#define CAN_TXBTO_TO15 (_U_(0x1) << CAN_TXBTO_TO15_Pos) +#define CAN_TXBTO_TO16_Pos 16 /**< \brief (CAN_TXBTO) Transmission Occurred 16 */ +#define CAN_TXBTO_TO16 (_U_(0x1) << CAN_TXBTO_TO16_Pos) +#define CAN_TXBTO_TO17_Pos 17 /**< \brief (CAN_TXBTO) Transmission Occurred 17 */ +#define CAN_TXBTO_TO17 (_U_(0x1) << CAN_TXBTO_TO17_Pos) +#define CAN_TXBTO_TO18_Pos 18 /**< \brief (CAN_TXBTO) Transmission Occurred 18 */ +#define CAN_TXBTO_TO18 (_U_(0x1) << CAN_TXBTO_TO18_Pos) +#define CAN_TXBTO_TO19_Pos 19 /**< \brief (CAN_TXBTO) Transmission Occurred 19 */ +#define CAN_TXBTO_TO19 (_U_(0x1) << CAN_TXBTO_TO19_Pos) +#define CAN_TXBTO_TO20_Pos 20 /**< \brief (CAN_TXBTO) Transmission Occurred 20 */ +#define CAN_TXBTO_TO20 (_U_(0x1) << CAN_TXBTO_TO20_Pos) +#define CAN_TXBTO_TO21_Pos 21 /**< \brief (CAN_TXBTO) Transmission Occurred 21 */ +#define CAN_TXBTO_TO21 (_U_(0x1) << CAN_TXBTO_TO21_Pos) +#define CAN_TXBTO_TO22_Pos 22 /**< \brief (CAN_TXBTO) Transmission Occurred 22 */ +#define CAN_TXBTO_TO22 (_U_(0x1) << CAN_TXBTO_TO22_Pos) +#define CAN_TXBTO_TO23_Pos 23 /**< \brief (CAN_TXBTO) Transmission Occurred 23 */ +#define CAN_TXBTO_TO23 (_U_(0x1) << CAN_TXBTO_TO23_Pos) +#define CAN_TXBTO_TO24_Pos 24 /**< \brief (CAN_TXBTO) Transmission Occurred 24 */ +#define CAN_TXBTO_TO24 (_U_(0x1) << CAN_TXBTO_TO24_Pos) +#define CAN_TXBTO_TO25_Pos 25 /**< \brief (CAN_TXBTO) Transmission Occurred 25 */ +#define CAN_TXBTO_TO25 (_U_(0x1) << CAN_TXBTO_TO25_Pos) +#define CAN_TXBTO_TO26_Pos 26 /**< \brief (CAN_TXBTO) Transmission Occurred 26 */ +#define CAN_TXBTO_TO26 (_U_(0x1) << CAN_TXBTO_TO26_Pos) +#define CAN_TXBTO_TO27_Pos 27 /**< \brief (CAN_TXBTO) Transmission Occurred 27 */ +#define CAN_TXBTO_TO27 (_U_(0x1) << CAN_TXBTO_TO27_Pos) +#define CAN_TXBTO_TO28_Pos 28 /**< \brief (CAN_TXBTO) Transmission Occurred 28 */ +#define CAN_TXBTO_TO28 (_U_(0x1) << CAN_TXBTO_TO28_Pos) +#define CAN_TXBTO_TO29_Pos 29 /**< \brief (CAN_TXBTO) Transmission Occurred 29 */ +#define CAN_TXBTO_TO29 (_U_(0x1) << CAN_TXBTO_TO29_Pos) +#define CAN_TXBTO_TO30_Pos 30 /**< \brief (CAN_TXBTO) Transmission Occurred 30 */ +#define CAN_TXBTO_TO30 (_U_(0x1) << CAN_TXBTO_TO30_Pos) +#define CAN_TXBTO_TO31_Pos 31 /**< \brief (CAN_TXBTO) Transmission Occurred 31 */ +#define CAN_TXBTO_TO31 (_U_(0x1) << CAN_TXBTO_TO31_Pos) +#define CAN_TXBTO_MASK _U_(0xFFFFFFFF) /**< \brief (CAN_TXBTO) MASK Register */ + +/* -------- CAN_TXBCF : (CAN Offset: 0xDC) (R/ 32) Tx Buffer Cancellation Finished -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t CF0:1; /*!< bit: 0 Tx Buffer Cancellation Finished 0 */ + uint32_t CF1:1; /*!< bit: 1 Tx Buffer Cancellation Finished 1 */ + uint32_t CF2:1; /*!< bit: 2 Tx Buffer Cancellation Finished 2 */ + uint32_t CF3:1; /*!< bit: 3 Tx Buffer Cancellation Finished 3 */ + uint32_t CF4:1; /*!< bit: 4 Tx Buffer Cancellation Finished 4 */ + uint32_t CF5:1; /*!< bit: 5 Tx Buffer Cancellation Finished 5 */ + uint32_t CF6:1; /*!< bit: 6 Tx Buffer Cancellation Finished 6 */ + uint32_t CF7:1; /*!< bit: 7 Tx Buffer Cancellation Finished 7 */ + uint32_t CF8:1; /*!< bit: 8 Tx Buffer Cancellation Finished 8 */ + uint32_t CF9:1; /*!< bit: 9 Tx Buffer Cancellation Finished 9 */ + uint32_t CF10:1; /*!< bit: 10 Tx Buffer Cancellation Finished 10 */ + uint32_t CF11:1; /*!< bit: 11 Tx Buffer Cancellation Finished 11 */ + uint32_t CF12:1; /*!< bit: 12 Tx Buffer Cancellation Finished 12 */ + uint32_t CF13:1; /*!< bit: 13 Tx Buffer Cancellation Finished 13 */ + uint32_t CF14:1; /*!< bit: 14 Tx Buffer Cancellation Finished 14 */ + uint32_t CF15:1; /*!< bit: 15 Tx Buffer Cancellation Finished 15 */ + uint32_t CF16:1; /*!< bit: 16 Tx Buffer Cancellation Finished 16 */ + uint32_t CF17:1; /*!< bit: 17 Tx Buffer Cancellation Finished 17 */ + uint32_t CF18:1; /*!< bit: 18 Tx Buffer Cancellation Finished 18 */ + uint32_t CF19:1; /*!< bit: 19 Tx Buffer Cancellation Finished 19 */ + uint32_t CF20:1; /*!< bit: 20 Tx Buffer Cancellation Finished 20 */ + uint32_t CF21:1; /*!< bit: 21 Tx Buffer Cancellation Finished 21 */ + uint32_t CF22:1; /*!< bit: 22 Tx Buffer Cancellation Finished 22 */ + uint32_t CF23:1; /*!< bit: 23 Tx Buffer Cancellation Finished 23 */ + uint32_t CF24:1; /*!< bit: 24 Tx Buffer Cancellation Finished 24 */ + uint32_t CF25:1; /*!< bit: 25 Tx Buffer Cancellation Finished 25 */ + uint32_t CF26:1; /*!< bit: 26 Tx Buffer Cancellation Finished 26 */ + uint32_t CF27:1; /*!< bit: 27 Tx Buffer Cancellation Finished 27 */ + uint32_t CF28:1; /*!< bit: 28 Tx Buffer Cancellation Finished 28 */ + uint32_t CF29:1; /*!< bit: 29 Tx Buffer Cancellation Finished 29 */ + uint32_t CF30:1; /*!< bit: 30 Tx Buffer Cancellation Finished 30 */ + uint32_t CF31:1; /*!< bit: 31 Tx Buffer Cancellation Finished 31 */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_TXBCF_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_TXBCF_OFFSET 0xDC /**< \brief (CAN_TXBCF offset) Tx Buffer Cancellation Finished */ +#define CAN_TXBCF_RESETVALUE _U_(0x00000000) /**< \brief (CAN_TXBCF reset_value) Tx Buffer Cancellation Finished */ + +#define CAN_TXBCF_CF0_Pos 0 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 0 */ +#define CAN_TXBCF_CF0 (_U_(0x1) << CAN_TXBCF_CF0_Pos) +#define CAN_TXBCF_CF1_Pos 1 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 1 */ +#define CAN_TXBCF_CF1 (_U_(0x1) << CAN_TXBCF_CF1_Pos) +#define CAN_TXBCF_CF2_Pos 2 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 2 */ +#define CAN_TXBCF_CF2 (_U_(0x1) << CAN_TXBCF_CF2_Pos) +#define CAN_TXBCF_CF3_Pos 3 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 3 */ +#define CAN_TXBCF_CF3 (_U_(0x1) << CAN_TXBCF_CF3_Pos) +#define CAN_TXBCF_CF4_Pos 4 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 4 */ +#define CAN_TXBCF_CF4 (_U_(0x1) << CAN_TXBCF_CF4_Pos) +#define CAN_TXBCF_CF5_Pos 5 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 5 */ +#define CAN_TXBCF_CF5 (_U_(0x1) << CAN_TXBCF_CF5_Pos) +#define CAN_TXBCF_CF6_Pos 6 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 6 */ +#define CAN_TXBCF_CF6 (_U_(0x1) << CAN_TXBCF_CF6_Pos) +#define CAN_TXBCF_CF7_Pos 7 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 7 */ +#define CAN_TXBCF_CF7 (_U_(0x1) << CAN_TXBCF_CF7_Pos) +#define CAN_TXBCF_CF8_Pos 8 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 8 */ +#define CAN_TXBCF_CF8 (_U_(0x1) << CAN_TXBCF_CF8_Pos) +#define CAN_TXBCF_CF9_Pos 9 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 9 */ +#define CAN_TXBCF_CF9 (_U_(0x1) << CAN_TXBCF_CF9_Pos) +#define CAN_TXBCF_CF10_Pos 10 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 10 */ +#define CAN_TXBCF_CF10 (_U_(0x1) << CAN_TXBCF_CF10_Pos) +#define CAN_TXBCF_CF11_Pos 11 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 11 */ +#define CAN_TXBCF_CF11 (_U_(0x1) << CAN_TXBCF_CF11_Pos) +#define CAN_TXBCF_CF12_Pos 12 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 12 */ +#define CAN_TXBCF_CF12 (_U_(0x1) << CAN_TXBCF_CF12_Pos) +#define CAN_TXBCF_CF13_Pos 13 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 13 */ +#define CAN_TXBCF_CF13 (_U_(0x1) << CAN_TXBCF_CF13_Pos) +#define CAN_TXBCF_CF14_Pos 14 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 14 */ +#define CAN_TXBCF_CF14 (_U_(0x1) << CAN_TXBCF_CF14_Pos) +#define CAN_TXBCF_CF15_Pos 15 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 15 */ +#define CAN_TXBCF_CF15 (_U_(0x1) << CAN_TXBCF_CF15_Pos) +#define CAN_TXBCF_CF16_Pos 16 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 16 */ +#define CAN_TXBCF_CF16 (_U_(0x1) << CAN_TXBCF_CF16_Pos) +#define CAN_TXBCF_CF17_Pos 17 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 17 */ +#define CAN_TXBCF_CF17 (_U_(0x1) << CAN_TXBCF_CF17_Pos) +#define CAN_TXBCF_CF18_Pos 18 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 18 */ +#define CAN_TXBCF_CF18 (_U_(0x1) << CAN_TXBCF_CF18_Pos) +#define CAN_TXBCF_CF19_Pos 19 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 19 */ +#define CAN_TXBCF_CF19 (_U_(0x1) << CAN_TXBCF_CF19_Pos) +#define CAN_TXBCF_CF20_Pos 20 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 20 */ +#define CAN_TXBCF_CF20 (_U_(0x1) << CAN_TXBCF_CF20_Pos) +#define CAN_TXBCF_CF21_Pos 21 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 21 */ +#define CAN_TXBCF_CF21 (_U_(0x1) << CAN_TXBCF_CF21_Pos) +#define CAN_TXBCF_CF22_Pos 22 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 22 */ +#define CAN_TXBCF_CF22 (_U_(0x1) << CAN_TXBCF_CF22_Pos) +#define CAN_TXBCF_CF23_Pos 23 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 23 */ +#define CAN_TXBCF_CF23 (_U_(0x1) << CAN_TXBCF_CF23_Pos) +#define CAN_TXBCF_CF24_Pos 24 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 24 */ +#define CAN_TXBCF_CF24 (_U_(0x1) << CAN_TXBCF_CF24_Pos) +#define CAN_TXBCF_CF25_Pos 25 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 25 */ +#define CAN_TXBCF_CF25 (_U_(0x1) << CAN_TXBCF_CF25_Pos) +#define CAN_TXBCF_CF26_Pos 26 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 26 */ +#define CAN_TXBCF_CF26 (_U_(0x1) << CAN_TXBCF_CF26_Pos) +#define CAN_TXBCF_CF27_Pos 27 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 27 */ +#define CAN_TXBCF_CF27 (_U_(0x1) << CAN_TXBCF_CF27_Pos) +#define CAN_TXBCF_CF28_Pos 28 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 28 */ +#define CAN_TXBCF_CF28 (_U_(0x1) << CAN_TXBCF_CF28_Pos) +#define CAN_TXBCF_CF29_Pos 29 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 29 */ +#define CAN_TXBCF_CF29 (_U_(0x1) << CAN_TXBCF_CF29_Pos) +#define CAN_TXBCF_CF30_Pos 30 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 30 */ +#define CAN_TXBCF_CF30 (_U_(0x1) << CAN_TXBCF_CF30_Pos) +#define CAN_TXBCF_CF31_Pos 31 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 31 */ +#define CAN_TXBCF_CF31 (_U_(0x1) << CAN_TXBCF_CF31_Pos) +#define CAN_TXBCF_MASK _U_(0xFFFFFFFF) /**< \brief (CAN_TXBCF) MASK Register */ + +/* -------- CAN_TXBTIE : (CAN Offset: 0xE0) (R/W 32) Tx Buffer Transmission Interrupt Enable -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t TIE0:1; /*!< bit: 0 Transmission Interrupt Enable 0 */ + uint32_t TIE1:1; /*!< bit: 1 Transmission Interrupt Enable 1 */ + uint32_t TIE2:1; /*!< bit: 2 Transmission Interrupt Enable 2 */ + uint32_t TIE3:1; /*!< bit: 3 Transmission Interrupt Enable 3 */ + uint32_t TIE4:1; /*!< bit: 4 Transmission Interrupt Enable 4 */ + uint32_t TIE5:1; /*!< bit: 5 Transmission Interrupt Enable 5 */ + uint32_t TIE6:1; /*!< bit: 6 Transmission Interrupt Enable 6 */ + uint32_t TIE7:1; /*!< bit: 7 Transmission Interrupt Enable 7 */ + uint32_t TIE8:1; /*!< bit: 8 Transmission Interrupt Enable 8 */ + uint32_t TIE9:1; /*!< bit: 9 Transmission Interrupt Enable 9 */ + uint32_t TIE10:1; /*!< bit: 10 Transmission Interrupt Enable 10 */ + uint32_t TIE11:1; /*!< bit: 11 Transmission Interrupt Enable 11 */ + uint32_t TIE12:1; /*!< bit: 12 Transmission Interrupt Enable 12 */ + uint32_t TIE13:1; /*!< bit: 13 Transmission Interrupt Enable 13 */ + uint32_t TIE14:1; /*!< bit: 14 Transmission Interrupt Enable 14 */ + uint32_t TIE15:1; /*!< bit: 15 Transmission Interrupt Enable 15 */ + uint32_t TIE16:1; /*!< bit: 16 Transmission Interrupt Enable 16 */ + uint32_t TIE17:1; /*!< bit: 17 Transmission Interrupt Enable 17 */ + uint32_t TIE18:1; /*!< bit: 18 Transmission Interrupt Enable 18 */ + uint32_t TIE19:1; /*!< bit: 19 Transmission Interrupt Enable 19 */ + uint32_t TIE20:1; /*!< bit: 20 Transmission Interrupt Enable 20 */ + uint32_t TIE21:1; /*!< bit: 21 Transmission Interrupt Enable 21 */ + uint32_t TIE22:1; /*!< bit: 22 Transmission Interrupt Enable 22 */ + uint32_t TIE23:1; /*!< bit: 23 Transmission Interrupt Enable 23 */ + uint32_t TIE24:1; /*!< bit: 24 Transmission Interrupt Enable 24 */ + uint32_t TIE25:1; /*!< bit: 25 Transmission Interrupt Enable 25 */ + uint32_t TIE26:1; /*!< bit: 26 Transmission Interrupt Enable 26 */ + uint32_t TIE27:1; /*!< bit: 27 Transmission Interrupt Enable 27 */ + uint32_t TIE28:1; /*!< bit: 28 Transmission Interrupt Enable 28 */ + uint32_t TIE29:1; /*!< bit: 29 Transmission Interrupt Enable 29 */ + uint32_t TIE30:1; /*!< bit: 30 Transmission Interrupt Enable 30 */ + uint32_t TIE31:1; /*!< bit: 31 Transmission Interrupt Enable 31 */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_TXBTIE_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_TXBTIE_OFFSET 0xE0 /**< \brief (CAN_TXBTIE offset) Tx Buffer Transmission Interrupt Enable */ +#define CAN_TXBTIE_RESETVALUE _U_(0x00000000) /**< \brief (CAN_TXBTIE reset_value) Tx Buffer Transmission Interrupt Enable */ + +#define CAN_TXBTIE_TIE0_Pos 0 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 0 */ +#define CAN_TXBTIE_TIE0 (_U_(0x1) << CAN_TXBTIE_TIE0_Pos) +#define CAN_TXBTIE_TIE1_Pos 1 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 1 */ +#define CAN_TXBTIE_TIE1 (_U_(0x1) << CAN_TXBTIE_TIE1_Pos) +#define CAN_TXBTIE_TIE2_Pos 2 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 2 */ +#define CAN_TXBTIE_TIE2 (_U_(0x1) << CAN_TXBTIE_TIE2_Pos) +#define CAN_TXBTIE_TIE3_Pos 3 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 3 */ +#define CAN_TXBTIE_TIE3 (_U_(0x1) << CAN_TXBTIE_TIE3_Pos) +#define CAN_TXBTIE_TIE4_Pos 4 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 4 */ +#define CAN_TXBTIE_TIE4 (_U_(0x1) << CAN_TXBTIE_TIE4_Pos) +#define CAN_TXBTIE_TIE5_Pos 5 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 5 */ +#define CAN_TXBTIE_TIE5 (_U_(0x1) << CAN_TXBTIE_TIE5_Pos) +#define CAN_TXBTIE_TIE6_Pos 6 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 6 */ +#define CAN_TXBTIE_TIE6 (_U_(0x1) << CAN_TXBTIE_TIE6_Pos) +#define CAN_TXBTIE_TIE7_Pos 7 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 7 */ +#define CAN_TXBTIE_TIE7 (_U_(0x1) << CAN_TXBTIE_TIE7_Pos) +#define CAN_TXBTIE_TIE8_Pos 8 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 8 */ +#define CAN_TXBTIE_TIE8 (_U_(0x1) << CAN_TXBTIE_TIE8_Pos) +#define CAN_TXBTIE_TIE9_Pos 9 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 9 */ +#define CAN_TXBTIE_TIE9 (_U_(0x1) << CAN_TXBTIE_TIE9_Pos) +#define CAN_TXBTIE_TIE10_Pos 10 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 10 */ +#define CAN_TXBTIE_TIE10 (_U_(0x1) << CAN_TXBTIE_TIE10_Pos) +#define CAN_TXBTIE_TIE11_Pos 11 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 11 */ +#define CAN_TXBTIE_TIE11 (_U_(0x1) << CAN_TXBTIE_TIE11_Pos) +#define CAN_TXBTIE_TIE12_Pos 12 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 12 */ +#define CAN_TXBTIE_TIE12 (_U_(0x1) << CAN_TXBTIE_TIE12_Pos) +#define CAN_TXBTIE_TIE13_Pos 13 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 13 */ +#define CAN_TXBTIE_TIE13 (_U_(0x1) << CAN_TXBTIE_TIE13_Pos) +#define CAN_TXBTIE_TIE14_Pos 14 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 14 */ +#define CAN_TXBTIE_TIE14 (_U_(0x1) << CAN_TXBTIE_TIE14_Pos) +#define CAN_TXBTIE_TIE15_Pos 15 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 15 */ +#define CAN_TXBTIE_TIE15 (_U_(0x1) << CAN_TXBTIE_TIE15_Pos) +#define CAN_TXBTIE_TIE16_Pos 16 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 16 */ +#define CAN_TXBTIE_TIE16 (_U_(0x1) << CAN_TXBTIE_TIE16_Pos) +#define CAN_TXBTIE_TIE17_Pos 17 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 17 */ +#define CAN_TXBTIE_TIE17 (_U_(0x1) << CAN_TXBTIE_TIE17_Pos) +#define CAN_TXBTIE_TIE18_Pos 18 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 18 */ +#define CAN_TXBTIE_TIE18 (_U_(0x1) << CAN_TXBTIE_TIE18_Pos) +#define CAN_TXBTIE_TIE19_Pos 19 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 19 */ +#define CAN_TXBTIE_TIE19 (_U_(0x1) << CAN_TXBTIE_TIE19_Pos) +#define CAN_TXBTIE_TIE20_Pos 20 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 20 */ +#define CAN_TXBTIE_TIE20 (_U_(0x1) << CAN_TXBTIE_TIE20_Pos) +#define CAN_TXBTIE_TIE21_Pos 21 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 21 */ +#define CAN_TXBTIE_TIE21 (_U_(0x1) << CAN_TXBTIE_TIE21_Pos) +#define CAN_TXBTIE_TIE22_Pos 22 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 22 */ +#define CAN_TXBTIE_TIE22 (_U_(0x1) << CAN_TXBTIE_TIE22_Pos) +#define CAN_TXBTIE_TIE23_Pos 23 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 23 */ +#define CAN_TXBTIE_TIE23 (_U_(0x1) << CAN_TXBTIE_TIE23_Pos) +#define CAN_TXBTIE_TIE24_Pos 24 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 24 */ +#define CAN_TXBTIE_TIE24 (_U_(0x1) << CAN_TXBTIE_TIE24_Pos) +#define CAN_TXBTIE_TIE25_Pos 25 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 25 */ +#define CAN_TXBTIE_TIE25 (_U_(0x1) << CAN_TXBTIE_TIE25_Pos) +#define CAN_TXBTIE_TIE26_Pos 26 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 26 */ +#define CAN_TXBTIE_TIE26 (_U_(0x1) << CAN_TXBTIE_TIE26_Pos) +#define CAN_TXBTIE_TIE27_Pos 27 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 27 */ +#define CAN_TXBTIE_TIE27 (_U_(0x1) << CAN_TXBTIE_TIE27_Pos) +#define CAN_TXBTIE_TIE28_Pos 28 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 28 */ +#define CAN_TXBTIE_TIE28 (_U_(0x1) << CAN_TXBTIE_TIE28_Pos) +#define CAN_TXBTIE_TIE29_Pos 29 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 29 */ +#define CAN_TXBTIE_TIE29 (_U_(0x1) << CAN_TXBTIE_TIE29_Pos) +#define CAN_TXBTIE_TIE30_Pos 30 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 30 */ +#define CAN_TXBTIE_TIE30 (_U_(0x1) << CAN_TXBTIE_TIE30_Pos) +#define CAN_TXBTIE_TIE31_Pos 31 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 31 */ +#define CAN_TXBTIE_TIE31 (_U_(0x1) << CAN_TXBTIE_TIE31_Pos) +#define CAN_TXBTIE_MASK _U_(0xFFFFFFFF) /**< \brief (CAN_TXBTIE) MASK Register */ + +/* -------- CAN_TXBCIE : (CAN Offset: 0xE4) (R/W 32) Tx Buffer Cancellation Finished Interrupt Enable -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t CFIE0:1; /*!< bit: 0 Cancellation Finished Interrupt Enable 0 */ + uint32_t CFIE1:1; /*!< bit: 1 Cancellation Finished Interrupt Enable 1 */ + uint32_t CFIE2:1; /*!< bit: 2 Cancellation Finished Interrupt Enable 2 */ + uint32_t CFIE3:1; /*!< bit: 3 Cancellation Finished Interrupt Enable 3 */ + uint32_t CFIE4:1; /*!< bit: 4 Cancellation Finished Interrupt Enable 4 */ + uint32_t CFIE5:1; /*!< bit: 5 Cancellation Finished Interrupt Enable 5 */ + uint32_t CFIE6:1; /*!< bit: 6 Cancellation Finished Interrupt Enable 6 */ + uint32_t CFIE7:1; /*!< bit: 7 Cancellation Finished Interrupt Enable 7 */ + uint32_t CFIE8:1; /*!< bit: 8 Cancellation Finished Interrupt Enable 8 */ + uint32_t CFIE9:1; /*!< bit: 9 Cancellation Finished Interrupt Enable 9 */ + uint32_t CFIE10:1; /*!< bit: 10 Cancellation Finished Interrupt Enable 10 */ + uint32_t CFIE11:1; /*!< bit: 11 Cancellation Finished Interrupt Enable 11 */ + uint32_t CFIE12:1; /*!< bit: 12 Cancellation Finished Interrupt Enable 12 */ + uint32_t CFIE13:1; /*!< bit: 13 Cancellation Finished Interrupt Enable 13 */ + uint32_t CFIE14:1; /*!< bit: 14 Cancellation Finished Interrupt Enable 14 */ + uint32_t CFIE15:1; /*!< bit: 15 Cancellation Finished Interrupt Enable 15 */ + uint32_t CFIE16:1; /*!< bit: 16 Cancellation Finished Interrupt Enable 16 */ + uint32_t CFIE17:1; /*!< bit: 17 Cancellation Finished Interrupt Enable 17 */ + uint32_t CFIE18:1; /*!< bit: 18 Cancellation Finished Interrupt Enable 18 */ + uint32_t CFIE19:1; /*!< bit: 19 Cancellation Finished Interrupt Enable 19 */ + uint32_t CFIE20:1; /*!< bit: 20 Cancellation Finished Interrupt Enable 20 */ + uint32_t CFIE21:1; /*!< bit: 21 Cancellation Finished Interrupt Enable 21 */ + uint32_t CFIE22:1; /*!< bit: 22 Cancellation Finished Interrupt Enable 22 */ + uint32_t CFIE23:1; /*!< bit: 23 Cancellation Finished Interrupt Enable 23 */ + uint32_t CFIE24:1; /*!< bit: 24 Cancellation Finished Interrupt Enable 24 */ + uint32_t CFIE25:1; /*!< bit: 25 Cancellation Finished Interrupt Enable 25 */ + uint32_t CFIE26:1; /*!< bit: 26 Cancellation Finished Interrupt Enable 26 */ + uint32_t CFIE27:1; /*!< bit: 27 Cancellation Finished Interrupt Enable 27 */ + uint32_t CFIE28:1; /*!< bit: 28 Cancellation Finished Interrupt Enable 28 */ + uint32_t CFIE29:1; /*!< bit: 29 Cancellation Finished Interrupt Enable 29 */ + uint32_t CFIE30:1; /*!< bit: 30 Cancellation Finished Interrupt Enable 30 */ + uint32_t CFIE31:1; /*!< bit: 31 Cancellation Finished Interrupt Enable 31 */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_TXBCIE_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_TXBCIE_OFFSET 0xE4 /**< \brief (CAN_TXBCIE offset) Tx Buffer Cancellation Finished Interrupt Enable */ +#define CAN_TXBCIE_RESETVALUE _U_(0x00000000) /**< \brief (CAN_TXBCIE reset_value) Tx Buffer Cancellation Finished Interrupt Enable */ + +#define CAN_TXBCIE_CFIE0_Pos 0 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 0 */ +#define CAN_TXBCIE_CFIE0 (_U_(0x1) << CAN_TXBCIE_CFIE0_Pos) +#define CAN_TXBCIE_CFIE1_Pos 1 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 1 */ +#define CAN_TXBCIE_CFIE1 (_U_(0x1) << CAN_TXBCIE_CFIE1_Pos) +#define CAN_TXBCIE_CFIE2_Pos 2 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 2 */ +#define CAN_TXBCIE_CFIE2 (_U_(0x1) << CAN_TXBCIE_CFIE2_Pos) +#define CAN_TXBCIE_CFIE3_Pos 3 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 3 */ +#define CAN_TXBCIE_CFIE3 (_U_(0x1) << CAN_TXBCIE_CFIE3_Pos) +#define CAN_TXBCIE_CFIE4_Pos 4 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 4 */ +#define CAN_TXBCIE_CFIE4 (_U_(0x1) << CAN_TXBCIE_CFIE4_Pos) +#define CAN_TXBCIE_CFIE5_Pos 5 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 5 */ +#define CAN_TXBCIE_CFIE5 (_U_(0x1) << CAN_TXBCIE_CFIE5_Pos) +#define CAN_TXBCIE_CFIE6_Pos 6 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 6 */ +#define CAN_TXBCIE_CFIE6 (_U_(0x1) << CAN_TXBCIE_CFIE6_Pos) +#define CAN_TXBCIE_CFIE7_Pos 7 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 7 */ +#define CAN_TXBCIE_CFIE7 (_U_(0x1) << CAN_TXBCIE_CFIE7_Pos) +#define CAN_TXBCIE_CFIE8_Pos 8 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 8 */ +#define CAN_TXBCIE_CFIE8 (_U_(0x1) << CAN_TXBCIE_CFIE8_Pos) +#define CAN_TXBCIE_CFIE9_Pos 9 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 9 */ +#define CAN_TXBCIE_CFIE9 (_U_(0x1) << CAN_TXBCIE_CFIE9_Pos) +#define CAN_TXBCIE_CFIE10_Pos 10 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 10 */ +#define CAN_TXBCIE_CFIE10 (_U_(0x1) << CAN_TXBCIE_CFIE10_Pos) +#define CAN_TXBCIE_CFIE11_Pos 11 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 11 */ +#define CAN_TXBCIE_CFIE11 (_U_(0x1) << CAN_TXBCIE_CFIE11_Pos) +#define CAN_TXBCIE_CFIE12_Pos 12 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 12 */ +#define CAN_TXBCIE_CFIE12 (_U_(0x1) << CAN_TXBCIE_CFIE12_Pos) +#define CAN_TXBCIE_CFIE13_Pos 13 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 13 */ +#define CAN_TXBCIE_CFIE13 (_U_(0x1) << CAN_TXBCIE_CFIE13_Pos) +#define CAN_TXBCIE_CFIE14_Pos 14 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 14 */ +#define CAN_TXBCIE_CFIE14 (_U_(0x1) << CAN_TXBCIE_CFIE14_Pos) +#define CAN_TXBCIE_CFIE15_Pos 15 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 15 */ +#define CAN_TXBCIE_CFIE15 (_U_(0x1) << CAN_TXBCIE_CFIE15_Pos) +#define CAN_TXBCIE_CFIE16_Pos 16 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 16 */ +#define CAN_TXBCIE_CFIE16 (_U_(0x1) << CAN_TXBCIE_CFIE16_Pos) +#define CAN_TXBCIE_CFIE17_Pos 17 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 17 */ +#define CAN_TXBCIE_CFIE17 (_U_(0x1) << CAN_TXBCIE_CFIE17_Pos) +#define CAN_TXBCIE_CFIE18_Pos 18 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 18 */ +#define CAN_TXBCIE_CFIE18 (_U_(0x1) << CAN_TXBCIE_CFIE18_Pos) +#define CAN_TXBCIE_CFIE19_Pos 19 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 19 */ +#define CAN_TXBCIE_CFIE19 (_U_(0x1) << CAN_TXBCIE_CFIE19_Pos) +#define CAN_TXBCIE_CFIE20_Pos 20 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 20 */ +#define CAN_TXBCIE_CFIE20 (_U_(0x1) << CAN_TXBCIE_CFIE20_Pos) +#define CAN_TXBCIE_CFIE21_Pos 21 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 21 */ +#define CAN_TXBCIE_CFIE21 (_U_(0x1) << CAN_TXBCIE_CFIE21_Pos) +#define CAN_TXBCIE_CFIE22_Pos 22 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 22 */ +#define CAN_TXBCIE_CFIE22 (_U_(0x1) << CAN_TXBCIE_CFIE22_Pos) +#define CAN_TXBCIE_CFIE23_Pos 23 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 23 */ +#define CAN_TXBCIE_CFIE23 (_U_(0x1) << CAN_TXBCIE_CFIE23_Pos) +#define CAN_TXBCIE_CFIE24_Pos 24 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 24 */ +#define CAN_TXBCIE_CFIE24 (_U_(0x1) << CAN_TXBCIE_CFIE24_Pos) +#define CAN_TXBCIE_CFIE25_Pos 25 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 25 */ +#define CAN_TXBCIE_CFIE25 (_U_(0x1) << CAN_TXBCIE_CFIE25_Pos) +#define CAN_TXBCIE_CFIE26_Pos 26 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 26 */ +#define CAN_TXBCIE_CFIE26 (_U_(0x1) << CAN_TXBCIE_CFIE26_Pos) +#define CAN_TXBCIE_CFIE27_Pos 27 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 27 */ +#define CAN_TXBCIE_CFIE27 (_U_(0x1) << CAN_TXBCIE_CFIE27_Pos) +#define CAN_TXBCIE_CFIE28_Pos 28 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 28 */ +#define CAN_TXBCIE_CFIE28 (_U_(0x1) << CAN_TXBCIE_CFIE28_Pos) +#define CAN_TXBCIE_CFIE29_Pos 29 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 29 */ +#define CAN_TXBCIE_CFIE29 (_U_(0x1) << CAN_TXBCIE_CFIE29_Pos) +#define CAN_TXBCIE_CFIE30_Pos 30 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 30 */ +#define CAN_TXBCIE_CFIE30 (_U_(0x1) << CAN_TXBCIE_CFIE30_Pos) +#define CAN_TXBCIE_CFIE31_Pos 31 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 31 */ +#define CAN_TXBCIE_CFIE31 (_U_(0x1) << CAN_TXBCIE_CFIE31_Pos) +#define CAN_TXBCIE_MASK _U_(0xFFFFFFFF) /**< \brief (CAN_TXBCIE) MASK Register */ + +/* -------- CAN_TXEFC : (CAN Offset: 0xF0) (R/W 32) Tx Event FIFO Configuration -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t EFSA:16; /*!< bit: 0..15 Event FIFO Start Address */ + uint32_t EFS:6; /*!< bit: 16..21 Event FIFO Size */ + uint32_t :2; /*!< bit: 22..23 Reserved */ + uint32_t EFWM:6; /*!< bit: 24..29 Event FIFO Watermark */ + uint32_t :2; /*!< bit: 30..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_TXEFC_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_TXEFC_OFFSET 0xF0 /**< \brief (CAN_TXEFC offset) Tx Event FIFO Configuration */ +#define CAN_TXEFC_RESETVALUE _U_(0x00000000) /**< \brief (CAN_TXEFC reset_value) Tx Event FIFO Configuration */ + +#define CAN_TXEFC_EFSA_Pos 0 /**< \brief (CAN_TXEFC) Event FIFO Start Address */ +#define CAN_TXEFC_EFSA_Msk (_U_(0xFFFF) << CAN_TXEFC_EFSA_Pos) +#define CAN_TXEFC_EFSA(value) (CAN_TXEFC_EFSA_Msk & ((value) << CAN_TXEFC_EFSA_Pos)) +#define CAN_TXEFC_EFS_Pos 16 /**< \brief (CAN_TXEFC) Event FIFO Size */ +#define CAN_TXEFC_EFS_Msk (_U_(0x3F) << CAN_TXEFC_EFS_Pos) +#define CAN_TXEFC_EFS(value) (CAN_TXEFC_EFS_Msk & ((value) << CAN_TXEFC_EFS_Pos)) +#define CAN_TXEFC_EFWM_Pos 24 /**< \brief (CAN_TXEFC) Event FIFO Watermark */ +#define CAN_TXEFC_EFWM_Msk (_U_(0x3F) << CAN_TXEFC_EFWM_Pos) +#define CAN_TXEFC_EFWM(value) (CAN_TXEFC_EFWM_Msk & ((value) << CAN_TXEFC_EFWM_Pos)) +#define CAN_TXEFC_MASK _U_(0x3F3FFFFF) /**< \brief (CAN_TXEFC) MASK Register */ + +/* -------- CAN_TXEFS : (CAN Offset: 0xF4) (R/ 32) Tx Event FIFO Status -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t EFFL:6; /*!< bit: 0.. 5 Event FIFO Fill Level */ + uint32_t :2; /*!< bit: 6.. 7 Reserved */ + uint32_t EFGI:5; /*!< bit: 8..12 Event FIFO Get Index */ + uint32_t :3; /*!< bit: 13..15 Reserved */ + uint32_t EFPI:5; /*!< bit: 16..20 Event FIFO Put Index */ + uint32_t :3; /*!< bit: 21..23 Reserved */ + uint32_t EFF:1; /*!< bit: 24 Event FIFO Full */ + uint32_t TEFL:1; /*!< bit: 25 Tx Event FIFO Element Lost */ + uint32_t :6; /*!< bit: 26..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_TXEFS_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_TXEFS_OFFSET 0xF4 /**< \brief (CAN_TXEFS offset) Tx Event FIFO Status */ +#define CAN_TXEFS_RESETVALUE _U_(0x00000000) /**< \brief (CAN_TXEFS reset_value) Tx Event FIFO Status */ + +#define CAN_TXEFS_EFFL_Pos 0 /**< \brief (CAN_TXEFS) Event FIFO Fill Level */ +#define CAN_TXEFS_EFFL_Msk (_U_(0x3F) << CAN_TXEFS_EFFL_Pos) +#define CAN_TXEFS_EFFL(value) (CAN_TXEFS_EFFL_Msk & ((value) << CAN_TXEFS_EFFL_Pos)) +#define CAN_TXEFS_EFGI_Pos 8 /**< \brief (CAN_TXEFS) Event FIFO Get Index */ +#define CAN_TXEFS_EFGI_Msk (_U_(0x1F) << CAN_TXEFS_EFGI_Pos) +#define CAN_TXEFS_EFGI(value) (CAN_TXEFS_EFGI_Msk & ((value) << CAN_TXEFS_EFGI_Pos)) +#define CAN_TXEFS_EFPI_Pos 16 /**< \brief (CAN_TXEFS) Event FIFO Put Index */ +#define CAN_TXEFS_EFPI_Msk (_U_(0x1F) << CAN_TXEFS_EFPI_Pos) +#define CAN_TXEFS_EFPI(value) (CAN_TXEFS_EFPI_Msk & ((value) << CAN_TXEFS_EFPI_Pos)) +#define CAN_TXEFS_EFF_Pos 24 /**< \brief (CAN_TXEFS) Event FIFO Full */ +#define CAN_TXEFS_EFF (_U_(0x1) << CAN_TXEFS_EFF_Pos) +#define CAN_TXEFS_TEFL_Pos 25 /**< \brief (CAN_TXEFS) Tx Event FIFO Element Lost */ +#define CAN_TXEFS_TEFL (_U_(0x1) << CAN_TXEFS_TEFL_Pos) +#define CAN_TXEFS_MASK _U_(0x031F1F3F) /**< \brief (CAN_TXEFS) MASK Register */ + +/* -------- CAN_TXEFA : (CAN Offset: 0xF8) (R/W 32) Tx Event FIFO Acknowledge -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t EFAI:5; /*!< bit: 0.. 4 Event FIFO Acknowledge Index */ + uint32_t :27; /*!< bit: 5..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_TXEFA_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_TXEFA_OFFSET 0xF8 /**< \brief (CAN_TXEFA offset) Tx Event FIFO Acknowledge */ +#define CAN_TXEFA_RESETVALUE _U_(0x00000000) /**< \brief (CAN_TXEFA reset_value) Tx Event FIFO Acknowledge */ + +#define CAN_TXEFA_EFAI_Pos 0 /**< \brief (CAN_TXEFA) Event FIFO Acknowledge Index */ +#define CAN_TXEFA_EFAI_Msk (_U_(0x1F) << CAN_TXEFA_EFAI_Pos) +#define CAN_TXEFA_EFAI(value) (CAN_TXEFA_EFAI_Msk & ((value) << CAN_TXEFA_EFAI_Pos)) +#define CAN_TXEFA_MASK _U_(0x0000001F) /**< \brief (CAN_TXEFA) MASK Register */ + +/* -------- CAN_RXBE_0 : (CAN Offset: 0x00) (R/W 32) Rx Buffer Element 0 -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t ID:29; /*!< bit: 0..28 Identifier */ + uint32_t RTR:1; /*!< bit: 29 Remote Transmission Request */ + uint32_t XTD:1; /*!< bit: 30 Extended Identifier */ + uint32_t ESI:1; /*!< bit: 31 Error State Indicator */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_RXBE_0_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_RXBE_0_OFFSET 0x00 /**< \brief (CAN_RXBE_0 offset) Rx Buffer Element 0 */ +#define CAN_RXBE_0_RESETVALUE _U_(0x00000000) /**< \brief (CAN_RXBE_0 reset_value) Rx Buffer Element 0 */ + +#define CAN_RXBE_0_ID_Pos 0 /**< \brief (CAN_RXBE_0) Identifier */ +#define CAN_RXBE_0_ID_Msk (_U_(0x1FFFFFFF) << CAN_RXBE_0_ID_Pos) +#define CAN_RXBE_0_ID(value) (CAN_RXBE_0_ID_Msk & ((value) << CAN_RXBE_0_ID_Pos)) +#define CAN_RXBE_0_RTR_Pos 29 /**< \brief (CAN_RXBE_0) Remote Transmission Request */ +#define CAN_RXBE_0_RTR (_U_(0x1) << CAN_RXBE_0_RTR_Pos) +#define CAN_RXBE_0_XTD_Pos 30 /**< \brief (CAN_RXBE_0) Extended Identifier */ +#define CAN_RXBE_0_XTD (_U_(0x1) << CAN_RXBE_0_XTD_Pos) +#define CAN_RXBE_0_ESI_Pos 31 /**< \brief (CAN_RXBE_0) Error State Indicator */ +#define CAN_RXBE_0_ESI (_U_(0x1) << CAN_RXBE_0_ESI_Pos) +#define CAN_RXBE_0_MASK _U_(0xFFFFFFFF) /**< \brief (CAN_RXBE_0) MASK Register */ + +/* -------- CAN_RXBE_1 : (CAN Offset: 0x04) (R/W 32) Rx Buffer Element 1 -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t RXTS:16; /*!< bit: 0..15 Rx Timestamp */ + uint32_t DLC:4; /*!< bit: 16..19 Data Length Code */ + uint32_t BRS:1; /*!< bit: 20 Bit Rate Search */ + uint32_t FDF:1; /*!< bit: 21 FD Format */ + uint32_t :2; /*!< bit: 22..23 Reserved */ + uint32_t FIDX:7; /*!< bit: 24..30 Filter Index */ + uint32_t ANMF:1; /*!< bit: 31 Accepted Non-matching Frame */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_RXBE_1_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_RXBE_1_OFFSET 0x04 /**< \brief (CAN_RXBE_1 offset) Rx Buffer Element 1 */ +#define CAN_RXBE_1_RESETVALUE _U_(0x00000000) /**< \brief (CAN_RXBE_1 reset_value) Rx Buffer Element 1 */ + +#define CAN_RXBE_1_RXTS_Pos 0 /**< \brief (CAN_RXBE_1) Rx Timestamp */ +#define CAN_RXBE_1_RXTS_Msk (_U_(0xFFFF) << CAN_RXBE_1_RXTS_Pos) +#define CAN_RXBE_1_RXTS(value) (CAN_RXBE_1_RXTS_Msk & ((value) << CAN_RXBE_1_RXTS_Pos)) +#define CAN_RXBE_1_DLC_Pos 16 /**< \brief (CAN_RXBE_1) Data Length Code */ +#define CAN_RXBE_1_DLC_Msk (_U_(0xF) << CAN_RXBE_1_DLC_Pos) +#define CAN_RXBE_1_DLC(value) (CAN_RXBE_1_DLC_Msk & ((value) << CAN_RXBE_1_DLC_Pos)) +#define CAN_RXBE_1_BRS_Pos 20 /**< \brief (CAN_RXBE_1) Bit Rate Search */ +#define CAN_RXBE_1_BRS (_U_(0x1) << CAN_RXBE_1_BRS_Pos) +#define CAN_RXBE_1_FDF_Pos 21 /**< \brief (CAN_RXBE_1) FD Format */ +#define CAN_RXBE_1_FDF (_U_(0x1) << CAN_RXBE_1_FDF_Pos) +#define CAN_RXBE_1_FIDX_Pos 24 /**< \brief (CAN_RXBE_1) Filter Index */ +#define CAN_RXBE_1_FIDX_Msk (_U_(0x7F) << CAN_RXBE_1_FIDX_Pos) +#define CAN_RXBE_1_FIDX(value) (CAN_RXBE_1_FIDX_Msk & ((value) << CAN_RXBE_1_FIDX_Pos)) +#define CAN_RXBE_1_ANMF_Pos 31 /**< \brief (CAN_RXBE_1) Accepted Non-matching Frame */ +#define CAN_RXBE_1_ANMF (_U_(0x1) << CAN_RXBE_1_ANMF_Pos) +#define CAN_RXBE_1_MASK _U_(0xFF3FFFFF) /**< \brief (CAN_RXBE_1) MASK Register */ + +/* -------- CAN_RXBE_DATA : (CAN Offset: 0x08) (R/W 32) Rx Buffer Element Data -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t DB0:8; /*!< bit: 0.. 7 Data Byte 0 */ + uint32_t DB1:8; /*!< bit: 8..15 Data Byte 1 */ + uint32_t DB2:8; /*!< bit: 16..23 Data Byte 2 */ + uint32_t DB3:8; /*!< bit: 24..31 Data Byte 3 */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_RXBE_DATA_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_RXBE_DATA_OFFSET 0x08 /**< \brief (CAN_RXBE_DATA offset) Rx Buffer Element Data */ +#define CAN_RXBE_DATA_RESETVALUE _U_(0x00000000) /**< \brief (CAN_RXBE_DATA reset_value) Rx Buffer Element Data */ + +#define CAN_RXBE_DATA_DB0_Pos 0 /**< \brief (CAN_RXBE_DATA) Data Byte 0 */ +#define CAN_RXBE_DATA_DB0_Msk (_U_(0xFF) << CAN_RXBE_DATA_DB0_Pos) +#define CAN_RXBE_DATA_DB0(value) (CAN_RXBE_DATA_DB0_Msk & ((value) << CAN_RXBE_DATA_DB0_Pos)) +#define CAN_RXBE_DATA_DB1_Pos 8 /**< \brief (CAN_RXBE_DATA) Data Byte 1 */ +#define CAN_RXBE_DATA_DB1_Msk (_U_(0xFF) << CAN_RXBE_DATA_DB1_Pos) +#define CAN_RXBE_DATA_DB1(value) (CAN_RXBE_DATA_DB1_Msk & ((value) << CAN_RXBE_DATA_DB1_Pos)) +#define CAN_RXBE_DATA_DB2_Pos 16 /**< \brief (CAN_RXBE_DATA) Data Byte 2 */ +#define CAN_RXBE_DATA_DB2_Msk (_U_(0xFF) << CAN_RXBE_DATA_DB2_Pos) +#define CAN_RXBE_DATA_DB2(value) (CAN_RXBE_DATA_DB2_Msk & ((value) << CAN_RXBE_DATA_DB2_Pos)) +#define CAN_RXBE_DATA_DB3_Pos 24 /**< \brief (CAN_RXBE_DATA) Data Byte 3 */ +#define CAN_RXBE_DATA_DB3_Msk (_U_(0xFF) << CAN_RXBE_DATA_DB3_Pos) +#define CAN_RXBE_DATA_DB3(value) (CAN_RXBE_DATA_DB3_Msk & ((value) << CAN_RXBE_DATA_DB3_Pos)) +#define CAN_RXBE_DATA_MASK _U_(0xFFFFFFFF) /**< \brief (CAN_RXBE_DATA) MASK Register */ + +/* -------- CAN_RXF0E_0 : (CAN Offset: 0x00) (R/W 32) Rx FIFO 0 Element 0 -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t ID:29; /*!< bit: 0..28 Identifier */ + uint32_t RTR:1; /*!< bit: 29 Remote Transmission Request */ + uint32_t XTD:1; /*!< bit: 30 Extended Identifier */ + uint32_t ESI:1; /*!< bit: 31 Error State Indicator */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_RXF0E_0_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_RXF0E_0_OFFSET 0x00 /**< \brief (CAN_RXF0E_0 offset) Rx FIFO 0 Element 0 */ +#define CAN_RXF0E_0_RESETVALUE _U_(0x00000000) /**< \brief (CAN_RXF0E_0 reset_value) Rx FIFO 0 Element 0 */ + +#define CAN_RXF0E_0_ID_Pos 0 /**< \brief (CAN_RXF0E_0) Identifier */ +#define CAN_RXF0E_0_ID_Msk (_U_(0x1FFFFFFF) << CAN_RXF0E_0_ID_Pos) +#define CAN_RXF0E_0_ID(value) (CAN_RXF0E_0_ID_Msk & ((value) << CAN_RXF0E_0_ID_Pos)) +#define CAN_RXF0E_0_RTR_Pos 29 /**< \brief (CAN_RXF0E_0) Remote Transmission Request */ +#define CAN_RXF0E_0_RTR (_U_(0x1) << CAN_RXF0E_0_RTR_Pos) +#define CAN_RXF0E_0_XTD_Pos 30 /**< \brief (CAN_RXF0E_0) Extended Identifier */ +#define CAN_RXF0E_0_XTD (_U_(0x1) << CAN_RXF0E_0_XTD_Pos) +#define CAN_RXF0E_0_ESI_Pos 31 /**< \brief (CAN_RXF0E_0) Error State Indicator */ +#define CAN_RXF0E_0_ESI (_U_(0x1) << CAN_RXF0E_0_ESI_Pos) +#define CAN_RXF0E_0_MASK _U_(0xFFFFFFFF) /**< \brief (CAN_RXF0E_0) MASK Register */ + +/* -------- CAN_RXF0E_1 : (CAN Offset: 0x04) (R/W 32) Rx FIFO 0 Element 1 -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t RXTS:16; /*!< bit: 0..15 Rx Timestamp */ + uint32_t DLC:4; /*!< bit: 16..19 Data Length Code */ + uint32_t BRS:1; /*!< bit: 20 Bit Rate Search */ + uint32_t FDF:1; /*!< bit: 21 FD Format */ + uint32_t :2; /*!< bit: 22..23 Reserved */ + uint32_t FIDX:7; /*!< bit: 24..30 Filter Index */ + uint32_t ANMF:1; /*!< bit: 31 Accepted Non-matching Frame */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_RXF0E_1_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_RXF0E_1_OFFSET 0x04 /**< \brief (CAN_RXF0E_1 offset) Rx FIFO 0 Element 1 */ +#define CAN_RXF0E_1_RESETVALUE _U_(0x00000000) /**< \brief (CAN_RXF0E_1 reset_value) Rx FIFO 0 Element 1 */ + +#define CAN_RXF0E_1_RXTS_Pos 0 /**< \brief (CAN_RXF0E_1) Rx Timestamp */ +#define CAN_RXF0E_1_RXTS_Msk (_U_(0xFFFF) << CAN_RXF0E_1_RXTS_Pos) +#define CAN_RXF0E_1_RXTS(value) (CAN_RXF0E_1_RXTS_Msk & ((value) << CAN_RXF0E_1_RXTS_Pos)) +#define CAN_RXF0E_1_DLC_Pos 16 /**< \brief (CAN_RXF0E_1) Data Length Code */ +#define CAN_RXF0E_1_DLC_Msk (_U_(0xF) << CAN_RXF0E_1_DLC_Pos) +#define CAN_RXF0E_1_DLC(value) (CAN_RXF0E_1_DLC_Msk & ((value) << CAN_RXF0E_1_DLC_Pos)) +#define CAN_RXF0E_1_BRS_Pos 20 /**< \brief (CAN_RXF0E_1) Bit Rate Search */ +#define CAN_RXF0E_1_BRS (_U_(0x1) << CAN_RXF0E_1_BRS_Pos) +#define CAN_RXF0E_1_FDF_Pos 21 /**< \brief (CAN_RXF0E_1) FD Format */ +#define CAN_RXF0E_1_FDF (_U_(0x1) << CAN_RXF0E_1_FDF_Pos) +#define CAN_RXF0E_1_FIDX_Pos 24 /**< \brief (CAN_RXF0E_1) Filter Index */ +#define CAN_RXF0E_1_FIDX_Msk (_U_(0x7F) << CAN_RXF0E_1_FIDX_Pos) +#define CAN_RXF0E_1_FIDX(value) (CAN_RXF0E_1_FIDX_Msk & ((value) << CAN_RXF0E_1_FIDX_Pos)) +#define CAN_RXF0E_1_ANMF_Pos 31 /**< \brief (CAN_RXF0E_1) Accepted Non-matching Frame */ +#define CAN_RXF0E_1_ANMF (_U_(0x1) << CAN_RXF0E_1_ANMF_Pos) +#define CAN_RXF0E_1_MASK _U_(0xFF3FFFFF) /**< \brief (CAN_RXF0E_1) MASK Register */ + +/* -------- CAN_RXF0E_DATA : (CAN Offset: 0x08) (R/W 32) Rx FIFO 0 Element Data -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t DB0:8; /*!< bit: 0.. 7 Data Byte 0 */ + uint32_t DB1:8; /*!< bit: 8..15 Data Byte 1 */ + uint32_t DB2:8; /*!< bit: 16..23 Data Byte 2 */ + uint32_t DB3:8; /*!< bit: 24..31 Data Byte 3 */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_RXF0E_DATA_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_RXF0E_DATA_OFFSET 0x08 /**< \brief (CAN_RXF0E_DATA offset) Rx FIFO 0 Element Data */ +#define CAN_RXF0E_DATA_RESETVALUE _U_(0x00000000) /**< \brief (CAN_RXF0E_DATA reset_value) Rx FIFO 0 Element Data */ + +#define CAN_RXF0E_DATA_DB0_Pos 0 /**< \brief (CAN_RXF0E_DATA) Data Byte 0 */ +#define CAN_RXF0E_DATA_DB0_Msk (_U_(0xFF) << CAN_RXF0E_DATA_DB0_Pos) +#define CAN_RXF0E_DATA_DB0(value) (CAN_RXF0E_DATA_DB0_Msk & ((value) << CAN_RXF0E_DATA_DB0_Pos)) +#define CAN_RXF0E_DATA_DB1_Pos 8 /**< \brief (CAN_RXF0E_DATA) Data Byte 1 */ +#define CAN_RXF0E_DATA_DB1_Msk (_U_(0xFF) << CAN_RXF0E_DATA_DB1_Pos) +#define CAN_RXF0E_DATA_DB1(value) (CAN_RXF0E_DATA_DB1_Msk & ((value) << CAN_RXF0E_DATA_DB1_Pos)) +#define CAN_RXF0E_DATA_DB2_Pos 16 /**< \brief (CAN_RXF0E_DATA) Data Byte 2 */ +#define CAN_RXF0E_DATA_DB2_Msk (_U_(0xFF) << CAN_RXF0E_DATA_DB2_Pos) +#define CAN_RXF0E_DATA_DB2(value) (CAN_RXF0E_DATA_DB2_Msk & ((value) << CAN_RXF0E_DATA_DB2_Pos)) +#define CAN_RXF0E_DATA_DB3_Pos 24 /**< \brief (CAN_RXF0E_DATA) Data Byte 3 */ +#define CAN_RXF0E_DATA_DB3_Msk (_U_(0xFF) << CAN_RXF0E_DATA_DB3_Pos) +#define CAN_RXF0E_DATA_DB3(value) (CAN_RXF0E_DATA_DB3_Msk & ((value) << CAN_RXF0E_DATA_DB3_Pos)) +#define CAN_RXF0E_DATA_MASK _U_(0xFFFFFFFF) /**< \brief (CAN_RXF0E_DATA) MASK Register */ + +/* -------- CAN_RXF1E_0 : (CAN Offset: 0x00) (R/W 32) Rx FIFO 1 Element 0 -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t ID:29; /*!< bit: 0..28 Identifier */ + uint32_t RTR:1; /*!< bit: 29 Remote Transmission Request */ + uint32_t XTD:1; /*!< bit: 30 Extended Identifier */ + uint32_t ESI:1; /*!< bit: 31 Error State Indicator */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_RXF1E_0_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_RXF1E_0_OFFSET 0x00 /**< \brief (CAN_RXF1E_0 offset) Rx FIFO 1 Element 0 */ +#define CAN_RXF1E_0_RESETVALUE _U_(0x00000000) /**< \brief (CAN_RXF1E_0 reset_value) Rx FIFO 1 Element 0 */ + +#define CAN_RXF1E_0_ID_Pos 0 /**< \brief (CAN_RXF1E_0) Identifier */ +#define CAN_RXF1E_0_ID_Msk (_U_(0x1FFFFFFF) << CAN_RXF1E_0_ID_Pos) +#define CAN_RXF1E_0_ID(value) (CAN_RXF1E_0_ID_Msk & ((value) << CAN_RXF1E_0_ID_Pos)) +#define CAN_RXF1E_0_RTR_Pos 29 /**< \brief (CAN_RXF1E_0) Remote Transmission Request */ +#define CAN_RXF1E_0_RTR (_U_(0x1) << CAN_RXF1E_0_RTR_Pos) +#define CAN_RXF1E_0_XTD_Pos 30 /**< \brief (CAN_RXF1E_0) Extended Identifier */ +#define CAN_RXF1E_0_XTD (_U_(0x1) << CAN_RXF1E_0_XTD_Pos) +#define CAN_RXF1E_0_ESI_Pos 31 /**< \brief (CAN_RXF1E_0) Error State Indicator */ +#define CAN_RXF1E_0_ESI (_U_(0x1) << CAN_RXF1E_0_ESI_Pos) +#define CAN_RXF1E_0_MASK _U_(0xFFFFFFFF) /**< \brief (CAN_RXF1E_0) MASK Register */ + +/* -------- CAN_RXF1E_1 : (CAN Offset: 0x04) (R/W 32) Rx FIFO 1 Element 1 -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t RXTS:16; /*!< bit: 0..15 Rx Timestamp */ + uint32_t DLC:4; /*!< bit: 16..19 Data Length Code */ + uint32_t BRS:1; /*!< bit: 20 Bit Rate Search */ + uint32_t FDF:1; /*!< bit: 21 FD Format */ + uint32_t :2; /*!< bit: 22..23 Reserved */ + uint32_t FIDX:7; /*!< bit: 24..30 Filter Index */ + uint32_t ANMF:1; /*!< bit: 31 Accepted Non-matching Frame */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_RXF1E_1_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_RXF1E_1_OFFSET 0x04 /**< \brief (CAN_RXF1E_1 offset) Rx FIFO 1 Element 1 */ +#define CAN_RXF1E_1_RESETVALUE _U_(0x00000000) /**< \brief (CAN_RXF1E_1 reset_value) Rx FIFO 1 Element 1 */ + +#define CAN_RXF1E_1_RXTS_Pos 0 /**< \brief (CAN_RXF1E_1) Rx Timestamp */ +#define CAN_RXF1E_1_RXTS_Msk (_U_(0xFFFF) << CAN_RXF1E_1_RXTS_Pos) +#define CAN_RXF1E_1_RXTS(value) (CAN_RXF1E_1_RXTS_Msk & ((value) << CAN_RXF1E_1_RXTS_Pos)) +#define CAN_RXF1E_1_DLC_Pos 16 /**< \brief (CAN_RXF1E_1) Data Length Code */ +#define CAN_RXF1E_1_DLC_Msk (_U_(0xF) << CAN_RXF1E_1_DLC_Pos) +#define CAN_RXF1E_1_DLC(value) (CAN_RXF1E_1_DLC_Msk & ((value) << CAN_RXF1E_1_DLC_Pos)) +#define CAN_RXF1E_1_BRS_Pos 20 /**< \brief (CAN_RXF1E_1) Bit Rate Search */ +#define CAN_RXF1E_1_BRS (_U_(0x1) << CAN_RXF1E_1_BRS_Pos) +#define CAN_RXF1E_1_FDF_Pos 21 /**< \brief (CAN_RXF1E_1) FD Format */ +#define CAN_RXF1E_1_FDF (_U_(0x1) << CAN_RXF1E_1_FDF_Pos) +#define CAN_RXF1E_1_FIDX_Pos 24 /**< \brief (CAN_RXF1E_1) Filter Index */ +#define CAN_RXF1E_1_FIDX_Msk (_U_(0x7F) << CAN_RXF1E_1_FIDX_Pos) +#define CAN_RXF1E_1_FIDX(value) (CAN_RXF1E_1_FIDX_Msk & ((value) << CAN_RXF1E_1_FIDX_Pos)) +#define CAN_RXF1E_1_ANMF_Pos 31 /**< \brief (CAN_RXF1E_1) Accepted Non-matching Frame */ +#define CAN_RXF1E_1_ANMF (_U_(0x1) << CAN_RXF1E_1_ANMF_Pos) +#define CAN_RXF1E_1_MASK _U_(0xFF3FFFFF) /**< \brief (CAN_RXF1E_1) MASK Register */ + +/* -------- CAN_RXF1E_DATA : (CAN Offset: 0x08) (R/W 32) Rx FIFO 1 Element Data -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t DB0:8; /*!< bit: 0.. 7 Data Byte 0 */ + uint32_t DB1:8; /*!< bit: 8..15 Data Byte 1 */ + uint32_t DB2:8; /*!< bit: 16..23 Data Byte 2 */ + uint32_t DB3:8; /*!< bit: 24..31 Data Byte 3 */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_RXF1E_DATA_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_RXF1E_DATA_OFFSET 0x08 /**< \brief (CAN_RXF1E_DATA offset) Rx FIFO 1 Element Data */ +#define CAN_RXF1E_DATA_RESETVALUE _U_(0x00000000) /**< \brief (CAN_RXF1E_DATA reset_value) Rx FIFO 1 Element Data */ + +#define CAN_RXF1E_DATA_DB0_Pos 0 /**< \brief (CAN_RXF1E_DATA) Data Byte 0 */ +#define CAN_RXF1E_DATA_DB0_Msk (_U_(0xFF) << CAN_RXF1E_DATA_DB0_Pos) +#define CAN_RXF1E_DATA_DB0(value) (CAN_RXF1E_DATA_DB0_Msk & ((value) << CAN_RXF1E_DATA_DB0_Pos)) +#define CAN_RXF1E_DATA_DB1_Pos 8 /**< \brief (CAN_RXF1E_DATA) Data Byte 1 */ +#define CAN_RXF1E_DATA_DB1_Msk (_U_(0xFF) << CAN_RXF1E_DATA_DB1_Pos) +#define CAN_RXF1E_DATA_DB1(value) (CAN_RXF1E_DATA_DB1_Msk & ((value) << CAN_RXF1E_DATA_DB1_Pos)) +#define CAN_RXF1E_DATA_DB2_Pos 16 /**< \brief (CAN_RXF1E_DATA) Data Byte 2 */ +#define CAN_RXF1E_DATA_DB2_Msk (_U_(0xFF) << CAN_RXF1E_DATA_DB2_Pos) +#define CAN_RXF1E_DATA_DB2(value) (CAN_RXF1E_DATA_DB2_Msk & ((value) << CAN_RXF1E_DATA_DB2_Pos)) +#define CAN_RXF1E_DATA_DB3_Pos 24 /**< \brief (CAN_RXF1E_DATA) Data Byte 3 */ +#define CAN_RXF1E_DATA_DB3_Msk (_U_(0xFF) << CAN_RXF1E_DATA_DB3_Pos) +#define CAN_RXF1E_DATA_DB3(value) (CAN_RXF1E_DATA_DB3_Msk & ((value) << CAN_RXF1E_DATA_DB3_Pos)) +#define CAN_RXF1E_DATA_MASK _U_(0xFFFFFFFF) /**< \brief (CAN_RXF1E_DATA) MASK Register */ + +/* -------- CAN_SIDFE_0 : (CAN Offset: 0x00) (R/W 32) Standard Message ID Filter Element -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t SFID2:11; /*!< bit: 0..10 Standard Filter ID 2 */ + uint32_t :5; /*!< bit: 11..15 Reserved */ + uint32_t SFID1:11; /*!< bit: 16..26 Standard Filter ID 1 */ + uint32_t SFEC:3; /*!< bit: 27..29 Standard Filter Element Configuration */ + uint32_t SFT:2; /*!< bit: 30..31 Standard Filter Type */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_SIDFE_0_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_SIDFE_0_OFFSET 0x00 /**< \brief (CAN_SIDFE_0 offset) Standard Message ID Filter Element */ +#define CAN_SIDFE_0_RESETVALUE _U_(0x00000000) /**< \brief (CAN_SIDFE_0 reset_value) Standard Message ID Filter Element */ + +#define CAN_SIDFE_0_SFID2_Pos 0 /**< \brief (CAN_SIDFE_0) Standard Filter ID 2 */ +#define CAN_SIDFE_0_SFID2_Msk (_U_(0x7FF) << CAN_SIDFE_0_SFID2_Pos) +#define CAN_SIDFE_0_SFID2(value) (CAN_SIDFE_0_SFID2_Msk & ((value) << CAN_SIDFE_0_SFID2_Pos)) +#define CAN_SIDFE_0_SFID1_Pos 16 /**< \brief (CAN_SIDFE_0) Standard Filter ID 1 */ +#define CAN_SIDFE_0_SFID1_Msk (_U_(0x7FF) << CAN_SIDFE_0_SFID1_Pos) +#define CAN_SIDFE_0_SFID1(value) (CAN_SIDFE_0_SFID1_Msk & ((value) << CAN_SIDFE_0_SFID1_Pos)) +#define CAN_SIDFE_0_SFEC_Pos 27 /**< \brief (CAN_SIDFE_0) Standard Filter Element Configuration */ +#define CAN_SIDFE_0_SFEC_Msk (_U_(0x7) << CAN_SIDFE_0_SFEC_Pos) +#define CAN_SIDFE_0_SFEC(value) (CAN_SIDFE_0_SFEC_Msk & ((value) << CAN_SIDFE_0_SFEC_Pos)) +#define CAN_SIDFE_0_SFEC_DISABLE_Val _U_(0x0) /**< \brief (CAN_SIDFE_0) Disable filter element */ +#define CAN_SIDFE_0_SFEC_STF0M_Val _U_(0x1) /**< \brief (CAN_SIDFE_0) Store in Rx FIFO 0 if filter match */ +#define CAN_SIDFE_0_SFEC_STF1M_Val _U_(0x2) /**< \brief (CAN_SIDFE_0) Store in Rx FIFO 1 if filter match */ +#define CAN_SIDFE_0_SFEC_REJECT_Val _U_(0x3) /**< \brief (CAN_SIDFE_0) Reject ID if filter match */ +#define CAN_SIDFE_0_SFEC_PRIORITY_Val _U_(0x4) /**< \brief (CAN_SIDFE_0) Set priority if filter match */ +#define CAN_SIDFE_0_SFEC_PRIF0M_Val _U_(0x5) /**< \brief (CAN_SIDFE_0) Set priority and store in FIFO 0 if filter match */ +#define CAN_SIDFE_0_SFEC_PRIF1M_Val _U_(0x6) /**< \brief (CAN_SIDFE_0) Set priority and store in FIFO 1 if filter match */ +#define CAN_SIDFE_0_SFEC_STRXBUF_Val _U_(0x7) /**< \brief (CAN_SIDFE_0) Store into Rx Buffer */ +#define CAN_SIDFE_0_SFEC_DISABLE (CAN_SIDFE_0_SFEC_DISABLE_Val << CAN_SIDFE_0_SFEC_Pos) +#define CAN_SIDFE_0_SFEC_STF0M (CAN_SIDFE_0_SFEC_STF0M_Val << CAN_SIDFE_0_SFEC_Pos) +#define CAN_SIDFE_0_SFEC_STF1M (CAN_SIDFE_0_SFEC_STF1M_Val << CAN_SIDFE_0_SFEC_Pos) +#define CAN_SIDFE_0_SFEC_REJECT (CAN_SIDFE_0_SFEC_REJECT_Val << CAN_SIDFE_0_SFEC_Pos) +#define CAN_SIDFE_0_SFEC_PRIORITY (CAN_SIDFE_0_SFEC_PRIORITY_Val << CAN_SIDFE_0_SFEC_Pos) +#define CAN_SIDFE_0_SFEC_PRIF0M (CAN_SIDFE_0_SFEC_PRIF0M_Val << CAN_SIDFE_0_SFEC_Pos) +#define CAN_SIDFE_0_SFEC_PRIF1M (CAN_SIDFE_0_SFEC_PRIF1M_Val << CAN_SIDFE_0_SFEC_Pos) +#define CAN_SIDFE_0_SFEC_STRXBUF (CAN_SIDFE_0_SFEC_STRXBUF_Val << CAN_SIDFE_0_SFEC_Pos) +#define CAN_SIDFE_0_SFT_Pos 30 /**< \brief (CAN_SIDFE_0) Standard Filter Type */ +#define CAN_SIDFE_0_SFT_Msk (_U_(0x3) << CAN_SIDFE_0_SFT_Pos) +#define CAN_SIDFE_0_SFT(value) (CAN_SIDFE_0_SFT_Msk & ((value) << CAN_SIDFE_0_SFT_Pos)) +#define CAN_SIDFE_0_SFT_RANGE_Val _U_(0x0) /**< \brief (CAN_SIDFE_0) Range filter from SFID1 to SFID2 */ +#define CAN_SIDFE_0_SFT_DUAL_Val _U_(0x1) /**< \brief (CAN_SIDFE_0) Dual ID filter for SFID1 or SFID2 */ +#define CAN_SIDFE_0_SFT_CLASSIC_Val _U_(0x2) /**< \brief (CAN_SIDFE_0) Classic filter */ +#define CAN_SIDFE_0_SFT_RANGE (CAN_SIDFE_0_SFT_RANGE_Val << CAN_SIDFE_0_SFT_Pos) +#define CAN_SIDFE_0_SFT_DUAL (CAN_SIDFE_0_SFT_DUAL_Val << CAN_SIDFE_0_SFT_Pos) +#define CAN_SIDFE_0_SFT_CLASSIC (CAN_SIDFE_0_SFT_CLASSIC_Val << CAN_SIDFE_0_SFT_Pos) +#define CAN_SIDFE_0_MASK _U_(0xFFFF07FF) /**< \brief (CAN_SIDFE_0) MASK Register */ + +/* -------- CAN_TXBE_0 : (CAN Offset: 0x00) (R/W 32) Tx Buffer Element 0 -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t ID:29; /*!< bit: 0..28 Identifier */ + uint32_t RTR:1; /*!< bit: 29 Remote Transmission Request */ + uint32_t XTD:1; /*!< bit: 30 Extended Identifier */ + uint32_t ESI:1; /*!< bit: 31 Error State Indicator */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_TXBE_0_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_TXBE_0_OFFSET 0x00 /**< \brief (CAN_TXBE_0 offset) Tx Buffer Element 0 */ +#define CAN_TXBE_0_RESETVALUE _U_(0x00000000) /**< \brief (CAN_TXBE_0 reset_value) Tx Buffer Element 0 */ + +#define CAN_TXBE_0_ID_Pos 0 /**< \brief (CAN_TXBE_0) Identifier */ +#define CAN_TXBE_0_ID_Msk (_U_(0x1FFFFFFF) << CAN_TXBE_0_ID_Pos) +#define CAN_TXBE_0_ID(value) (CAN_TXBE_0_ID_Msk & ((value) << CAN_TXBE_0_ID_Pos)) +#define CAN_TXBE_0_RTR_Pos 29 /**< \brief (CAN_TXBE_0) Remote Transmission Request */ +#define CAN_TXBE_0_RTR (_U_(0x1) << CAN_TXBE_0_RTR_Pos) +#define CAN_TXBE_0_XTD_Pos 30 /**< \brief (CAN_TXBE_0) Extended Identifier */ +#define CAN_TXBE_0_XTD (_U_(0x1) << CAN_TXBE_0_XTD_Pos) +#define CAN_TXBE_0_ESI_Pos 31 /**< \brief (CAN_TXBE_0) Error State Indicator */ +#define CAN_TXBE_0_ESI (_U_(0x1) << CAN_TXBE_0_ESI_Pos) +#define CAN_TXBE_0_MASK _U_(0xFFFFFFFF) /**< \brief (CAN_TXBE_0) MASK Register */ + +/* -------- CAN_TXBE_1 : (CAN Offset: 0x04) (R/W 32) Tx Buffer Element 1 -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t :16; /*!< bit: 0..15 Reserved */ + uint32_t DLC:4; /*!< bit: 16..19 Identifier */ + uint32_t BRS:1; /*!< bit: 20 Bit Rate Search */ + uint32_t FDF:1; /*!< bit: 21 FD Format */ + uint32_t :1; /*!< bit: 22 Reserved */ + uint32_t EFC:1; /*!< bit: 23 Event FIFO Control */ + uint32_t MM:8; /*!< bit: 24..31 Message Marker */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_TXBE_1_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_TXBE_1_OFFSET 0x04 /**< \brief (CAN_TXBE_1 offset) Tx Buffer Element 1 */ +#define CAN_TXBE_1_RESETVALUE _U_(0x00000000) /**< \brief (CAN_TXBE_1 reset_value) Tx Buffer Element 1 */ + +#define CAN_TXBE_1_DLC_Pos 16 /**< \brief (CAN_TXBE_1) Identifier */ +#define CAN_TXBE_1_DLC_Msk (_U_(0xF) << CAN_TXBE_1_DLC_Pos) +#define CAN_TXBE_1_DLC(value) (CAN_TXBE_1_DLC_Msk & ((value) << CAN_TXBE_1_DLC_Pos)) +#define CAN_TXBE_1_BRS_Pos 20 /**< \brief (CAN_TXBE_1) Bit Rate Search */ +#define CAN_TXBE_1_BRS (_U_(0x1) << CAN_TXBE_1_BRS_Pos) +#define CAN_TXBE_1_FDF_Pos 21 /**< \brief (CAN_TXBE_1) FD Format */ +#define CAN_TXBE_1_FDF (_U_(0x1) << CAN_TXBE_1_FDF_Pos) +#define CAN_TXBE_1_EFC_Pos 23 /**< \brief (CAN_TXBE_1) Event FIFO Control */ +#define CAN_TXBE_1_EFC (_U_(0x1) << CAN_TXBE_1_EFC_Pos) +#define CAN_TXBE_1_MM_Pos 24 /**< \brief (CAN_TXBE_1) Message Marker */ +#define CAN_TXBE_1_MM_Msk (_U_(0xFF) << CAN_TXBE_1_MM_Pos) +#define CAN_TXBE_1_MM(value) (CAN_TXBE_1_MM_Msk & ((value) << CAN_TXBE_1_MM_Pos)) +#define CAN_TXBE_1_MASK _U_(0xFFBF0000) /**< \brief (CAN_TXBE_1) MASK Register */ + +/* -------- CAN_TXBE_DATA : (CAN Offset: 0x08) (R/W 32) Tx Buffer Element Data -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t DB0:8; /*!< bit: 0.. 7 Data Byte 0 */ + uint32_t DB1:8; /*!< bit: 8..15 Data Byte 1 */ + uint32_t DB2:8; /*!< bit: 16..23 Data Byte 2 */ + uint32_t DB3:8; /*!< bit: 24..31 Data Byte 3 */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_TXBE_DATA_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_TXBE_DATA_OFFSET 0x08 /**< \brief (CAN_TXBE_DATA offset) Tx Buffer Element Data */ +#define CAN_TXBE_DATA_RESETVALUE _U_(0x00000000) /**< \brief (CAN_TXBE_DATA reset_value) Tx Buffer Element Data */ + +#define CAN_TXBE_DATA_DB0_Pos 0 /**< \brief (CAN_TXBE_DATA) Data Byte 0 */ +#define CAN_TXBE_DATA_DB0_Msk (_U_(0xFF) << CAN_TXBE_DATA_DB0_Pos) +#define CAN_TXBE_DATA_DB0(value) (CAN_TXBE_DATA_DB0_Msk & ((value) << CAN_TXBE_DATA_DB0_Pos)) +#define CAN_TXBE_DATA_DB1_Pos 8 /**< \brief (CAN_TXBE_DATA) Data Byte 1 */ +#define CAN_TXBE_DATA_DB1_Msk (_U_(0xFF) << CAN_TXBE_DATA_DB1_Pos) +#define CAN_TXBE_DATA_DB1(value) (CAN_TXBE_DATA_DB1_Msk & ((value) << CAN_TXBE_DATA_DB1_Pos)) +#define CAN_TXBE_DATA_DB2_Pos 16 /**< \brief (CAN_TXBE_DATA) Data Byte 2 */ +#define CAN_TXBE_DATA_DB2_Msk (_U_(0xFF) << CAN_TXBE_DATA_DB2_Pos) +#define CAN_TXBE_DATA_DB2(value) (CAN_TXBE_DATA_DB2_Msk & ((value) << CAN_TXBE_DATA_DB2_Pos)) +#define CAN_TXBE_DATA_DB3_Pos 24 /**< \brief (CAN_TXBE_DATA) Data Byte 3 */ +#define CAN_TXBE_DATA_DB3_Msk (_U_(0xFF) << CAN_TXBE_DATA_DB3_Pos) +#define CAN_TXBE_DATA_DB3(value) (CAN_TXBE_DATA_DB3_Msk & ((value) << CAN_TXBE_DATA_DB3_Pos)) +#define CAN_TXBE_DATA_MASK _U_(0xFFFFFFFF) /**< \brief (CAN_TXBE_DATA) MASK Register */ + +/* -------- CAN_TXEFE_0 : (CAN Offset: 0x00) (R/W 32) Tx Event FIFO Element 0 -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t ID:29; /*!< bit: 0..28 Identifier */ + uint32_t RTR:1; /*!< bit: 29 Remote Transmission Request */ + uint32_t XTD:1; /*!< bit: 30 Extended Indentifier */ + uint32_t ESI:1; /*!< bit: 31 Error State Indicator */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_TXEFE_0_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_TXEFE_0_OFFSET 0x00 /**< \brief (CAN_TXEFE_0 offset) Tx Event FIFO Element 0 */ +#define CAN_TXEFE_0_RESETVALUE _U_(0x00000000) /**< \brief (CAN_TXEFE_0 reset_value) Tx Event FIFO Element 0 */ + +#define CAN_TXEFE_0_ID_Pos 0 /**< \brief (CAN_TXEFE_0) Identifier */ +#define CAN_TXEFE_0_ID_Msk (_U_(0x1FFFFFFF) << CAN_TXEFE_0_ID_Pos) +#define CAN_TXEFE_0_ID(value) (CAN_TXEFE_0_ID_Msk & ((value) << CAN_TXEFE_0_ID_Pos)) +#define CAN_TXEFE_0_RTR_Pos 29 /**< \brief (CAN_TXEFE_0) Remote Transmission Request */ +#define CAN_TXEFE_0_RTR (_U_(0x1) << CAN_TXEFE_0_RTR_Pos) +#define CAN_TXEFE_0_XTD_Pos 30 /**< \brief (CAN_TXEFE_0) Extended Indentifier */ +#define CAN_TXEFE_0_XTD (_U_(0x1) << CAN_TXEFE_0_XTD_Pos) +#define CAN_TXEFE_0_ESI_Pos 31 /**< \brief (CAN_TXEFE_0) Error State Indicator */ +#define CAN_TXEFE_0_ESI (_U_(0x1) << CAN_TXEFE_0_ESI_Pos) +#define CAN_TXEFE_0_MASK _U_(0xFFFFFFFF) /**< \brief (CAN_TXEFE_0) MASK Register */ + +/* -------- CAN_TXEFE_1 : (CAN Offset: 0x04) (R/W 32) Tx Event FIFO Element 1 -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t TXTS:16; /*!< bit: 0..15 Tx Timestamp */ + uint32_t DLC:4; /*!< bit: 16..19 Data Length Code */ + uint32_t BRS:1; /*!< bit: 20 Bit Rate Search */ + uint32_t FDF:1; /*!< bit: 21 FD Format */ + uint32_t ET:2; /*!< bit: 22..23 Event Type */ + uint32_t MM:8; /*!< bit: 24..31 Message Marker */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_TXEFE_1_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_TXEFE_1_OFFSET 0x04 /**< \brief (CAN_TXEFE_1 offset) Tx Event FIFO Element 1 */ +#define CAN_TXEFE_1_RESETVALUE _U_(0x00000000) /**< \brief (CAN_TXEFE_1 reset_value) Tx Event FIFO Element 1 */ + +#define CAN_TXEFE_1_TXTS_Pos 0 /**< \brief (CAN_TXEFE_1) Tx Timestamp */ +#define CAN_TXEFE_1_TXTS_Msk (_U_(0xFFFF) << CAN_TXEFE_1_TXTS_Pos) +#define CAN_TXEFE_1_TXTS(value) (CAN_TXEFE_1_TXTS_Msk & ((value) << CAN_TXEFE_1_TXTS_Pos)) +#define CAN_TXEFE_1_DLC_Pos 16 /**< \brief (CAN_TXEFE_1) Data Length Code */ +#define CAN_TXEFE_1_DLC_Msk (_U_(0xF) << CAN_TXEFE_1_DLC_Pos) +#define CAN_TXEFE_1_DLC(value) (CAN_TXEFE_1_DLC_Msk & ((value) << CAN_TXEFE_1_DLC_Pos)) +#define CAN_TXEFE_1_BRS_Pos 20 /**< \brief (CAN_TXEFE_1) Bit Rate Search */ +#define CAN_TXEFE_1_BRS (_U_(0x1) << CAN_TXEFE_1_BRS_Pos) +#define CAN_TXEFE_1_FDF_Pos 21 /**< \brief (CAN_TXEFE_1) FD Format */ +#define CAN_TXEFE_1_FDF (_U_(0x1) << CAN_TXEFE_1_FDF_Pos) +#define CAN_TXEFE_1_ET_Pos 22 /**< \brief (CAN_TXEFE_1) Event Type */ +#define CAN_TXEFE_1_ET_Msk (_U_(0x3) << CAN_TXEFE_1_ET_Pos) +#define CAN_TXEFE_1_ET(value) (CAN_TXEFE_1_ET_Msk & ((value) << CAN_TXEFE_1_ET_Pos)) +#define CAN_TXEFE_1_ET_TXE_Val _U_(0x1) /**< \brief (CAN_TXEFE_1) Tx event */ +#define CAN_TXEFE_1_ET_TXC_Val _U_(0x2) /**< \brief (CAN_TXEFE_1) Transmission in spite of cancellation */ +#define CAN_TXEFE_1_ET_TXE (CAN_TXEFE_1_ET_TXE_Val << CAN_TXEFE_1_ET_Pos) +#define CAN_TXEFE_1_ET_TXC (CAN_TXEFE_1_ET_TXC_Val << CAN_TXEFE_1_ET_Pos) +#define CAN_TXEFE_1_MM_Pos 24 /**< \brief (CAN_TXEFE_1) Message Marker */ +#define CAN_TXEFE_1_MM_Msk (_U_(0xFF) << CAN_TXEFE_1_MM_Pos) +#define CAN_TXEFE_1_MM(value) (CAN_TXEFE_1_MM_Msk & ((value) << CAN_TXEFE_1_MM_Pos)) +#define CAN_TXEFE_1_MASK _U_(0xFFFFFFFF) /**< \brief (CAN_TXEFE_1) MASK Register */ + +/* -------- CAN_XIDFE_0 : (CAN Offset: 0x00) (R/W 32) Extended Message ID Filter Element 0 -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t EFID1:29; /*!< bit: 0..28 Extended Filter ID 1 */ + uint32_t EFEC:3; /*!< bit: 29..31 Extended Filter Element Configuration */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_XIDFE_0_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_XIDFE_0_OFFSET 0x00 /**< \brief (CAN_XIDFE_0 offset) Extended Message ID Filter Element 0 */ +#define CAN_XIDFE_0_RESETVALUE _U_(0x00000000) /**< \brief (CAN_XIDFE_0 reset_value) Extended Message ID Filter Element 0 */ + +#define CAN_XIDFE_0_EFID1_Pos 0 /**< \brief (CAN_XIDFE_0) Extended Filter ID 1 */ +#define CAN_XIDFE_0_EFID1_Msk (_U_(0x1FFFFFFF) << CAN_XIDFE_0_EFID1_Pos) +#define CAN_XIDFE_0_EFID1(value) (CAN_XIDFE_0_EFID1_Msk & ((value) << CAN_XIDFE_0_EFID1_Pos)) +#define CAN_XIDFE_0_EFEC_Pos 29 /**< \brief (CAN_XIDFE_0) Extended Filter Element Configuration */ +#define CAN_XIDFE_0_EFEC_Msk (_U_(0x7) << CAN_XIDFE_0_EFEC_Pos) +#define CAN_XIDFE_0_EFEC(value) (CAN_XIDFE_0_EFEC_Msk & ((value) << CAN_XIDFE_0_EFEC_Pos)) +#define CAN_XIDFE_0_EFEC_DISABLE_Val _U_(0x0) /**< \brief (CAN_XIDFE_0) Disable filter element */ +#define CAN_XIDFE_0_EFEC_STF0M_Val _U_(0x1) /**< \brief (CAN_XIDFE_0) Store in Rx FIFO 0 if filter match */ +#define CAN_XIDFE_0_EFEC_STF1M_Val _U_(0x2) /**< \brief (CAN_XIDFE_0) Store in Rx FIFO 1 if filter match */ +#define CAN_XIDFE_0_EFEC_REJECT_Val _U_(0x3) /**< \brief (CAN_XIDFE_0) Reject ID if filter match */ +#define CAN_XIDFE_0_EFEC_PRIORITY_Val _U_(0x4) /**< \brief (CAN_XIDFE_0) Set priority if filter match */ +#define CAN_XIDFE_0_EFEC_PRIF0M_Val _U_(0x5) /**< \brief (CAN_XIDFE_0) Set priority and store in FIFO 0 if filter match */ +#define CAN_XIDFE_0_EFEC_PRIF1M_Val _U_(0x6) /**< \brief (CAN_XIDFE_0) Set priority and store in FIFO 1 if filter match */ +#define CAN_XIDFE_0_EFEC_STRXBUF_Val _U_(0x7) /**< \brief (CAN_XIDFE_0) Store into Rx Buffer */ +#define CAN_XIDFE_0_EFEC_DISABLE (CAN_XIDFE_0_EFEC_DISABLE_Val << CAN_XIDFE_0_EFEC_Pos) +#define CAN_XIDFE_0_EFEC_STF0M (CAN_XIDFE_0_EFEC_STF0M_Val << CAN_XIDFE_0_EFEC_Pos) +#define CAN_XIDFE_0_EFEC_STF1M (CAN_XIDFE_0_EFEC_STF1M_Val << CAN_XIDFE_0_EFEC_Pos) +#define CAN_XIDFE_0_EFEC_REJECT (CAN_XIDFE_0_EFEC_REJECT_Val << CAN_XIDFE_0_EFEC_Pos) +#define CAN_XIDFE_0_EFEC_PRIORITY (CAN_XIDFE_0_EFEC_PRIORITY_Val << CAN_XIDFE_0_EFEC_Pos) +#define CAN_XIDFE_0_EFEC_PRIF0M (CAN_XIDFE_0_EFEC_PRIF0M_Val << CAN_XIDFE_0_EFEC_Pos) +#define CAN_XIDFE_0_EFEC_PRIF1M (CAN_XIDFE_0_EFEC_PRIF1M_Val << CAN_XIDFE_0_EFEC_Pos) +#define CAN_XIDFE_0_EFEC_STRXBUF (CAN_XIDFE_0_EFEC_STRXBUF_Val << CAN_XIDFE_0_EFEC_Pos) +#define CAN_XIDFE_0_MASK _U_(0xFFFFFFFF) /**< \brief (CAN_XIDFE_0) MASK Register */ + +/* -------- CAN_XIDFE_1 : (CAN Offset: 0x04) (R/W 32) Extended Message ID Filter Element 1 -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t EFID2:29; /*!< bit: 0..28 Extended Filter ID 2 */ + uint32_t :1; /*!< bit: 29 Reserved */ + uint32_t EFT:2; /*!< bit: 30..31 Extended Filter Type */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_XIDFE_1_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_XIDFE_1_OFFSET 0x04 /**< \brief (CAN_XIDFE_1 offset) Extended Message ID Filter Element 1 */ +#define CAN_XIDFE_1_RESETVALUE _U_(0x00000000) /**< \brief (CAN_XIDFE_1 reset_value) Extended Message ID Filter Element 1 */ + +#define CAN_XIDFE_1_EFID2_Pos 0 /**< \brief (CAN_XIDFE_1) Extended Filter ID 2 */ +#define CAN_XIDFE_1_EFID2_Msk (_U_(0x1FFFFFFF) << CAN_XIDFE_1_EFID2_Pos) +#define CAN_XIDFE_1_EFID2(value) (CAN_XIDFE_1_EFID2_Msk & ((value) << CAN_XIDFE_1_EFID2_Pos)) +#define CAN_XIDFE_1_EFT_Pos 30 /**< \brief (CAN_XIDFE_1) Extended Filter Type */ +#define CAN_XIDFE_1_EFT_Msk (_U_(0x3) << CAN_XIDFE_1_EFT_Pos) +#define CAN_XIDFE_1_EFT(value) (CAN_XIDFE_1_EFT_Msk & ((value) << CAN_XIDFE_1_EFT_Pos)) +#define CAN_XIDFE_1_EFT_RANGEM_Val _U_(0x0) /**< \brief (CAN_XIDFE_1) Range filter from EFID1 to EFID2 */ +#define CAN_XIDFE_1_EFT_DUAL_Val _U_(0x1) /**< \brief (CAN_XIDFE_1) Dual ID filter for EFID1 or EFID2 */ +#define CAN_XIDFE_1_EFT_CLASSIC_Val _U_(0x2) /**< \brief (CAN_XIDFE_1) Classic filter */ +#define CAN_XIDFE_1_EFT_RANGE_Val _U_(0x3) /**< \brief (CAN_XIDFE_1) Range filter from EFID1 to EFID2 with no XIDAM mask */ +#define CAN_XIDFE_1_EFT_RANGEM (CAN_XIDFE_1_EFT_RANGEM_Val << CAN_XIDFE_1_EFT_Pos) +#define CAN_XIDFE_1_EFT_DUAL (CAN_XIDFE_1_EFT_DUAL_Val << CAN_XIDFE_1_EFT_Pos) +#define CAN_XIDFE_1_EFT_CLASSIC (CAN_XIDFE_1_EFT_CLASSIC_Val << CAN_XIDFE_1_EFT_Pos) +#define CAN_XIDFE_1_EFT_RANGE (CAN_XIDFE_1_EFT_RANGE_Val << CAN_XIDFE_1_EFT_Pos) +#define CAN_XIDFE_1_MASK _U_(0xDFFFFFFF) /**< \brief (CAN_XIDFE_1) MASK Register */ + +/** \brief CAN APB hardware registers */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef struct { + __I CAN_CREL_Type CREL; /**< \brief Offset: 0x00 (R/ 32) Core Release */ + __I CAN_ENDN_Type ENDN; /**< \brief Offset: 0x04 (R/ 32) Endian */ + __IO CAN_MRCFG_Type MRCFG; /**< \brief Offset: 0x08 (R/W 32) Message RAM Configuration */ + __IO CAN_DBTP_Type DBTP; /**< \brief Offset: 0x0C (R/W 32) Fast Bit Timing and Prescaler */ + __IO CAN_TEST_Type TEST; /**< \brief Offset: 0x10 (R/W 32) Test */ + __IO CAN_RWD_Type RWD; /**< \brief Offset: 0x14 (R/W 32) RAM Watchdog */ + __IO CAN_CCCR_Type CCCR; /**< \brief Offset: 0x18 (R/W 32) CC Control */ + __IO CAN_NBTP_Type NBTP; /**< \brief Offset: 0x1C (R/W 32) Nominal Bit Timing and Prescaler */ + __IO CAN_TSCC_Type TSCC; /**< \brief Offset: 0x20 (R/W 32) Timestamp Counter Configuration */ + __I CAN_TSCV_Type TSCV; /**< \brief Offset: 0x24 (R/ 32) Timestamp Counter Value */ + __IO CAN_TOCC_Type TOCC; /**< \brief Offset: 0x28 (R/W 32) Timeout Counter Configuration */ + __IO CAN_TOCV_Type TOCV; /**< \brief Offset: 0x2C (R/W 32) Timeout Counter Value */ + RoReg8 Reserved1[0x10]; + __I CAN_ECR_Type ECR; /**< \brief Offset: 0x40 (R/ 32) Error Counter */ + __I CAN_PSR_Type PSR; /**< \brief Offset: 0x44 (R/ 32) Protocol Status */ + __IO CAN_TDCR_Type TDCR; /**< \brief Offset: 0x48 (R/W 32) Extended ID Filter Configuration */ + RoReg8 Reserved2[0x4]; + __IO CAN_IR_Type IR; /**< \brief Offset: 0x50 (R/W 32) Interrupt */ + __IO CAN_IE_Type IE; /**< \brief Offset: 0x54 (R/W 32) Interrupt Enable */ + __IO CAN_ILS_Type ILS; /**< \brief Offset: 0x58 (R/W 32) Interrupt Line Select */ + __IO CAN_ILE_Type ILE; /**< \brief Offset: 0x5C (R/W 32) Interrupt Line Enable */ + RoReg8 Reserved3[0x20]; + __IO CAN_GFC_Type GFC; /**< \brief Offset: 0x80 (R/W 32) Global Filter Configuration */ + __IO CAN_SIDFC_Type SIDFC; /**< \brief Offset: 0x84 (R/W 32) Standard ID Filter Configuration */ + __IO CAN_XIDFC_Type XIDFC; /**< \brief Offset: 0x88 (R/W 32) Extended ID Filter Configuration */ + RoReg8 Reserved4[0x4]; + __IO CAN_XIDAM_Type XIDAM; /**< \brief Offset: 0x90 (R/W 32) Extended ID AND Mask */ + __I CAN_HPMS_Type HPMS; /**< \brief Offset: 0x94 (R/ 32) High Priority Message Status */ + __IO CAN_NDAT1_Type NDAT1; /**< \brief Offset: 0x98 (R/W 32) New Data 1 */ + __IO CAN_NDAT2_Type NDAT2; /**< \brief Offset: 0x9C (R/W 32) New Data 2 */ + __IO CAN_RXF0C_Type RXF0C; /**< \brief Offset: 0xA0 (R/W 32) Rx FIFO 0 Configuration */ + __I CAN_RXF0S_Type RXF0S; /**< \brief Offset: 0xA4 (R/ 32) Rx FIFO 0 Status */ + __IO CAN_RXF0A_Type RXF0A; /**< \brief Offset: 0xA8 (R/W 32) Rx FIFO 0 Acknowledge */ + __IO CAN_RXBC_Type RXBC; /**< \brief Offset: 0xAC (R/W 32) Rx Buffer Configuration */ + __IO CAN_RXF1C_Type RXF1C; /**< \brief Offset: 0xB0 (R/W 32) Rx FIFO 1 Configuration */ + __I CAN_RXF1S_Type RXF1S; /**< \brief Offset: 0xB4 (R/ 32) Rx FIFO 1 Status */ + __IO CAN_RXF1A_Type RXF1A; /**< \brief Offset: 0xB8 (R/W 32) Rx FIFO 1 Acknowledge */ + __IO CAN_RXESC_Type RXESC; /**< \brief Offset: 0xBC (R/W 32) Rx Buffer / FIFO Element Size Configuration */ + __IO CAN_TXBC_Type TXBC; /**< \brief Offset: 0xC0 (R/W 32) Tx Buffer Configuration */ + __I CAN_TXFQS_Type TXFQS; /**< \brief Offset: 0xC4 (R/ 32) Tx FIFO / Queue Status */ + __IO CAN_TXESC_Type TXESC; /**< \brief Offset: 0xC8 (R/W 32) Tx Buffer Element Size Configuration */ + __I CAN_TXBRP_Type TXBRP; /**< \brief Offset: 0xCC (R/ 32) Tx Buffer Request Pending */ + __IO CAN_TXBAR_Type TXBAR; /**< \brief Offset: 0xD0 (R/W 32) Tx Buffer Add Request */ + __IO CAN_TXBCR_Type TXBCR; /**< \brief Offset: 0xD4 (R/W 32) Tx Buffer Cancellation Request */ + __I CAN_TXBTO_Type TXBTO; /**< \brief Offset: 0xD8 (R/ 32) Tx Buffer Transmission Occurred */ + __I CAN_TXBCF_Type TXBCF; /**< \brief Offset: 0xDC (R/ 32) Tx Buffer Cancellation Finished */ + __IO CAN_TXBTIE_Type TXBTIE; /**< \brief Offset: 0xE0 (R/W 32) Tx Buffer Transmission Interrupt Enable */ + __IO CAN_TXBCIE_Type TXBCIE; /**< \brief Offset: 0xE4 (R/W 32) Tx Buffer Cancellation Finished Interrupt Enable */ + RoReg8 Reserved5[0x8]; + __IO CAN_TXEFC_Type TXEFC; /**< \brief Offset: 0xF0 (R/W 32) Tx Event FIFO Configuration */ + __I CAN_TXEFS_Type TXEFS; /**< \brief Offset: 0xF4 (R/ 32) Tx Event FIFO Status */ + __IO CAN_TXEFA_Type TXEFA; /**< \brief Offset: 0xF8 (R/W 32) Tx Event FIFO Acknowledge */ +} Can; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/** \brief CAN Mram_rxbe hardware registers */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef struct { + __IO CAN_RXBE_0_Type RXBE_0; /**< \brief Offset: 0x00 (R/W 32) Rx Buffer Element 0 */ + __IO CAN_RXBE_1_Type RXBE_1; /**< \brief Offset: 0x04 (R/W 32) Rx Buffer Element 1 */ + __IO CAN_RXBE_DATA_Type RXBE_DATA[16]; /**< \brief Offset: 0x08 (R/W 32) Rx Buffer Element Data */ +} CanMramRxbe +#ifdef __GNUC__ + __attribute__ ((aligned (4))) +#endif +; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/** \brief CAN Mram_rxf0e hardware registers */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef struct { + __IO CAN_RXF0E_0_Type RXF0E_0; /**< \brief Offset: 0x00 (R/W 32) Rx FIFO 0 Element 0 */ + __IO CAN_RXF0E_1_Type RXF0E_1; /**< \brief Offset: 0x04 (R/W 32) Rx FIFO 0 Element 1 */ + __IO CAN_RXF0E_DATA_Type RXF0E_DATA[16]; /**< \brief Offset: 0x08 (R/W 32) Rx FIFO 0 Element Data */ +} CanMramRxf0e +#ifdef __GNUC__ + __attribute__ ((aligned (4))) +#endif +; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/** \brief CAN Mram_rxf1e hardware registers */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef struct { + __IO CAN_RXF1E_0_Type RXF1E_0; /**< \brief Offset: 0x00 (R/W 32) Rx FIFO 1 Element 0 */ + __IO CAN_RXF1E_1_Type RXF1E_1; /**< \brief Offset: 0x04 (R/W 32) Rx FIFO 1 Element 1 */ + __IO CAN_RXF1E_DATA_Type RXF1E_DATA[16]; /**< \brief Offset: 0x08 (R/W 32) Rx FIFO 1 Element Data */ +} CanMramRxf1e +#ifdef __GNUC__ + __attribute__ ((aligned (4))) +#endif +; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/** \brief CAN Mram_sidfe hardware registers */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef struct { + __IO CAN_SIDFE_0_Type SIDFE_0; /**< \brief Offset: 0x00 (R/W 32) Standard Message ID Filter Element */ +} CanMramSidfe +#ifdef __GNUC__ + __attribute__ ((aligned (4))) +#endif +; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/** \brief CAN Mram_txbe hardware registers */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef struct { + __IO CAN_TXBE_0_Type TXBE_0; /**< \brief Offset: 0x00 (R/W 32) Tx Buffer Element 0 */ + __IO CAN_TXBE_1_Type TXBE_1; /**< \brief Offset: 0x04 (R/W 32) Tx Buffer Element 1 */ + __IO CAN_TXBE_DATA_Type TXBE_DATA[16]; /**< \brief Offset: 0x08 (R/W 32) Tx Buffer Element Data */ +} CanMramTxbe +#ifdef __GNUC__ + __attribute__ ((aligned (4))) +#endif +; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/** \brief CAN Mram_txefe hardware registers */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef struct { + __IO CAN_TXEFE_0_Type TXEFE_0; /**< \brief Offset: 0x00 (R/W 32) Tx Event FIFO Element 0 */ + __IO CAN_TXEFE_1_Type TXEFE_1; /**< \brief Offset: 0x04 (R/W 32) Tx Event FIFO Element 1 */ +} CanMramTxefe +#ifdef __GNUC__ + __attribute__ ((aligned (4))) +#endif +; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/** \brief CAN Mram_xifde hardware registers */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef struct { + __IO CAN_XIDFE_0_Type XIDFE_0; /**< \brief Offset: 0x00 (R/W 32) Extended Message ID Filter Element 0 */ + __IO CAN_XIDFE_1_Type XIDFE_1; /**< \brief Offset: 0x04 (R/W 32) Extended Message ID Filter Element 1 */ +} CanMramXifde +#ifdef __GNUC__ + __attribute__ ((aligned (4))) +#endif +; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define SECTION_CAN_MRAM_RXBE +#define SECTION_CAN_MRAM_RXF0E +#define SECTION_CAN_MRAM_RXF1E +#define SECTION_CAN_MRAM_SIDFE +#define SECTION_CAN_MRAM_TXBE +#define SECTION_CAN_MRAM_TXEFE +#define SECTION_CAN_MRAM_XIFDE + +/*@}*/ + +#endif /* _SAME54_CAN_COMPONENT_ */ diff --git a/arch/arm/SAME54/SAME54A/mcu/inc/component/ccl.h b/arch/arm/SAME54/SAME54A/mcu/inc/component/ccl.h index 5175d3a5..b5dbb9ab 100644 --- a/arch/arm/SAME54/SAME54A/mcu/inc/component/ccl.h +++ b/arch/arm/SAME54/SAME54A/mcu/inc/component/ccl.h @@ -1,217 +1,228 @@ -/** - * \brief Component description for CCL - * - * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries. - * - * Subject to your compliance with these terms, you may use Microchip software and any derivatives - * exclusively with Microchip products. It is your responsibility to comply with third party license - * terms applicable to your use of third party software (including open source software) that may - * accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, - * APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND - * FITNESS FOR A PARTICULAR PURPOSE. - * - * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF - * MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT - * EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - */ - -/* file generated from device description version 2020-03-12T17:27:04Z */ -#ifndef _SAME54_CCL_COMPONENT_H_ -#define _SAME54_CCL_COMPONENT_H_ - -/* ************************************************************************** */ -/* SOFTWARE API DEFINITION FOR CCL */ -/* ************************************************************************** */ - -/* -------- CCL_CTRL : (CCL Offset: 0x00) (R/W 8) Control -------- */ -#define CCL_CTRL_RESETVALUE _U_(0x00) /**< (CCL_CTRL) Control Reset Value */ - -#define CCL_CTRL_SWRST_Pos _U_(0) /**< (CCL_CTRL) Software Reset Position */ -#define CCL_CTRL_SWRST_Msk (_U_(0x1) << CCL_CTRL_SWRST_Pos) /**< (CCL_CTRL) Software Reset Mask */ -#define CCL_CTRL_SWRST(value) (CCL_CTRL_SWRST_Msk & ((value) << CCL_CTRL_SWRST_Pos)) -#define CCL_CTRL_SWRST_DISABLE_Val _U_(0x0) /**< (CCL_CTRL) The peripheral is not reset */ -#define CCL_CTRL_SWRST_ENABLE_Val _U_(0x1) /**< (CCL_CTRL) The peripheral is reset */ -#define CCL_CTRL_SWRST_DISABLE (CCL_CTRL_SWRST_DISABLE_Val << CCL_CTRL_SWRST_Pos) /**< (CCL_CTRL) The peripheral is not reset Position */ -#define CCL_CTRL_SWRST_ENABLE (CCL_CTRL_SWRST_ENABLE_Val << CCL_CTRL_SWRST_Pos) /**< (CCL_CTRL) The peripheral is reset Position */ -#define CCL_CTRL_ENABLE_Pos _U_(1) /**< (CCL_CTRL) Enable Position */ -#define CCL_CTRL_ENABLE_Msk (_U_(0x1) << CCL_CTRL_ENABLE_Pos) /**< (CCL_CTRL) Enable Mask */ -#define CCL_CTRL_ENABLE(value) (CCL_CTRL_ENABLE_Msk & ((value) << CCL_CTRL_ENABLE_Pos)) -#define CCL_CTRL_ENABLE_DISABLE_Val _U_(0x0) /**< (CCL_CTRL) The peripheral is disabled */ -#define CCL_CTRL_ENABLE_ENABLE_Val _U_(0x1) /**< (CCL_CTRL) The peripheral is enabled */ -#define CCL_CTRL_ENABLE_DISABLE (CCL_CTRL_ENABLE_DISABLE_Val << CCL_CTRL_ENABLE_Pos) /**< (CCL_CTRL) The peripheral is disabled Position */ -#define CCL_CTRL_ENABLE_ENABLE (CCL_CTRL_ENABLE_ENABLE_Val << CCL_CTRL_ENABLE_Pos) /**< (CCL_CTRL) The peripheral is enabled Position */ -#define CCL_CTRL_RUNSTDBY_Pos _U_(6) /**< (CCL_CTRL) Run in Standby Position */ -#define CCL_CTRL_RUNSTDBY_Msk (_U_(0x1) << CCL_CTRL_RUNSTDBY_Pos) /**< (CCL_CTRL) Run in Standby Mask */ -#define CCL_CTRL_RUNSTDBY(value) (CCL_CTRL_RUNSTDBY_Msk & ((value) << CCL_CTRL_RUNSTDBY_Pos)) -#define CCL_CTRL_RUNSTDBY_DISABLE_Val _U_(0x0) /**< (CCL_CTRL) Generic clock is not required in standby sleep mode */ -#define CCL_CTRL_RUNSTDBY_ENABLE_Val _U_(0x1) /**< (CCL_CTRL) Generic clock is required in standby sleep mode */ -#define CCL_CTRL_RUNSTDBY_DISABLE (CCL_CTRL_RUNSTDBY_DISABLE_Val << CCL_CTRL_RUNSTDBY_Pos) /**< (CCL_CTRL) Generic clock is not required in standby sleep mode Position */ -#define CCL_CTRL_RUNSTDBY_ENABLE (CCL_CTRL_RUNSTDBY_ENABLE_Val << CCL_CTRL_RUNSTDBY_Pos) /**< (CCL_CTRL) Generic clock is required in standby sleep mode Position */ -#define CCL_CTRL_Msk _U_(0x43) /**< (CCL_CTRL) Register Mask */ - - -/* -------- CCL_SEQCTRL : (CCL Offset: 0x04) (R/W 8) SEQ Control x -------- */ -#define CCL_SEQCTRL_RESETVALUE _U_(0x00) /**< (CCL_SEQCTRL) SEQ Control x Reset Value */ - -#define CCL_SEQCTRL_SEQSEL_Pos _U_(0) /**< (CCL_SEQCTRL) Sequential Selection Position */ -#define CCL_SEQCTRL_SEQSEL_Msk (_U_(0xF) << CCL_SEQCTRL_SEQSEL_Pos) /**< (CCL_SEQCTRL) Sequential Selection Mask */ -#define CCL_SEQCTRL_SEQSEL(value) (CCL_SEQCTRL_SEQSEL_Msk & ((value) << CCL_SEQCTRL_SEQSEL_Pos)) -#define CCL_SEQCTRL_SEQSEL_DISABLE_Val _U_(0x0) /**< (CCL_SEQCTRL) Sequential logic is disabled */ -#define CCL_SEQCTRL_SEQSEL_DFF_Val _U_(0x1) /**< (CCL_SEQCTRL) D flip flop */ -#define CCL_SEQCTRL_SEQSEL_JK_Val _U_(0x2) /**< (CCL_SEQCTRL) JK flip flop */ -#define CCL_SEQCTRL_SEQSEL_LATCH_Val _U_(0x3) /**< (CCL_SEQCTRL) D latch */ -#define CCL_SEQCTRL_SEQSEL_RS_Val _U_(0x4) /**< (CCL_SEQCTRL) RS latch */ -#define CCL_SEQCTRL_SEQSEL_DISABLE (CCL_SEQCTRL_SEQSEL_DISABLE_Val << CCL_SEQCTRL_SEQSEL_Pos) /**< (CCL_SEQCTRL) Sequential logic is disabled Position */ -#define CCL_SEQCTRL_SEQSEL_DFF (CCL_SEQCTRL_SEQSEL_DFF_Val << CCL_SEQCTRL_SEQSEL_Pos) /**< (CCL_SEQCTRL) D flip flop Position */ -#define CCL_SEQCTRL_SEQSEL_JK (CCL_SEQCTRL_SEQSEL_JK_Val << CCL_SEQCTRL_SEQSEL_Pos) /**< (CCL_SEQCTRL) JK flip flop Position */ -#define CCL_SEQCTRL_SEQSEL_LATCH (CCL_SEQCTRL_SEQSEL_LATCH_Val << CCL_SEQCTRL_SEQSEL_Pos) /**< (CCL_SEQCTRL) D latch Position */ -#define CCL_SEQCTRL_SEQSEL_RS (CCL_SEQCTRL_SEQSEL_RS_Val << CCL_SEQCTRL_SEQSEL_Pos) /**< (CCL_SEQCTRL) RS latch Position */ -#define CCL_SEQCTRL_Msk _U_(0x0F) /**< (CCL_SEQCTRL) Register Mask */ - - -/* -------- CCL_LUTCTRL : (CCL Offset: 0x08) (R/W 32) LUT Control x -------- */ -#define CCL_LUTCTRL_RESETVALUE _U_(0x00) /**< (CCL_LUTCTRL) LUT Control x Reset Value */ - -#define CCL_LUTCTRL_ENABLE_Pos _U_(1) /**< (CCL_LUTCTRL) LUT Enable Position */ -#define CCL_LUTCTRL_ENABLE_Msk (_U_(0x1) << CCL_LUTCTRL_ENABLE_Pos) /**< (CCL_LUTCTRL) LUT Enable Mask */ -#define CCL_LUTCTRL_ENABLE(value) (CCL_LUTCTRL_ENABLE_Msk & ((value) << CCL_LUTCTRL_ENABLE_Pos)) -#define CCL_LUTCTRL_ENABLE_DISABLE_Val _U_(0x0) /**< (CCL_LUTCTRL) LUT block is disabled */ -#define CCL_LUTCTRL_ENABLE_ENABLE_Val _U_(0x1) /**< (CCL_LUTCTRL) LUT block is enabled */ -#define CCL_LUTCTRL_ENABLE_DISABLE (CCL_LUTCTRL_ENABLE_DISABLE_Val << CCL_LUTCTRL_ENABLE_Pos) /**< (CCL_LUTCTRL) LUT block is disabled Position */ -#define CCL_LUTCTRL_ENABLE_ENABLE (CCL_LUTCTRL_ENABLE_ENABLE_Val << CCL_LUTCTRL_ENABLE_Pos) /**< (CCL_LUTCTRL) LUT block is enabled Position */ -#define CCL_LUTCTRL_FILTSEL_Pos _U_(4) /**< (CCL_LUTCTRL) Filter Selection Position */ -#define CCL_LUTCTRL_FILTSEL_Msk (_U_(0x3) << CCL_LUTCTRL_FILTSEL_Pos) /**< (CCL_LUTCTRL) Filter Selection Mask */ -#define CCL_LUTCTRL_FILTSEL(value) (CCL_LUTCTRL_FILTSEL_Msk & ((value) << CCL_LUTCTRL_FILTSEL_Pos)) -#define CCL_LUTCTRL_FILTSEL_DISABLE_Val _U_(0x0) /**< (CCL_LUTCTRL) Filter disabled */ -#define CCL_LUTCTRL_FILTSEL_SYNCH_Val _U_(0x1) /**< (CCL_LUTCTRL) Synchronizer enabled */ -#define CCL_LUTCTRL_FILTSEL_FILTER_Val _U_(0x2) /**< (CCL_LUTCTRL) Filter enabled */ -#define CCL_LUTCTRL_FILTSEL_DISABLE (CCL_LUTCTRL_FILTSEL_DISABLE_Val << CCL_LUTCTRL_FILTSEL_Pos) /**< (CCL_LUTCTRL) Filter disabled Position */ -#define CCL_LUTCTRL_FILTSEL_SYNCH (CCL_LUTCTRL_FILTSEL_SYNCH_Val << CCL_LUTCTRL_FILTSEL_Pos) /**< (CCL_LUTCTRL) Synchronizer enabled Position */ -#define CCL_LUTCTRL_FILTSEL_FILTER (CCL_LUTCTRL_FILTSEL_FILTER_Val << CCL_LUTCTRL_FILTSEL_Pos) /**< (CCL_LUTCTRL) Filter enabled Position */ -#define CCL_LUTCTRL_EDGESEL_Pos _U_(7) /**< (CCL_LUTCTRL) Edge Selection Position */ -#define CCL_LUTCTRL_EDGESEL_Msk (_U_(0x1) << CCL_LUTCTRL_EDGESEL_Pos) /**< (CCL_LUTCTRL) Edge Selection Mask */ -#define CCL_LUTCTRL_EDGESEL(value) (CCL_LUTCTRL_EDGESEL_Msk & ((value) << CCL_LUTCTRL_EDGESEL_Pos)) -#define CCL_LUTCTRL_EDGESEL_DISABLE_Val _U_(0x0) /**< (CCL_LUTCTRL) Edge detector is disabled */ -#define CCL_LUTCTRL_EDGESEL_ENABLE_Val _U_(0x1) /**< (CCL_LUTCTRL) Edge detector is enabled */ -#define CCL_LUTCTRL_EDGESEL_DISABLE (CCL_LUTCTRL_EDGESEL_DISABLE_Val << CCL_LUTCTRL_EDGESEL_Pos) /**< (CCL_LUTCTRL) Edge detector is disabled Position */ -#define CCL_LUTCTRL_EDGESEL_ENABLE (CCL_LUTCTRL_EDGESEL_ENABLE_Val << CCL_LUTCTRL_EDGESEL_Pos) /**< (CCL_LUTCTRL) Edge detector is enabled Position */ -#define CCL_LUTCTRL_INSEL0_Pos _U_(8) /**< (CCL_LUTCTRL) Input Selection 0 Position */ -#define CCL_LUTCTRL_INSEL0_Msk (_U_(0xF) << CCL_LUTCTRL_INSEL0_Pos) /**< (CCL_LUTCTRL) Input Selection 0 Mask */ -#define CCL_LUTCTRL_INSEL0(value) (CCL_LUTCTRL_INSEL0_Msk & ((value) << CCL_LUTCTRL_INSEL0_Pos)) -#define CCL_LUTCTRL_INSEL0_MASK_Val _U_(0x0) /**< (CCL_LUTCTRL) Masked input */ -#define CCL_LUTCTRL_INSEL0_FEEDBACK_Val _U_(0x1) /**< (CCL_LUTCTRL) Feedback input source */ -#define CCL_LUTCTRL_INSEL0_LINK_Val _U_(0x2) /**< (CCL_LUTCTRL) Linked LUT input source */ -#define CCL_LUTCTRL_INSEL0_EVENT_Val _U_(0x3) /**< (CCL_LUTCTRL) Event input source */ -#define CCL_LUTCTRL_INSEL0_IO_Val _U_(0x4) /**< (CCL_LUTCTRL) I/O pin input source */ -#define CCL_LUTCTRL_INSEL0_AC_Val _U_(0x5) /**< (CCL_LUTCTRL) AC input source */ -#define CCL_LUTCTRL_INSEL0_TC_Val _U_(0x6) /**< (CCL_LUTCTRL) TC input source */ -#define CCL_LUTCTRL_INSEL0_ALTTC_Val _U_(0x7) /**< (CCL_LUTCTRL) Alternate TC input source */ -#define CCL_LUTCTRL_INSEL0_TCC_Val _U_(0x8) /**< (CCL_LUTCTRL) TCC input source */ -#define CCL_LUTCTRL_INSEL0_SERCOM_Val _U_(0x9) /**< (CCL_LUTCTRL) SERCOM input source */ -#define CCL_LUTCTRL_INSEL0_MASK (CCL_LUTCTRL_INSEL0_MASK_Val << CCL_LUTCTRL_INSEL0_Pos) /**< (CCL_LUTCTRL) Masked input Position */ -#define CCL_LUTCTRL_INSEL0_FEEDBACK (CCL_LUTCTRL_INSEL0_FEEDBACK_Val << CCL_LUTCTRL_INSEL0_Pos) /**< (CCL_LUTCTRL) Feedback input source Position */ -#define CCL_LUTCTRL_INSEL0_LINK (CCL_LUTCTRL_INSEL0_LINK_Val << CCL_LUTCTRL_INSEL0_Pos) /**< (CCL_LUTCTRL) Linked LUT input source Position */ -#define CCL_LUTCTRL_INSEL0_EVENT (CCL_LUTCTRL_INSEL0_EVENT_Val << CCL_LUTCTRL_INSEL0_Pos) /**< (CCL_LUTCTRL) Event input source Position */ -#define CCL_LUTCTRL_INSEL0_IO (CCL_LUTCTRL_INSEL0_IO_Val << CCL_LUTCTRL_INSEL0_Pos) /**< (CCL_LUTCTRL) I/O pin input source Position */ -#define CCL_LUTCTRL_INSEL0_AC (CCL_LUTCTRL_INSEL0_AC_Val << CCL_LUTCTRL_INSEL0_Pos) /**< (CCL_LUTCTRL) AC input source Position */ -#define CCL_LUTCTRL_INSEL0_TC (CCL_LUTCTRL_INSEL0_TC_Val << CCL_LUTCTRL_INSEL0_Pos) /**< (CCL_LUTCTRL) TC input source Position */ -#define CCL_LUTCTRL_INSEL0_ALTTC (CCL_LUTCTRL_INSEL0_ALTTC_Val << CCL_LUTCTRL_INSEL0_Pos) /**< (CCL_LUTCTRL) Alternate TC input source Position */ -#define CCL_LUTCTRL_INSEL0_TCC (CCL_LUTCTRL_INSEL0_TCC_Val << CCL_LUTCTRL_INSEL0_Pos) /**< (CCL_LUTCTRL) TCC input source Position */ -#define CCL_LUTCTRL_INSEL0_SERCOM (CCL_LUTCTRL_INSEL0_SERCOM_Val << CCL_LUTCTRL_INSEL0_Pos) /**< (CCL_LUTCTRL) SERCOM input source Position */ -#define CCL_LUTCTRL_INSEL1_Pos _U_(12) /**< (CCL_LUTCTRL) Input Selection 1 Position */ -#define CCL_LUTCTRL_INSEL1_Msk (_U_(0xF) << CCL_LUTCTRL_INSEL1_Pos) /**< (CCL_LUTCTRL) Input Selection 1 Mask */ -#define CCL_LUTCTRL_INSEL1(value) (CCL_LUTCTRL_INSEL1_Msk & ((value) << CCL_LUTCTRL_INSEL1_Pos)) -#define CCL_LUTCTRL_INSEL1_MASK_Val _U_(0x0) /**< (CCL_LUTCTRL) Masked input */ -#define CCL_LUTCTRL_INSEL1_FEEDBACK_Val _U_(0x1) /**< (CCL_LUTCTRL) Feedback input source */ -#define CCL_LUTCTRL_INSEL1_LINK_Val _U_(0x2) /**< (CCL_LUTCTRL) Linked LUT input source */ -#define CCL_LUTCTRL_INSEL1_EVENT_Val _U_(0x3) /**< (CCL_LUTCTRL) Event input source */ -#define CCL_LUTCTRL_INSEL1_IO_Val _U_(0x4) /**< (CCL_LUTCTRL) I/O pin input source */ -#define CCL_LUTCTRL_INSEL1_AC_Val _U_(0x5) /**< (CCL_LUTCTRL) AC input source */ -#define CCL_LUTCTRL_INSEL1_TC_Val _U_(0x6) /**< (CCL_LUTCTRL) TC input source */ -#define CCL_LUTCTRL_INSEL1_ALTTC_Val _U_(0x7) /**< (CCL_LUTCTRL) Alternate TC input source */ -#define CCL_LUTCTRL_INSEL1_TCC_Val _U_(0x8) /**< (CCL_LUTCTRL) TCC input source */ -#define CCL_LUTCTRL_INSEL1_SERCOM_Val _U_(0x9) /**< (CCL_LUTCTRL) SERCOM input source */ -#define CCL_LUTCTRL_INSEL1_MASK (CCL_LUTCTRL_INSEL1_MASK_Val << CCL_LUTCTRL_INSEL1_Pos) /**< (CCL_LUTCTRL) Masked input Position */ -#define CCL_LUTCTRL_INSEL1_FEEDBACK (CCL_LUTCTRL_INSEL1_FEEDBACK_Val << CCL_LUTCTRL_INSEL1_Pos) /**< (CCL_LUTCTRL) Feedback input source Position */ -#define CCL_LUTCTRL_INSEL1_LINK (CCL_LUTCTRL_INSEL1_LINK_Val << CCL_LUTCTRL_INSEL1_Pos) /**< (CCL_LUTCTRL) Linked LUT input source Position */ -#define CCL_LUTCTRL_INSEL1_EVENT (CCL_LUTCTRL_INSEL1_EVENT_Val << CCL_LUTCTRL_INSEL1_Pos) /**< (CCL_LUTCTRL) Event input source Position */ -#define CCL_LUTCTRL_INSEL1_IO (CCL_LUTCTRL_INSEL1_IO_Val << CCL_LUTCTRL_INSEL1_Pos) /**< (CCL_LUTCTRL) I/O pin input source Position */ -#define CCL_LUTCTRL_INSEL1_AC (CCL_LUTCTRL_INSEL1_AC_Val << CCL_LUTCTRL_INSEL1_Pos) /**< (CCL_LUTCTRL) AC input source Position */ -#define CCL_LUTCTRL_INSEL1_TC (CCL_LUTCTRL_INSEL1_TC_Val << CCL_LUTCTRL_INSEL1_Pos) /**< (CCL_LUTCTRL) TC input source Position */ -#define CCL_LUTCTRL_INSEL1_ALTTC (CCL_LUTCTRL_INSEL1_ALTTC_Val << CCL_LUTCTRL_INSEL1_Pos) /**< (CCL_LUTCTRL) Alternate TC input source Position */ -#define CCL_LUTCTRL_INSEL1_TCC (CCL_LUTCTRL_INSEL1_TCC_Val << CCL_LUTCTRL_INSEL1_Pos) /**< (CCL_LUTCTRL) TCC input source Position */ -#define CCL_LUTCTRL_INSEL1_SERCOM (CCL_LUTCTRL_INSEL1_SERCOM_Val << CCL_LUTCTRL_INSEL1_Pos) /**< (CCL_LUTCTRL) SERCOM input source Position */ -#define CCL_LUTCTRL_INSEL2_Pos _U_(16) /**< (CCL_LUTCTRL) Input Selection 2 Position */ -#define CCL_LUTCTRL_INSEL2_Msk (_U_(0xF) << CCL_LUTCTRL_INSEL2_Pos) /**< (CCL_LUTCTRL) Input Selection 2 Mask */ -#define CCL_LUTCTRL_INSEL2(value) (CCL_LUTCTRL_INSEL2_Msk & ((value) << CCL_LUTCTRL_INSEL2_Pos)) -#define CCL_LUTCTRL_INSEL2_MASK_Val _U_(0x0) /**< (CCL_LUTCTRL) Masked input */ -#define CCL_LUTCTRL_INSEL2_FEEDBACK_Val _U_(0x1) /**< (CCL_LUTCTRL) Feedback input source */ -#define CCL_LUTCTRL_INSEL2_LINK_Val _U_(0x2) /**< (CCL_LUTCTRL) Linked LUT input source */ -#define CCL_LUTCTRL_INSEL2_EVENT_Val _U_(0x3) /**< (CCL_LUTCTRL) Event input source */ -#define CCL_LUTCTRL_INSEL2_IO_Val _U_(0x4) /**< (CCL_LUTCTRL) I/O pin input source */ -#define CCL_LUTCTRL_INSEL2_AC_Val _U_(0x5) /**< (CCL_LUTCTRL) AC input source */ -#define CCL_LUTCTRL_INSEL2_TC_Val _U_(0x6) /**< (CCL_LUTCTRL) TC input source */ -#define CCL_LUTCTRL_INSEL2_ALTTC_Val _U_(0x7) /**< (CCL_LUTCTRL) Alternate TC input source */ -#define CCL_LUTCTRL_INSEL2_TCC_Val _U_(0x8) /**< (CCL_LUTCTRL) TCC input source */ -#define CCL_LUTCTRL_INSEL2_SERCOM_Val _U_(0x9) /**< (CCL_LUTCTRL) SERCOM input source */ -#define CCL_LUTCTRL_INSEL2_MASK (CCL_LUTCTRL_INSEL2_MASK_Val << CCL_LUTCTRL_INSEL2_Pos) /**< (CCL_LUTCTRL) Masked input Position */ -#define CCL_LUTCTRL_INSEL2_FEEDBACK (CCL_LUTCTRL_INSEL2_FEEDBACK_Val << CCL_LUTCTRL_INSEL2_Pos) /**< (CCL_LUTCTRL) Feedback input source Position */ -#define CCL_LUTCTRL_INSEL2_LINK (CCL_LUTCTRL_INSEL2_LINK_Val << CCL_LUTCTRL_INSEL2_Pos) /**< (CCL_LUTCTRL) Linked LUT input source Position */ -#define CCL_LUTCTRL_INSEL2_EVENT (CCL_LUTCTRL_INSEL2_EVENT_Val << CCL_LUTCTRL_INSEL2_Pos) /**< (CCL_LUTCTRL) Event input source Position */ -#define CCL_LUTCTRL_INSEL2_IO (CCL_LUTCTRL_INSEL2_IO_Val << CCL_LUTCTRL_INSEL2_Pos) /**< (CCL_LUTCTRL) I/O pin input source Position */ -#define CCL_LUTCTRL_INSEL2_AC (CCL_LUTCTRL_INSEL2_AC_Val << CCL_LUTCTRL_INSEL2_Pos) /**< (CCL_LUTCTRL) AC input source Position */ -#define CCL_LUTCTRL_INSEL2_TC (CCL_LUTCTRL_INSEL2_TC_Val << CCL_LUTCTRL_INSEL2_Pos) /**< (CCL_LUTCTRL) TC input source Position */ -#define CCL_LUTCTRL_INSEL2_ALTTC (CCL_LUTCTRL_INSEL2_ALTTC_Val << CCL_LUTCTRL_INSEL2_Pos) /**< (CCL_LUTCTRL) Alternate TC input source Position */ -#define CCL_LUTCTRL_INSEL2_TCC (CCL_LUTCTRL_INSEL2_TCC_Val << CCL_LUTCTRL_INSEL2_Pos) /**< (CCL_LUTCTRL) TCC input source Position */ -#define CCL_LUTCTRL_INSEL2_SERCOM (CCL_LUTCTRL_INSEL2_SERCOM_Val << CCL_LUTCTRL_INSEL2_Pos) /**< (CCL_LUTCTRL) SERCOM input source Position */ -#define CCL_LUTCTRL_INVEI_Pos _U_(20) /**< (CCL_LUTCTRL) Inverted Event Input Enable Position */ -#define CCL_LUTCTRL_INVEI_Msk (_U_(0x1) << CCL_LUTCTRL_INVEI_Pos) /**< (CCL_LUTCTRL) Inverted Event Input Enable Mask */ -#define CCL_LUTCTRL_INVEI(value) (CCL_LUTCTRL_INVEI_Msk & ((value) << CCL_LUTCTRL_INVEI_Pos)) -#define CCL_LUTCTRL_INVEI_DISABLE_Val _U_(0x0) /**< (CCL_LUTCTRL) Incoming event is not inverted */ -#define CCL_LUTCTRL_INVEI_ENABLE_Val _U_(0x1) /**< (CCL_LUTCTRL) Incoming event is inverted */ -#define CCL_LUTCTRL_INVEI_DISABLE (CCL_LUTCTRL_INVEI_DISABLE_Val << CCL_LUTCTRL_INVEI_Pos) /**< (CCL_LUTCTRL) Incoming event is not inverted Position */ -#define CCL_LUTCTRL_INVEI_ENABLE (CCL_LUTCTRL_INVEI_ENABLE_Val << CCL_LUTCTRL_INVEI_Pos) /**< (CCL_LUTCTRL) Incoming event is inverted Position */ -#define CCL_LUTCTRL_LUTEI_Pos _U_(21) /**< (CCL_LUTCTRL) LUT Event Input Enable Position */ -#define CCL_LUTCTRL_LUTEI_Msk (_U_(0x1) << CCL_LUTCTRL_LUTEI_Pos) /**< (CCL_LUTCTRL) LUT Event Input Enable Mask */ -#define CCL_LUTCTRL_LUTEI(value) (CCL_LUTCTRL_LUTEI_Msk & ((value) << CCL_LUTCTRL_LUTEI_Pos)) -#define CCL_LUTCTRL_LUTEI_DISABLE_Val _U_(0x0) /**< (CCL_LUTCTRL) LUT incoming event is disabled */ -#define CCL_LUTCTRL_LUTEI_ENABLE_Val _U_(0x1) /**< (CCL_LUTCTRL) LUT incoming event is enabled */ -#define CCL_LUTCTRL_LUTEI_DISABLE (CCL_LUTCTRL_LUTEI_DISABLE_Val << CCL_LUTCTRL_LUTEI_Pos) /**< (CCL_LUTCTRL) LUT incoming event is disabled Position */ -#define CCL_LUTCTRL_LUTEI_ENABLE (CCL_LUTCTRL_LUTEI_ENABLE_Val << CCL_LUTCTRL_LUTEI_Pos) /**< (CCL_LUTCTRL) LUT incoming event is enabled Position */ -#define CCL_LUTCTRL_LUTEO_Pos _U_(22) /**< (CCL_LUTCTRL) LUT Event Output Enable Position */ -#define CCL_LUTCTRL_LUTEO_Msk (_U_(0x1) << CCL_LUTCTRL_LUTEO_Pos) /**< (CCL_LUTCTRL) LUT Event Output Enable Mask */ -#define CCL_LUTCTRL_LUTEO(value) (CCL_LUTCTRL_LUTEO_Msk & ((value) << CCL_LUTCTRL_LUTEO_Pos)) -#define CCL_LUTCTRL_LUTEO_DISABLE_Val _U_(0x0) /**< (CCL_LUTCTRL) LUT event output is disabled */ -#define CCL_LUTCTRL_LUTEO_ENABLE_Val _U_(0x1) /**< (CCL_LUTCTRL) LUT event output is enabled */ -#define CCL_LUTCTRL_LUTEO_DISABLE (CCL_LUTCTRL_LUTEO_DISABLE_Val << CCL_LUTCTRL_LUTEO_Pos) /**< (CCL_LUTCTRL) LUT event output is disabled Position */ -#define CCL_LUTCTRL_LUTEO_ENABLE (CCL_LUTCTRL_LUTEO_ENABLE_Val << CCL_LUTCTRL_LUTEO_Pos) /**< (CCL_LUTCTRL) LUT event output is enabled Position */ -#define CCL_LUTCTRL_TRUTH_Pos _U_(24) /**< (CCL_LUTCTRL) Truth Value Position */ -#define CCL_LUTCTRL_TRUTH_Msk (_U_(0xFF) << CCL_LUTCTRL_TRUTH_Pos) /**< (CCL_LUTCTRL) Truth Value Mask */ -#define CCL_LUTCTRL_TRUTH(value) (CCL_LUTCTRL_TRUTH_Msk & ((value) << CCL_LUTCTRL_TRUTH_Pos)) -#define CCL_LUTCTRL_Msk _U_(0xFF7FFFB2) /**< (CCL_LUTCTRL) Register Mask */ - - -/** \brief CCL register offsets definitions */ -#define CCL_CTRL_REG_OFST (0x00) /**< (CCL_CTRL) Control Offset */ -#define CCL_SEQCTRL_REG_OFST (0x04) /**< (CCL_SEQCTRL) SEQ Control x Offset */ -#define CCL_LUTCTRL_REG_OFST (0x08) /**< (CCL_LUTCTRL) LUT Control x Offset */ - -#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) -/** \brief CCL register API structure */ -typedef struct -{ /* Configurable Custom Logic */ - __IO uint8_t CCL_CTRL; /**< Offset: 0x00 (R/W 8) Control */ - __I uint8_t Reserved1[0x03]; - __IO uint8_t CCL_SEQCTRL[2]; /**< Offset: 0x04 (R/W 8) SEQ Control x */ - __I uint8_t Reserved2[0x02]; - __IO uint32_t CCL_LUTCTRL[4]; /**< Offset: 0x08 (R/W 32) LUT Control x */ -} ccl_registers_t; - - -#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ -#endif /* _SAME54_CCL_COMPONENT_H_ */ +/** + * \file + * + * \brief Component description for CCL + * + * Copyright (c) 2019 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAME54_CCL_COMPONENT_ +#define _SAME54_CCL_COMPONENT_ + +/* ========================================================================== */ +/** SOFTWARE API DEFINITION FOR CCL */ +/* ========================================================================== */ +/** \addtogroup SAME54_CCL Configurable Custom Logic */ +/*@{*/ + +#define CCL_U2225 +#define REV_CCL 0x110 + +/* -------- CCL_CTRL : (CCL Offset: 0x0) (R/W 8) Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t SWRST:1; /*!< bit: 0 Software Reset */ + uint8_t ENABLE:1; /*!< bit: 1 Enable */ + uint8_t :4; /*!< bit: 2.. 5 Reserved */ + uint8_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */ + uint8_t :1; /*!< bit: 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} CCL_CTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CCL_CTRL_OFFSET 0x0 /**< \brief (CCL_CTRL offset) Control */ +#define CCL_CTRL_RESETVALUE _U_(0x00) /**< \brief (CCL_CTRL reset_value) Control */ + +#define CCL_CTRL_SWRST_Pos 0 /**< \brief (CCL_CTRL) Software Reset */ +#define CCL_CTRL_SWRST (_U_(0x1) << CCL_CTRL_SWRST_Pos) +#define CCL_CTRL_ENABLE_Pos 1 /**< \brief (CCL_CTRL) Enable */ +#define CCL_CTRL_ENABLE (_U_(0x1) << CCL_CTRL_ENABLE_Pos) +#define CCL_CTRL_RUNSTDBY_Pos 6 /**< \brief (CCL_CTRL) Run in Standby */ +#define CCL_CTRL_RUNSTDBY (_U_(0x1) << CCL_CTRL_RUNSTDBY_Pos) +#define CCL_CTRL_MASK _U_(0x43) /**< \brief (CCL_CTRL) MASK Register */ + +/* -------- CCL_SEQCTRL : (CCL Offset: 0x4) (R/W 8) SEQ Control x -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t SEQSEL:4; /*!< bit: 0.. 3 Sequential Selection */ + uint8_t :4; /*!< bit: 4.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} CCL_SEQCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CCL_SEQCTRL_OFFSET 0x4 /**< \brief (CCL_SEQCTRL offset) SEQ Control x */ +#define CCL_SEQCTRL_RESETVALUE _U_(0x00) /**< \brief (CCL_SEQCTRL reset_value) SEQ Control x */ + +#define CCL_SEQCTRL_SEQSEL_Pos 0 /**< \brief (CCL_SEQCTRL) Sequential Selection */ +#define CCL_SEQCTRL_SEQSEL_Msk (_U_(0xF) << CCL_SEQCTRL_SEQSEL_Pos) +#define CCL_SEQCTRL_SEQSEL(value) (CCL_SEQCTRL_SEQSEL_Msk & ((value) << CCL_SEQCTRL_SEQSEL_Pos)) +#define CCL_SEQCTRL_SEQSEL_DISABLE_Val _U_(0x0) /**< \brief (CCL_SEQCTRL) Sequential logic is disabled */ +#define CCL_SEQCTRL_SEQSEL_DFF_Val _U_(0x1) /**< \brief (CCL_SEQCTRL) D flip flop */ +#define CCL_SEQCTRL_SEQSEL_JK_Val _U_(0x2) /**< \brief (CCL_SEQCTRL) JK flip flop */ +#define CCL_SEQCTRL_SEQSEL_LATCH_Val _U_(0x3) /**< \brief (CCL_SEQCTRL) D latch */ +#define CCL_SEQCTRL_SEQSEL_RS_Val _U_(0x4) /**< \brief (CCL_SEQCTRL) RS latch */ +#define CCL_SEQCTRL_SEQSEL_DISABLE (CCL_SEQCTRL_SEQSEL_DISABLE_Val << CCL_SEQCTRL_SEQSEL_Pos) +#define CCL_SEQCTRL_SEQSEL_DFF (CCL_SEQCTRL_SEQSEL_DFF_Val << CCL_SEQCTRL_SEQSEL_Pos) +#define CCL_SEQCTRL_SEQSEL_JK (CCL_SEQCTRL_SEQSEL_JK_Val << CCL_SEQCTRL_SEQSEL_Pos) +#define CCL_SEQCTRL_SEQSEL_LATCH (CCL_SEQCTRL_SEQSEL_LATCH_Val << CCL_SEQCTRL_SEQSEL_Pos) +#define CCL_SEQCTRL_SEQSEL_RS (CCL_SEQCTRL_SEQSEL_RS_Val << CCL_SEQCTRL_SEQSEL_Pos) +#define CCL_SEQCTRL_MASK _U_(0x0F) /**< \brief (CCL_SEQCTRL) MASK Register */ + +/* -------- CCL_LUTCTRL : (CCL Offset: 0x8) (R/W 32) LUT Control x -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t :1; /*!< bit: 0 Reserved */ + uint32_t ENABLE:1; /*!< bit: 1 LUT Enable */ + uint32_t :2; /*!< bit: 2.. 3 Reserved */ + uint32_t FILTSEL:2; /*!< bit: 4.. 5 Filter Selection */ + uint32_t :1; /*!< bit: 6 Reserved */ + uint32_t EDGESEL:1; /*!< bit: 7 Edge Selection */ + uint32_t INSEL0:4; /*!< bit: 8..11 Input Selection 0 */ + uint32_t INSEL1:4; /*!< bit: 12..15 Input Selection 1 */ + uint32_t INSEL2:4; /*!< bit: 16..19 Input Selection 2 */ + uint32_t INVEI:1; /*!< bit: 20 Inverted Event Input Enable */ + uint32_t LUTEI:1; /*!< bit: 21 LUT Event Input Enable */ + uint32_t LUTEO:1; /*!< bit: 22 LUT Event Output Enable */ + uint32_t :1; /*!< bit: 23 Reserved */ + uint32_t TRUTH:8; /*!< bit: 24..31 Truth Value */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CCL_LUTCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CCL_LUTCTRL_OFFSET 0x8 /**< \brief (CCL_LUTCTRL offset) LUT Control x */ +#define CCL_LUTCTRL_RESETVALUE _U_(0x00000000) /**< \brief (CCL_LUTCTRL reset_value) LUT Control x */ + +#define CCL_LUTCTRL_ENABLE_Pos 1 /**< \brief (CCL_LUTCTRL) LUT Enable */ +#define CCL_LUTCTRL_ENABLE (_U_(0x1) << CCL_LUTCTRL_ENABLE_Pos) +#define CCL_LUTCTRL_FILTSEL_Pos 4 /**< \brief (CCL_LUTCTRL) Filter Selection */ +#define CCL_LUTCTRL_FILTSEL_Msk (_U_(0x3) << CCL_LUTCTRL_FILTSEL_Pos) +#define CCL_LUTCTRL_FILTSEL(value) (CCL_LUTCTRL_FILTSEL_Msk & ((value) << CCL_LUTCTRL_FILTSEL_Pos)) +#define CCL_LUTCTRL_FILTSEL_DISABLE_Val _U_(0x0) /**< \brief (CCL_LUTCTRL) Filter disabled */ +#define CCL_LUTCTRL_FILTSEL_SYNCH_Val _U_(0x1) /**< \brief (CCL_LUTCTRL) Synchronizer enabled */ +#define CCL_LUTCTRL_FILTSEL_FILTER_Val _U_(0x2) /**< \brief (CCL_LUTCTRL) Filter enabled */ +#define CCL_LUTCTRL_FILTSEL_DISABLE (CCL_LUTCTRL_FILTSEL_DISABLE_Val << CCL_LUTCTRL_FILTSEL_Pos) +#define CCL_LUTCTRL_FILTSEL_SYNCH (CCL_LUTCTRL_FILTSEL_SYNCH_Val << CCL_LUTCTRL_FILTSEL_Pos) +#define CCL_LUTCTRL_FILTSEL_FILTER (CCL_LUTCTRL_FILTSEL_FILTER_Val << CCL_LUTCTRL_FILTSEL_Pos) +#define CCL_LUTCTRL_EDGESEL_Pos 7 /**< \brief (CCL_LUTCTRL) Edge Selection */ +#define CCL_LUTCTRL_EDGESEL (_U_(0x1) << CCL_LUTCTRL_EDGESEL_Pos) +#define CCL_LUTCTRL_INSEL0_Pos 8 /**< \brief (CCL_LUTCTRL) Input Selection 0 */ +#define CCL_LUTCTRL_INSEL0_Msk (_U_(0xF) << CCL_LUTCTRL_INSEL0_Pos) +#define CCL_LUTCTRL_INSEL0(value) (CCL_LUTCTRL_INSEL0_Msk & ((value) << CCL_LUTCTRL_INSEL0_Pos)) +#define CCL_LUTCTRL_INSEL0_MASK_Val _U_(0x0) /**< \brief (CCL_LUTCTRL) Masked input */ +#define CCL_LUTCTRL_INSEL0_FEEDBACK_Val _U_(0x1) /**< \brief (CCL_LUTCTRL) Feedback input source */ +#define CCL_LUTCTRL_INSEL0_LINK_Val _U_(0x2) /**< \brief (CCL_LUTCTRL) Linked LUT input source */ +#define CCL_LUTCTRL_INSEL0_EVENT_Val _U_(0x3) /**< \brief (CCL_LUTCTRL) Event input source */ +#define CCL_LUTCTRL_INSEL0_IO_Val _U_(0x4) /**< \brief (CCL_LUTCTRL) I/O pin input source */ +#define CCL_LUTCTRL_INSEL0_AC_Val _U_(0x5) /**< \brief (CCL_LUTCTRL) AC input source */ +#define CCL_LUTCTRL_INSEL0_TC_Val _U_(0x6) /**< \brief (CCL_LUTCTRL) TC input source */ +#define CCL_LUTCTRL_INSEL0_ALTTC_Val _U_(0x7) /**< \brief (CCL_LUTCTRL) Alternate TC input source */ +#define CCL_LUTCTRL_INSEL0_TCC_Val _U_(0x8) /**< \brief (CCL_LUTCTRL) TCC input source */ +#define CCL_LUTCTRL_INSEL0_SERCOM_Val _U_(0x9) /**< \brief (CCL_LUTCTRL) SERCOM input source */ +#define CCL_LUTCTRL_INSEL0_MASK (CCL_LUTCTRL_INSEL0_MASK_Val << CCL_LUTCTRL_INSEL0_Pos) +#define CCL_LUTCTRL_INSEL0_FEEDBACK (CCL_LUTCTRL_INSEL0_FEEDBACK_Val << CCL_LUTCTRL_INSEL0_Pos) +#define CCL_LUTCTRL_INSEL0_LINK (CCL_LUTCTRL_INSEL0_LINK_Val << CCL_LUTCTRL_INSEL0_Pos) +#define CCL_LUTCTRL_INSEL0_EVENT (CCL_LUTCTRL_INSEL0_EVENT_Val << CCL_LUTCTRL_INSEL0_Pos) +#define CCL_LUTCTRL_INSEL0_IO (CCL_LUTCTRL_INSEL0_IO_Val << CCL_LUTCTRL_INSEL0_Pos) +#define CCL_LUTCTRL_INSEL0_AC (CCL_LUTCTRL_INSEL0_AC_Val << CCL_LUTCTRL_INSEL0_Pos) +#define CCL_LUTCTRL_INSEL0_TC (CCL_LUTCTRL_INSEL0_TC_Val << CCL_LUTCTRL_INSEL0_Pos) +#define CCL_LUTCTRL_INSEL0_ALTTC (CCL_LUTCTRL_INSEL0_ALTTC_Val << CCL_LUTCTRL_INSEL0_Pos) +#define CCL_LUTCTRL_INSEL0_TCC (CCL_LUTCTRL_INSEL0_TCC_Val << CCL_LUTCTRL_INSEL0_Pos) +#define CCL_LUTCTRL_INSEL0_SERCOM (CCL_LUTCTRL_INSEL0_SERCOM_Val << CCL_LUTCTRL_INSEL0_Pos) +#define CCL_LUTCTRL_INSEL1_Pos 12 /**< \brief (CCL_LUTCTRL) Input Selection 1 */ +#define CCL_LUTCTRL_INSEL1_Msk (_U_(0xF) << CCL_LUTCTRL_INSEL1_Pos) +#define CCL_LUTCTRL_INSEL1(value) (CCL_LUTCTRL_INSEL1_Msk & ((value) << CCL_LUTCTRL_INSEL1_Pos)) +#define CCL_LUTCTRL_INSEL1_MASK_Val _U_(0x0) /**< \brief (CCL_LUTCTRL) Masked input */ +#define CCL_LUTCTRL_INSEL1_FEEDBACK_Val _U_(0x1) /**< \brief (CCL_LUTCTRL) Feedback input source */ +#define CCL_LUTCTRL_INSEL1_LINK_Val _U_(0x2) /**< \brief (CCL_LUTCTRL) Linked LUT input source */ +#define CCL_LUTCTRL_INSEL1_EVENT_Val _U_(0x3) /**< \brief (CCL_LUTCTRL) Event input source */ +#define CCL_LUTCTRL_INSEL1_IO_Val _U_(0x4) /**< \brief (CCL_LUTCTRL) I/O pin input source */ +#define CCL_LUTCTRL_INSEL1_AC_Val _U_(0x5) /**< \brief (CCL_LUTCTRL) AC input source */ +#define CCL_LUTCTRL_INSEL1_TC_Val _U_(0x6) /**< \brief (CCL_LUTCTRL) TC input source */ +#define CCL_LUTCTRL_INSEL1_ALTTC_Val _U_(0x7) /**< \brief (CCL_LUTCTRL) Alternate TC input source */ +#define CCL_LUTCTRL_INSEL1_TCC_Val _U_(0x8) /**< \brief (CCL_LUTCTRL) TCC input source */ +#define CCL_LUTCTRL_INSEL1_SERCOM_Val _U_(0x9) /**< \brief (CCL_LUTCTRL) SERCOM input source */ +#define CCL_LUTCTRL_INSEL1_MASK (CCL_LUTCTRL_INSEL1_MASK_Val << CCL_LUTCTRL_INSEL1_Pos) +#define CCL_LUTCTRL_INSEL1_FEEDBACK (CCL_LUTCTRL_INSEL1_FEEDBACK_Val << CCL_LUTCTRL_INSEL1_Pos) +#define CCL_LUTCTRL_INSEL1_LINK (CCL_LUTCTRL_INSEL1_LINK_Val << CCL_LUTCTRL_INSEL1_Pos) +#define CCL_LUTCTRL_INSEL1_EVENT (CCL_LUTCTRL_INSEL1_EVENT_Val << CCL_LUTCTRL_INSEL1_Pos) +#define CCL_LUTCTRL_INSEL1_IO (CCL_LUTCTRL_INSEL1_IO_Val << CCL_LUTCTRL_INSEL1_Pos) +#define CCL_LUTCTRL_INSEL1_AC (CCL_LUTCTRL_INSEL1_AC_Val << CCL_LUTCTRL_INSEL1_Pos) +#define CCL_LUTCTRL_INSEL1_TC (CCL_LUTCTRL_INSEL1_TC_Val << CCL_LUTCTRL_INSEL1_Pos) +#define CCL_LUTCTRL_INSEL1_ALTTC (CCL_LUTCTRL_INSEL1_ALTTC_Val << CCL_LUTCTRL_INSEL1_Pos) +#define CCL_LUTCTRL_INSEL1_TCC (CCL_LUTCTRL_INSEL1_TCC_Val << CCL_LUTCTRL_INSEL1_Pos) +#define CCL_LUTCTRL_INSEL1_SERCOM (CCL_LUTCTRL_INSEL1_SERCOM_Val << CCL_LUTCTRL_INSEL1_Pos) +#define CCL_LUTCTRL_INSEL2_Pos 16 /**< \brief (CCL_LUTCTRL) Input Selection 2 */ +#define CCL_LUTCTRL_INSEL2_Msk (_U_(0xF) << CCL_LUTCTRL_INSEL2_Pos) +#define CCL_LUTCTRL_INSEL2(value) (CCL_LUTCTRL_INSEL2_Msk & ((value) << CCL_LUTCTRL_INSEL2_Pos)) +#define CCL_LUTCTRL_INSEL2_MASK_Val _U_(0x0) /**< \brief (CCL_LUTCTRL) Masked input */ +#define CCL_LUTCTRL_INSEL2_FEEDBACK_Val _U_(0x1) /**< \brief (CCL_LUTCTRL) Feedback input source */ +#define CCL_LUTCTRL_INSEL2_LINK_Val _U_(0x2) /**< \brief (CCL_LUTCTRL) Linked LUT input source */ +#define CCL_LUTCTRL_INSEL2_EVENT_Val _U_(0x3) /**< \brief (CCL_LUTCTRL) Event input source */ +#define CCL_LUTCTRL_INSEL2_IO_Val _U_(0x4) /**< \brief (CCL_LUTCTRL) I/O pin input source */ +#define CCL_LUTCTRL_INSEL2_AC_Val _U_(0x5) /**< \brief (CCL_LUTCTRL) AC input source */ +#define CCL_LUTCTRL_INSEL2_TC_Val _U_(0x6) /**< \brief (CCL_LUTCTRL) TC input source */ +#define CCL_LUTCTRL_INSEL2_ALTTC_Val _U_(0x7) /**< \brief (CCL_LUTCTRL) Alternate TC input source */ +#define CCL_LUTCTRL_INSEL2_TCC_Val _U_(0x8) /**< \brief (CCL_LUTCTRL) TCC input source */ +#define CCL_LUTCTRL_INSEL2_SERCOM_Val _U_(0x9) /**< \brief (CCL_LUTCTRL) SERCOM input source */ +#define CCL_LUTCTRL_INSEL2_MASK (CCL_LUTCTRL_INSEL2_MASK_Val << CCL_LUTCTRL_INSEL2_Pos) +#define CCL_LUTCTRL_INSEL2_FEEDBACK (CCL_LUTCTRL_INSEL2_FEEDBACK_Val << CCL_LUTCTRL_INSEL2_Pos) +#define CCL_LUTCTRL_INSEL2_LINK (CCL_LUTCTRL_INSEL2_LINK_Val << CCL_LUTCTRL_INSEL2_Pos) +#define CCL_LUTCTRL_INSEL2_EVENT (CCL_LUTCTRL_INSEL2_EVENT_Val << CCL_LUTCTRL_INSEL2_Pos) +#define CCL_LUTCTRL_INSEL2_IO (CCL_LUTCTRL_INSEL2_IO_Val << CCL_LUTCTRL_INSEL2_Pos) +#define CCL_LUTCTRL_INSEL2_AC (CCL_LUTCTRL_INSEL2_AC_Val << CCL_LUTCTRL_INSEL2_Pos) +#define CCL_LUTCTRL_INSEL2_TC (CCL_LUTCTRL_INSEL2_TC_Val << CCL_LUTCTRL_INSEL2_Pos) +#define CCL_LUTCTRL_INSEL2_ALTTC (CCL_LUTCTRL_INSEL2_ALTTC_Val << CCL_LUTCTRL_INSEL2_Pos) +#define CCL_LUTCTRL_INSEL2_TCC (CCL_LUTCTRL_INSEL2_TCC_Val << CCL_LUTCTRL_INSEL2_Pos) +#define CCL_LUTCTRL_INSEL2_SERCOM (CCL_LUTCTRL_INSEL2_SERCOM_Val << CCL_LUTCTRL_INSEL2_Pos) +#define CCL_LUTCTRL_INVEI_Pos 20 /**< \brief (CCL_LUTCTRL) Inverted Event Input Enable */ +#define CCL_LUTCTRL_INVEI (_U_(0x1) << CCL_LUTCTRL_INVEI_Pos) +#define CCL_LUTCTRL_LUTEI_Pos 21 /**< \brief (CCL_LUTCTRL) LUT Event Input Enable */ +#define CCL_LUTCTRL_LUTEI (_U_(0x1) << CCL_LUTCTRL_LUTEI_Pos) +#define CCL_LUTCTRL_LUTEO_Pos 22 /**< \brief (CCL_LUTCTRL) LUT Event Output Enable */ +#define CCL_LUTCTRL_LUTEO (_U_(0x1) << CCL_LUTCTRL_LUTEO_Pos) +#define CCL_LUTCTRL_TRUTH_Pos 24 /**< \brief (CCL_LUTCTRL) Truth Value */ +#define CCL_LUTCTRL_TRUTH_Msk (_U_(0xFF) << CCL_LUTCTRL_TRUTH_Pos) +#define CCL_LUTCTRL_TRUTH(value) (CCL_LUTCTRL_TRUTH_Msk & ((value) << CCL_LUTCTRL_TRUTH_Pos)) +#define CCL_LUTCTRL_MASK _U_(0xFF7FFFB2) /**< \brief (CCL_LUTCTRL) MASK Register */ + +/** \brief CCL hardware registers */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef struct { + __IO CCL_CTRL_Type CTRL; /**< \brief Offset: 0x0 (R/W 8) Control */ + RoReg8 Reserved1[0x3]; + __IO CCL_SEQCTRL_Type SEQCTRL[2]; /**< \brief Offset: 0x4 (R/W 8) SEQ Control x */ + RoReg8 Reserved2[0x2]; + __IO CCL_LUTCTRL_Type LUTCTRL[4]; /**< \brief Offset: 0x8 (R/W 32) LUT Control x */ +} Ccl; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/*@}*/ + +#endif /* _SAME54_CCL_COMPONENT_ */ diff --git a/arch/arm/SAME54/SAME54A/mcu/inc/component/cmcc.h b/arch/arm/SAME54/SAME54A/mcu/inc/component/cmcc.h index 73f1952a..55799b5c 100644 --- a/arch/arm/SAME54/SAME54A/mcu/inc/component/cmcc.h +++ b/arch/arm/SAME54/SAME54A/mcu/inc/component/cmcc.h @@ -1,247 +1,357 @@ -/** - * \brief Component description for CMCC - * - * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries. - * - * Subject to your compliance with these terms, you may use Microchip software and any derivatives - * exclusively with Microchip products. It is your responsibility to comply with third party license - * terms applicable to your use of third party software (including open source software) that may - * accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, - * APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND - * FITNESS FOR A PARTICULAR PURPOSE. - * - * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF - * MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT - * EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - */ - -/* file generated from device description version 2020-03-12T17:27:04Z */ -#ifndef _SAME54_CMCC_COMPONENT_H_ -#define _SAME54_CMCC_COMPONENT_H_ - -/* ************************************************************************** */ -/* SOFTWARE API DEFINITION FOR CMCC */ -/* ************************************************************************** */ - -/* -------- CMCC_TYPE : (CMCC Offset: 0x00) ( R/ 32) Cache Type Register -------- */ -#define CMCC_TYPE_RESETVALUE _U_(0x12D2) /**< (CMCC_TYPE) Cache Type Register Reset Value */ - -#define CMCC_TYPE_GCLK_Pos _U_(1) /**< (CMCC_TYPE) dynamic Clock Gating supported Position */ -#define CMCC_TYPE_GCLK_Msk (_U_(0x1) << CMCC_TYPE_GCLK_Pos) /**< (CMCC_TYPE) dynamic Clock Gating supported Mask */ -#define CMCC_TYPE_GCLK(value) (CMCC_TYPE_GCLK_Msk & ((value) << CMCC_TYPE_GCLK_Pos)) -#define CMCC_TYPE_RRP_Pos _U_(4) /**< (CMCC_TYPE) Round Robin Policy supported Position */ -#define CMCC_TYPE_RRP_Msk (_U_(0x1) << CMCC_TYPE_RRP_Pos) /**< (CMCC_TYPE) Round Robin Policy supported Mask */ -#define CMCC_TYPE_RRP(value) (CMCC_TYPE_RRP_Msk & ((value) << CMCC_TYPE_RRP_Pos)) -#define CMCC_TYPE_WAYNUM_Pos _U_(5) /**< (CMCC_TYPE) Number of Way Position */ -#define CMCC_TYPE_WAYNUM_Msk (_U_(0x3) << CMCC_TYPE_WAYNUM_Pos) /**< (CMCC_TYPE) Number of Way Mask */ -#define CMCC_TYPE_WAYNUM(value) (CMCC_TYPE_WAYNUM_Msk & ((value) << CMCC_TYPE_WAYNUM_Pos)) -#define CMCC_TYPE_WAYNUM_DMAPPED_Val _U_(0x0) /**< (CMCC_TYPE) Direct Mapped Cache */ -#define CMCC_TYPE_WAYNUM_ARCH2WAY_Val _U_(0x1) /**< (CMCC_TYPE) 2-WAY set associative */ -#define CMCC_TYPE_WAYNUM_ARCH4WAY_Val _U_(0x2) /**< (CMCC_TYPE) 4-WAY set associative */ -#define CMCC_TYPE_WAYNUM_DMAPPED (CMCC_TYPE_WAYNUM_DMAPPED_Val << CMCC_TYPE_WAYNUM_Pos) /**< (CMCC_TYPE) Direct Mapped Cache Position */ -#define CMCC_TYPE_WAYNUM_ARCH2WAY (CMCC_TYPE_WAYNUM_ARCH2WAY_Val << CMCC_TYPE_WAYNUM_Pos) /**< (CMCC_TYPE) 2-WAY set associative Position */ -#define CMCC_TYPE_WAYNUM_ARCH4WAY (CMCC_TYPE_WAYNUM_ARCH4WAY_Val << CMCC_TYPE_WAYNUM_Pos) /**< (CMCC_TYPE) 4-WAY set associative Position */ -#define CMCC_TYPE_LCKDOWN_Pos _U_(7) /**< (CMCC_TYPE) Lock Down supported Position */ -#define CMCC_TYPE_LCKDOWN_Msk (_U_(0x1) << CMCC_TYPE_LCKDOWN_Pos) /**< (CMCC_TYPE) Lock Down supported Mask */ -#define CMCC_TYPE_LCKDOWN(value) (CMCC_TYPE_LCKDOWN_Msk & ((value) << CMCC_TYPE_LCKDOWN_Pos)) -#define CMCC_TYPE_CSIZE_Pos _U_(8) /**< (CMCC_TYPE) Cache Size Position */ -#define CMCC_TYPE_CSIZE_Msk (_U_(0x7) << CMCC_TYPE_CSIZE_Pos) /**< (CMCC_TYPE) Cache Size Mask */ -#define CMCC_TYPE_CSIZE(value) (CMCC_TYPE_CSIZE_Msk & ((value) << CMCC_TYPE_CSIZE_Pos)) -#define CMCC_TYPE_CSIZE_CSIZE_1KB_Val _U_(0x0) /**< (CMCC_TYPE) Cache Size is 1 KB */ -#define CMCC_TYPE_CSIZE_CSIZE_2KB_Val _U_(0x1) /**< (CMCC_TYPE) Cache Size is 2 KB */ -#define CMCC_TYPE_CSIZE_CSIZE_4KB_Val _U_(0x2) /**< (CMCC_TYPE) Cache Size is 4 KB */ -#define CMCC_TYPE_CSIZE_CSIZE_8KB_Val _U_(0x3) /**< (CMCC_TYPE) Cache Size is 8 KB */ -#define CMCC_TYPE_CSIZE_CSIZE_16KB_Val _U_(0x4) /**< (CMCC_TYPE) Cache Size is 16 KB */ -#define CMCC_TYPE_CSIZE_CSIZE_32KB_Val _U_(0x5) /**< (CMCC_TYPE) Cache Size is 32 KB */ -#define CMCC_TYPE_CSIZE_CSIZE_64KB_Val _U_(0x6) /**< (CMCC_TYPE) Cache Size is 64 KB */ -#define CMCC_TYPE_CSIZE_CSIZE_1KB (CMCC_TYPE_CSIZE_CSIZE_1KB_Val << CMCC_TYPE_CSIZE_Pos) /**< (CMCC_TYPE) Cache Size is 1 KB Position */ -#define CMCC_TYPE_CSIZE_CSIZE_2KB (CMCC_TYPE_CSIZE_CSIZE_2KB_Val << CMCC_TYPE_CSIZE_Pos) /**< (CMCC_TYPE) Cache Size is 2 KB Position */ -#define CMCC_TYPE_CSIZE_CSIZE_4KB (CMCC_TYPE_CSIZE_CSIZE_4KB_Val << CMCC_TYPE_CSIZE_Pos) /**< (CMCC_TYPE) Cache Size is 4 KB Position */ -#define CMCC_TYPE_CSIZE_CSIZE_8KB (CMCC_TYPE_CSIZE_CSIZE_8KB_Val << CMCC_TYPE_CSIZE_Pos) /**< (CMCC_TYPE) Cache Size is 8 KB Position */ -#define CMCC_TYPE_CSIZE_CSIZE_16KB (CMCC_TYPE_CSIZE_CSIZE_16KB_Val << CMCC_TYPE_CSIZE_Pos) /**< (CMCC_TYPE) Cache Size is 16 KB Position */ -#define CMCC_TYPE_CSIZE_CSIZE_32KB (CMCC_TYPE_CSIZE_CSIZE_32KB_Val << CMCC_TYPE_CSIZE_Pos) /**< (CMCC_TYPE) Cache Size is 32 KB Position */ -#define CMCC_TYPE_CSIZE_CSIZE_64KB (CMCC_TYPE_CSIZE_CSIZE_64KB_Val << CMCC_TYPE_CSIZE_Pos) /**< (CMCC_TYPE) Cache Size is 64 KB Position */ -#define CMCC_TYPE_CLSIZE_Pos _U_(11) /**< (CMCC_TYPE) Cache Line Size Position */ -#define CMCC_TYPE_CLSIZE_Msk (_U_(0x7) << CMCC_TYPE_CLSIZE_Pos) /**< (CMCC_TYPE) Cache Line Size Mask */ -#define CMCC_TYPE_CLSIZE(value) (CMCC_TYPE_CLSIZE_Msk & ((value) << CMCC_TYPE_CLSIZE_Pos)) -#define CMCC_TYPE_CLSIZE_CLSIZE_4B_Val _U_(0x0) /**< (CMCC_TYPE) Cache Line Size is 4 bytes */ -#define CMCC_TYPE_CLSIZE_CLSIZE_8B_Val _U_(0x1) /**< (CMCC_TYPE) Cache Line Size is 8 bytes */ -#define CMCC_TYPE_CLSIZE_CLSIZE_16B_Val _U_(0x2) /**< (CMCC_TYPE) Cache Line Size is 16 bytes */ -#define CMCC_TYPE_CLSIZE_CLSIZE_32B_Val _U_(0x3) /**< (CMCC_TYPE) Cache Line Size is 32 bytes */ -#define CMCC_TYPE_CLSIZE_CLSIZE_64B_Val _U_(0x4) /**< (CMCC_TYPE) Cache Line Size is 64 bytes */ -#define CMCC_TYPE_CLSIZE_CLSIZE_128B_Val _U_(0x5) /**< (CMCC_TYPE) Cache Line Size is 128 bytes */ -#define CMCC_TYPE_CLSIZE_CLSIZE_4B (CMCC_TYPE_CLSIZE_CLSIZE_4B_Val << CMCC_TYPE_CLSIZE_Pos) /**< (CMCC_TYPE) Cache Line Size is 4 bytes Position */ -#define CMCC_TYPE_CLSIZE_CLSIZE_8B (CMCC_TYPE_CLSIZE_CLSIZE_8B_Val << CMCC_TYPE_CLSIZE_Pos) /**< (CMCC_TYPE) Cache Line Size is 8 bytes Position */ -#define CMCC_TYPE_CLSIZE_CLSIZE_16B (CMCC_TYPE_CLSIZE_CLSIZE_16B_Val << CMCC_TYPE_CLSIZE_Pos) /**< (CMCC_TYPE) Cache Line Size is 16 bytes Position */ -#define CMCC_TYPE_CLSIZE_CLSIZE_32B (CMCC_TYPE_CLSIZE_CLSIZE_32B_Val << CMCC_TYPE_CLSIZE_Pos) /**< (CMCC_TYPE) Cache Line Size is 32 bytes Position */ -#define CMCC_TYPE_CLSIZE_CLSIZE_64B (CMCC_TYPE_CLSIZE_CLSIZE_64B_Val << CMCC_TYPE_CLSIZE_Pos) /**< (CMCC_TYPE) Cache Line Size is 64 bytes Position */ -#define CMCC_TYPE_CLSIZE_CLSIZE_128B (CMCC_TYPE_CLSIZE_CLSIZE_128B_Val << CMCC_TYPE_CLSIZE_Pos) /**< (CMCC_TYPE) Cache Line Size is 128 bytes Position */ -#define CMCC_TYPE_Msk _U_(0x00003FF2) /**< (CMCC_TYPE) Register Mask */ - - -/* -------- CMCC_CFG : (CMCC Offset: 0x04) (R/W 32) Cache Configuration Register -------- */ -#define CMCC_CFG_RESETVALUE _U_(0x20) /**< (CMCC_CFG) Cache Configuration Register Reset Value */ - -#define CMCC_CFG_ICDIS_Pos _U_(1) /**< (CMCC_CFG) Instruction Cache Disable Position */ -#define CMCC_CFG_ICDIS_Msk (_U_(0x1) << CMCC_CFG_ICDIS_Pos) /**< (CMCC_CFG) Instruction Cache Disable Mask */ -#define CMCC_CFG_ICDIS(value) (CMCC_CFG_ICDIS_Msk & ((value) << CMCC_CFG_ICDIS_Pos)) -#define CMCC_CFG_DCDIS_Pos _U_(2) /**< (CMCC_CFG) Data Cache Disable Position */ -#define CMCC_CFG_DCDIS_Msk (_U_(0x1) << CMCC_CFG_DCDIS_Pos) /**< (CMCC_CFG) Data Cache Disable Mask */ -#define CMCC_CFG_DCDIS(value) (CMCC_CFG_DCDIS_Msk & ((value) << CMCC_CFG_DCDIS_Pos)) -#define CMCC_CFG_CSIZESW_Pos _U_(4) /**< (CMCC_CFG) Cache size configured by software Position */ -#define CMCC_CFG_CSIZESW_Msk (_U_(0x7) << CMCC_CFG_CSIZESW_Pos) /**< (CMCC_CFG) Cache size configured by software Mask */ -#define CMCC_CFG_CSIZESW(value) (CMCC_CFG_CSIZESW_Msk & ((value) << CMCC_CFG_CSIZESW_Pos)) -#define CMCC_CFG_CSIZESW_CONF_CSIZE_1KB_Val _U_(0x0) /**< (CMCC_CFG) The Cache Size is configured to 1KB */ -#define CMCC_CFG_CSIZESW_CONF_CSIZE_2KB_Val _U_(0x1) /**< (CMCC_CFG) The Cache Size is configured to 2KB */ -#define CMCC_CFG_CSIZESW_CONF_CSIZE_4KB_Val _U_(0x2) /**< (CMCC_CFG) The Cache Size is configured to 4KB */ -#define CMCC_CFG_CSIZESW_CONF_CSIZE_8KB_Val _U_(0x3) /**< (CMCC_CFG) The Cache Size is configured to 8KB */ -#define CMCC_CFG_CSIZESW_CONF_CSIZE_16KB_Val _U_(0x4) /**< (CMCC_CFG) The Cache Size is configured to 16KB */ -#define CMCC_CFG_CSIZESW_CONF_CSIZE_32KB_Val _U_(0x5) /**< (CMCC_CFG) The Cache Size is configured to 32KB */ -#define CMCC_CFG_CSIZESW_CONF_CSIZE_64KB_Val _U_(0x6) /**< (CMCC_CFG) The Cache Size is configured to 64KB */ -#define CMCC_CFG_CSIZESW_CONF_CSIZE_1KB (CMCC_CFG_CSIZESW_CONF_CSIZE_1KB_Val << CMCC_CFG_CSIZESW_Pos) /**< (CMCC_CFG) The Cache Size is configured to 1KB Position */ -#define CMCC_CFG_CSIZESW_CONF_CSIZE_2KB (CMCC_CFG_CSIZESW_CONF_CSIZE_2KB_Val << CMCC_CFG_CSIZESW_Pos) /**< (CMCC_CFG) The Cache Size is configured to 2KB Position */ -#define CMCC_CFG_CSIZESW_CONF_CSIZE_4KB (CMCC_CFG_CSIZESW_CONF_CSIZE_4KB_Val << CMCC_CFG_CSIZESW_Pos) /**< (CMCC_CFG) The Cache Size is configured to 4KB Position */ -#define CMCC_CFG_CSIZESW_CONF_CSIZE_8KB (CMCC_CFG_CSIZESW_CONF_CSIZE_8KB_Val << CMCC_CFG_CSIZESW_Pos) /**< (CMCC_CFG) The Cache Size is configured to 8KB Position */ -#define CMCC_CFG_CSIZESW_CONF_CSIZE_16KB (CMCC_CFG_CSIZESW_CONF_CSIZE_16KB_Val << CMCC_CFG_CSIZESW_Pos) /**< (CMCC_CFG) The Cache Size is configured to 16KB Position */ -#define CMCC_CFG_CSIZESW_CONF_CSIZE_32KB (CMCC_CFG_CSIZESW_CONF_CSIZE_32KB_Val << CMCC_CFG_CSIZESW_Pos) /**< (CMCC_CFG) The Cache Size is configured to 32KB Position */ -#define CMCC_CFG_CSIZESW_CONF_CSIZE_64KB (CMCC_CFG_CSIZESW_CONF_CSIZE_64KB_Val << CMCC_CFG_CSIZESW_Pos) /**< (CMCC_CFG) The Cache Size is configured to 64KB Position */ -#define CMCC_CFG_Msk _U_(0x00000076) /**< (CMCC_CFG) Register Mask */ - - -/* -------- CMCC_CTRL : (CMCC Offset: 0x08) ( /W 32) Cache Control Register -------- */ -#define CMCC_CTRL_RESETVALUE _U_(0x00) /**< (CMCC_CTRL) Cache Control Register Reset Value */ - -#define CMCC_CTRL_CEN_Pos _U_(0) /**< (CMCC_CTRL) Cache Controller Enable Position */ -#define CMCC_CTRL_CEN_Msk (_U_(0x1) << CMCC_CTRL_CEN_Pos) /**< (CMCC_CTRL) Cache Controller Enable Mask */ -#define CMCC_CTRL_CEN(value) (CMCC_CTRL_CEN_Msk & ((value) << CMCC_CTRL_CEN_Pos)) -#define CMCC_CTRL_Msk _U_(0x00000001) /**< (CMCC_CTRL) Register Mask */ - - -/* -------- CMCC_SR : (CMCC Offset: 0x0C) ( R/ 32) Cache Status Register -------- */ -#define CMCC_SR_RESETVALUE _U_(0x00) /**< (CMCC_SR) Cache Status Register Reset Value */ - -#define CMCC_SR_CSTS_Pos _U_(0) /**< (CMCC_SR) Cache Controller Status Position */ -#define CMCC_SR_CSTS_Msk (_U_(0x1) << CMCC_SR_CSTS_Pos) /**< (CMCC_SR) Cache Controller Status Mask */ -#define CMCC_SR_CSTS(value) (CMCC_SR_CSTS_Msk & ((value) << CMCC_SR_CSTS_Pos)) -#define CMCC_SR_Msk _U_(0x00000001) /**< (CMCC_SR) Register Mask */ - - -/* -------- CMCC_LCKWAY : (CMCC Offset: 0x10) (R/W 32) Cache Lock per Way Register -------- */ -#define CMCC_LCKWAY_RESETVALUE _U_(0x00) /**< (CMCC_LCKWAY) Cache Lock per Way Register Reset Value */ - -#define CMCC_LCKWAY_LCKWAY_Pos _U_(0) /**< (CMCC_LCKWAY) Lockdown way Register Position */ -#define CMCC_LCKWAY_LCKWAY_Msk (_U_(0xF) << CMCC_LCKWAY_LCKWAY_Pos) /**< (CMCC_LCKWAY) Lockdown way Register Mask */ -#define CMCC_LCKWAY_LCKWAY(value) (CMCC_LCKWAY_LCKWAY_Msk & ((value) << CMCC_LCKWAY_LCKWAY_Pos)) -#define CMCC_LCKWAY_Msk _U_(0x0000000F) /**< (CMCC_LCKWAY) Register Mask */ - - -/* -------- CMCC_MAINT0 : (CMCC Offset: 0x20) ( /W 32) Cache Maintenance Register 0 -------- */ -#define CMCC_MAINT0_RESETVALUE _U_(0x00) /**< (CMCC_MAINT0) Cache Maintenance Register 0 Reset Value */ - -#define CMCC_MAINT0_INVALL_Pos _U_(0) /**< (CMCC_MAINT0) Cache Controller invalidate All Position */ -#define CMCC_MAINT0_INVALL_Msk (_U_(0x1) << CMCC_MAINT0_INVALL_Pos) /**< (CMCC_MAINT0) Cache Controller invalidate All Mask */ -#define CMCC_MAINT0_INVALL(value) (CMCC_MAINT0_INVALL_Msk & ((value) << CMCC_MAINT0_INVALL_Pos)) -#define CMCC_MAINT0_Msk _U_(0x00000001) /**< (CMCC_MAINT0) Register Mask */ - - -/* -------- CMCC_MAINT1 : (CMCC Offset: 0x24) ( /W 32) Cache Maintenance Register 1 -------- */ -#define CMCC_MAINT1_RESETVALUE _U_(0x00) /**< (CMCC_MAINT1) Cache Maintenance Register 1 Reset Value */ - -#define CMCC_MAINT1_INDEX_Pos _U_(4) /**< (CMCC_MAINT1) Invalidate Index Position */ -#define CMCC_MAINT1_INDEX_Msk (_U_(0xFF) << CMCC_MAINT1_INDEX_Pos) /**< (CMCC_MAINT1) Invalidate Index Mask */ -#define CMCC_MAINT1_INDEX(value) (CMCC_MAINT1_INDEX_Msk & ((value) << CMCC_MAINT1_INDEX_Pos)) -#define CMCC_MAINT1_WAY_Pos _U_(28) /**< (CMCC_MAINT1) Invalidate Way Position */ -#define CMCC_MAINT1_WAY_Msk (_U_(0xF) << CMCC_MAINT1_WAY_Pos) /**< (CMCC_MAINT1) Invalidate Way Mask */ -#define CMCC_MAINT1_WAY(value) (CMCC_MAINT1_WAY_Msk & ((value) << CMCC_MAINT1_WAY_Pos)) -#define CMCC_MAINT1_WAY_WAY0_Val _U_(0x0) /**< (CMCC_MAINT1) Way 0 is selection for index invalidation */ -#define CMCC_MAINT1_WAY_WAY1_Val _U_(0x1) /**< (CMCC_MAINT1) Way 1 is selection for index invalidation */ -#define CMCC_MAINT1_WAY_WAY2_Val _U_(0x2) /**< (CMCC_MAINT1) Way 2 is selection for index invalidation */ -#define CMCC_MAINT1_WAY_WAY3_Val _U_(0x3) /**< (CMCC_MAINT1) Way 3 is selection for index invalidation */ -#define CMCC_MAINT1_WAY_WAY0 (CMCC_MAINT1_WAY_WAY0_Val << CMCC_MAINT1_WAY_Pos) /**< (CMCC_MAINT1) Way 0 is selection for index invalidation Position */ -#define CMCC_MAINT1_WAY_WAY1 (CMCC_MAINT1_WAY_WAY1_Val << CMCC_MAINT1_WAY_Pos) /**< (CMCC_MAINT1) Way 1 is selection for index invalidation Position */ -#define CMCC_MAINT1_WAY_WAY2 (CMCC_MAINT1_WAY_WAY2_Val << CMCC_MAINT1_WAY_Pos) /**< (CMCC_MAINT1) Way 2 is selection for index invalidation Position */ -#define CMCC_MAINT1_WAY_WAY3 (CMCC_MAINT1_WAY_WAY3_Val << CMCC_MAINT1_WAY_Pos) /**< (CMCC_MAINT1) Way 3 is selection for index invalidation Position */ -#define CMCC_MAINT1_Msk _U_(0xF0000FF0) /**< (CMCC_MAINT1) Register Mask */ - - -/* -------- CMCC_MCFG : (CMCC Offset: 0x28) (R/W 32) Cache Monitor Configuration Register -------- */ -#define CMCC_MCFG_RESETVALUE _U_(0x00) /**< (CMCC_MCFG) Cache Monitor Configuration Register Reset Value */ - -#define CMCC_MCFG_MODE_Pos _U_(0) /**< (CMCC_MCFG) Cache Controller Monitor Counter Mode Position */ -#define CMCC_MCFG_MODE_Msk (_U_(0x3) << CMCC_MCFG_MODE_Pos) /**< (CMCC_MCFG) Cache Controller Monitor Counter Mode Mask */ -#define CMCC_MCFG_MODE(value) (CMCC_MCFG_MODE_Msk & ((value) << CMCC_MCFG_MODE_Pos)) -#define CMCC_MCFG_MODE_CYCLE_COUNT_Val _U_(0x0) /**< (CMCC_MCFG) Cycle counter */ -#define CMCC_MCFG_MODE_IHIT_COUNT_Val _U_(0x1) /**< (CMCC_MCFG) Instruction hit counter */ -#define CMCC_MCFG_MODE_DHIT_COUNT_Val _U_(0x2) /**< (CMCC_MCFG) Data hit counter */ -#define CMCC_MCFG_MODE_CYCLE_COUNT (CMCC_MCFG_MODE_CYCLE_COUNT_Val << CMCC_MCFG_MODE_Pos) /**< (CMCC_MCFG) Cycle counter Position */ -#define CMCC_MCFG_MODE_IHIT_COUNT (CMCC_MCFG_MODE_IHIT_COUNT_Val << CMCC_MCFG_MODE_Pos) /**< (CMCC_MCFG) Instruction hit counter Position */ -#define CMCC_MCFG_MODE_DHIT_COUNT (CMCC_MCFG_MODE_DHIT_COUNT_Val << CMCC_MCFG_MODE_Pos) /**< (CMCC_MCFG) Data hit counter Position */ -#define CMCC_MCFG_Msk _U_(0x00000003) /**< (CMCC_MCFG) Register Mask */ - - -/* -------- CMCC_MEN : (CMCC Offset: 0x2C) (R/W 32) Cache Monitor Enable Register -------- */ -#define CMCC_MEN_RESETVALUE _U_(0x00) /**< (CMCC_MEN) Cache Monitor Enable Register Reset Value */ - -#define CMCC_MEN_MENABLE_Pos _U_(0) /**< (CMCC_MEN) Cache Controller Monitor Enable Position */ -#define CMCC_MEN_MENABLE_Msk (_U_(0x1) << CMCC_MEN_MENABLE_Pos) /**< (CMCC_MEN) Cache Controller Monitor Enable Mask */ -#define CMCC_MEN_MENABLE(value) (CMCC_MEN_MENABLE_Msk & ((value) << CMCC_MEN_MENABLE_Pos)) -#define CMCC_MEN_Msk _U_(0x00000001) /**< (CMCC_MEN) Register Mask */ - - -/* -------- CMCC_MCTRL : (CMCC Offset: 0x30) ( /W 32) Cache Monitor Control Register -------- */ -#define CMCC_MCTRL_RESETVALUE _U_(0x00) /**< (CMCC_MCTRL) Cache Monitor Control Register Reset Value */ - -#define CMCC_MCTRL_SWRST_Pos _U_(0) /**< (CMCC_MCTRL) Cache Controller Software Reset Position */ -#define CMCC_MCTRL_SWRST_Msk (_U_(0x1) << CMCC_MCTRL_SWRST_Pos) /**< (CMCC_MCTRL) Cache Controller Software Reset Mask */ -#define CMCC_MCTRL_SWRST(value) (CMCC_MCTRL_SWRST_Msk & ((value) << CMCC_MCTRL_SWRST_Pos)) -#define CMCC_MCTRL_Msk _U_(0x00000001) /**< (CMCC_MCTRL) Register Mask */ - - -/* -------- CMCC_MSR : (CMCC Offset: 0x34) ( R/ 32) Cache Monitor Status Register -------- */ -#define CMCC_MSR_RESETVALUE _U_(0x00) /**< (CMCC_MSR) Cache Monitor Status Register Reset Value */ - -#define CMCC_MSR_EVENT_CNT_Pos _U_(0) /**< (CMCC_MSR) Monitor Event Counter Position */ -#define CMCC_MSR_EVENT_CNT_Msk (_U_(0xFFFFFFFF) << CMCC_MSR_EVENT_CNT_Pos) /**< (CMCC_MSR) Monitor Event Counter Mask */ -#define CMCC_MSR_EVENT_CNT(value) (CMCC_MSR_EVENT_CNT_Msk & ((value) << CMCC_MSR_EVENT_CNT_Pos)) -#define CMCC_MSR_Msk _U_(0xFFFFFFFF) /**< (CMCC_MSR) Register Mask */ - - -/** \brief CMCC register offsets definitions */ -#define CMCC_TYPE_REG_OFST (0x00) /**< (CMCC_TYPE) Cache Type Register Offset */ -#define CMCC_CFG_REG_OFST (0x04) /**< (CMCC_CFG) Cache Configuration Register Offset */ -#define CMCC_CTRL_REG_OFST (0x08) /**< (CMCC_CTRL) Cache Control Register Offset */ -#define CMCC_SR_REG_OFST (0x0C) /**< (CMCC_SR) Cache Status Register Offset */ -#define CMCC_LCKWAY_REG_OFST (0x10) /**< (CMCC_LCKWAY) Cache Lock per Way Register Offset */ -#define CMCC_MAINT0_REG_OFST (0x20) /**< (CMCC_MAINT0) Cache Maintenance Register 0 Offset */ -#define CMCC_MAINT1_REG_OFST (0x24) /**< (CMCC_MAINT1) Cache Maintenance Register 1 Offset */ -#define CMCC_MCFG_REG_OFST (0x28) /**< (CMCC_MCFG) Cache Monitor Configuration Register Offset */ -#define CMCC_MEN_REG_OFST (0x2C) /**< (CMCC_MEN) Cache Monitor Enable Register Offset */ -#define CMCC_MCTRL_REG_OFST (0x30) /**< (CMCC_MCTRL) Cache Monitor Control Register Offset */ -#define CMCC_MSR_REG_OFST (0x34) /**< (CMCC_MSR) Cache Monitor Status Register Offset */ - -#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) -/** \brief CMCC register API structure */ -typedef struct -{ /* Cortex M Cache Controller */ - __I uint32_t CMCC_TYPE; /**< Offset: 0x00 (R/ 32) Cache Type Register */ - __IO uint32_t CMCC_CFG; /**< Offset: 0x04 (R/W 32) Cache Configuration Register */ - __O uint32_t CMCC_CTRL; /**< Offset: 0x08 ( /W 32) Cache Control Register */ - __I uint32_t CMCC_SR; /**< Offset: 0x0C (R/ 32) Cache Status Register */ - __IO uint32_t CMCC_LCKWAY; /**< Offset: 0x10 (R/W 32) Cache Lock per Way Register */ - __I uint8_t Reserved1[0x0C]; - __O uint32_t CMCC_MAINT0; /**< Offset: 0x20 ( /W 32) Cache Maintenance Register 0 */ - __O uint32_t CMCC_MAINT1; /**< Offset: 0x24 ( /W 32) Cache Maintenance Register 1 */ - __IO uint32_t CMCC_MCFG; /**< Offset: 0x28 (R/W 32) Cache Monitor Configuration Register */ - __IO uint32_t CMCC_MEN; /**< Offset: 0x2C (R/W 32) Cache Monitor Enable Register */ - __O uint32_t CMCC_MCTRL; /**< Offset: 0x30 ( /W 32) Cache Monitor Control Register */ - __I uint32_t CMCC_MSR; /**< Offset: 0x34 (R/ 32) Cache Monitor Status Register */ -} cmcc_registers_t; - - -#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ -#endif /* _SAME54_CMCC_COMPONENT_H_ */ +/** + * \file + * + * \brief Component description for CMCC + * + * Copyright (c) 2019 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAME54_CMCC_COMPONENT_ +#define _SAME54_CMCC_COMPONENT_ + +/* ========================================================================== */ +/** SOFTWARE API DEFINITION FOR CMCC */ +/* ========================================================================== */ +/** \addtogroup SAME54_CMCC Cortex M Cache Controller */ +/*@{*/ + +#define CMCC_U2015 +#define REV_CMCC 0x600 + +/* -------- CMCC_TYPE : (CMCC Offset: 0x00) (R/ 32) Cache Type Register -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t :1; /*!< bit: 0 Reserved */ + uint32_t GCLK:1; /*!< bit: 1 dynamic Clock Gating supported */ + uint32_t :2; /*!< bit: 2.. 3 Reserved */ + uint32_t RRP:1; /*!< bit: 4 Round Robin Policy supported */ + uint32_t WAYNUM:2; /*!< bit: 5.. 6 Number of Way */ + uint32_t LCKDOWN:1; /*!< bit: 7 Lock Down supported */ + uint32_t CSIZE:3; /*!< bit: 8..10 Cache Size */ + uint32_t CLSIZE:3; /*!< bit: 11..13 Cache Line Size */ + uint32_t :18; /*!< bit: 14..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CMCC_TYPE_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CMCC_TYPE_OFFSET 0x00 /**< \brief (CMCC_TYPE offset) Cache Type Register */ +#define CMCC_TYPE_RESETVALUE _U_(0x000012D2) /**< \brief (CMCC_TYPE reset_value) Cache Type Register */ + +#define CMCC_TYPE_GCLK_Pos 1 /**< \brief (CMCC_TYPE) dynamic Clock Gating supported */ +#define CMCC_TYPE_GCLK (_U_(0x1) << CMCC_TYPE_GCLK_Pos) +#define CMCC_TYPE_RRP_Pos 4 /**< \brief (CMCC_TYPE) Round Robin Policy supported */ +#define CMCC_TYPE_RRP (_U_(0x1) << CMCC_TYPE_RRP_Pos) +#define CMCC_TYPE_WAYNUM_Pos 5 /**< \brief (CMCC_TYPE) Number of Way */ +#define CMCC_TYPE_WAYNUM_Msk (_U_(0x3) << CMCC_TYPE_WAYNUM_Pos) +#define CMCC_TYPE_WAYNUM(value) (CMCC_TYPE_WAYNUM_Msk & ((value) << CMCC_TYPE_WAYNUM_Pos)) +#define CMCC_TYPE_WAYNUM_DMAPPED_Val _U_(0x0) /**< \brief (CMCC_TYPE) Direct Mapped Cache */ +#define CMCC_TYPE_WAYNUM_ARCH2WAY_Val _U_(0x1) /**< \brief (CMCC_TYPE) 2-WAY set associative */ +#define CMCC_TYPE_WAYNUM_ARCH4WAY_Val _U_(0x2) /**< \brief (CMCC_TYPE) 4-WAY set associative */ +#define CMCC_TYPE_WAYNUM_DMAPPED (CMCC_TYPE_WAYNUM_DMAPPED_Val << CMCC_TYPE_WAYNUM_Pos) +#define CMCC_TYPE_WAYNUM_ARCH2WAY (CMCC_TYPE_WAYNUM_ARCH2WAY_Val << CMCC_TYPE_WAYNUM_Pos) +#define CMCC_TYPE_WAYNUM_ARCH4WAY (CMCC_TYPE_WAYNUM_ARCH4WAY_Val << CMCC_TYPE_WAYNUM_Pos) +#define CMCC_TYPE_LCKDOWN_Pos 7 /**< \brief (CMCC_TYPE) Lock Down supported */ +#define CMCC_TYPE_LCKDOWN (_U_(0x1) << CMCC_TYPE_LCKDOWN_Pos) +#define CMCC_TYPE_CSIZE_Pos 8 /**< \brief (CMCC_TYPE) Cache Size */ +#define CMCC_TYPE_CSIZE_Msk (_U_(0x7) << CMCC_TYPE_CSIZE_Pos) +#define CMCC_TYPE_CSIZE(value) (CMCC_TYPE_CSIZE_Msk & ((value) << CMCC_TYPE_CSIZE_Pos)) +#define CMCC_TYPE_CSIZE_CSIZE_1KB_Val _U_(0x0) /**< \brief (CMCC_TYPE) Cache Size is 1 KB */ +#define CMCC_TYPE_CSIZE_CSIZE_2KB_Val _U_(0x1) /**< \brief (CMCC_TYPE) Cache Size is 2 KB */ +#define CMCC_TYPE_CSIZE_CSIZE_4KB_Val _U_(0x2) /**< \brief (CMCC_TYPE) Cache Size is 4 KB */ +#define CMCC_TYPE_CSIZE_CSIZE_8KB_Val _U_(0x3) /**< \brief (CMCC_TYPE) Cache Size is 8 KB */ +#define CMCC_TYPE_CSIZE_CSIZE_16KB_Val _U_(0x4) /**< \brief (CMCC_TYPE) Cache Size is 16 KB */ +#define CMCC_TYPE_CSIZE_CSIZE_32KB_Val _U_(0x5) /**< \brief (CMCC_TYPE) Cache Size is 32 KB */ +#define CMCC_TYPE_CSIZE_CSIZE_64KB_Val _U_(0x6) /**< \brief (CMCC_TYPE) Cache Size is 64 KB */ +#define CMCC_TYPE_CSIZE_CSIZE_1KB (CMCC_TYPE_CSIZE_CSIZE_1KB_Val << CMCC_TYPE_CSIZE_Pos) +#define CMCC_TYPE_CSIZE_CSIZE_2KB (CMCC_TYPE_CSIZE_CSIZE_2KB_Val << CMCC_TYPE_CSIZE_Pos) +#define CMCC_TYPE_CSIZE_CSIZE_4KB (CMCC_TYPE_CSIZE_CSIZE_4KB_Val << CMCC_TYPE_CSIZE_Pos) +#define CMCC_TYPE_CSIZE_CSIZE_8KB (CMCC_TYPE_CSIZE_CSIZE_8KB_Val << CMCC_TYPE_CSIZE_Pos) +#define CMCC_TYPE_CSIZE_CSIZE_16KB (CMCC_TYPE_CSIZE_CSIZE_16KB_Val << CMCC_TYPE_CSIZE_Pos) +#define CMCC_TYPE_CSIZE_CSIZE_32KB (CMCC_TYPE_CSIZE_CSIZE_32KB_Val << CMCC_TYPE_CSIZE_Pos) +#define CMCC_TYPE_CSIZE_CSIZE_64KB (CMCC_TYPE_CSIZE_CSIZE_64KB_Val << CMCC_TYPE_CSIZE_Pos) +#define CMCC_TYPE_CLSIZE_Pos 11 /**< \brief (CMCC_TYPE) Cache Line Size */ +#define CMCC_TYPE_CLSIZE_Msk (_U_(0x7) << CMCC_TYPE_CLSIZE_Pos) +#define CMCC_TYPE_CLSIZE(value) (CMCC_TYPE_CLSIZE_Msk & ((value) << CMCC_TYPE_CLSIZE_Pos)) +#define CMCC_TYPE_CLSIZE_CLSIZE_4B_Val _U_(0x0) /**< \brief (CMCC_TYPE) Cache Line Size is 4 bytes */ +#define CMCC_TYPE_CLSIZE_CLSIZE_8B_Val _U_(0x1) /**< \brief (CMCC_TYPE) Cache Line Size is 8 bytes */ +#define CMCC_TYPE_CLSIZE_CLSIZE_16B_Val _U_(0x2) /**< \brief (CMCC_TYPE) Cache Line Size is 16 bytes */ +#define CMCC_TYPE_CLSIZE_CLSIZE_32B_Val _U_(0x3) /**< \brief (CMCC_TYPE) Cache Line Size is 32 bytes */ +#define CMCC_TYPE_CLSIZE_CLSIZE_64B_Val _U_(0x4) /**< \brief (CMCC_TYPE) Cache Line Size is 64 bytes */ +#define CMCC_TYPE_CLSIZE_CLSIZE_128B_Val _U_(0x5) /**< \brief (CMCC_TYPE) Cache Line Size is 128 bytes */ +#define CMCC_TYPE_CLSIZE_CLSIZE_4B (CMCC_TYPE_CLSIZE_CLSIZE_4B_Val << CMCC_TYPE_CLSIZE_Pos) +#define CMCC_TYPE_CLSIZE_CLSIZE_8B (CMCC_TYPE_CLSIZE_CLSIZE_8B_Val << CMCC_TYPE_CLSIZE_Pos) +#define CMCC_TYPE_CLSIZE_CLSIZE_16B (CMCC_TYPE_CLSIZE_CLSIZE_16B_Val << CMCC_TYPE_CLSIZE_Pos) +#define CMCC_TYPE_CLSIZE_CLSIZE_32B (CMCC_TYPE_CLSIZE_CLSIZE_32B_Val << CMCC_TYPE_CLSIZE_Pos) +#define CMCC_TYPE_CLSIZE_CLSIZE_64B (CMCC_TYPE_CLSIZE_CLSIZE_64B_Val << CMCC_TYPE_CLSIZE_Pos) +#define CMCC_TYPE_CLSIZE_CLSIZE_128B (CMCC_TYPE_CLSIZE_CLSIZE_128B_Val << CMCC_TYPE_CLSIZE_Pos) +#define CMCC_TYPE_MASK _U_(0x00003FF2) /**< \brief (CMCC_TYPE) MASK Register */ + +/* -------- CMCC_CFG : (CMCC Offset: 0x04) (R/W 32) Cache Configuration Register -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t :1; /*!< bit: 0 Reserved */ + uint32_t ICDIS:1; /*!< bit: 1 Instruction Cache Disable */ + uint32_t DCDIS:1; /*!< bit: 2 Data Cache Disable */ + uint32_t :1; /*!< bit: 3 Reserved */ + uint32_t CSIZESW:3; /*!< bit: 4.. 6 Cache size configured by software */ + uint32_t :25; /*!< bit: 7..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CMCC_CFG_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CMCC_CFG_OFFSET 0x04 /**< \brief (CMCC_CFG offset) Cache Configuration Register */ +#define CMCC_CFG_RESETVALUE _U_(0x00000020) /**< \brief (CMCC_CFG reset_value) Cache Configuration Register */ + +#define CMCC_CFG_ICDIS_Pos 1 /**< \brief (CMCC_CFG) Instruction Cache Disable */ +#define CMCC_CFG_ICDIS (_U_(0x1) << CMCC_CFG_ICDIS_Pos) +#define CMCC_CFG_DCDIS_Pos 2 /**< \brief (CMCC_CFG) Data Cache Disable */ +#define CMCC_CFG_DCDIS (_U_(0x1) << CMCC_CFG_DCDIS_Pos) +#define CMCC_CFG_CSIZESW_Pos 4 /**< \brief (CMCC_CFG) Cache size configured by software */ +#define CMCC_CFG_CSIZESW_Msk (_U_(0x7) << CMCC_CFG_CSIZESW_Pos) +#define CMCC_CFG_CSIZESW(value) (CMCC_CFG_CSIZESW_Msk & ((value) << CMCC_CFG_CSIZESW_Pos)) +#define CMCC_CFG_CSIZESW_CONF_CSIZE_1KB_Val _U_(0x0) /**< \brief (CMCC_CFG) the Cache Size is configured to 1KB */ +#define CMCC_CFG_CSIZESW_CONF_CSIZE_2KB_Val _U_(0x1) /**< \brief (CMCC_CFG) the Cache Size is configured to 2KB */ +#define CMCC_CFG_CSIZESW_CONF_CSIZE_4KB_Val _U_(0x2) /**< \brief (CMCC_CFG) the Cache Size is configured to 4KB */ +#define CMCC_CFG_CSIZESW_CONF_CSIZE_8KB_Val _U_(0x3) /**< \brief (CMCC_CFG) the Cache Size is configured to 8KB */ +#define CMCC_CFG_CSIZESW_CONF_CSIZE_16KB_Val _U_(0x4) /**< \brief (CMCC_CFG) the Cache Size is configured to 16KB */ +#define CMCC_CFG_CSIZESW_CONF_CSIZE_32KB_Val _U_(0x5) /**< \brief (CMCC_CFG) the Cache Size is configured to 32KB */ +#define CMCC_CFG_CSIZESW_CONF_CSIZE_64KB_Val _U_(0x6) /**< \brief (CMCC_CFG) the Cache Size is configured to 64KB */ +#define CMCC_CFG_CSIZESW_CONF_CSIZE_1KB (CMCC_CFG_CSIZESW_CONF_CSIZE_1KB_Val << CMCC_CFG_CSIZESW_Pos) +#define CMCC_CFG_CSIZESW_CONF_CSIZE_2KB (CMCC_CFG_CSIZESW_CONF_CSIZE_2KB_Val << CMCC_CFG_CSIZESW_Pos) +#define CMCC_CFG_CSIZESW_CONF_CSIZE_4KB (CMCC_CFG_CSIZESW_CONF_CSIZE_4KB_Val << CMCC_CFG_CSIZESW_Pos) +#define CMCC_CFG_CSIZESW_CONF_CSIZE_8KB (CMCC_CFG_CSIZESW_CONF_CSIZE_8KB_Val << CMCC_CFG_CSIZESW_Pos) +#define CMCC_CFG_CSIZESW_CONF_CSIZE_16KB (CMCC_CFG_CSIZESW_CONF_CSIZE_16KB_Val << CMCC_CFG_CSIZESW_Pos) +#define CMCC_CFG_CSIZESW_CONF_CSIZE_32KB (CMCC_CFG_CSIZESW_CONF_CSIZE_32KB_Val << CMCC_CFG_CSIZESW_Pos) +#define CMCC_CFG_CSIZESW_CONF_CSIZE_64KB (CMCC_CFG_CSIZESW_CONF_CSIZE_64KB_Val << CMCC_CFG_CSIZESW_Pos) +#define CMCC_CFG_MASK _U_(0x00000076) /**< \brief (CMCC_CFG) MASK Register */ + +/* -------- CMCC_CTRL : (CMCC Offset: 0x08) ( /W 32) Cache Control Register -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t CEN:1; /*!< bit: 0 Cache Controller Enable */ + uint32_t :31; /*!< bit: 1..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CMCC_CTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CMCC_CTRL_OFFSET 0x08 /**< \brief (CMCC_CTRL offset) Cache Control Register */ +#define CMCC_CTRL_RESETVALUE _U_(0x00000000) /**< \brief (CMCC_CTRL reset_value) Cache Control Register */ + +#define CMCC_CTRL_CEN_Pos 0 /**< \brief (CMCC_CTRL) Cache Controller Enable */ +#define CMCC_CTRL_CEN (_U_(0x1) << CMCC_CTRL_CEN_Pos) +#define CMCC_CTRL_MASK _U_(0x00000001) /**< \brief (CMCC_CTRL) MASK Register */ + +/* -------- CMCC_SR : (CMCC Offset: 0x0C) (R/ 32) Cache Status Register -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t CSTS:1; /*!< bit: 0 Cache Controller Status */ + uint32_t :31; /*!< bit: 1..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CMCC_SR_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CMCC_SR_OFFSET 0x0C /**< \brief (CMCC_SR offset) Cache Status Register */ +#define CMCC_SR_RESETVALUE _U_(0x00000000) /**< \brief (CMCC_SR reset_value) Cache Status Register */ + +#define CMCC_SR_CSTS_Pos 0 /**< \brief (CMCC_SR) Cache Controller Status */ +#define CMCC_SR_CSTS (_U_(0x1) << CMCC_SR_CSTS_Pos) +#define CMCC_SR_MASK _U_(0x00000001) /**< \brief (CMCC_SR) MASK Register */ + +/* -------- CMCC_LCKWAY : (CMCC Offset: 0x10) (R/W 32) Cache Lock per Way Register -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t LCKWAY:4; /*!< bit: 0.. 3 Lockdown way Register */ + uint32_t :28; /*!< bit: 4..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CMCC_LCKWAY_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CMCC_LCKWAY_OFFSET 0x10 /**< \brief (CMCC_LCKWAY offset) Cache Lock per Way Register */ +#define CMCC_LCKWAY_RESETVALUE _U_(0x00000000) /**< \brief (CMCC_LCKWAY reset_value) Cache Lock per Way Register */ + +#define CMCC_LCKWAY_LCKWAY_Pos 0 /**< \brief (CMCC_LCKWAY) Lockdown way Register */ +#define CMCC_LCKWAY_LCKWAY_Msk (_U_(0xF) << CMCC_LCKWAY_LCKWAY_Pos) +#define CMCC_LCKWAY_LCKWAY(value) (CMCC_LCKWAY_LCKWAY_Msk & ((value) << CMCC_LCKWAY_LCKWAY_Pos)) +#define CMCC_LCKWAY_MASK _U_(0x0000000F) /**< \brief (CMCC_LCKWAY) MASK Register */ + +/* -------- CMCC_MAINT0 : (CMCC Offset: 0x20) ( /W 32) Cache Maintenance Register 0 -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t INVALL:1; /*!< bit: 0 Cache Controller invalidate All */ + uint32_t :31; /*!< bit: 1..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CMCC_MAINT0_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CMCC_MAINT0_OFFSET 0x20 /**< \brief (CMCC_MAINT0 offset) Cache Maintenance Register 0 */ +#define CMCC_MAINT0_RESETVALUE _U_(0x00000000) /**< \brief (CMCC_MAINT0 reset_value) Cache Maintenance Register 0 */ + +#define CMCC_MAINT0_INVALL_Pos 0 /**< \brief (CMCC_MAINT0) Cache Controller invalidate All */ +#define CMCC_MAINT0_INVALL (_U_(0x1) << CMCC_MAINT0_INVALL_Pos) +#define CMCC_MAINT0_MASK _U_(0x00000001) /**< \brief (CMCC_MAINT0) MASK Register */ + +/* -------- CMCC_MAINT1 : (CMCC Offset: 0x24) ( /W 32) Cache Maintenance Register 1 -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t :4; /*!< bit: 0.. 3 Reserved */ + uint32_t INDEX:8; /*!< bit: 4..11 Invalidate Index */ + uint32_t :16; /*!< bit: 12..27 Reserved */ + uint32_t WAY:4; /*!< bit: 28..31 Invalidate Way */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CMCC_MAINT1_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CMCC_MAINT1_OFFSET 0x24 /**< \brief (CMCC_MAINT1 offset) Cache Maintenance Register 1 */ +#define CMCC_MAINT1_RESETVALUE _U_(0x00000000) /**< \brief (CMCC_MAINT1 reset_value) Cache Maintenance Register 1 */ + +#define CMCC_MAINT1_INDEX_Pos 4 /**< \brief (CMCC_MAINT1) Invalidate Index */ +#define CMCC_MAINT1_INDEX_Msk (_U_(0xFF) << CMCC_MAINT1_INDEX_Pos) +#define CMCC_MAINT1_INDEX(value) (CMCC_MAINT1_INDEX_Msk & ((value) << CMCC_MAINT1_INDEX_Pos)) +#define CMCC_MAINT1_WAY_Pos 28 /**< \brief (CMCC_MAINT1) Invalidate Way */ +#define CMCC_MAINT1_WAY_Msk (_U_(0xF) << CMCC_MAINT1_WAY_Pos) +#define CMCC_MAINT1_WAY(value) (CMCC_MAINT1_WAY_Msk & ((value) << CMCC_MAINT1_WAY_Pos)) +#define CMCC_MAINT1_WAY_WAY0_Val _U_(0x0) /**< \brief (CMCC_MAINT1) Way 0 is selection for index invalidation */ +#define CMCC_MAINT1_WAY_WAY1_Val _U_(0x1) /**< \brief (CMCC_MAINT1) Way 1 is selection for index invalidation */ +#define CMCC_MAINT1_WAY_WAY2_Val _U_(0x2) /**< \brief (CMCC_MAINT1) Way 2 is selection for index invalidation */ +#define CMCC_MAINT1_WAY_WAY3_Val _U_(0x3) /**< \brief (CMCC_MAINT1) Way 3 is selection for index invalidation */ +#define CMCC_MAINT1_WAY_WAY0 (CMCC_MAINT1_WAY_WAY0_Val << CMCC_MAINT1_WAY_Pos) +#define CMCC_MAINT1_WAY_WAY1 (CMCC_MAINT1_WAY_WAY1_Val << CMCC_MAINT1_WAY_Pos) +#define CMCC_MAINT1_WAY_WAY2 (CMCC_MAINT1_WAY_WAY2_Val << CMCC_MAINT1_WAY_Pos) +#define CMCC_MAINT1_WAY_WAY3 (CMCC_MAINT1_WAY_WAY3_Val << CMCC_MAINT1_WAY_Pos) +#define CMCC_MAINT1_MASK _U_(0xF0000FF0) /**< \brief (CMCC_MAINT1) MASK Register */ + +/* -------- CMCC_MCFG : (CMCC Offset: 0x28) (R/W 32) Cache Monitor Configuration Register -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t MODE:2; /*!< bit: 0.. 1 Cache Controller Monitor Counter Mode */ + uint32_t :30; /*!< bit: 2..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CMCC_MCFG_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CMCC_MCFG_OFFSET 0x28 /**< \brief (CMCC_MCFG offset) Cache Monitor Configuration Register */ +#define CMCC_MCFG_RESETVALUE _U_(0x00000000) /**< \brief (CMCC_MCFG reset_value) Cache Monitor Configuration Register */ + +#define CMCC_MCFG_MODE_Pos 0 /**< \brief (CMCC_MCFG) Cache Controller Monitor Counter Mode */ +#define CMCC_MCFG_MODE_Msk (_U_(0x3) << CMCC_MCFG_MODE_Pos) +#define CMCC_MCFG_MODE(value) (CMCC_MCFG_MODE_Msk & ((value) << CMCC_MCFG_MODE_Pos)) +#define CMCC_MCFG_MODE_CYCLE_COUNT_Val _U_(0x0) /**< \brief (CMCC_MCFG) cycle counter */ +#define CMCC_MCFG_MODE_IHIT_COUNT_Val _U_(0x1) /**< \brief (CMCC_MCFG) instruction hit counter */ +#define CMCC_MCFG_MODE_DHIT_COUNT_Val _U_(0x2) /**< \brief (CMCC_MCFG) data hit counter */ +#define CMCC_MCFG_MODE_CYCLE_COUNT (CMCC_MCFG_MODE_CYCLE_COUNT_Val << CMCC_MCFG_MODE_Pos) +#define CMCC_MCFG_MODE_IHIT_COUNT (CMCC_MCFG_MODE_IHIT_COUNT_Val << CMCC_MCFG_MODE_Pos) +#define CMCC_MCFG_MODE_DHIT_COUNT (CMCC_MCFG_MODE_DHIT_COUNT_Val << CMCC_MCFG_MODE_Pos) +#define CMCC_MCFG_MASK _U_(0x00000003) /**< \brief (CMCC_MCFG) MASK Register */ + +/* -------- CMCC_MEN : (CMCC Offset: 0x2C) (R/W 32) Cache Monitor Enable Register -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t MENABLE:1; /*!< bit: 0 Cache Controller Monitor Enable */ + uint32_t :31; /*!< bit: 1..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CMCC_MEN_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CMCC_MEN_OFFSET 0x2C /**< \brief (CMCC_MEN offset) Cache Monitor Enable Register */ +#define CMCC_MEN_RESETVALUE _U_(0x00000000) /**< \brief (CMCC_MEN reset_value) Cache Monitor Enable Register */ + +#define CMCC_MEN_MENABLE_Pos 0 /**< \brief (CMCC_MEN) Cache Controller Monitor Enable */ +#define CMCC_MEN_MENABLE (_U_(0x1) << CMCC_MEN_MENABLE_Pos) +#define CMCC_MEN_MASK _U_(0x00000001) /**< \brief (CMCC_MEN) MASK Register */ + +/* -------- CMCC_MCTRL : (CMCC Offset: 0x30) ( /W 32) Cache Monitor Control Register -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t SWRST:1; /*!< bit: 0 Cache Controller Software Reset */ + uint32_t :31; /*!< bit: 1..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CMCC_MCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CMCC_MCTRL_OFFSET 0x30 /**< \brief (CMCC_MCTRL offset) Cache Monitor Control Register */ +#define CMCC_MCTRL_RESETVALUE _U_(0x00000000) /**< \brief (CMCC_MCTRL reset_value) Cache Monitor Control Register */ + +#define CMCC_MCTRL_SWRST_Pos 0 /**< \brief (CMCC_MCTRL) Cache Controller Software Reset */ +#define CMCC_MCTRL_SWRST (_U_(0x1) << CMCC_MCTRL_SWRST_Pos) +#define CMCC_MCTRL_MASK _U_(0x00000001) /**< \brief (CMCC_MCTRL) MASK Register */ + +/* -------- CMCC_MSR : (CMCC Offset: 0x34) (R/ 32) Cache Monitor Status Register -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t EVENT_CNT:32; /*!< bit: 0..31 Monitor Event Counter */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CMCC_MSR_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CMCC_MSR_OFFSET 0x34 /**< \brief (CMCC_MSR offset) Cache Monitor Status Register */ +#define CMCC_MSR_RESETVALUE _U_(0x00000000) /**< \brief (CMCC_MSR reset_value) Cache Monitor Status Register */ + +#define CMCC_MSR_EVENT_CNT_Pos 0 /**< \brief (CMCC_MSR) Monitor Event Counter */ +#define CMCC_MSR_EVENT_CNT_Msk (_U_(0xFFFFFFFF) << CMCC_MSR_EVENT_CNT_Pos) +#define CMCC_MSR_EVENT_CNT(value) (CMCC_MSR_EVENT_CNT_Msk & ((value) << CMCC_MSR_EVENT_CNT_Pos)) +#define CMCC_MSR_MASK _U_(0xFFFFFFFF) /**< \brief (CMCC_MSR) MASK Register */ + +/** \brief CMCC APB hardware registers */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef struct { + __I CMCC_TYPE_Type TYPE; /**< \brief Offset: 0x00 (R/ 32) Cache Type Register */ + __IO CMCC_CFG_Type CFG; /**< \brief Offset: 0x04 (R/W 32) Cache Configuration Register */ + __O CMCC_CTRL_Type CTRL; /**< \brief Offset: 0x08 ( /W 32) Cache Control Register */ + __I CMCC_SR_Type SR; /**< \brief Offset: 0x0C (R/ 32) Cache Status Register */ + __IO CMCC_LCKWAY_Type LCKWAY; /**< \brief Offset: 0x10 (R/W 32) Cache Lock per Way Register */ + RoReg8 Reserved1[0xC]; + __O CMCC_MAINT0_Type MAINT0; /**< \brief Offset: 0x20 ( /W 32) Cache Maintenance Register 0 */ + __O CMCC_MAINT1_Type MAINT1; /**< \brief Offset: 0x24 ( /W 32) Cache Maintenance Register 1 */ + __IO CMCC_MCFG_Type MCFG; /**< \brief Offset: 0x28 (R/W 32) Cache Monitor Configuration Register */ + __IO CMCC_MEN_Type MEN; /**< \brief Offset: 0x2C (R/W 32) Cache Monitor Enable Register */ + __O CMCC_MCTRL_Type MCTRL; /**< \brief Offset: 0x30 ( /W 32) Cache Monitor Control Register */ + __I CMCC_MSR_Type MSR; /**< \brief Offset: 0x34 (R/ 32) Cache Monitor Status Register */ +} Cmcc; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/*@}*/ + +#endif /* _SAME54_CMCC_COMPONENT_ */ diff --git a/arch/arm/SAME54/SAME54A/mcu/inc/component/dac.h b/arch/arm/SAME54/SAME54A/mcu/inc/component/dac.h index 3582ef5e..60f28c0b 100644 --- a/arch/arm/SAME54/SAME54A/mcu/inc/component/dac.h +++ b/arch/arm/SAME54/SAME54A/mcu/inc/component/dac.h @@ -1,439 +1,544 @@ -/** - * \brief Component description for DAC - * - * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries. - * - * Subject to your compliance with these terms, you may use Microchip software and any derivatives - * exclusively with Microchip products. It is your responsibility to comply with third party license - * terms applicable to your use of third party software (including open source software) that may - * accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, - * APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND - * FITNESS FOR A PARTICULAR PURPOSE. - * - * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF - * MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT - * EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - */ - -/* file generated from device description version 2020-03-12T17:27:04Z */ -#ifndef _SAME54_DAC_COMPONENT_H_ -#define _SAME54_DAC_COMPONENT_H_ - -/* ************************************************************************** */ -/* SOFTWARE API DEFINITION FOR DAC */ -/* ************************************************************************** */ - -/* -------- DAC_CTRLA : (DAC Offset: 0x00) (R/W 8) Control A -------- */ -#define DAC_CTRLA_RESETVALUE _U_(0x00) /**< (DAC_CTRLA) Control A Reset Value */ - -#define DAC_CTRLA_SWRST_Pos _U_(0) /**< (DAC_CTRLA) Software Reset Position */ -#define DAC_CTRLA_SWRST_Msk (_U_(0x1) << DAC_CTRLA_SWRST_Pos) /**< (DAC_CTRLA) Software Reset Mask */ -#define DAC_CTRLA_SWRST(value) (DAC_CTRLA_SWRST_Msk & ((value) << DAC_CTRLA_SWRST_Pos)) -#define DAC_CTRLA_ENABLE_Pos _U_(1) /**< (DAC_CTRLA) Enable DAC Controller Position */ -#define DAC_CTRLA_ENABLE_Msk (_U_(0x1) << DAC_CTRLA_ENABLE_Pos) /**< (DAC_CTRLA) Enable DAC Controller Mask */ -#define DAC_CTRLA_ENABLE(value) (DAC_CTRLA_ENABLE_Msk & ((value) << DAC_CTRLA_ENABLE_Pos)) -#define DAC_CTRLA_Msk _U_(0x03) /**< (DAC_CTRLA) Register Mask */ - - -/* -------- DAC_CTRLB : (DAC Offset: 0x01) (R/W 8) Control B -------- */ -#define DAC_CTRLB_RESETVALUE _U_(0x02) /**< (DAC_CTRLB) Control B Reset Value */ - -#define DAC_CTRLB_DIFF_Pos _U_(0) /**< (DAC_CTRLB) Differential mode enable Position */ -#define DAC_CTRLB_DIFF_Msk (_U_(0x1) << DAC_CTRLB_DIFF_Pos) /**< (DAC_CTRLB) Differential mode enable Mask */ -#define DAC_CTRLB_DIFF(value) (DAC_CTRLB_DIFF_Msk & ((value) << DAC_CTRLB_DIFF_Pos)) -#define DAC_CTRLB_REFSEL_Pos _U_(1) /**< (DAC_CTRLB) Reference Selection for DAC0/1 Position */ -#define DAC_CTRLB_REFSEL_Msk (_U_(0x3) << DAC_CTRLB_REFSEL_Pos) /**< (DAC_CTRLB) Reference Selection for DAC0/1 Mask */ -#define DAC_CTRLB_REFSEL(value) (DAC_CTRLB_REFSEL_Msk & ((value) << DAC_CTRLB_REFSEL_Pos)) -#define DAC_CTRLB_REFSEL_VREFPU_Val _U_(0x0) /**< (DAC_CTRLB) External reference unbuffered */ -#define DAC_CTRLB_REFSEL_VDDANA_Val _U_(0x1) /**< (DAC_CTRLB) Analog supply */ -#define DAC_CTRLB_REFSEL_VREFPB_Val _U_(0x2) /**< (DAC_CTRLB) External reference buffered */ -#define DAC_CTRLB_REFSEL_INTREF_Val _U_(0x3) /**< (DAC_CTRLB) Internal bandgap reference */ -#define DAC_CTRLB_REFSEL_VREFPU (DAC_CTRLB_REFSEL_VREFPU_Val << DAC_CTRLB_REFSEL_Pos) /**< (DAC_CTRLB) External reference unbuffered Position */ -#define DAC_CTRLB_REFSEL_VDDANA (DAC_CTRLB_REFSEL_VDDANA_Val << DAC_CTRLB_REFSEL_Pos) /**< (DAC_CTRLB) Analog supply Position */ -#define DAC_CTRLB_REFSEL_VREFPB (DAC_CTRLB_REFSEL_VREFPB_Val << DAC_CTRLB_REFSEL_Pos) /**< (DAC_CTRLB) External reference buffered Position */ -#define DAC_CTRLB_REFSEL_INTREF (DAC_CTRLB_REFSEL_INTREF_Val << DAC_CTRLB_REFSEL_Pos) /**< (DAC_CTRLB) Internal bandgap reference Position */ -#define DAC_CTRLB_Msk _U_(0x07) /**< (DAC_CTRLB) Register Mask */ - - -/* -------- DAC_EVCTRL : (DAC Offset: 0x02) (R/W 8) Event Control -------- */ -#define DAC_EVCTRL_RESETVALUE _U_(0x00) /**< (DAC_EVCTRL) Event Control Reset Value */ - -#define DAC_EVCTRL_STARTEI0_Pos _U_(0) /**< (DAC_EVCTRL) Start Conversion Event Input DAC 0 Position */ -#define DAC_EVCTRL_STARTEI0_Msk (_U_(0x1) << DAC_EVCTRL_STARTEI0_Pos) /**< (DAC_EVCTRL) Start Conversion Event Input DAC 0 Mask */ -#define DAC_EVCTRL_STARTEI0(value) (DAC_EVCTRL_STARTEI0_Msk & ((value) << DAC_EVCTRL_STARTEI0_Pos)) -#define DAC_EVCTRL_STARTEI1_Pos _U_(1) /**< (DAC_EVCTRL) Start Conversion Event Input DAC 1 Position */ -#define DAC_EVCTRL_STARTEI1_Msk (_U_(0x1) << DAC_EVCTRL_STARTEI1_Pos) /**< (DAC_EVCTRL) Start Conversion Event Input DAC 1 Mask */ -#define DAC_EVCTRL_STARTEI1(value) (DAC_EVCTRL_STARTEI1_Msk & ((value) << DAC_EVCTRL_STARTEI1_Pos)) -#define DAC_EVCTRL_EMPTYEO0_Pos _U_(2) /**< (DAC_EVCTRL) Data Buffer Empty Event Output DAC 0 Position */ -#define DAC_EVCTRL_EMPTYEO0_Msk (_U_(0x1) << DAC_EVCTRL_EMPTYEO0_Pos) /**< (DAC_EVCTRL) Data Buffer Empty Event Output DAC 0 Mask */ -#define DAC_EVCTRL_EMPTYEO0(value) (DAC_EVCTRL_EMPTYEO0_Msk & ((value) << DAC_EVCTRL_EMPTYEO0_Pos)) -#define DAC_EVCTRL_EMPTYEO1_Pos _U_(3) /**< (DAC_EVCTRL) Data Buffer Empty Event Output DAC 1 Position */ -#define DAC_EVCTRL_EMPTYEO1_Msk (_U_(0x1) << DAC_EVCTRL_EMPTYEO1_Pos) /**< (DAC_EVCTRL) Data Buffer Empty Event Output DAC 1 Mask */ -#define DAC_EVCTRL_EMPTYEO1(value) (DAC_EVCTRL_EMPTYEO1_Msk & ((value) << DAC_EVCTRL_EMPTYEO1_Pos)) -#define DAC_EVCTRL_INVEI0_Pos _U_(4) /**< (DAC_EVCTRL) Enable Invertion of DAC 0 input event Position */ -#define DAC_EVCTRL_INVEI0_Msk (_U_(0x1) << DAC_EVCTRL_INVEI0_Pos) /**< (DAC_EVCTRL) Enable Invertion of DAC 0 input event Mask */ -#define DAC_EVCTRL_INVEI0(value) (DAC_EVCTRL_INVEI0_Msk & ((value) << DAC_EVCTRL_INVEI0_Pos)) -#define DAC_EVCTRL_INVEI1_Pos _U_(5) /**< (DAC_EVCTRL) Enable Invertion of DAC 1 input event Position */ -#define DAC_EVCTRL_INVEI1_Msk (_U_(0x1) << DAC_EVCTRL_INVEI1_Pos) /**< (DAC_EVCTRL) Enable Invertion of DAC 1 input event Mask */ -#define DAC_EVCTRL_INVEI1(value) (DAC_EVCTRL_INVEI1_Msk & ((value) << DAC_EVCTRL_INVEI1_Pos)) -#define DAC_EVCTRL_RESRDYEO0_Pos _U_(6) /**< (DAC_EVCTRL) Result Ready Event Output 0 Position */ -#define DAC_EVCTRL_RESRDYEO0_Msk (_U_(0x1) << DAC_EVCTRL_RESRDYEO0_Pos) /**< (DAC_EVCTRL) Result Ready Event Output 0 Mask */ -#define DAC_EVCTRL_RESRDYEO0(value) (DAC_EVCTRL_RESRDYEO0_Msk & ((value) << DAC_EVCTRL_RESRDYEO0_Pos)) -#define DAC_EVCTRL_RESRDYEO1_Pos _U_(7) /**< (DAC_EVCTRL) Result Ready Event Output 1 Position */ -#define DAC_EVCTRL_RESRDYEO1_Msk (_U_(0x1) << DAC_EVCTRL_RESRDYEO1_Pos) /**< (DAC_EVCTRL) Result Ready Event Output 1 Mask */ -#define DAC_EVCTRL_RESRDYEO1(value) (DAC_EVCTRL_RESRDYEO1_Msk & ((value) << DAC_EVCTRL_RESRDYEO1_Pos)) -#define DAC_EVCTRL_Msk _U_(0xFF) /**< (DAC_EVCTRL) Register Mask */ - -#define DAC_EVCTRL_STARTEI_Pos _U_(0) /**< (DAC_EVCTRL Position) Start Conversion Event Input DAC x */ -#define DAC_EVCTRL_STARTEI_Msk (_U_(0x3) << DAC_EVCTRL_STARTEI_Pos) /**< (DAC_EVCTRL Mask) STARTEI */ -#define DAC_EVCTRL_STARTEI(value) (DAC_EVCTRL_STARTEI_Msk & ((value) << DAC_EVCTRL_STARTEI_Pos)) -#define DAC_EVCTRL_EMPTYEO_Pos _U_(2) /**< (DAC_EVCTRL Position) Data Buffer Empty Event Output DAC x */ -#define DAC_EVCTRL_EMPTYEO_Msk (_U_(0x3) << DAC_EVCTRL_EMPTYEO_Pos) /**< (DAC_EVCTRL Mask) EMPTYEO */ -#define DAC_EVCTRL_EMPTYEO(value) (DAC_EVCTRL_EMPTYEO_Msk & ((value) << DAC_EVCTRL_EMPTYEO_Pos)) -#define DAC_EVCTRL_INVEI_Pos _U_(4) /**< (DAC_EVCTRL Position) Enable Invertion of DAC x input event */ -#define DAC_EVCTRL_INVEI_Msk (_U_(0x3) << DAC_EVCTRL_INVEI_Pos) /**< (DAC_EVCTRL Mask) INVEI */ -#define DAC_EVCTRL_INVEI(value) (DAC_EVCTRL_INVEI_Msk & ((value) << DAC_EVCTRL_INVEI_Pos)) -#define DAC_EVCTRL_RESRDYEO_Pos _U_(6) /**< (DAC_EVCTRL Position) Result Ready Event Output x */ -#define DAC_EVCTRL_RESRDYEO_Msk (_U_(0x3) << DAC_EVCTRL_RESRDYEO_Pos) /**< (DAC_EVCTRL Mask) RESRDYEO */ -#define DAC_EVCTRL_RESRDYEO(value) (DAC_EVCTRL_RESRDYEO_Msk & ((value) << DAC_EVCTRL_RESRDYEO_Pos)) - -/* -------- DAC_INTENCLR : (DAC Offset: 0x04) (R/W 8) Interrupt Enable Clear -------- */ -#define DAC_INTENCLR_RESETVALUE _U_(0x00) /**< (DAC_INTENCLR) Interrupt Enable Clear Reset Value */ - -#define DAC_INTENCLR_UNDERRUN0_Pos _U_(0) /**< (DAC_INTENCLR) Underrun 0 Interrupt Enable Position */ -#define DAC_INTENCLR_UNDERRUN0_Msk (_U_(0x1) << DAC_INTENCLR_UNDERRUN0_Pos) /**< (DAC_INTENCLR) Underrun 0 Interrupt Enable Mask */ -#define DAC_INTENCLR_UNDERRUN0(value) (DAC_INTENCLR_UNDERRUN0_Msk & ((value) << DAC_INTENCLR_UNDERRUN0_Pos)) -#define DAC_INTENCLR_UNDERRUN1_Pos _U_(1) /**< (DAC_INTENCLR) Underrun 1 Interrupt Enable Position */ -#define DAC_INTENCLR_UNDERRUN1_Msk (_U_(0x1) << DAC_INTENCLR_UNDERRUN1_Pos) /**< (DAC_INTENCLR) Underrun 1 Interrupt Enable Mask */ -#define DAC_INTENCLR_UNDERRUN1(value) (DAC_INTENCLR_UNDERRUN1_Msk & ((value) << DAC_INTENCLR_UNDERRUN1_Pos)) -#define DAC_INTENCLR_EMPTY0_Pos _U_(2) /**< (DAC_INTENCLR) Data Buffer 0 Empty Interrupt Enable Position */ -#define DAC_INTENCLR_EMPTY0_Msk (_U_(0x1) << DAC_INTENCLR_EMPTY0_Pos) /**< (DAC_INTENCLR) Data Buffer 0 Empty Interrupt Enable Mask */ -#define DAC_INTENCLR_EMPTY0(value) (DAC_INTENCLR_EMPTY0_Msk & ((value) << DAC_INTENCLR_EMPTY0_Pos)) -#define DAC_INTENCLR_EMPTY1_Pos _U_(3) /**< (DAC_INTENCLR) Data Buffer 1 Empty Interrupt Enable Position */ -#define DAC_INTENCLR_EMPTY1_Msk (_U_(0x1) << DAC_INTENCLR_EMPTY1_Pos) /**< (DAC_INTENCLR) Data Buffer 1 Empty Interrupt Enable Mask */ -#define DAC_INTENCLR_EMPTY1(value) (DAC_INTENCLR_EMPTY1_Msk & ((value) << DAC_INTENCLR_EMPTY1_Pos)) -#define DAC_INTENCLR_RESRDY0_Pos _U_(4) /**< (DAC_INTENCLR) Result 0 Ready Interrupt Enable Position */ -#define DAC_INTENCLR_RESRDY0_Msk (_U_(0x1) << DAC_INTENCLR_RESRDY0_Pos) /**< (DAC_INTENCLR) Result 0 Ready Interrupt Enable Mask */ -#define DAC_INTENCLR_RESRDY0(value) (DAC_INTENCLR_RESRDY0_Msk & ((value) << DAC_INTENCLR_RESRDY0_Pos)) -#define DAC_INTENCLR_RESRDY1_Pos _U_(5) /**< (DAC_INTENCLR) Result 1 Ready Interrupt Enable Position */ -#define DAC_INTENCLR_RESRDY1_Msk (_U_(0x1) << DAC_INTENCLR_RESRDY1_Pos) /**< (DAC_INTENCLR) Result 1 Ready Interrupt Enable Mask */ -#define DAC_INTENCLR_RESRDY1(value) (DAC_INTENCLR_RESRDY1_Msk & ((value) << DAC_INTENCLR_RESRDY1_Pos)) -#define DAC_INTENCLR_OVERRUN0_Pos _U_(6) /**< (DAC_INTENCLR) Overrun 0 Interrupt Enable Position */ -#define DAC_INTENCLR_OVERRUN0_Msk (_U_(0x1) << DAC_INTENCLR_OVERRUN0_Pos) /**< (DAC_INTENCLR) Overrun 0 Interrupt Enable Mask */ -#define DAC_INTENCLR_OVERRUN0(value) (DAC_INTENCLR_OVERRUN0_Msk & ((value) << DAC_INTENCLR_OVERRUN0_Pos)) -#define DAC_INTENCLR_OVERRUN1_Pos _U_(7) /**< (DAC_INTENCLR) Overrun 1 Interrupt Enable Position */ -#define DAC_INTENCLR_OVERRUN1_Msk (_U_(0x1) << DAC_INTENCLR_OVERRUN1_Pos) /**< (DAC_INTENCLR) Overrun 1 Interrupt Enable Mask */ -#define DAC_INTENCLR_OVERRUN1(value) (DAC_INTENCLR_OVERRUN1_Msk & ((value) << DAC_INTENCLR_OVERRUN1_Pos)) -#define DAC_INTENCLR_Msk _U_(0xFF) /**< (DAC_INTENCLR) Register Mask */ - -#define DAC_INTENCLR_UNDERRUN_Pos _U_(0) /**< (DAC_INTENCLR Position) Underrun x Interrupt Enable */ -#define DAC_INTENCLR_UNDERRUN_Msk (_U_(0x3) << DAC_INTENCLR_UNDERRUN_Pos) /**< (DAC_INTENCLR Mask) UNDERRUN */ -#define DAC_INTENCLR_UNDERRUN(value) (DAC_INTENCLR_UNDERRUN_Msk & ((value) << DAC_INTENCLR_UNDERRUN_Pos)) -#define DAC_INTENCLR_EMPTY_Pos _U_(2) /**< (DAC_INTENCLR Position) Data Buffer x Empty Interrupt Enable */ -#define DAC_INTENCLR_EMPTY_Msk (_U_(0x3) << DAC_INTENCLR_EMPTY_Pos) /**< (DAC_INTENCLR Mask) EMPTY */ -#define DAC_INTENCLR_EMPTY(value) (DAC_INTENCLR_EMPTY_Msk & ((value) << DAC_INTENCLR_EMPTY_Pos)) -#define DAC_INTENCLR_RESRDY_Pos _U_(4) /**< (DAC_INTENCLR Position) Result x Ready Interrupt Enable */ -#define DAC_INTENCLR_RESRDY_Msk (_U_(0x3) << DAC_INTENCLR_RESRDY_Pos) /**< (DAC_INTENCLR Mask) RESRDY */ -#define DAC_INTENCLR_RESRDY(value) (DAC_INTENCLR_RESRDY_Msk & ((value) << DAC_INTENCLR_RESRDY_Pos)) -#define DAC_INTENCLR_OVERRUN_Pos _U_(6) /**< (DAC_INTENCLR Position) Overrun x Interrupt Enable */ -#define DAC_INTENCLR_OVERRUN_Msk (_U_(0x3) << DAC_INTENCLR_OVERRUN_Pos) /**< (DAC_INTENCLR Mask) OVERRUN */ -#define DAC_INTENCLR_OVERRUN(value) (DAC_INTENCLR_OVERRUN_Msk & ((value) << DAC_INTENCLR_OVERRUN_Pos)) - -/* -------- DAC_INTENSET : (DAC Offset: 0x05) (R/W 8) Interrupt Enable Set -------- */ -#define DAC_INTENSET_RESETVALUE _U_(0x00) /**< (DAC_INTENSET) Interrupt Enable Set Reset Value */ - -#define DAC_INTENSET_UNDERRUN0_Pos _U_(0) /**< (DAC_INTENSET) Underrun 0 Interrupt Enable Position */ -#define DAC_INTENSET_UNDERRUN0_Msk (_U_(0x1) << DAC_INTENSET_UNDERRUN0_Pos) /**< (DAC_INTENSET) Underrun 0 Interrupt Enable Mask */ -#define DAC_INTENSET_UNDERRUN0(value) (DAC_INTENSET_UNDERRUN0_Msk & ((value) << DAC_INTENSET_UNDERRUN0_Pos)) -#define DAC_INTENSET_UNDERRUN1_Pos _U_(1) /**< (DAC_INTENSET) Underrun 1 Interrupt Enable Position */ -#define DAC_INTENSET_UNDERRUN1_Msk (_U_(0x1) << DAC_INTENSET_UNDERRUN1_Pos) /**< (DAC_INTENSET) Underrun 1 Interrupt Enable Mask */ -#define DAC_INTENSET_UNDERRUN1(value) (DAC_INTENSET_UNDERRUN1_Msk & ((value) << DAC_INTENSET_UNDERRUN1_Pos)) -#define DAC_INTENSET_EMPTY0_Pos _U_(2) /**< (DAC_INTENSET) Data Buffer 0 Empty Interrupt Enable Position */ -#define DAC_INTENSET_EMPTY0_Msk (_U_(0x1) << DAC_INTENSET_EMPTY0_Pos) /**< (DAC_INTENSET) Data Buffer 0 Empty Interrupt Enable Mask */ -#define DAC_INTENSET_EMPTY0(value) (DAC_INTENSET_EMPTY0_Msk & ((value) << DAC_INTENSET_EMPTY0_Pos)) -#define DAC_INTENSET_EMPTY1_Pos _U_(3) /**< (DAC_INTENSET) Data Buffer 1 Empty Interrupt Enable Position */ -#define DAC_INTENSET_EMPTY1_Msk (_U_(0x1) << DAC_INTENSET_EMPTY1_Pos) /**< (DAC_INTENSET) Data Buffer 1 Empty Interrupt Enable Mask */ -#define DAC_INTENSET_EMPTY1(value) (DAC_INTENSET_EMPTY1_Msk & ((value) << DAC_INTENSET_EMPTY1_Pos)) -#define DAC_INTENSET_RESRDY0_Pos _U_(4) /**< (DAC_INTENSET) Result 0 Ready Interrupt Enable Position */ -#define DAC_INTENSET_RESRDY0_Msk (_U_(0x1) << DAC_INTENSET_RESRDY0_Pos) /**< (DAC_INTENSET) Result 0 Ready Interrupt Enable Mask */ -#define DAC_INTENSET_RESRDY0(value) (DAC_INTENSET_RESRDY0_Msk & ((value) << DAC_INTENSET_RESRDY0_Pos)) -#define DAC_INTENSET_RESRDY1_Pos _U_(5) /**< (DAC_INTENSET) Result 1 Ready Interrupt Enable Position */ -#define DAC_INTENSET_RESRDY1_Msk (_U_(0x1) << DAC_INTENSET_RESRDY1_Pos) /**< (DAC_INTENSET) Result 1 Ready Interrupt Enable Mask */ -#define DAC_INTENSET_RESRDY1(value) (DAC_INTENSET_RESRDY1_Msk & ((value) << DAC_INTENSET_RESRDY1_Pos)) -#define DAC_INTENSET_OVERRUN0_Pos _U_(6) /**< (DAC_INTENSET) Overrun 0 Interrupt Enable Position */ -#define DAC_INTENSET_OVERRUN0_Msk (_U_(0x1) << DAC_INTENSET_OVERRUN0_Pos) /**< (DAC_INTENSET) Overrun 0 Interrupt Enable Mask */ -#define DAC_INTENSET_OVERRUN0(value) (DAC_INTENSET_OVERRUN0_Msk & ((value) << DAC_INTENSET_OVERRUN0_Pos)) -#define DAC_INTENSET_OVERRUN1_Pos _U_(7) /**< (DAC_INTENSET) Overrun 1 Interrupt Enable Position */ -#define DAC_INTENSET_OVERRUN1_Msk (_U_(0x1) << DAC_INTENSET_OVERRUN1_Pos) /**< (DAC_INTENSET) Overrun 1 Interrupt Enable Mask */ -#define DAC_INTENSET_OVERRUN1(value) (DAC_INTENSET_OVERRUN1_Msk & ((value) << DAC_INTENSET_OVERRUN1_Pos)) -#define DAC_INTENSET_Msk _U_(0xFF) /**< (DAC_INTENSET) Register Mask */ - -#define DAC_INTENSET_UNDERRUN_Pos _U_(0) /**< (DAC_INTENSET Position) Underrun x Interrupt Enable */ -#define DAC_INTENSET_UNDERRUN_Msk (_U_(0x3) << DAC_INTENSET_UNDERRUN_Pos) /**< (DAC_INTENSET Mask) UNDERRUN */ -#define DAC_INTENSET_UNDERRUN(value) (DAC_INTENSET_UNDERRUN_Msk & ((value) << DAC_INTENSET_UNDERRUN_Pos)) -#define DAC_INTENSET_EMPTY_Pos _U_(2) /**< (DAC_INTENSET Position) Data Buffer x Empty Interrupt Enable */ -#define DAC_INTENSET_EMPTY_Msk (_U_(0x3) << DAC_INTENSET_EMPTY_Pos) /**< (DAC_INTENSET Mask) EMPTY */ -#define DAC_INTENSET_EMPTY(value) (DAC_INTENSET_EMPTY_Msk & ((value) << DAC_INTENSET_EMPTY_Pos)) -#define DAC_INTENSET_RESRDY_Pos _U_(4) /**< (DAC_INTENSET Position) Result x Ready Interrupt Enable */ -#define DAC_INTENSET_RESRDY_Msk (_U_(0x3) << DAC_INTENSET_RESRDY_Pos) /**< (DAC_INTENSET Mask) RESRDY */ -#define DAC_INTENSET_RESRDY(value) (DAC_INTENSET_RESRDY_Msk & ((value) << DAC_INTENSET_RESRDY_Pos)) -#define DAC_INTENSET_OVERRUN_Pos _U_(6) /**< (DAC_INTENSET Position) Overrun x Interrupt Enable */ -#define DAC_INTENSET_OVERRUN_Msk (_U_(0x3) << DAC_INTENSET_OVERRUN_Pos) /**< (DAC_INTENSET Mask) OVERRUN */ -#define DAC_INTENSET_OVERRUN(value) (DAC_INTENSET_OVERRUN_Msk & ((value) << DAC_INTENSET_OVERRUN_Pos)) - -/* -------- DAC_INTFLAG : (DAC Offset: 0x06) (R/W 8) Interrupt Flag Status and Clear -------- */ -#define DAC_INTFLAG_RESETVALUE _U_(0x00) /**< (DAC_INTFLAG) Interrupt Flag Status and Clear Reset Value */ - -#define DAC_INTFLAG_UNDERRUN0_Pos _U_(0) /**< (DAC_INTFLAG) Result 0 Underrun Position */ -#define DAC_INTFLAG_UNDERRUN0_Msk (_U_(0x1) << DAC_INTFLAG_UNDERRUN0_Pos) /**< (DAC_INTFLAG) Result 0 Underrun Mask */ -#define DAC_INTFLAG_UNDERRUN0(value) (DAC_INTFLAG_UNDERRUN0_Msk & ((value) << DAC_INTFLAG_UNDERRUN0_Pos)) -#define DAC_INTFLAG_UNDERRUN1_Pos _U_(1) /**< (DAC_INTFLAG) Result 1 Underrun Position */ -#define DAC_INTFLAG_UNDERRUN1_Msk (_U_(0x1) << DAC_INTFLAG_UNDERRUN1_Pos) /**< (DAC_INTFLAG) Result 1 Underrun Mask */ -#define DAC_INTFLAG_UNDERRUN1(value) (DAC_INTFLAG_UNDERRUN1_Msk & ((value) << DAC_INTFLAG_UNDERRUN1_Pos)) -#define DAC_INTFLAG_EMPTY0_Pos _U_(2) /**< (DAC_INTFLAG) Data Buffer 0 Empty Position */ -#define DAC_INTFLAG_EMPTY0_Msk (_U_(0x1) << DAC_INTFLAG_EMPTY0_Pos) /**< (DAC_INTFLAG) Data Buffer 0 Empty Mask */ -#define DAC_INTFLAG_EMPTY0(value) (DAC_INTFLAG_EMPTY0_Msk & ((value) << DAC_INTFLAG_EMPTY0_Pos)) -#define DAC_INTFLAG_EMPTY1_Pos _U_(3) /**< (DAC_INTFLAG) Data Buffer 1 Empty Position */ -#define DAC_INTFLAG_EMPTY1_Msk (_U_(0x1) << DAC_INTFLAG_EMPTY1_Pos) /**< (DAC_INTFLAG) Data Buffer 1 Empty Mask */ -#define DAC_INTFLAG_EMPTY1(value) (DAC_INTFLAG_EMPTY1_Msk & ((value) << DAC_INTFLAG_EMPTY1_Pos)) -#define DAC_INTFLAG_RESRDY0_Pos _U_(4) /**< (DAC_INTFLAG) Result 0 Ready Position */ -#define DAC_INTFLAG_RESRDY0_Msk (_U_(0x1) << DAC_INTFLAG_RESRDY0_Pos) /**< (DAC_INTFLAG) Result 0 Ready Mask */ -#define DAC_INTFLAG_RESRDY0(value) (DAC_INTFLAG_RESRDY0_Msk & ((value) << DAC_INTFLAG_RESRDY0_Pos)) -#define DAC_INTFLAG_RESRDY1_Pos _U_(5) /**< (DAC_INTFLAG) Result 1 Ready Position */ -#define DAC_INTFLAG_RESRDY1_Msk (_U_(0x1) << DAC_INTFLAG_RESRDY1_Pos) /**< (DAC_INTFLAG) Result 1 Ready Mask */ -#define DAC_INTFLAG_RESRDY1(value) (DAC_INTFLAG_RESRDY1_Msk & ((value) << DAC_INTFLAG_RESRDY1_Pos)) -#define DAC_INTFLAG_OVERRUN0_Pos _U_(6) /**< (DAC_INTFLAG) Result 0 Overrun Position */ -#define DAC_INTFLAG_OVERRUN0_Msk (_U_(0x1) << DAC_INTFLAG_OVERRUN0_Pos) /**< (DAC_INTFLAG) Result 0 Overrun Mask */ -#define DAC_INTFLAG_OVERRUN0(value) (DAC_INTFLAG_OVERRUN0_Msk & ((value) << DAC_INTFLAG_OVERRUN0_Pos)) -#define DAC_INTFLAG_OVERRUN1_Pos _U_(7) /**< (DAC_INTFLAG) Result 1 Overrun Position */ -#define DAC_INTFLAG_OVERRUN1_Msk (_U_(0x1) << DAC_INTFLAG_OVERRUN1_Pos) /**< (DAC_INTFLAG) Result 1 Overrun Mask */ -#define DAC_INTFLAG_OVERRUN1(value) (DAC_INTFLAG_OVERRUN1_Msk & ((value) << DAC_INTFLAG_OVERRUN1_Pos)) -#define DAC_INTFLAG_Msk _U_(0xFF) /**< (DAC_INTFLAG) Register Mask */ - -#define DAC_INTFLAG_UNDERRUN_Pos _U_(0) /**< (DAC_INTFLAG Position) Result x Underrun */ -#define DAC_INTFLAG_UNDERRUN_Msk (_U_(0x3) << DAC_INTFLAG_UNDERRUN_Pos) /**< (DAC_INTFLAG Mask) UNDERRUN */ -#define DAC_INTFLAG_UNDERRUN(value) (DAC_INTFLAG_UNDERRUN_Msk & ((value) << DAC_INTFLAG_UNDERRUN_Pos)) -#define DAC_INTFLAG_EMPTY_Pos _U_(2) /**< (DAC_INTFLAG Position) Data Buffer x Empty */ -#define DAC_INTFLAG_EMPTY_Msk (_U_(0x3) << DAC_INTFLAG_EMPTY_Pos) /**< (DAC_INTFLAG Mask) EMPTY */ -#define DAC_INTFLAG_EMPTY(value) (DAC_INTFLAG_EMPTY_Msk & ((value) << DAC_INTFLAG_EMPTY_Pos)) -#define DAC_INTFLAG_RESRDY_Pos _U_(4) /**< (DAC_INTFLAG Position) Result x Ready */ -#define DAC_INTFLAG_RESRDY_Msk (_U_(0x3) << DAC_INTFLAG_RESRDY_Pos) /**< (DAC_INTFLAG Mask) RESRDY */ -#define DAC_INTFLAG_RESRDY(value) (DAC_INTFLAG_RESRDY_Msk & ((value) << DAC_INTFLAG_RESRDY_Pos)) -#define DAC_INTFLAG_OVERRUN_Pos _U_(6) /**< (DAC_INTFLAG Position) Result x Overrun */ -#define DAC_INTFLAG_OVERRUN_Msk (_U_(0x3) << DAC_INTFLAG_OVERRUN_Pos) /**< (DAC_INTFLAG Mask) OVERRUN */ -#define DAC_INTFLAG_OVERRUN(value) (DAC_INTFLAG_OVERRUN_Msk & ((value) << DAC_INTFLAG_OVERRUN_Pos)) - -/* -------- DAC_STATUS : (DAC Offset: 0x07) ( R/ 8) Status -------- */ -#define DAC_STATUS_RESETVALUE _U_(0x00) /**< (DAC_STATUS) Status Reset Value */ - -#define DAC_STATUS_READY0_Pos _U_(0) /**< (DAC_STATUS) DAC 0 Startup Ready Position */ -#define DAC_STATUS_READY0_Msk (_U_(0x1) << DAC_STATUS_READY0_Pos) /**< (DAC_STATUS) DAC 0 Startup Ready Mask */ -#define DAC_STATUS_READY0(value) (DAC_STATUS_READY0_Msk & ((value) << DAC_STATUS_READY0_Pos)) -#define DAC_STATUS_READY1_Pos _U_(1) /**< (DAC_STATUS) DAC 1 Startup Ready Position */ -#define DAC_STATUS_READY1_Msk (_U_(0x1) << DAC_STATUS_READY1_Pos) /**< (DAC_STATUS) DAC 1 Startup Ready Mask */ -#define DAC_STATUS_READY1(value) (DAC_STATUS_READY1_Msk & ((value) << DAC_STATUS_READY1_Pos)) -#define DAC_STATUS_EOC0_Pos _U_(2) /**< (DAC_STATUS) DAC 0 End of Conversion Position */ -#define DAC_STATUS_EOC0_Msk (_U_(0x1) << DAC_STATUS_EOC0_Pos) /**< (DAC_STATUS) DAC 0 End of Conversion Mask */ -#define DAC_STATUS_EOC0(value) (DAC_STATUS_EOC0_Msk & ((value) << DAC_STATUS_EOC0_Pos)) -#define DAC_STATUS_EOC1_Pos _U_(3) /**< (DAC_STATUS) DAC 1 End of Conversion Position */ -#define DAC_STATUS_EOC1_Msk (_U_(0x1) << DAC_STATUS_EOC1_Pos) /**< (DAC_STATUS) DAC 1 End of Conversion Mask */ -#define DAC_STATUS_EOC1(value) (DAC_STATUS_EOC1_Msk & ((value) << DAC_STATUS_EOC1_Pos)) -#define DAC_STATUS_Msk _U_(0x0F) /**< (DAC_STATUS) Register Mask */ - -#define DAC_STATUS_READY_Pos _U_(0) /**< (DAC_STATUS Position) DAC x Startup Ready */ -#define DAC_STATUS_READY_Msk (_U_(0x3) << DAC_STATUS_READY_Pos) /**< (DAC_STATUS Mask) READY */ -#define DAC_STATUS_READY(value) (DAC_STATUS_READY_Msk & ((value) << DAC_STATUS_READY_Pos)) -#define DAC_STATUS_EOC_Pos _U_(2) /**< (DAC_STATUS Position) DAC x End of Conversion */ -#define DAC_STATUS_EOC_Msk (_U_(0x3) << DAC_STATUS_EOC_Pos) /**< (DAC_STATUS Mask) EOC */ -#define DAC_STATUS_EOC(value) (DAC_STATUS_EOC_Msk & ((value) << DAC_STATUS_EOC_Pos)) - -/* -------- DAC_SYNCBUSY : (DAC Offset: 0x08) ( R/ 32) Synchronization Busy -------- */ -#define DAC_SYNCBUSY_RESETVALUE _U_(0x00) /**< (DAC_SYNCBUSY) Synchronization Busy Reset Value */ - -#define DAC_SYNCBUSY_SWRST_Pos _U_(0) /**< (DAC_SYNCBUSY) Software Reset Position */ -#define DAC_SYNCBUSY_SWRST_Msk (_U_(0x1) << DAC_SYNCBUSY_SWRST_Pos) /**< (DAC_SYNCBUSY) Software Reset Mask */ -#define DAC_SYNCBUSY_SWRST(value) (DAC_SYNCBUSY_SWRST_Msk & ((value) << DAC_SYNCBUSY_SWRST_Pos)) -#define DAC_SYNCBUSY_ENABLE_Pos _U_(1) /**< (DAC_SYNCBUSY) DAC Enable Status Position */ -#define DAC_SYNCBUSY_ENABLE_Msk (_U_(0x1) << DAC_SYNCBUSY_ENABLE_Pos) /**< (DAC_SYNCBUSY) DAC Enable Status Mask */ -#define DAC_SYNCBUSY_ENABLE(value) (DAC_SYNCBUSY_ENABLE_Msk & ((value) << DAC_SYNCBUSY_ENABLE_Pos)) -#define DAC_SYNCBUSY_DATA0_Pos _U_(2) /**< (DAC_SYNCBUSY) Data DAC 0 Position */ -#define DAC_SYNCBUSY_DATA0_Msk (_U_(0x1) << DAC_SYNCBUSY_DATA0_Pos) /**< (DAC_SYNCBUSY) Data DAC 0 Mask */ -#define DAC_SYNCBUSY_DATA0(value) (DAC_SYNCBUSY_DATA0_Msk & ((value) << DAC_SYNCBUSY_DATA0_Pos)) -#define DAC_SYNCBUSY_DATA1_Pos _U_(3) /**< (DAC_SYNCBUSY) Data DAC 1 Position */ -#define DAC_SYNCBUSY_DATA1_Msk (_U_(0x1) << DAC_SYNCBUSY_DATA1_Pos) /**< (DAC_SYNCBUSY) Data DAC 1 Mask */ -#define DAC_SYNCBUSY_DATA1(value) (DAC_SYNCBUSY_DATA1_Msk & ((value) << DAC_SYNCBUSY_DATA1_Pos)) -#define DAC_SYNCBUSY_DATABUF0_Pos _U_(4) /**< (DAC_SYNCBUSY) Data Buffer DAC 0 Position */ -#define DAC_SYNCBUSY_DATABUF0_Msk (_U_(0x1) << DAC_SYNCBUSY_DATABUF0_Pos) /**< (DAC_SYNCBUSY) Data Buffer DAC 0 Mask */ -#define DAC_SYNCBUSY_DATABUF0(value) (DAC_SYNCBUSY_DATABUF0_Msk & ((value) << DAC_SYNCBUSY_DATABUF0_Pos)) -#define DAC_SYNCBUSY_DATABUF1_Pos _U_(5) /**< (DAC_SYNCBUSY) Data Buffer DAC 1 Position */ -#define DAC_SYNCBUSY_DATABUF1_Msk (_U_(0x1) << DAC_SYNCBUSY_DATABUF1_Pos) /**< (DAC_SYNCBUSY) Data Buffer DAC 1 Mask */ -#define DAC_SYNCBUSY_DATABUF1(value) (DAC_SYNCBUSY_DATABUF1_Msk & ((value) << DAC_SYNCBUSY_DATABUF1_Pos)) -#define DAC_SYNCBUSY_Msk _U_(0x0000003F) /**< (DAC_SYNCBUSY) Register Mask */ - -#define DAC_SYNCBUSY_DATA_Pos _U_(2) /**< (DAC_SYNCBUSY Position) Data DAC x */ -#define DAC_SYNCBUSY_DATA_Msk (_U_(0x3) << DAC_SYNCBUSY_DATA_Pos) /**< (DAC_SYNCBUSY Mask) DATA */ -#define DAC_SYNCBUSY_DATA(value) (DAC_SYNCBUSY_DATA_Msk & ((value) << DAC_SYNCBUSY_DATA_Pos)) -#define DAC_SYNCBUSY_DATABUF_Pos _U_(4) /**< (DAC_SYNCBUSY Position) Data Buffer DAC x */ -#define DAC_SYNCBUSY_DATABUF_Msk (_U_(0x3) << DAC_SYNCBUSY_DATABUF_Pos) /**< (DAC_SYNCBUSY Mask) DATABUF */ -#define DAC_SYNCBUSY_DATABUF(value) (DAC_SYNCBUSY_DATABUF_Msk & ((value) << DAC_SYNCBUSY_DATABUF_Pos)) - -/* -------- DAC_DACCTRL : (DAC Offset: 0x0C) (R/W 16) DAC n Control -------- */ -#define DAC_DACCTRL_RESETVALUE _U_(0x00) /**< (DAC_DACCTRL) DAC n Control Reset Value */ - -#define DAC_DACCTRL_LEFTADJ_Pos _U_(0) /**< (DAC_DACCTRL) Left Adjusted Data Position */ -#define DAC_DACCTRL_LEFTADJ_Msk (_U_(0x1) << DAC_DACCTRL_LEFTADJ_Pos) /**< (DAC_DACCTRL) Left Adjusted Data Mask */ -#define DAC_DACCTRL_LEFTADJ(value) (DAC_DACCTRL_LEFTADJ_Msk & ((value) << DAC_DACCTRL_LEFTADJ_Pos)) -#define DAC_DACCTRL_ENABLE_Pos _U_(1) /**< (DAC_DACCTRL) Enable DAC0 Position */ -#define DAC_DACCTRL_ENABLE_Msk (_U_(0x1) << DAC_DACCTRL_ENABLE_Pos) /**< (DAC_DACCTRL) Enable DAC0 Mask */ -#define DAC_DACCTRL_ENABLE(value) (DAC_DACCTRL_ENABLE_Msk & ((value) << DAC_DACCTRL_ENABLE_Pos)) -#define DAC_DACCTRL_CCTRL_Pos _U_(2) /**< (DAC_DACCTRL) Current Control Position */ -#define DAC_DACCTRL_CCTRL_Msk (_U_(0x3) << DAC_DACCTRL_CCTRL_Pos) /**< (DAC_DACCTRL) Current Control Mask */ -#define DAC_DACCTRL_CCTRL(value) (DAC_DACCTRL_CCTRL_Msk & ((value) << DAC_DACCTRL_CCTRL_Pos)) -#define DAC_DACCTRL_CCTRL_CC100K_Val _U_(0x0) /**< (DAC_DACCTRL) 100kSPS */ -#define DAC_DACCTRL_CCTRL_CC1M_Val _U_(0x1) /**< (DAC_DACCTRL) 500kSPS */ -#define DAC_DACCTRL_CCTRL_CC12M_Val _U_(0x2) /**< (DAC_DACCTRL) 1MSPS */ -#define DAC_DACCTRL_CCTRL_CC100K (DAC_DACCTRL_CCTRL_CC100K_Val << DAC_DACCTRL_CCTRL_Pos) /**< (DAC_DACCTRL) 100kSPS Position */ -#define DAC_DACCTRL_CCTRL_CC1M (DAC_DACCTRL_CCTRL_CC1M_Val << DAC_DACCTRL_CCTRL_Pos) /**< (DAC_DACCTRL) 500kSPS Position */ -#define DAC_DACCTRL_CCTRL_CC12M (DAC_DACCTRL_CCTRL_CC12M_Val << DAC_DACCTRL_CCTRL_Pos) /**< (DAC_DACCTRL) 1MSPS Position */ -#define DAC_DACCTRL_FEXT_Pos _U_(5) /**< (DAC_DACCTRL) Standalone Filter Position */ -#define DAC_DACCTRL_FEXT_Msk (_U_(0x1) << DAC_DACCTRL_FEXT_Pos) /**< (DAC_DACCTRL) Standalone Filter Mask */ -#define DAC_DACCTRL_FEXT(value) (DAC_DACCTRL_FEXT_Msk & ((value) << DAC_DACCTRL_FEXT_Pos)) -#define DAC_DACCTRL_RUNSTDBY_Pos _U_(6) /**< (DAC_DACCTRL) Run in Standby Position */ -#define DAC_DACCTRL_RUNSTDBY_Msk (_U_(0x1) << DAC_DACCTRL_RUNSTDBY_Pos) /**< (DAC_DACCTRL) Run in Standby Mask */ -#define DAC_DACCTRL_RUNSTDBY(value) (DAC_DACCTRL_RUNSTDBY_Msk & ((value) << DAC_DACCTRL_RUNSTDBY_Pos)) -#define DAC_DACCTRL_DITHER_Pos _U_(7) /**< (DAC_DACCTRL) Dithering Mode Position */ -#define DAC_DACCTRL_DITHER_Msk (_U_(0x1) << DAC_DACCTRL_DITHER_Pos) /**< (DAC_DACCTRL) Dithering Mode Mask */ -#define DAC_DACCTRL_DITHER(value) (DAC_DACCTRL_DITHER_Msk & ((value) << DAC_DACCTRL_DITHER_Pos)) -#define DAC_DACCTRL_REFRESH_Pos _U_(8) /**< (DAC_DACCTRL) Refresh period Position */ -#define DAC_DACCTRL_REFRESH_Msk (_U_(0xF) << DAC_DACCTRL_REFRESH_Pos) /**< (DAC_DACCTRL) Refresh period Mask */ -#define DAC_DACCTRL_REFRESH(value) (DAC_DACCTRL_REFRESH_Msk & ((value) << DAC_DACCTRL_REFRESH_Pos)) -#define DAC_DACCTRL_REFRESH_REFRESH_0_Val _U_(0x0) /**< (DAC_DACCTRL) Do not Refresh */ -#define DAC_DACCTRL_REFRESH_REFRESH_1_Val _U_(0x1) /**< (DAC_DACCTRL) Refresh every 30 us */ -#define DAC_DACCTRL_REFRESH_REFRESH_2_Val _U_(0x2) /**< (DAC_DACCTRL) Refresh every 60 us */ -#define DAC_DACCTRL_REFRESH_REFRESH_3_Val _U_(0x3) /**< (DAC_DACCTRL) Refresh every 90 us */ -#define DAC_DACCTRL_REFRESH_REFRESH_4_Val _U_(0x4) /**< (DAC_DACCTRL) Refresh every 120 us */ -#define DAC_DACCTRL_REFRESH_REFRESH_5_Val _U_(0x5) /**< (DAC_DACCTRL) Refresh every 150 us */ -#define DAC_DACCTRL_REFRESH_REFRESH_6_Val _U_(0x6) /**< (DAC_DACCTRL) Refresh every 180 us */ -#define DAC_DACCTRL_REFRESH_REFRESH_7_Val _U_(0x7) /**< (DAC_DACCTRL) Refresh every 210 us */ -#define DAC_DACCTRL_REFRESH_REFRESH_8_Val _U_(0x8) /**< (DAC_DACCTRL) Refresh every 240 us */ -#define DAC_DACCTRL_REFRESH_REFRESH_9_Val _U_(0x9) /**< (DAC_DACCTRL) Refresh every 270 us */ -#define DAC_DACCTRL_REFRESH_REFRESH_10_Val _U_(0xA) /**< (DAC_DACCTRL) Refresh every 300 us */ -#define DAC_DACCTRL_REFRESH_REFRESH_11_Val _U_(0xB) /**< (DAC_DACCTRL) Refresh every 330 us */ -#define DAC_DACCTRL_REFRESH_REFRESH_12_Val _U_(0xC) /**< (DAC_DACCTRL) Refresh every 360 us */ -#define DAC_DACCTRL_REFRESH_REFRESH_13_Val _U_(0xD) /**< (DAC_DACCTRL) Refresh every 390 us */ -#define DAC_DACCTRL_REFRESH_REFRESH_14_Val _U_(0xE) /**< (DAC_DACCTRL) Refresh every 420 us */ -#define DAC_DACCTRL_REFRESH_REFRESH_15_Val _U_(0xF) /**< (DAC_DACCTRL) Refresh every 450 us */ -#define DAC_DACCTRL_REFRESH_REFRESH_0 (DAC_DACCTRL_REFRESH_REFRESH_0_Val << DAC_DACCTRL_REFRESH_Pos) /**< (DAC_DACCTRL) Do not Refresh Position */ -#define DAC_DACCTRL_REFRESH_REFRESH_1 (DAC_DACCTRL_REFRESH_REFRESH_1_Val << DAC_DACCTRL_REFRESH_Pos) /**< (DAC_DACCTRL) Refresh every 30 us Position */ -#define DAC_DACCTRL_REFRESH_REFRESH_2 (DAC_DACCTRL_REFRESH_REFRESH_2_Val << DAC_DACCTRL_REFRESH_Pos) /**< (DAC_DACCTRL) Refresh every 60 us Position */ -#define DAC_DACCTRL_REFRESH_REFRESH_3 (DAC_DACCTRL_REFRESH_REFRESH_3_Val << DAC_DACCTRL_REFRESH_Pos) /**< (DAC_DACCTRL) Refresh every 90 us Position */ -#define DAC_DACCTRL_REFRESH_REFRESH_4 (DAC_DACCTRL_REFRESH_REFRESH_4_Val << DAC_DACCTRL_REFRESH_Pos) /**< (DAC_DACCTRL) Refresh every 120 us Position */ -#define DAC_DACCTRL_REFRESH_REFRESH_5 (DAC_DACCTRL_REFRESH_REFRESH_5_Val << DAC_DACCTRL_REFRESH_Pos) /**< (DAC_DACCTRL) Refresh every 150 us Position */ -#define DAC_DACCTRL_REFRESH_REFRESH_6 (DAC_DACCTRL_REFRESH_REFRESH_6_Val << DAC_DACCTRL_REFRESH_Pos) /**< (DAC_DACCTRL) Refresh every 180 us Position */ -#define DAC_DACCTRL_REFRESH_REFRESH_7 (DAC_DACCTRL_REFRESH_REFRESH_7_Val << DAC_DACCTRL_REFRESH_Pos) /**< (DAC_DACCTRL) Refresh every 210 us Position */ -#define DAC_DACCTRL_REFRESH_REFRESH_8 (DAC_DACCTRL_REFRESH_REFRESH_8_Val << DAC_DACCTRL_REFRESH_Pos) /**< (DAC_DACCTRL) Refresh every 240 us Position */ -#define DAC_DACCTRL_REFRESH_REFRESH_9 (DAC_DACCTRL_REFRESH_REFRESH_9_Val << DAC_DACCTRL_REFRESH_Pos) /**< (DAC_DACCTRL) Refresh every 270 us Position */ -#define DAC_DACCTRL_REFRESH_REFRESH_10 (DAC_DACCTRL_REFRESH_REFRESH_10_Val << DAC_DACCTRL_REFRESH_Pos) /**< (DAC_DACCTRL) Refresh every 300 us Position */ -#define DAC_DACCTRL_REFRESH_REFRESH_11 (DAC_DACCTRL_REFRESH_REFRESH_11_Val << DAC_DACCTRL_REFRESH_Pos) /**< (DAC_DACCTRL) Refresh every 330 us Position */ -#define DAC_DACCTRL_REFRESH_REFRESH_12 (DAC_DACCTRL_REFRESH_REFRESH_12_Val << DAC_DACCTRL_REFRESH_Pos) /**< (DAC_DACCTRL) Refresh every 360 us Position */ -#define DAC_DACCTRL_REFRESH_REFRESH_13 (DAC_DACCTRL_REFRESH_REFRESH_13_Val << DAC_DACCTRL_REFRESH_Pos) /**< (DAC_DACCTRL) Refresh every 390 us Position */ -#define DAC_DACCTRL_REFRESH_REFRESH_14 (DAC_DACCTRL_REFRESH_REFRESH_14_Val << DAC_DACCTRL_REFRESH_Pos) /**< (DAC_DACCTRL) Refresh every 420 us Position */ -#define DAC_DACCTRL_REFRESH_REFRESH_15 (DAC_DACCTRL_REFRESH_REFRESH_15_Val << DAC_DACCTRL_REFRESH_Pos) /**< (DAC_DACCTRL) Refresh every 450 us Position */ -#define DAC_DACCTRL_OSR_Pos _U_(13) /**< (DAC_DACCTRL) Sampling Rate Position */ -#define DAC_DACCTRL_OSR_Msk (_U_(0x7) << DAC_DACCTRL_OSR_Pos) /**< (DAC_DACCTRL) Sampling Rate Mask */ -#define DAC_DACCTRL_OSR(value) (DAC_DACCTRL_OSR_Msk & ((value) << DAC_DACCTRL_OSR_Pos)) -#define DAC_DACCTRL_OSR_OSR_1_Val _U_(0x0) /**< (DAC_DACCTRL) No Over Sampling */ -#define DAC_DACCTRL_OSR_OSR_2_Val _U_(0x1) /**< (DAC_DACCTRL) 2x Over Sampling Ratio */ -#define DAC_DACCTRL_OSR_OSR_4_Val _U_(0x2) /**< (DAC_DACCTRL) 4x Over Sampling Ratio */ -#define DAC_DACCTRL_OSR_OSR_8_Val _U_(0x3) /**< (DAC_DACCTRL) 8x Over Sampling Ratio */ -#define DAC_DACCTRL_OSR_OSR_16_Val _U_(0x4) /**< (DAC_DACCTRL) 16x Over Sampling Ratio */ -#define DAC_DACCTRL_OSR_OSR_32_Val _U_(0x5) /**< (DAC_DACCTRL) 32x Over Sampling Ratio */ -#define DAC_DACCTRL_OSR_OSR_1 (DAC_DACCTRL_OSR_OSR_1_Val << DAC_DACCTRL_OSR_Pos) /**< (DAC_DACCTRL) No Over Sampling Position */ -#define DAC_DACCTRL_OSR_OSR_2 (DAC_DACCTRL_OSR_OSR_2_Val << DAC_DACCTRL_OSR_Pos) /**< (DAC_DACCTRL) 2x Over Sampling Ratio Position */ -#define DAC_DACCTRL_OSR_OSR_4 (DAC_DACCTRL_OSR_OSR_4_Val << DAC_DACCTRL_OSR_Pos) /**< (DAC_DACCTRL) 4x Over Sampling Ratio Position */ -#define DAC_DACCTRL_OSR_OSR_8 (DAC_DACCTRL_OSR_OSR_8_Val << DAC_DACCTRL_OSR_Pos) /**< (DAC_DACCTRL) 8x Over Sampling Ratio Position */ -#define DAC_DACCTRL_OSR_OSR_16 (DAC_DACCTRL_OSR_OSR_16_Val << DAC_DACCTRL_OSR_Pos) /**< (DAC_DACCTRL) 16x Over Sampling Ratio Position */ -#define DAC_DACCTRL_OSR_OSR_32 (DAC_DACCTRL_OSR_OSR_32_Val << DAC_DACCTRL_OSR_Pos) /**< (DAC_DACCTRL) 32x Over Sampling Ratio Position */ -#define DAC_DACCTRL_Msk _U_(0xEFEF) /**< (DAC_DACCTRL) Register Mask */ - - -/* -------- DAC_DATA : (DAC Offset: 0x10) ( /W 16) DAC n Data -------- */ -#define DAC_DATA_RESETVALUE _U_(0x00) /**< (DAC_DATA) DAC n Data Reset Value */ - -#define DAC_DATA_DATA_Pos _U_(0) /**< (DAC_DATA) DAC0 Data Position */ -#define DAC_DATA_DATA_Msk (_U_(0xFFFF) << DAC_DATA_DATA_Pos) /**< (DAC_DATA) DAC0 Data Mask */ -#define DAC_DATA_DATA(value) (DAC_DATA_DATA_Msk & ((value) << DAC_DATA_DATA_Pos)) -#define DAC_DATA_Msk _U_(0xFFFF) /**< (DAC_DATA) Register Mask */ - - -/* -------- DAC_DATABUF : (DAC Offset: 0x14) ( /W 16) DAC n Data Buffer -------- */ -#define DAC_DATABUF_RESETVALUE _U_(0x00) /**< (DAC_DATABUF) DAC n Data Buffer Reset Value */ - -#define DAC_DATABUF_DATABUF_Pos _U_(0) /**< (DAC_DATABUF) DAC0 Data Buffer Position */ -#define DAC_DATABUF_DATABUF_Msk (_U_(0xFFFF) << DAC_DATABUF_DATABUF_Pos) /**< (DAC_DATABUF) DAC0 Data Buffer Mask */ -#define DAC_DATABUF_DATABUF(value) (DAC_DATABUF_DATABUF_Msk & ((value) << DAC_DATABUF_DATABUF_Pos)) -#define DAC_DATABUF_Msk _U_(0xFFFF) /**< (DAC_DATABUF) Register Mask */ - - -/* -------- DAC_DBGCTRL : (DAC Offset: 0x18) (R/W 8) Debug Control -------- */ -#define DAC_DBGCTRL_RESETVALUE _U_(0x00) /**< (DAC_DBGCTRL) Debug Control Reset Value */ - -#define DAC_DBGCTRL_DBGRUN_Pos _U_(0) /**< (DAC_DBGCTRL) Debug Run Position */ -#define DAC_DBGCTRL_DBGRUN_Msk (_U_(0x1) << DAC_DBGCTRL_DBGRUN_Pos) /**< (DAC_DBGCTRL) Debug Run Mask */ -#define DAC_DBGCTRL_DBGRUN(value) (DAC_DBGCTRL_DBGRUN_Msk & ((value) << DAC_DBGCTRL_DBGRUN_Pos)) -#define DAC_DBGCTRL_Msk _U_(0x01) /**< (DAC_DBGCTRL) Register Mask */ - - -/* -------- DAC_RESULT : (DAC Offset: 0x1C) ( R/ 16) Filter Result -------- */ -#define DAC_RESULT_RESETVALUE _U_(0x00) /**< (DAC_RESULT) Filter Result Reset Value */ - -#define DAC_RESULT_RESULT_Pos _U_(0) /**< (DAC_RESULT) Filter Result Position */ -#define DAC_RESULT_RESULT_Msk (_U_(0xFFFF) << DAC_RESULT_RESULT_Pos) /**< (DAC_RESULT) Filter Result Mask */ -#define DAC_RESULT_RESULT(value) (DAC_RESULT_RESULT_Msk & ((value) << DAC_RESULT_RESULT_Pos)) -#define DAC_RESULT_Msk _U_(0xFFFF) /**< (DAC_RESULT) Register Mask */ - - -/** \brief DAC register offsets definitions */ -#define DAC_CTRLA_REG_OFST (0x00) /**< (DAC_CTRLA) Control A Offset */ -#define DAC_CTRLB_REG_OFST (0x01) /**< (DAC_CTRLB) Control B Offset */ -#define DAC_EVCTRL_REG_OFST (0x02) /**< (DAC_EVCTRL) Event Control Offset */ -#define DAC_INTENCLR_REG_OFST (0x04) /**< (DAC_INTENCLR) Interrupt Enable Clear Offset */ -#define DAC_INTENSET_REG_OFST (0x05) /**< (DAC_INTENSET) Interrupt Enable Set Offset */ -#define DAC_INTFLAG_REG_OFST (0x06) /**< (DAC_INTFLAG) Interrupt Flag Status and Clear Offset */ -#define DAC_STATUS_REG_OFST (0x07) /**< (DAC_STATUS) Status Offset */ -#define DAC_SYNCBUSY_REG_OFST (0x08) /**< (DAC_SYNCBUSY) Synchronization Busy Offset */ -#define DAC_DACCTRL_REG_OFST (0x0C) /**< (DAC_DACCTRL) DAC n Control Offset */ -#define DAC_DATA_REG_OFST (0x10) /**< (DAC_DATA) DAC n Data Offset */ -#define DAC_DATABUF_REG_OFST (0x14) /**< (DAC_DATABUF) DAC n Data Buffer Offset */ -#define DAC_DBGCTRL_REG_OFST (0x18) /**< (DAC_DBGCTRL) Debug Control Offset */ -#define DAC_RESULT_REG_OFST (0x1C) /**< (DAC_RESULT) Filter Result Offset */ - -#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) -/** \brief DAC register API structure */ -typedef struct -{ /* Digital-to-Analog Converter */ - __IO uint8_t DAC_CTRLA; /**< Offset: 0x00 (R/W 8) Control A */ - __IO uint8_t DAC_CTRLB; /**< Offset: 0x01 (R/W 8) Control B */ - __IO uint8_t DAC_EVCTRL; /**< Offset: 0x02 (R/W 8) Event Control */ - __I uint8_t Reserved1[0x01]; - __IO uint8_t DAC_INTENCLR; /**< Offset: 0x04 (R/W 8) Interrupt Enable Clear */ - __IO uint8_t DAC_INTENSET; /**< Offset: 0x05 (R/W 8) Interrupt Enable Set */ - __IO uint8_t DAC_INTFLAG; /**< Offset: 0x06 (R/W 8) Interrupt Flag Status and Clear */ - __I uint8_t DAC_STATUS; /**< Offset: 0x07 (R/ 8) Status */ - __I uint32_t DAC_SYNCBUSY; /**< Offset: 0x08 (R/ 32) Synchronization Busy */ - __IO uint16_t DAC_DACCTRL[2]; /**< Offset: 0x0C (R/W 16) DAC n Control */ - __O uint16_t DAC_DATA[2]; /**< Offset: 0x10 ( /W 16) DAC n Data */ - __O uint16_t DAC_DATABUF[2]; /**< Offset: 0x14 ( /W 16) DAC n Data Buffer */ - __IO uint8_t DAC_DBGCTRL; /**< Offset: 0x18 (R/W 8) Debug Control */ - __I uint8_t Reserved2[0x03]; - __I uint16_t DAC_RESULT[2]; /**< Offset: 0x1C (R/ 16) Filter Result */ -} dac_registers_t; - - -#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ -#endif /* _SAME54_DAC_COMPONENT_H_ */ +/** + * \file + * + * \brief Component description for DAC + * + * Copyright (c) 2019 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAME54_DAC_COMPONENT_ +#define _SAME54_DAC_COMPONENT_ + +/* ========================================================================== */ +/** SOFTWARE API DEFINITION FOR DAC */ +/* ========================================================================== */ +/** \addtogroup SAME54_DAC Digital-to-Analog Converter */ +/*@{*/ + +#define DAC_U2502 +#define REV_DAC 0x100 + +/* -------- DAC_CTRLA : (DAC Offset: 0x00) (R/W 8) Control A -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t SWRST:1; /*!< bit: 0 Software Reset */ + uint8_t ENABLE:1; /*!< bit: 1 Enable DAC Controller */ + uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} DAC_CTRLA_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DAC_CTRLA_OFFSET 0x00 /**< \brief (DAC_CTRLA offset) Control A */ +#define DAC_CTRLA_RESETVALUE _U_(0x00) /**< \brief (DAC_CTRLA reset_value) Control A */ + +#define DAC_CTRLA_SWRST_Pos 0 /**< \brief (DAC_CTRLA) Software Reset */ +#define DAC_CTRLA_SWRST (_U_(0x1) << DAC_CTRLA_SWRST_Pos) +#define DAC_CTRLA_ENABLE_Pos 1 /**< \brief (DAC_CTRLA) Enable DAC Controller */ +#define DAC_CTRLA_ENABLE (_U_(0x1) << DAC_CTRLA_ENABLE_Pos) +#define DAC_CTRLA_MASK _U_(0x03) /**< \brief (DAC_CTRLA) MASK Register */ + +/* -------- DAC_CTRLB : (DAC Offset: 0x01) (R/W 8) Control B -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t DIFF:1; /*!< bit: 0 Differential mode enable */ + uint8_t REFSEL:2; /*!< bit: 1.. 2 Reference Selection for DAC0/1 */ + uint8_t :5; /*!< bit: 3.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} DAC_CTRLB_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DAC_CTRLB_OFFSET 0x01 /**< \brief (DAC_CTRLB offset) Control B */ +#define DAC_CTRLB_RESETVALUE _U_(0x02) /**< \brief (DAC_CTRLB reset_value) Control B */ + +#define DAC_CTRLB_DIFF_Pos 0 /**< \brief (DAC_CTRLB) Differential mode enable */ +#define DAC_CTRLB_DIFF (_U_(0x1) << DAC_CTRLB_DIFF_Pos) +#define DAC_CTRLB_REFSEL_Pos 1 /**< \brief (DAC_CTRLB) Reference Selection for DAC0/1 */ +#define DAC_CTRLB_REFSEL_Msk (_U_(0x3) << DAC_CTRLB_REFSEL_Pos) +#define DAC_CTRLB_REFSEL(value) (DAC_CTRLB_REFSEL_Msk & ((value) << DAC_CTRLB_REFSEL_Pos)) +#define DAC_CTRLB_REFSEL_VREFPU_Val _U_(0x0) /**< \brief (DAC_CTRLB) External reference unbuffered */ +#define DAC_CTRLB_REFSEL_VDDANA_Val _U_(0x1) /**< \brief (DAC_CTRLB) Analog supply */ +#define DAC_CTRLB_REFSEL_VREFPB_Val _U_(0x2) /**< \brief (DAC_CTRLB) External reference buffered */ +#define DAC_CTRLB_REFSEL_INTREF_Val _U_(0x3) /**< \brief (DAC_CTRLB) Internal bandgap reference */ +#define DAC_CTRLB_REFSEL_VREFPU (DAC_CTRLB_REFSEL_VREFPU_Val << DAC_CTRLB_REFSEL_Pos) +#define DAC_CTRLB_REFSEL_VDDANA (DAC_CTRLB_REFSEL_VDDANA_Val << DAC_CTRLB_REFSEL_Pos) +#define DAC_CTRLB_REFSEL_VREFPB (DAC_CTRLB_REFSEL_VREFPB_Val << DAC_CTRLB_REFSEL_Pos) +#define DAC_CTRLB_REFSEL_INTREF (DAC_CTRLB_REFSEL_INTREF_Val << DAC_CTRLB_REFSEL_Pos) +#define DAC_CTRLB_MASK _U_(0x07) /**< \brief (DAC_CTRLB) MASK Register */ + +/* -------- DAC_EVCTRL : (DAC Offset: 0x02) (R/W 8) Event Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t STARTEI0:1; /*!< bit: 0 Start Conversion Event Input DAC 0 */ + uint8_t STARTEI1:1; /*!< bit: 1 Start Conversion Event Input DAC 1 */ + uint8_t EMPTYEO0:1; /*!< bit: 2 Data Buffer Empty Event Output DAC 0 */ + uint8_t EMPTYEO1:1; /*!< bit: 3 Data Buffer Empty Event Output DAC 1 */ + uint8_t INVEI0:1; /*!< bit: 4 Enable Invertion of DAC 0 input event */ + uint8_t INVEI1:1; /*!< bit: 5 Enable Invertion of DAC 1 input event */ + uint8_t RESRDYEO0:1; /*!< bit: 6 Result Ready Event Output 0 */ + uint8_t RESRDYEO1:1; /*!< bit: 7 Result Ready Event Output 1 */ + } bit; /*!< Structure used for bit access */ + struct { + uint8_t STARTEI:2; /*!< bit: 0.. 1 Start Conversion Event Input DAC x */ + uint8_t EMPTYEO:2; /*!< bit: 2.. 3 Data Buffer Empty Event Output DAC x */ + uint8_t INVEI:2; /*!< bit: 4.. 5 Enable Invertion of DAC x input event */ + uint8_t RESRDYEO:2; /*!< bit: 6.. 7 Result Ready Event Output x */ + } vec; /*!< Structure used for vec access */ + uint8_t reg; /*!< Type used for register access */ +} DAC_EVCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DAC_EVCTRL_OFFSET 0x02 /**< \brief (DAC_EVCTRL offset) Event Control */ +#define DAC_EVCTRL_RESETVALUE _U_(0x00) /**< \brief (DAC_EVCTRL reset_value) Event Control */ + +#define DAC_EVCTRL_STARTEI0_Pos 0 /**< \brief (DAC_EVCTRL) Start Conversion Event Input DAC 0 */ +#define DAC_EVCTRL_STARTEI0 (_U_(1) << DAC_EVCTRL_STARTEI0_Pos) +#define DAC_EVCTRL_STARTEI1_Pos 1 /**< \brief (DAC_EVCTRL) Start Conversion Event Input DAC 1 */ +#define DAC_EVCTRL_STARTEI1 (_U_(1) << DAC_EVCTRL_STARTEI1_Pos) +#define DAC_EVCTRL_STARTEI_Pos 0 /**< \brief (DAC_EVCTRL) Start Conversion Event Input DAC x */ +#define DAC_EVCTRL_STARTEI_Msk (_U_(0x3) << DAC_EVCTRL_STARTEI_Pos) +#define DAC_EVCTRL_STARTEI(value) (DAC_EVCTRL_STARTEI_Msk & ((value) << DAC_EVCTRL_STARTEI_Pos)) +#define DAC_EVCTRL_EMPTYEO0_Pos 2 /**< \brief (DAC_EVCTRL) Data Buffer Empty Event Output DAC 0 */ +#define DAC_EVCTRL_EMPTYEO0 (_U_(1) << DAC_EVCTRL_EMPTYEO0_Pos) +#define DAC_EVCTRL_EMPTYEO1_Pos 3 /**< \brief (DAC_EVCTRL) Data Buffer Empty Event Output DAC 1 */ +#define DAC_EVCTRL_EMPTYEO1 (_U_(1) << DAC_EVCTRL_EMPTYEO1_Pos) +#define DAC_EVCTRL_EMPTYEO_Pos 2 /**< \brief (DAC_EVCTRL) Data Buffer Empty Event Output DAC x */ +#define DAC_EVCTRL_EMPTYEO_Msk (_U_(0x3) << DAC_EVCTRL_EMPTYEO_Pos) +#define DAC_EVCTRL_EMPTYEO(value) (DAC_EVCTRL_EMPTYEO_Msk & ((value) << DAC_EVCTRL_EMPTYEO_Pos)) +#define DAC_EVCTRL_INVEI0_Pos 4 /**< \brief (DAC_EVCTRL) Enable Invertion of DAC 0 input event */ +#define DAC_EVCTRL_INVEI0 (_U_(1) << DAC_EVCTRL_INVEI0_Pos) +#define DAC_EVCTRL_INVEI1_Pos 5 /**< \brief (DAC_EVCTRL) Enable Invertion of DAC 1 input event */ +#define DAC_EVCTRL_INVEI1 (_U_(1) << DAC_EVCTRL_INVEI1_Pos) +#define DAC_EVCTRL_INVEI_Pos 4 /**< \brief (DAC_EVCTRL) Enable Invertion of DAC x input event */ +#define DAC_EVCTRL_INVEI_Msk (_U_(0x3) << DAC_EVCTRL_INVEI_Pos) +#define DAC_EVCTRL_INVEI(value) (DAC_EVCTRL_INVEI_Msk & ((value) << DAC_EVCTRL_INVEI_Pos)) +#define DAC_EVCTRL_RESRDYEO0_Pos 6 /**< \brief (DAC_EVCTRL) Result Ready Event Output 0 */ +#define DAC_EVCTRL_RESRDYEO0 (_U_(1) << DAC_EVCTRL_RESRDYEO0_Pos) +#define DAC_EVCTRL_RESRDYEO1_Pos 7 /**< \brief (DAC_EVCTRL) Result Ready Event Output 1 */ +#define DAC_EVCTRL_RESRDYEO1 (_U_(1) << DAC_EVCTRL_RESRDYEO1_Pos) +#define DAC_EVCTRL_RESRDYEO_Pos 6 /**< \brief (DAC_EVCTRL) Result Ready Event Output x */ +#define DAC_EVCTRL_RESRDYEO_Msk (_U_(0x3) << DAC_EVCTRL_RESRDYEO_Pos) +#define DAC_EVCTRL_RESRDYEO(value) (DAC_EVCTRL_RESRDYEO_Msk & ((value) << DAC_EVCTRL_RESRDYEO_Pos)) +#define DAC_EVCTRL_MASK _U_(0xFF) /**< \brief (DAC_EVCTRL) MASK Register */ + +/* -------- DAC_INTENCLR : (DAC Offset: 0x04) (R/W 8) Interrupt Enable Clear -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t UNDERRUN0:1; /*!< bit: 0 Underrun 0 Interrupt Enable */ + uint8_t UNDERRUN1:1; /*!< bit: 1 Underrun 1 Interrupt Enable */ + uint8_t EMPTY0:1; /*!< bit: 2 Data Buffer 0 Empty Interrupt Enable */ + uint8_t EMPTY1:1; /*!< bit: 3 Data Buffer 1 Empty Interrupt Enable */ + uint8_t RESRDY0:1; /*!< bit: 4 Result 0 Ready Interrupt Enable */ + uint8_t RESRDY1:1; /*!< bit: 5 Result 1 Ready Interrupt Enable */ + uint8_t OVERRUN0:1; /*!< bit: 6 Overrun 0 Interrupt Enable */ + uint8_t OVERRUN1:1; /*!< bit: 7 Overrun 1 Interrupt Enable */ + } bit; /*!< Structure used for bit access */ + struct { + uint8_t UNDERRUN:2; /*!< bit: 0.. 1 Underrun x Interrupt Enable */ + uint8_t EMPTY:2; /*!< bit: 2.. 3 Data Buffer x Empty Interrupt Enable */ + uint8_t RESRDY:2; /*!< bit: 4.. 5 Result x Ready Interrupt Enable */ + uint8_t OVERRUN:2; /*!< bit: 6.. 7 Overrun x Interrupt Enable */ + } vec; /*!< Structure used for vec access */ + uint8_t reg; /*!< Type used for register access */ +} DAC_INTENCLR_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DAC_INTENCLR_OFFSET 0x04 /**< \brief (DAC_INTENCLR offset) Interrupt Enable Clear */ +#define DAC_INTENCLR_RESETVALUE _U_(0x00) /**< \brief (DAC_INTENCLR reset_value) Interrupt Enable Clear */ + +#define DAC_INTENCLR_UNDERRUN0_Pos 0 /**< \brief (DAC_INTENCLR) Underrun 0 Interrupt Enable */ +#define DAC_INTENCLR_UNDERRUN0 (_U_(1) << DAC_INTENCLR_UNDERRUN0_Pos) +#define DAC_INTENCLR_UNDERRUN1_Pos 1 /**< \brief (DAC_INTENCLR) Underrun 1 Interrupt Enable */ +#define DAC_INTENCLR_UNDERRUN1 (_U_(1) << DAC_INTENCLR_UNDERRUN1_Pos) +#define DAC_INTENCLR_UNDERRUN_Pos 0 /**< \brief (DAC_INTENCLR) Underrun x Interrupt Enable */ +#define DAC_INTENCLR_UNDERRUN_Msk (_U_(0x3) << DAC_INTENCLR_UNDERRUN_Pos) +#define DAC_INTENCLR_UNDERRUN(value) (DAC_INTENCLR_UNDERRUN_Msk & ((value) << DAC_INTENCLR_UNDERRUN_Pos)) +#define DAC_INTENCLR_EMPTY0_Pos 2 /**< \brief (DAC_INTENCLR) Data Buffer 0 Empty Interrupt Enable */ +#define DAC_INTENCLR_EMPTY0 (_U_(1) << DAC_INTENCLR_EMPTY0_Pos) +#define DAC_INTENCLR_EMPTY1_Pos 3 /**< \brief (DAC_INTENCLR) Data Buffer 1 Empty Interrupt Enable */ +#define DAC_INTENCLR_EMPTY1 (_U_(1) << DAC_INTENCLR_EMPTY1_Pos) +#define DAC_INTENCLR_EMPTY_Pos 2 /**< \brief (DAC_INTENCLR) Data Buffer x Empty Interrupt Enable */ +#define DAC_INTENCLR_EMPTY_Msk (_U_(0x3) << DAC_INTENCLR_EMPTY_Pos) +#define DAC_INTENCLR_EMPTY(value) (DAC_INTENCLR_EMPTY_Msk & ((value) << DAC_INTENCLR_EMPTY_Pos)) +#define DAC_INTENCLR_RESRDY0_Pos 4 /**< \brief (DAC_INTENCLR) Result 0 Ready Interrupt Enable */ +#define DAC_INTENCLR_RESRDY0 (_U_(1) << DAC_INTENCLR_RESRDY0_Pos) +#define DAC_INTENCLR_RESRDY1_Pos 5 /**< \brief (DAC_INTENCLR) Result 1 Ready Interrupt Enable */ +#define DAC_INTENCLR_RESRDY1 (_U_(1) << DAC_INTENCLR_RESRDY1_Pos) +#define DAC_INTENCLR_RESRDY_Pos 4 /**< \brief (DAC_INTENCLR) Result x Ready Interrupt Enable */ +#define DAC_INTENCLR_RESRDY_Msk (_U_(0x3) << DAC_INTENCLR_RESRDY_Pos) +#define DAC_INTENCLR_RESRDY(value) (DAC_INTENCLR_RESRDY_Msk & ((value) << DAC_INTENCLR_RESRDY_Pos)) +#define DAC_INTENCLR_OVERRUN0_Pos 6 /**< \brief (DAC_INTENCLR) Overrun 0 Interrupt Enable */ +#define DAC_INTENCLR_OVERRUN0 (_U_(1) << DAC_INTENCLR_OVERRUN0_Pos) +#define DAC_INTENCLR_OVERRUN1_Pos 7 /**< \brief (DAC_INTENCLR) Overrun 1 Interrupt Enable */ +#define DAC_INTENCLR_OVERRUN1 (_U_(1) << DAC_INTENCLR_OVERRUN1_Pos) +#define DAC_INTENCLR_OVERRUN_Pos 6 /**< \brief (DAC_INTENCLR) Overrun x Interrupt Enable */ +#define DAC_INTENCLR_OVERRUN_Msk (_U_(0x3) << DAC_INTENCLR_OVERRUN_Pos) +#define DAC_INTENCLR_OVERRUN(value) (DAC_INTENCLR_OVERRUN_Msk & ((value) << DAC_INTENCLR_OVERRUN_Pos)) +#define DAC_INTENCLR_MASK _U_(0xFF) /**< \brief (DAC_INTENCLR) MASK Register */ + +/* -------- DAC_INTENSET : (DAC Offset: 0x05) (R/W 8) Interrupt Enable Set -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t UNDERRUN0:1; /*!< bit: 0 Underrun 0 Interrupt Enable */ + uint8_t UNDERRUN1:1; /*!< bit: 1 Underrun 1 Interrupt Enable */ + uint8_t EMPTY0:1; /*!< bit: 2 Data Buffer 0 Empty Interrupt Enable */ + uint8_t EMPTY1:1; /*!< bit: 3 Data Buffer 1 Empty Interrupt Enable */ + uint8_t RESRDY0:1; /*!< bit: 4 Result 0 Ready Interrupt Enable */ + uint8_t RESRDY1:1; /*!< bit: 5 Result 1 Ready Interrupt Enable */ + uint8_t OVERRUN0:1; /*!< bit: 6 Overrun 0 Interrupt Enable */ + uint8_t OVERRUN1:1; /*!< bit: 7 Overrun 1 Interrupt Enable */ + } bit; /*!< Structure used for bit access */ + struct { + uint8_t UNDERRUN:2; /*!< bit: 0.. 1 Underrun x Interrupt Enable */ + uint8_t EMPTY:2; /*!< bit: 2.. 3 Data Buffer x Empty Interrupt Enable */ + uint8_t RESRDY:2; /*!< bit: 4.. 5 Result x Ready Interrupt Enable */ + uint8_t OVERRUN:2; /*!< bit: 6.. 7 Overrun x Interrupt Enable */ + } vec; /*!< Structure used for vec access */ + uint8_t reg; /*!< Type used for register access */ +} DAC_INTENSET_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DAC_INTENSET_OFFSET 0x05 /**< \brief (DAC_INTENSET offset) Interrupt Enable Set */ +#define DAC_INTENSET_RESETVALUE _U_(0x00) /**< \brief (DAC_INTENSET reset_value) Interrupt Enable Set */ + +#define DAC_INTENSET_UNDERRUN0_Pos 0 /**< \brief (DAC_INTENSET) Underrun 0 Interrupt Enable */ +#define DAC_INTENSET_UNDERRUN0 (_U_(1) << DAC_INTENSET_UNDERRUN0_Pos) +#define DAC_INTENSET_UNDERRUN1_Pos 1 /**< \brief (DAC_INTENSET) Underrun 1 Interrupt Enable */ +#define DAC_INTENSET_UNDERRUN1 (_U_(1) << DAC_INTENSET_UNDERRUN1_Pos) +#define DAC_INTENSET_UNDERRUN_Pos 0 /**< \brief (DAC_INTENSET) Underrun x Interrupt Enable */ +#define DAC_INTENSET_UNDERRUN_Msk (_U_(0x3) << DAC_INTENSET_UNDERRUN_Pos) +#define DAC_INTENSET_UNDERRUN(value) (DAC_INTENSET_UNDERRUN_Msk & ((value) << DAC_INTENSET_UNDERRUN_Pos)) +#define DAC_INTENSET_EMPTY0_Pos 2 /**< \brief (DAC_INTENSET) Data Buffer 0 Empty Interrupt Enable */ +#define DAC_INTENSET_EMPTY0 (_U_(1) << DAC_INTENSET_EMPTY0_Pos) +#define DAC_INTENSET_EMPTY1_Pos 3 /**< \brief (DAC_INTENSET) Data Buffer 1 Empty Interrupt Enable */ +#define DAC_INTENSET_EMPTY1 (_U_(1) << DAC_INTENSET_EMPTY1_Pos) +#define DAC_INTENSET_EMPTY_Pos 2 /**< \brief (DAC_INTENSET) Data Buffer x Empty Interrupt Enable */ +#define DAC_INTENSET_EMPTY_Msk (_U_(0x3) << DAC_INTENSET_EMPTY_Pos) +#define DAC_INTENSET_EMPTY(value) (DAC_INTENSET_EMPTY_Msk & ((value) << DAC_INTENSET_EMPTY_Pos)) +#define DAC_INTENSET_RESRDY0_Pos 4 /**< \brief (DAC_INTENSET) Result 0 Ready Interrupt Enable */ +#define DAC_INTENSET_RESRDY0 (_U_(1) << DAC_INTENSET_RESRDY0_Pos) +#define DAC_INTENSET_RESRDY1_Pos 5 /**< \brief (DAC_INTENSET) Result 1 Ready Interrupt Enable */ +#define DAC_INTENSET_RESRDY1 (_U_(1) << DAC_INTENSET_RESRDY1_Pos) +#define DAC_INTENSET_RESRDY_Pos 4 /**< \brief (DAC_INTENSET) Result x Ready Interrupt Enable */ +#define DAC_INTENSET_RESRDY_Msk (_U_(0x3) << DAC_INTENSET_RESRDY_Pos) +#define DAC_INTENSET_RESRDY(value) (DAC_INTENSET_RESRDY_Msk & ((value) << DAC_INTENSET_RESRDY_Pos)) +#define DAC_INTENSET_OVERRUN0_Pos 6 /**< \brief (DAC_INTENSET) Overrun 0 Interrupt Enable */ +#define DAC_INTENSET_OVERRUN0 (_U_(1) << DAC_INTENSET_OVERRUN0_Pos) +#define DAC_INTENSET_OVERRUN1_Pos 7 /**< \brief (DAC_INTENSET) Overrun 1 Interrupt Enable */ +#define DAC_INTENSET_OVERRUN1 (_U_(1) << DAC_INTENSET_OVERRUN1_Pos) +#define DAC_INTENSET_OVERRUN_Pos 6 /**< \brief (DAC_INTENSET) Overrun x Interrupt Enable */ +#define DAC_INTENSET_OVERRUN_Msk (_U_(0x3) << DAC_INTENSET_OVERRUN_Pos) +#define DAC_INTENSET_OVERRUN(value) (DAC_INTENSET_OVERRUN_Msk & ((value) << DAC_INTENSET_OVERRUN_Pos)) +#define DAC_INTENSET_MASK _U_(0xFF) /**< \brief (DAC_INTENSET) MASK Register */ + +/* -------- DAC_INTFLAG : (DAC Offset: 0x06) (R/W 8) Interrupt Flag Status and Clear -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { // __I to avoid read-modify-write on write-to-clear register + struct { + __I uint8_t UNDERRUN0:1; /*!< bit: 0 Result 0 Underrun */ + __I uint8_t UNDERRUN1:1; /*!< bit: 1 Result 1 Underrun */ + __I uint8_t EMPTY0:1; /*!< bit: 2 Data Buffer 0 Empty */ + __I uint8_t EMPTY1:1; /*!< bit: 3 Data Buffer 1 Empty */ + __I uint8_t RESRDY0:1; /*!< bit: 4 Result 0 Ready */ + __I uint8_t RESRDY1:1; /*!< bit: 5 Result 1 Ready */ + __I uint8_t OVERRUN0:1; /*!< bit: 6 Result 0 Overrun */ + __I uint8_t OVERRUN1:1; /*!< bit: 7 Result 1 Overrun */ + } bit; /*!< Structure used for bit access */ + struct { + __I uint8_t UNDERRUN:2; /*!< bit: 0.. 1 Result x Underrun */ + __I uint8_t EMPTY:2; /*!< bit: 2.. 3 Data Buffer x Empty */ + __I uint8_t RESRDY:2; /*!< bit: 4.. 5 Result x Ready */ + __I uint8_t OVERRUN:2; /*!< bit: 6.. 7 Result x Overrun */ + } vec; /*!< Structure used for vec access */ + uint8_t reg; /*!< Type used for register access */ +} DAC_INTFLAG_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DAC_INTFLAG_OFFSET 0x06 /**< \brief (DAC_INTFLAG offset) Interrupt Flag Status and Clear */ +#define DAC_INTFLAG_RESETVALUE _U_(0x00) /**< \brief (DAC_INTFLAG reset_value) Interrupt Flag Status and Clear */ + +#define DAC_INTFLAG_UNDERRUN0_Pos 0 /**< \brief (DAC_INTFLAG) Result 0 Underrun */ +#define DAC_INTFLAG_UNDERRUN0 (_U_(1) << DAC_INTFLAG_UNDERRUN0_Pos) +#define DAC_INTFLAG_UNDERRUN1_Pos 1 /**< \brief (DAC_INTFLAG) Result 1 Underrun */ +#define DAC_INTFLAG_UNDERRUN1 (_U_(1) << DAC_INTFLAG_UNDERRUN1_Pos) +#define DAC_INTFLAG_UNDERRUN_Pos 0 /**< \brief (DAC_INTFLAG) Result x Underrun */ +#define DAC_INTFLAG_UNDERRUN_Msk (_U_(0x3) << DAC_INTFLAG_UNDERRUN_Pos) +#define DAC_INTFLAG_UNDERRUN(value) (DAC_INTFLAG_UNDERRUN_Msk & ((value) << DAC_INTFLAG_UNDERRUN_Pos)) +#define DAC_INTFLAG_EMPTY0_Pos 2 /**< \brief (DAC_INTFLAG) Data Buffer 0 Empty */ +#define DAC_INTFLAG_EMPTY0 (_U_(1) << DAC_INTFLAG_EMPTY0_Pos) +#define DAC_INTFLAG_EMPTY1_Pos 3 /**< \brief (DAC_INTFLAG) Data Buffer 1 Empty */ +#define DAC_INTFLAG_EMPTY1 (_U_(1) << DAC_INTFLAG_EMPTY1_Pos) +#define DAC_INTFLAG_EMPTY_Pos 2 /**< \brief (DAC_INTFLAG) Data Buffer x Empty */ +#define DAC_INTFLAG_EMPTY_Msk (_U_(0x3) << DAC_INTFLAG_EMPTY_Pos) +#define DAC_INTFLAG_EMPTY(value) (DAC_INTFLAG_EMPTY_Msk & ((value) << DAC_INTFLAG_EMPTY_Pos)) +#define DAC_INTFLAG_RESRDY0_Pos 4 /**< \brief (DAC_INTFLAG) Result 0 Ready */ +#define DAC_INTFLAG_RESRDY0 (_U_(1) << DAC_INTFLAG_RESRDY0_Pos) +#define DAC_INTFLAG_RESRDY1_Pos 5 /**< \brief (DAC_INTFLAG) Result 1 Ready */ +#define DAC_INTFLAG_RESRDY1 (_U_(1) << DAC_INTFLAG_RESRDY1_Pos) +#define DAC_INTFLAG_RESRDY_Pos 4 /**< \brief (DAC_INTFLAG) Result x Ready */ +#define DAC_INTFLAG_RESRDY_Msk (_U_(0x3) << DAC_INTFLAG_RESRDY_Pos) +#define DAC_INTFLAG_RESRDY(value) (DAC_INTFLAG_RESRDY_Msk & ((value) << DAC_INTFLAG_RESRDY_Pos)) +#define DAC_INTFLAG_OVERRUN0_Pos 6 /**< \brief (DAC_INTFLAG) Result 0 Overrun */ +#define DAC_INTFLAG_OVERRUN0 (_U_(1) << DAC_INTFLAG_OVERRUN0_Pos) +#define DAC_INTFLAG_OVERRUN1_Pos 7 /**< \brief (DAC_INTFLAG) Result 1 Overrun */ +#define DAC_INTFLAG_OVERRUN1 (_U_(1) << DAC_INTFLAG_OVERRUN1_Pos) +#define DAC_INTFLAG_OVERRUN_Pos 6 /**< \brief (DAC_INTFLAG) Result x Overrun */ +#define DAC_INTFLAG_OVERRUN_Msk (_U_(0x3) << DAC_INTFLAG_OVERRUN_Pos) +#define DAC_INTFLAG_OVERRUN(value) (DAC_INTFLAG_OVERRUN_Msk & ((value) << DAC_INTFLAG_OVERRUN_Pos)) +#define DAC_INTFLAG_MASK _U_(0xFF) /**< \brief (DAC_INTFLAG) MASK Register */ + +/* -------- DAC_STATUS : (DAC Offset: 0x07) (R/ 8) Status -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t READY0:1; /*!< bit: 0 DAC 0 Startup Ready */ + uint8_t READY1:1; /*!< bit: 1 DAC 1 Startup Ready */ + uint8_t EOC0:1; /*!< bit: 2 DAC 0 End of Conversion */ + uint8_t EOC1:1; /*!< bit: 3 DAC 1 End of Conversion */ + uint8_t :4; /*!< bit: 4.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint8_t READY:2; /*!< bit: 0.. 1 DAC x Startup Ready */ + uint8_t EOC:2; /*!< bit: 2.. 3 DAC x End of Conversion */ + uint8_t :4; /*!< bit: 4.. 7 Reserved */ + } vec; /*!< Structure used for vec access */ + uint8_t reg; /*!< Type used for register access */ +} DAC_STATUS_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DAC_STATUS_OFFSET 0x07 /**< \brief (DAC_STATUS offset) Status */ +#define DAC_STATUS_RESETVALUE _U_(0x00) /**< \brief (DAC_STATUS reset_value) Status */ + +#define DAC_STATUS_READY0_Pos 0 /**< \brief (DAC_STATUS) DAC 0 Startup Ready */ +#define DAC_STATUS_READY0 (_U_(1) << DAC_STATUS_READY0_Pos) +#define DAC_STATUS_READY1_Pos 1 /**< \brief (DAC_STATUS) DAC 1 Startup Ready */ +#define DAC_STATUS_READY1 (_U_(1) << DAC_STATUS_READY1_Pos) +#define DAC_STATUS_READY_Pos 0 /**< \brief (DAC_STATUS) DAC x Startup Ready */ +#define DAC_STATUS_READY_Msk (_U_(0x3) << DAC_STATUS_READY_Pos) +#define DAC_STATUS_READY(value) (DAC_STATUS_READY_Msk & ((value) << DAC_STATUS_READY_Pos)) +#define DAC_STATUS_EOC0_Pos 2 /**< \brief (DAC_STATUS) DAC 0 End of Conversion */ +#define DAC_STATUS_EOC0 (_U_(1) << DAC_STATUS_EOC0_Pos) +#define DAC_STATUS_EOC1_Pos 3 /**< \brief (DAC_STATUS) DAC 1 End of Conversion */ +#define DAC_STATUS_EOC1 (_U_(1) << DAC_STATUS_EOC1_Pos) +#define DAC_STATUS_EOC_Pos 2 /**< \brief (DAC_STATUS) DAC x End of Conversion */ +#define DAC_STATUS_EOC_Msk (_U_(0x3) << DAC_STATUS_EOC_Pos) +#define DAC_STATUS_EOC(value) (DAC_STATUS_EOC_Msk & ((value) << DAC_STATUS_EOC_Pos)) +#define DAC_STATUS_MASK _U_(0x0F) /**< \brief (DAC_STATUS) MASK Register */ + +/* -------- DAC_SYNCBUSY : (DAC Offset: 0x08) (R/ 32) Synchronization Busy -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t SWRST:1; /*!< bit: 0 Software Reset */ + uint32_t ENABLE:1; /*!< bit: 1 DAC Enable Status */ + uint32_t DATA0:1; /*!< bit: 2 Data DAC 0 */ + uint32_t DATA1:1; /*!< bit: 3 Data DAC 1 */ + uint32_t DATABUF0:1; /*!< bit: 4 Data Buffer DAC 0 */ + uint32_t DATABUF1:1; /*!< bit: 5 Data Buffer DAC 1 */ + uint32_t :26; /*!< bit: 6..31 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint32_t :2; /*!< bit: 0.. 1 Reserved */ + uint32_t DATA:2; /*!< bit: 2.. 3 Data DAC x */ + uint32_t DATABUF:2; /*!< bit: 4.. 5 Data Buffer DAC x */ + uint32_t :26; /*!< bit: 6..31 Reserved */ + } vec; /*!< Structure used for vec access */ + uint32_t reg; /*!< Type used for register access */ +} DAC_SYNCBUSY_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DAC_SYNCBUSY_OFFSET 0x08 /**< \brief (DAC_SYNCBUSY offset) Synchronization Busy */ +#define DAC_SYNCBUSY_RESETVALUE _U_(0x00000000) /**< \brief (DAC_SYNCBUSY reset_value) Synchronization Busy */ + +#define DAC_SYNCBUSY_SWRST_Pos 0 /**< \brief (DAC_SYNCBUSY) Software Reset */ +#define DAC_SYNCBUSY_SWRST (_U_(0x1) << DAC_SYNCBUSY_SWRST_Pos) +#define DAC_SYNCBUSY_ENABLE_Pos 1 /**< \brief (DAC_SYNCBUSY) DAC Enable Status */ +#define DAC_SYNCBUSY_ENABLE (_U_(0x1) << DAC_SYNCBUSY_ENABLE_Pos) +#define DAC_SYNCBUSY_DATA0_Pos 2 /**< \brief (DAC_SYNCBUSY) Data DAC 0 */ +#define DAC_SYNCBUSY_DATA0 (_U_(1) << DAC_SYNCBUSY_DATA0_Pos) +#define DAC_SYNCBUSY_DATA1_Pos 3 /**< \brief (DAC_SYNCBUSY) Data DAC 1 */ +#define DAC_SYNCBUSY_DATA1 (_U_(1) << DAC_SYNCBUSY_DATA1_Pos) +#define DAC_SYNCBUSY_DATA_Pos 2 /**< \brief (DAC_SYNCBUSY) Data DAC x */ +#define DAC_SYNCBUSY_DATA_Msk (_U_(0x3) << DAC_SYNCBUSY_DATA_Pos) +#define DAC_SYNCBUSY_DATA(value) (DAC_SYNCBUSY_DATA_Msk & ((value) << DAC_SYNCBUSY_DATA_Pos)) +#define DAC_SYNCBUSY_DATABUF0_Pos 4 /**< \brief (DAC_SYNCBUSY) Data Buffer DAC 0 */ +#define DAC_SYNCBUSY_DATABUF0 (_U_(1) << DAC_SYNCBUSY_DATABUF0_Pos) +#define DAC_SYNCBUSY_DATABUF1_Pos 5 /**< \brief (DAC_SYNCBUSY) Data Buffer DAC 1 */ +#define DAC_SYNCBUSY_DATABUF1 (_U_(1) << DAC_SYNCBUSY_DATABUF1_Pos) +#define DAC_SYNCBUSY_DATABUF_Pos 4 /**< \brief (DAC_SYNCBUSY) Data Buffer DAC x */ +#define DAC_SYNCBUSY_DATABUF_Msk (_U_(0x3) << DAC_SYNCBUSY_DATABUF_Pos) +#define DAC_SYNCBUSY_DATABUF(value) (DAC_SYNCBUSY_DATABUF_Msk & ((value) << DAC_SYNCBUSY_DATABUF_Pos)) +#define DAC_SYNCBUSY_MASK _U_(0x0000003F) /**< \brief (DAC_SYNCBUSY) MASK Register */ + +/* -------- DAC_DACCTRL : (DAC Offset: 0x0C) (R/W 16) DAC n Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t LEFTADJ:1; /*!< bit: 0 Left Adjusted Data */ + uint16_t ENABLE:1; /*!< bit: 1 Enable DAC0 */ + uint16_t CCTRL:2; /*!< bit: 2.. 3 Current Control */ + uint16_t :1; /*!< bit: 4 Reserved */ + uint16_t FEXT:1; /*!< bit: 5 Standalone Filter */ + uint16_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */ + uint16_t DITHER:1; /*!< bit: 7 Dithering Mode */ + uint16_t REFRESH:4; /*!< bit: 8..11 Refresh period */ + uint16_t :1; /*!< bit: 12 Reserved */ + uint16_t OSR:3; /*!< bit: 13..15 Sampling Rate */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} DAC_DACCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DAC_DACCTRL_OFFSET 0x0C /**< \brief (DAC_DACCTRL offset) DAC n Control */ +#define DAC_DACCTRL_RESETVALUE _U_(0x0000) /**< \brief (DAC_DACCTRL reset_value) DAC n Control */ + +#define DAC_DACCTRL_LEFTADJ_Pos 0 /**< \brief (DAC_DACCTRL) Left Adjusted Data */ +#define DAC_DACCTRL_LEFTADJ (_U_(0x1) << DAC_DACCTRL_LEFTADJ_Pos) +#define DAC_DACCTRL_ENABLE_Pos 1 /**< \brief (DAC_DACCTRL) Enable DAC0 */ +#define DAC_DACCTRL_ENABLE (_U_(0x1) << DAC_DACCTRL_ENABLE_Pos) +#define DAC_DACCTRL_CCTRL_Pos 2 /**< \brief (DAC_DACCTRL) Current Control */ +#define DAC_DACCTRL_CCTRL_Msk (_U_(0x3) << DAC_DACCTRL_CCTRL_Pos) +#define DAC_DACCTRL_CCTRL(value) (DAC_DACCTRL_CCTRL_Msk & ((value) << DAC_DACCTRL_CCTRL_Pos)) +#define DAC_DACCTRL_CCTRL_CC100K_Val _U_(0x0) /**< \brief (DAC_DACCTRL) GCLK_DAC ≤ 1.2MHz (100kSPS) */ +#define DAC_DACCTRL_CCTRL_CC1M_Val _U_(0x1) /**< \brief (DAC_DACCTRL) 1.2MHz < GCLK_DAC ≤ 6MHz (500kSPS) */ +#define DAC_DACCTRL_CCTRL_CC12M_Val _U_(0x2) /**< \brief (DAC_DACCTRL) 6MHz < GCLK_DAC ≤ 12MHz (1MSPS) */ +#define DAC_DACCTRL_CCTRL_CC100K (DAC_DACCTRL_CCTRL_CC100K_Val << DAC_DACCTRL_CCTRL_Pos) +#define DAC_DACCTRL_CCTRL_CC1M (DAC_DACCTRL_CCTRL_CC1M_Val << DAC_DACCTRL_CCTRL_Pos) +#define DAC_DACCTRL_CCTRL_CC12M (DAC_DACCTRL_CCTRL_CC12M_Val << DAC_DACCTRL_CCTRL_Pos) +#define DAC_DACCTRL_FEXT_Pos 5 /**< \brief (DAC_DACCTRL) Standalone Filter */ +#define DAC_DACCTRL_FEXT (_U_(0x1) << DAC_DACCTRL_FEXT_Pos) +#define DAC_DACCTRL_RUNSTDBY_Pos 6 /**< \brief (DAC_DACCTRL) Run in Standby */ +#define DAC_DACCTRL_RUNSTDBY (_U_(0x1) << DAC_DACCTRL_RUNSTDBY_Pos) +#define DAC_DACCTRL_DITHER_Pos 7 /**< \brief (DAC_DACCTRL) Dithering Mode */ +#define DAC_DACCTRL_DITHER (_U_(0x1) << DAC_DACCTRL_DITHER_Pos) +#define DAC_DACCTRL_REFRESH_Pos 8 /**< \brief (DAC_DACCTRL) Refresh period */ +#define DAC_DACCTRL_REFRESH_Msk (_U_(0xF) << DAC_DACCTRL_REFRESH_Pos) +#define DAC_DACCTRL_REFRESH(value) (DAC_DACCTRL_REFRESH_Msk & ((value) << DAC_DACCTRL_REFRESH_Pos)) +#define DAC_DACCTRL_OSR_Pos 13 /**< \brief (DAC_DACCTRL) Sampling Rate */ +#define DAC_DACCTRL_OSR_Msk (_U_(0x7) << DAC_DACCTRL_OSR_Pos) +#define DAC_DACCTRL_OSR(value) (DAC_DACCTRL_OSR_Msk & ((value) << DAC_DACCTRL_OSR_Pos)) +#define DAC_DACCTRL_MASK _U_(0xEFEF) /**< \brief (DAC_DACCTRL) MASK Register */ + +/* -------- DAC_DATA : (DAC Offset: 0x10) ( /W 16) DAC n Data -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t DATA:16; /*!< bit: 0..15 DAC0 Data */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} DAC_DATA_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DAC_DATA_OFFSET 0x10 /**< \brief (DAC_DATA offset) DAC n Data */ +#define DAC_DATA_RESETVALUE _U_(0x0000) /**< \brief (DAC_DATA reset_value) DAC n Data */ + +#define DAC_DATA_DATA_Pos 0 /**< \brief (DAC_DATA) DAC0 Data */ +#define DAC_DATA_DATA_Msk (_U_(0xFFFF) << DAC_DATA_DATA_Pos) +#define DAC_DATA_DATA(value) (DAC_DATA_DATA_Msk & ((value) << DAC_DATA_DATA_Pos)) +#define DAC_DATA_MASK _U_(0xFFFF) /**< \brief (DAC_DATA) MASK Register */ + +/* -------- DAC_DATABUF : (DAC Offset: 0x14) ( /W 16) DAC n Data Buffer -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t DATABUF:16; /*!< bit: 0..15 DAC0 Data Buffer */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} DAC_DATABUF_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DAC_DATABUF_OFFSET 0x14 /**< \brief (DAC_DATABUF offset) DAC n Data Buffer */ +#define DAC_DATABUF_RESETVALUE _U_(0x0000) /**< \brief (DAC_DATABUF reset_value) DAC n Data Buffer */ + +#define DAC_DATABUF_DATABUF_Pos 0 /**< \brief (DAC_DATABUF) DAC0 Data Buffer */ +#define DAC_DATABUF_DATABUF_Msk (_U_(0xFFFF) << DAC_DATABUF_DATABUF_Pos) +#define DAC_DATABUF_DATABUF(value) (DAC_DATABUF_DATABUF_Msk & ((value) << DAC_DATABUF_DATABUF_Pos)) +#define DAC_DATABUF_MASK _U_(0xFFFF) /**< \brief (DAC_DATABUF) MASK Register */ + +/* -------- DAC_DBGCTRL : (DAC Offset: 0x18) (R/W 8) Debug Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t DBGRUN:1; /*!< bit: 0 Debug Run */ + uint8_t :7; /*!< bit: 1.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} DAC_DBGCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DAC_DBGCTRL_OFFSET 0x18 /**< \brief (DAC_DBGCTRL offset) Debug Control */ +#define DAC_DBGCTRL_RESETVALUE _U_(0x00) /**< \brief (DAC_DBGCTRL reset_value) Debug Control */ + +#define DAC_DBGCTRL_DBGRUN_Pos 0 /**< \brief (DAC_DBGCTRL) Debug Run */ +#define DAC_DBGCTRL_DBGRUN (_U_(0x1) << DAC_DBGCTRL_DBGRUN_Pos) +#define DAC_DBGCTRL_MASK _U_(0x01) /**< \brief (DAC_DBGCTRL) MASK Register */ + +/* -------- DAC_RESULT : (DAC Offset: 0x1C) (R/ 16) Filter Result -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t RESULT:16; /*!< bit: 0..15 Filter Result */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} DAC_RESULT_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DAC_RESULT_OFFSET 0x1C /**< \brief (DAC_RESULT offset) Filter Result */ +#define DAC_RESULT_RESETVALUE _U_(0x0000) /**< \brief (DAC_RESULT reset_value) Filter Result */ + +#define DAC_RESULT_RESULT_Pos 0 /**< \brief (DAC_RESULT) Filter Result */ +#define DAC_RESULT_RESULT_Msk (_U_(0xFFFF) << DAC_RESULT_RESULT_Pos) +#define DAC_RESULT_RESULT(value) (DAC_RESULT_RESULT_Msk & ((value) << DAC_RESULT_RESULT_Pos)) +#define DAC_RESULT_MASK _U_(0xFFFF) /**< \brief (DAC_RESULT) MASK Register */ + +/** \brief DAC hardware registers */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef struct { + __IO DAC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 8) Control A */ + __IO DAC_CTRLB_Type CTRLB; /**< \brief Offset: 0x01 (R/W 8) Control B */ + __IO DAC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x02 (R/W 8) Event Control */ + RoReg8 Reserved1[0x1]; + __IO DAC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x04 (R/W 8) Interrupt Enable Clear */ + __IO DAC_INTENSET_Type INTENSET; /**< \brief Offset: 0x05 (R/W 8) Interrupt Enable Set */ + __IO DAC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x06 (R/W 8) Interrupt Flag Status and Clear */ + __I DAC_STATUS_Type STATUS; /**< \brief Offset: 0x07 (R/ 8) Status */ + __I DAC_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x08 (R/ 32) Synchronization Busy */ + __IO DAC_DACCTRL_Type DACCTRL[2]; /**< \brief Offset: 0x0C (R/W 16) DAC n Control */ + __O DAC_DATA_Type DATA[2]; /**< \brief Offset: 0x10 ( /W 16) DAC n Data */ + __O DAC_DATABUF_Type DATABUF[2]; /**< \brief Offset: 0x14 ( /W 16) DAC n Data Buffer */ + __IO DAC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x18 (R/W 8) Debug Control */ + RoReg8 Reserved2[0x3]; + __I DAC_RESULT_Type RESULT[2]; /**< \brief Offset: 0x1C (R/ 16) Filter Result */ +} Dac; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/*@}*/ + +#endif /* _SAME54_DAC_COMPONENT_ */ diff --git a/arch/arm/SAME54/SAME54A/mcu/inc/component/dmac.h b/arch/arm/SAME54/SAME54A/mcu/inc/component/dmac.h index e4486c99..a611b79d 100644 --- a/arch/arm/SAME54/SAME54A/mcu/inc/component/dmac.h +++ b/arch/arm/SAME54/SAME54A/mcu/inc/component/dmac.h @@ -1,1125 +1,1416 @@ -/** - * \brief Component description for DMAC - * - * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries. - * - * Subject to your compliance with these terms, you may use Microchip software and any derivatives - * exclusively with Microchip products. It is your responsibility to comply with third party license - * terms applicable to your use of third party software (including open source software) that may - * accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, - * APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND - * FITNESS FOR A PARTICULAR PURPOSE. - * - * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF - * MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT - * EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - */ - -/* file generated from device description version 2020-03-12T17:27:04Z */ -#ifndef _SAME54_DMAC_COMPONENT_H_ -#define _SAME54_DMAC_COMPONENT_H_ - -/* ************************************************************************** */ -/* SOFTWARE API DEFINITION FOR DMAC */ -/* ************************************************************************** */ - -/* -------- DMAC_BTCTRL : (DMAC Offset: 0x00) (R/W 16) Block Transfer Control -------- */ -#define DMAC_BTCTRL_RESETVALUE _U_(0x00) /**< (DMAC_BTCTRL) Block Transfer Control Reset Value */ - -#define DMAC_BTCTRL_VALID_Pos _U_(0) /**< (DMAC_BTCTRL) Descriptor Valid Position */ -#define DMAC_BTCTRL_VALID_Msk (_U_(0x1) << DMAC_BTCTRL_VALID_Pos) /**< (DMAC_BTCTRL) Descriptor Valid Mask */ -#define DMAC_BTCTRL_VALID(value) (DMAC_BTCTRL_VALID_Msk & ((value) << DMAC_BTCTRL_VALID_Pos)) -#define DMAC_BTCTRL_EVOSEL_Pos _U_(1) /**< (DMAC_BTCTRL) Block Event Output Selection Position */ -#define DMAC_BTCTRL_EVOSEL_Msk (_U_(0x3) << DMAC_BTCTRL_EVOSEL_Pos) /**< (DMAC_BTCTRL) Block Event Output Selection Mask */ -#define DMAC_BTCTRL_EVOSEL(value) (DMAC_BTCTRL_EVOSEL_Msk & ((value) << DMAC_BTCTRL_EVOSEL_Pos)) -#define DMAC_BTCTRL_EVOSEL_DISABLE_Val _U_(0x0) /**< (DMAC_BTCTRL) Event generation disabled */ -#define DMAC_BTCTRL_EVOSEL_BLOCK_Val _U_(0x1) /**< (DMAC_BTCTRL) Block event strobe */ -#define DMAC_BTCTRL_EVOSEL_BURST_Val _U_(0x3) /**< (DMAC_BTCTRL) Burst event strobe */ -#define DMAC_BTCTRL_EVOSEL_DISABLE (DMAC_BTCTRL_EVOSEL_DISABLE_Val << DMAC_BTCTRL_EVOSEL_Pos) /**< (DMAC_BTCTRL) Event generation disabled Position */ -#define DMAC_BTCTRL_EVOSEL_BLOCK (DMAC_BTCTRL_EVOSEL_BLOCK_Val << DMAC_BTCTRL_EVOSEL_Pos) /**< (DMAC_BTCTRL) Block event strobe Position */ -#define DMAC_BTCTRL_EVOSEL_BURST (DMAC_BTCTRL_EVOSEL_BURST_Val << DMAC_BTCTRL_EVOSEL_Pos) /**< (DMAC_BTCTRL) Burst event strobe Position */ -#define DMAC_BTCTRL_BLOCKACT_Pos _U_(3) /**< (DMAC_BTCTRL) Block Action Position */ -#define DMAC_BTCTRL_BLOCKACT_Msk (_U_(0x3) << DMAC_BTCTRL_BLOCKACT_Pos) /**< (DMAC_BTCTRL) Block Action Mask */ -#define DMAC_BTCTRL_BLOCKACT(value) (DMAC_BTCTRL_BLOCKACT_Msk & ((value) << DMAC_BTCTRL_BLOCKACT_Pos)) -#define DMAC_BTCTRL_BLOCKACT_NOACT_Val _U_(0x0) /**< (DMAC_BTCTRL) Channel will be disabled if it is the last block transfer in the transaction */ -#define DMAC_BTCTRL_BLOCKACT_INT_Val _U_(0x1) /**< (DMAC_BTCTRL) Channel will be disabled if it is the last block transfer in the transaction and block interrupt */ -#define DMAC_BTCTRL_BLOCKACT_SUSPEND_Val _U_(0x2) /**< (DMAC_BTCTRL) Channel suspend operation is completed */ -#define DMAC_BTCTRL_BLOCKACT_BOTH_Val _U_(0x3) /**< (DMAC_BTCTRL) Both channel suspend operation and block interrupt */ -#define DMAC_BTCTRL_BLOCKACT_NOACT (DMAC_BTCTRL_BLOCKACT_NOACT_Val << DMAC_BTCTRL_BLOCKACT_Pos) /**< (DMAC_BTCTRL) Channel will be disabled if it is the last block transfer in the transaction Position */ -#define DMAC_BTCTRL_BLOCKACT_INT (DMAC_BTCTRL_BLOCKACT_INT_Val << DMAC_BTCTRL_BLOCKACT_Pos) /**< (DMAC_BTCTRL) Channel will be disabled if it is the last block transfer in the transaction and block interrupt Position */ -#define DMAC_BTCTRL_BLOCKACT_SUSPEND (DMAC_BTCTRL_BLOCKACT_SUSPEND_Val << DMAC_BTCTRL_BLOCKACT_Pos) /**< (DMAC_BTCTRL) Channel suspend operation is completed Position */ -#define DMAC_BTCTRL_BLOCKACT_BOTH (DMAC_BTCTRL_BLOCKACT_BOTH_Val << DMAC_BTCTRL_BLOCKACT_Pos) /**< (DMAC_BTCTRL) Both channel suspend operation and block interrupt Position */ -#define DMAC_BTCTRL_BEATSIZE_Pos _U_(8) /**< (DMAC_BTCTRL) Beat Size Position */ -#define DMAC_BTCTRL_BEATSIZE_Msk (_U_(0x3) << DMAC_BTCTRL_BEATSIZE_Pos) /**< (DMAC_BTCTRL) Beat Size Mask */ -#define DMAC_BTCTRL_BEATSIZE(value) (DMAC_BTCTRL_BEATSIZE_Msk & ((value) << DMAC_BTCTRL_BEATSIZE_Pos)) -#define DMAC_BTCTRL_BEATSIZE_BYTE_Val _U_(0x0) /**< (DMAC_BTCTRL) 8-bit bus transfer */ -#define DMAC_BTCTRL_BEATSIZE_HWORD_Val _U_(0x1) /**< (DMAC_BTCTRL) 16-bit bus transfer */ -#define DMAC_BTCTRL_BEATSIZE_WORD_Val _U_(0x2) /**< (DMAC_BTCTRL) 32-bit bus transfer */ -#define DMAC_BTCTRL_BEATSIZE_BYTE (DMAC_BTCTRL_BEATSIZE_BYTE_Val << DMAC_BTCTRL_BEATSIZE_Pos) /**< (DMAC_BTCTRL) 8-bit bus transfer Position */ -#define DMAC_BTCTRL_BEATSIZE_HWORD (DMAC_BTCTRL_BEATSIZE_HWORD_Val << DMAC_BTCTRL_BEATSIZE_Pos) /**< (DMAC_BTCTRL) 16-bit bus transfer Position */ -#define DMAC_BTCTRL_BEATSIZE_WORD (DMAC_BTCTRL_BEATSIZE_WORD_Val << DMAC_BTCTRL_BEATSIZE_Pos) /**< (DMAC_BTCTRL) 32-bit bus transfer Position */ -#define DMAC_BTCTRL_SRCINC_Pos _U_(10) /**< (DMAC_BTCTRL) Source Address Increment Enable Position */ -#define DMAC_BTCTRL_SRCINC_Msk (_U_(0x1) << DMAC_BTCTRL_SRCINC_Pos) /**< (DMAC_BTCTRL) Source Address Increment Enable Mask */ -#define DMAC_BTCTRL_SRCINC(value) (DMAC_BTCTRL_SRCINC_Msk & ((value) << DMAC_BTCTRL_SRCINC_Pos)) -#define DMAC_BTCTRL_DSTINC_Pos _U_(11) /**< (DMAC_BTCTRL) Destination Address Increment Enable Position */ -#define DMAC_BTCTRL_DSTINC_Msk (_U_(0x1) << DMAC_BTCTRL_DSTINC_Pos) /**< (DMAC_BTCTRL) Destination Address Increment Enable Mask */ -#define DMAC_BTCTRL_DSTINC(value) (DMAC_BTCTRL_DSTINC_Msk & ((value) << DMAC_BTCTRL_DSTINC_Pos)) -#define DMAC_BTCTRL_STEPSEL_Pos _U_(12) /**< (DMAC_BTCTRL) Step Selection Position */ -#define DMAC_BTCTRL_STEPSEL_Msk (_U_(0x1) << DMAC_BTCTRL_STEPSEL_Pos) /**< (DMAC_BTCTRL) Step Selection Mask */ -#define DMAC_BTCTRL_STEPSEL(value) (DMAC_BTCTRL_STEPSEL_Msk & ((value) << DMAC_BTCTRL_STEPSEL_Pos)) -#define DMAC_BTCTRL_STEPSEL_DST_Val _U_(0x0) /**< (DMAC_BTCTRL) Step size settings apply to the destination address */ -#define DMAC_BTCTRL_STEPSEL_SRC_Val _U_(0x1) /**< (DMAC_BTCTRL) Step size settings apply to the source address */ -#define DMAC_BTCTRL_STEPSEL_DST (DMAC_BTCTRL_STEPSEL_DST_Val << DMAC_BTCTRL_STEPSEL_Pos) /**< (DMAC_BTCTRL) Step size settings apply to the destination address Position */ -#define DMAC_BTCTRL_STEPSEL_SRC (DMAC_BTCTRL_STEPSEL_SRC_Val << DMAC_BTCTRL_STEPSEL_Pos) /**< (DMAC_BTCTRL) Step size settings apply to the source address Position */ -#define DMAC_BTCTRL_STEPSIZE_Pos _U_(13) /**< (DMAC_BTCTRL) Address Increment Step Size Position */ -#define DMAC_BTCTRL_STEPSIZE_Msk (_U_(0x7) << DMAC_BTCTRL_STEPSIZE_Pos) /**< (DMAC_BTCTRL) Address Increment Step Size Mask */ -#define DMAC_BTCTRL_STEPSIZE(value) (DMAC_BTCTRL_STEPSIZE_Msk & ((value) << DMAC_BTCTRL_STEPSIZE_Pos)) -#define DMAC_BTCTRL_STEPSIZE_X1_Val _U_(0x0) /**< (DMAC_BTCTRL) Next ADDR = ADDR + (1< 8 bits, 1 -> 16 bits +#define USB_EPNUM 8 // parameter for rtl : max of ENDPOINT and PIPE NUM +#define USB_EPT_NUM 8 // Number of USB end points +#define USB_GCLK_ID 10 // Index of Generic Clock +#define USB_INITIAL_CONTROL_QOS 3 // CONTROL QOS RESET value +#define USB_INITIAL_DATA_QOS 3 // DATA QOS RESET value +#define USB_MISSING_SOF_DET_IMPLEMENTED 1 // 48 mHz xPLL feature implemented +#define USB_PIPE_NUM 8 // Number of USB pipes +#define USB_SYSTEM_CLOCK_IS_CKUSB 0 // Dual (1'b0) or Single (1'b1) clock system +#define USB_USB_2_AHB_FIFO_DEPTH 4 // bytes number, should be at least 2, and 2^n (4,8,16 ...) +#define USB_USB_2_AHB_RD_DATA_BITS 16 // 8, 16 or 32, here : 8-bits is required as UTMI interface should work in 8-bits mode +#define USB_USB_2_AHB_RD_THRESHOLD 2 // as soon as there are 16 bytes-free inside the fifo, ahb read transfer is requested +#define USB_USB_2_AHB_WR_DATA_BITS 8 // 8, 16 or 32 : here : 8-bits is required as UTMI interface should work in 8-bits mode + +#endif /* _SAME54_USB_INSTANCE_ */ diff --git a/arch/arm/SAME54/SAME54A/mcu/inc/instance/wdt.h b/arch/arm/SAME54/SAME54A/mcu/inc/instance/wdt.h new file mode 100644 index 00000000..c96d7705 --- /dev/null +++ b/arch/arm/SAME54/SAME54A/mcu/inc/instance/wdt.h @@ -0,0 +1,55 @@ +/** + * \file + * + * \brief Instance description for WDT + * + * Copyright (c) 2019 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAME54_WDT_INSTANCE_ +#define _SAME54_WDT_INSTANCE_ + +/* ========== Register definition for WDT peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_WDT_CTRLA (0x40002000) /**< \brief (WDT) Control */ +#define REG_WDT_CONFIG (0x40002001) /**< \brief (WDT) Configuration */ +#define REG_WDT_EWCTRL (0x40002002) /**< \brief (WDT) Early Warning Interrupt Control */ +#define REG_WDT_INTENCLR (0x40002004) /**< \brief (WDT) Interrupt Enable Clear */ +#define REG_WDT_INTENSET (0x40002005) /**< \brief (WDT) Interrupt Enable Set */ +#define REG_WDT_INTFLAG (0x40002006) /**< \brief (WDT) Interrupt Flag Status and Clear */ +#define REG_WDT_SYNCBUSY (0x40002008) /**< \brief (WDT) Synchronization Busy */ +#define REG_WDT_CLEAR (0x4000200C) /**< \brief (WDT) Clear */ +#else +#define REG_WDT_CTRLA (*(RwReg8 *)0x40002000UL) /**< \brief (WDT) Control */ +#define REG_WDT_CONFIG (*(RwReg8 *)0x40002001UL) /**< \brief (WDT) Configuration */ +#define REG_WDT_EWCTRL (*(RwReg8 *)0x40002002UL) /**< \brief (WDT) Early Warning Interrupt Control */ +#define REG_WDT_INTENCLR (*(RwReg8 *)0x40002004UL) /**< \brief (WDT) Interrupt Enable Clear */ +#define REG_WDT_INTENSET (*(RwReg8 *)0x40002005UL) /**< \brief (WDT) Interrupt Enable Set */ +#define REG_WDT_INTFLAG (*(RwReg8 *)0x40002006UL) /**< \brief (WDT) Interrupt Flag Status and Clear */ +#define REG_WDT_SYNCBUSY (*(RoReg *)0x40002008UL) /**< \brief (WDT) Synchronization Busy */ +#define REG_WDT_CLEAR (*(WoReg8 *)0x4000200CUL) /**< \brief (WDT) Clear */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + + +#endif /* _SAME54_WDT_INSTANCE_ */ diff --git a/arch/arm/SAME54/SAME54A/mcu/inc/pio/same54n19a.h b/arch/arm/SAME54/SAME54A/mcu/inc/pio/same54n19a.h index 2580a7d0..8d51a313 100644 --- a/arch/arm/SAME54/SAME54A/mcu/inc/pio/same54n19a.h +++ b/arch/arm/SAME54/SAME54A/mcu/inc/pio/same54n19a.h @@ -1,3239 +1,2688 @@ -/** - * \brief Peripheral I/O description for SAME54N19A - * - * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries. - * - * Subject to your compliance with these terms, you may use Microchip software and any derivatives - * exclusively with Microchip products. It is your responsibility to comply with third party license - * terms applicable to your use of third party software (including open source software) that may - * accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, - * APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND - * FITNESS FOR A PARTICULAR PURPOSE. - * - * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF - * MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT - * EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - */ - -/* file generated from device description version 2020-03-12T17:26:56Z */ -#ifndef _SAME54N19A_GPIO_H_ -#define _SAME54N19A_GPIO_H_ - -/* ========== Peripheral I/O pin numbers ========== */ -#define PIN_PA00 ( 0 ) /**< Pin Number for PA00 */ -#define PIN_PA01 ( 1 ) /**< Pin Number for PA01 */ -#define PIN_PA02 ( 2 ) /**< Pin Number for PA02 */ -#define PIN_PA03 ( 3 ) /**< Pin Number for PA03 */ -#define PIN_PA04 ( 4 ) /**< Pin Number for PA04 */ -#define PIN_PA05 ( 5 ) /**< Pin Number for PA05 */ -#define PIN_PA06 ( 6 ) /**< Pin Number for PA06 */ -#define PIN_PA07 ( 7 ) /**< Pin Number for PA07 */ -#define PIN_PA08 ( 8 ) /**< Pin Number for PA08 */ -#define PIN_PA09 ( 9 ) /**< Pin Number for PA09 */ -#define PIN_PA10 ( 10 ) /**< Pin Number for PA10 */ -#define PIN_PA11 ( 11 ) /**< Pin Number for PA11 */ -#define PIN_PA12 ( 12 ) /**< Pin Number for PA12 */ -#define PIN_PA13 ( 13 ) /**< Pin Number for PA13 */ -#define PIN_PA14 ( 14 ) /**< Pin Number for PA14 */ -#define PIN_PA15 ( 15 ) /**< Pin Number for PA15 */ -#define PIN_PA16 ( 16 ) /**< Pin Number for PA16 */ -#define PIN_PA17 ( 17 ) /**< Pin Number for PA17 */ -#define PIN_PA18 ( 18 ) /**< Pin Number for PA18 */ -#define PIN_PA19 ( 19 ) /**< Pin Number for PA19 */ -#define PIN_PA20 ( 20 ) /**< Pin Number for PA20 */ -#define PIN_PA21 ( 21 ) /**< Pin Number for PA21 */ -#define PIN_PA22 ( 22 ) /**< Pin Number for PA22 */ -#define PIN_PA23 ( 23 ) /**< Pin Number for PA23 */ -#define PIN_PA24 ( 24 ) /**< Pin Number for PA24 */ -#define PIN_PA25 ( 25 ) /**< Pin Number for PA25 */ -#define PIN_PA27 ( 27 ) /**< Pin Number for PA27 */ -#define PIN_PA30 ( 30 ) /**< Pin Number for PA30 */ -#define PIN_PA31 ( 31 ) /**< Pin Number for PA31 */ -#define PIN_PB00 ( 32 ) /**< Pin Number for PB00 */ -#define PIN_PB01 ( 33 ) /**< Pin Number for PB01 */ -#define PIN_PB02 ( 34 ) /**< Pin Number for PB02 */ -#define PIN_PB03 ( 35 ) /**< Pin Number for PB03 */ -#define PIN_PB04 ( 36 ) /**< Pin Number for PB04 */ -#define PIN_PB05 ( 37 ) /**< Pin Number for PB05 */ -#define PIN_PB06 ( 38 ) /**< Pin Number for PB06 */ -#define PIN_PB07 ( 39 ) /**< Pin Number for PB07 */ -#define PIN_PB08 ( 40 ) /**< Pin Number for PB08 */ -#define PIN_PB09 ( 41 ) /**< Pin Number for PB09 */ -#define PIN_PB10 ( 42 ) /**< Pin Number for PB10 */ -#define PIN_PB11 ( 43 ) /**< Pin Number for PB11 */ -#define PIN_PB12 ( 44 ) /**< Pin Number for PB12 */ -#define PIN_PB13 ( 45 ) /**< Pin Number for PB13 */ -#define PIN_PB14 ( 46 ) /**< Pin Number for PB14 */ -#define PIN_PB15 ( 47 ) /**< Pin Number for PB15 */ -#define PIN_PB16 ( 48 ) /**< Pin Number for PB16 */ -#define PIN_PB17 ( 49 ) /**< Pin Number for PB17 */ -#define PIN_PB18 ( 50 ) /**< Pin Number for PB18 */ -#define PIN_PB19 ( 51 ) /**< Pin Number for PB19 */ -#define PIN_PB20 ( 52 ) /**< Pin Number for PB20 */ -#define PIN_PB21 ( 53 ) /**< Pin Number for PB21 */ -#define PIN_PB22 ( 54 ) /**< Pin Number for PB22 */ -#define PIN_PB23 ( 55 ) /**< Pin Number for PB23 */ -#define PIN_PB24 ( 56 ) /**< Pin Number for PB24 */ -#define PIN_PB25 ( 57 ) /**< Pin Number for PB25 */ -#define PIN_PB30 ( 62 ) /**< Pin Number for PB30 */ -#define PIN_PB31 ( 63 ) /**< Pin Number for PB31 */ -#define PIN_PC00 ( 64 ) /**< Pin Number for PC00 */ -#define PIN_PC01 ( 65 ) /**< Pin Number for PC01 */ -#define PIN_PC02 ( 66 ) /**< Pin Number for PC02 */ -#define PIN_PC03 ( 67 ) /**< Pin Number for PC03 */ -#define PIN_PC05 ( 69 ) /**< Pin Number for PC05 */ -#define PIN_PC06 ( 70 ) /**< Pin Number for PC06 */ -#define PIN_PC07 ( 71 ) /**< Pin Number for PC07 */ -#define PIN_PC10 ( 74 ) /**< Pin Number for PC10 */ -#define PIN_PC11 ( 75 ) /**< Pin Number for PC11 */ -#define PIN_PC12 ( 76 ) /**< Pin Number for PC12 */ -#define PIN_PC13 ( 77 ) /**< Pin Number for PC13 */ -#define PIN_PC14 ( 78 ) /**< Pin Number for PC14 */ -#define PIN_PC15 ( 79 ) /**< Pin Number for PC15 */ -#define PIN_PC16 ( 80 ) /**< Pin Number for PC16 */ -#define PIN_PC17 ( 81 ) /**< Pin Number for PC17 */ -#define PIN_PC18 ( 82 ) /**< Pin Number for PC18 */ -#define PIN_PC19 ( 83 ) /**< Pin Number for PC19 */ -#define PIN_PC20 ( 84 ) /**< Pin Number for PC20 */ -#define PIN_PC21 ( 85 ) /**< Pin Number for PC21 */ -#define PIN_PC24 ( 88 ) /**< Pin Number for PC24 */ -#define PIN_PC25 ( 89 ) /**< Pin Number for PC25 */ -#define PIN_PC26 ( 90 ) /**< Pin Number for PC26 */ -#define PIN_PC27 ( 91 ) /**< Pin Number for PC27 */ -#define PIN_PC28 ( 92 ) /**< Pin Number for PC28 */ - -/* ========== Peripheral I/O masks ========== */ -#define PORT_PA00 (_U_(1) << 0) /**< PORT mask for PA00 */ -#define PORT_PA01 (_U_(1) << 1) /**< PORT mask for PA01 */ -#define PORT_PA02 (_U_(1) << 2) /**< PORT mask for PA02 */ -#define PORT_PA03 (_U_(1) << 3) /**< PORT mask for PA03 */ -#define PORT_PA04 (_U_(1) << 4) /**< PORT mask for PA04 */ -#define PORT_PA05 (_U_(1) << 5) /**< PORT mask for PA05 */ -#define PORT_PA06 (_U_(1) << 6) /**< PORT mask for PA06 */ -#define PORT_PA07 (_U_(1) << 7) /**< PORT mask for PA07 */ -#define PORT_PA08 (_U_(1) << 8) /**< PORT mask for PA08 */ -#define PORT_PA09 (_U_(1) << 9) /**< PORT mask for PA09 */ -#define PORT_PA10 (_U_(1) << 10) /**< PORT mask for PA10 */ -#define PORT_PA11 (_U_(1) << 11) /**< PORT mask for PA11 */ -#define PORT_PA12 (_U_(1) << 12) /**< PORT mask for PA12 */ -#define PORT_PA13 (_U_(1) << 13) /**< PORT mask for PA13 */ -#define PORT_PA14 (_U_(1) << 14) /**< PORT mask for PA14 */ -#define PORT_PA15 (_U_(1) << 15) /**< PORT mask for PA15 */ -#define PORT_PA16 (_U_(1) << 16) /**< PORT mask for PA16 */ -#define PORT_PA17 (_U_(1) << 17) /**< PORT mask for PA17 */ -#define PORT_PA18 (_U_(1) << 18) /**< PORT mask for PA18 */ -#define PORT_PA19 (_U_(1) << 19) /**< PORT mask for PA19 */ -#define PORT_PA20 (_U_(1) << 20) /**< PORT mask for PA20 */ -#define PORT_PA21 (_U_(1) << 21) /**< PORT mask for PA21 */ -#define PORT_PA22 (_U_(1) << 22) /**< PORT mask for PA22 */ -#define PORT_PA23 (_U_(1) << 23) /**< PORT mask for PA23 */ -#define PORT_PA24 (_U_(1) << 24) /**< PORT mask for PA24 */ -#define PORT_PA25 (_U_(1) << 25) /**< PORT mask for PA25 */ -#define PORT_PA27 (_U_(1) << 27) /**< PORT mask for PA27 */ -#define PORT_PA30 (_U_(1) << 30) /**< PORT mask for PA30 */ -#define PORT_PA31 (_U_(1) << 31) /**< PORT mask for PA31 */ -#define PORT_PB00 (_U_(1) << 0) /**< PORT mask for PB00 */ -#define PORT_PB01 (_U_(1) << 1) /**< PORT mask for PB01 */ -#define PORT_PB02 (_U_(1) << 2) /**< PORT mask for PB02 */ -#define PORT_PB03 (_U_(1) << 3) /**< PORT mask for PB03 */ -#define PORT_PB04 (_U_(1) << 4) /**< PORT mask for PB04 */ -#define PORT_PB05 (_U_(1) << 5) /**< PORT mask for PB05 */ -#define PORT_PB06 (_U_(1) << 6) /**< PORT mask for PB06 */ -#define PORT_PB07 (_U_(1) << 7) /**< PORT mask for PB07 */ -#define PORT_PB08 (_U_(1) << 8) /**< PORT mask for PB08 */ -#define PORT_PB09 (_U_(1) << 9) /**< PORT mask for PB09 */ -#define PORT_PB10 (_U_(1) << 10) /**< PORT mask for PB10 */ -#define PORT_PB11 (_U_(1) << 11) /**< PORT mask for PB11 */ -#define PORT_PB12 (_U_(1) << 12) /**< PORT mask for PB12 */ -#define PORT_PB13 (_U_(1) << 13) /**< PORT mask for PB13 */ -#define PORT_PB14 (_U_(1) << 14) /**< PORT mask for PB14 */ -#define PORT_PB15 (_U_(1) << 15) /**< PORT mask for PB15 */ -#define PORT_PB16 (_U_(1) << 16) /**< PORT mask for PB16 */ -#define PORT_PB17 (_U_(1) << 17) /**< PORT mask for PB17 */ -#define PORT_PB18 (_U_(1) << 18) /**< PORT mask for PB18 */ -#define PORT_PB19 (_U_(1) << 19) /**< PORT mask for PB19 */ -#define PORT_PB20 (_U_(1) << 20) /**< PORT mask for PB20 */ -#define PORT_PB21 (_U_(1) << 21) /**< PORT mask for PB21 */ -#define PORT_PB22 (_U_(1) << 22) /**< PORT mask for PB22 */ -#define PORT_PB23 (_U_(1) << 23) /**< PORT mask for PB23 */ -#define PORT_PB24 (_U_(1) << 24) /**< PORT mask for PB24 */ -#define PORT_PB25 (_U_(1) << 25) /**< PORT mask for PB25 */ -#define PORT_PB30 (_U_(1) << 30) /**< PORT mask for PB30 */ -#define PORT_PB31 (_U_(1) << 31) /**< PORT mask for PB31 */ -#define PORT_PC00 (_U_(1) << 0) /**< PORT mask for PC00 */ -#define PORT_PC01 (_U_(1) << 1) /**< PORT mask for PC01 */ -#define PORT_PC02 (_U_(1) << 2) /**< PORT mask for PC02 */ -#define PORT_PC03 (_U_(1) << 3) /**< PORT mask for PC03 */ -#define PORT_PC05 (_U_(1) << 5) /**< PORT mask for PC05 */ -#define PORT_PC06 (_U_(1) << 6) /**< PORT mask for PC06 */ -#define PORT_PC07 (_U_(1) << 7) /**< PORT mask for PC07 */ -#define PORT_PC10 (_U_(1) << 10) /**< PORT mask for PC10 */ -#define PORT_PC11 (_U_(1) << 11) /**< PORT mask for PC11 */ -#define PORT_PC12 (_U_(1) << 12) /**< PORT mask for PC12 */ -#define PORT_PC13 (_U_(1) << 13) /**< PORT mask for PC13 */ -#define PORT_PC14 (_U_(1) << 14) /**< PORT mask for PC14 */ -#define PORT_PC15 (_U_(1) << 15) /**< PORT mask for PC15 */ -#define PORT_PC16 (_U_(1) << 16) /**< PORT mask for PC16 */ -#define PORT_PC17 (_U_(1) << 17) /**< PORT mask for PC17 */ -#define PORT_PC18 (_U_(1) << 18) /**< PORT mask for PC18 */ -#define PORT_PC19 (_U_(1) << 19) /**< PORT mask for PC19 */ -#define PORT_PC20 (_U_(1) << 20) /**< PORT mask for PC20 */ -#define PORT_PC21 (_U_(1) << 21) /**< PORT mask for PC21 */ -#define PORT_PC24 (_U_(1) << 24) /**< PORT mask for PC24 */ -#define PORT_PC25 (_U_(1) << 25) /**< PORT mask for PC25 */ -#define PORT_PC26 (_U_(1) << 26) /**< PORT mask for PC26 */ -#define PORT_PC27 (_U_(1) << 27) /**< PORT mask for PC27 */ -#define PORT_PC28 (_U_(1) << 28) /**< PORT mask for PC28 */ - -/* ========== PORT definition for AC peripheral ========== */ -#define PIN_PA04B_AC_AIN0 (4L) -#define MUX_PA04B_AC_AIN0 (1L) -#define PINMUX_PA04B_AC_AIN0 ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0) -#define PORT_PA04B_AC_AIN0 ((1UL) << 4) - -#define PIN_PA05B_AC_AIN1 (5L) -#define MUX_PA05B_AC_AIN1 (1L) -#define PINMUX_PA05B_AC_AIN1 ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1) -#define PORT_PA05B_AC_AIN1 ((1UL) << 5) - -#define PIN_PA06B_AC_AIN2 (6L) -#define MUX_PA06B_AC_AIN2 (1L) -#define PINMUX_PA06B_AC_AIN2 ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2) -#define PORT_PA06B_AC_AIN2 ((1UL) << 6) - -#define PIN_PA07B_AC_AIN3 (7L) -#define MUX_PA07B_AC_AIN3 (1L) -#define PINMUX_PA07B_AC_AIN3 ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3) -#define PORT_PA07B_AC_AIN3 ((1UL) << 7) - -#define PIN_PA12M_AC_CMP0 (12L) -#define MUX_PA12M_AC_CMP0 (12L) -#define PINMUX_PA12M_AC_CMP0 ((PIN_PA12M_AC_CMP0 << 16) | MUX_PA12M_AC_CMP0) -#define PORT_PA12M_AC_CMP0 ((1UL) << 12) - -#define PIN_PA18M_AC_CMP0 (18L) -#define MUX_PA18M_AC_CMP0 (12L) -#define PINMUX_PA18M_AC_CMP0 ((PIN_PA18M_AC_CMP0 << 16) | MUX_PA18M_AC_CMP0) -#define PORT_PA18M_AC_CMP0 ((1UL) << 18) - -#define PIN_PB24M_AC_CMP0 (56L) -#define MUX_PB24M_AC_CMP0 (12L) -#define PINMUX_PB24M_AC_CMP0 ((PIN_PB24M_AC_CMP0 << 16) | MUX_PB24M_AC_CMP0) -#define PORT_PB24M_AC_CMP0 ((1UL) << 24) - -#define PIN_PA13M_AC_CMP1 (13L) -#define MUX_PA13M_AC_CMP1 (12L) -#define PINMUX_PA13M_AC_CMP1 ((PIN_PA13M_AC_CMP1 << 16) | MUX_PA13M_AC_CMP1) -#define PORT_PA13M_AC_CMP1 ((1UL) << 13) - -#define PIN_PA19M_AC_CMP1 (19L) -#define MUX_PA19M_AC_CMP1 (12L) -#define PINMUX_PA19M_AC_CMP1 ((PIN_PA19M_AC_CMP1 << 16) | MUX_PA19M_AC_CMP1) -#define PORT_PA19M_AC_CMP1 ((1UL) << 19) - -#define PIN_PB25M_AC_CMP1 (57L) -#define MUX_PB25M_AC_CMP1 (12L) -#define PINMUX_PB25M_AC_CMP1 ((PIN_PB25M_AC_CMP1 << 16) | MUX_PB25M_AC_CMP1) -#define PORT_PB25M_AC_CMP1 ((1UL) << 25) - -/* ========== PORT definition for ADC0 peripheral ========== */ -#define PIN_PA02B_ADC0_AIN0 (2L) -#define MUX_PA02B_ADC0_AIN0 (1L) -#define PINMUX_PA02B_ADC0_AIN0 ((PIN_PA02B_ADC0_AIN0 << 16) | MUX_PA02B_ADC0_AIN0) -#define PORT_PA02B_ADC0_AIN0 ((1UL) << 2) - -#define PIN_PA03B_ADC0_AIN1 (3L) -#define MUX_PA03B_ADC0_AIN1 (1L) -#define PINMUX_PA03B_ADC0_AIN1 ((PIN_PA03B_ADC0_AIN1 << 16) | MUX_PA03B_ADC0_AIN1) -#define PORT_PA03B_ADC0_AIN1 ((1UL) << 3) - -#define PIN_PB08B_ADC0_AIN2 (40L) -#define MUX_PB08B_ADC0_AIN2 (1L) -#define PINMUX_PB08B_ADC0_AIN2 ((PIN_PB08B_ADC0_AIN2 << 16) | MUX_PB08B_ADC0_AIN2) -#define PORT_PB08B_ADC0_AIN2 ((1UL) << 8) - -#define PIN_PB09B_ADC0_AIN3 (41L) -#define MUX_PB09B_ADC0_AIN3 (1L) -#define PINMUX_PB09B_ADC0_AIN3 ((PIN_PB09B_ADC0_AIN3 << 16) | MUX_PB09B_ADC0_AIN3) -#define PORT_PB09B_ADC0_AIN3 ((1UL) << 9) - -#define PIN_PA04B_ADC0_AIN4 (4L) -#define MUX_PA04B_ADC0_AIN4 (1L) -#define PINMUX_PA04B_ADC0_AIN4 ((PIN_PA04B_ADC0_AIN4 << 16) | MUX_PA04B_ADC0_AIN4) -#define PORT_PA04B_ADC0_AIN4 ((1UL) << 4) - -#define PIN_PA05B_ADC0_AIN5 (5L) -#define MUX_PA05B_ADC0_AIN5 (1L) -#define PINMUX_PA05B_ADC0_AIN5 ((PIN_PA05B_ADC0_AIN5 << 16) | MUX_PA05B_ADC0_AIN5) -#define PORT_PA05B_ADC0_AIN5 ((1UL) << 5) - -#define PIN_PA06B_ADC0_AIN6 (6L) -#define MUX_PA06B_ADC0_AIN6 (1L) -#define PINMUX_PA06B_ADC0_AIN6 ((PIN_PA06B_ADC0_AIN6 << 16) | MUX_PA06B_ADC0_AIN6) -#define PORT_PA06B_ADC0_AIN6 ((1UL) << 6) - -#define PIN_PA07B_ADC0_AIN7 (7L) -#define MUX_PA07B_ADC0_AIN7 (1L) -#define PINMUX_PA07B_ADC0_AIN7 ((PIN_PA07B_ADC0_AIN7 << 16) | MUX_PA07B_ADC0_AIN7) -#define PORT_PA07B_ADC0_AIN7 ((1UL) << 7) - -#define PIN_PA08B_ADC0_AIN8 (8L) -#define MUX_PA08B_ADC0_AIN8 (1L) -#define PINMUX_PA08B_ADC0_AIN8 ((PIN_PA08B_ADC0_AIN8 << 16) | MUX_PA08B_ADC0_AIN8) -#define PORT_PA08B_ADC0_AIN8 ((1UL) << 8) - -#define PIN_PA09B_ADC0_AIN9 (9L) -#define MUX_PA09B_ADC0_AIN9 (1L) -#define PINMUX_PA09B_ADC0_AIN9 ((PIN_PA09B_ADC0_AIN9 << 16) | MUX_PA09B_ADC0_AIN9) -#define PORT_PA09B_ADC0_AIN9 ((1UL) << 9) - -#define PIN_PA10B_ADC0_AIN10 (10L) -#define MUX_PA10B_ADC0_AIN10 (1L) -#define PINMUX_PA10B_ADC0_AIN10 ((PIN_PA10B_ADC0_AIN10 << 16) | MUX_PA10B_ADC0_AIN10) -#define PORT_PA10B_ADC0_AIN10 ((1UL) << 10) - -#define PIN_PA11B_ADC0_AIN11 (11L) -#define MUX_PA11B_ADC0_AIN11 (1L) -#define PINMUX_PA11B_ADC0_AIN11 ((PIN_PA11B_ADC0_AIN11 << 16) | MUX_PA11B_ADC0_AIN11) -#define PORT_PA11B_ADC0_AIN11 ((1UL) << 11) - -#define PIN_PB00B_ADC0_AIN12 (32L) -#define MUX_PB00B_ADC0_AIN12 (1L) -#define PINMUX_PB00B_ADC0_AIN12 ((PIN_PB00B_ADC0_AIN12 << 16) | MUX_PB00B_ADC0_AIN12) -#define PORT_PB00B_ADC0_AIN12 ((1UL) << 0) - -#define PIN_PB01B_ADC0_AIN13 (33L) -#define MUX_PB01B_ADC0_AIN13 (1L) -#define PINMUX_PB01B_ADC0_AIN13 ((PIN_PB01B_ADC0_AIN13 << 16) | MUX_PB01B_ADC0_AIN13) -#define PORT_PB01B_ADC0_AIN13 ((1UL) << 1) - -#define PIN_PB02B_ADC0_AIN14 (34L) -#define MUX_PB02B_ADC0_AIN14 (1L) -#define PINMUX_PB02B_ADC0_AIN14 ((PIN_PB02B_ADC0_AIN14 << 16) | MUX_PB02B_ADC0_AIN14) -#define PORT_PB02B_ADC0_AIN14 ((1UL) << 2) - -#define PIN_PB03B_ADC0_AIN15 (35L) -#define MUX_PB03B_ADC0_AIN15 (1L) -#define PINMUX_PB03B_ADC0_AIN15 ((PIN_PB03B_ADC0_AIN15 << 16) | MUX_PB03B_ADC0_AIN15) -#define PORT_PB03B_ADC0_AIN15 ((1UL) << 3) - -#define PIN_PA03B_ADC0_VREFA (3L) -#define MUX_PA03B_ADC0_VREFA (1L) -#define PINMUX_PA03B_ADC0_VREFA ((PIN_PA03B_ADC0_VREFA << 16) | MUX_PA03B_ADC0_VREFA) -#define PORT_PA03B_ADC0_VREFA ((1UL) << 3) - -#define PIN_PA04B_ADC0_VREFB (4L) -#define MUX_PA04B_ADC0_VREFB (1L) -#define PINMUX_PA04B_ADC0_VREFB ((PIN_PA04B_ADC0_VREFB << 16) | MUX_PA04B_ADC0_VREFB) -#define PORT_PA04B_ADC0_VREFB ((1UL) << 4) - -#define PIN_PA06B_ADC0_VREFC (6L) -#define MUX_PA06B_ADC0_VREFC (1L) -#define PINMUX_PA06B_ADC0_VREFC ((PIN_PA06B_ADC0_VREFC << 16) | MUX_PA06B_ADC0_VREFC) -#define PORT_PA06B_ADC0_VREFC ((1UL) << 6) - -#define PIN_PA03B_ADC0_X0 (3L) -#define MUX_PA03B_ADC0_X0 (1L) -#define PINMUX_PA03B_ADC0_X0 ((PIN_PA03B_ADC0_X0 << 16) | MUX_PA03B_ADC0_X0) -#define PORT_PA03B_ADC0_X0 ((1UL) << 3) - -#define PIN_PB08B_ADC0_X1 (40L) -#define MUX_PB08B_ADC0_X1 (1L) -#define PINMUX_PB08B_ADC0_X1 ((PIN_PB08B_ADC0_X1 << 16) | MUX_PB08B_ADC0_X1) -#define PORT_PB08B_ADC0_X1 ((1UL) << 8) - -#define PIN_PB09B_ADC0_X2 (41L) -#define MUX_PB09B_ADC0_X2 (1L) -#define PINMUX_PB09B_ADC0_X2 ((PIN_PB09B_ADC0_X2 << 16) | MUX_PB09B_ADC0_X2) -#define PORT_PB09B_ADC0_X2 ((1UL) << 9) - -#define PIN_PA04B_ADC0_X3 (4L) -#define MUX_PA04B_ADC0_X3 (1L) -#define PINMUX_PA04B_ADC0_X3 ((PIN_PA04B_ADC0_X3 << 16) | MUX_PA04B_ADC0_X3) -#define PORT_PA04B_ADC0_X3 ((1UL) << 4) - -#define PIN_PA06B_ADC0_X4 (6L) -#define MUX_PA06B_ADC0_X4 (1L) -#define PINMUX_PA06B_ADC0_X4 ((PIN_PA06B_ADC0_X4 << 16) | MUX_PA06B_ADC0_X4) -#define PORT_PA06B_ADC0_X4 ((1UL) << 6) - -#define PIN_PA07B_ADC0_X5 (7L) -#define MUX_PA07B_ADC0_X5 (1L) -#define PINMUX_PA07B_ADC0_X5 ((PIN_PA07B_ADC0_X5 << 16) | MUX_PA07B_ADC0_X5) -#define PORT_PA07B_ADC0_X5 ((1UL) << 7) - -#define PIN_PA08B_ADC0_X6 (8L) -#define MUX_PA08B_ADC0_X6 (1L) -#define PINMUX_PA08B_ADC0_X6 ((PIN_PA08B_ADC0_X6 << 16) | MUX_PA08B_ADC0_X6) -#define PORT_PA08B_ADC0_X6 ((1UL) << 8) - -#define PIN_PA09B_ADC0_X7 (9L) -#define MUX_PA09B_ADC0_X7 (1L) -#define PINMUX_PA09B_ADC0_X7 ((PIN_PA09B_ADC0_X7 << 16) | MUX_PA09B_ADC0_X7) -#define PORT_PA09B_ADC0_X7 ((1UL) << 9) - -#define PIN_PA10B_ADC0_X8 (10L) -#define MUX_PA10B_ADC0_X8 (1L) -#define PINMUX_PA10B_ADC0_X8 ((PIN_PA10B_ADC0_X8 << 16) | MUX_PA10B_ADC0_X8) -#define PORT_PA10B_ADC0_X8 ((1UL) << 10) - -#define PIN_PA11B_ADC0_X9 (11L) -#define MUX_PA11B_ADC0_X9 (1L) -#define PINMUX_PA11B_ADC0_X9 ((PIN_PA11B_ADC0_X9 << 16) | MUX_PA11B_ADC0_X9) -#define PORT_PA11B_ADC0_X9 ((1UL) << 11) - -#define PIN_PA16B_ADC0_X10 (16L) -#define MUX_PA16B_ADC0_X10 (1L) -#define PINMUX_PA16B_ADC0_X10 ((PIN_PA16B_ADC0_X10 << 16) | MUX_PA16B_ADC0_X10) -#define PORT_PA16B_ADC0_X10 ((1UL) << 16) - -#define PIN_PA17B_ADC0_X11 (17L) -#define MUX_PA17B_ADC0_X11 (1L) -#define PINMUX_PA17B_ADC0_X11 ((PIN_PA17B_ADC0_X11 << 16) | MUX_PA17B_ADC0_X11) -#define PORT_PA17B_ADC0_X11 ((1UL) << 17) - -#define PIN_PA18B_ADC0_X12 (18L) -#define MUX_PA18B_ADC0_X12 (1L) -#define PINMUX_PA18B_ADC0_X12 ((PIN_PA18B_ADC0_X12 << 16) | MUX_PA18B_ADC0_X12) -#define PORT_PA18B_ADC0_X12 ((1UL) << 18) - -#define PIN_PA19B_ADC0_X13 (19L) -#define MUX_PA19B_ADC0_X13 (1L) -#define PINMUX_PA19B_ADC0_X13 ((PIN_PA19B_ADC0_X13 << 16) | MUX_PA19B_ADC0_X13) -#define PORT_PA19B_ADC0_X13 ((1UL) << 19) - -#define PIN_PA20B_ADC0_X14 (20L) -#define MUX_PA20B_ADC0_X14 (1L) -#define PINMUX_PA20B_ADC0_X14 ((PIN_PA20B_ADC0_X14 << 16) | MUX_PA20B_ADC0_X14) -#define PORT_PA20B_ADC0_X14 ((1UL) << 20) - -#define PIN_PA21B_ADC0_X15 (21L) -#define MUX_PA21B_ADC0_X15 (1L) -#define PINMUX_PA21B_ADC0_X15 ((PIN_PA21B_ADC0_X15 << 16) | MUX_PA21B_ADC0_X15) -#define PORT_PA21B_ADC0_X15 ((1UL) << 21) - -#define PIN_PA22B_ADC0_X16 (22L) -#define MUX_PA22B_ADC0_X16 (1L) -#define PINMUX_PA22B_ADC0_X16 ((PIN_PA22B_ADC0_X16 << 16) | MUX_PA22B_ADC0_X16) -#define PORT_PA22B_ADC0_X16 ((1UL) << 22) - -#define PIN_PA23B_ADC0_X17 (23L) -#define MUX_PA23B_ADC0_X17 (1L) -#define PINMUX_PA23B_ADC0_X17 ((PIN_PA23B_ADC0_X17 << 16) | MUX_PA23B_ADC0_X17) -#define PORT_PA23B_ADC0_X17 ((1UL) << 23) - -#define PIN_PA27B_ADC0_X18 (27L) -#define MUX_PA27B_ADC0_X18 (1L) -#define PINMUX_PA27B_ADC0_X18 ((PIN_PA27B_ADC0_X18 << 16) | MUX_PA27B_ADC0_X18) -#define PORT_PA27B_ADC0_X18 ((1UL) << 27) - -#define PIN_PA30B_ADC0_X19 (30L) -#define MUX_PA30B_ADC0_X19 (1L) -#define PINMUX_PA30B_ADC0_X19 ((PIN_PA30B_ADC0_X19 << 16) | MUX_PA30B_ADC0_X19) -#define PORT_PA30B_ADC0_X19 ((1UL) << 30) - -#define PIN_PB02B_ADC0_X20 (34L) -#define MUX_PB02B_ADC0_X20 (1L) -#define PINMUX_PB02B_ADC0_X20 ((PIN_PB02B_ADC0_X20 << 16) | MUX_PB02B_ADC0_X20) -#define PORT_PB02B_ADC0_X20 ((1UL) << 2) - -#define PIN_PB03B_ADC0_X21 (35L) -#define MUX_PB03B_ADC0_X21 (1L) -#define PINMUX_PB03B_ADC0_X21 ((PIN_PB03B_ADC0_X21 << 16) | MUX_PB03B_ADC0_X21) -#define PORT_PB03B_ADC0_X21 ((1UL) << 3) - -#define PIN_PB04B_ADC0_X22 (36L) -#define MUX_PB04B_ADC0_X22 (1L) -#define PINMUX_PB04B_ADC0_X22 ((PIN_PB04B_ADC0_X22 << 16) | MUX_PB04B_ADC0_X22) -#define PORT_PB04B_ADC0_X22 ((1UL) << 4) - -#define PIN_PB05B_ADC0_X23 (37L) -#define MUX_PB05B_ADC0_X23 (1L) -#define PINMUX_PB05B_ADC0_X23 ((PIN_PB05B_ADC0_X23 << 16) | MUX_PB05B_ADC0_X23) -#define PORT_PB05B_ADC0_X23 ((1UL) << 5) - -#define PIN_PB06B_ADC0_X24 (38L) -#define MUX_PB06B_ADC0_X24 (1L) -#define PINMUX_PB06B_ADC0_X24 ((PIN_PB06B_ADC0_X24 << 16) | MUX_PB06B_ADC0_X24) -#define PORT_PB06B_ADC0_X24 ((1UL) << 6) - -#define PIN_PB07B_ADC0_X25 (39L) -#define MUX_PB07B_ADC0_X25 (1L) -#define PINMUX_PB07B_ADC0_X25 ((PIN_PB07B_ADC0_X25 << 16) | MUX_PB07B_ADC0_X25) -#define PORT_PB07B_ADC0_X25 ((1UL) << 7) - -#define PIN_PB12B_ADC0_X26 (44L) -#define MUX_PB12B_ADC0_X26 (1L) -#define PINMUX_PB12B_ADC0_X26 ((PIN_PB12B_ADC0_X26 << 16) | MUX_PB12B_ADC0_X26) -#define PORT_PB12B_ADC0_X26 ((1UL) << 12) - -#define PIN_PB13B_ADC0_X27 (45L) -#define MUX_PB13B_ADC0_X27 (1L) -#define PINMUX_PB13B_ADC0_X27 ((PIN_PB13B_ADC0_X27 << 16) | MUX_PB13B_ADC0_X27) -#define PORT_PB13B_ADC0_X27 ((1UL) << 13) - -#define PIN_PB14B_ADC0_X28 (46L) -#define MUX_PB14B_ADC0_X28 (1L) -#define PINMUX_PB14B_ADC0_X28 ((PIN_PB14B_ADC0_X28 << 16) | MUX_PB14B_ADC0_X28) -#define PORT_PB14B_ADC0_X28 ((1UL) << 14) - -#define PIN_PB15B_ADC0_X29 (47L) -#define MUX_PB15B_ADC0_X29 (1L) -#define PINMUX_PB15B_ADC0_X29 ((PIN_PB15B_ADC0_X29 << 16) | MUX_PB15B_ADC0_X29) -#define PORT_PB15B_ADC0_X29 ((1UL) << 15) - -#define PIN_PB00B_ADC0_X30 (32L) -#define MUX_PB00B_ADC0_X30 (1L) -#define PINMUX_PB00B_ADC0_X30 ((PIN_PB00B_ADC0_X30 << 16) | MUX_PB00B_ADC0_X30) -#define PORT_PB00B_ADC0_X30 ((1UL) << 0) - -#define PIN_PB01B_ADC0_X31 (33L) -#define MUX_PB01B_ADC0_X31 (1L) -#define PINMUX_PB01B_ADC0_X31 ((PIN_PB01B_ADC0_X31 << 16) | MUX_PB01B_ADC0_X31) -#define PORT_PB01B_ADC0_X31 ((1UL) << 1) - -#define PIN_PA03B_ADC0_Y0 (3L) -#define MUX_PA03B_ADC0_Y0 (1L) -#define PINMUX_PA03B_ADC0_Y0 ((PIN_PA03B_ADC0_Y0 << 16) | MUX_PA03B_ADC0_Y0) -#define PORT_PA03B_ADC0_Y0 ((1UL) << 3) - -#define PIN_PB08B_ADC0_Y1 (40L) -#define MUX_PB08B_ADC0_Y1 (1L) -#define PINMUX_PB08B_ADC0_Y1 ((PIN_PB08B_ADC0_Y1 << 16) | MUX_PB08B_ADC0_Y1) -#define PORT_PB08B_ADC0_Y1 ((1UL) << 8) - -#define PIN_PB09B_ADC0_Y2 (41L) -#define MUX_PB09B_ADC0_Y2 (1L) -#define PINMUX_PB09B_ADC0_Y2 ((PIN_PB09B_ADC0_Y2 << 16) | MUX_PB09B_ADC0_Y2) -#define PORT_PB09B_ADC0_Y2 ((1UL) << 9) - -#define PIN_PA04B_ADC0_Y3 (4L) -#define MUX_PA04B_ADC0_Y3 (1L) -#define PINMUX_PA04B_ADC0_Y3 ((PIN_PA04B_ADC0_Y3 << 16) | MUX_PA04B_ADC0_Y3) -#define PORT_PA04B_ADC0_Y3 ((1UL) << 4) - -#define PIN_PA06B_ADC0_Y4 (6L) -#define MUX_PA06B_ADC0_Y4 (1L) -#define PINMUX_PA06B_ADC0_Y4 ((PIN_PA06B_ADC0_Y4 << 16) | MUX_PA06B_ADC0_Y4) -#define PORT_PA06B_ADC0_Y4 ((1UL) << 6) - -#define PIN_PA07B_ADC0_Y5 (7L) -#define MUX_PA07B_ADC0_Y5 (1L) -#define PINMUX_PA07B_ADC0_Y5 ((PIN_PA07B_ADC0_Y5 << 16) | MUX_PA07B_ADC0_Y5) -#define PORT_PA07B_ADC0_Y5 ((1UL) << 7) - -#define PIN_PA08B_ADC0_Y6 (8L) -#define MUX_PA08B_ADC0_Y6 (1L) -#define PINMUX_PA08B_ADC0_Y6 ((PIN_PA08B_ADC0_Y6 << 16) | MUX_PA08B_ADC0_Y6) -#define PORT_PA08B_ADC0_Y6 ((1UL) << 8) - -#define PIN_PA09B_ADC0_Y7 (9L) -#define MUX_PA09B_ADC0_Y7 (1L) -#define PINMUX_PA09B_ADC0_Y7 ((PIN_PA09B_ADC0_Y7 << 16) | MUX_PA09B_ADC0_Y7) -#define PORT_PA09B_ADC0_Y7 ((1UL) << 9) - -#define PIN_PA10B_ADC0_Y8 (10L) -#define MUX_PA10B_ADC0_Y8 (1L) -#define PINMUX_PA10B_ADC0_Y8 ((PIN_PA10B_ADC0_Y8 << 16) | MUX_PA10B_ADC0_Y8) -#define PORT_PA10B_ADC0_Y8 ((1UL) << 10) - -#define PIN_PA11B_ADC0_Y9 (11L) -#define MUX_PA11B_ADC0_Y9 (1L) -#define PINMUX_PA11B_ADC0_Y9 ((PIN_PA11B_ADC0_Y9 << 16) | MUX_PA11B_ADC0_Y9) -#define PORT_PA11B_ADC0_Y9 ((1UL) << 11) - -#define PIN_PA16B_ADC0_Y10 (16L) -#define MUX_PA16B_ADC0_Y10 (1L) -#define PINMUX_PA16B_ADC0_Y10 ((PIN_PA16B_ADC0_Y10 << 16) | MUX_PA16B_ADC0_Y10) -#define PORT_PA16B_ADC0_Y10 ((1UL) << 16) - -#define PIN_PA17B_ADC0_Y11 (17L) -#define MUX_PA17B_ADC0_Y11 (1L) -#define PINMUX_PA17B_ADC0_Y11 ((PIN_PA17B_ADC0_Y11 << 16) | MUX_PA17B_ADC0_Y11) -#define PORT_PA17B_ADC0_Y11 ((1UL) << 17) - -#define PIN_PA18B_ADC0_Y12 (18L) -#define MUX_PA18B_ADC0_Y12 (1L) -#define PINMUX_PA18B_ADC0_Y12 ((PIN_PA18B_ADC0_Y12 << 16) | MUX_PA18B_ADC0_Y12) -#define PORT_PA18B_ADC0_Y12 ((1UL) << 18) - -#define PIN_PA19B_ADC0_Y13 (19L) -#define MUX_PA19B_ADC0_Y13 (1L) -#define PINMUX_PA19B_ADC0_Y13 ((PIN_PA19B_ADC0_Y13 << 16) | MUX_PA19B_ADC0_Y13) -#define PORT_PA19B_ADC0_Y13 ((1UL) << 19) - -#define PIN_PA20B_ADC0_Y14 (20L) -#define MUX_PA20B_ADC0_Y14 (1L) -#define PINMUX_PA20B_ADC0_Y14 ((PIN_PA20B_ADC0_Y14 << 16) | MUX_PA20B_ADC0_Y14) -#define PORT_PA20B_ADC0_Y14 ((1UL) << 20) - -#define PIN_PA21B_ADC0_Y15 (21L) -#define MUX_PA21B_ADC0_Y15 (1L) -#define PINMUX_PA21B_ADC0_Y15 ((PIN_PA21B_ADC0_Y15 << 16) | MUX_PA21B_ADC0_Y15) -#define PORT_PA21B_ADC0_Y15 ((1UL) << 21) - -#define PIN_PA22B_ADC0_Y16 (22L) -#define MUX_PA22B_ADC0_Y16 (1L) -#define PINMUX_PA22B_ADC0_Y16 ((PIN_PA22B_ADC0_Y16 << 16) | MUX_PA22B_ADC0_Y16) -#define PORT_PA22B_ADC0_Y16 ((1UL) << 22) - -#define PIN_PA23B_ADC0_Y17 (23L) -#define MUX_PA23B_ADC0_Y17 (1L) -#define PINMUX_PA23B_ADC0_Y17 ((PIN_PA23B_ADC0_Y17 << 16) | MUX_PA23B_ADC0_Y17) -#define PORT_PA23B_ADC0_Y17 ((1UL) << 23) - -#define PIN_PA27B_ADC0_Y18 (27L) -#define MUX_PA27B_ADC0_Y18 (1L) -#define PINMUX_PA27B_ADC0_Y18 ((PIN_PA27B_ADC0_Y18 << 16) | MUX_PA27B_ADC0_Y18) -#define PORT_PA27B_ADC0_Y18 ((1UL) << 27) - -#define PIN_PA30B_ADC0_Y19 (30L) -#define MUX_PA30B_ADC0_Y19 (1L) -#define PINMUX_PA30B_ADC0_Y19 ((PIN_PA30B_ADC0_Y19 << 16) | MUX_PA30B_ADC0_Y19) -#define PORT_PA30B_ADC0_Y19 ((1UL) << 30) - -#define PIN_PB02B_ADC0_Y20 (34L) -#define MUX_PB02B_ADC0_Y20 (1L) -#define PINMUX_PB02B_ADC0_Y20 ((PIN_PB02B_ADC0_Y20 << 16) | MUX_PB02B_ADC0_Y20) -#define PORT_PB02B_ADC0_Y20 ((1UL) << 2) - -#define PIN_PB03B_ADC0_Y21 (35L) -#define MUX_PB03B_ADC0_Y21 (1L) -#define PINMUX_PB03B_ADC0_Y21 ((PIN_PB03B_ADC0_Y21 << 16) | MUX_PB03B_ADC0_Y21) -#define PORT_PB03B_ADC0_Y21 ((1UL) << 3) - -#define PIN_PB04B_ADC0_Y22 (36L) -#define MUX_PB04B_ADC0_Y22 (1L) -#define PINMUX_PB04B_ADC0_Y22 ((PIN_PB04B_ADC0_Y22 << 16) | MUX_PB04B_ADC0_Y22) -#define PORT_PB04B_ADC0_Y22 ((1UL) << 4) - -#define PIN_PB05B_ADC0_Y23 (37L) -#define MUX_PB05B_ADC0_Y23 (1L) -#define PINMUX_PB05B_ADC0_Y23 ((PIN_PB05B_ADC0_Y23 << 16) | MUX_PB05B_ADC0_Y23) -#define PORT_PB05B_ADC0_Y23 ((1UL) << 5) - -#define PIN_PB06B_ADC0_Y24 (38L) -#define MUX_PB06B_ADC0_Y24 (1L) -#define PINMUX_PB06B_ADC0_Y24 ((PIN_PB06B_ADC0_Y24 << 16) | MUX_PB06B_ADC0_Y24) -#define PORT_PB06B_ADC0_Y24 ((1UL) << 6) - -#define PIN_PB07B_ADC0_Y25 (39L) -#define MUX_PB07B_ADC0_Y25 (1L) -#define PINMUX_PB07B_ADC0_Y25 ((PIN_PB07B_ADC0_Y25 << 16) | MUX_PB07B_ADC0_Y25) -#define PORT_PB07B_ADC0_Y25 ((1UL) << 7) - -#define PIN_PB12B_ADC0_Y26 (44L) -#define MUX_PB12B_ADC0_Y26 (1L) -#define PINMUX_PB12B_ADC0_Y26 ((PIN_PB12B_ADC0_Y26 << 16) | MUX_PB12B_ADC0_Y26) -#define PORT_PB12B_ADC0_Y26 ((1UL) << 12) - -#define PIN_PB13B_ADC0_Y27 (45L) -#define MUX_PB13B_ADC0_Y27 (1L) -#define PINMUX_PB13B_ADC0_Y27 ((PIN_PB13B_ADC0_Y27 << 16) | MUX_PB13B_ADC0_Y27) -#define PORT_PB13B_ADC0_Y27 ((1UL) << 13) - -#define PIN_PB14B_ADC0_Y28 (46L) -#define MUX_PB14B_ADC0_Y28 (1L) -#define PINMUX_PB14B_ADC0_Y28 ((PIN_PB14B_ADC0_Y28 << 16) | MUX_PB14B_ADC0_Y28) -#define PORT_PB14B_ADC0_Y28 ((1UL) << 14) - -#define PIN_PB15B_ADC0_Y29 (47L) -#define MUX_PB15B_ADC0_Y29 (1L) -#define PINMUX_PB15B_ADC0_Y29 ((PIN_PB15B_ADC0_Y29 << 16) | MUX_PB15B_ADC0_Y29) -#define PORT_PB15B_ADC0_Y29 ((1UL) << 15) - -#define PIN_PB00B_ADC0_Y30 (32L) -#define MUX_PB00B_ADC0_Y30 (1L) -#define PINMUX_PB00B_ADC0_Y30 ((PIN_PB00B_ADC0_Y30 << 16) | MUX_PB00B_ADC0_Y30) -#define PORT_PB00B_ADC0_Y30 ((1UL) << 0) - -#define PIN_PB01B_ADC0_Y31 (33L) -#define MUX_PB01B_ADC0_Y31 (1L) -#define PINMUX_PB01B_ADC0_Y31 ((PIN_PB01B_ADC0_Y31 << 16) | MUX_PB01B_ADC0_Y31) -#define PORT_PB01B_ADC0_Y31 ((1UL) << 1) - -/* ========== PORT definition for ADC1 peripheral ========== */ -#define PIN_PB08B_ADC1_AIN0 (40L) -#define MUX_PB08B_ADC1_AIN0 (1L) -#define PINMUX_PB08B_ADC1_AIN0 ((PIN_PB08B_ADC1_AIN0 << 16) | MUX_PB08B_ADC1_AIN0) -#define PORT_PB08B_ADC1_AIN0 ((1UL) << 8) - -#define PIN_PB09B_ADC1_AIN1 (41L) -#define MUX_PB09B_ADC1_AIN1 (1L) -#define PINMUX_PB09B_ADC1_AIN1 ((PIN_PB09B_ADC1_AIN1 << 16) | MUX_PB09B_ADC1_AIN1) -#define PORT_PB09B_ADC1_AIN1 ((1UL) << 9) - -#define PIN_PA08B_ADC1_AIN2 (8L) -#define MUX_PA08B_ADC1_AIN2 (1L) -#define PINMUX_PA08B_ADC1_AIN2 ((PIN_PA08B_ADC1_AIN2 << 16) | MUX_PA08B_ADC1_AIN2) -#define PORT_PA08B_ADC1_AIN2 ((1UL) << 8) - -#define PIN_PA09B_ADC1_AIN3 (9L) -#define MUX_PA09B_ADC1_AIN3 (1L) -#define PINMUX_PA09B_ADC1_AIN3 ((PIN_PA09B_ADC1_AIN3 << 16) | MUX_PA09B_ADC1_AIN3) -#define PORT_PA09B_ADC1_AIN3 ((1UL) << 9) - -#define PIN_PC02B_ADC1_AIN4 (66L) -#define MUX_PC02B_ADC1_AIN4 (1L) -#define PINMUX_PC02B_ADC1_AIN4 ((PIN_PC02B_ADC1_AIN4 << 16) | MUX_PC02B_ADC1_AIN4) -#define PORT_PC02B_ADC1_AIN4 ((1UL) << 2) - -#define PIN_PC03B_ADC1_AIN5 (67L) -#define MUX_PC03B_ADC1_AIN5 (1L) -#define PINMUX_PC03B_ADC1_AIN5 ((PIN_PC03B_ADC1_AIN5 << 16) | MUX_PC03B_ADC1_AIN5) -#define PORT_PC03B_ADC1_AIN5 ((1UL) << 3) - -#define PIN_PB04B_ADC1_AIN6 (36L) -#define MUX_PB04B_ADC1_AIN6 (1L) -#define PINMUX_PB04B_ADC1_AIN6 ((PIN_PB04B_ADC1_AIN6 << 16) | MUX_PB04B_ADC1_AIN6) -#define PORT_PB04B_ADC1_AIN6 ((1UL) << 4) - -#define PIN_PB05B_ADC1_AIN7 (37L) -#define MUX_PB05B_ADC1_AIN7 (1L) -#define PINMUX_PB05B_ADC1_AIN7 ((PIN_PB05B_ADC1_AIN7 << 16) | MUX_PB05B_ADC1_AIN7) -#define PORT_PB05B_ADC1_AIN7 ((1UL) << 5) - -#define PIN_PB06B_ADC1_AIN8 (38L) -#define MUX_PB06B_ADC1_AIN8 (1L) -#define PINMUX_PB06B_ADC1_AIN8 ((PIN_PB06B_ADC1_AIN8 << 16) | MUX_PB06B_ADC1_AIN8) -#define PORT_PB06B_ADC1_AIN8 ((1UL) << 6) - -#define PIN_PB07B_ADC1_AIN9 (39L) -#define MUX_PB07B_ADC1_AIN9 (1L) -#define PINMUX_PB07B_ADC1_AIN9 ((PIN_PB07B_ADC1_AIN9 << 16) | MUX_PB07B_ADC1_AIN9) -#define PORT_PB07B_ADC1_AIN9 ((1UL) << 7) - -#define PIN_PC00B_ADC1_AIN10 (64L) -#define MUX_PC00B_ADC1_AIN10 (1L) -#define PINMUX_PC00B_ADC1_AIN10 ((PIN_PC00B_ADC1_AIN10 << 16) | MUX_PC00B_ADC1_AIN10) -#define PORT_PC00B_ADC1_AIN10 ((1UL) << 0) - -#define PIN_PC01B_ADC1_AIN11 (65L) -#define MUX_PC01B_ADC1_AIN11 (1L) -#define PINMUX_PC01B_ADC1_AIN11 ((PIN_PC01B_ADC1_AIN11 << 16) | MUX_PC01B_ADC1_AIN11) -#define PORT_PC01B_ADC1_AIN11 ((1UL) << 1) - -/* ========== PORT definition for CAN0 peripheral ========== */ -#define PIN_PA23I_CAN0_RX (23L) -#define MUX_PA23I_CAN0_RX (8L) -#define PINMUX_PA23I_CAN0_RX ((PIN_PA23I_CAN0_RX << 16) | MUX_PA23I_CAN0_RX) -#define PORT_PA23I_CAN0_RX ((1UL) << 23) - -#define PIN_PA25I_CAN0_RX (25L) -#define MUX_PA25I_CAN0_RX (8L) -#define PINMUX_PA25I_CAN0_RX ((PIN_PA25I_CAN0_RX << 16) | MUX_PA25I_CAN0_RX) -#define PORT_PA25I_CAN0_RX ((1UL) << 25) - -#define PIN_PA22I_CAN0_TX (22L) -#define MUX_PA22I_CAN0_TX (8L) -#define PINMUX_PA22I_CAN0_TX ((PIN_PA22I_CAN0_TX << 16) | MUX_PA22I_CAN0_TX) -#define PORT_PA22I_CAN0_TX ((1UL) << 22) - -#define PIN_PA24I_CAN0_TX (24L) -#define MUX_PA24I_CAN0_TX (8L) -#define PINMUX_PA24I_CAN0_TX ((PIN_PA24I_CAN0_TX << 16) | MUX_PA24I_CAN0_TX) -#define PORT_PA24I_CAN0_TX ((1UL) << 24) - -/* ========== PORT definition for CAN1 peripheral ========== */ -#define PIN_PB13H_CAN1_RX (45L) -#define MUX_PB13H_CAN1_RX (7L) -#define PINMUX_PB13H_CAN1_RX ((PIN_PB13H_CAN1_RX << 16) | MUX_PB13H_CAN1_RX) -#define PORT_PB13H_CAN1_RX ((1UL) << 13) - -#define PIN_PB15H_CAN1_RX (47L) -#define MUX_PB15H_CAN1_RX (7L) -#define PINMUX_PB15H_CAN1_RX ((PIN_PB15H_CAN1_RX << 16) | MUX_PB15H_CAN1_RX) -#define PORT_PB15H_CAN1_RX ((1UL) << 15) - -#define PIN_PB12H_CAN1_TX (44L) -#define MUX_PB12H_CAN1_TX (7L) -#define PINMUX_PB12H_CAN1_TX ((PIN_PB12H_CAN1_TX << 16) | MUX_PB12H_CAN1_TX) -#define PORT_PB12H_CAN1_TX ((1UL) << 12) - -#define PIN_PB14H_CAN1_TX (46L) -#define MUX_PB14H_CAN1_TX (7L) -#define PINMUX_PB14H_CAN1_TX ((PIN_PB14H_CAN1_TX << 16) | MUX_PB14H_CAN1_TX) -#define PORT_PB14H_CAN1_TX ((1UL) << 14) - -/* ========== PORT definition for CCL peripheral ========== */ -#define PIN_PA04N_CCL_IN0 (4L) -#define MUX_PA04N_CCL_IN0 (13L) -#define PINMUX_PA04N_CCL_IN0 ((PIN_PA04N_CCL_IN0 << 16) | MUX_PA04N_CCL_IN0) -#define PORT_PA04N_CCL_IN0 ((1UL) << 4) - -#define PIN_PA16N_CCL_IN0 (16L) -#define MUX_PA16N_CCL_IN0 (13L) -#define PINMUX_PA16N_CCL_IN0 ((PIN_PA16N_CCL_IN0 << 16) | MUX_PA16N_CCL_IN0) -#define PORT_PA16N_CCL_IN0 ((1UL) << 16) - -#define PIN_PB22N_CCL_IN0 (54L) -#define MUX_PB22N_CCL_IN0 (13L) -#define PINMUX_PB22N_CCL_IN0 ((PIN_PB22N_CCL_IN0 << 16) | MUX_PB22N_CCL_IN0) -#define PORT_PB22N_CCL_IN0 ((1UL) << 22) - -#define PIN_PA05N_CCL_IN1 (5L) -#define MUX_PA05N_CCL_IN1 (13L) -#define PINMUX_PA05N_CCL_IN1 ((PIN_PA05N_CCL_IN1 << 16) | MUX_PA05N_CCL_IN1) -#define PORT_PA05N_CCL_IN1 ((1UL) << 5) - -#define PIN_PA17N_CCL_IN1 (17L) -#define MUX_PA17N_CCL_IN1 (13L) -#define PINMUX_PA17N_CCL_IN1 ((PIN_PA17N_CCL_IN1 << 16) | MUX_PA17N_CCL_IN1) -#define PORT_PA17N_CCL_IN1 ((1UL) << 17) - -#define PIN_PB00N_CCL_IN1 (32L) -#define MUX_PB00N_CCL_IN1 (13L) -#define PINMUX_PB00N_CCL_IN1 ((PIN_PB00N_CCL_IN1 << 16) | MUX_PB00N_CCL_IN1) -#define PORT_PB00N_CCL_IN1 ((1UL) << 0) - -#define PIN_PA06N_CCL_IN2 (6L) -#define MUX_PA06N_CCL_IN2 (13L) -#define PINMUX_PA06N_CCL_IN2 ((PIN_PA06N_CCL_IN2 << 16) | MUX_PA06N_CCL_IN2) -#define PORT_PA06N_CCL_IN2 ((1UL) << 6) - -#define PIN_PA18N_CCL_IN2 (18L) -#define MUX_PA18N_CCL_IN2 (13L) -#define PINMUX_PA18N_CCL_IN2 ((PIN_PA18N_CCL_IN2 << 16) | MUX_PA18N_CCL_IN2) -#define PORT_PA18N_CCL_IN2 ((1UL) << 18) - -#define PIN_PB01N_CCL_IN2 (33L) -#define MUX_PB01N_CCL_IN2 (13L) -#define PINMUX_PB01N_CCL_IN2 ((PIN_PB01N_CCL_IN2 << 16) | MUX_PB01N_CCL_IN2) -#define PORT_PB01N_CCL_IN2 ((1UL) << 1) - -#define PIN_PA08N_CCL_IN3 (8L) -#define MUX_PA08N_CCL_IN3 (13L) -#define PINMUX_PA08N_CCL_IN3 ((PIN_PA08N_CCL_IN3 << 16) | MUX_PA08N_CCL_IN3) -#define PORT_PA08N_CCL_IN3 ((1UL) << 8) - -#define PIN_PA30N_CCL_IN3 (30L) -#define MUX_PA30N_CCL_IN3 (13L) -#define PINMUX_PA30N_CCL_IN3 ((PIN_PA30N_CCL_IN3 << 16) | MUX_PA30N_CCL_IN3) -#define PORT_PA30N_CCL_IN3 ((1UL) << 30) - -#define PIN_PA09N_CCL_IN4 (9L) -#define MUX_PA09N_CCL_IN4 (13L) -#define PINMUX_PA09N_CCL_IN4 ((PIN_PA09N_CCL_IN4 << 16) | MUX_PA09N_CCL_IN4) -#define PORT_PA09N_CCL_IN4 ((1UL) << 9) - -#define PIN_PC27N_CCL_IN4 (91L) -#define MUX_PC27N_CCL_IN4 (13L) -#define PINMUX_PC27N_CCL_IN4 ((PIN_PC27N_CCL_IN4 << 16) | MUX_PC27N_CCL_IN4) -#define PORT_PC27N_CCL_IN4 ((1UL) << 27) - -#define PIN_PA10N_CCL_IN5 (10L) -#define MUX_PA10N_CCL_IN5 (13L) -#define PINMUX_PA10N_CCL_IN5 ((PIN_PA10N_CCL_IN5 << 16) | MUX_PA10N_CCL_IN5) -#define PORT_PA10N_CCL_IN5 ((1UL) << 10) - -#define PIN_PC28N_CCL_IN5 (92L) -#define MUX_PC28N_CCL_IN5 (13L) -#define PINMUX_PC28N_CCL_IN5 ((PIN_PC28N_CCL_IN5 << 16) | MUX_PC28N_CCL_IN5) -#define PORT_PC28N_CCL_IN5 ((1UL) << 28) - -#define PIN_PA22N_CCL_IN6 (22L) -#define MUX_PA22N_CCL_IN6 (13L) -#define PINMUX_PA22N_CCL_IN6 ((PIN_PA22N_CCL_IN6 << 16) | MUX_PA22N_CCL_IN6) -#define PORT_PA22N_CCL_IN6 ((1UL) << 22) - -#define PIN_PB06N_CCL_IN6 (38L) -#define MUX_PB06N_CCL_IN6 (13L) -#define PINMUX_PB06N_CCL_IN6 ((PIN_PB06N_CCL_IN6 << 16) | MUX_PB06N_CCL_IN6) -#define PORT_PB06N_CCL_IN6 ((1UL) << 6) - -#define PIN_PA23N_CCL_IN7 (23L) -#define MUX_PA23N_CCL_IN7 (13L) -#define PINMUX_PA23N_CCL_IN7 ((PIN_PA23N_CCL_IN7 << 16) | MUX_PA23N_CCL_IN7) -#define PORT_PA23N_CCL_IN7 ((1UL) << 23) - -#define PIN_PB07N_CCL_IN7 (39L) -#define MUX_PB07N_CCL_IN7 (13L) -#define PINMUX_PB07N_CCL_IN7 ((PIN_PB07N_CCL_IN7 << 16) | MUX_PB07N_CCL_IN7) -#define PORT_PB07N_CCL_IN7 ((1UL) << 7) - -#define PIN_PA24N_CCL_IN8 (24L) -#define MUX_PA24N_CCL_IN8 (13L) -#define PINMUX_PA24N_CCL_IN8 ((PIN_PA24N_CCL_IN8 << 16) | MUX_PA24N_CCL_IN8) -#define PORT_PA24N_CCL_IN8 ((1UL) << 24) - -#define PIN_PB08N_CCL_IN8 (40L) -#define MUX_PB08N_CCL_IN8 (13L) -#define PINMUX_PB08N_CCL_IN8 ((PIN_PB08N_CCL_IN8 << 16) | MUX_PB08N_CCL_IN8) -#define PORT_PB08N_CCL_IN8 ((1UL) << 8) - -#define PIN_PB14N_CCL_IN9 (46L) -#define MUX_PB14N_CCL_IN9 (13L) -#define PINMUX_PB14N_CCL_IN9 ((PIN_PB14N_CCL_IN9 << 16) | MUX_PB14N_CCL_IN9) -#define PORT_PB14N_CCL_IN9 ((1UL) << 14) - -#define PIN_PC20N_CCL_IN9 (84L) -#define MUX_PC20N_CCL_IN9 (13L) -#define PINMUX_PC20N_CCL_IN9 ((PIN_PC20N_CCL_IN9 << 16) | MUX_PC20N_CCL_IN9) -#define PORT_PC20N_CCL_IN9 ((1UL) << 20) - -#define PIN_PB15N_CCL_IN10 (47L) -#define MUX_PB15N_CCL_IN10 (13L) -#define PINMUX_PB15N_CCL_IN10 ((PIN_PB15N_CCL_IN10 << 16) | MUX_PB15N_CCL_IN10) -#define PORT_PB15N_CCL_IN10 ((1UL) << 15) - -#define PIN_PC21N_CCL_IN10 (85L) -#define MUX_PC21N_CCL_IN10 (13L) -#define PINMUX_PC21N_CCL_IN10 ((PIN_PC21N_CCL_IN10 << 16) | MUX_PC21N_CCL_IN10) -#define PORT_PC21N_CCL_IN10 ((1UL) << 21) - -#define PIN_PB10N_CCL_IN11 (42L) -#define MUX_PB10N_CCL_IN11 (13L) -#define PINMUX_PB10N_CCL_IN11 ((PIN_PB10N_CCL_IN11 << 16) | MUX_PB10N_CCL_IN11) -#define PORT_PB10N_CCL_IN11 ((1UL) << 10) - -#define PIN_PB16N_CCL_IN11 (48L) -#define MUX_PB16N_CCL_IN11 (13L) -#define PINMUX_PB16N_CCL_IN11 ((PIN_PB16N_CCL_IN11 << 16) | MUX_PB16N_CCL_IN11) -#define PORT_PB16N_CCL_IN11 ((1UL) << 16) - -#define PIN_PA07N_CCL_OUT0 (7L) -#define MUX_PA07N_CCL_OUT0 (13L) -#define PINMUX_PA07N_CCL_OUT0 ((PIN_PA07N_CCL_OUT0 << 16) | MUX_PA07N_CCL_OUT0) -#define PORT_PA07N_CCL_OUT0 ((1UL) << 7) - -#define PIN_PA19N_CCL_OUT0 (19L) -#define MUX_PA19N_CCL_OUT0 (13L) -#define PINMUX_PA19N_CCL_OUT0 ((PIN_PA19N_CCL_OUT0 << 16) | MUX_PA19N_CCL_OUT0) -#define PORT_PA19N_CCL_OUT0 ((1UL) << 19) - -#define PIN_PB02N_CCL_OUT0 (34L) -#define MUX_PB02N_CCL_OUT0 (13L) -#define PINMUX_PB02N_CCL_OUT0 ((PIN_PB02N_CCL_OUT0 << 16) | MUX_PB02N_CCL_OUT0) -#define PORT_PB02N_CCL_OUT0 ((1UL) << 2) - -#define PIN_PB23N_CCL_OUT0 (55L) -#define MUX_PB23N_CCL_OUT0 (13L) -#define PINMUX_PB23N_CCL_OUT0 ((PIN_PB23N_CCL_OUT0 << 16) | MUX_PB23N_CCL_OUT0) -#define PORT_PB23N_CCL_OUT0 ((1UL) << 23) - -#define PIN_PA11N_CCL_OUT1 (11L) -#define MUX_PA11N_CCL_OUT1 (13L) -#define PINMUX_PA11N_CCL_OUT1 ((PIN_PA11N_CCL_OUT1 << 16) | MUX_PA11N_CCL_OUT1) -#define PORT_PA11N_CCL_OUT1 ((1UL) << 11) - -#define PIN_PA31N_CCL_OUT1 (31L) -#define MUX_PA31N_CCL_OUT1 (13L) -#define PINMUX_PA31N_CCL_OUT1 ((PIN_PA31N_CCL_OUT1 << 16) | MUX_PA31N_CCL_OUT1) -#define PORT_PA31N_CCL_OUT1 ((1UL) << 31) - -#define PIN_PB11N_CCL_OUT1 (43L) -#define MUX_PB11N_CCL_OUT1 (13L) -#define PINMUX_PB11N_CCL_OUT1 ((PIN_PB11N_CCL_OUT1 << 16) | MUX_PB11N_CCL_OUT1) -#define PORT_PB11N_CCL_OUT1 ((1UL) << 11) - -#define PIN_PA25N_CCL_OUT2 (25L) -#define MUX_PA25N_CCL_OUT2 (13L) -#define PINMUX_PA25N_CCL_OUT2 ((PIN_PA25N_CCL_OUT2 << 16) | MUX_PA25N_CCL_OUT2) -#define PORT_PA25N_CCL_OUT2 ((1UL) << 25) - -#define PIN_PB09N_CCL_OUT2 (41L) -#define MUX_PB09N_CCL_OUT2 (13L) -#define PINMUX_PB09N_CCL_OUT2 ((PIN_PB09N_CCL_OUT2 << 16) | MUX_PB09N_CCL_OUT2) -#define PORT_PB09N_CCL_OUT2 ((1UL) << 9) - -#define PIN_PB17N_CCL_OUT3 (49L) -#define MUX_PB17N_CCL_OUT3 (13L) -#define PINMUX_PB17N_CCL_OUT3 ((PIN_PB17N_CCL_OUT3 << 16) | MUX_PB17N_CCL_OUT3) -#define PORT_PB17N_CCL_OUT3 ((1UL) << 17) - -/* ========== PORT definition for DAC peripheral ========== */ -#define PIN_PA02B_DAC_VOUT0 (2L) -#define MUX_PA02B_DAC_VOUT0 (1L) -#define PINMUX_PA02B_DAC_VOUT0 ((PIN_PA02B_DAC_VOUT0 << 16) | MUX_PA02B_DAC_VOUT0) -#define PORT_PA02B_DAC_VOUT0 ((1UL) << 2) - -#define PIN_PA05B_DAC_VOUT1 (5L) -#define MUX_PA05B_DAC_VOUT1 (1L) -#define PINMUX_PA05B_DAC_VOUT1 ((PIN_PA05B_DAC_VOUT1 << 16) | MUX_PA05B_DAC_VOUT1) -#define PORT_PA05B_DAC_VOUT1 ((1UL) << 5) - -/* ========== PORT definition for EIC peripheral ========== */ -#define PIN_PA00A_EIC_EXTINT0 (0L) -#define MUX_PA00A_EIC_EXTINT0 (0L) -#define PINMUX_PA00A_EIC_EXTINT0 ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0) -#define PORT_PA00A_EIC_EXTINT0 ((1UL) << 0) -#define PIN_PA00A_EIC_EXTINT_NUM _L_(0) /**< EIC signal: PIN_PA00 External Interrupt Line */ - -#define PIN_PA16A_EIC_EXTINT0 (16L) -#define MUX_PA16A_EIC_EXTINT0 (0L) -#define PINMUX_PA16A_EIC_EXTINT0 ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0) -#define PORT_PA16A_EIC_EXTINT0 ((1UL) << 16) -#define PIN_PA16A_EIC_EXTINT_NUM _L_(0) /**< EIC signal: PIN_PA16 External Interrupt Line */ - -#define PIN_PB00A_EIC_EXTINT0 (32L) -#define MUX_PB00A_EIC_EXTINT0 (0L) -#define PINMUX_PB00A_EIC_EXTINT0 ((PIN_PB00A_EIC_EXTINT0 << 16) | MUX_PB00A_EIC_EXTINT0) -#define PORT_PB00A_EIC_EXTINT0 ((1UL) << 0) -#define PIN_PB00A_EIC_EXTINT_NUM _L_(0) /**< EIC signal: PIN_PB00 External Interrupt Line */ - -#define PIN_PB16A_EIC_EXTINT0 (48L) -#define MUX_PB16A_EIC_EXTINT0 (0L) -#define PINMUX_PB16A_EIC_EXTINT0 ((PIN_PB16A_EIC_EXTINT0 << 16) | MUX_PB16A_EIC_EXTINT0) -#define PORT_PB16A_EIC_EXTINT0 ((1UL) << 16) -#define PIN_PB16A_EIC_EXTINT_NUM _L_(0) /**< EIC signal: PIN_PB16 External Interrupt Line */ - -#define PIN_PC00A_EIC_EXTINT0 (64L) -#define MUX_PC00A_EIC_EXTINT0 (0L) -#define PINMUX_PC00A_EIC_EXTINT0 ((PIN_PC00A_EIC_EXTINT0 << 16) | MUX_PC00A_EIC_EXTINT0) -#define PORT_PC00A_EIC_EXTINT0 ((1UL) << 0) -#define PIN_PC00A_EIC_EXTINT_NUM _L_(0) /**< EIC signal: PIN_PC00 External Interrupt Line */ - -#define PIN_PC16A_EIC_EXTINT0 (80L) -#define MUX_PC16A_EIC_EXTINT0 (0L) -#define PINMUX_PC16A_EIC_EXTINT0 ((PIN_PC16A_EIC_EXTINT0 << 16) | MUX_PC16A_EIC_EXTINT0) -#define PORT_PC16A_EIC_EXTINT0 ((1UL) << 16) -#define PIN_PC16A_EIC_EXTINT_NUM _L_(0) /**< EIC signal: PIN_PC16 External Interrupt Line */ - -#define PIN_PA01A_EIC_EXTINT1 (1L) -#define MUX_PA01A_EIC_EXTINT1 (0L) -#define PINMUX_PA01A_EIC_EXTINT1 ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1) -#define PORT_PA01A_EIC_EXTINT1 ((1UL) << 1) -#define PIN_PA01A_EIC_EXTINT_NUM _L_(1) /**< EIC signal: PIN_PA01 External Interrupt Line */ - -#define PIN_PA17A_EIC_EXTINT1 (17L) -#define MUX_PA17A_EIC_EXTINT1 (0L) -#define PINMUX_PA17A_EIC_EXTINT1 ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1) -#define PORT_PA17A_EIC_EXTINT1 ((1UL) << 17) -#define PIN_PA17A_EIC_EXTINT_NUM _L_(1) /**< EIC signal: PIN_PA17 External Interrupt Line */ - -#define PIN_PB01A_EIC_EXTINT1 (33L) -#define MUX_PB01A_EIC_EXTINT1 (0L) -#define PINMUX_PB01A_EIC_EXTINT1 ((PIN_PB01A_EIC_EXTINT1 << 16) | MUX_PB01A_EIC_EXTINT1) -#define PORT_PB01A_EIC_EXTINT1 ((1UL) << 1) -#define PIN_PB01A_EIC_EXTINT_NUM _L_(1) /**< EIC signal: PIN_PB01 External Interrupt Line */ - -#define PIN_PB17A_EIC_EXTINT1 (49L) -#define MUX_PB17A_EIC_EXTINT1 (0L) -#define PINMUX_PB17A_EIC_EXTINT1 ((PIN_PB17A_EIC_EXTINT1 << 16) | MUX_PB17A_EIC_EXTINT1) -#define PORT_PB17A_EIC_EXTINT1 ((1UL) << 17) -#define PIN_PB17A_EIC_EXTINT_NUM _L_(1) /**< EIC signal: PIN_PB17 External Interrupt Line */ - -#define PIN_PC01A_EIC_EXTINT1 (65L) -#define MUX_PC01A_EIC_EXTINT1 (0L) -#define PINMUX_PC01A_EIC_EXTINT1 ((PIN_PC01A_EIC_EXTINT1 << 16) | MUX_PC01A_EIC_EXTINT1) -#define PORT_PC01A_EIC_EXTINT1 ((1UL) << 1) -#define PIN_PC01A_EIC_EXTINT_NUM _L_(1) /**< EIC signal: PIN_PC01 External Interrupt Line */ - -#define PIN_PC17A_EIC_EXTINT1 (81L) -#define MUX_PC17A_EIC_EXTINT1 (0L) -#define PINMUX_PC17A_EIC_EXTINT1 ((PIN_PC17A_EIC_EXTINT1 << 16) | MUX_PC17A_EIC_EXTINT1) -#define PORT_PC17A_EIC_EXTINT1 ((1UL) << 17) -#define PIN_PC17A_EIC_EXTINT_NUM _L_(1) /**< EIC signal: PIN_PC17 External Interrupt Line */ - -#define PIN_PA02A_EIC_EXTINT2 (2L) -#define MUX_PA02A_EIC_EXTINT2 (0L) -#define PINMUX_PA02A_EIC_EXTINT2 ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2) -#define PORT_PA02A_EIC_EXTINT2 ((1UL) << 2) -#define PIN_PA02A_EIC_EXTINT_NUM _L_(2) /**< EIC signal: PIN_PA02 External Interrupt Line */ - -#define PIN_PA18A_EIC_EXTINT2 (18L) -#define MUX_PA18A_EIC_EXTINT2 (0L) -#define PINMUX_PA18A_EIC_EXTINT2 ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2) -#define PORT_PA18A_EIC_EXTINT2 ((1UL) << 18) -#define PIN_PA18A_EIC_EXTINT_NUM _L_(2) /**< EIC signal: PIN_PA18 External Interrupt Line */ - -#define PIN_PB02A_EIC_EXTINT2 (34L) -#define MUX_PB02A_EIC_EXTINT2 (0L) -#define PINMUX_PB02A_EIC_EXTINT2 ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2) -#define PORT_PB02A_EIC_EXTINT2 ((1UL) << 2) -#define PIN_PB02A_EIC_EXTINT_NUM _L_(2) /**< EIC signal: PIN_PB02 External Interrupt Line */ - -#define PIN_PB18A_EIC_EXTINT2 (50L) -#define MUX_PB18A_EIC_EXTINT2 (0L) -#define PINMUX_PB18A_EIC_EXTINT2 ((PIN_PB18A_EIC_EXTINT2 << 16) | MUX_PB18A_EIC_EXTINT2) -#define PORT_PB18A_EIC_EXTINT2 ((1UL) << 18) -#define PIN_PB18A_EIC_EXTINT_NUM _L_(2) /**< EIC signal: PIN_PB18 External Interrupt Line */ - -#define PIN_PC02A_EIC_EXTINT2 (66L) -#define MUX_PC02A_EIC_EXTINT2 (0L) -#define PINMUX_PC02A_EIC_EXTINT2 ((PIN_PC02A_EIC_EXTINT2 << 16) | MUX_PC02A_EIC_EXTINT2) -#define PORT_PC02A_EIC_EXTINT2 ((1UL) << 2) -#define PIN_PC02A_EIC_EXTINT_NUM _L_(2) /**< EIC signal: PIN_PC02 External Interrupt Line */ - -#define PIN_PC18A_EIC_EXTINT2 (82L) -#define MUX_PC18A_EIC_EXTINT2 (0L) -#define PINMUX_PC18A_EIC_EXTINT2 ((PIN_PC18A_EIC_EXTINT2 << 16) | MUX_PC18A_EIC_EXTINT2) -#define PORT_PC18A_EIC_EXTINT2 ((1UL) << 18) -#define PIN_PC18A_EIC_EXTINT_NUM _L_(2) /**< EIC signal: PIN_PC18 External Interrupt Line */ - -#define PIN_PA03A_EIC_EXTINT3 (3L) -#define MUX_PA03A_EIC_EXTINT3 (0L) -#define PINMUX_PA03A_EIC_EXTINT3 ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3) -#define PORT_PA03A_EIC_EXTINT3 ((1UL) << 3) -#define PIN_PA03A_EIC_EXTINT_NUM _L_(3) /**< EIC signal: PIN_PA03 External Interrupt Line */ - -#define PIN_PA19A_EIC_EXTINT3 (19L) -#define MUX_PA19A_EIC_EXTINT3 (0L) -#define PINMUX_PA19A_EIC_EXTINT3 ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3) -#define PORT_PA19A_EIC_EXTINT3 ((1UL) << 19) -#define PIN_PA19A_EIC_EXTINT_NUM _L_(3) /**< EIC signal: PIN_PA19 External Interrupt Line */ - -#define PIN_PB03A_EIC_EXTINT3 (35L) -#define MUX_PB03A_EIC_EXTINT3 (0L) -#define PINMUX_PB03A_EIC_EXTINT3 ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3) -#define PORT_PB03A_EIC_EXTINT3 ((1UL) << 3) -#define PIN_PB03A_EIC_EXTINT_NUM _L_(3) /**< EIC signal: PIN_PB03 External Interrupt Line */ - -#define PIN_PB19A_EIC_EXTINT3 (51L) -#define MUX_PB19A_EIC_EXTINT3 (0L) -#define PINMUX_PB19A_EIC_EXTINT3 ((PIN_PB19A_EIC_EXTINT3 << 16) | MUX_PB19A_EIC_EXTINT3) -#define PORT_PB19A_EIC_EXTINT3 ((1UL) << 19) -#define PIN_PB19A_EIC_EXTINT_NUM _L_(3) /**< EIC signal: PIN_PB19 External Interrupt Line */ - -#define PIN_PC03A_EIC_EXTINT3 (67L) -#define MUX_PC03A_EIC_EXTINT3 (0L) -#define PINMUX_PC03A_EIC_EXTINT3 ((PIN_PC03A_EIC_EXTINT3 << 16) | MUX_PC03A_EIC_EXTINT3) -#define PORT_PC03A_EIC_EXTINT3 ((1UL) << 3) -#define PIN_PC03A_EIC_EXTINT_NUM _L_(3) /**< EIC signal: PIN_PC03 External Interrupt Line */ - -#define PIN_PC19A_EIC_EXTINT3 (83L) -#define MUX_PC19A_EIC_EXTINT3 (0L) -#define PINMUX_PC19A_EIC_EXTINT3 ((PIN_PC19A_EIC_EXTINT3 << 16) | MUX_PC19A_EIC_EXTINT3) -#define PORT_PC19A_EIC_EXTINT3 ((1UL) << 19) -#define PIN_PC19A_EIC_EXTINT_NUM _L_(3) /**< EIC signal: PIN_PC19 External Interrupt Line */ - -#define PIN_PA04A_EIC_EXTINT4 (4L) -#define MUX_PA04A_EIC_EXTINT4 (0L) -#define PINMUX_PA04A_EIC_EXTINT4 ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4) -#define PORT_PA04A_EIC_EXTINT4 ((1UL) << 4) -#define PIN_PA04A_EIC_EXTINT_NUM _L_(4) /**< EIC signal: PIN_PA04 External Interrupt Line */ - -#define PIN_PA20A_EIC_EXTINT4 (20L) -#define MUX_PA20A_EIC_EXTINT4 (0L) -#define PINMUX_PA20A_EIC_EXTINT4 ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4) -#define PORT_PA20A_EIC_EXTINT4 ((1UL) << 20) -#define PIN_PA20A_EIC_EXTINT_NUM _L_(4) /**< EIC signal: PIN_PA20 External Interrupt Line */ - -#define PIN_PB04A_EIC_EXTINT4 (36L) -#define MUX_PB04A_EIC_EXTINT4 (0L) -#define PINMUX_PB04A_EIC_EXTINT4 ((PIN_PB04A_EIC_EXTINT4 << 16) | MUX_PB04A_EIC_EXTINT4) -#define PORT_PB04A_EIC_EXTINT4 ((1UL) << 4) -#define PIN_PB04A_EIC_EXTINT_NUM _L_(4) /**< EIC signal: PIN_PB04 External Interrupt Line */ - -#define PIN_PB20A_EIC_EXTINT4 (52L) -#define MUX_PB20A_EIC_EXTINT4 (0L) -#define PINMUX_PB20A_EIC_EXTINT4 ((PIN_PB20A_EIC_EXTINT4 << 16) | MUX_PB20A_EIC_EXTINT4) -#define PORT_PB20A_EIC_EXTINT4 ((1UL) << 20) -#define PIN_PB20A_EIC_EXTINT_NUM _L_(4) /**< EIC signal: PIN_PB20 External Interrupt Line */ - -#define PIN_PC20A_EIC_EXTINT4 (84L) -#define MUX_PC20A_EIC_EXTINT4 (0L) -#define PINMUX_PC20A_EIC_EXTINT4 ((PIN_PC20A_EIC_EXTINT4 << 16) | MUX_PC20A_EIC_EXTINT4) -#define PORT_PC20A_EIC_EXTINT4 ((1UL) << 20) -#define PIN_PC20A_EIC_EXTINT_NUM _L_(4) /**< EIC signal: PIN_PC20 External Interrupt Line */ - -#define PIN_PA05A_EIC_EXTINT5 (5L) -#define MUX_PA05A_EIC_EXTINT5 (0L) -#define PINMUX_PA05A_EIC_EXTINT5 ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5) -#define PORT_PA05A_EIC_EXTINT5 ((1UL) << 5) -#define PIN_PA05A_EIC_EXTINT_NUM _L_(5) /**< EIC signal: PIN_PA05 External Interrupt Line */ - -#define PIN_PA21A_EIC_EXTINT5 (21L) -#define MUX_PA21A_EIC_EXTINT5 (0L) -#define PINMUX_PA21A_EIC_EXTINT5 ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5) -#define PORT_PA21A_EIC_EXTINT5 ((1UL) << 21) -#define PIN_PA21A_EIC_EXTINT_NUM _L_(5) /**< EIC signal: PIN_PA21 External Interrupt Line */ - -#define PIN_PB05A_EIC_EXTINT5 (37L) -#define MUX_PB05A_EIC_EXTINT5 (0L) -#define PINMUX_PB05A_EIC_EXTINT5 ((PIN_PB05A_EIC_EXTINT5 << 16) | MUX_PB05A_EIC_EXTINT5) -#define PORT_PB05A_EIC_EXTINT5 ((1UL) << 5) -#define PIN_PB05A_EIC_EXTINT_NUM _L_(5) /**< EIC signal: PIN_PB05 External Interrupt Line */ - -#define PIN_PB21A_EIC_EXTINT5 (53L) -#define MUX_PB21A_EIC_EXTINT5 (0L) -#define PINMUX_PB21A_EIC_EXTINT5 ((PIN_PB21A_EIC_EXTINT5 << 16) | MUX_PB21A_EIC_EXTINT5) -#define PORT_PB21A_EIC_EXTINT5 ((1UL) << 21) -#define PIN_PB21A_EIC_EXTINT_NUM _L_(5) /**< EIC signal: PIN_PB21 External Interrupt Line */ - -#define PIN_PC05A_EIC_EXTINT5 (69L) -#define MUX_PC05A_EIC_EXTINT5 (0L) -#define PINMUX_PC05A_EIC_EXTINT5 ((PIN_PC05A_EIC_EXTINT5 << 16) | MUX_PC05A_EIC_EXTINT5) -#define PORT_PC05A_EIC_EXTINT5 ((1UL) << 5) -#define PIN_PC05A_EIC_EXTINT_NUM _L_(5) /**< EIC signal: PIN_PC05 External Interrupt Line */ - -#define PIN_PC21A_EIC_EXTINT5 (85L) -#define MUX_PC21A_EIC_EXTINT5 (0L) -#define PINMUX_PC21A_EIC_EXTINT5 ((PIN_PC21A_EIC_EXTINT5 << 16) | MUX_PC21A_EIC_EXTINT5) -#define PORT_PC21A_EIC_EXTINT5 ((1UL) << 21) -#define PIN_PC21A_EIC_EXTINT_NUM _L_(5) /**< EIC signal: PIN_PC21 External Interrupt Line */ - -#define PIN_PA06A_EIC_EXTINT6 (6L) -#define MUX_PA06A_EIC_EXTINT6 (0L) -#define PINMUX_PA06A_EIC_EXTINT6 ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6) -#define PORT_PA06A_EIC_EXTINT6 ((1UL) << 6) -#define PIN_PA06A_EIC_EXTINT_NUM _L_(6) /**< EIC signal: PIN_PA06 External Interrupt Line */ - -#define PIN_PA22A_EIC_EXTINT6 (22L) -#define MUX_PA22A_EIC_EXTINT6 (0L) -#define PINMUX_PA22A_EIC_EXTINT6 ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6) -#define PORT_PA22A_EIC_EXTINT6 ((1UL) << 22) -#define PIN_PA22A_EIC_EXTINT_NUM _L_(6) /**< EIC signal: PIN_PA22 External Interrupt Line */ - -#define PIN_PB06A_EIC_EXTINT6 (38L) -#define MUX_PB06A_EIC_EXTINT6 (0L) -#define PINMUX_PB06A_EIC_EXTINT6 ((PIN_PB06A_EIC_EXTINT6 << 16) | MUX_PB06A_EIC_EXTINT6) -#define PORT_PB06A_EIC_EXTINT6 ((1UL) << 6) -#define PIN_PB06A_EIC_EXTINT_NUM _L_(6) /**< EIC signal: PIN_PB06 External Interrupt Line */ - -#define PIN_PB22A_EIC_EXTINT6 (54L) -#define MUX_PB22A_EIC_EXTINT6 (0L) -#define PINMUX_PB22A_EIC_EXTINT6 ((PIN_PB22A_EIC_EXTINT6 << 16) | MUX_PB22A_EIC_EXTINT6) -#define PORT_PB22A_EIC_EXTINT6 ((1UL) << 22) -#define PIN_PB22A_EIC_EXTINT_NUM _L_(6) /**< EIC signal: PIN_PB22 External Interrupt Line */ - -#define PIN_PC06A_EIC_EXTINT6 (70L) -#define MUX_PC06A_EIC_EXTINT6 (0L) -#define PINMUX_PC06A_EIC_EXTINT6 ((PIN_PC06A_EIC_EXTINT6 << 16) | MUX_PC06A_EIC_EXTINT6) -#define PORT_PC06A_EIC_EXTINT6 ((1UL) << 6) -#define PIN_PC06A_EIC_EXTINT_NUM _L_(6) /**< EIC signal: PIN_PC06 External Interrupt Line */ - -#define PIN_PA07A_EIC_EXTINT7 (7L) -#define MUX_PA07A_EIC_EXTINT7 (0L) -#define PINMUX_PA07A_EIC_EXTINT7 ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7) -#define PORT_PA07A_EIC_EXTINT7 ((1UL) << 7) -#define PIN_PA07A_EIC_EXTINT_NUM _L_(7) /**< EIC signal: PIN_PA07 External Interrupt Line */ - -#define PIN_PA23A_EIC_EXTINT7 (23L) -#define MUX_PA23A_EIC_EXTINT7 (0L) -#define PINMUX_PA23A_EIC_EXTINT7 ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7) -#define PORT_PA23A_EIC_EXTINT7 ((1UL) << 23) -#define PIN_PA23A_EIC_EXTINT_NUM _L_(7) /**< EIC signal: PIN_PA23 External Interrupt Line */ - -#define PIN_PB07A_EIC_EXTINT7 (39L) -#define MUX_PB07A_EIC_EXTINT7 (0L) -#define PINMUX_PB07A_EIC_EXTINT7 ((PIN_PB07A_EIC_EXTINT7 << 16) | MUX_PB07A_EIC_EXTINT7) -#define PORT_PB07A_EIC_EXTINT7 ((1UL) << 7) -#define PIN_PB07A_EIC_EXTINT_NUM _L_(7) /**< EIC signal: PIN_PB07 External Interrupt Line */ - -#define PIN_PB23A_EIC_EXTINT7 (55L) -#define MUX_PB23A_EIC_EXTINT7 (0L) -#define PINMUX_PB23A_EIC_EXTINT7 ((PIN_PB23A_EIC_EXTINT7 << 16) | MUX_PB23A_EIC_EXTINT7) -#define PORT_PB23A_EIC_EXTINT7 ((1UL) << 23) -#define PIN_PB23A_EIC_EXTINT_NUM _L_(7) /**< EIC signal: PIN_PB23 External Interrupt Line */ - -#define PIN_PA24A_EIC_EXTINT8 (24L) -#define MUX_PA24A_EIC_EXTINT8 (0L) -#define PINMUX_PA24A_EIC_EXTINT8 ((PIN_PA24A_EIC_EXTINT8 << 16) | MUX_PA24A_EIC_EXTINT8) -#define PORT_PA24A_EIC_EXTINT8 ((1UL) << 24) -#define PIN_PA24A_EIC_EXTINT_NUM _L_(8) /**< EIC signal: PIN_PA24 External Interrupt Line */ - -#define PIN_PB08A_EIC_EXTINT8 (40L) -#define MUX_PB08A_EIC_EXTINT8 (0L) -#define PINMUX_PB08A_EIC_EXTINT8 ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8) -#define PORT_PB08A_EIC_EXTINT8 ((1UL) << 8) -#define PIN_PB08A_EIC_EXTINT_NUM _L_(8) /**< EIC signal: PIN_PB08 External Interrupt Line */ - -#define PIN_PB24A_EIC_EXTINT8 (56L) -#define MUX_PB24A_EIC_EXTINT8 (0L) -#define PINMUX_PB24A_EIC_EXTINT8 ((PIN_PB24A_EIC_EXTINT8 << 16) | MUX_PB24A_EIC_EXTINT8) -#define PORT_PB24A_EIC_EXTINT8 ((1UL) << 24) -#define PIN_PB24A_EIC_EXTINT_NUM _L_(8) /**< EIC signal: PIN_PB24 External Interrupt Line */ - -#define PIN_PC24A_EIC_EXTINT8 (88L) -#define MUX_PC24A_EIC_EXTINT8 (0L) -#define PINMUX_PC24A_EIC_EXTINT8 ((PIN_PC24A_EIC_EXTINT8 << 16) | MUX_PC24A_EIC_EXTINT8) -#define PORT_PC24A_EIC_EXTINT8 ((1UL) << 24) -#define PIN_PC24A_EIC_EXTINT_NUM _L_(8) /**< EIC signal: PIN_PC24 External Interrupt Line */ - -#define PIN_PA09A_EIC_EXTINT9 (9L) -#define MUX_PA09A_EIC_EXTINT9 (0L) -#define PINMUX_PA09A_EIC_EXTINT9 ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9) -#define PORT_PA09A_EIC_EXTINT9 ((1UL) << 9) -#define PIN_PA09A_EIC_EXTINT_NUM _L_(9) /**< EIC signal: PIN_PA09 External Interrupt Line */ - -#define PIN_PA25A_EIC_EXTINT9 (25L) -#define MUX_PA25A_EIC_EXTINT9 (0L) -#define PINMUX_PA25A_EIC_EXTINT9 ((PIN_PA25A_EIC_EXTINT9 << 16) | MUX_PA25A_EIC_EXTINT9) -#define PORT_PA25A_EIC_EXTINT9 ((1UL) << 25) -#define PIN_PA25A_EIC_EXTINT_NUM _L_(9) /**< EIC signal: PIN_PA25 External Interrupt Line */ - -#define PIN_PB09A_EIC_EXTINT9 (41L) -#define MUX_PB09A_EIC_EXTINT9 (0L) -#define PINMUX_PB09A_EIC_EXTINT9 ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9) -#define PORT_PB09A_EIC_EXTINT9 ((1UL) << 9) -#define PIN_PB09A_EIC_EXTINT_NUM _L_(9) /**< EIC signal: PIN_PB09 External Interrupt Line */ - -#define PIN_PB25A_EIC_EXTINT9 (57L) -#define MUX_PB25A_EIC_EXTINT9 (0L) -#define PINMUX_PB25A_EIC_EXTINT9 ((PIN_PB25A_EIC_EXTINT9 << 16) | MUX_PB25A_EIC_EXTINT9) -#define PORT_PB25A_EIC_EXTINT9 ((1UL) << 25) -#define PIN_PB25A_EIC_EXTINT_NUM _L_(9) /**< EIC signal: PIN_PB25 External Interrupt Line */ - -#define PIN_PC07A_EIC_EXTINT9 (71L) -#define MUX_PC07A_EIC_EXTINT9 (0L) -#define PINMUX_PC07A_EIC_EXTINT9 ((PIN_PC07A_EIC_EXTINT9 << 16) | MUX_PC07A_EIC_EXTINT9) -#define PORT_PC07A_EIC_EXTINT9 ((1UL) << 7) -#define PIN_PC07A_EIC_EXTINT_NUM _L_(9) /**< EIC signal: PIN_PC07 External Interrupt Line */ - -#define PIN_PC25A_EIC_EXTINT9 (89L) -#define MUX_PC25A_EIC_EXTINT9 (0L) -#define PINMUX_PC25A_EIC_EXTINT9 ((PIN_PC25A_EIC_EXTINT9 << 16) | MUX_PC25A_EIC_EXTINT9) -#define PORT_PC25A_EIC_EXTINT9 ((1UL) << 25) -#define PIN_PC25A_EIC_EXTINT_NUM _L_(9) /**< EIC signal: PIN_PC25 External Interrupt Line */ - -#define PIN_PA10A_EIC_EXTINT10 (10L) -#define MUX_PA10A_EIC_EXTINT10 (0L) -#define PINMUX_PA10A_EIC_EXTINT10 ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10) -#define PORT_PA10A_EIC_EXTINT10 ((1UL) << 10) -#define PIN_PA10A_EIC_EXTINT_NUM _L_(10) /**< EIC signal: PIN_PA10 External Interrupt Line */ - -#define PIN_PB10A_EIC_EXTINT10 (42L) -#define MUX_PB10A_EIC_EXTINT10 (0L) -#define PINMUX_PB10A_EIC_EXTINT10 ((PIN_PB10A_EIC_EXTINT10 << 16) | MUX_PB10A_EIC_EXTINT10) -#define PORT_PB10A_EIC_EXTINT10 ((1UL) << 10) -#define PIN_PB10A_EIC_EXTINT_NUM _L_(10) /**< EIC signal: PIN_PB10 External Interrupt Line */ - -#define PIN_PC10A_EIC_EXTINT10 (74L) -#define MUX_PC10A_EIC_EXTINT10 (0L) -#define PINMUX_PC10A_EIC_EXTINT10 ((PIN_PC10A_EIC_EXTINT10 << 16) | MUX_PC10A_EIC_EXTINT10) -#define PORT_PC10A_EIC_EXTINT10 ((1UL) << 10) -#define PIN_PC10A_EIC_EXTINT_NUM _L_(10) /**< EIC signal: PIN_PC10 External Interrupt Line */ - -#define PIN_PC26A_EIC_EXTINT10 (90L) -#define MUX_PC26A_EIC_EXTINT10 (0L) -#define PINMUX_PC26A_EIC_EXTINT10 ((PIN_PC26A_EIC_EXTINT10 << 16) | MUX_PC26A_EIC_EXTINT10) -#define PORT_PC26A_EIC_EXTINT10 ((1UL) << 26) -#define PIN_PC26A_EIC_EXTINT_NUM _L_(10) /**< EIC signal: PIN_PC26 External Interrupt Line */ - -#define PIN_PA11A_EIC_EXTINT11 (11L) -#define MUX_PA11A_EIC_EXTINT11 (0L) -#define PINMUX_PA11A_EIC_EXTINT11 ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11) -#define PORT_PA11A_EIC_EXTINT11 ((1UL) << 11) -#define PIN_PA11A_EIC_EXTINT_NUM _L_(11) /**< EIC signal: PIN_PA11 External Interrupt Line */ - -#define PIN_PA27A_EIC_EXTINT11 (27L) -#define MUX_PA27A_EIC_EXTINT11 (0L) -#define PINMUX_PA27A_EIC_EXTINT11 ((PIN_PA27A_EIC_EXTINT11 << 16) | MUX_PA27A_EIC_EXTINT11) -#define PORT_PA27A_EIC_EXTINT11 ((1UL) << 27) -#define PIN_PA27A_EIC_EXTINT_NUM _L_(11) /**< EIC signal: PIN_PA27 External Interrupt Line */ - -#define PIN_PB11A_EIC_EXTINT11 (43L) -#define MUX_PB11A_EIC_EXTINT11 (0L) -#define PINMUX_PB11A_EIC_EXTINT11 ((PIN_PB11A_EIC_EXTINT11 << 16) | MUX_PB11A_EIC_EXTINT11) -#define PORT_PB11A_EIC_EXTINT11 ((1UL) << 11) -#define PIN_PB11A_EIC_EXTINT_NUM _L_(11) /**< EIC signal: PIN_PB11 External Interrupt Line */ - -#define PIN_PC11A_EIC_EXTINT11 (75L) -#define MUX_PC11A_EIC_EXTINT11 (0L) -#define PINMUX_PC11A_EIC_EXTINT11 ((PIN_PC11A_EIC_EXTINT11 << 16) | MUX_PC11A_EIC_EXTINT11) -#define PORT_PC11A_EIC_EXTINT11 ((1UL) << 11) -#define PIN_PC11A_EIC_EXTINT_NUM _L_(11) /**< EIC signal: PIN_PC11 External Interrupt Line */ - -#define PIN_PC27A_EIC_EXTINT11 (91L) -#define MUX_PC27A_EIC_EXTINT11 (0L) -#define PINMUX_PC27A_EIC_EXTINT11 ((PIN_PC27A_EIC_EXTINT11 << 16) | MUX_PC27A_EIC_EXTINT11) -#define PORT_PC27A_EIC_EXTINT11 ((1UL) << 27) -#define PIN_PC27A_EIC_EXTINT_NUM _L_(11) /**< EIC signal: PIN_PC27 External Interrupt Line */ - -#define PIN_PA12A_EIC_EXTINT12 (12L) -#define MUX_PA12A_EIC_EXTINT12 (0L) -#define PINMUX_PA12A_EIC_EXTINT12 ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12) -#define PORT_PA12A_EIC_EXTINT12 ((1UL) << 12) -#define PIN_PA12A_EIC_EXTINT_NUM _L_(12) /**< EIC signal: PIN_PA12 External Interrupt Line */ - -#define PIN_PB12A_EIC_EXTINT12 (44L) -#define MUX_PB12A_EIC_EXTINT12 (0L) -#define PINMUX_PB12A_EIC_EXTINT12 ((PIN_PB12A_EIC_EXTINT12 << 16) | MUX_PB12A_EIC_EXTINT12) -#define PORT_PB12A_EIC_EXTINT12 ((1UL) << 12) -#define PIN_PB12A_EIC_EXTINT_NUM _L_(12) /**< EIC signal: PIN_PB12 External Interrupt Line */ - -#define PIN_PC12A_EIC_EXTINT12 (76L) -#define MUX_PC12A_EIC_EXTINT12 (0L) -#define PINMUX_PC12A_EIC_EXTINT12 ((PIN_PC12A_EIC_EXTINT12 << 16) | MUX_PC12A_EIC_EXTINT12) -#define PORT_PC12A_EIC_EXTINT12 ((1UL) << 12) -#define PIN_PC12A_EIC_EXTINT_NUM _L_(12) /**< EIC signal: PIN_PC12 External Interrupt Line */ - -#define PIN_PC28A_EIC_EXTINT12 (92L) -#define MUX_PC28A_EIC_EXTINT12 (0L) -#define PINMUX_PC28A_EIC_EXTINT12 ((PIN_PC28A_EIC_EXTINT12 << 16) | MUX_PC28A_EIC_EXTINT12) -#define PORT_PC28A_EIC_EXTINT12 ((1UL) << 28) -#define PIN_PC28A_EIC_EXTINT_NUM _L_(12) /**< EIC signal: PIN_PC28 External Interrupt Line */ - -#define PIN_PA13A_EIC_EXTINT13 (13L) -#define MUX_PA13A_EIC_EXTINT13 (0L) -#define PINMUX_PA13A_EIC_EXTINT13 ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13) -#define PORT_PA13A_EIC_EXTINT13 ((1UL) << 13) -#define PIN_PA13A_EIC_EXTINT_NUM _L_(13) /**< EIC signal: PIN_PA13 External Interrupt Line */ - -#define PIN_PB13A_EIC_EXTINT13 (45L) -#define MUX_PB13A_EIC_EXTINT13 (0L) -#define PINMUX_PB13A_EIC_EXTINT13 ((PIN_PB13A_EIC_EXTINT13 << 16) | MUX_PB13A_EIC_EXTINT13) -#define PORT_PB13A_EIC_EXTINT13 ((1UL) << 13) -#define PIN_PB13A_EIC_EXTINT_NUM _L_(13) /**< EIC signal: PIN_PB13 External Interrupt Line */ - -#define PIN_PC13A_EIC_EXTINT13 (77L) -#define MUX_PC13A_EIC_EXTINT13 (0L) -#define PINMUX_PC13A_EIC_EXTINT13 ((PIN_PC13A_EIC_EXTINT13 << 16) | MUX_PC13A_EIC_EXTINT13) -#define PORT_PC13A_EIC_EXTINT13 ((1UL) << 13) -#define PIN_PC13A_EIC_EXTINT_NUM _L_(13) /**< EIC signal: PIN_PC13 External Interrupt Line */ - -#define PIN_PA30A_EIC_EXTINT14 (30L) -#define MUX_PA30A_EIC_EXTINT14 (0L) -#define PINMUX_PA30A_EIC_EXTINT14 ((PIN_PA30A_EIC_EXTINT14 << 16) | MUX_PA30A_EIC_EXTINT14) -#define PORT_PA30A_EIC_EXTINT14 ((1UL) << 30) -#define PIN_PA30A_EIC_EXTINT_NUM _L_(14) /**< EIC signal: PIN_PA30 External Interrupt Line */ - -#define PIN_PB14A_EIC_EXTINT14 (46L) -#define MUX_PB14A_EIC_EXTINT14 (0L) -#define PINMUX_PB14A_EIC_EXTINT14 ((PIN_PB14A_EIC_EXTINT14 << 16) | MUX_PB14A_EIC_EXTINT14) -#define PORT_PB14A_EIC_EXTINT14 ((1UL) << 14) -#define PIN_PB14A_EIC_EXTINT_NUM _L_(14) /**< EIC signal: PIN_PB14 External Interrupt Line */ - -#define PIN_PB30A_EIC_EXTINT14 (62L) -#define MUX_PB30A_EIC_EXTINT14 (0L) -#define PINMUX_PB30A_EIC_EXTINT14 ((PIN_PB30A_EIC_EXTINT14 << 16) | MUX_PB30A_EIC_EXTINT14) -#define PORT_PB30A_EIC_EXTINT14 ((1UL) << 30) -#define PIN_PB30A_EIC_EXTINT_NUM _L_(14) /**< EIC signal: PIN_PB30 External Interrupt Line */ - -#define PIN_PC14A_EIC_EXTINT14 (78L) -#define MUX_PC14A_EIC_EXTINT14 (0L) -#define PINMUX_PC14A_EIC_EXTINT14 ((PIN_PC14A_EIC_EXTINT14 << 16) | MUX_PC14A_EIC_EXTINT14) -#define PORT_PC14A_EIC_EXTINT14 ((1UL) << 14) -#define PIN_PC14A_EIC_EXTINT_NUM _L_(14) /**< EIC signal: PIN_PC14 External Interrupt Line */ - -#define PIN_PA14A_EIC_EXTINT14 (14L) -#define MUX_PA14A_EIC_EXTINT14 (0L) -#define PINMUX_PA14A_EIC_EXTINT14 ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14) -#define PORT_PA14A_EIC_EXTINT14 ((1UL) << 14) -#define PIN_PA14A_EIC_EXTINT_NUM _L_(14) /**< EIC signal: PIN_PA14 External Interrupt Line */ - -#define PIN_PA15A_EIC_EXTINT15 (15L) -#define MUX_PA15A_EIC_EXTINT15 (0L) -#define PINMUX_PA15A_EIC_EXTINT15 ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15) -#define PORT_PA15A_EIC_EXTINT15 ((1UL) << 15) -#define PIN_PA15A_EIC_EXTINT_NUM _L_(15) /**< EIC signal: PIN_PA15 External Interrupt Line */ - -#define PIN_PA31A_EIC_EXTINT15 (31L) -#define MUX_PA31A_EIC_EXTINT15 (0L) -#define PINMUX_PA31A_EIC_EXTINT15 ((PIN_PA31A_EIC_EXTINT15 << 16) | MUX_PA31A_EIC_EXTINT15) -#define PORT_PA31A_EIC_EXTINT15 ((1UL) << 31) -#define PIN_PA31A_EIC_EXTINT_NUM _L_(15) /**< EIC signal: PIN_PA31 External Interrupt Line */ - -#define PIN_PB15A_EIC_EXTINT15 (47L) -#define MUX_PB15A_EIC_EXTINT15 (0L) -#define PINMUX_PB15A_EIC_EXTINT15 ((PIN_PB15A_EIC_EXTINT15 << 16) | MUX_PB15A_EIC_EXTINT15) -#define PORT_PB15A_EIC_EXTINT15 ((1UL) << 15) -#define PIN_PB15A_EIC_EXTINT_NUM _L_(15) /**< EIC signal: PIN_PB15 External Interrupt Line */ - -#define PIN_PB31A_EIC_EXTINT15 (63L) -#define MUX_PB31A_EIC_EXTINT15 (0L) -#define PINMUX_PB31A_EIC_EXTINT15 ((PIN_PB31A_EIC_EXTINT15 << 16) | MUX_PB31A_EIC_EXTINT15) -#define PORT_PB31A_EIC_EXTINT15 ((1UL) << 31) -#define PIN_PB31A_EIC_EXTINT_NUM _L_(15) /**< EIC signal: PIN_PB31 External Interrupt Line */ - -#define PIN_PC15A_EIC_EXTINT15 (79L) -#define MUX_PC15A_EIC_EXTINT15 (0L) -#define PINMUX_PC15A_EIC_EXTINT15 ((PIN_PC15A_EIC_EXTINT15 << 16) | MUX_PC15A_EIC_EXTINT15) -#define PORT_PC15A_EIC_EXTINT15 ((1UL) << 15) -#define PIN_PC15A_EIC_EXTINT_NUM _L_(15) /**< EIC signal: PIN_PC15 External Interrupt Line */ - -#define PIN_PA08A_EIC_NMI (8L) -#define MUX_PA08A_EIC_NMI (0L) -#define PINMUX_PA08A_EIC_NMI ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI) -#define PORT_PA08A_EIC_NMI ((1UL) << 8) - -/* ========== PORT definition for GCLK peripheral ========== */ -#define PIN_PA30M_GCLK_IO0 (30L) -#define MUX_PA30M_GCLK_IO0 (12L) -#define PINMUX_PA30M_GCLK_IO0 ((PIN_PA30M_GCLK_IO0 << 16) | MUX_PA30M_GCLK_IO0) -#define PORT_PA30M_GCLK_IO0 ((1UL) << 30) - -#define PIN_PB14M_GCLK_IO0 (46L) -#define MUX_PB14M_GCLK_IO0 (12L) -#define PINMUX_PB14M_GCLK_IO0 ((PIN_PB14M_GCLK_IO0 << 16) | MUX_PB14M_GCLK_IO0) -#define PORT_PB14M_GCLK_IO0 ((1UL) << 14) - -#define PIN_PA14M_GCLK_IO0 (14L) -#define MUX_PA14M_GCLK_IO0 (12L) -#define PINMUX_PA14M_GCLK_IO0 ((PIN_PA14M_GCLK_IO0 << 16) | MUX_PA14M_GCLK_IO0) -#define PORT_PA14M_GCLK_IO0 ((1UL) << 14) - -#define PIN_PB22M_GCLK_IO0 (54L) -#define MUX_PB22M_GCLK_IO0 (12L) -#define PINMUX_PB22M_GCLK_IO0 ((PIN_PB22M_GCLK_IO0 << 16) | MUX_PB22M_GCLK_IO0) -#define PORT_PB22M_GCLK_IO0 ((1UL) << 22) - -#define PIN_PB15M_GCLK_IO1 (47L) -#define MUX_PB15M_GCLK_IO1 (12L) -#define PINMUX_PB15M_GCLK_IO1 ((PIN_PB15M_GCLK_IO1 << 16) | MUX_PB15M_GCLK_IO1) -#define PORT_PB15M_GCLK_IO1 ((1UL) << 15) - -#define PIN_PA15M_GCLK_IO1 (15L) -#define MUX_PA15M_GCLK_IO1 (12L) -#define PINMUX_PA15M_GCLK_IO1 ((PIN_PA15M_GCLK_IO1 << 16) | MUX_PA15M_GCLK_IO1) -#define PORT_PA15M_GCLK_IO1 ((1UL) << 15) - -#define PIN_PB23M_GCLK_IO1 (55L) -#define MUX_PB23M_GCLK_IO1 (12L) -#define PINMUX_PB23M_GCLK_IO1 ((PIN_PB23M_GCLK_IO1 << 16) | MUX_PB23M_GCLK_IO1) -#define PORT_PB23M_GCLK_IO1 ((1UL) << 23) - -#define PIN_PA27M_GCLK_IO1 (27L) -#define MUX_PA27M_GCLK_IO1 (12L) -#define PINMUX_PA27M_GCLK_IO1 ((PIN_PA27M_GCLK_IO1 << 16) | MUX_PA27M_GCLK_IO1) -#define PORT_PA27M_GCLK_IO1 ((1UL) << 27) - -#define PIN_PA16M_GCLK_IO2 (16L) -#define MUX_PA16M_GCLK_IO2 (12L) -#define PINMUX_PA16M_GCLK_IO2 ((PIN_PA16M_GCLK_IO2 << 16) | MUX_PA16M_GCLK_IO2) -#define PORT_PA16M_GCLK_IO2 ((1UL) << 16) - -#define PIN_PB16M_GCLK_IO2 (48L) -#define MUX_PB16M_GCLK_IO2 (12L) -#define PINMUX_PB16M_GCLK_IO2 ((PIN_PB16M_GCLK_IO2 << 16) | MUX_PB16M_GCLK_IO2) -#define PORT_PB16M_GCLK_IO2 ((1UL) << 16) - -#define PIN_PA17M_GCLK_IO3 (17L) -#define MUX_PA17M_GCLK_IO3 (12L) -#define PINMUX_PA17M_GCLK_IO3 ((PIN_PA17M_GCLK_IO3 << 16) | MUX_PA17M_GCLK_IO3) -#define PORT_PA17M_GCLK_IO3 ((1UL) << 17) - -#define PIN_PB17M_GCLK_IO3 (49L) -#define MUX_PB17M_GCLK_IO3 (12L) -#define PINMUX_PB17M_GCLK_IO3 ((PIN_PB17M_GCLK_IO3 << 16) | MUX_PB17M_GCLK_IO3) -#define PORT_PB17M_GCLK_IO3 ((1UL) << 17) - -#define PIN_PA10M_GCLK_IO4 (10L) -#define MUX_PA10M_GCLK_IO4 (12L) -#define PINMUX_PA10M_GCLK_IO4 ((PIN_PA10M_GCLK_IO4 << 16) | MUX_PA10M_GCLK_IO4) -#define PORT_PA10M_GCLK_IO4 ((1UL) << 10) - -#define PIN_PB10M_GCLK_IO4 (42L) -#define MUX_PB10M_GCLK_IO4 (12L) -#define PINMUX_PB10M_GCLK_IO4 ((PIN_PB10M_GCLK_IO4 << 16) | MUX_PB10M_GCLK_IO4) -#define PORT_PB10M_GCLK_IO4 ((1UL) << 10) - -#define PIN_PB18M_GCLK_IO4 (50L) -#define MUX_PB18M_GCLK_IO4 (12L) -#define PINMUX_PB18M_GCLK_IO4 ((PIN_PB18M_GCLK_IO4 << 16) | MUX_PB18M_GCLK_IO4) -#define PORT_PB18M_GCLK_IO4 ((1UL) << 18) - -#define PIN_PA11M_GCLK_IO5 (11L) -#define MUX_PA11M_GCLK_IO5 (12L) -#define PINMUX_PA11M_GCLK_IO5 ((PIN_PA11M_GCLK_IO5 << 16) | MUX_PA11M_GCLK_IO5) -#define PORT_PA11M_GCLK_IO5 ((1UL) << 11) - -#define PIN_PB11M_GCLK_IO5 (43L) -#define MUX_PB11M_GCLK_IO5 (12L) -#define PINMUX_PB11M_GCLK_IO5 ((PIN_PB11M_GCLK_IO5 << 16) | MUX_PB11M_GCLK_IO5) -#define PORT_PB11M_GCLK_IO5 ((1UL) << 11) - -#define PIN_PB19M_GCLK_IO5 (51L) -#define MUX_PB19M_GCLK_IO5 (12L) -#define PINMUX_PB19M_GCLK_IO5 ((PIN_PB19M_GCLK_IO5 << 16) | MUX_PB19M_GCLK_IO5) -#define PORT_PB19M_GCLK_IO5 ((1UL) << 19) - -#define PIN_PB12M_GCLK_IO6 (44L) -#define MUX_PB12M_GCLK_IO6 (12L) -#define PINMUX_PB12M_GCLK_IO6 ((PIN_PB12M_GCLK_IO6 << 16) | MUX_PB12M_GCLK_IO6) -#define PORT_PB12M_GCLK_IO6 ((1UL) << 12) - -#define PIN_PB20M_GCLK_IO6 (52L) -#define MUX_PB20M_GCLK_IO6 (12L) -#define PINMUX_PB20M_GCLK_IO6 ((PIN_PB20M_GCLK_IO6 << 16) | MUX_PB20M_GCLK_IO6) -#define PORT_PB20M_GCLK_IO6 ((1UL) << 20) - -#define PIN_PB13M_GCLK_IO7 (45L) -#define MUX_PB13M_GCLK_IO7 (12L) -#define PINMUX_PB13M_GCLK_IO7 ((PIN_PB13M_GCLK_IO7 << 16) | MUX_PB13M_GCLK_IO7) -#define PORT_PB13M_GCLK_IO7 ((1UL) << 13) - -#define PIN_PB21M_GCLK_IO7 (53L) -#define MUX_PB21M_GCLK_IO7 (12L) -#define PINMUX_PB21M_GCLK_IO7 ((PIN_PB21M_GCLK_IO7 << 16) | MUX_PB21M_GCLK_IO7) -#define PORT_PB21M_GCLK_IO7 ((1UL) << 21) - -/* ========== PORT definition for GMAC peripheral ========== */ -#define PIN_PC21L_GMAC_GCOL (85L) -#define MUX_PC21L_GMAC_GCOL (11L) -#define PINMUX_PC21L_GMAC_GCOL ((PIN_PC21L_GMAC_GCOL << 16) | MUX_PC21L_GMAC_GCOL) -#define PORT_PC21L_GMAC_GCOL ((1UL) << 21) - -#define PIN_PA16L_GMAC_GCRS (16L) -#define MUX_PA16L_GMAC_GCRS (11L) -#define PINMUX_PA16L_GMAC_GCRS ((PIN_PA16L_GMAC_GCRS << 16) | MUX_PA16L_GMAC_GCRS) -#define PORT_PA16L_GMAC_GCRS ((1UL) << 16) - -#define PIN_PA20L_GMAC_GMDC (20L) -#define MUX_PA20L_GMAC_GMDC (11L) -#define PINMUX_PA20L_GMAC_GMDC ((PIN_PA20L_GMAC_GMDC << 16) | MUX_PA20L_GMAC_GMDC) -#define PORT_PA20L_GMAC_GMDC ((1UL) << 20) - -#define PIN_PB14L_GMAC_GMDC (46L) -#define MUX_PB14L_GMAC_GMDC (11L) -#define PINMUX_PB14L_GMAC_GMDC ((PIN_PB14L_GMAC_GMDC << 16) | MUX_PB14L_GMAC_GMDC) -#define PORT_PB14L_GMAC_GMDC ((1UL) << 14) - -#define PIN_PC11L_GMAC_GMDC (75L) -#define MUX_PC11L_GMAC_GMDC (11L) -#define PINMUX_PC11L_GMAC_GMDC ((PIN_PC11L_GMAC_GMDC << 16) | MUX_PC11L_GMAC_GMDC) -#define PORT_PC11L_GMAC_GMDC ((1UL) << 11) - -#define PIN_PA21L_GMAC_GMDIO (21L) -#define MUX_PA21L_GMAC_GMDIO (11L) -#define PINMUX_PA21L_GMAC_GMDIO ((PIN_PA21L_GMAC_GMDIO << 16) | MUX_PA21L_GMAC_GMDIO) -#define PORT_PA21L_GMAC_GMDIO ((1UL) << 21) - -#define PIN_PB15L_GMAC_GMDIO (47L) -#define MUX_PB15L_GMAC_GMDIO (11L) -#define PINMUX_PB15L_GMAC_GMDIO ((PIN_PB15L_GMAC_GMDIO << 16) | MUX_PB15L_GMAC_GMDIO) -#define PORT_PB15L_GMAC_GMDIO ((1UL) << 15) - -#define PIN_PC12L_GMAC_GMDIO (76L) -#define MUX_PC12L_GMAC_GMDIO (11L) -#define PINMUX_PC12L_GMAC_GMDIO ((PIN_PC12L_GMAC_GMDIO << 16) | MUX_PC12L_GMAC_GMDIO) -#define PORT_PC12L_GMAC_GMDIO ((1UL) << 12) - -#define PIN_PA13L_GMAC_GRX0 (13L) -#define MUX_PA13L_GMAC_GRX0 (11L) -#define PINMUX_PA13L_GMAC_GRX0 ((PIN_PA13L_GMAC_GRX0 << 16) | MUX_PA13L_GMAC_GRX0) -#define PORT_PA13L_GMAC_GRX0 ((1UL) << 13) - -#define PIN_PA12L_GMAC_GRX1 (12L) -#define MUX_PA12L_GMAC_GRX1 (11L) -#define PINMUX_PA12L_GMAC_GRX1 ((PIN_PA12L_GMAC_GRX1 << 16) | MUX_PA12L_GMAC_GRX1) -#define PORT_PA12L_GMAC_GRX1 ((1UL) << 12) - -#define PIN_PC15L_GMAC_GRX2 (79L) -#define MUX_PC15L_GMAC_GRX2 (11L) -#define PINMUX_PC15L_GMAC_GRX2 ((PIN_PC15L_GMAC_GRX2 << 16) | MUX_PC15L_GMAC_GRX2) -#define PORT_PC15L_GMAC_GRX2 ((1UL) << 15) - -#define PIN_PC14L_GMAC_GRX3 (78L) -#define MUX_PC14L_GMAC_GRX3 (11L) -#define PINMUX_PC14L_GMAC_GRX3 ((PIN_PC14L_GMAC_GRX3 << 16) | MUX_PC14L_GMAC_GRX3) -#define PORT_PC14L_GMAC_GRX3 ((1UL) << 14) - -#define PIN_PC18L_GMAC_GRXCK (82L) -#define MUX_PC18L_GMAC_GRXCK (11L) -#define PINMUX_PC18L_GMAC_GRXCK ((PIN_PC18L_GMAC_GRXCK << 16) | MUX_PC18L_GMAC_GRXCK) -#define PORT_PC18L_GMAC_GRXCK ((1UL) << 18) - -#define PIN_PC20L_GMAC_GRXDV (84L) -#define MUX_PC20L_GMAC_GRXDV (11L) -#define PINMUX_PC20L_GMAC_GRXDV ((PIN_PC20L_GMAC_GRXDV << 16) | MUX_PC20L_GMAC_GRXDV) -#define PORT_PC20L_GMAC_GRXDV ((1UL) << 20) - -#define PIN_PA15L_GMAC_GRXER (15L) -#define MUX_PA15L_GMAC_GRXER (11L) -#define PINMUX_PA15L_GMAC_GRXER ((PIN_PA15L_GMAC_GRXER << 16) | MUX_PA15L_GMAC_GRXER) -#define PORT_PA15L_GMAC_GRXER ((1UL) << 15) - -#define PIN_PA18L_GMAC_GTX0 (18L) -#define MUX_PA18L_GMAC_GTX0 (11L) -#define PINMUX_PA18L_GMAC_GTX0 ((PIN_PA18L_GMAC_GTX0 << 16) | MUX_PA18L_GMAC_GTX0) -#define PORT_PA18L_GMAC_GTX0 ((1UL) << 18) - -#define PIN_PA19L_GMAC_GTX1 (19L) -#define MUX_PA19L_GMAC_GTX1 (11L) -#define PINMUX_PA19L_GMAC_GTX1 ((PIN_PA19L_GMAC_GTX1 << 16) | MUX_PA19L_GMAC_GTX1) -#define PORT_PA19L_GMAC_GTX1 ((1UL) << 19) - -#define PIN_PC16L_GMAC_GTX2 (80L) -#define MUX_PC16L_GMAC_GTX2 (11L) -#define PINMUX_PC16L_GMAC_GTX2 ((PIN_PC16L_GMAC_GTX2 << 16) | MUX_PC16L_GMAC_GTX2) -#define PORT_PC16L_GMAC_GTX2 ((1UL) << 16) - -#define PIN_PC17L_GMAC_GTX3 (81L) -#define MUX_PC17L_GMAC_GTX3 (11L) -#define PINMUX_PC17L_GMAC_GTX3 ((PIN_PC17L_GMAC_GTX3 << 16) | MUX_PC17L_GMAC_GTX3) -#define PORT_PC17L_GMAC_GTX3 ((1UL) << 17) - -#define PIN_PA14L_GMAC_GTXCK (14L) -#define MUX_PA14L_GMAC_GTXCK (11L) -#define PINMUX_PA14L_GMAC_GTXCK ((PIN_PA14L_GMAC_GTXCK << 16) | MUX_PA14L_GMAC_GTXCK) -#define PORT_PA14L_GMAC_GTXCK ((1UL) << 14) - -#define PIN_PA17L_GMAC_GTXEN (17L) -#define MUX_PA17L_GMAC_GTXEN (11L) -#define PINMUX_PA17L_GMAC_GTXEN ((PIN_PA17L_GMAC_GTXEN << 16) | MUX_PA17L_GMAC_GTXEN) -#define PORT_PA17L_GMAC_GTXEN ((1UL) << 17) - -#define PIN_PC19L_GMAC_GTXER (83L) -#define MUX_PC19L_GMAC_GTXER (11L) -#define PINMUX_PC19L_GMAC_GTXER ((PIN_PC19L_GMAC_GTXER << 16) | MUX_PC19L_GMAC_GTXER) -#define PORT_PC19L_GMAC_GTXER ((1UL) << 19) - -/* ========== PORT definition for I2S peripheral ========== */ -#define PIN_PA09J_I2S_FS0 (9L) -#define MUX_PA09J_I2S_FS0 (9L) -#define PINMUX_PA09J_I2S_FS0 ((PIN_PA09J_I2S_FS0 << 16) | MUX_PA09J_I2S_FS0) -#define PORT_PA09J_I2S_FS0 ((1UL) << 9) - -#define PIN_PA20J_I2S_FS0 (20L) -#define MUX_PA20J_I2S_FS0 (9L) -#define PINMUX_PA20J_I2S_FS0 ((PIN_PA20J_I2S_FS0 << 16) | MUX_PA20J_I2S_FS0) -#define PORT_PA20J_I2S_FS0 ((1UL) << 20) - -#define PIN_PA23J_I2S_FS1 (23L) -#define MUX_PA23J_I2S_FS1 (9L) -#define PINMUX_PA23J_I2S_FS1 ((PIN_PA23J_I2S_FS1 << 16) | MUX_PA23J_I2S_FS1) -#define PORT_PA23J_I2S_FS1 ((1UL) << 23) - -#define PIN_PB11J_I2S_FS1 (43L) -#define MUX_PB11J_I2S_FS1 (9L) -#define PINMUX_PB11J_I2S_FS1 ((PIN_PB11J_I2S_FS1 << 16) | MUX_PB11J_I2S_FS1) -#define PORT_PB11J_I2S_FS1 ((1UL) << 11) - -#define PIN_PA08J_I2S_MCK0 (8L) -#define MUX_PA08J_I2S_MCK0 (9L) -#define PINMUX_PA08J_I2S_MCK0 ((PIN_PA08J_I2S_MCK0 << 16) | MUX_PA08J_I2S_MCK0) -#define PORT_PA08J_I2S_MCK0 ((1UL) << 8) - -#define PIN_PB17J_I2S_MCK0 (49L) -#define MUX_PB17J_I2S_MCK0 (9L) -#define PINMUX_PB17J_I2S_MCK0 ((PIN_PB17J_I2S_MCK0 << 16) | MUX_PB17J_I2S_MCK0) -#define PORT_PB17J_I2S_MCK0 ((1UL) << 17) - -#define PIN_PB13J_I2S_MCK1 (45L) -#define MUX_PB13J_I2S_MCK1 (9L) -#define PINMUX_PB13J_I2S_MCK1 ((PIN_PB13J_I2S_MCK1 << 16) | MUX_PB13J_I2S_MCK1) -#define PORT_PB13J_I2S_MCK1 ((1UL) << 13) - -#define PIN_PA10J_I2S_SCK0 (10L) -#define MUX_PA10J_I2S_SCK0 (9L) -#define PINMUX_PA10J_I2S_SCK0 ((PIN_PA10J_I2S_SCK0 << 16) | MUX_PA10J_I2S_SCK0) -#define PORT_PA10J_I2S_SCK0 ((1UL) << 10) - -#define PIN_PB16J_I2S_SCK0 (48L) -#define MUX_PB16J_I2S_SCK0 (9L) -#define PINMUX_PB16J_I2S_SCK0 ((PIN_PB16J_I2S_SCK0 << 16) | MUX_PB16J_I2S_SCK0) -#define PORT_PB16J_I2S_SCK0 ((1UL) << 16) - -#define PIN_PB12J_I2S_SCK1 (44L) -#define MUX_PB12J_I2S_SCK1 (9L) -#define PINMUX_PB12J_I2S_SCK1 ((PIN_PB12J_I2S_SCK1 << 16) | MUX_PB12J_I2S_SCK1) -#define PORT_PB12J_I2S_SCK1 ((1UL) << 12) - -#define PIN_PA22J_I2S_SDI (22L) -#define MUX_PA22J_I2S_SDI (9L) -#define PINMUX_PA22J_I2S_SDI ((PIN_PA22J_I2S_SDI << 16) | MUX_PA22J_I2S_SDI) -#define PORT_PA22J_I2S_SDI ((1UL) << 22) - -#define PIN_PB10J_I2S_SDI (42L) -#define MUX_PB10J_I2S_SDI (9L) -#define PINMUX_PB10J_I2S_SDI ((PIN_PB10J_I2S_SDI << 16) | MUX_PB10J_I2S_SDI) -#define PORT_PB10J_I2S_SDI ((1UL) << 10) - -#define PIN_PA11J_I2S_SDO (11L) -#define MUX_PA11J_I2S_SDO (9L) -#define PINMUX_PA11J_I2S_SDO ((PIN_PA11J_I2S_SDO << 16) | MUX_PA11J_I2S_SDO) -#define PORT_PA11J_I2S_SDO ((1UL) << 11) - -#define PIN_PA21J_I2S_SDO (21L) -#define MUX_PA21J_I2S_SDO (9L) -#define PINMUX_PA21J_I2S_SDO ((PIN_PA21J_I2S_SDO << 16) | MUX_PA21J_I2S_SDO) -#define PORT_PA21J_I2S_SDO ((1UL) << 21) - -/* ========== PORT definition for PCC peripheral ========== */ -#define PIN_PA14K_PCC_CLK (14L) -#define MUX_PA14K_PCC_CLK (10L) -#define PINMUX_PA14K_PCC_CLK ((PIN_PA14K_PCC_CLK << 16) | MUX_PA14K_PCC_CLK) -#define PORT_PA14K_PCC_CLK ((1UL) << 14) - -#define PIN_PA16K_PCC_DATA0 (16L) -#define MUX_PA16K_PCC_DATA0 (10L) -#define PINMUX_PA16K_PCC_DATA0 ((PIN_PA16K_PCC_DATA0 << 16) | MUX_PA16K_PCC_DATA0) -#define PORT_PA16K_PCC_DATA0 ((1UL) << 16) - -#define PIN_PA17K_PCC_DATA1 (17L) -#define MUX_PA17K_PCC_DATA1 (10L) -#define PINMUX_PA17K_PCC_DATA1 ((PIN_PA17K_PCC_DATA1 << 16) | MUX_PA17K_PCC_DATA1) -#define PORT_PA17K_PCC_DATA1 ((1UL) << 17) - -#define PIN_PA18K_PCC_DATA2 (18L) -#define MUX_PA18K_PCC_DATA2 (10L) -#define PINMUX_PA18K_PCC_DATA2 ((PIN_PA18K_PCC_DATA2 << 16) | MUX_PA18K_PCC_DATA2) -#define PORT_PA18K_PCC_DATA2 ((1UL) << 18) - -#define PIN_PA19K_PCC_DATA3 (19L) -#define MUX_PA19K_PCC_DATA3 (10L) -#define PINMUX_PA19K_PCC_DATA3 ((PIN_PA19K_PCC_DATA3 << 16) | MUX_PA19K_PCC_DATA3) -#define PORT_PA19K_PCC_DATA3 ((1UL) << 19) - -#define PIN_PA20K_PCC_DATA4 (20L) -#define MUX_PA20K_PCC_DATA4 (10L) -#define PINMUX_PA20K_PCC_DATA4 ((PIN_PA20K_PCC_DATA4 << 16) | MUX_PA20K_PCC_DATA4) -#define PORT_PA20K_PCC_DATA4 ((1UL) << 20) - -#define PIN_PA21K_PCC_DATA5 (21L) -#define MUX_PA21K_PCC_DATA5 (10L) -#define PINMUX_PA21K_PCC_DATA5 ((PIN_PA21K_PCC_DATA5 << 16) | MUX_PA21K_PCC_DATA5) -#define PORT_PA21K_PCC_DATA5 ((1UL) << 21) - -#define PIN_PA22K_PCC_DATA6 (22L) -#define MUX_PA22K_PCC_DATA6 (10L) -#define PINMUX_PA22K_PCC_DATA6 ((PIN_PA22K_PCC_DATA6 << 16) | MUX_PA22K_PCC_DATA6) -#define PORT_PA22K_PCC_DATA6 ((1UL) << 22) - -#define PIN_PA23K_PCC_DATA7 (23L) -#define MUX_PA23K_PCC_DATA7 (10L) -#define PINMUX_PA23K_PCC_DATA7 ((PIN_PA23K_PCC_DATA7 << 16) | MUX_PA23K_PCC_DATA7) -#define PORT_PA23K_PCC_DATA7 ((1UL) << 23) - -#define PIN_PB14K_PCC_DATA8 (46L) -#define MUX_PB14K_PCC_DATA8 (10L) -#define PINMUX_PB14K_PCC_DATA8 ((PIN_PB14K_PCC_DATA8 << 16) | MUX_PB14K_PCC_DATA8) -#define PORT_PB14K_PCC_DATA8 ((1UL) << 14) - -#define PIN_PB15K_PCC_DATA9 (47L) -#define MUX_PB15K_PCC_DATA9 (10L) -#define PINMUX_PB15K_PCC_DATA9 ((PIN_PB15K_PCC_DATA9 << 16) | MUX_PB15K_PCC_DATA9) -#define PORT_PB15K_PCC_DATA9 ((1UL) << 15) - -#define PIN_PC12K_PCC_DATA10 (76L) -#define MUX_PC12K_PCC_DATA10 (10L) -#define PINMUX_PC12K_PCC_DATA10 ((PIN_PC12K_PCC_DATA10 << 16) | MUX_PC12K_PCC_DATA10) -#define PORT_PC12K_PCC_DATA10 ((1UL) << 12) - -#define PIN_PC13K_PCC_DATA11 (77L) -#define MUX_PC13K_PCC_DATA11 (10L) -#define PINMUX_PC13K_PCC_DATA11 ((PIN_PC13K_PCC_DATA11 << 16) | MUX_PC13K_PCC_DATA11) -#define PORT_PC13K_PCC_DATA11 ((1UL) << 13) - -#define PIN_PC14K_PCC_DATA12 (78L) -#define MUX_PC14K_PCC_DATA12 (10L) -#define PINMUX_PC14K_PCC_DATA12 ((PIN_PC14K_PCC_DATA12 << 16) | MUX_PC14K_PCC_DATA12) -#define PORT_PC14K_PCC_DATA12 ((1UL) << 14) - -#define PIN_PC15K_PCC_DATA13 (79L) -#define MUX_PC15K_PCC_DATA13 (10L) -#define PINMUX_PC15K_PCC_DATA13 ((PIN_PC15K_PCC_DATA13 << 16) | MUX_PC15K_PCC_DATA13) -#define PORT_PC15K_PCC_DATA13 ((1UL) << 15) - -#define PIN_PA12K_PCC_DEN1 (12L) -#define MUX_PA12K_PCC_DEN1 (10L) -#define PINMUX_PA12K_PCC_DEN1 ((PIN_PA12K_PCC_DEN1 << 16) | MUX_PA12K_PCC_DEN1) -#define PORT_PA12K_PCC_DEN1 ((1UL) << 12) - -#define PIN_PA13K_PCC_DEN2 (13L) -#define MUX_PA13K_PCC_DEN2 (10L) -#define PINMUX_PA13K_PCC_DEN2 ((PIN_PA13K_PCC_DEN2 << 16) | MUX_PA13K_PCC_DEN2) -#define PORT_PA13K_PCC_DEN2 ((1UL) << 13) - -/* ========== PORT definition for PDEC peripheral ========== */ -#define PIN_PB18G_PDEC_QDI0 (50L) -#define MUX_PB18G_PDEC_QDI0 (6L) -#define PINMUX_PB18G_PDEC_QDI0 ((PIN_PB18G_PDEC_QDI0 << 16) | MUX_PB18G_PDEC_QDI0) -#define PORT_PB18G_PDEC_QDI0 ((1UL) << 18) - -#define PIN_PB23G_PDEC_QDI0 (55L) -#define MUX_PB23G_PDEC_QDI0 (6L) -#define PINMUX_PB23G_PDEC_QDI0 ((PIN_PB23G_PDEC_QDI0 << 16) | MUX_PB23G_PDEC_QDI0) -#define PORT_PB23G_PDEC_QDI0 ((1UL) << 23) - -#define PIN_PC16G_PDEC_QDI0 (80L) -#define MUX_PC16G_PDEC_QDI0 (6L) -#define PINMUX_PC16G_PDEC_QDI0 ((PIN_PC16G_PDEC_QDI0 << 16) | MUX_PC16G_PDEC_QDI0) -#define PORT_PC16G_PDEC_QDI0 ((1UL) << 16) - -#define PIN_PA24G_PDEC_QDI0 (24L) -#define MUX_PA24G_PDEC_QDI0 (6L) -#define PINMUX_PA24G_PDEC_QDI0 ((PIN_PA24G_PDEC_QDI0 << 16) | MUX_PA24G_PDEC_QDI0) -#define PORT_PA24G_PDEC_QDI0 ((1UL) << 24) - -#define PIN_PB19G_PDEC_QDI1 (51L) -#define MUX_PB19G_PDEC_QDI1 (6L) -#define PINMUX_PB19G_PDEC_QDI1 ((PIN_PB19G_PDEC_QDI1 << 16) | MUX_PB19G_PDEC_QDI1) -#define PORT_PB19G_PDEC_QDI1 ((1UL) << 19) - -#define PIN_PB24G_PDEC_QDI1 (56L) -#define MUX_PB24G_PDEC_QDI1 (6L) -#define PINMUX_PB24G_PDEC_QDI1 ((PIN_PB24G_PDEC_QDI1 << 16) | MUX_PB24G_PDEC_QDI1) -#define PORT_PB24G_PDEC_QDI1 ((1UL) << 24) - -#define PIN_PC17G_PDEC_QDI1 (81L) -#define MUX_PC17G_PDEC_QDI1 (6L) -#define PINMUX_PC17G_PDEC_QDI1 ((PIN_PC17G_PDEC_QDI1 << 16) | MUX_PC17G_PDEC_QDI1) -#define PORT_PC17G_PDEC_QDI1 ((1UL) << 17) - -#define PIN_PA25G_PDEC_QDI1 (25L) -#define MUX_PA25G_PDEC_QDI1 (6L) -#define PINMUX_PA25G_PDEC_QDI1 ((PIN_PA25G_PDEC_QDI1 << 16) | MUX_PA25G_PDEC_QDI1) -#define PORT_PA25G_PDEC_QDI1 ((1UL) << 25) - -#define PIN_PB20G_PDEC_QDI2 (52L) -#define MUX_PB20G_PDEC_QDI2 (6L) -#define PINMUX_PB20G_PDEC_QDI2 ((PIN_PB20G_PDEC_QDI2 << 16) | MUX_PB20G_PDEC_QDI2) -#define PORT_PB20G_PDEC_QDI2 ((1UL) << 20) - -#define PIN_PB25G_PDEC_QDI2 (57L) -#define MUX_PB25G_PDEC_QDI2 (6L) -#define PINMUX_PB25G_PDEC_QDI2 ((PIN_PB25G_PDEC_QDI2 << 16) | MUX_PB25G_PDEC_QDI2) -#define PORT_PB25G_PDEC_QDI2 ((1UL) << 25) - -#define PIN_PC18G_PDEC_QDI2 (82L) -#define MUX_PC18G_PDEC_QDI2 (6L) -#define PINMUX_PC18G_PDEC_QDI2 ((PIN_PC18G_PDEC_QDI2 << 16) | MUX_PC18G_PDEC_QDI2) -#define PORT_PC18G_PDEC_QDI2 ((1UL) << 18) - -#define PIN_PB22G_PDEC_QDI2 (54L) -#define MUX_PB22G_PDEC_QDI2 (6L) -#define PINMUX_PB22G_PDEC_QDI2 ((PIN_PB22G_PDEC_QDI2 << 16) | MUX_PB22G_PDEC_QDI2) -#define PORT_PB22G_PDEC_QDI2 ((1UL) << 22) - -/* ========== PORT definition for QSPI peripheral ========== */ -#define PIN_PB11H_QSPI_CS (43L) -#define MUX_PB11H_QSPI_CS (7L) -#define PINMUX_PB11H_QSPI_CS ((PIN_PB11H_QSPI_CS << 16) | MUX_PB11H_QSPI_CS) -#define PORT_PB11H_QSPI_CS ((1UL) << 11) - -#define PIN_PA08H_QSPI_DATA0 (8L) -#define MUX_PA08H_QSPI_DATA0 (7L) -#define PINMUX_PA08H_QSPI_DATA0 ((PIN_PA08H_QSPI_DATA0 << 16) | MUX_PA08H_QSPI_DATA0) -#define PORT_PA08H_QSPI_DATA0 ((1UL) << 8) - -#define PIN_PA09H_QSPI_DATA1 (9L) -#define MUX_PA09H_QSPI_DATA1 (7L) -#define PINMUX_PA09H_QSPI_DATA1 ((PIN_PA09H_QSPI_DATA1 << 16) | MUX_PA09H_QSPI_DATA1) -#define PORT_PA09H_QSPI_DATA1 ((1UL) << 9) - -#define PIN_PA10H_QSPI_DATA2 (10L) -#define MUX_PA10H_QSPI_DATA2 (7L) -#define PINMUX_PA10H_QSPI_DATA2 ((PIN_PA10H_QSPI_DATA2 << 16) | MUX_PA10H_QSPI_DATA2) -#define PORT_PA10H_QSPI_DATA2 ((1UL) << 10) - -#define PIN_PA11H_QSPI_DATA3 (11L) -#define MUX_PA11H_QSPI_DATA3 (7L) -#define PINMUX_PA11H_QSPI_DATA3 ((PIN_PA11H_QSPI_DATA3 << 16) | MUX_PA11H_QSPI_DATA3) -#define PORT_PA11H_QSPI_DATA3 ((1UL) << 11) - -#define PIN_PB10H_QSPI_SCK (42L) -#define MUX_PB10H_QSPI_SCK (7L) -#define PINMUX_PB10H_QSPI_SCK ((PIN_PB10H_QSPI_SCK << 16) | MUX_PB10H_QSPI_SCK) -#define PORT_PB10H_QSPI_SCK ((1UL) << 10) - -/* ========== PORT definition for SDHC0 peripheral ========== */ -#define PIN_PA06I_SDHC0_SDCD (6L) -#define MUX_PA06I_SDHC0_SDCD (8L) -#define PINMUX_PA06I_SDHC0_SDCD ((PIN_PA06I_SDHC0_SDCD << 16) | MUX_PA06I_SDHC0_SDCD) -#define PORT_PA06I_SDHC0_SDCD ((1UL) << 6) - -#define PIN_PA12I_SDHC0_SDCD (12L) -#define MUX_PA12I_SDHC0_SDCD (8L) -#define PINMUX_PA12I_SDHC0_SDCD ((PIN_PA12I_SDHC0_SDCD << 16) | MUX_PA12I_SDHC0_SDCD) -#define PORT_PA12I_SDHC0_SDCD ((1UL) << 12) - -#define PIN_PB12I_SDHC0_SDCD (44L) -#define MUX_PB12I_SDHC0_SDCD (8L) -#define PINMUX_PB12I_SDHC0_SDCD ((PIN_PB12I_SDHC0_SDCD << 16) | MUX_PB12I_SDHC0_SDCD) -#define PORT_PB12I_SDHC0_SDCD ((1UL) << 12) - -#define PIN_PC06I_SDHC0_SDCD (70L) -#define MUX_PC06I_SDHC0_SDCD (8L) -#define PINMUX_PC06I_SDHC0_SDCD ((PIN_PC06I_SDHC0_SDCD << 16) | MUX_PC06I_SDHC0_SDCD) -#define PORT_PC06I_SDHC0_SDCD ((1UL) << 6) - -#define PIN_PB11I_SDHC0_SDCK (43L) -#define MUX_PB11I_SDHC0_SDCK (8L) -#define PINMUX_PB11I_SDHC0_SDCK ((PIN_PB11I_SDHC0_SDCK << 16) | MUX_PB11I_SDHC0_SDCK) -#define PORT_PB11I_SDHC0_SDCK ((1UL) << 11) - -#define PIN_PA08I_SDHC0_SDCMD (8L) -#define MUX_PA08I_SDHC0_SDCMD (8L) -#define PINMUX_PA08I_SDHC0_SDCMD ((PIN_PA08I_SDHC0_SDCMD << 16) | MUX_PA08I_SDHC0_SDCMD) -#define PORT_PA08I_SDHC0_SDCMD ((1UL) << 8) - -#define PIN_PA09I_SDHC0_SDDAT0 (9L) -#define MUX_PA09I_SDHC0_SDDAT0 (8L) -#define PINMUX_PA09I_SDHC0_SDDAT0 ((PIN_PA09I_SDHC0_SDDAT0 << 16) | MUX_PA09I_SDHC0_SDDAT0) -#define PORT_PA09I_SDHC0_SDDAT0 ((1UL) << 9) - -#define PIN_PA10I_SDHC0_SDDAT1 (10L) -#define MUX_PA10I_SDHC0_SDDAT1 (8L) -#define PINMUX_PA10I_SDHC0_SDDAT1 ((PIN_PA10I_SDHC0_SDDAT1 << 16) | MUX_PA10I_SDHC0_SDDAT1) -#define PORT_PA10I_SDHC0_SDDAT1 ((1UL) << 10) - -#define PIN_PA11I_SDHC0_SDDAT2 (11L) -#define MUX_PA11I_SDHC0_SDDAT2 (8L) -#define PINMUX_PA11I_SDHC0_SDDAT2 ((PIN_PA11I_SDHC0_SDDAT2 << 16) | MUX_PA11I_SDHC0_SDDAT2) -#define PORT_PA11I_SDHC0_SDDAT2 ((1UL) << 11) - -#define PIN_PB10I_SDHC0_SDDAT3 (42L) -#define MUX_PB10I_SDHC0_SDDAT3 (8L) -#define PINMUX_PB10I_SDHC0_SDDAT3 ((PIN_PB10I_SDHC0_SDDAT3 << 16) | MUX_PB10I_SDHC0_SDDAT3) -#define PORT_PB10I_SDHC0_SDDAT3 ((1UL) << 10) - -#define PIN_PA07I_SDHC0_SDWP (7L) -#define MUX_PA07I_SDHC0_SDWP (8L) -#define PINMUX_PA07I_SDHC0_SDWP ((PIN_PA07I_SDHC0_SDWP << 16) | MUX_PA07I_SDHC0_SDWP) -#define PORT_PA07I_SDHC0_SDWP ((1UL) << 7) - -#define PIN_PA13I_SDHC0_SDWP (13L) -#define MUX_PA13I_SDHC0_SDWP (8L) -#define PINMUX_PA13I_SDHC0_SDWP ((PIN_PA13I_SDHC0_SDWP << 16) | MUX_PA13I_SDHC0_SDWP) -#define PORT_PA13I_SDHC0_SDWP ((1UL) << 13) - -#define PIN_PB13I_SDHC0_SDWP (45L) -#define MUX_PB13I_SDHC0_SDWP (8L) -#define PINMUX_PB13I_SDHC0_SDWP ((PIN_PB13I_SDHC0_SDWP << 16) | MUX_PB13I_SDHC0_SDWP) -#define PORT_PB13I_SDHC0_SDWP ((1UL) << 13) - -#define PIN_PC07I_SDHC0_SDWP (71L) -#define MUX_PC07I_SDHC0_SDWP (8L) -#define PINMUX_PC07I_SDHC0_SDWP ((PIN_PC07I_SDHC0_SDWP << 16) | MUX_PC07I_SDHC0_SDWP) -#define PORT_PC07I_SDHC0_SDWP ((1UL) << 7) - -/* ========== PORT definition for SDHC1 peripheral ========== */ -#define PIN_PB16I_SDHC1_SDCD (48L) -#define MUX_PB16I_SDHC1_SDCD (8L) -#define PINMUX_PB16I_SDHC1_SDCD ((PIN_PB16I_SDHC1_SDCD << 16) | MUX_PB16I_SDHC1_SDCD) -#define PORT_PB16I_SDHC1_SDCD ((1UL) << 16) - -#define PIN_PC20I_SDHC1_SDCD (84L) -#define MUX_PC20I_SDHC1_SDCD (8L) -#define PINMUX_PC20I_SDHC1_SDCD ((PIN_PC20I_SDHC1_SDCD << 16) | MUX_PC20I_SDHC1_SDCD) -#define PORT_PC20I_SDHC1_SDCD ((1UL) << 20) - -#define PIN_PA21I_SDHC1_SDCK (21L) -#define MUX_PA21I_SDHC1_SDCK (8L) -#define PINMUX_PA21I_SDHC1_SDCK ((PIN_PA21I_SDHC1_SDCK << 16) | MUX_PA21I_SDHC1_SDCK) -#define PORT_PA21I_SDHC1_SDCK ((1UL) << 21) - -#define PIN_PA20I_SDHC1_SDCMD (20L) -#define MUX_PA20I_SDHC1_SDCMD (8L) -#define PINMUX_PA20I_SDHC1_SDCMD ((PIN_PA20I_SDHC1_SDCMD << 16) | MUX_PA20I_SDHC1_SDCMD) -#define PORT_PA20I_SDHC1_SDCMD ((1UL) << 20) - -#define PIN_PB18I_SDHC1_SDDAT0 (50L) -#define MUX_PB18I_SDHC1_SDDAT0 (8L) -#define PINMUX_PB18I_SDHC1_SDDAT0 ((PIN_PB18I_SDHC1_SDDAT0 << 16) | MUX_PB18I_SDHC1_SDDAT0) -#define PORT_PB18I_SDHC1_SDDAT0 ((1UL) << 18) - -#define PIN_PB19I_SDHC1_SDDAT1 (51L) -#define MUX_PB19I_SDHC1_SDDAT1 (8L) -#define PINMUX_PB19I_SDHC1_SDDAT1 ((PIN_PB19I_SDHC1_SDDAT1 << 16) | MUX_PB19I_SDHC1_SDDAT1) -#define PORT_PB19I_SDHC1_SDDAT1 ((1UL) << 19) - -#define PIN_PB20I_SDHC1_SDDAT2 (52L) -#define MUX_PB20I_SDHC1_SDDAT2 (8L) -#define PINMUX_PB20I_SDHC1_SDDAT2 ((PIN_PB20I_SDHC1_SDDAT2 << 16) | MUX_PB20I_SDHC1_SDDAT2) -#define PORT_PB20I_SDHC1_SDDAT2 ((1UL) << 20) - -#define PIN_PB21I_SDHC1_SDDAT3 (53L) -#define MUX_PB21I_SDHC1_SDDAT3 (8L) -#define PINMUX_PB21I_SDHC1_SDDAT3 ((PIN_PB21I_SDHC1_SDDAT3 << 16) | MUX_PB21I_SDHC1_SDDAT3) -#define PORT_PB21I_SDHC1_SDDAT3 ((1UL) << 21) - -#define PIN_PB17I_SDHC1_SDWP (49L) -#define MUX_PB17I_SDHC1_SDWP (8L) -#define PINMUX_PB17I_SDHC1_SDWP ((PIN_PB17I_SDHC1_SDWP << 16) | MUX_PB17I_SDHC1_SDWP) -#define PORT_PB17I_SDHC1_SDWP ((1UL) << 17) - -#define PIN_PC21I_SDHC1_SDWP (85L) -#define MUX_PC21I_SDHC1_SDWP (8L) -#define PINMUX_PC21I_SDHC1_SDWP ((PIN_PC21I_SDHC1_SDWP << 16) | MUX_PC21I_SDHC1_SDWP) -#define PORT_PC21I_SDHC1_SDWP ((1UL) << 21) - -/* ========== PORT definition for SERCOM0 peripheral ========== */ -#define PIN_PA04D_SERCOM0_PAD0 (4L) -#define MUX_PA04D_SERCOM0_PAD0 (3L) -#define PINMUX_PA04D_SERCOM0_PAD0 ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0) -#define PORT_PA04D_SERCOM0_PAD0 ((1UL) << 4) - -#define PIN_PC17D_SERCOM0_PAD0 (81L) -#define MUX_PC17D_SERCOM0_PAD0 (3L) -#define PINMUX_PC17D_SERCOM0_PAD0 ((PIN_PC17D_SERCOM0_PAD0 << 16) | MUX_PC17D_SERCOM0_PAD0) -#define PORT_PC17D_SERCOM0_PAD0 ((1UL) << 17) - -#define PIN_PA08C_SERCOM0_PAD0 (8L) -#define MUX_PA08C_SERCOM0_PAD0 (2L) -#define PINMUX_PA08C_SERCOM0_PAD0 ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0) -#define PORT_PA08C_SERCOM0_PAD0 ((1UL) << 8) - -#define PIN_PB24C_SERCOM0_PAD0 (56L) -#define MUX_PB24C_SERCOM0_PAD0 (2L) -#define PINMUX_PB24C_SERCOM0_PAD0 ((PIN_PB24C_SERCOM0_PAD0 << 16) | MUX_PB24C_SERCOM0_PAD0) -#define PORT_PB24C_SERCOM0_PAD0 ((1UL) << 24) - -#define PIN_PA05D_SERCOM0_PAD1 (5L) -#define MUX_PA05D_SERCOM0_PAD1 (3L) -#define PINMUX_PA05D_SERCOM0_PAD1 ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1) -#define PORT_PA05D_SERCOM0_PAD1 ((1UL) << 5) - -#define PIN_PC16D_SERCOM0_PAD1 (80L) -#define MUX_PC16D_SERCOM0_PAD1 (3L) -#define PINMUX_PC16D_SERCOM0_PAD1 ((PIN_PC16D_SERCOM0_PAD1 << 16) | MUX_PC16D_SERCOM0_PAD1) -#define PORT_PC16D_SERCOM0_PAD1 ((1UL) << 16) - -#define PIN_PA09C_SERCOM0_PAD1 (9L) -#define MUX_PA09C_SERCOM0_PAD1 (2L) -#define PINMUX_PA09C_SERCOM0_PAD1 ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1) -#define PORT_PA09C_SERCOM0_PAD1 ((1UL) << 9) - -#define PIN_PB25C_SERCOM0_PAD1 (57L) -#define MUX_PB25C_SERCOM0_PAD1 (2L) -#define PINMUX_PB25C_SERCOM0_PAD1 ((PIN_PB25C_SERCOM0_PAD1 << 16) | MUX_PB25C_SERCOM0_PAD1) -#define PORT_PB25C_SERCOM0_PAD1 ((1UL) << 25) - -#define PIN_PA06D_SERCOM0_PAD2 (6L) -#define MUX_PA06D_SERCOM0_PAD2 (3L) -#define PINMUX_PA06D_SERCOM0_PAD2 ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2) -#define PORT_PA06D_SERCOM0_PAD2 ((1UL) << 6) - -#define PIN_PC18D_SERCOM0_PAD2 (82L) -#define MUX_PC18D_SERCOM0_PAD2 (3L) -#define PINMUX_PC18D_SERCOM0_PAD2 ((PIN_PC18D_SERCOM0_PAD2 << 16) | MUX_PC18D_SERCOM0_PAD2) -#define PORT_PC18D_SERCOM0_PAD2 ((1UL) << 18) - -#define PIN_PA10C_SERCOM0_PAD2 (10L) -#define MUX_PA10C_SERCOM0_PAD2 (2L) -#define PINMUX_PA10C_SERCOM0_PAD2 ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2) -#define PORT_PA10C_SERCOM0_PAD2 ((1UL) << 10) - -#define PIN_PC24C_SERCOM0_PAD2 (88L) -#define MUX_PC24C_SERCOM0_PAD2 (2L) -#define PINMUX_PC24C_SERCOM0_PAD2 ((PIN_PC24C_SERCOM0_PAD2 << 16) | MUX_PC24C_SERCOM0_PAD2) -#define PORT_PC24C_SERCOM0_PAD2 ((1UL) << 24) - -#define PIN_PA07D_SERCOM0_PAD3 (7L) -#define MUX_PA07D_SERCOM0_PAD3 (3L) -#define PINMUX_PA07D_SERCOM0_PAD3 ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3) -#define PORT_PA07D_SERCOM0_PAD3 ((1UL) << 7) - -#define PIN_PC19D_SERCOM0_PAD3 (83L) -#define MUX_PC19D_SERCOM0_PAD3 (3L) -#define PINMUX_PC19D_SERCOM0_PAD3 ((PIN_PC19D_SERCOM0_PAD3 << 16) | MUX_PC19D_SERCOM0_PAD3) -#define PORT_PC19D_SERCOM0_PAD3 ((1UL) << 19) - -#define PIN_PA11C_SERCOM0_PAD3 (11L) -#define MUX_PA11C_SERCOM0_PAD3 (2L) -#define PINMUX_PA11C_SERCOM0_PAD3 ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3) -#define PORT_PA11C_SERCOM0_PAD3 ((1UL) << 11) - -#define PIN_PC25C_SERCOM0_PAD3 (89L) -#define MUX_PC25C_SERCOM0_PAD3 (2L) -#define PINMUX_PC25C_SERCOM0_PAD3 ((PIN_PC25C_SERCOM0_PAD3 << 16) | MUX_PC25C_SERCOM0_PAD3) -#define PORT_PC25C_SERCOM0_PAD3 ((1UL) << 25) - -/* ========== PORT definition for SERCOM1 peripheral ========== */ -#define PIN_PA00D_SERCOM1_PAD0 (0L) -#define MUX_PA00D_SERCOM1_PAD0 (3L) -#define PINMUX_PA00D_SERCOM1_PAD0 ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0) -#define PORT_PA00D_SERCOM1_PAD0 ((1UL) << 0) - -#define PIN_PA16C_SERCOM1_PAD0 (16L) -#define MUX_PA16C_SERCOM1_PAD0 (2L) -#define PINMUX_PA16C_SERCOM1_PAD0 ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0) -#define PORT_PA16C_SERCOM1_PAD0 ((1UL) << 16) - -#define PIN_PC27C_SERCOM1_PAD0 (91L) -#define MUX_PC27C_SERCOM1_PAD0 (2L) -#define PINMUX_PC27C_SERCOM1_PAD0 ((PIN_PC27C_SERCOM1_PAD0 << 16) | MUX_PC27C_SERCOM1_PAD0) -#define PORT_PC27C_SERCOM1_PAD0 ((1UL) << 27) - -#define PIN_PA01D_SERCOM1_PAD1 (1L) -#define MUX_PA01D_SERCOM1_PAD1 (3L) -#define PINMUX_PA01D_SERCOM1_PAD1 ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1) -#define PORT_PA01D_SERCOM1_PAD1 ((1UL) << 1) - -#define PIN_PA17C_SERCOM1_PAD1 (17L) -#define MUX_PA17C_SERCOM1_PAD1 (2L) -#define PINMUX_PA17C_SERCOM1_PAD1 ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1) -#define PORT_PA17C_SERCOM1_PAD1 ((1UL) << 17) - -#define PIN_PC28C_SERCOM1_PAD1 (92L) -#define MUX_PC28C_SERCOM1_PAD1 (2L) -#define PINMUX_PC28C_SERCOM1_PAD1 ((PIN_PC28C_SERCOM1_PAD1 << 16) | MUX_PC28C_SERCOM1_PAD1) -#define PORT_PC28C_SERCOM1_PAD1 ((1UL) << 28) - -#define PIN_PA30D_SERCOM1_PAD2 (30L) -#define MUX_PA30D_SERCOM1_PAD2 (3L) -#define PINMUX_PA30D_SERCOM1_PAD2 ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2) -#define PORT_PA30D_SERCOM1_PAD2 ((1UL) << 30) - -#define PIN_PA18C_SERCOM1_PAD2 (18L) -#define MUX_PA18C_SERCOM1_PAD2 (2L) -#define PINMUX_PA18C_SERCOM1_PAD2 ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2) -#define PORT_PA18C_SERCOM1_PAD2 ((1UL) << 18) - -#define PIN_PB22C_SERCOM1_PAD2 (54L) -#define MUX_PB22C_SERCOM1_PAD2 (2L) -#define PINMUX_PB22C_SERCOM1_PAD2 ((PIN_PB22C_SERCOM1_PAD2 << 16) | MUX_PB22C_SERCOM1_PAD2) -#define PORT_PB22C_SERCOM1_PAD2 ((1UL) << 22) - -#define PIN_PA31D_SERCOM1_PAD3 (31L) -#define MUX_PA31D_SERCOM1_PAD3 (3L) -#define PINMUX_PA31D_SERCOM1_PAD3 ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3) -#define PORT_PA31D_SERCOM1_PAD3 ((1UL) << 31) - -#define PIN_PA19C_SERCOM1_PAD3 (19L) -#define MUX_PA19C_SERCOM1_PAD3 (2L) -#define PINMUX_PA19C_SERCOM1_PAD3 ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3) -#define PORT_PA19C_SERCOM1_PAD3 ((1UL) << 19) - -#define PIN_PB23C_SERCOM1_PAD3 (55L) -#define MUX_PB23C_SERCOM1_PAD3 (2L) -#define PINMUX_PB23C_SERCOM1_PAD3 ((PIN_PB23C_SERCOM1_PAD3 << 16) | MUX_PB23C_SERCOM1_PAD3) -#define PORT_PB23C_SERCOM1_PAD3 ((1UL) << 23) - -/* ========== PORT definition for SERCOM2 peripheral ========== */ -#define PIN_PA09D_SERCOM2_PAD0 (9L) -#define MUX_PA09D_SERCOM2_PAD0 (3L) -#define PINMUX_PA09D_SERCOM2_PAD0 ((PIN_PA09D_SERCOM2_PAD0 << 16) | MUX_PA09D_SERCOM2_PAD0) -#define PORT_PA09D_SERCOM2_PAD0 ((1UL) << 9) - -#define PIN_PB25D_SERCOM2_PAD0 (57L) -#define MUX_PB25D_SERCOM2_PAD0 (3L) -#define PINMUX_PB25D_SERCOM2_PAD0 ((PIN_PB25D_SERCOM2_PAD0 << 16) | MUX_PB25D_SERCOM2_PAD0) -#define PORT_PB25D_SERCOM2_PAD0 ((1UL) << 25) - -#define PIN_PA12C_SERCOM2_PAD0 (12L) -#define MUX_PA12C_SERCOM2_PAD0 (2L) -#define PINMUX_PA12C_SERCOM2_PAD0 ((PIN_PA12C_SERCOM2_PAD0 << 16) | MUX_PA12C_SERCOM2_PAD0) -#define PORT_PA12C_SERCOM2_PAD0 ((1UL) << 12) - -#define PIN_PA08D_SERCOM2_PAD1 (8L) -#define MUX_PA08D_SERCOM2_PAD1 (3L) -#define PINMUX_PA08D_SERCOM2_PAD1 ((PIN_PA08D_SERCOM2_PAD1 << 16) | MUX_PA08D_SERCOM2_PAD1) -#define PORT_PA08D_SERCOM2_PAD1 ((1UL) << 8) - -#define PIN_PB24D_SERCOM2_PAD1 (56L) -#define MUX_PB24D_SERCOM2_PAD1 (3L) -#define PINMUX_PB24D_SERCOM2_PAD1 ((PIN_PB24D_SERCOM2_PAD1 << 16) | MUX_PB24D_SERCOM2_PAD1) -#define PORT_PB24D_SERCOM2_PAD1 ((1UL) << 24) - -#define PIN_PA13C_SERCOM2_PAD1 (13L) -#define MUX_PA13C_SERCOM2_PAD1 (2L) -#define PINMUX_PA13C_SERCOM2_PAD1 ((PIN_PA13C_SERCOM2_PAD1 << 16) | MUX_PA13C_SERCOM2_PAD1) -#define PORT_PA13C_SERCOM2_PAD1 ((1UL) << 13) - -#define PIN_PA10D_SERCOM2_PAD2 (10L) -#define MUX_PA10D_SERCOM2_PAD2 (3L) -#define PINMUX_PA10D_SERCOM2_PAD2 ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2) -#define PORT_PA10D_SERCOM2_PAD2 ((1UL) << 10) - -#define PIN_PC24D_SERCOM2_PAD2 (88L) -#define MUX_PC24D_SERCOM2_PAD2 (3L) -#define PINMUX_PC24D_SERCOM2_PAD2 ((PIN_PC24D_SERCOM2_PAD2 << 16) | MUX_PC24D_SERCOM2_PAD2) -#define PORT_PC24D_SERCOM2_PAD2 ((1UL) << 24) - -#define PIN_PA14C_SERCOM2_PAD2 (14L) -#define MUX_PA14C_SERCOM2_PAD2 (2L) -#define PINMUX_PA14C_SERCOM2_PAD2 ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2) -#define PORT_PA14C_SERCOM2_PAD2 ((1UL) << 14) - -#define PIN_PA11D_SERCOM2_PAD3 (11L) -#define MUX_PA11D_SERCOM2_PAD3 (3L) -#define PINMUX_PA11D_SERCOM2_PAD3 ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3) -#define PORT_PA11D_SERCOM2_PAD3 ((1UL) << 11) - -#define PIN_PC25D_SERCOM2_PAD3 (89L) -#define MUX_PC25D_SERCOM2_PAD3 (3L) -#define PINMUX_PC25D_SERCOM2_PAD3 ((PIN_PC25D_SERCOM2_PAD3 << 16) | MUX_PC25D_SERCOM2_PAD3) -#define PORT_PC25D_SERCOM2_PAD3 ((1UL) << 25) - -#define PIN_PA15C_SERCOM2_PAD3 (15L) -#define MUX_PA15C_SERCOM2_PAD3 (2L) -#define PINMUX_PA15C_SERCOM2_PAD3 ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3) -#define PORT_PA15C_SERCOM2_PAD3 ((1UL) << 15) - -/* ========== PORT definition for SERCOM3 peripheral ========== */ -#define PIN_PA17D_SERCOM3_PAD0 (17L) -#define MUX_PA17D_SERCOM3_PAD0 (3L) -#define PINMUX_PA17D_SERCOM3_PAD0 ((PIN_PA17D_SERCOM3_PAD0 << 16) | MUX_PA17D_SERCOM3_PAD0) -#define PORT_PA17D_SERCOM3_PAD0 ((1UL) << 17) - -#define PIN_PA22C_SERCOM3_PAD0 (22L) -#define MUX_PA22C_SERCOM3_PAD0 (2L) -#define PINMUX_PA22C_SERCOM3_PAD0 ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0) -#define PORT_PA22C_SERCOM3_PAD0 ((1UL) << 22) - -#define PIN_PB20C_SERCOM3_PAD0 (52L) -#define MUX_PB20C_SERCOM3_PAD0 (2L) -#define PINMUX_PB20C_SERCOM3_PAD0 ((PIN_PB20C_SERCOM3_PAD0 << 16) | MUX_PB20C_SERCOM3_PAD0) -#define PORT_PB20C_SERCOM3_PAD0 ((1UL) << 20) - -#define PIN_PA16D_SERCOM3_PAD1 (16L) -#define MUX_PA16D_SERCOM3_PAD1 (3L) -#define PINMUX_PA16D_SERCOM3_PAD1 ((PIN_PA16D_SERCOM3_PAD1 << 16) | MUX_PA16D_SERCOM3_PAD1) -#define PORT_PA16D_SERCOM3_PAD1 ((1UL) << 16) - -#define PIN_PA23C_SERCOM3_PAD1 (23L) -#define MUX_PA23C_SERCOM3_PAD1 (2L) -#define PINMUX_PA23C_SERCOM3_PAD1 ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1) -#define PORT_PA23C_SERCOM3_PAD1 ((1UL) << 23) - -#define PIN_PB21C_SERCOM3_PAD1 (53L) -#define MUX_PB21C_SERCOM3_PAD1 (2L) -#define PINMUX_PB21C_SERCOM3_PAD1 ((PIN_PB21C_SERCOM3_PAD1 << 16) | MUX_PB21C_SERCOM3_PAD1) -#define PORT_PB21C_SERCOM3_PAD1 ((1UL) << 21) - -#define PIN_PA18D_SERCOM3_PAD2 (18L) -#define MUX_PA18D_SERCOM3_PAD2 (3L) -#define PINMUX_PA18D_SERCOM3_PAD2 ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2) -#define PORT_PA18D_SERCOM3_PAD2 ((1UL) << 18) - -#define PIN_PA20D_SERCOM3_PAD2 (20L) -#define MUX_PA20D_SERCOM3_PAD2 (3L) -#define PINMUX_PA20D_SERCOM3_PAD2 ((PIN_PA20D_SERCOM3_PAD2 << 16) | MUX_PA20D_SERCOM3_PAD2) -#define PORT_PA20D_SERCOM3_PAD2 ((1UL) << 20) - -#define PIN_PA24C_SERCOM3_PAD2 (24L) -#define MUX_PA24C_SERCOM3_PAD2 (2L) -#define PINMUX_PA24C_SERCOM3_PAD2 ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2) -#define PORT_PA24C_SERCOM3_PAD2 ((1UL) << 24) - -#define PIN_PA19D_SERCOM3_PAD3 (19L) -#define MUX_PA19D_SERCOM3_PAD3 (3L) -#define PINMUX_PA19D_SERCOM3_PAD3 ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3) -#define PORT_PA19D_SERCOM3_PAD3 ((1UL) << 19) - -#define PIN_PA21D_SERCOM3_PAD3 (21L) -#define MUX_PA21D_SERCOM3_PAD3 (3L) -#define PINMUX_PA21D_SERCOM3_PAD3 ((PIN_PA21D_SERCOM3_PAD3 << 16) | MUX_PA21D_SERCOM3_PAD3) -#define PORT_PA21D_SERCOM3_PAD3 ((1UL) << 21) - -#define PIN_PA25C_SERCOM3_PAD3 (25L) -#define MUX_PA25C_SERCOM3_PAD3 (2L) -#define PINMUX_PA25C_SERCOM3_PAD3 ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3) -#define PORT_PA25C_SERCOM3_PAD3 ((1UL) << 25) - -/* ========== PORT definition for SERCOM4 peripheral ========== */ -#define PIN_PA13D_SERCOM4_PAD0 (13L) -#define MUX_PA13D_SERCOM4_PAD0 (3L) -#define PINMUX_PA13D_SERCOM4_PAD0 ((PIN_PA13D_SERCOM4_PAD0 << 16) | MUX_PA13D_SERCOM4_PAD0) -#define PORT_PA13D_SERCOM4_PAD0 ((1UL) << 13) - -#define PIN_PB08D_SERCOM4_PAD0 (40L) -#define MUX_PB08D_SERCOM4_PAD0 (3L) -#define PINMUX_PB08D_SERCOM4_PAD0 ((PIN_PB08D_SERCOM4_PAD0 << 16) | MUX_PB08D_SERCOM4_PAD0) -#define PORT_PB08D_SERCOM4_PAD0 ((1UL) << 8) - -#define PIN_PB12C_SERCOM4_PAD0 (44L) -#define MUX_PB12C_SERCOM4_PAD0 (2L) -#define PINMUX_PB12C_SERCOM4_PAD0 ((PIN_PB12C_SERCOM4_PAD0 << 16) | MUX_PB12C_SERCOM4_PAD0) -#define PORT_PB12C_SERCOM4_PAD0 ((1UL) << 12) - -#define PIN_PA12D_SERCOM4_PAD1 (12L) -#define MUX_PA12D_SERCOM4_PAD1 (3L) -#define PINMUX_PA12D_SERCOM4_PAD1 ((PIN_PA12D_SERCOM4_PAD1 << 16) | MUX_PA12D_SERCOM4_PAD1) -#define PORT_PA12D_SERCOM4_PAD1 ((1UL) << 12) - -#define PIN_PB09D_SERCOM4_PAD1 (41L) -#define MUX_PB09D_SERCOM4_PAD1 (3L) -#define PINMUX_PB09D_SERCOM4_PAD1 ((PIN_PB09D_SERCOM4_PAD1 << 16) | MUX_PB09D_SERCOM4_PAD1) -#define PORT_PB09D_SERCOM4_PAD1 ((1UL) << 9) - -#define PIN_PB13C_SERCOM4_PAD1 (45L) -#define MUX_PB13C_SERCOM4_PAD1 (2L) -#define PINMUX_PB13C_SERCOM4_PAD1 ((PIN_PB13C_SERCOM4_PAD1 << 16) | MUX_PB13C_SERCOM4_PAD1) -#define PORT_PB13C_SERCOM4_PAD1 ((1UL) << 13) - -#define PIN_PA14D_SERCOM4_PAD2 (14L) -#define MUX_PA14D_SERCOM4_PAD2 (3L) -#define PINMUX_PA14D_SERCOM4_PAD2 ((PIN_PA14D_SERCOM4_PAD2 << 16) | MUX_PA14D_SERCOM4_PAD2) -#define PORT_PA14D_SERCOM4_PAD2 ((1UL) << 14) - -#define PIN_PB10D_SERCOM4_PAD2 (42L) -#define MUX_PB10D_SERCOM4_PAD2 (3L) -#define PINMUX_PB10D_SERCOM4_PAD2 ((PIN_PB10D_SERCOM4_PAD2 << 16) | MUX_PB10D_SERCOM4_PAD2) -#define PORT_PB10D_SERCOM4_PAD2 ((1UL) << 10) - -#define PIN_PB14C_SERCOM4_PAD2 (46L) -#define MUX_PB14C_SERCOM4_PAD2 (2L) -#define PINMUX_PB14C_SERCOM4_PAD2 ((PIN_PB14C_SERCOM4_PAD2 << 16) | MUX_PB14C_SERCOM4_PAD2) -#define PORT_PB14C_SERCOM4_PAD2 ((1UL) << 14) - -#define PIN_PB11D_SERCOM4_PAD3 (43L) -#define MUX_PB11D_SERCOM4_PAD3 (3L) -#define PINMUX_PB11D_SERCOM4_PAD3 ((PIN_PB11D_SERCOM4_PAD3 << 16) | MUX_PB11D_SERCOM4_PAD3) -#define PORT_PB11D_SERCOM4_PAD3 ((1UL) << 11) - -#define PIN_PA15D_SERCOM4_PAD3 (15L) -#define MUX_PA15D_SERCOM4_PAD3 (3L) -#define PINMUX_PA15D_SERCOM4_PAD3 ((PIN_PA15D_SERCOM4_PAD3 << 16) | MUX_PA15D_SERCOM4_PAD3) -#define PORT_PA15D_SERCOM4_PAD3 ((1UL) << 15) - -#define PIN_PB15C_SERCOM4_PAD3 (47L) -#define MUX_PB15C_SERCOM4_PAD3 (2L) -#define PINMUX_PB15C_SERCOM4_PAD3 ((PIN_PB15C_SERCOM4_PAD3 << 16) | MUX_PB15C_SERCOM4_PAD3) -#define PORT_PB15C_SERCOM4_PAD3 ((1UL) << 15) - -/* ========== PORT definition for SERCOM5 peripheral ========== */ -#define PIN_PA23D_SERCOM5_PAD0 (23L) -#define MUX_PA23D_SERCOM5_PAD0 (3L) -#define PINMUX_PA23D_SERCOM5_PAD0 ((PIN_PA23D_SERCOM5_PAD0 << 16) | MUX_PA23D_SERCOM5_PAD0) -#define PORT_PA23D_SERCOM5_PAD0 ((1UL) << 23) - -#define PIN_PB02D_SERCOM5_PAD0 (34L) -#define MUX_PB02D_SERCOM5_PAD0 (3L) -#define PINMUX_PB02D_SERCOM5_PAD0 ((PIN_PB02D_SERCOM5_PAD0 << 16) | MUX_PB02D_SERCOM5_PAD0) -#define PORT_PB02D_SERCOM5_PAD0 ((1UL) << 2) - -#define PIN_PB31D_SERCOM5_PAD0 (63L) -#define MUX_PB31D_SERCOM5_PAD0 (3L) -#define PINMUX_PB31D_SERCOM5_PAD0 ((PIN_PB31D_SERCOM5_PAD0 << 16) | MUX_PB31D_SERCOM5_PAD0) -#define PORT_PB31D_SERCOM5_PAD0 ((1UL) << 31) - -#define PIN_PB16C_SERCOM5_PAD0 (48L) -#define MUX_PB16C_SERCOM5_PAD0 (2L) -#define PINMUX_PB16C_SERCOM5_PAD0 ((PIN_PB16C_SERCOM5_PAD0 << 16) | MUX_PB16C_SERCOM5_PAD0) -#define PORT_PB16C_SERCOM5_PAD0 ((1UL) << 16) - -#define PIN_PA22D_SERCOM5_PAD1 (22L) -#define MUX_PA22D_SERCOM5_PAD1 (3L) -#define PINMUX_PA22D_SERCOM5_PAD1 ((PIN_PA22D_SERCOM5_PAD1 << 16) | MUX_PA22D_SERCOM5_PAD1) -#define PORT_PA22D_SERCOM5_PAD1 ((1UL) << 22) - -#define PIN_PB03D_SERCOM5_PAD1 (35L) -#define MUX_PB03D_SERCOM5_PAD1 (3L) -#define PINMUX_PB03D_SERCOM5_PAD1 ((PIN_PB03D_SERCOM5_PAD1 << 16) | MUX_PB03D_SERCOM5_PAD1) -#define PORT_PB03D_SERCOM5_PAD1 ((1UL) << 3) - -#define PIN_PB30D_SERCOM5_PAD1 (62L) -#define MUX_PB30D_SERCOM5_PAD1 (3L) -#define PINMUX_PB30D_SERCOM5_PAD1 ((PIN_PB30D_SERCOM5_PAD1 << 16) | MUX_PB30D_SERCOM5_PAD1) -#define PORT_PB30D_SERCOM5_PAD1 ((1UL) << 30) - -#define PIN_PB17C_SERCOM5_PAD1 (49L) -#define MUX_PB17C_SERCOM5_PAD1 (2L) -#define PINMUX_PB17C_SERCOM5_PAD1 ((PIN_PB17C_SERCOM5_PAD1 << 16) | MUX_PB17C_SERCOM5_PAD1) -#define PORT_PB17C_SERCOM5_PAD1 ((1UL) << 17) - -#define PIN_PA24D_SERCOM5_PAD2 (24L) -#define MUX_PA24D_SERCOM5_PAD2 (3L) -#define PINMUX_PA24D_SERCOM5_PAD2 ((PIN_PA24D_SERCOM5_PAD2 << 16) | MUX_PA24D_SERCOM5_PAD2) -#define PORT_PA24D_SERCOM5_PAD2 ((1UL) << 24) - -#define PIN_PB00D_SERCOM5_PAD2 (32L) -#define MUX_PB00D_SERCOM5_PAD2 (3L) -#define PINMUX_PB00D_SERCOM5_PAD2 ((PIN_PB00D_SERCOM5_PAD2 << 16) | MUX_PB00D_SERCOM5_PAD2) -#define PORT_PB00D_SERCOM5_PAD2 ((1UL) << 0) - -#define PIN_PB22D_SERCOM5_PAD2 (54L) -#define MUX_PB22D_SERCOM5_PAD2 (3L) -#define PINMUX_PB22D_SERCOM5_PAD2 ((PIN_PB22D_SERCOM5_PAD2 << 16) | MUX_PB22D_SERCOM5_PAD2) -#define PORT_PB22D_SERCOM5_PAD2 ((1UL) << 22) - -#define PIN_PA20C_SERCOM5_PAD2 (20L) -#define MUX_PA20C_SERCOM5_PAD2 (2L) -#define PINMUX_PA20C_SERCOM5_PAD2 ((PIN_PA20C_SERCOM5_PAD2 << 16) | MUX_PA20C_SERCOM5_PAD2) -#define PORT_PA20C_SERCOM5_PAD2 ((1UL) << 20) - -#define PIN_PB18C_SERCOM5_PAD2 (50L) -#define MUX_PB18C_SERCOM5_PAD2 (2L) -#define PINMUX_PB18C_SERCOM5_PAD2 ((PIN_PB18C_SERCOM5_PAD2 << 16) | MUX_PB18C_SERCOM5_PAD2) -#define PORT_PB18C_SERCOM5_PAD2 ((1UL) << 18) - -#define PIN_PA25D_SERCOM5_PAD3 (25L) -#define MUX_PA25D_SERCOM5_PAD3 (3L) -#define PINMUX_PA25D_SERCOM5_PAD3 ((PIN_PA25D_SERCOM5_PAD3 << 16) | MUX_PA25D_SERCOM5_PAD3) -#define PORT_PA25D_SERCOM5_PAD3 ((1UL) << 25) - -#define PIN_PB01D_SERCOM5_PAD3 (33L) -#define MUX_PB01D_SERCOM5_PAD3 (3L) -#define PINMUX_PB01D_SERCOM5_PAD3 ((PIN_PB01D_SERCOM5_PAD3 << 16) | MUX_PB01D_SERCOM5_PAD3) -#define PORT_PB01D_SERCOM5_PAD3 ((1UL) << 1) - -#define PIN_PB23D_SERCOM5_PAD3 (55L) -#define MUX_PB23D_SERCOM5_PAD3 (3L) -#define PINMUX_PB23D_SERCOM5_PAD3 ((PIN_PB23D_SERCOM5_PAD3 << 16) | MUX_PB23D_SERCOM5_PAD3) -#define PORT_PB23D_SERCOM5_PAD3 ((1UL) << 23) - -#define PIN_PA21C_SERCOM5_PAD3 (21L) -#define MUX_PA21C_SERCOM5_PAD3 (2L) -#define PINMUX_PA21C_SERCOM5_PAD3 ((PIN_PA21C_SERCOM5_PAD3 << 16) | MUX_PA21C_SERCOM5_PAD3) -#define PORT_PA21C_SERCOM5_PAD3 ((1UL) << 21) - -#define PIN_PB19C_SERCOM5_PAD3 (51L) -#define MUX_PB19C_SERCOM5_PAD3 (2L) -#define PINMUX_PB19C_SERCOM5_PAD3 ((PIN_PB19C_SERCOM5_PAD3 << 16) | MUX_PB19C_SERCOM5_PAD3) -#define PORT_PB19C_SERCOM5_PAD3 ((1UL) << 19) - -/* ========== PORT definition for SERCOM6 peripheral ========== */ -#define PIN_PC13D_SERCOM6_PAD0 (77L) -#define MUX_PC13D_SERCOM6_PAD0 (3L) -#define PINMUX_PC13D_SERCOM6_PAD0 ((PIN_PC13D_SERCOM6_PAD0 << 16) | MUX_PC13D_SERCOM6_PAD0) -#define PORT_PC13D_SERCOM6_PAD0 ((1UL) << 13) - -#define PIN_PC16C_SERCOM6_PAD0 (80L) -#define MUX_PC16C_SERCOM6_PAD0 (2L) -#define PINMUX_PC16C_SERCOM6_PAD0 ((PIN_PC16C_SERCOM6_PAD0 << 16) | MUX_PC16C_SERCOM6_PAD0) -#define PORT_PC16C_SERCOM6_PAD0 ((1UL) << 16) - -#define PIN_PC12D_SERCOM6_PAD1 (76L) -#define MUX_PC12D_SERCOM6_PAD1 (3L) -#define PINMUX_PC12D_SERCOM6_PAD1 ((PIN_PC12D_SERCOM6_PAD1 << 16) | MUX_PC12D_SERCOM6_PAD1) -#define PORT_PC12D_SERCOM6_PAD1 ((1UL) << 12) - -#define PIN_PC05C_SERCOM6_PAD1 (69L) -#define MUX_PC05C_SERCOM6_PAD1 (2L) -#define PINMUX_PC05C_SERCOM6_PAD1 ((PIN_PC05C_SERCOM6_PAD1 << 16) | MUX_PC05C_SERCOM6_PAD1) -#define PORT_PC05C_SERCOM6_PAD1 ((1UL) << 5) - -#define PIN_PC17C_SERCOM6_PAD1 (81L) -#define MUX_PC17C_SERCOM6_PAD1 (2L) -#define PINMUX_PC17C_SERCOM6_PAD1 ((PIN_PC17C_SERCOM6_PAD1 << 16) | MUX_PC17C_SERCOM6_PAD1) -#define PORT_PC17C_SERCOM6_PAD1 ((1UL) << 17) - -#define PIN_PC14D_SERCOM6_PAD2 (78L) -#define MUX_PC14D_SERCOM6_PAD2 (3L) -#define PINMUX_PC14D_SERCOM6_PAD2 ((PIN_PC14D_SERCOM6_PAD2 << 16) | MUX_PC14D_SERCOM6_PAD2) -#define PORT_PC14D_SERCOM6_PAD2 ((1UL) << 14) - -#define PIN_PC06C_SERCOM6_PAD2 (70L) -#define MUX_PC06C_SERCOM6_PAD2 (2L) -#define PINMUX_PC06C_SERCOM6_PAD2 ((PIN_PC06C_SERCOM6_PAD2 << 16) | MUX_PC06C_SERCOM6_PAD2) -#define PORT_PC06C_SERCOM6_PAD2 ((1UL) << 6) - -#define PIN_PC10C_SERCOM6_PAD2 (74L) -#define MUX_PC10C_SERCOM6_PAD2 (2L) -#define PINMUX_PC10C_SERCOM6_PAD2 ((PIN_PC10C_SERCOM6_PAD2 << 16) | MUX_PC10C_SERCOM6_PAD2) -#define PORT_PC10C_SERCOM6_PAD2 ((1UL) << 10) - -#define PIN_PC18C_SERCOM6_PAD2 (82L) -#define MUX_PC18C_SERCOM6_PAD2 (2L) -#define PINMUX_PC18C_SERCOM6_PAD2 ((PIN_PC18C_SERCOM6_PAD2 << 16) | MUX_PC18C_SERCOM6_PAD2) -#define PORT_PC18C_SERCOM6_PAD2 ((1UL) << 18) - -#define PIN_PC15D_SERCOM6_PAD3 (79L) -#define MUX_PC15D_SERCOM6_PAD3 (3L) -#define PINMUX_PC15D_SERCOM6_PAD3 ((PIN_PC15D_SERCOM6_PAD3 << 16) | MUX_PC15D_SERCOM6_PAD3) -#define PORT_PC15D_SERCOM6_PAD3 ((1UL) << 15) - -#define PIN_PC07C_SERCOM6_PAD3 (71L) -#define MUX_PC07C_SERCOM6_PAD3 (2L) -#define PINMUX_PC07C_SERCOM6_PAD3 ((PIN_PC07C_SERCOM6_PAD3 << 16) | MUX_PC07C_SERCOM6_PAD3) -#define PORT_PC07C_SERCOM6_PAD3 ((1UL) << 7) - -#define PIN_PC11C_SERCOM6_PAD3 (75L) -#define MUX_PC11C_SERCOM6_PAD3 (2L) -#define PINMUX_PC11C_SERCOM6_PAD3 ((PIN_PC11C_SERCOM6_PAD3 << 16) | MUX_PC11C_SERCOM6_PAD3) -#define PORT_PC11C_SERCOM6_PAD3 ((1UL) << 11) - -#define PIN_PC19C_SERCOM6_PAD3 (83L) -#define MUX_PC19C_SERCOM6_PAD3 (2L) -#define PINMUX_PC19C_SERCOM6_PAD3 ((PIN_PC19C_SERCOM6_PAD3 << 16) | MUX_PC19C_SERCOM6_PAD3) -#define PORT_PC19C_SERCOM6_PAD3 ((1UL) << 19) - -/* ========== PORT definition for SERCOM7 peripheral ========== */ -#define PIN_PB21D_SERCOM7_PAD0 (53L) -#define MUX_PB21D_SERCOM7_PAD0 (3L) -#define PINMUX_PB21D_SERCOM7_PAD0 ((PIN_PB21D_SERCOM7_PAD0 << 16) | MUX_PB21D_SERCOM7_PAD0) -#define PORT_PB21D_SERCOM7_PAD0 ((1UL) << 21) - -#define PIN_PB30C_SERCOM7_PAD0 (62L) -#define MUX_PB30C_SERCOM7_PAD0 (2L) -#define PINMUX_PB30C_SERCOM7_PAD0 ((PIN_PB30C_SERCOM7_PAD0 << 16) | MUX_PB30C_SERCOM7_PAD0) -#define PORT_PB30C_SERCOM7_PAD0 ((1UL) << 30) - -#define PIN_PC12C_SERCOM7_PAD0 (76L) -#define MUX_PC12C_SERCOM7_PAD0 (2L) -#define PINMUX_PC12C_SERCOM7_PAD0 ((PIN_PC12C_SERCOM7_PAD0 << 16) | MUX_PC12C_SERCOM7_PAD0) -#define PORT_PC12C_SERCOM7_PAD0 ((1UL) << 12) - -#define PIN_PB20D_SERCOM7_PAD1 (52L) -#define MUX_PB20D_SERCOM7_PAD1 (3L) -#define PINMUX_PB20D_SERCOM7_PAD1 ((PIN_PB20D_SERCOM7_PAD1 << 16) | MUX_PB20D_SERCOM7_PAD1) -#define PORT_PB20D_SERCOM7_PAD1 ((1UL) << 20) - -#define PIN_PB31C_SERCOM7_PAD1 (63L) -#define MUX_PB31C_SERCOM7_PAD1 (2L) -#define PINMUX_PB31C_SERCOM7_PAD1 ((PIN_PB31C_SERCOM7_PAD1 << 16) | MUX_PB31C_SERCOM7_PAD1) -#define PORT_PB31C_SERCOM7_PAD1 ((1UL) << 31) - -#define PIN_PC13C_SERCOM7_PAD1 (77L) -#define MUX_PC13C_SERCOM7_PAD1 (2L) -#define PINMUX_PC13C_SERCOM7_PAD1 ((PIN_PC13C_SERCOM7_PAD1 << 16) | MUX_PC13C_SERCOM7_PAD1) -#define PORT_PC13C_SERCOM7_PAD1 ((1UL) << 13) - -#define PIN_PB18D_SERCOM7_PAD2 (50L) -#define MUX_PB18D_SERCOM7_PAD2 (3L) -#define PINMUX_PB18D_SERCOM7_PAD2 ((PIN_PB18D_SERCOM7_PAD2 << 16) | MUX_PB18D_SERCOM7_PAD2) -#define PORT_PB18D_SERCOM7_PAD2 ((1UL) << 18) - -#define PIN_PC10D_SERCOM7_PAD2 (74L) -#define MUX_PC10D_SERCOM7_PAD2 (3L) -#define PINMUX_PC10D_SERCOM7_PAD2 ((PIN_PC10D_SERCOM7_PAD2 << 16) | MUX_PC10D_SERCOM7_PAD2) -#define PORT_PC10D_SERCOM7_PAD2 ((1UL) << 10) - -#define PIN_PC14C_SERCOM7_PAD2 (78L) -#define MUX_PC14C_SERCOM7_PAD2 (2L) -#define PINMUX_PC14C_SERCOM7_PAD2 ((PIN_PC14C_SERCOM7_PAD2 << 16) | MUX_PC14C_SERCOM7_PAD2) -#define PORT_PC14C_SERCOM7_PAD2 ((1UL) << 14) - -#define PIN_PA30C_SERCOM7_PAD2 (30L) -#define MUX_PA30C_SERCOM7_PAD2 (2L) -#define PINMUX_PA30C_SERCOM7_PAD2 ((PIN_PA30C_SERCOM7_PAD2 << 16) | MUX_PA30C_SERCOM7_PAD2) -#define PORT_PA30C_SERCOM7_PAD2 ((1UL) << 30) - -#define PIN_PB19D_SERCOM7_PAD3 (51L) -#define MUX_PB19D_SERCOM7_PAD3 (3L) -#define PINMUX_PB19D_SERCOM7_PAD3 ((PIN_PB19D_SERCOM7_PAD3 << 16) | MUX_PB19D_SERCOM7_PAD3) -#define PORT_PB19D_SERCOM7_PAD3 ((1UL) << 19) - -#define PIN_PC11D_SERCOM7_PAD3 (75L) -#define MUX_PC11D_SERCOM7_PAD3 (3L) -#define PINMUX_PC11D_SERCOM7_PAD3 ((PIN_PC11D_SERCOM7_PAD3 << 16) | MUX_PC11D_SERCOM7_PAD3) -#define PORT_PC11D_SERCOM7_PAD3 ((1UL) << 11) - -#define PIN_PC15C_SERCOM7_PAD3 (79L) -#define MUX_PC15C_SERCOM7_PAD3 (2L) -#define PINMUX_PC15C_SERCOM7_PAD3 ((PIN_PC15C_SERCOM7_PAD3 << 16) | MUX_PC15C_SERCOM7_PAD3) -#define PORT_PC15C_SERCOM7_PAD3 ((1UL) << 15) - -#define PIN_PA31C_SERCOM7_PAD3 (31L) -#define MUX_PA31C_SERCOM7_PAD3 (2L) -#define PINMUX_PA31C_SERCOM7_PAD3 ((PIN_PA31C_SERCOM7_PAD3 << 16) | MUX_PA31C_SERCOM7_PAD3) -#define PORT_PA31C_SERCOM7_PAD3 ((1UL) << 31) - -/* ========== PORT definition for TC0 peripheral ========== */ -#define PIN_PA04E_TC0_WO0 (4L) -#define MUX_PA04E_TC0_WO0 (4L) -#define PINMUX_PA04E_TC0_WO0 ((PIN_PA04E_TC0_WO0 << 16) | MUX_PA04E_TC0_WO0) -#define PORT_PA04E_TC0_WO0 ((1UL) << 4) - -#define PIN_PA08E_TC0_WO0 (8L) -#define MUX_PA08E_TC0_WO0 (4L) -#define PINMUX_PA08E_TC0_WO0 ((PIN_PA08E_TC0_WO0 << 16) | MUX_PA08E_TC0_WO0) -#define PORT_PA08E_TC0_WO0 ((1UL) << 8) - -#define PIN_PB30E_TC0_WO0 (62L) -#define MUX_PB30E_TC0_WO0 (4L) -#define PINMUX_PB30E_TC0_WO0 ((PIN_PB30E_TC0_WO0 << 16) | MUX_PB30E_TC0_WO0) -#define PORT_PB30E_TC0_WO0 ((1UL) << 30) - -#define PIN_PA05E_TC0_WO1 (5L) -#define MUX_PA05E_TC0_WO1 (4L) -#define PINMUX_PA05E_TC0_WO1 ((PIN_PA05E_TC0_WO1 << 16) | MUX_PA05E_TC0_WO1) -#define PORT_PA05E_TC0_WO1 ((1UL) << 5) - -#define PIN_PA09E_TC0_WO1 (9L) -#define MUX_PA09E_TC0_WO1 (4L) -#define PINMUX_PA09E_TC0_WO1 ((PIN_PA09E_TC0_WO1 << 16) | MUX_PA09E_TC0_WO1) -#define PORT_PA09E_TC0_WO1 ((1UL) << 9) - -#define PIN_PB31E_TC0_WO1 (63L) -#define MUX_PB31E_TC0_WO1 (4L) -#define PINMUX_PB31E_TC0_WO1 ((PIN_PB31E_TC0_WO1 << 16) | MUX_PB31E_TC0_WO1) -#define PORT_PB31E_TC0_WO1 ((1UL) << 31) - -/* ========== PORT definition for TC1 peripheral ========== */ -#define PIN_PA06E_TC1_WO0 (6L) -#define MUX_PA06E_TC1_WO0 (4L) -#define PINMUX_PA06E_TC1_WO0 ((PIN_PA06E_TC1_WO0 << 16) | MUX_PA06E_TC1_WO0) -#define PORT_PA06E_TC1_WO0 ((1UL) << 6) - -#define PIN_PA10E_TC1_WO0 (10L) -#define MUX_PA10E_TC1_WO0 (4L) -#define PINMUX_PA10E_TC1_WO0 ((PIN_PA10E_TC1_WO0 << 16) | MUX_PA10E_TC1_WO0) -#define PORT_PA10E_TC1_WO0 ((1UL) << 10) - -#define PIN_PA07E_TC1_WO1 (7L) -#define MUX_PA07E_TC1_WO1 (4L) -#define PINMUX_PA07E_TC1_WO1 ((PIN_PA07E_TC1_WO1 << 16) | MUX_PA07E_TC1_WO1) -#define PORT_PA07E_TC1_WO1 ((1UL) << 7) - -#define PIN_PA11E_TC1_WO1 (11L) -#define MUX_PA11E_TC1_WO1 (4L) -#define PINMUX_PA11E_TC1_WO1 ((PIN_PA11E_TC1_WO1 << 16) | MUX_PA11E_TC1_WO1) -#define PORT_PA11E_TC1_WO1 ((1UL) << 11) - -/* ========== PORT definition for TC2 peripheral ========== */ -#define PIN_PA12E_TC2_WO0 (12L) -#define MUX_PA12E_TC2_WO0 (4L) -#define PINMUX_PA12E_TC2_WO0 ((PIN_PA12E_TC2_WO0 << 16) | MUX_PA12E_TC2_WO0) -#define PORT_PA12E_TC2_WO0 ((1UL) << 12) - -#define PIN_PA16E_TC2_WO0 (16L) -#define MUX_PA16E_TC2_WO0 (4L) -#define PINMUX_PA16E_TC2_WO0 ((PIN_PA16E_TC2_WO0 << 16) | MUX_PA16E_TC2_WO0) -#define PORT_PA16E_TC2_WO0 ((1UL) << 16) - -#define PIN_PA00E_TC2_WO0 (0L) -#define MUX_PA00E_TC2_WO0 (4L) -#define PINMUX_PA00E_TC2_WO0 ((PIN_PA00E_TC2_WO0 << 16) | MUX_PA00E_TC2_WO0) -#define PORT_PA00E_TC2_WO0 ((1UL) << 0) - -#define PIN_PA01E_TC2_WO1 (1L) -#define MUX_PA01E_TC2_WO1 (4L) -#define PINMUX_PA01E_TC2_WO1 ((PIN_PA01E_TC2_WO1 << 16) | MUX_PA01E_TC2_WO1) -#define PORT_PA01E_TC2_WO1 ((1UL) << 1) - -#define PIN_PA13E_TC2_WO1 (13L) -#define MUX_PA13E_TC2_WO1 (4L) -#define PINMUX_PA13E_TC2_WO1 ((PIN_PA13E_TC2_WO1 << 16) | MUX_PA13E_TC2_WO1) -#define PORT_PA13E_TC2_WO1 ((1UL) << 13) - -#define PIN_PA17E_TC2_WO1 (17L) -#define MUX_PA17E_TC2_WO1 (4L) -#define PINMUX_PA17E_TC2_WO1 ((PIN_PA17E_TC2_WO1 << 16) | MUX_PA17E_TC2_WO1) -#define PORT_PA17E_TC2_WO1 ((1UL) << 17) - -/* ========== PORT definition for TC3 peripheral ========== */ -#define PIN_PA18E_TC3_WO0 (18L) -#define MUX_PA18E_TC3_WO0 (4L) -#define PINMUX_PA18E_TC3_WO0 ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0) -#define PORT_PA18E_TC3_WO0 ((1UL) << 18) - -#define PIN_PA14E_TC3_WO0 (14L) -#define MUX_PA14E_TC3_WO0 (4L) -#define PINMUX_PA14E_TC3_WO0 ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0) -#define PORT_PA14E_TC3_WO0 ((1UL) << 14) - -#define PIN_PA15E_TC3_WO1 (15L) -#define MUX_PA15E_TC3_WO1 (4L) -#define PINMUX_PA15E_TC3_WO1 ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1) -#define PORT_PA15E_TC3_WO1 ((1UL) << 15) - -#define PIN_PA19E_TC3_WO1 (19L) -#define MUX_PA19E_TC3_WO1 (4L) -#define PINMUX_PA19E_TC3_WO1 ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1) -#define PORT_PA19E_TC3_WO1 ((1UL) << 19) - -/* ========== PORT definition for TC4 peripheral ========== */ -#define PIN_PA22E_TC4_WO0 (22L) -#define MUX_PA22E_TC4_WO0 (4L) -#define PINMUX_PA22E_TC4_WO0 ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0) -#define PORT_PA22E_TC4_WO0 ((1UL) << 22) - -#define PIN_PB08E_TC4_WO0 (40L) -#define MUX_PB08E_TC4_WO0 (4L) -#define PINMUX_PB08E_TC4_WO0 ((PIN_PB08E_TC4_WO0 << 16) | MUX_PB08E_TC4_WO0) -#define PORT_PB08E_TC4_WO0 ((1UL) << 8) - -#define PIN_PB12E_TC4_WO0 (44L) -#define MUX_PB12E_TC4_WO0 (4L) -#define PINMUX_PB12E_TC4_WO0 ((PIN_PB12E_TC4_WO0 << 16) | MUX_PB12E_TC4_WO0) -#define PORT_PB12E_TC4_WO0 ((1UL) << 12) - -#define PIN_PA23E_TC4_WO1 (23L) -#define MUX_PA23E_TC4_WO1 (4L) -#define PINMUX_PA23E_TC4_WO1 ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1) -#define PORT_PA23E_TC4_WO1 ((1UL) << 23) - -#define PIN_PB09E_TC4_WO1 (41L) -#define MUX_PB09E_TC4_WO1 (4L) -#define PINMUX_PB09E_TC4_WO1 ((PIN_PB09E_TC4_WO1 << 16) | MUX_PB09E_TC4_WO1) -#define PORT_PB09E_TC4_WO1 ((1UL) << 9) - -#define PIN_PB13E_TC4_WO1 (45L) -#define MUX_PB13E_TC4_WO1 (4L) -#define PINMUX_PB13E_TC4_WO1 ((PIN_PB13E_TC4_WO1 << 16) | MUX_PB13E_TC4_WO1) -#define PORT_PB13E_TC4_WO1 ((1UL) << 13) - -/* ========== PORT definition for TC5 peripheral ========== */ -#define PIN_PA24E_TC5_WO0 (24L) -#define MUX_PA24E_TC5_WO0 (4L) -#define PINMUX_PA24E_TC5_WO0 ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0) -#define PORT_PA24E_TC5_WO0 ((1UL) << 24) - -#define PIN_PB10E_TC5_WO0 (42L) -#define MUX_PB10E_TC5_WO0 (4L) -#define PINMUX_PB10E_TC5_WO0 ((PIN_PB10E_TC5_WO0 << 16) | MUX_PB10E_TC5_WO0) -#define PORT_PB10E_TC5_WO0 ((1UL) << 10) - -#define PIN_PB14E_TC5_WO0 (46L) -#define MUX_PB14E_TC5_WO0 (4L) -#define PINMUX_PB14E_TC5_WO0 ((PIN_PB14E_TC5_WO0 << 16) | MUX_PB14E_TC5_WO0) -#define PORT_PB14E_TC5_WO0 ((1UL) << 14) - -#define PIN_PA25E_TC5_WO1 (25L) -#define MUX_PA25E_TC5_WO1 (4L) -#define PINMUX_PA25E_TC5_WO1 ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1) -#define PORT_PA25E_TC5_WO1 ((1UL) << 25) - -#define PIN_PB11E_TC5_WO1 (43L) -#define MUX_PB11E_TC5_WO1 (4L) -#define PINMUX_PB11E_TC5_WO1 ((PIN_PB11E_TC5_WO1 << 16) | MUX_PB11E_TC5_WO1) -#define PORT_PB11E_TC5_WO1 ((1UL) << 11) - -#define PIN_PB15E_TC5_WO1 (47L) -#define MUX_PB15E_TC5_WO1 (4L) -#define PINMUX_PB15E_TC5_WO1 ((PIN_PB15E_TC5_WO1 << 16) | MUX_PB15E_TC5_WO1) -#define PORT_PB15E_TC5_WO1 ((1UL) << 15) - -/* ========== PORT definition for TC6 peripheral ========== */ -#define PIN_PA30E_TC6_WO0 (30L) -#define MUX_PA30E_TC6_WO0 (4L) -#define PINMUX_PA30E_TC6_WO0 ((PIN_PA30E_TC6_WO0 << 16) | MUX_PA30E_TC6_WO0) -#define PORT_PA30E_TC6_WO0 ((1UL) << 30) - -#define PIN_PB02E_TC6_WO0 (34L) -#define MUX_PB02E_TC6_WO0 (4L) -#define PINMUX_PB02E_TC6_WO0 ((PIN_PB02E_TC6_WO0 << 16) | MUX_PB02E_TC6_WO0) -#define PORT_PB02E_TC6_WO0 ((1UL) << 2) - -#define PIN_PB16E_TC6_WO0 (48L) -#define MUX_PB16E_TC6_WO0 (4L) -#define PINMUX_PB16E_TC6_WO0 ((PIN_PB16E_TC6_WO0 << 16) | MUX_PB16E_TC6_WO0) -#define PORT_PB16E_TC6_WO0 ((1UL) << 16) - -#define PIN_PA31E_TC6_WO1 (31L) -#define MUX_PA31E_TC6_WO1 (4L) -#define PINMUX_PA31E_TC6_WO1 ((PIN_PA31E_TC6_WO1 << 16) | MUX_PA31E_TC6_WO1) -#define PORT_PA31E_TC6_WO1 ((1UL) << 31) - -#define PIN_PB03E_TC6_WO1 (35L) -#define MUX_PB03E_TC6_WO1 (4L) -#define PINMUX_PB03E_TC6_WO1 ((PIN_PB03E_TC6_WO1 << 16) | MUX_PB03E_TC6_WO1) -#define PORT_PB03E_TC6_WO1 ((1UL) << 3) - -#define PIN_PB17E_TC6_WO1 (49L) -#define MUX_PB17E_TC6_WO1 (4L) -#define PINMUX_PB17E_TC6_WO1 ((PIN_PB17E_TC6_WO1 << 16) | MUX_PB17E_TC6_WO1) -#define PORT_PB17E_TC6_WO1 ((1UL) << 17) - -/* ========== PORT definition for TC7 peripheral ========== */ -#define PIN_PA20E_TC7_WO0 (20L) -#define MUX_PA20E_TC7_WO0 (4L) -#define PINMUX_PA20E_TC7_WO0 ((PIN_PA20E_TC7_WO0 << 16) | MUX_PA20E_TC7_WO0) -#define PORT_PA20E_TC7_WO0 ((1UL) << 20) - -#define PIN_PB00E_TC7_WO0 (32L) -#define MUX_PB00E_TC7_WO0 (4L) -#define PINMUX_PB00E_TC7_WO0 ((PIN_PB00E_TC7_WO0 << 16) | MUX_PB00E_TC7_WO0) -#define PORT_PB00E_TC7_WO0 ((1UL) << 0) - -#define PIN_PB22E_TC7_WO0 (54L) -#define MUX_PB22E_TC7_WO0 (4L) -#define PINMUX_PB22E_TC7_WO0 ((PIN_PB22E_TC7_WO0 << 16) | MUX_PB22E_TC7_WO0) -#define PORT_PB22E_TC7_WO0 ((1UL) << 22) - -#define PIN_PA21E_TC7_WO1 (21L) -#define MUX_PA21E_TC7_WO1 (4L) -#define PINMUX_PA21E_TC7_WO1 ((PIN_PA21E_TC7_WO1 << 16) | MUX_PA21E_TC7_WO1) -#define PORT_PA21E_TC7_WO1 ((1UL) << 21) - -#define PIN_PB01E_TC7_WO1 (33L) -#define MUX_PB01E_TC7_WO1 (4L) -#define PINMUX_PB01E_TC7_WO1 ((PIN_PB01E_TC7_WO1 << 16) | MUX_PB01E_TC7_WO1) -#define PORT_PB01E_TC7_WO1 ((1UL) << 1) - -#define PIN_PB23E_TC7_WO1 (55L) -#define MUX_PB23E_TC7_WO1 (4L) -#define PINMUX_PB23E_TC7_WO1 ((PIN_PB23E_TC7_WO1 << 16) | MUX_PB23E_TC7_WO1) -#define PORT_PB23E_TC7_WO1 ((1UL) << 23) - -/* ========== PORT definition for TCC0 peripheral ========== */ -#define PIN_PA20G_TCC0_WO0 (20L) -#define MUX_PA20G_TCC0_WO0 (6L) -#define PINMUX_PA20G_TCC0_WO0 ((PIN_PA20G_TCC0_WO0 << 16) | MUX_PA20G_TCC0_WO0) -#define PORT_PA20G_TCC0_WO0 ((1UL) << 20) - -#define PIN_PB12G_TCC0_WO0 (44L) -#define MUX_PB12G_TCC0_WO0 (6L) -#define PINMUX_PB12G_TCC0_WO0 ((PIN_PB12G_TCC0_WO0 << 16) | MUX_PB12G_TCC0_WO0) -#define PORT_PB12G_TCC0_WO0 ((1UL) << 12) - -#define PIN_PA08F_TCC0_WO0 (8L) -#define MUX_PA08F_TCC0_WO0 (5L) -#define PINMUX_PA08F_TCC0_WO0 ((PIN_PA08F_TCC0_WO0 << 16) | MUX_PA08F_TCC0_WO0) -#define PORT_PA08F_TCC0_WO0 ((1UL) << 8) - -#define PIN_PC10F_TCC0_WO0 (74L) -#define MUX_PC10F_TCC0_WO0 (5L) -#define PINMUX_PC10F_TCC0_WO0 ((PIN_PC10F_TCC0_WO0 << 16) | MUX_PC10F_TCC0_WO0) -#define PORT_PC10F_TCC0_WO0 ((1UL) << 10) - -#define PIN_PC16F_TCC0_WO0 (80L) -#define MUX_PC16F_TCC0_WO0 (5L) -#define PINMUX_PC16F_TCC0_WO0 ((PIN_PC16F_TCC0_WO0 << 16) | MUX_PC16F_TCC0_WO0) -#define PORT_PC16F_TCC0_WO0 ((1UL) << 16) - -#define PIN_PA21G_TCC0_WO1 (21L) -#define MUX_PA21G_TCC0_WO1 (6L) -#define PINMUX_PA21G_TCC0_WO1 ((PIN_PA21G_TCC0_WO1 << 16) | MUX_PA21G_TCC0_WO1) -#define PORT_PA21G_TCC0_WO1 ((1UL) << 21) - -#define PIN_PB13G_TCC0_WO1 (45L) -#define MUX_PB13G_TCC0_WO1 (6L) -#define PINMUX_PB13G_TCC0_WO1 ((PIN_PB13G_TCC0_WO1 << 16) | MUX_PB13G_TCC0_WO1) -#define PORT_PB13G_TCC0_WO1 ((1UL) << 13) - -#define PIN_PA09F_TCC0_WO1 (9L) -#define MUX_PA09F_TCC0_WO1 (5L) -#define PINMUX_PA09F_TCC0_WO1 ((PIN_PA09F_TCC0_WO1 << 16) | MUX_PA09F_TCC0_WO1) -#define PORT_PA09F_TCC0_WO1 ((1UL) << 9) - -#define PIN_PC11F_TCC0_WO1 (75L) -#define MUX_PC11F_TCC0_WO1 (5L) -#define PINMUX_PC11F_TCC0_WO1 ((PIN_PC11F_TCC0_WO1 << 16) | MUX_PC11F_TCC0_WO1) -#define PORT_PC11F_TCC0_WO1 ((1UL) << 11) - -#define PIN_PC17F_TCC0_WO1 (81L) -#define MUX_PC17F_TCC0_WO1 (5L) -#define PINMUX_PC17F_TCC0_WO1 ((PIN_PC17F_TCC0_WO1 << 16) | MUX_PC17F_TCC0_WO1) -#define PORT_PC17F_TCC0_WO1 ((1UL) << 17) - -#define PIN_PA22G_TCC0_WO2 (22L) -#define MUX_PA22G_TCC0_WO2 (6L) -#define PINMUX_PA22G_TCC0_WO2 ((PIN_PA22G_TCC0_WO2 << 16) | MUX_PA22G_TCC0_WO2) -#define PORT_PA22G_TCC0_WO2 ((1UL) << 22) - -#define PIN_PB14G_TCC0_WO2 (46L) -#define MUX_PB14G_TCC0_WO2 (6L) -#define PINMUX_PB14G_TCC0_WO2 ((PIN_PB14G_TCC0_WO2 << 16) | MUX_PB14G_TCC0_WO2) -#define PORT_PB14G_TCC0_WO2 ((1UL) << 14) - -#define PIN_PA10F_TCC0_WO2 (10L) -#define MUX_PA10F_TCC0_WO2 (5L) -#define PINMUX_PA10F_TCC0_WO2 ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2) -#define PORT_PA10F_TCC0_WO2 ((1UL) << 10) - -#define PIN_PC12F_TCC0_WO2 (76L) -#define MUX_PC12F_TCC0_WO2 (5L) -#define PINMUX_PC12F_TCC0_WO2 ((PIN_PC12F_TCC0_WO2 << 16) | MUX_PC12F_TCC0_WO2) -#define PORT_PC12F_TCC0_WO2 ((1UL) << 12) - -#define PIN_PC18F_TCC0_WO2 (82L) -#define MUX_PC18F_TCC0_WO2 (5L) -#define PINMUX_PC18F_TCC0_WO2 ((PIN_PC18F_TCC0_WO2 << 16) | MUX_PC18F_TCC0_WO2) -#define PORT_PC18F_TCC0_WO2 ((1UL) << 18) - -#define PIN_PA23G_TCC0_WO3 (23L) -#define MUX_PA23G_TCC0_WO3 (6L) -#define PINMUX_PA23G_TCC0_WO3 ((PIN_PA23G_TCC0_WO3 << 16) | MUX_PA23G_TCC0_WO3) -#define PORT_PA23G_TCC0_WO3 ((1UL) << 23) - -#define PIN_PB15G_TCC0_WO3 (47L) -#define MUX_PB15G_TCC0_WO3 (6L) -#define PINMUX_PB15G_TCC0_WO3 ((PIN_PB15G_TCC0_WO3 << 16) | MUX_PB15G_TCC0_WO3) -#define PORT_PB15G_TCC0_WO3 ((1UL) << 15) - -#define PIN_PA11F_TCC0_WO3 (11L) -#define MUX_PA11F_TCC0_WO3 (5L) -#define PINMUX_PA11F_TCC0_WO3 ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3) -#define PORT_PA11F_TCC0_WO3 ((1UL) << 11) - -#define PIN_PC13F_TCC0_WO3 (77L) -#define MUX_PC13F_TCC0_WO3 (5L) -#define PINMUX_PC13F_TCC0_WO3 ((PIN_PC13F_TCC0_WO3 << 16) | MUX_PC13F_TCC0_WO3) -#define PORT_PC13F_TCC0_WO3 ((1UL) << 13) - -#define PIN_PC19F_TCC0_WO3 (83L) -#define MUX_PC19F_TCC0_WO3 (5L) -#define PINMUX_PC19F_TCC0_WO3 ((PIN_PC19F_TCC0_WO3 << 16) | MUX_PC19F_TCC0_WO3) -#define PORT_PC19F_TCC0_WO3 ((1UL) << 19) - -#define PIN_PA16G_TCC0_WO4 (16L) -#define MUX_PA16G_TCC0_WO4 (6L) -#define PINMUX_PA16G_TCC0_WO4 ((PIN_PA16G_TCC0_WO4 << 16) | MUX_PA16G_TCC0_WO4) -#define PORT_PA16G_TCC0_WO4 ((1UL) << 16) - -#define PIN_PB16G_TCC0_WO4 (48L) -#define MUX_PB16G_TCC0_WO4 (6L) -#define PINMUX_PB16G_TCC0_WO4 ((PIN_PB16G_TCC0_WO4 << 16) | MUX_PB16G_TCC0_WO4) -#define PORT_PB16G_TCC0_WO4 ((1UL) << 16) - -#define PIN_PB10F_TCC0_WO4 (42L) -#define MUX_PB10F_TCC0_WO4 (5L) -#define PINMUX_PB10F_TCC0_WO4 ((PIN_PB10F_TCC0_WO4 << 16) | MUX_PB10F_TCC0_WO4) -#define PORT_PB10F_TCC0_WO4 ((1UL) << 10) - -#define PIN_PC14F_TCC0_WO4 (78L) -#define MUX_PC14F_TCC0_WO4 (5L) -#define PINMUX_PC14F_TCC0_WO4 ((PIN_PC14F_TCC0_WO4 << 16) | MUX_PC14F_TCC0_WO4) -#define PORT_PC14F_TCC0_WO4 ((1UL) << 14) - -#define PIN_PC20F_TCC0_WO4 (84L) -#define MUX_PC20F_TCC0_WO4 (5L) -#define PINMUX_PC20F_TCC0_WO4 ((PIN_PC20F_TCC0_WO4 << 16) | MUX_PC20F_TCC0_WO4) -#define PORT_PC20F_TCC0_WO4 ((1UL) << 20) - -#define PIN_PA17G_TCC0_WO5 (17L) -#define MUX_PA17G_TCC0_WO5 (6L) -#define PINMUX_PA17G_TCC0_WO5 ((PIN_PA17G_TCC0_WO5 << 16) | MUX_PA17G_TCC0_WO5) -#define PORT_PA17G_TCC0_WO5 ((1UL) << 17) - -#define PIN_PB17G_TCC0_WO5 (49L) -#define MUX_PB17G_TCC0_WO5 (6L) -#define PINMUX_PB17G_TCC0_WO5 ((PIN_PB17G_TCC0_WO5 << 16) | MUX_PB17G_TCC0_WO5) -#define PORT_PB17G_TCC0_WO5 ((1UL) << 17) - -#define PIN_PB11F_TCC0_WO5 (43L) -#define MUX_PB11F_TCC0_WO5 (5L) -#define PINMUX_PB11F_TCC0_WO5 ((PIN_PB11F_TCC0_WO5 << 16) | MUX_PB11F_TCC0_WO5) -#define PORT_PB11F_TCC0_WO5 ((1UL) << 11) - -#define PIN_PC15F_TCC0_WO5 (79L) -#define MUX_PC15F_TCC0_WO5 (5L) -#define PINMUX_PC15F_TCC0_WO5 ((PIN_PC15F_TCC0_WO5 << 16) | MUX_PC15F_TCC0_WO5) -#define PORT_PC15F_TCC0_WO5 ((1UL) << 15) - -#define PIN_PC21F_TCC0_WO5 (85L) -#define MUX_PC21F_TCC0_WO5 (5L) -#define PINMUX_PC21F_TCC0_WO5 ((PIN_PC21F_TCC0_WO5 << 16) | MUX_PC21F_TCC0_WO5) -#define PORT_PC21F_TCC0_WO5 ((1UL) << 21) - -#define PIN_PA18G_TCC0_WO6 (18L) -#define MUX_PA18G_TCC0_WO6 (6L) -#define PINMUX_PA18G_TCC0_WO6 ((PIN_PA18G_TCC0_WO6 << 16) | MUX_PA18G_TCC0_WO6) -#define PORT_PA18G_TCC0_WO6 ((1UL) << 18) - -#define PIN_PB30G_TCC0_WO6 (62L) -#define MUX_PB30G_TCC0_WO6 (6L) -#define PINMUX_PB30G_TCC0_WO6 ((PIN_PB30G_TCC0_WO6 << 16) | MUX_PB30G_TCC0_WO6) -#define PORT_PB30G_TCC0_WO6 ((1UL) << 30) - -#define PIN_PA12F_TCC0_WO6 (12L) -#define MUX_PA12F_TCC0_WO6 (5L) -#define PINMUX_PA12F_TCC0_WO6 ((PIN_PA12F_TCC0_WO6 << 16) | MUX_PA12F_TCC0_WO6) -#define PORT_PA12F_TCC0_WO6 ((1UL) << 12) - -#define PIN_PA19G_TCC0_WO7 (19L) -#define MUX_PA19G_TCC0_WO7 (6L) -#define PINMUX_PA19G_TCC0_WO7 ((PIN_PA19G_TCC0_WO7 << 16) | MUX_PA19G_TCC0_WO7) -#define PORT_PA19G_TCC0_WO7 ((1UL) << 19) - -#define PIN_PB31G_TCC0_WO7 (63L) -#define MUX_PB31G_TCC0_WO7 (6L) -#define PINMUX_PB31G_TCC0_WO7 ((PIN_PB31G_TCC0_WO7 << 16) | MUX_PB31G_TCC0_WO7) -#define PORT_PB31G_TCC0_WO7 ((1UL) << 31) - -#define PIN_PA13F_TCC0_WO7 (13L) -#define MUX_PA13F_TCC0_WO7 (5L) -#define PINMUX_PA13F_TCC0_WO7 ((PIN_PA13F_TCC0_WO7 << 16) | MUX_PA13F_TCC0_WO7) -#define PORT_PA13F_TCC0_WO7 ((1UL) << 13) - -/* ========== PORT definition for TCC1 peripheral ========== */ -#define PIN_PB10G_TCC1_WO0 (42L) -#define MUX_PB10G_TCC1_WO0 (6L) -#define PINMUX_PB10G_TCC1_WO0 ((PIN_PB10G_TCC1_WO0 << 16) | MUX_PB10G_TCC1_WO0) -#define PORT_PB10G_TCC1_WO0 ((1UL) << 10) - -#define PIN_PC14G_TCC1_WO0 (78L) -#define MUX_PC14G_TCC1_WO0 (6L) -#define PINMUX_PC14G_TCC1_WO0 ((PIN_PC14G_TCC1_WO0 << 16) | MUX_PC14G_TCC1_WO0) -#define PORT_PC14G_TCC1_WO0 ((1UL) << 14) - -#define PIN_PA16F_TCC1_WO0 (16L) -#define MUX_PA16F_TCC1_WO0 (5L) -#define PINMUX_PA16F_TCC1_WO0 ((PIN_PA16F_TCC1_WO0 << 16) | MUX_PA16F_TCC1_WO0) -#define PORT_PA16F_TCC1_WO0 ((1UL) << 16) - -#define PIN_PB18F_TCC1_WO0 (50L) -#define MUX_PB18F_TCC1_WO0 (5L) -#define PINMUX_PB18F_TCC1_WO0 ((PIN_PB18F_TCC1_WO0 << 16) | MUX_PB18F_TCC1_WO0) -#define PORT_PB18F_TCC1_WO0 ((1UL) << 18) - -#define PIN_PB11G_TCC1_WO1 (43L) -#define MUX_PB11G_TCC1_WO1 (6L) -#define PINMUX_PB11G_TCC1_WO1 ((PIN_PB11G_TCC1_WO1 << 16) | MUX_PB11G_TCC1_WO1) -#define PORT_PB11G_TCC1_WO1 ((1UL) << 11) - -#define PIN_PC15G_TCC1_WO1 (79L) -#define MUX_PC15G_TCC1_WO1 (6L) -#define PINMUX_PC15G_TCC1_WO1 ((PIN_PC15G_TCC1_WO1 << 16) | MUX_PC15G_TCC1_WO1) -#define PORT_PC15G_TCC1_WO1 ((1UL) << 15) - -#define PIN_PA17F_TCC1_WO1 (17L) -#define MUX_PA17F_TCC1_WO1 (5L) -#define PINMUX_PA17F_TCC1_WO1 ((PIN_PA17F_TCC1_WO1 << 16) | MUX_PA17F_TCC1_WO1) -#define PORT_PA17F_TCC1_WO1 ((1UL) << 17) - -#define PIN_PB19F_TCC1_WO1 (51L) -#define MUX_PB19F_TCC1_WO1 (5L) -#define PINMUX_PB19F_TCC1_WO1 ((PIN_PB19F_TCC1_WO1 << 16) | MUX_PB19F_TCC1_WO1) -#define PORT_PB19F_TCC1_WO1 ((1UL) << 19) - -#define PIN_PA12G_TCC1_WO2 (12L) -#define MUX_PA12G_TCC1_WO2 (6L) -#define PINMUX_PA12G_TCC1_WO2 ((PIN_PA12G_TCC1_WO2 << 16) | MUX_PA12G_TCC1_WO2) -#define PORT_PA12G_TCC1_WO2 ((1UL) << 12) - -#define PIN_PA14G_TCC1_WO2 (14L) -#define MUX_PA14G_TCC1_WO2 (6L) -#define PINMUX_PA14G_TCC1_WO2 ((PIN_PA14G_TCC1_WO2 << 16) | MUX_PA14G_TCC1_WO2) -#define PORT_PA14G_TCC1_WO2 ((1UL) << 14) - -#define PIN_PA18F_TCC1_WO2 (18L) -#define MUX_PA18F_TCC1_WO2 (5L) -#define PINMUX_PA18F_TCC1_WO2 ((PIN_PA18F_TCC1_WO2 << 16) | MUX_PA18F_TCC1_WO2) -#define PORT_PA18F_TCC1_WO2 ((1UL) << 18) - -#define PIN_PB20F_TCC1_WO2 (52L) -#define MUX_PB20F_TCC1_WO2 (5L) -#define PINMUX_PB20F_TCC1_WO2 ((PIN_PB20F_TCC1_WO2 << 16) | MUX_PB20F_TCC1_WO2) -#define PORT_PB20F_TCC1_WO2 ((1UL) << 20) - -#define PIN_PA13G_TCC1_WO3 (13L) -#define MUX_PA13G_TCC1_WO3 (6L) -#define PINMUX_PA13G_TCC1_WO3 ((PIN_PA13G_TCC1_WO3 << 16) | MUX_PA13G_TCC1_WO3) -#define PORT_PA13G_TCC1_WO3 ((1UL) << 13) - -#define PIN_PA15G_TCC1_WO3 (15L) -#define MUX_PA15G_TCC1_WO3 (6L) -#define PINMUX_PA15G_TCC1_WO3 ((PIN_PA15G_TCC1_WO3 << 16) | MUX_PA15G_TCC1_WO3) -#define PORT_PA15G_TCC1_WO3 ((1UL) << 15) - -#define PIN_PA19F_TCC1_WO3 (19L) -#define MUX_PA19F_TCC1_WO3 (5L) -#define PINMUX_PA19F_TCC1_WO3 ((PIN_PA19F_TCC1_WO3 << 16) | MUX_PA19F_TCC1_WO3) -#define PORT_PA19F_TCC1_WO3 ((1UL) << 19) - -#define PIN_PB21F_TCC1_WO3 (53L) -#define MUX_PB21F_TCC1_WO3 (5L) -#define PINMUX_PB21F_TCC1_WO3 ((PIN_PB21F_TCC1_WO3 << 16) | MUX_PB21F_TCC1_WO3) -#define PORT_PB21F_TCC1_WO3 ((1UL) << 21) - -#define PIN_PA08G_TCC1_WO4 (8L) -#define MUX_PA08G_TCC1_WO4 (6L) -#define PINMUX_PA08G_TCC1_WO4 ((PIN_PA08G_TCC1_WO4 << 16) | MUX_PA08G_TCC1_WO4) -#define PORT_PA08G_TCC1_WO4 ((1UL) << 8) - -#define PIN_PC10G_TCC1_WO4 (74L) -#define MUX_PC10G_TCC1_WO4 (6L) -#define PINMUX_PC10G_TCC1_WO4 ((PIN_PC10G_TCC1_WO4 << 16) | MUX_PC10G_TCC1_WO4) -#define PORT_PC10G_TCC1_WO4 ((1UL) << 10) - -#define PIN_PA20F_TCC1_WO4 (20L) -#define MUX_PA20F_TCC1_WO4 (5L) -#define PINMUX_PA20F_TCC1_WO4 ((PIN_PA20F_TCC1_WO4 << 16) | MUX_PA20F_TCC1_WO4) -#define PORT_PA20F_TCC1_WO4 ((1UL) << 20) - -#define PIN_PA09G_TCC1_WO5 (9L) -#define MUX_PA09G_TCC1_WO5 (6L) -#define PINMUX_PA09G_TCC1_WO5 ((PIN_PA09G_TCC1_WO5 << 16) | MUX_PA09G_TCC1_WO5) -#define PORT_PA09G_TCC1_WO5 ((1UL) << 9) - -#define PIN_PC11G_TCC1_WO5 (75L) -#define MUX_PC11G_TCC1_WO5 (6L) -#define PINMUX_PC11G_TCC1_WO5 ((PIN_PC11G_TCC1_WO5 << 16) | MUX_PC11G_TCC1_WO5) -#define PORT_PC11G_TCC1_WO5 ((1UL) << 11) - -#define PIN_PA21F_TCC1_WO5 (21L) -#define MUX_PA21F_TCC1_WO5 (5L) -#define PINMUX_PA21F_TCC1_WO5 ((PIN_PA21F_TCC1_WO5 << 16) | MUX_PA21F_TCC1_WO5) -#define PORT_PA21F_TCC1_WO5 ((1UL) << 21) - -#define PIN_PA10G_TCC1_WO6 (10L) -#define MUX_PA10G_TCC1_WO6 (6L) -#define PINMUX_PA10G_TCC1_WO6 ((PIN_PA10G_TCC1_WO6 << 16) | MUX_PA10G_TCC1_WO6) -#define PORT_PA10G_TCC1_WO6 ((1UL) << 10) - -#define PIN_PC12G_TCC1_WO6 (76L) -#define MUX_PC12G_TCC1_WO6 (6L) -#define PINMUX_PC12G_TCC1_WO6 ((PIN_PC12G_TCC1_WO6 << 16) | MUX_PC12G_TCC1_WO6) -#define PORT_PC12G_TCC1_WO6 ((1UL) << 12) - -#define PIN_PA22F_TCC1_WO6 (22L) -#define MUX_PA22F_TCC1_WO6 (5L) -#define PINMUX_PA22F_TCC1_WO6 ((PIN_PA22F_TCC1_WO6 << 16) | MUX_PA22F_TCC1_WO6) -#define PORT_PA22F_TCC1_WO6 ((1UL) << 22) - -#define PIN_PA11G_TCC1_WO7 (11L) -#define MUX_PA11G_TCC1_WO7 (6L) -#define PINMUX_PA11G_TCC1_WO7 ((PIN_PA11G_TCC1_WO7 << 16) | MUX_PA11G_TCC1_WO7) -#define PORT_PA11G_TCC1_WO7 ((1UL) << 11) - -#define PIN_PC13G_TCC1_WO7 (77L) -#define MUX_PC13G_TCC1_WO7 (6L) -#define PINMUX_PC13G_TCC1_WO7 ((PIN_PC13G_TCC1_WO7 << 16) | MUX_PC13G_TCC1_WO7) -#define PORT_PC13G_TCC1_WO7 ((1UL) << 13) - -#define PIN_PA23F_TCC1_WO7 (23L) -#define MUX_PA23F_TCC1_WO7 (5L) -#define PINMUX_PA23F_TCC1_WO7 ((PIN_PA23F_TCC1_WO7 << 16) | MUX_PA23F_TCC1_WO7) -#define PORT_PA23F_TCC1_WO7 ((1UL) << 23) - -/* ========== PORT definition for TCC2 peripheral ========== */ -#define PIN_PA14F_TCC2_WO0 (14L) -#define MUX_PA14F_TCC2_WO0 (5L) -#define PINMUX_PA14F_TCC2_WO0 ((PIN_PA14F_TCC2_WO0 << 16) | MUX_PA14F_TCC2_WO0) -#define PORT_PA14F_TCC2_WO0 ((1UL) << 14) - -#define PIN_PA30F_TCC2_WO0 (30L) -#define MUX_PA30F_TCC2_WO0 (5L) -#define PINMUX_PA30F_TCC2_WO0 ((PIN_PA30F_TCC2_WO0 << 16) | MUX_PA30F_TCC2_WO0) -#define PORT_PA30F_TCC2_WO0 ((1UL) << 30) - -#define PIN_PA15F_TCC2_WO1 (15L) -#define MUX_PA15F_TCC2_WO1 (5L) -#define PINMUX_PA15F_TCC2_WO1 ((PIN_PA15F_TCC2_WO1 << 16) | MUX_PA15F_TCC2_WO1) -#define PORT_PA15F_TCC2_WO1 ((1UL) << 15) - -#define PIN_PA31F_TCC2_WO1 (31L) -#define MUX_PA31F_TCC2_WO1 (5L) -#define PINMUX_PA31F_TCC2_WO1 ((PIN_PA31F_TCC2_WO1 << 16) | MUX_PA31F_TCC2_WO1) -#define PORT_PA31F_TCC2_WO1 ((1UL) << 31) - -#define PIN_PA24F_TCC2_WO2 (24L) -#define MUX_PA24F_TCC2_WO2 (5L) -#define PINMUX_PA24F_TCC2_WO2 ((PIN_PA24F_TCC2_WO2 << 16) | MUX_PA24F_TCC2_WO2) -#define PORT_PA24F_TCC2_WO2 ((1UL) << 24) - -#define PIN_PB02F_TCC2_WO2 (34L) -#define MUX_PB02F_TCC2_WO2 (5L) -#define PINMUX_PB02F_TCC2_WO2 ((PIN_PB02F_TCC2_WO2 << 16) | MUX_PB02F_TCC2_WO2) -#define PORT_PB02F_TCC2_WO2 ((1UL) << 2) - -/* ========== PORT definition for TCC3 peripheral ========== */ -#define PIN_PB12F_TCC3_WO0 (44L) -#define MUX_PB12F_TCC3_WO0 (5L) -#define PINMUX_PB12F_TCC3_WO0 ((PIN_PB12F_TCC3_WO0 << 16) | MUX_PB12F_TCC3_WO0) -#define PORT_PB12F_TCC3_WO0 ((1UL) << 12) - -#define PIN_PB16F_TCC3_WO0 (48L) -#define MUX_PB16F_TCC3_WO0 (5L) -#define PINMUX_PB16F_TCC3_WO0 ((PIN_PB16F_TCC3_WO0 << 16) | MUX_PB16F_TCC3_WO0) -#define PORT_PB16F_TCC3_WO0 ((1UL) << 16) - -#define PIN_PB13F_TCC3_WO1 (45L) -#define MUX_PB13F_TCC3_WO1 (5L) -#define PINMUX_PB13F_TCC3_WO1 ((PIN_PB13F_TCC3_WO1 << 16) | MUX_PB13F_TCC3_WO1) -#define PORT_PB13F_TCC3_WO1 ((1UL) << 13) - -#define PIN_PB17F_TCC3_WO1 (49L) -#define MUX_PB17F_TCC3_WO1 (5L) -#define PINMUX_PB17F_TCC3_WO1 ((PIN_PB17F_TCC3_WO1 << 16) | MUX_PB17F_TCC3_WO1) -#define PORT_PB17F_TCC3_WO1 ((1UL) << 17) - -/* ========== PORT definition for TCC4 peripheral ========== */ -#define PIN_PB14F_TCC4_WO0 (46L) -#define MUX_PB14F_TCC4_WO0 (5L) -#define PINMUX_PB14F_TCC4_WO0 ((PIN_PB14F_TCC4_WO0 << 16) | MUX_PB14F_TCC4_WO0) -#define PORT_PB14F_TCC4_WO0 ((1UL) << 14) - -#define PIN_PB30F_TCC4_WO0 (62L) -#define MUX_PB30F_TCC4_WO0 (5L) -#define PINMUX_PB30F_TCC4_WO0 ((PIN_PB30F_TCC4_WO0 << 16) | MUX_PB30F_TCC4_WO0) -#define PORT_PB30F_TCC4_WO0 ((1UL) << 30) - -#define PIN_PB15F_TCC4_WO1 (47L) -#define MUX_PB15F_TCC4_WO1 (5L) -#define PINMUX_PB15F_TCC4_WO1 ((PIN_PB15F_TCC4_WO1 << 16) | MUX_PB15F_TCC4_WO1) -#define PORT_PB15F_TCC4_WO1 ((1UL) << 15) - -#define PIN_PB31F_TCC4_WO1 (63L) -#define MUX_PB31F_TCC4_WO1 (5L) -#define PINMUX_PB31F_TCC4_WO1 ((PIN_PB31F_TCC4_WO1 << 16) | MUX_PB31F_TCC4_WO1) -#define PORT_PB31F_TCC4_WO1 ((1UL) << 31) - -/* ========== PORT definition for USB peripheral ========== */ -#define PIN_PA24H_USB_DM (24L) -#define MUX_PA24H_USB_DM (7L) -#define PINMUX_PA24H_USB_DM ((PIN_PA24H_USB_DM << 16) | MUX_PA24H_USB_DM) -#define PORT_PA24H_USB_DM ((1UL) << 24) - -#define PIN_PA25H_USB_DP (25L) -#define MUX_PA25H_USB_DP (7L) -#define PINMUX_PA25H_USB_DP ((PIN_PA25H_USB_DP << 16) | MUX_PA25H_USB_DP) -#define PORT_PA25H_USB_DP ((1UL) << 25) - -#define PIN_PA23H_USB_SOF_1KHZ (23L) -#define MUX_PA23H_USB_SOF_1KHZ (7L) -#define PINMUX_PA23H_USB_SOF_1KHZ ((PIN_PA23H_USB_SOF_1KHZ << 16) | MUX_PA23H_USB_SOF_1KHZ) -#define PORT_PA23H_USB_SOF_1KHZ ((1UL) << 23) - -#define PIN_PB22H_USB_SOF_1KHZ (54L) -#define MUX_PB22H_USB_SOF_1KHZ (7L) -#define PINMUX_PB22H_USB_SOF_1KHZ ((PIN_PB22H_USB_SOF_1KHZ << 16) | MUX_PB22H_USB_SOF_1KHZ) -#define PORT_PB22H_USB_SOF_1KHZ ((1UL) << 22) - - - -#endif /* _SAME54N19A_GPIO_H_ */ - +/** + * \file + * + * \brief Peripheral I/O description for SAME54N19A + * + * Copyright (c) 2019 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAME54N19A_PIO_ +#define _SAME54N19A_PIO_ + +#define PIN_PA00 0 /**< \brief Pin Number for PA00 */ +#define PORT_PA00 (_UL_(1) << 0) /**< \brief PORT Mask for PA00 */ +#define PIN_PA01 1 /**< \brief Pin Number for PA01 */ +#define PORT_PA01 (_UL_(1) << 1) /**< \brief PORT Mask for PA01 */ +#define PIN_PA02 2 /**< \brief Pin Number for PA02 */ +#define PORT_PA02 (_UL_(1) << 2) /**< \brief PORT Mask for PA02 */ +#define PIN_PA03 3 /**< \brief Pin Number for PA03 */ +#define PORT_PA03 (_UL_(1) << 3) /**< \brief PORT Mask for PA03 */ +#define PIN_PA04 4 /**< \brief Pin Number for PA04 */ +#define PORT_PA04 (_UL_(1) << 4) /**< \brief PORT Mask for PA04 */ +#define PIN_PA05 5 /**< \brief Pin Number for PA05 */ +#define PORT_PA05 (_UL_(1) << 5) /**< \brief PORT Mask for PA05 */ +#define PIN_PA06 6 /**< \brief Pin Number for PA06 */ +#define PORT_PA06 (_UL_(1) << 6) /**< \brief PORT Mask for PA06 */ +#define PIN_PA07 7 /**< \brief Pin Number for PA07 */ +#define PORT_PA07 (_UL_(1) << 7) /**< \brief PORT Mask for PA07 */ +#define PIN_PA08 8 /**< \brief Pin Number for PA08 */ +#define PORT_PA08 (_UL_(1) << 8) /**< \brief PORT Mask for PA08 */ +#define PIN_PA09 9 /**< \brief Pin Number for PA09 */ +#define PORT_PA09 (_UL_(1) << 9) /**< \brief PORT Mask for PA09 */ +#define PIN_PA10 10 /**< \brief Pin Number for PA10 */ +#define PORT_PA10 (_UL_(1) << 10) /**< \brief PORT Mask for PA10 */ +#define PIN_PA11 11 /**< \brief Pin Number for PA11 */ +#define PORT_PA11 (_UL_(1) << 11) /**< \brief PORT Mask for PA11 */ +#define PIN_PA12 12 /**< \brief Pin Number for PA12 */ +#define PORT_PA12 (_UL_(1) << 12) /**< \brief PORT Mask for PA12 */ +#define PIN_PA13 13 /**< \brief Pin Number for PA13 */ +#define PORT_PA13 (_UL_(1) << 13) /**< \brief PORT Mask for PA13 */ +#define PIN_PA14 14 /**< \brief Pin Number for PA14 */ +#define PORT_PA14 (_UL_(1) << 14) /**< \brief PORT Mask for PA14 */ +#define PIN_PA15 15 /**< \brief Pin Number for PA15 */ +#define PORT_PA15 (_UL_(1) << 15) /**< \brief PORT Mask for PA15 */ +#define PIN_PA16 16 /**< \brief Pin Number for PA16 */ +#define PORT_PA16 (_UL_(1) << 16) /**< \brief PORT Mask for PA16 */ +#define PIN_PA17 17 /**< \brief Pin Number for PA17 */ +#define PORT_PA17 (_UL_(1) << 17) /**< \brief PORT Mask for PA17 */ +#define PIN_PA18 18 /**< \brief Pin Number for PA18 */ +#define PORT_PA18 (_UL_(1) << 18) /**< \brief PORT Mask for PA18 */ +#define PIN_PA19 19 /**< \brief Pin Number for PA19 */ +#define PORT_PA19 (_UL_(1) << 19) /**< \brief PORT Mask for PA19 */ +#define PIN_PA20 20 /**< \brief Pin Number for PA20 */ +#define PORT_PA20 (_UL_(1) << 20) /**< \brief PORT Mask for PA20 */ +#define PIN_PA21 21 /**< \brief Pin Number for PA21 */ +#define PORT_PA21 (_UL_(1) << 21) /**< \brief PORT Mask for PA21 */ +#define PIN_PA22 22 /**< \brief Pin Number for PA22 */ +#define PORT_PA22 (_UL_(1) << 22) /**< \brief PORT Mask for PA22 */ +#define PIN_PA23 23 /**< \brief Pin Number for PA23 */ +#define PORT_PA23 (_UL_(1) << 23) /**< \brief PORT Mask for PA23 */ +#define PIN_PA24 24 /**< \brief Pin Number for PA24 */ +#define PORT_PA24 (_UL_(1) << 24) /**< \brief PORT Mask for PA24 */ +#define PIN_PA25 25 /**< \brief Pin Number for PA25 */ +#define PORT_PA25 (_UL_(1) << 25) /**< \brief PORT Mask for PA25 */ +#define PIN_PA27 27 /**< \brief Pin Number for PA27 */ +#define PORT_PA27 (_UL_(1) << 27) /**< \brief PORT Mask for PA27 */ +#define PIN_PA30 30 /**< \brief Pin Number for PA30 */ +#define PORT_PA30 (_UL_(1) << 30) /**< \brief PORT Mask for PA30 */ +#define PIN_PA31 31 /**< \brief Pin Number for PA31 */ +#define PORT_PA31 (_UL_(1) << 31) /**< \brief PORT Mask for PA31 */ +#define PIN_PB00 32 /**< \brief Pin Number for PB00 */ +#define PORT_PB00 (_UL_(1) << 0) /**< \brief PORT Mask for PB00 */ +#define PIN_PB01 33 /**< \brief Pin Number for PB01 */ +#define PORT_PB01 (_UL_(1) << 1) /**< \brief PORT Mask for PB01 */ +#define PIN_PB02 34 /**< \brief Pin Number for PB02 */ +#define PORT_PB02 (_UL_(1) << 2) /**< \brief PORT Mask for PB02 */ +#define PIN_PB03 35 /**< \brief Pin Number for PB03 */ +#define PORT_PB03 (_UL_(1) << 3) /**< \brief PORT Mask for PB03 */ +#define PIN_PB04 36 /**< \brief Pin Number for PB04 */ +#define PORT_PB04 (_UL_(1) << 4) /**< \brief PORT Mask for PB04 */ +#define PIN_PB05 37 /**< \brief Pin Number for PB05 */ +#define PORT_PB05 (_UL_(1) << 5) /**< \brief PORT Mask for PB05 */ +#define PIN_PB06 38 /**< \brief Pin Number for PB06 */ +#define PORT_PB06 (_UL_(1) << 6) /**< \brief PORT Mask for PB06 */ +#define PIN_PB07 39 /**< \brief Pin Number for PB07 */ +#define PORT_PB07 (_UL_(1) << 7) /**< \brief PORT Mask for PB07 */ +#define PIN_PB08 40 /**< \brief Pin Number for PB08 */ +#define PORT_PB08 (_UL_(1) << 8) /**< \brief PORT Mask for PB08 */ +#define PIN_PB09 41 /**< \brief Pin Number for PB09 */ +#define PORT_PB09 (_UL_(1) << 9) /**< \brief PORT Mask for PB09 */ +#define PIN_PB10 42 /**< \brief Pin Number for PB10 */ +#define PORT_PB10 (_UL_(1) << 10) /**< \brief PORT Mask for PB10 */ +#define PIN_PB11 43 /**< \brief Pin Number for PB11 */ +#define PORT_PB11 (_UL_(1) << 11) /**< \brief PORT Mask for PB11 */ +#define PIN_PB12 44 /**< \brief Pin Number for PB12 */ +#define PORT_PB12 (_UL_(1) << 12) /**< \brief PORT Mask for PB12 */ +#define PIN_PB13 45 /**< \brief Pin Number for PB13 */ +#define PORT_PB13 (_UL_(1) << 13) /**< \brief PORT Mask for PB13 */ +#define PIN_PB14 46 /**< \brief Pin Number for PB14 */ +#define PORT_PB14 (_UL_(1) << 14) /**< \brief PORT Mask for PB14 */ +#define PIN_PB15 47 /**< \brief Pin Number for PB15 */ +#define PORT_PB15 (_UL_(1) << 15) /**< \brief PORT Mask for PB15 */ +#define PIN_PB16 48 /**< \brief Pin Number for PB16 */ +#define PORT_PB16 (_UL_(1) << 16) /**< \brief PORT Mask for PB16 */ +#define PIN_PB17 49 /**< \brief Pin Number for PB17 */ +#define PORT_PB17 (_UL_(1) << 17) /**< \brief PORT Mask for PB17 */ +#define PIN_PB18 50 /**< \brief Pin Number for PB18 */ +#define PORT_PB18 (_UL_(1) << 18) /**< \brief PORT Mask for PB18 */ +#define PIN_PB19 51 /**< \brief Pin Number for PB19 */ +#define PORT_PB19 (_UL_(1) << 19) /**< \brief PORT Mask for PB19 */ +#define PIN_PB20 52 /**< \brief Pin Number for PB20 */ +#define PORT_PB20 (_UL_(1) << 20) /**< \brief PORT Mask for PB20 */ +#define PIN_PB21 53 /**< \brief Pin Number for PB21 */ +#define PORT_PB21 (_UL_(1) << 21) /**< \brief PORT Mask for PB21 */ +#define PIN_PB22 54 /**< \brief Pin Number for PB22 */ +#define PORT_PB22 (_UL_(1) << 22) /**< \brief PORT Mask for PB22 */ +#define PIN_PB23 55 /**< \brief Pin Number for PB23 */ +#define PORT_PB23 (_UL_(1) << 23) /**< \brief PORT Mask for PB23 */ +#define PIN_PB24 56 /**< \brief Pin Number for PB24 */ +#define PORT_PB24 (_UL_(1) << 24) /**< \brief PORT Mask for PB24 */ +#define PIN_PB25 57 /**< \brief Pin Number for PB25 */ +#define PORT_PB25 (_UL_(1) << 25) /**< \brief PORT Mask for PB25 */ +#define PIN_PB30 62 /**< \brief Pin Number for PB30 */ +#define PORT_PB30 (_UL_(1) << 30) /**< \brief PORT Mask for PB30 */ +#define PIN_PB31 63 /**< \brief Pin Number for PB31 */ +#define PORT_PB31 (_UL_(1) << 31) /**< \brief PORT Mask for PB31 */ +#define PIN_PC00 64 /**< \brief Pin Number for PC00 */ +#define PORT_PC00 (_UL_(1) << 0) /**< \brief PORT Mask for PC00 */ +#define PIN_PC01 65 /**< \brief Pin Number for PC01 */ +#define PORT_PC01 (_UL_(1) << 1) /**< \brief PORT Mask for PC01 */ +#define PIN_PC02 66 /**< \brief Pin Number for PC02 */ +#define PORT_PC02 (_UL_(1) << 2) /**< \brief PORT Mask for PC02 */ +#define PIN_PC03 67 /**< \brief Pin Number for PC03 */ +#define PORT_PC03 (_UL_(1) << 3) /**< \brief PORT Mask for PC03 */ +#define PIN_PC05 69 /**< \brief Pin Number for PC05 */ +#define PORT_PC05 (_UL_(1) << 5) /**< \brief PORT Mask for PC05 */ +#define PIN_PC06 70 /**< \brief Pin Number for PC06 */ +#define PORT_PC06 (_UL_(1) << 6) /**< \brief PORT Mask for PC06 */ +#define PIN_PC07 71 /**< \brief Pin Number for PC07 */ +#define PORT_PC07 (_UL_(1) << 7) /**< \brief PORT Mask for PC07 */ +#define PIN_PC10 74 /**< \brief Pin Number for PC10 */ +#define PORT_PC10 (_UL_(1) << 10) /**< \brief PORT Mask for PC10 */ +#define PIN_PC11 75 /**< \brief Pin Number for PC11 */ +#define PORT_PC11 (_UL_(1) << 11) /**< \brief PORT Mask for PC11 */ +#define PIN_PC12 76 /**< \brief Pin Number for PC12 */ +#define PORT_PC12 (_UL_(1) << 12) /**< \brief PORT Mask for PC12 */ +#define PIN_PC13 77 /**< \brief Pin Number for PC13 */ +#define PORT_PC13 (_UL_(1) << 13) /**< \brief PORT Mask for PC13 */ +#define PIN_PC14 78 /**< \brief Pin Number for PC14 */ +#define PORT_PC14 (_UL_(1) << 14) /**< \brief PORT Mask for PC14 */ +#define PIN_PC15 79 /**< \brief Pin Number for PC15 */ +#define PORT_PC15 (_UL_(1) << 15) /**< \brief PORT Mask for PC15 */ +#define PIN_PC16 80 /**< \brief Pin Number for PC16 */ +#define PORT_PC16 (_UL_(1) << 16) /**< \brief PORT Mask for PC16 */ +#define PIN_PC17 81 /**< \brief Pin Number for PC17 */ +#define PORT_PC17 (_UL_(1) << 17) /**< \brief PORT Mask for PC17 */ +#define PIN_PC18 82 /**< \brief Pin Number for PC18 */ +#define PORT_PC18 (_UL_(1) << 18) /**< \brief PORT Mask for PC18 */ +#define PIN_PC19 83 /**< \brief Pin Number for PC19 */ +#define PORT_PC19 (_UL_(1) << 19) /**< \brief PORT Mask for PC19 */ +#define PIN_PC20 84 /**< \brief Pin Number for PC20 */ +#define PORT_PC20 (_UL_(1) << 20) /**< \brief PORT Mask for PC20 */ +#define PIN_PC21 85 /**< \brief Pin Number for PC21 */ +#define PORT_PC21 (_UL_(1) << 21) /**< \brief PORT Mask for PC21 */ +#define PIN_PC24 88 /**< \brief Pin Number for PC24 */ +#define PORT_PC24 (_UL_(1) << 24) /**< \brief PORT Mask for PC24 */ +#define PIN_PC25 89 /**< \brief Pin Number for PC25 */ +#define PORT_PC25 (_UL_(1) << 25) /**< \brief PORT Mask for PC25 */ +#define PIN_PC26 90 /**< \brief Pin Number for PC26 */ +#define PORT_PC26 (_UL_(1) << 26) /**< \brief PORT Mask for PC26 */ +#define PIN_PC27 91 /**< \brief Pin Number for PC27 */ +#define PORT_PC27 (_UL_(1) << 27) /**< \brief PORT Mask for PC27 */ +#define PIN_PC28 92 /**< \brief Pin Number for PC28 */ +#define PORT_PC28 (_UL_(1) << 28) /**< \brief PORT Mask for PC28 */ +/* ========== PORT definition for CM4 peripheral ========== */ +#define PIN_PA30H_CM4_SWCLK _L_(30) /**< \brief CM4 signal: SWCLK on PA30 mux H */ +#define MUX_PA30H_CM4_SWCLK _L_(7) +#define PINMUX_PA30H_CM4_SWCLK ((PIN_PA30H_CM4_SWCLK << 16) | MUX_PA30H_CM4_SWCLK) +#define PORT_PA30H_CM4_SWCLK (_UL_(1) << 30) +#define PIN_PC27M_CM4_SWO _L_(91) /**< \brief CM4 signal: SWO on PC27 mux M */ +#define MUX_PC27M_CM4_SWO _L_(12) +#define PINMUX_PC27M_CM4_SWO ((PIN_PC27M_CM4_SWO << 16) | MUX_PC27M_CM4_SWO) +#define PORT_PC27M_CM4_SWO (_UL_(1) << 27) +#define PIN_PB30H_CM4_SWO _L_(62) /**< \brief CM4 signal: SWO on PB30 mux H */ +#define MUX_PB30H_CM4_SWO _L_(7) +#define PINMUX_PB30H_CM4_SWO ((PIN_PB30H_CM4_SWO << 16) | MUX_PB30H_CM4_SWO) +#define PORT_PB30H_CM4_SWO (_UL_(1) << 30) +#define PIN_PC27H_CM4_TRACECLK _L_(91) /**< \brief CM4 signal: TRACECLK on PC27 mux H */ +#define MUX_PC27H_CM4_TRACECLK _L_(7) +#define PINMUX_PC27H_CM4_TRACECLK ((PIN_PC27H_CM4_TRACECLK << 16) | MUX_PC27H_CM4_TRACECLK) +#define PORT_PC27H_CM4_TRACECLK (_UL_(1) << 27) +#define PIN_PC28H_CM4_TRACEDATA0 _L_(92) /**< \brief CM4 signal: TRACEDATA0 on PC28 mux H */ +#define MUX_PC28H_CM4_TRACEDATA0 _L_(7) +#define PINMUX_PC28H_CM4_TRACEDATA0 ((PIN_PC28H_CM4_TRACEDATA0 << 16) | MUX_PC28H_CM4_TRACEDATA0) +#define PORT_PC28H_CM4_TRACEDATA0 (_UL_(1) << 28) +#define PIN_PC26H_CM4_TRACEDATA1 _L_(90) /**< \brief CM4 signal: TRACEDATA1 on PC26 mux H */ +#define MUX_PC26H_CM4_TRACEDATA1 _L_(7) +#define PINMUX_PC26H_CM4_TRACEDATA1 ((PIN_PC26H_CM4_TRACEDATA1 << 16) | MUX_PC26H_CM4_TRACEDATA1) +#define PORT_PC26H_CM4_TRACEDATA1 (_UL_(1) << 26) +#define PIN_PC25H_CM4_TRACEDATA2 _L_(89) /**< \brief CM4 signal: TRACEDATA2 on PC25 mux H */ +#define MUX_PC25H_CM4_TRACEDATA2 _L_(7) +#define PINMUX_PC25H_CM4_TRACEDATA2 ((PIN_PC25H_CM4_TRACEDATA2 << 16) | MUX_PC25H_CM4_TRACEDATA2) +#define PORT_PC25H_CM4_TRACEDATA2 (_UL_(1) << 25) +#define PIN_PC24H_CM4_TRACEDATA3 _L_(88) /**< \brief CM4 signal: TRACEDATA3 on PC24 mux H */ +#define MUX_PC24H_CM4_TRACEDATA3 _L_(7) +#define PINMUX_PC24H_CM4_TRACEDATA3 ((PIN_PC24H_CM4_TRACEDATA3 << 16) | MUX_PC24H_CM4_TRACEDATA3) +#define PORT_PC24H_CM4_TRACEDATA3 (_UL_(1) << 24) +/* ========== PORT definition for ANAREF peripheral ========== */ +#define PIN_PA03B_ANAREF_VREF0 _L_(3) /**< \brief ANAREF signal: VREF0 on PA03 mux B */ +#define MUX_PA03B_ANAREF_VREF0 _L_(1) +#define PINMUX_PA03B_ANAREF_VREF0 ((PIN_PA03B_ANAREF_VREF0 << 16) | MUX_PA03B_ANAREF_VREF0) +#define PORT_PA03B_ANAREF_VREF0 (_UL_(1) << 3) +#define PIN_PA04B_ANAREF_VREF1 _L_(4) /**< \brief ANAREF signal: VREF1 on PA04 mux B */ +#define MUX_PA04B_ANAREF_VREF1 _L_(1) +#define PINMUX_PA04B_ANAREF_VREF1 ((PIN_PA04B_ANAREF_VREF1 << 16) | MUX_PA04B_ANAREF_VREF1) +#define PORT_PA04B_ANAREF_VREF1 (_UL_(1) << 4) +#define PIN_PA06B_ANAREF_VREF2 _L_(6) /**< \brief ANAREF signal: VREF2 on PA06 mux B */ +#define MUX_PA06B_ANAREF_VREF2 _L_(1) +#define PINMUX_PA06B_ANAREF_VREF2 ((PIN_PA06B_ANAREF_VREF2 << 16) | MUX_PA06B_ANAREF_VREF2) +#define PORT_PA06B_ANAREF_VREF2 (_UL_(1) << 6) +/* ========== PORT definition for GCLK peripheral ========== */ +#define PIN_PA30M_GCLK_IO0 _L_(30) /**< \brief GCLK signal: IO0 on PA30 mux M */ +#define MUX_PA30M_GCLK_IO0 _L_(12) +#define PINMUX_PA30M_GCLK_IO0 ((PIN_PA30M_GCLK_IO0 << 16) | MUX_PA30M_GCLK_IO0) +#define PORT_PA30M_GCLK_IO0 (_UL_(1) << 30) +#define PIN_PB14M_GCLK_IO0 _L_(46) /**< \brief GCLK signal: IO0 on PB14 mux M */ +#define MUX_PB14M_GCLK_IO0 _L_(12) +#define PINMUX_PB14M_GCLK_IO0 ((PIN_PB14M_GCLK_IO0 << 16) | MUX_PB14M_GCLK_IO0) +#define PORT_PB14M_GCLK_IO0 (_UL_(1) << 14) +#define PIN_PA14M_GCLK_IO0 _L_(14) /**< \brief GCLK signal: IO0 on PA14 mux M */ +#define MUX_PA14M_GCLK_IO0 _L_(12) +#define PINMUX_PA14M_GCLK_IO0 ((PIN_PA14M_GCLK_IO0 << 16) | MUX_PA14M_GCLK_IO0) +#define PORT_PA14M_GCLK_IO0 (_UL_(1) << 14) +#define PIN_PB22M_GCLK_IO0 _L_(54) /**< \brief GCLK signal: IO0 on PB22 mux M */ +#define MUX_PB22M_GCLK_IO0 _L_(12) +#define PINMUX_PB22M_GCLK_IO0 ((PIN_PB22M_GCLK_IO0 << 16) | MUX_PB22M_GCLK_IO0) +#define PORT_PB22M_GCLK_IO0 (_UL_(1) << 22) +#define PIN_PB15M_GCLK_IO1 _L_(47) /**< \brief GCLK signal: IO1 on PB15 mux M */ +#define MUX_PB15M_GCLK_IO1 _L_(12) +#define PINMUX_PB15M_GCLK_IO1 ((PIN_PB15M_GCLK_IO1 << 16) | MUX_PB15M_GCLK_IO1) +#define PORT_PB15M_GCLK_IO1 (_UL_(1) << 15) +#define PIN_PA15M_GCLK_IO1 _L_(15) /**< \brief GCLK signal: IO1 on PA15 mux M */ +#define MUX_PA15M_GCLK_IO1 _L_(12) +#define PINMUX_PA15M_GCLK_IO1 ((PIN_PA15M_GCLK_IO1 << 16) | MUX_PA15M_GCLK_IO1) +#define PORT_PA15M_GCLK_IO1 (_UL_(1) << 15) +#define PIN_PB23M_GCLK_IO1 _L_(55) /**< \brief GCLK signal: IO1 on PB23 mux M */ +#define MUX_PB23M_GCLK_IO1 _L_(12) +#define PINMUX_PB23M_GCLK_IO1 ((PIN_PB23M_GCLK_IO1 << 16) | MUX_PB23M_GCLK_IO1) +#define PORT_PB23M_GCLK_IO1 (_UL_(1) << 23) +#define PIN_PA27M_GCLK_IO1 _L_(27) /**< \brief GCLK signal: IO1 on PA27 mux M */ +#define MUX_PA27M_GCLK_IO1 _L_(12) +#define PINMUX_PA27M_GCLK_IO1 ((PIN_PA27M_GCLK_IO1 << 16) | MUX_PA27M_GCLK_IO1) +#define PORT_PA27M_GCLK_IO1 (_UL_(1) << 27) +#define PIN_PA16M_GCLK_IO2 _L_(16) /**< \brief GCLK signal: IO2 on PA16 mux M */ +#define MUX_PA16M_GCLK_IO2 _L_(12) +#define PINMUX_PA16M_GCLK_IO2 ((PIN_PA16M_GCLK_IO2 << 16) | MUX_PA16M_GCLK_IO2) +#define PORT_PA16M_GCLK_IO2 (_UL_(1) << 16) +#define PIN_PB16M_GCLK_IO2 _L_(48) /**< \brief GCLK signal: IO2 on PB16 mux M */ +#define MUX_PB16M_GCLK_IO2 _L_(12) +#define PINMUX_PB16M_GCLK_IO2 ((PIN_PB16M_GCLK_IO2 << 16) | MUX_PB16M_GCLK_IO2) +#define PORT_PB16M_GCLK_IO2 (_UL_(1) << 16) +#define PIN_PA17M_GCLK_IO3 _L_(17) /**< \brief GCLK signal: IO3 on PA17 mux M */ +#define MUX_PA17M_GCLK_IO3 _L_(12) +#define PINMUX_PA17M_GCLK_IO3 ((PIN_PA17M_GCLK_IO3 << 16) | MUX_PA17M_GCLK_IO3) +#define PORT_PA17M_GCLK_IO3 (_UL_(1) << 17) +#define PIN_PB17M_GCLK_IO3 _L_(49) /**< \brief GCLK signal: IO3 on PB17 mux M */ +#define MUX_PB17M_GCLK_IO3 _L_(12) +#define PINMUX_PB17M_GCLK_IO3 ((PIN_PB17M_GCLK_IO3 << 16) | MUX_PB17M_GCLK_IO3) +#define PORT_PB17M_GCLK_IO3 (_UL_(1) << 17) +#define PIN_PA10M_GCLK_IO4 _L_(10) /**< \brief GCLK signal: IO4 on PA10 mux M */ +#define MUX_PA10M_GCLK_IO4 _L_(12) +#define PINMUX_PA10M_GCLK_IO4 ((PIN_PA10M_GCLK_IO4 << 16) | MUX_PA10M_GCLK_IO4) +#define PORT_PA10M_GCLK_IO4 (_UL_(1) << 10) +#define PIN_PB10M_GCLK_IO4 _L_(42) /**< \brief GCLK signal: IO4 on PB10 mux M */ +#define MUX_PB10M_GCLK_IO4 _L_(12) +#define PINMUX_PB10M_GCLK_IO4 ((PIN_PB10M_GCLK_IO4 << 16) | MUX_PB10M_GCLK_IO4) +#define PORT_PB10M_GCLK_IO4 (_UL_(1) << 10) +#define PIN_PB18M_GCLK_IO4 _L_(50) /**< \brief GCLK signal: IO4 on PB18 mux M */ +#define MUX_PB18M_GCLK_IO4 _L_(12) +#define PINMUX_PB18M_GCLK_IO4 ((PIN_PB18M_GCLK_IO4 << 16) | MUX_PB18M_GCLK_IO4) +#define PORT_PB18M_GCLK_IO4 (_UL_(1) << 18) +#define PIN_PA11M_GCLK_IO5 _L_(11) /**< \brief GCLK signal: IO5 on PA11 mux M */ +#define MUX_PA11M_GCLK_IO5 _L_(12) +#define PINMUX_PA11M_GCLK_IO5 ((PIN_PA11M_GCLK_IO5 << 16) | MUX_PA11M_GCLK_IO5) +#define PORT_PA11M_GCLK_IO5 (_UL_(1) << 11) +#define PIN_PB11M_GCLK_IO5 _L_(43) /**< \brief GCLK signal: IO5 on PB11 mux M */ +#define MUX_PB11M_GCLK_IO5 _L_(12) +#define PINMUX_PB11M_GCLK_IO5 ((PIN_PB11M_GCLK_IO5 << 16) | MUX_PB11M_GCLK_IO5) +#define PORT_PB11M_GCLK_IO5 (_UL_(1) << 11) +#define PIN_PB19M_GCLK_IO5 _L_(51) /**< \brief GCLK signal: IO5 on PB19 mux M */ +#define MUX_PB19M_GCLK_IO5 _L_(12) +#define PINMUX_PB19M_GCLK_IO5 ((PIN_PB19M_GCLK_IO5 << 16) | MUX_PB19M_GCLK_IO5) +#define PORT_PB19M_GCLK_IO5 (_UL_(1) << 19) +#define PIN_PB12M_GCLK_IO6 _L_(44) /**< \brief GCLK signal: IO6 on PB12 mux M */ +#define MUX_PB12M_GCLK_IO6 _L_(12) +#define PINMUX_PB12M_GCLK_IO6 ((PIN_PB12M_GCLK_IO6 << 16) | MUX_PB12M_GCLK_IO6) +#define PORT_PB12M_GCLK_IO6 (_UL_(1) << 12) +#define PIN_PB20M_GCLK_IO6 _L_(52) /**< \brief GCLK signal: IO6 on PB20 mux M */ +#define MUX_PB20M_GCLK_IO6 _L_(12) +#define PINMUX_PB20M_GCLK_IO6 ((PIN_PB20M_GCLK_IO6 << 16) | MUX_PB20M_GCLK_IO6) +#define PORT_PB20M_GCLK_IO6 (_UL_(1) << 20) +#define PIN_PB13M_GCLK_IO7 _L_(45) /**< \brief GCLK signal: IO7 on PB13 mux M */ +#define MUX_PB13M_GCLK_IO7 _L_(12) +#define PINMUX_PB13M_GCLK_IO7 ((PIN_PB13M_GCLK_IO7 << 16) | MUX_PB13M_GCLK_IO7) +#define PORT_PB13M_GCLK_IO7 (_UL_(1) << 13) +#define PIN_PB21M_GCLK_IO7 _L_(53) /**< \brief GCLK signal: IO7 on PB21 mux M */ +#define MUX_PB21M_GCLK_IO7 _L_(12) +#define PINMUX_PB21M_GCLK_IO7 ((PIN_PB21M_GCLK_IO7 << 16) | MUX_PB21M_GCLK_IO7) +#define PORT_PB21M_GCLK_IO7 (_UL_(1) << 21) +/* ========== PORT definition for EIC peripheral ========== */ +#define PIN_PA00A_EIC_EXTINT0 _L_(0) /**< \brief EIC signal: EXTINT0 on PA00 mux A */ +#define MUX_PA00A_EIC_EXTINT0 _L_(0) +#define PINMUX_PA00A_EIC_EXTINT0 ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0) +#define PORT_PA00A_EIC_EXTINT0 (_UL_(1) << 0) +#define PIN_PA00A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PA00 External Interrupt Line */ +#define PIN_PA16A_EIC_EXTINT0 _L_(16) /**< \brief EIC signal: EXTINT0 on PA16 mux A */ +#define MUX_PA16A_EIC_EXTINT0 _L_(0) +#define PINMUX_PA16A_EIC_EXTINT0 ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0) +#define PORT_PA16A_EIC_EXTINT0 (_UL_(1) << 16) +#define PIN_PA16A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PA16 External Interrupt Line */ +#define PIN_PB00A_EIC_EXTINT0 _L_(32) /**< \brief EIC signal: EXTINT0 on PB00 mux A */ +#define MUX_PB00A_EIC_EXTINT0 _L_(0) +#define PINMUX_PB00A_EIC_EXTINT0 ((PIN_PB00A_EIC_EXTINT0 << 16) | MUX_PB00A_EIC_EXTINT0) +#define PORT_PB00A_EIC_EXTINT0 (_UL_(1) << 0) +#define PIN_PB00A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PB00 External Interrupt Line */ +#define PIN_PB16A_EIC_EXTINT0 _L_(48) /**< \brief EIC signal: EXTINT0 on PB16 mux A */ +#define MUX_PB16A_EIC_EXTINT0 _L_(0) +#define PINMUX_PB16A_EIC_EXTINT0 ((PIN_PB16A_EIC_EXTINT0 << 16) | MUX_PB16A_EIC_EXTINT0) +#define PORT_PB16A_EIC_EXTINT0 (_UL_(1) << 16) +#define PIN_PB16A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PB16 External Interrupt Line */ +#define PIN_PC00A_EIC_EXTINT0 _L_(64) /**< \brief EIC signal: EXTINT0 on PC00 mux A */ +#define MUX_PC00A_EIC_EXTINT0 _L_(0) +#define PINMUX_PC00A_EIC_EXTINT0 ((PIN_PC00A_EIC_EXTINT0 << 16) | MUX_PC00A_EIC_EXTINT0) +#define PORT_PC00A_EIC_EXTINT0 (_UL_(1) << 0) +#define PIN_PC00A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PC00 External Interrupt Line */ +#define PIN_PC16A_EIC_EXTINT0 _L_(80) /**< \brief EIC signal: EXTINT0 on PC16 mux A */ +#define MUX_PC16A_EIC_EXTINT0 _L_(0) +#define PINMUX_PC16A_EIC_EXTINT0 ((PIN_PC16A_EIC_EXTINT0 << 16) | MUX_PC16A_EIC_EXTINT0) +#define PORT_PC16A_EIC_EXTINT0 (_UL_(1) << 16) +#define PIN_PC16A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PC16 External Interrupt Line */ +#define PIN_PA01A_EIC_EXTINT1 _L_(1) /**< \brief EIC signal: EXTINT1 on PA01 mux A */ +#define MUX_PA01A_EIC_EXTINT1 _L_(0) +#define PINMUX_PA01A_EIC_EXTINT1 ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1) +#define PORT_PA01A_EIC_EXTINT1 (_UL_(1) << 1) +#define PIN_PA01A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PA01 External Interrupt Line */ +#define PIN_PA17A_EIC_EXTINT1 _L_(17) /**< \brief EIC signal: EXTINT1 on PA17 mux A */ +#define MUX_PA17A_EIC_EXTINT1 _L_(0) +#define PINMUX_PA17A_EIC_EXTINT1 ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1) +#define PORT_PA17A_EIC_EXTINT1 (_UL_(1) << 17) +#define PIN_PA17A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PA17 External Interrupt Line */ +#define PIN_PB01A_EIC_EXTINT1 _L_(33) /**< \brief EIC signal: EXTINT1 on PB01 mux A */ +#define MUX_PB01A_EIC_EXTINT1 _L_(0) +#define PINMUX_PB01A_EIC_EXTINT1 ((PIN_PB01A_EIC_EXTINT1 << 16) | MUX_PB01A_EIC_EXTINT1) +#define PORT_PB01A_EIC_EXTINT1 (_UL_(1) << 1) +#define PIN_PB01A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PB01 External Interrupt Line */ +#define PIN_PB17A_EIC_EXTINT1 _L_(49) /**< \brief EIC signal: EXTINT1 on PB17 mux A */ +#define MUX_PB17A_EIC_EXTINT1 _L_(0) +#define PINMUX_PB17A_EIC_EXTINT1 ((PIN_PB17A_EIC_EXTINT1 << 16) | MUX_PB17A_EIC_EXTINT1) +#define PORT_PB17A_EIC_EXTINT1 (_UL_(1) << 17) +#define PIN_PB17A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PB17 External Interrupt Line */ +#define PIN_PC01A_EIC_EXTINT1 _L_(65) /**< \brief EIC signal: EXTINT1 on PC01 mux A */ +#define MUX_PC01A_EIC_EXTINT1 _L_(0) +#define PINMUX_PC01A_EIC_EXTINT1 ((PIN_PC01A_EIC_EXTINT1 << 16) | MUX_PC01A_EIC_EXTINT1) +#define PORT_PC01A_EIC_EXTINT1 (_UL_(1) << 1) +#define PIN_PC01A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PC01 External Interrupt Line */ +#define PIN_PC17A_EIC_EXTINT1 _L_(81) /**< \brief EIC signal: EXTINT1 on PC17 mux A */ +#define MUX_PC17A_EIC_EXTINT1 _L_(0) +#define PINMUX_PC17A_EIC_EXTINT1 ((PIN_PC17A_EIC_EXTINT1 << 16) | MUX_PC17A_EIC_EXTINT1) +#define PORT_PC17A_EIC_EXTINT1 (_UL_(1) << 17) +#define PIN_PC17A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PC17 External Interrupt Line */ +#define PIN_PA02A_EIC_EXTINT2 _L_(2) /**< \brief EIC signal: EXTINT2 on PA02 mux A */ +#define MUX_PA02A_EIC_EXTINT2 _L_(0) +#define PINMUX_PA02A_EIC_EXTINT2 ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2) +#define PORT_PA02A_EIC_EXTINT2 (_UL_(1) << 2) +#define PIN_PA02A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PA02 External Interrupt Line */ +#define PIN_PA18A_EIC_EXTINT2 _L_(18) /**< \brief EIC signal: EXTINT2 on PA18 mux A */ +#define MUX_PA18A_EIC_EXTINT2 _L_(0) +#define PINMUX_PA18A_EIC_EXTINT2 ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2) +#define PORT_PA18A_EIC_EXTINT2 (_UL_(1) << 18) +#define PIN_PA18A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PA18 External Interrupt Line */ +#define PIN_PB02A_EIC_EXTINT2 _L_(34) /**< \brief EIC signal: EXTINT2 on PB02 mux A */ +#define MUX_PB02A_EIC_EXTINT2 _L_(0) +#define PINMUX_PB02A_EIC_EXTINT2 ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2) +#define PORT_PB02A_EIC_EXTINT2 (_UL_(1) << 2) +#define PIN_PB02A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PB02 External Interrupt Line */ +#define PIN_PB18A_EIC_EXTINT2 _L_(50) /**< \brief EIC signal: EXTINT2 on PB18 mux A */ +#define MUX_PB18A_EIC_EXTINT2 _L_(0) +#define PINMUX_PB18A_EIC_EXTINT2 ((PIN_PB18A_EIC_EXTINT2 << 16) | MUX_PB18A_EIC_EXTINT2) +#define PORT_PB18A_EIC_EXTINT2 (_UL_(1) << 18) +#define PIN_PB18A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PB18 External Interrupt Line */ +#define PIN_PC02A_EIC_EXTINT2 _L_(66) /**< \brief EIC signal: EXTINT2 on PC02 mux A */ +#define MUX_PC02A_EIC_EXTINT2 _L_(0) +#define PINMUX_PC02A_EIC_EXTINT2 ((PIN_PC02A_EIC_EXTINT2 << 16) | MUX_PC02A_EIC_EXTINT2) +#define PORT_PC02A_EIC_EXTINT2 (_UL_(1) << 2) +#define PIN_PC02A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PC02 External Interrupt Line */ +#define PIN_PC18A_EIC_EXTINT2 _L_(82) /**< \brief EIC signal: EXTINT2 on PC18 mux A */ +#define MUX_PC18A_EIC_EXTINT2 _L_(0) +#define PINMUX_PC18A_EIC_EXTINT2 ((PIN_PC18A_EIC_EXTINT2 << 16) | MUX_PC18A_EIC_EXTINT2) +#define PORT_PC18A_EIC_EXTINT2 (_UL_(1) << 18) +#define PIN_PC18A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PC18 External Interrupt Line */ +#define PIN_PA03A_EIC_EXTINT3 _L_(3) /**< \brief EIC signal: EXTINT3 on PA03 mux A */ +#define MUX_PA03A_EIC_EXTINT3 _L_(0) +#define PINMUX_PA03A_EIC_EXTINT3 ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3) +#define PORT_PA03A_EIC_EXTINT3 (_UL_(1) << 3) +#define PIN_PA03A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PA03 External Interrupt Line */ +#define PIN_PA19A_EIC_EXTINT3 _L_(19) /**< \brief EIC signal: EXTINT3 on PA19 mux A */ +#define MUX_PA19A_EIC_EXTINT3 _L_(0) +#define PINMUX_PA19A_EIC_EXTINT3 ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3) +#define PORT_PA19A_EIC_EXTINT3 (_UL_(1) << 19) +#define PIN_PA19A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PA19 External Interrupt Line */ +#define PIN_PB03A_EIC_EXTINT3 _L_(35) /**< \brief EIC signal: EXTINT3 on PB03 mux A */ +#define MUX_PB03A_EIC_EXTINT3 _L_(0) +#define PINMUX_PB03A_EIC_EXTINT3 ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3) +#define PORT_PB03A_EIC_EXTINT3 (_UL_(1) << 3) +#define PIN_PB03A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PB03 External Interrupt Line */ +#define PIN_PB19A_EIC_EXTINT3 _L_(51) /**< \brief EIC signal: EXTINT3 on PB19 mux A */ +#define MUX_PB19A_EIC_EXTINT3 _L_(0) +#define PINMUX_PB19A_EIC_EXTINT3 ((PIN_PB19A_EIC_EXTINT3 << 16) | MUX_PB19A_EIC_EXTINT3) +#define PORT_PB19A_EIC_EXTINT3 (_UL_(1) << 19) +#define PIN_PB19A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PB19 External Interrupt Line */ +#define PIN_PC03A_EIC_EXTINT3 _L_(67) /**< \brief EIC signal: EXTINT3 on PC03 mux A */ +#define MUX_PC03A_EIC_EXTINT3 _L_(0) +#define PINMUX_PC03A_EIC_EXTINT3 ((PIN_PC03A_EIC_EXTINT3 << 16) | MUX_PC03A_EIC_EXTINT3) +#define PORT_PC03A_EIC_EXTINT3 (_UL_(1) << 3) +#define PIN_PC03A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PC03 External Interrupt Line */ +#define PIN_PC19A_EIC_EXTINT3 _L_(83) /**< \brief EIC signal: EXTINT3 on PC19 mux A */ +#define MUX_PC19A_EIC_EXTINT3 _L_(0) +#define PINMUX_PC19A_EIC_EXTINT3 ((PIN_PC19A_EIC_EXTINT3 << 16) | MUX_PC19A_EIC_EXTINT3) +#define PORT_PC19A_EIC_EXTINT3 (_UL_(1) << 19) +#define PIN_PC19A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PC19 External Interrupt Line */ +#define PIN_PA04A_EIC_EXTINT4 _L_(4) /**< \brief EIC signal: EXTINT4 on PA04 mux A */ +#define MUX_PA04A_EIC_EXTINT4 _L_(0) +#define PINMUX_PA04A_EIC_EXTINT4 ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4) +#define PORT_PA04A_EIC_EXTINT4 (_UL_(1) << 4) +#define PIN_PA04A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PA04 External Interrupt Line */ +#define PIN_PA20A_EIC_EXTINT4 _L_(20) /**< \brief EIC signal: EXTINT4 on PA20 mux A */ +#define MUX_PA20A_EIC_EXTINT4 _L_(0) +#define PINMUX_PA20A_EIC_EXTINT4 ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4) +#define PORT_PA20A_EIC_EXTINT4 (_UL_(1) << 20) +#define PIN_PA20A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PA20 External Interrupt Line */ +#define PIN_PB04A_EIC_EXTINT4 _L_(36) /**< \brief EIC signal: EXTINT4 on PB04 mux A */ +#define MUX_PB04A_EIC_EXTINT4 _L_(0) +#define PINMUX_PB04A_EIC_EXTINT4 ((PIN_PB04A_EIC_EXTINT4 << 16) | MUX_PB04A_EIC_EXTINT4) +#define PORT_PB04A_EIC_EXTINT4 (_UL_(1) << 4) +#define PIN_PB04A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PB04 External Interrupt Line */ +#define PIN_PB20A_EIC_EXTINT4 _L_(52) /**< \brief EIC signal: EXTINT4 on PB20 mux A */ +#define MUX_PB20A_EIC_EXTINT4 _L_(0) +#define PINMUX_PB20A_EIC_EXTINT4 ((PIN_PB20A_EIC_EXTINT4 << 16) | MUX_PB20A_EIC_EXTINT4) +#define PORT_PB20A_EIC_EXTINT4 (_UL_(1) << 20) +#define PIN_PB20A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PB20 External Interrupt Line */ +#define PIN_PC20A_EIC_EXTINT4 _L_(84) /**< \brief EIC signal: EXTINT4 on PC20 mux A */ +#define MUX_PC20A_EIC_EXTINT4 _L_(0) +#define PINMUX_PC20A_EIC_EXTINT4 ((PIN_PC20A_EIC_EXTINT4 << 16) | MUX_PC20A_EIC_EXTINT4) +#define PORT_PC20A_EIC_EXTINT4 (_UL_(1) << 20) +#define PIN_PC20A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PC20 External Interrupt Line */ +#define PIN_PA05A_EIC_EXTINT5 _L_(5) /**< \brief EIC signal: EXTINT5 on PA05 mux A */ +#define MUX_PA05A_EIC_EXTINT5 _L_(0) +#define PINMUX_PA05A_EIC_EXTINT5 ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5) +#define PORT_PA05A_EIC_EXTINT5 (_UL_(1) << 5) +#define PIN_PA05A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PA05 External Interrupt Line */ +#define PIN_PA21A_EIC_EXTINT5 _L_(21) /**< \brief EIC signal: EXTINT5 on PA21 mux A */ +#define MUX_PA21A_EIC_EXTINT5 _L_(0) +#define PINMUX_PA21A_EIC_EXTINT5 ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5) +#define PORT_PA21A_EIC_EXTINT5 (_UL_(1) << 21) +#define PIN_PA21A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PA21 External Interrupt Line */ +#define PIN_PB05A_EIC_EXTINT5 _L_(37) /**< \brief EIC signal: EXTINT5 on PB05 mux A */ +#define MUX_PB05A_EIC_EXTINT5 _L_(0) +#define PINMUX_PB05A_EIC_EXTINT5 ((PIN_PB05A_EIC_EXTINT5 << 16) | MUX_PB05A_EIC_EXTINT5) +#define PORT_PB05A_EIC_EXTINT5 (_UL_(1) << 5) +#define PIN_PB05A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PB05 External Interrupt Line */ +#define PIN_PB21A_EIC_EXTINT5 _L_(53) /**< \brief EIC signal: EXTINT5 on PB21 mux A */ +#define MUX_PB21A_EIC_EXTINT5 _L_(0) +#define PINMUX_PB21A_EIC_EXTINT5 ((PIN_PB21A_EIC_EXTINT5 << 16) | MUX_PB21A_EIC_EXTINT5) +#define PORT_PB21A_EIC_EXTINT5 (_UL_(1) << 21) +#define PIN_PB21A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PB21 External Interrupt Line */ +#define PIN_PC05A_EIC_EXTINT5 _L_(69) /**< \brief EIC signal: EXTINT5 on PC05 mux A */ +#define MUX_PC05A_EIC_EXTINT5 _L_(0) +#define PINMUX_PC05A_EIC_EXTINT5 ((PIN_PC05A_EIC_EXTINT5 << 16) | MUX_PC05A_EIC_EXTINT5) +#define PORT_PC05A_EIC_EXTINT5 (_UL_(1) << 5) +#define PIN_PC05A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PC05 External Interrupt Line */ +#define PIN_PC21A_EIC_EXTINT5 _L_(85) /**< \brief EIC signal: EXTINT5 on PC21 mux A */ +#define MUX_PC21A_EIC_EXTINT5 _L_(0) +#define PINMUX_PC21A_EIC_EXTINT5 ((PIN_PC21A_EIC_EXTINT5 << 16) | MUX_PC21A_EIC_EXTINT5) +#define PORT_PC21A_EIC_EXTINT5 (_UL_(1) << 21) +#define PIN_PC21A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PC21 External Interrupt Line */ +#define PIN_PA06A_EIC_EXTINT6 _L_(6) /**< \brief EIC signal: EXTINT6 on PA06 mux A */ +#define MUX_PA06A_EIC_EXTINT6 _L_(0) +#define PINMUX_PA06A_EIC_EXTINT6 ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6) +#define PORT_PA06A_EIC_EXTINT6 (_UL_(1) << 6) +#define PIN_PA06A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PA06 External Interrupt Line */ +#define PIN_PA22A_EIC_EXTINT6 _L_(22) /**< \brief EIC signal: EXTINT6 on PA22 mux A */ +#define MUX_PA22A_EIC_EXTINT6 _L_(0) +#define PINMUX_PA22A_EIC_EXTINT6 ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6) +#define PORT_PA22A_EIC_EXTINT6 (_UL_(1) << 22) +#define PIN_PA22A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PA22 External Interrupt Line */ +#define PIN_PB06A_EIC_EXTINT6 _L_(38) /**< \brief EIC signal: EXTINT6 on PB06 mux A */ +#define MUX_PB06A_EIC_EXTINT6 _L_(0) +#define PINMUX_PB06A_EIC_EXTINT6 ((PIN_PB06A_EIC_EXTINT6 << 16) | MUX_PB06A_EIC_EXTINT6) +#define PORT_PB06A_EIC_EXTINT6 (_UL_(1) << 6) +#define PIN_PB06A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PB06 External Interrupt Line */ +#define PIN_PB22A_EIC_EXTINT6 _L_(54) /**< \brief EIC signal: EXTINT6 on PB22 mux A */ +#define MUX_PB22A_EIC_EXTINT6 _L_(0) +#define PINMUX_PB22A_EIC_EXTINT6 ((PIN_PB22A_EIC_EXTINT6 << 16) | MUX_PB22A_EIC_EXTINT6) +#define PORT_PB22A_EIC_EXTINT6 (_UL_(1) << 22) +#define PIN_PB22A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PB22 External Interrupt Line */ +#define PIN_PC06A_EIC_EXTINT6 _L_(70) /**< \brief EIC signal: EXTINT6 on PC06 mux A */ +#define MUX_PC06A_EIC_EXTINT6 _L_(0) +#define PINMUX_PC06A_EIC_EXTINT6 ((PIN_PC06A_EIC_EXTINT6 << 16) | MUX_PC06A_EIC_EXTINT6) +#define PORT_PC06A_EIC_EXTINT6 (_UL_(1) << 6) +#define PIN_PC06A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PC06 External Interrupt Line */ +#define PIN_PA07A_EIC_EXTINT7 _L_(7) /**< \brief EIC signal: EXTINT7 on PA07 mux A */ +#define MUX_PA07A_EIC_EXTINT7 _L_(0) +#define PINMUX_PA07A_EIC_EXTINT7 ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7) +#define PORT_PA07A_EIC_EXTINT7 (_UL_(1) << 7) +#define PIN_PA07A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PA07 External Interrupt Line */ +#define PIN_PA23A_EIC_EXTINT7 _L_(23) /**< \brief EIC signal: EXTINT7 on PA23 mux A */ +#define MUX_PA23A_EIC_EXTINT7 _L_(0) +#define PINMUX_PA23A_EIC_EXTINT7 ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7) +#define PORT_PA23A_EIC_EXTINT7 (_UL_(1) << 23) +#define PIN_PA23A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PA23 External Interrupt Line */ +#define PIN_PB07A_EIC_EXTINT7 _L_(39) /**< \brief EIC signal: EXTINT7 on PB07 mux A */ +#define MUX_PB07A_EIC_EXTINT7 _L_(0) +#define PINMUX_PB07A_EIC_EXTINT7 ((PIN_PB07A_EIC_EXTINT7 << 16) | MUX_PB07A_EIC_EXTINT7) +#define PORT_PB07A_EIC_EXTINT7 (_UL_(1) << 7) +#define PIN_PB07A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PB07 External Interrupt Line */ +#define PIN_PB23A_EIC_EXTINT7 _L_(55) /**< \brief EIC signal: EXTINT7 on PB23 mux A */ +#define MUX_PB23A_EIC_EXTINT7 _L_(0) +#define PINMUX_PB23A_EIC_EXTINT7 ((PIN_PB23A_EIC_EXTINT7 << 16) | MUX_PB23A_EIC_EXTINT7) +#define PORT_PB23A_EIC_EXTINT7 (_UL_(1) << 23) +#define PIN_PB23A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PB23 External Interrupt Line */ +#define PIN_PA24A_EIC_EXTINT8 _L_(24) /**< \brief EIC signal: EXTINT8 on PA24 mux A */ +#define MUX_PA24A_EIC_EXTINT8 _L_(0) +#define PINMUX_PA24A_EIC_EXTINT8 ((PIN_PA24A_EIC_EXTINT8 << 16) | MUX_PA24A_EIC_EXTINT8) +#define PORT_PA24A_EIC_EXTINT8 (_UL_(1) << 24) +#define PIN_PA24A_EIC_EXTINT_NUM _L_(8) /**< \brief EIC signal: PIN_PA24 External Interrupt Line */ +#define PIN_PB08A_EIC_EXTINT8 _L_(40) /**< \brief EIC signal: EXTINT8 on PB08 mux A */ +#define MUX_PB08A_EIC_EXTINT8 _L_(0) +#define PINMUX_PB08A_EIC_EXTINT8 ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8) +#define PORT_PB08A_EIC_EXTINT8 (_UL_(1) << 8) +#define PIN_PB08A_EIC_EXTINT_NUM _L_(8) /**< \brief EIC signal: PIN_PB08 External Interrupt Line */ +#define PIN_PB24A_EIC_EXTINT8 _L_(56) /**< \brief EIC signal: EXTINT8 on PB24 mux A */ +#define MUX_PB24A_EIC_EXTINT8 _L_(0) +#define PINMUX_PB24A_EIC_EXTINT8 ((PIN_PB24A_EIC_EXTINT8 << 16) | MUX_PB24A_EIC_EXTINT8) +#define PORT_PB24A_EIC_EXTINT8 (_UL_(1) << 24) +#define PIN_PB24A_EIC_EXTINT_NUM _L_(8) /**< \brief EIC signal: PIN_PB24 External Interrupt Line */ +#define PIN_PC24A_EIC_EXTINT8 _L_(88) /**< \brief EIC signal: EXTINT8 on PC24 mux A */ +#define MUX_PC24A_EIC_EXTINT8 _L_(0) +#define PINMUX_PC24A_EIC_EXTINT8 ((PIN_PC24A_EIC_EXTINT8 << 16) | MUX_PC24A_EIC_EXTINT8) +#define PORT_PC24A_EIC_EXTINT8 (_UL_(1) << 24) +#define PIN_PC24A_EIC_EXTINT_NUM _L_(8) /**< \brief EIC signal: PIN_PC24 External Interrupt Line */ +#define PIN_PA09A_EIC_EXTINT9 _L_(9) /**< \brief EIC signal: EXTINT9 on PA09 mux A */ +#define MUX_PA09A_EIC_EXTINT9 _L_(0) +#define PINMUX_PA09A_EIC_EXTINT9 ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9) +#define PORT_PA09A_EIC_EXTINT9 (_UL_(1) << 9) +#define PIN_PA09A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PA09 External Interrupt Line */ +#define PIN_PA25A_EIC_EXTINT9 _L_(25) /**< \brief EIC signal: EXTINT9 on PA25 mux A */ +#define MUX_PA25A_EIC_EXTINT9 _L_(0) +#define PINMUX_PA25A_EIC_EXTINT9 ((PIN_PA25A_EIC_EXTINT9 << 16) | MUX_PA25A_EIC_EXTINT9) +#define PORT_PA25A_EIC_EXTINT9 (_UL_(1) << 25) +#define PIN_PA25A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PA25 External Interrupt Line */ +#define PIN_PB09A_EIC_EXTINT9 _L_(41) /**< \brief EIC signal: EXTINT9 on PB09 mux A */ +#define MUX_PB09A_EIC_EXTINT9 _L_(0) +#define PINMUX_PB09A_EIC_EXTINT9 ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9) +#define PORT_PB09A_EIC_EXTINT9 (_UL_(1) << 9) +#define PIN_PB09A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PB09 External Interrupt Line */ +#define PIN_PB25A_EIC_EXTINT9 _L_(57) /**< \brief EIC signal: EXTINT9 on PB25 mux A */ +#define MUX_PB25A_EIC_EXTINT9 _L_(0) +#define PINMUX_PB25A_EIC_EXTINT9 ((PIN_PB25A_EIC_EXTINT9 << 16) | MUX_PB25A_EIC_EXTINT9) +#define PORT_PB25A_EIC_EXTINT9 (_UL_(1) << 25) +#define PIN_PB25A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PB25 External Interrupt Line */ +#define PIN_PC07A_EIC_EXTINT9 _L_(71) /**< \brief EIC signal: EXTINT9 on PC07 mux A */ +#define MUX_PC07A_EIC_EXTINT9 _L_(0) +#define PINMUX_PC07A_EIC_EXTINT9 ((PIN_PC07A_EIC_EXTINT9 << 16) | MUX_PC07A_EIC_EXTINT9) +#define PORT_PC07A_EIC_EXTINT9 (_UL_(1) << 7) +#define PIN_PC07A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PC07 External Interrupt Line */ +#define PIN_PC25A_EIC_EXTINT9 _L_(89) /**< \brief EIC signal: EXTINT9 on PC25 mux A */ +#define MUX_PC25A_EIC_EXTINT9 _L_(0) +#define PINMUX_PC25A_EIC_EXTINT9 ((PIN_PC25A_EIC_EXTINT9 << 16) | MUX_PC25A_EIC_EXTINT9) +#define PORT_PC25A_EIC_EXTINT9 (_UL_(1) << 25) +#define PIN_PC25A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PC25 External Interrupt Line */ +#define PIN_PA10A_EIC_EXTINT10 _L_(10) /**< \brief EIC signal: EXTINT10 on PA10 mux A */ +#define MUX_PA10A_EIC_EXTINT10 _L_(0) +#define PINMUX_PA10A_EIC_EXTINT10 ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10) +#define PORT_PA10A_EIC_EXTINT10 (_UL_(1) << 10) +#define PIN_PA10A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PA10 External Interrupt Line */ +#define PIN_PB10A_EIC_EXTINT10 _L_(42) /**< \brief EIC signal: EXTINT10 on PB10 mux A */ +#define MUX_PB10A_EIC_EXTINT10 _L_(0) +#define PINMUX_PB10A_EIC_EXTINT10 ((PIN_PB10A_EIC_EXTINT10 << 16) | MUX_PB10A_EIC_EXTINT10) +#define PORT_PB10A_EIC_EXTINT10 (_UL_(1) << 10) +#define PIN_PB10A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PB10 External Interrupt Line */ +#define PIN_PC10A_EIC_EXTINT10 _L_(74) /**< \brief EIC signal: EXTINT10 on PC10 mux A */ +#define MUX_PC10A_EIC_EXTINT10 _L_(0) +#define PINMUX_PC10A_EIC_EXTINT10 ((PIN_PC10A_EIC_EXTINT10 << 16) | MUX_PC10A_EIC_EXTINT10) +#define PORT_PC10A_EIC_EXTINT10 (_UL_(1) << 10) +#define PIN_PC10A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PC10 External Interrupt Line */ +#define PIN_PC26A_EIC_EXTINT10 _L_(90) /**< \brief EIC signal: EXTINT10 on PC26 mux A */ +#define MUX_PC26A_EIC_EXTINT10 _L_(0) +#define PINMUX_PC26A_EIC_EXTINT10 ((PIN_PC26A_EIC_EXTINT10 << 16) | MUX_PC26A_EIC_EXTINT10) +#define PORT_PC26A_EIC_EXTINT10 (_UL_(1) << 26) +#define PIN_PC26A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PC26 External Interrupt Line */ +#define PIN_PA11A_EIC_EXTINT11 _L_(11) /**< \brief EIC signal: EXTINT11 on PA11 mux A */ +#define MUX_PA11A_EIC_EXTINT11 _L_(0) +#define PINMUX_PA11A_EIC_EXTINT11 ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11) +#define PORT_PA11A_EIC_EXTINT11 (_UL_(1) << 11) +#define PIN_PA11A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PA11 External Interrupt Line */ +#define PIN_PA27A_EIC_EXTINT11 _L_(27) /**< \brief EIC signal: EXTINT11 on PA27 mux A */ +#define MUX_PA27A_EIC_EXTINT11 _L_(0) +#define PINMUX_PA27A_EIC_EXTINT11 ((PIN_PA27A_EIC_EXTINT11 << 16) | MUX_PA27A_EIC_EXTINT11) +#define PORT_PA27A_EIC_EXTINT11 (_UL_(1) << 27) +#define PIN_PA27A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PA27 External Interrupt Line */ +#define PIN_PB11A_EIC_EXTINT11 _L_(43) /**< \brief EIC signal: EXTINT11 on PB11 mux A */ +#define MUX_PB11A_EIC_EXTINT11 _L_(0) +#define PINMUX_PB11A_EIC_EXTINT11 ((PIN_PB11A_EIC_EXTINT11 << 16) | MUX_PB11A_EIC_EXTINT11) +#define PORT_PB11A_EIC_EXTINT11 (_UL_(1) << 11) +#define PIN_PB11A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PB11 External Interrupt Line */ +#define PIN_PC11A_EIC_EXTINT11 _L_(75) /**< \brief EIC signal: EXTINT11 on PC11 mux A */ +#define MUX_PC11A_EIC_EXTINT11 _L_(0) +#define PINMUX_PC11A_EIC_EXTINT11 ((PIN_PC11A_EIC_EXTINT11 << 16) | MUX_PC11A_EIC_EXTINT11) +#define PORT_PC11A_EIC_EXTINT11 (_UL_(1) << 11) +#define PIN_PC11A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PC11 External Interrupt Line */ +#define PIN_PC27A_EIC_EXTINT11 _L_(91) /**< \brief EIC signal: EXTINT11 on PC27 mux A */ +#define MUX_PC27A_EIC_EXTINT11 _L_(0) +#define PINMUX_PC27A_EIC_EXTINT11 ((PIN_PC27A_EIC_EXTINT11 << 16) | MUX_PC27A_EIC_EXTINT11) +#define PORT_PC27A_EIC_EXTINT11 (_UL_(1) << 27) +#define PIN_PC27A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PC27 External Interrupt Line */ +#define PIN_PA12A_EIC_EXTINT12 _L_(12) /**< \brief EIC signal: EXTINT12 on PA12 mux A */ +#define MUX_PA12A_EIC_EXTINT12 _L_(0) +#define PINMUX_PA12A_EIC_EXTINT12 ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12) +#define PORT_PA12A_EIC_EXTINT12 (_UL_(1) << 12) +#define PIN_PA12A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PA12 External Interrupt Line */ +#define PIN_PB12A_EIC_EXTINT12 _L_(44) /**< \brief EIC signal: EXTINT12 on PB12 mux A */ +#define MUX_PB12A_EIC_EXTINT12 _L_(0) +#define PINMUX_PB12A_EIC_EXTINT12 ((PIN_PB12A_EIC_EXTINT12 << 16) | MUX_PB12A_EIC_EXTINT12) +#define PORT_PB12A_EIC_EXTINT12 (_UL_(1) << 12) +#define PIN_PB12A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PB12 External Interrupt Line */ +#define PIN_PC12A_EIC_EXTINT12 _L_(76) /**< \brief EIC signal: EXTINT12 on PC12 mux A */ +#define MUX_PC12A_EIC_EXTINT12 _L_(0) +#define PINMUX_PC12A_EIC_EXTINT12 ((PIN_PC12A_EIC_EXTINT12 << 16) | MUX_PC12A_EIC_EXTINT12) +#define PORT_PC12A_EIC_EXTINT12 (_UL_(1) << 12) +#define PIN_PC12A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PC12 External Interrupt Line */ +#define PIN_PC28A_EIC_EXTINT12 _L_(92) /**< \brief EIC signal: EXTINT12 on PC28 mux A */ +#define MUX_PC28A_EIC_EXTINT12 _L_(0) +#define PINMUX_PC28A_EIC_EXTINT12 ((PIN_PC28A_EIC_EXTINT12 << 16) | MUX_PC28A_EIC_EXTINT12) +#define PORT_PC28A_EIC_EXTINT12 (_UL_(1) << 28) +#define PIN_PC28A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PC28 External Interrupt Line */ +#define PIN_PA13A_EIC_EXTINT13 _L_(13) /**< \brief EIC signal: EXTINT13 on PA13 mux A */ +#define MUX_PA13A_EIC_EXTINT13 _L_(0) +#define PINMUX_PA13A_EIC_EXTINT13 ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13) +#define PORT_PA13A_EIC_EXTINT13 (_UL_(1) << 13) +#define PIN_PA13A_EIC_EXTINT_NUM _L_(13) /**< \brief EIC signal: PIN_PA13 External Interrupt Line */ +#define PIN_PB13A_EIC_EXTINT13 _L_(45) /**< \brief EIC signal: EXTINT13 on PB13 mux A */ +#define MUX_PB13A_EIC_EXTINT13 _L_(0) +#define PINMUX_PB13A_EIC_EXTINT13 ((PIN_PB13A_EIC_EXTINT13 << 16) | MUX_PB13A_EIC_EXTINT13) +#define PORT_PB13A_EIC_EXTINT13 (_UL_(1) << 13) +#define PIN_PB13A_EIC_EXTINT_NUM _L_(13) /**< \brief EIC signal: PIN_PB13 External Interrupt Line */ +#define PIN_PC13A_EIC_EXTINT13 _L_(77) /**< \brief EIC signal: EXTINT13 on PC13 mux A */ +#define MUX_PC13A_EIC_EXTINT13 _L_(0) +#define PINMUX_PC13A_EIC_EXTINT13 ((PIN_PC13A_EIC_EXTINT13 << 16) | MUX_PC13A_EIC_EXTINT13) +#define PORT_PC13A_EIC_EXTINT13 (_UL_(1) << 13) +#define PIN_PC13A_EIC_EXTINT_NUM _L_(13) /**< \brief EIC signal: PIN_PC13 External Interrupt Line */ +#define PIN_PA30A_EIC_EXTINT14 _L_(30) /**< \brief EIC signal: EXTINT14 on PA30 mux A */ +#define MUX_PA30A_EIC_EXTINT14 _L_(0) +#define PINMUX_PA30A_EIC_EXTINT14 ((PIN_PA30A_EIC_EXTINT14 << 16) | MUX_PA30A_EIC_EXTINT14) +#define PORT_PA30A_EIC_EXTINT14 (_UL_(1) << 30) +#define PIN_PA30A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PA30 External Interrupt Line */ +#define PIN_PB14A_EIC_EXTINT14 _L_(46) /**< \brief EIC signal: EXTINT14 on PB14 mux A */ +#define MUX_PB14A_EIC_EXTINT14 _L_(0) +#define PINMUX_PB14A_EIC_EXTINT14 ((PIN_PB14A_EIC_EXTINT14 << 16) | MUX_PB14A_EIC_EXTINT14) +#define PORT_PB14A_EIC_EXTINT14 (_UL_(1) << 14) +#define PIN_PB14A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PB14 External Interrupt Line */ +#define PIN_PB30A_EIC_EXTINT14 _L_(62) /**< \brief EIC signal: EXTINT14 on PB30 mux A */ +#define MUX_PB30A_EIC_EXTINT14 _L_(0) +#define PINMUX_PB30A_EIC_EXTINT14 ((PIN_PB30A_EIC_EXTINT14 << 16) | MUX_PB30A_EIC_EXTINT14) +#define PORT_PB30A_EIC_EXTINT14 (_UL_(1) << 30) +#define PIN_PB30A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PB30 External Interrupt Line */ +#define PIN_PC14A_EIC_EXTINT14 _L_(78) /**< \brief EIC signal: EXTINT14 on PC14 mux A */ +#define MUX_PC14A_EIC_EXTINT14 _L_(0) +#define PINMUX_PC14A_EIC_EXTINT14 ((PIN_PC14A_EIC_EXTINT14 << 16) | MUX_PC14A_EIC_EXTINT14) +#define PORT_PC14A_EIC_EXTINT14 (_UL_(1) << 14) +#define PIN_PC14A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PC14 External Interrupt Line */ +#define PIN_PA14A_EIC_EXTINT14 _L_(14) /**< \brief EIC signal: EXTINT14 on PA14 mux A */ +#define MUX_PA14A_EIC_EXTINT14 _L_(0) +#define PINMUX_PA14A_EIC_EXTINT14 ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14) +#define PORT_PA14A_EIC_EXTINT14 (_UL_(1) << 14) +#define PIN_PA14A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PA14 External Interrupt Line */ +#define PIN_PA15A_EIC_EXTINT15 _L_(15) /**< \brief EIC signal: EXTINT15 on PA15 mux A */ +#define MUX_PA15A_EIC_EXTINT15 _L_(0) +#define PINMUX_PA15A_EIC_EXTINT15 ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15) +#define PORT_PA15A_EIC_EXTINT15 (_UL_(1) << 15) +#define PIN_PA15A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PA15 External Interrupt Line */ +#define PIN_PA31A_EIC_EXTINT15 _L_(31) /**< \brief EIC signal: EXTINT15 on PA31 mux A */ +#define MUX_PA31A_EIC_EXTINT15 _L_(0) +#define PINMUX_PA31A_EIC_EXTINT15 ((PIN_PA31A_EIC_EXTINT15 << 16) | MUX_PA31A_EIC_EXTINT15) +#define PORT_PA31A_EIC_EXTINT15 (_UL_(1) << 31) +#define PIN_PA31A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PA31 External Interrupt Line */ +#define PIN_PB15A_EIC_EXTINT15 _L_(47) /**< \brief EIC signal: EXTINT15 on PB15 mux A */ +#define MUX_PB15A_EIC_EXTINT15 _L_(0) +#define PINMUX_PB15A_EIC_EXTINT15 ((PIN_PB15A_EIC_EXTINT15 << 16) | MUX_PB15A_EIC_EXTINT15) +#define PORT_PB15A_EIC_EXTINT15 (_UL_(1) << 15) +#define PIN_PB15A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PB15 External Interrupt Line */ +#define PIN_PB31A_EIC_EXTINT15 _L_(63) /**< \brief EIC signal: EXTINT15 on PB31 mux A */ +#define MUX_PB31A_EIC_EXTINT15 _L_(0) +#define PINMUX_PB31A_EIC_EXTINT15 ((PIN_PB31A_EIC_EXTINT15 << 16) | MUX_PB31A_EIC_EXTINT15) +#define PORT_PB31A_EIC_EXTINT15 (_UL_(1) << 31) +#define PIN_PB31A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PB31 External Interrupt Line */ +#define PIN_PC15A_EIC_EXTINT15 _L_(79) /**< \brief EIC signal: EXTINT15 on PC15 mux A */ +#define MUX_PC15A_EIC_EXTINT15 _L_(0) +#define PINMUX_PC15A_EIC_EXTINT15 ((PIN_PC15A_EIC_EXTINT15 << 16) | MUX_PC15A_EIC_EXTINT15) +#define PORT_PC15A_EIC_EXTINT15 (_UL_(1) << 15) +#define PIN_PC15A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PC15 External Interrupt Line */ +#define PIN_PA08A_EIC_NMI _L_(8) /**< \brief EIC signal: NMI on PA08 mux A */ +#define MUX_PA08A_EIC_NMI _L_(0) +#define PINMUX_PA08A_EIC_NMI ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI) +#define PORT_PA08A_EIC_NMI (_UL_(1) << 8) +/* ========== PORT definition for SERCOM0 peripheral ========== */ +#define PIN_PA04D_SERCOM0_PAD0 _L_(4) /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */ +#define MUX_PA04D_SERCOM0_PAD0 _L_(3) +#define PINMUX_PA04D_SERCOM0_PAD0 ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0) +#define PORT_PA04D_SERCOM0_PAD0 (_UL_(1) << 4) +#define PIN_PC17D_SERCOM0_PAD0 _L_(81) /**< \brief SERCOM0 signal: PAD0 on PC17 mux D */ +#define MUX_PC17D_SERCOM0_PAD0 _L_(3) +#define PINMUX_PC17D_SERCOM0_PAD0 ((PIN_PC17D_SERCOM0_PAD0 << 16) | MUX_PC17D_SERCOM0_PAD0) +#define PORT_PC17D_SERCOM0_PAD0 (_UL_(1) << 17) +#define PIN_PA08C_SERCOM0_PAD0 _L_(8) /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */ +#define MUX_PA08C_SERCOM0_PAD0 _L_(2) +#define PINMUX_PA08C_SERCOM0_PAD0 ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0) +#define PORT_PA08C_SERCOM0_PAD0 (_UL_(1) << 8) +#define PIN_PB24C_SERCOM0_PAD0 _L_(56) /**< \brief SERCOM0 signal: PAD0 on PB24 mux C */ +#define MUX_PB24C_SERCOM0_PAD0 _L_(2) +#define PINMUX_PB24C_SERCOM0_PAD0 ((PIN_PB24C_SERCOM0_PAD0 << 16) | MUX_PB24C_SERCOM0_PAD0) +#define PORT_PB24C_SERCOM0_PAD0 (_UL_(1) << 24) +#define PIN_PA05D_SERCOM0_PAD1 _L_(5) /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */ +#define MUX_PA05D_SERCOM0_PAD1 _L_(3) +#define PINMUX_PA05D_SERCOM0_PAD1 ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1) +#define PORT_PA05D_SERCOM0_PAD1 (_UL_(1) << 5) +#define PIN_PC16D_SERCOM0_PAD1 _L_(80) /**< \brief SERCOM0 signal: PAD1 on PC16 mux D */ +#define MUX_PC16D_SERCOM0_PAD1 _L_(3) +#define PINMUX_PC16D_SERCOM0_PAD1 ((PIN_PC16D_SERCOM0_PAD1 << 16) | MUX_PC16D_SERCOM0_PAD1) +#define PORT_PC16D_SERCOM0_PAD1 (_UL_(1) << 16) +#define PIN_PA09C_SERCOM0_PAD1 _L_(9) /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */ +#define MUX_PA09C_SERCOM0_PAD1 _L_(2) +#define PINMUX_PA09C_SERCOM0_PAD1 ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1) +#define PORT_PA09C_SERCOM0_PAD1 (_UL_(1) << 9) +#define PIN_PB25C_SERCOM0_PAD1 _L_(57) /**< \brief SERCOM0 signal: PAD1 on PB25 mux C */ +#define MUX_PB25C_SERCOM0_PAD1 _L_(2) +#define PINMUX_PB25C_SERCOM0_PAD1 ((PIN_PB25C_SERCOM0_PAD1 << 16) | MUX_PB25C_SERCOM0_PAD1) +#define PORT_PB25C_SERCOM0_PAD1 (_UL_(1) << 25) +#define PIN_PA06D_SERCOM0_PAD2 _L_(6) /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */ +#define MUX_PA06D_SERCOM0_PAD2 _L_(3) +#define PINMUX_PA06D_SERCOM0_PAD2 ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2) +#define PORT_PA06D_SERCOM0_PAD2 (_UL_(1) << 6) +#define PIN_PC18D_SERCOM0_PAD2 _L_(82) /**< \brief SERCOM0 signal: PAD2 on PC18 mux D */ +#define MUX_PC18D_SERCOM0_PAD2 _L_(3) +#define PINMUX_PC18D_SERCOM0_PAD2 ((PIN_PC18D_SERCOM0_PAD2 << 16) | MUX_PC18D_SERCOM0_PAD2) +#define PORT_PC18D_SERCOM0_PAD2 (_UL_(1) << 18) +#define PIN_PA10C_SERCOM0_PAD2 _L_(10) /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */ +#define MUX_PA10C_SERCOM0_PAD2 _L_(2) +#define PINMUX_PA10C_SERCOM0_PAD2 ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2) +#define PORT_PA10C_SERCOM0_PAD2 (_UL_(1) << 10) +#define PIN_PC24C_SERCOM0_PAD2 _L_(88) /**< \brief SERCOM0 signal: PAD2 on PC24 mux C */ +#define MUX_PC24C_SERCOM0_PAD2 _L_(2) +#define PINMUX_PC24C_SERCOM0_PAD2 ((PIN_PC24C_SERCOM0_PAD2 << 16) | MUX_PC24C_SERCOM0_PAD2) +#define PORT_PC24C_SERCOM0_PAD2 (_UL_(1) << 24) +#define PIN_PA07D_SERCOM0_PAD3 _L_(7) /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */ +#define MUX_PA07D_SERCOM0_PAD3 _L_(3) +#define PINMUX_PA07D_SERCOM0_PAD3 ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3) +#define PORT_PA07D_SERCOM0_PAD3 (_UL_(1) << 7) +#define PIN_PC19D_SERCOM0_PAD3 _L_(83) /**< \brief SERCOM0 signal: PAD3 on PC19 mux D */ +#define MUX_PC19D_SERCOM0_PAD3 _L_(3) +#define PINMUX_PC19D_SERCOM0_PAD3 ((PIN_PC19D_SERCOM0_PAD3 << 16) | MUX_PC19D_SERCOM0_PAD3) +#define PORT_PC19D_SERCOM0_PAD3 (_UL_(1) << 19) +#define PIN_PA11C_SERCOM0_PAD3 _L_(11) /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */ +#define MUX_PA11C_SERCOM0_PAD3 _L_(2) +#define PINMUX_PA11C_SERCOM0_PAD3 ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3) +#define PORT_PA11C_SERCOM0_PAD3 (_UL_(1) << 11) +#define PIN_PC25C_SERCOM0_PAD3 _L_(89) /**< \brief SERCOM0 signal: PAD3 on PC25 mux C */ +#define MUX_PC25C_SERCOM0_PAD3 _L_(2) +#define PINMUX_PC25C_SERCOM0_PAD3 ((PIN_PC25C_SERCOM0_PAD3 << 16) | MUX_PC25C_SERCOM0_PAD3) +#define PORT_PC25C_SERCOM0_PAD3 (_UL_(1) << 25) +/* ========== PORT definition for SERCOM1 peripheral ========== */ +#define PIN_PA00D_SERCOM1_PAD0 _L_(0) /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */ +#define MUX_PA00D_SERCOM1_PAD0 _L_(3) +#define PINMUX_PA00D_SERCOM1_PAD0 ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0) +#define PORT_PA00D_SERCOM1_PAD0 (_UL_(1) << 0) +#define PIN_PA16C_SERCOM1_PAD0 _L_(16) /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */ +#define MUX_PA16C_SERCOM1_PAD0 _L_(2) +#define PINMUX_PA16C_SERCOM1_PAD0 ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0) +#define PORT_PA16C_SERCOM1_PAD0 (_UL_(1) << 16) +#define PIN_PC27C_SERCOM1_PAD0 _L_(91) /**< \brief SERCOM1 signal: PAD0 on PC27 mux C */ +#define MUX_PC27C_SERCOM1_PAD0 _L_(2) +#define PINMUX_PC27C_SERCOM1_PAD0 ((PIN_PC27C_SERCOM1_PAD0 << 16) | MUX_PC27C_SERCOM1_PAD0) +#define PORT_PC27C_SERCOM1_PAD0 (_UL_(1) << 27) +#define PIN_PA01D_SERCOM1_PAD1 _L_(1) /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */ +#define MUX_PA01D_SERCOM1_PAD1 _L_(3) +#define PINMUX_PA01D_SERCOM1_PAD1 ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1) +#define PORT_PA01D_SERCOM1_PAD1 (_UL_(1) << 1) +#define PIN_PA17C_SERCOM1_PAD1 _L_(17) /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */ +#define MUX_PA17C_SERCOM1_PAD1 _L_(2) +#define PINMUX_PA17C_SERCOM1_PAD1 ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1) +#define PORT_PA17C_SERCOM1_PAD1 (_UL_(1) << 17) +#define PIN_PC28C_SERCOM1_PAD1 _L_(92) /**< \brief SERCOM1 signal: PAD1 on PC28 mux C */ +#define MUX_PC28C_SERCOM1_PAD1 _L_(2) +#define PINMUX_PC28C_SERCOM1_PAD1 ((PIN_PC28C_SERCOM1_PAD1 << 16) | MUX_PC28C_SERCOM1_PAD1) +#define PORT_PC28C_SERCOM1_PAD1 (_UL_(1) << 28) +#define PIN_PA30D_SERCOM1_PAD2 _L_(30) /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */ +#define MUX_PA30D_SERCOM1_PAD2 _L_(3) +#define PINMUX_PA30D_SERCOM1_PAD2 ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2) +#define PORT_PA30D_SERCOM1_PAD2 (_UL_(1) << 30) +#define PIN_PA18C_SERCOM1_PAD2 _L_(18) /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */ +#define MUX_PA18C_SERCOM1_PAD2 _L_(2) +#define PINMUX_PA18C_SERCOM1_PAD2 ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2) +#define PORT_PA18C_SERCOM1_PAD2 (_UL_(1) << 18) +#define PIN_PB22C_SERCOM1_PAD2 _L_(54) /**< \brief SERCOM1 signal: PAD2 on PB22 mux C */ +#define MUX_PB22C_SERCOM1_PAD2 _L_(2) +#define PINMUX_PB22C_SERCOM1_PAD2 ((PIN_PB22C_SERCOM1_PAD2 << 16) | MUX_PB22C_SERCOM1_PAD2) +#define PORT_PB22C_SERCOM1_PAD2 (_UL_(1) << 22) +#define PIN_PA31D_SERCOM1_PAD3 _L_(31) /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */ +#define MUX_PA31D_SERCOM1_PAD3 _L_(3) +#define PINMUX_PA31D_SERCOM1_PAD3 ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3) +#define PORT_PA31D_SERCOM1_PAD3 (_UL_(1) << 31) +#define PIN_PA19C_SERCOM1_PAD3 _L_(19) /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */ +#define MUX_PA19C_SERCOM1_PAD3 _L_(2) +#define PINMUX_PA19C_SERCOM1_PAD3 ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3) +#define PORT_PA19C_SERCOM1_PAD3 (_UL_(1) << 19) +#define PIN_PB23C_SERCOM1_PAD3 _L_(55) /**< \brief SERCOM1 signal: PAD3 on PB23 mux C */ +#define MUX_PB23C_SERCOM1_PAD3 _L_(2) +#define PINMUX_PB23C_SERCOM1_PAD3 ((PIN_PB23C_SERCOM1_PAD3 << 16) | MUX_PB23C_SERCOM1_PAD3) +#define PORT_PB23C_SERCOM1_PAD3 (_UL_(1) << 23) +/* ========== PORT definition for TC0 peripheral ========== */ +#define PIN_PA04E_TC0_WO0 _L_(4) /**< \brief TC0 signal: WO0 on PA04 mux E */ +#define MUX_PA04E_TC0_WO0 _L_(4) +#define PINMUX_PA04E_TC0_WO0 ((PIN_PA04E_TC0_WO0 << 16) | MUX_PA04E_TC0_WO0) +#define PORT_PA04E_TC0_WO0 (_UL_(1) << 4) +#define PIN_PA08E_TC0_WO0 _L_(8) /**< \brief TC0 signal: WO0 on PA08 mux E */ +#define MUX_PA08E_TC0_WO0 _L_(4) +#define PINMUX_PA08E_TC0_WO0 ((PIN_PA08E_TC0_WO0 << 16) | MUX_PA08E_TC0_WO0) +#define PORT_PA08E_TC0_WO0 (_UL_(1) << 8) +#define PIN_PB30E_TC0_WO0 _L_(62) /**< \brief TC0 signal: WO0 on PB30 mux E */ +#define MUX_PB30E_TC0_WO0 _L_(4) +#define PINMUX_PB30E_TC0_WO0 ((PIN_PB30E_TC0_WO0 << 16) | MUX_PB30E_TC0_WO0) +#define PORT_PB30E_TC0_WO0 (_UL_(1) << 30) +#define PIN_PA05E_TC0_WO1 _L_(5) /**< \brief TC0 signal: WO1 on PA05 mux E */ +#define MUX_PA05E_TC0_WO1 _L_(4) +#define PINMUX_PA05E_TC0_WO1 ((PIN_PA05E_TC0_WO1 << 16) | MUX_PA05E_TC0_WO1) +#define PORT_PA05E_TC0_WO1 (_UL_(1) << 5) +#define PIN_PA09E_TC0_WO1 _L_(9) /**< \brief TC0 signal: WO1 on PA09 mux E */ +#define MUX_PA09E_TC0_WO1 _L_(4) +#define PINMUX_PA09E_TC0_WO1 ((PIN_PA09E_TC0_WO1 << 16) | MUX_PA09E_TC0_WO1) +#define PORT_PA09E_TC0_WO1 (_UL_(1) << 9) +#define PIN_PB31E_TC0_WO1 _L_(63) /**< \brief TC0 signal: WO1 on PB31 mux E */ +#define MUX_PB31E_TC0_WO1 _L_(4) +#define PINMUX_PB31E_TC0_WO1 ((PIN_PB31E_TC0_WO1 << 16) | MUX_PB31E_TC0_WO1) +#define PORT_PB31E_TC0_WO1 (_UL_(1) << 31) +/* ========== PORT definition for TC1 peripheral ========== */ +#define PIN_PA06E_TC1_WO0 _L_(6) /**< \brief TC1 signal: WO0 on PA06 mux E */ +#define MUX_PA06E_TC1_WO0 _L_(4) +#define PINMUX_PA06E_TC1_WO0 ((PIN_PA06E_TC1_WO0 << 16) | MUX_PA06E_TC1_WO0) +#define PORT_PA06E_TC1_WO0 (_UL_(1) << 6) +#define PIN_PA10E_TC1_WO0 _L_(10) /**< \brief TC1 signal: WO0 on PA10 mux E */ +#define MUX_PA10E_TC1_WO0 _L_(4) +#define PINMUX_PA10E_TC1_WO0 ((PIN_PA10E_TC1_WO0 << 16) | MUX_PA10E_TC1_WO0) +#define PORT_PA10E_TC1_WO0 (_UL_(1) << 10) +#define PIN_PA07E_TC1_WO1 _L_(7) /**< \brief TC1 signal: WO1 on PA07 mux E */ +#define MUX_PA07E_TC1_WO1 _L_(4) +#define PINMUX_PA07E_TC1_WO1 ((PIN_PA07E_TC1_WO1 << 16) | MUX_PA07E_TC1_WO1) +#define PORT_PA07E_TC1_WO1 (_UL_(1) << 7) +#define PIN_PA11E_TC1_WO1 _L_(11) /**< \brief TC1 signal: WO1 on PA11 mux E */ +#define MUX_PA11E_TC1_WO1 _L_(4) +#define PINMUX_PA11E_TC1_WO1 ((PIN_PA11E_TC1_WO1 << 16) | MUX_PA11E_TC1_WO1) +#define PORT_PA11E_TC1_WO1 (_UL_(1) << 11) +/* ========== PORT definition for USB peripheral ========== */ +#define PIN_PA24H_USB_DM _L_(24) /**< \brief USB signal: DM on PA24 mux H */ +#define MUX_PA24H_USB_DM _L_(7) +#define PINMUX_PA24H_USB_DM ((PIN_PA24H_USB_DM << 16) | MUX_PA24H_USB_DM) +#define PORT_PA24H_USB_DM (_UL_(1) << 24) +#define PIN_PA25H_USB_DP _L_(25) /**< \brief USB signal: DP on PA25 mux H */ +#define MUX_PA25H_USB_DP _L_(7) +#define PINMUX_PA25H_USB_DP ((PIN_PA25H_USB_DP << 16) | MUX_PA25H_USB_DP) +#define PORT_PA25H_USB_DP (_UL_(1) << 25) +#define PIN_PA23H_USB_SOF_1KHZ _L_(23) /**< \brief USB signal: SOF_1KHZ on PA23 mux H */ +#define MUX_PA23H_USB_SOF_1KHZ _L_(7) +#define PINMUX_PA23H_USB_SOF_1KHZ ((PIN_PA23H_USB_SOF_1KHZ << 16) | MUX_PA23H_USB_SOF_1KHZ) +#define PORT_PA23H_USB_SOF_1KHZ (_UL_(1) << 23) +#define PIN_PB22H_USB_SOF_1KHZ _L_(54) /**< \brief USB signal: SOF_1KHZ on PB22 mux H */ +#define MUX_PB22H_USB_SOF_1KHZ _L_(7) +#define PINMUX_PB22H_USB_SOF_1KHZ ((PIN_PB22H_USB_SOF_1KHZ << 16) | MUX_PB22H_USB_SOF_1KHZ) +#define PORT_PB22H_USB_SOF_1KHZ (_UL_(1) << 22) +/* ========== PORT definition for SERCOM2 peripheral ========== */ +#define PIN_PA09D_SERCOM2_PAD0 _L_(9) /**< \brief SERCOM2 signal: PAD0 on PA09 mux D */ +#define MUX_PA09D_SERCOM2_PAD0 _L_(3) +#define PINMUX_PA09D_SERCOM2_PAD0 ((PIN_PA09D_SERCOM2_PAD0 << 16) | MUX_PA09D_SERCOM2_PAD0) +#define PORT_PA09D_SERCOM2_PAD0 (_UL_(1) << 9) +#define PIN_PB25D_SERCOM2_PAD0 _L_(57) /**< \brief SERCOM2 signal: PAD0 on PB25 mux D */ +#define MUX_PB25D_SERCOM2_PAD0 _L_(3) +#define PINMUX_PB25D_SERCOM2_PAD0 ((PIN_PB25D_SERCOM2_PAD0 << 16) | MUX_PB25D_SERCOM2_PAD0) +#define PORT_PB25D_SERCOM2_PAD0 (_UL_(1) << 25) +#define PIN_PA12C_SERCOM2_PAD0 _L_(12) /**< \brief SERCOM2 signal: PAD0 on PA12 mux C */ +#define MUX_PA12C_SERCOM2_PAD0 _L_(2) +#define PINMUX_PA12C_SERCOM2_PAD0 ((PIN_PA12C_SERCOM2_PAD0 << 16) | MUX_PA12C_SERCOM2_PAD0) +#define PORT_PA12C_SERCOM2_PAD0 (_UL_(1) << 12) +#define PIN_PA08D_SERCOM2_PAD1 _L_(8) /**< \brief SERCOM2 signal: PAD1 on PA08 mux D */ +#define MUX_PA08D_SERCOM2_PAD1 _L_(3) +#define PINMUX_PA08D_SERCOM2_PAD1 ((PIN_PA08D_SERCOM2_PAD1 << 16) | MUX_PA08D_SERCOM2_PAD1) +#define PORT_PA08D_SERCOM2_PAD1 (_UL_(1) << 8) +#define PIN_PB24D_SERCOM2_PAD1 _L_(56) /**< \brief SERCOM2 signal: PAD1 on PB24 mux D */ +#define MUX_PB24D_SERCOM2_PAD1 _L_(3) +#define PINMUX_PB24D_SERCOM2_PAD1 ((PIN_PB24D_SERCOM2_PAD1 << 16) | MUX_PB24D_SERCOM2_PAD1) +#define PORT_PB24D_SERCOM2_PAD1 (_UL_(1) << 24) +#define PIN_PA13C_SERCOM2_PAD1 _L_(13) /**< \brief SERCOM2 signal: PAD1 on PA13 mux C */ +#define MUX_PA13C_SERCOM2_PAD1 _L_(2) +#define PINMUX_PA13C_SERCOM2_PAD1 ((PIN_PA13C_SERCOM2_PAD1 << 16) | MUX_PA13C_SERCOM2_PAD1) +#define PORT_PA13C_SERCOM2_PAD1 (_UL_(1) << 13) +#define PIN_PA10D_SERCOM2_PAD2 _L_(10) /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */ +#define MUX_PA10D_SERCOM2_PAD2 _L_(3) +#define PINMUX_PA10D_SERCOM2_PAD2 ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2) +#define PORT_PA10D_SERCOM2_PAD2 (_UL_(1) << 10) +#define PIN_PC24D_SERCOM2_PAD2 _L_(88) /**< \brief SERCOM2 signal: PAD2 on PC24 mux D */ +#define MUX_PC24D_SERCOM2_PAD2 _L_(3) +#define PINMUX_PC24D_SERCOM2_PAD2 ((PIN_PC24D_SERCOM2_PAD2 << 16) | MUX_PC24D_SERCOM2_PAD2) +#define PORT_PC24D_SERCOM2_PAD2 (_UL_(1) << 24) +#define PIN_PA14C_SERCOM2_PAD2 _L_(14) /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */ +#define MUX_PA14C_SERCOM2_PAD2 _L_(2) +#define PINMUX_PA14C_SERCOM2_PAD2 ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2) +#define PORT_PA14C_SERCOM2_PAD2 (_UL_(1) << 14) +#define PIN_PA11D_SERCOM2_PAD3 _L_(11) /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */ +#define MUX_PA11D_SERCOM2_PAD3 _L_(3) +#define PINMUX_PA11D_SERCOM2_PAD3 ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3) +#define PORT_PA11D_SERCOM2_PAD3 (_UL_(1) << 11) +#define PIN_PC25D_SERCOM2_PAD3 _L_(89) /**< \brief SERCOM2 signal: PAD3 on PC25 mux D */ +#define MUX_PC25D_SERCOM2_PAD3 _L_(3) +#define PINMUX_PC25D_SERCOM2_PAD3 ((PIN_PC25D_SERCOM2_PAD3 << 16) | MUX_PC25D_SERCOM2_PAD3) +#define PORT_PC25D_SERCOM2_PAD3 (_UL_(1) << 25) +#define PIN_PA15C_SERCOM2_PAD3 _L_(15) /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */ +#define MUX_PA15C_SERCOM2_PAD3 _L_(2) +#define PINMUX_PA15C_SERCOM2_PAD3 ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3) +#define PORT_PA15C_SERCOM2_PAD3 (_UL_(1) << 15) +/* ========== PORT definition for SERCOM3 peripheral ========== */ +#define PIN_PA17D_SERCOM3_PAD0 _L_(17) /**< \brief SERCOM3 signal: PAD0 on PA17 mux D */ +#define MUX_PA17D_SERCOM3_PAD0 _L_(3) +#define PINMUX_PA17D_SERCOM3_PAD0 ((PIN_PA17D_SERCOM3_PAD0 << 16) | MUX_PA17D_SERCOM3_PAD0) +#define PORT_PA17D_SERCOM3_PAD0 (_UL_(1) << 17) +#define PIN_PA22C_SERCOM3_PAD0 _L_(22) /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */ +#define MUX_PA22C_SERCOM3_PAD0 _L_(2) +#define PINMUX_PA22C_SERCOM3_PAD0 ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0) +#define PORT_PA22C_SERCOM3_PAD0 (_UL_(1) << 22) +#define PIN_PB20C_SERCOM3_PAD0 _L_(52) /**< \brief SERCOM3 signal: PAD0 on PB20 mux C */ +#define MUX_PB20C_SERCOM3_PAD0 _L_(2) +#define PINMUX_PB20C_SERCOM3_PAD0 ((PIN_PB20C_SERCOM3_PAD0 << 16) | MUX_PB20C_SERCOM3_PAD0) +#define PORT_PB20C_SERCOM3_PAD0 (_UL_(1) << 20) +#define PIN_PA16D_SERCOM3_PAD1 _L_(16) /**< \brief SERCOM3 signal: PAD1 on PA16 mux D */ +#define MUX_PA16D_SERCOM3_PAD1 _L_(3) +#define PINMUX_PA16D_SERCOM3_PAD1 ((PIN_PA16D_SERCOM3_PAD1 << 16) | MUX_PA16D_SERCOM3_PAD1) +#define PORT_PA16D_SERCOM3_PAD1 (_UL_(1) << 16) +#define PIN_PA23C_SERCOM3_PAD1 _L_(23) /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */ +#define MUX_PA23C_SERCOM3_PAD1 _L_(2) +#define PINMUX_PA23C_SERCOM3_PAD1 ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1) +#define PORT_PA23C_SERCOM3_PAD1 (_UL_(1) << 23) +#define PIN_PB21C_SERCOM3_PAD1 _L_(53) /**< \brief SERCOM3 signal: PAD1 on PB21 mux C */ +#define MUX_PB21C_SERCOM3_PAD1 _L_(2) +#define PINMUX_PB21C_SERCOM3_PAD1 ((PIN_PB21C_SERCOM3_PAD1 << 16) | MUX_PB21C_SERCOM3_PAD1) +#define PORT_PB21C_SERCOM3_PAD1 (_UL_(1) << 21) +#define PIN_PA18D_SERCOM3_PAD2 _L_(18) /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */ +#define MUX_PA18D_SERCOM3_PAD2 _L_(3) +#define PINMUX_PA18D_SERCOM3_PAD2 ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2) +#define PORT_PA18D_SERCOM3_PAD2 (_UL_(1) << 18) +#define PIN_PA20D_SERCOM3_PAD2 _L_(20) /**< \brief SERCOM3 signal: PAD2 on PA20 mux D */ +#define MUX_PA20D_SERCOM3_PAD2 _L_(3) +#define PINMUX_PA20D_SERCOM3_PAD2 ((PIN_PA20D_SERCOM3_PAD2 << 16) | MUX_PA20D_SERCOM3_PAD2) +#define PORT_PA20D_SERCOM3_PAD2 (_UL_(1) << 20) +#define PIN_PA24C_SERCOM3_PAD2 _L_(24) /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */ +#define MUX_PA24C_SERCOM3_PAD2 _L_(2) +#define PINMUX_PA24C_SERCOM3_PAD2 ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2) +#define PORT_PA24C_SERCOM3_PAD2 (_UL_(1) << 24) +#define PIN_PA19D_SERCOM3_PAD3 _L_(19) /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */ +#define MUX_PA19D_SERCOM3_PAD3 _L_(3) +#define PINMUX_PA19D_SERCOM3_PAD3 ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3) +#define PORT_PA19D_SERCOM3_PAD3 (_UL_(1) << 19) +#define PIN_PA21D_SERCOM3_PAD3 _L_(21) /**< \brief SERCOM3 signal: PAD3 on PA21 mux D */ +#define MUX_PA21D_SERCOM3_PAD3 _L_(3) +#define PINMUX_PA21D_SERCOM3_PAD3 ((PIN_PA21D_SERCOM3_PAD3 << 16) | MUX_PA21D_SERCOM3_PAD3) +#define PORT_PA21D_SERCOM3_PAD3 (_UL_(1) << 21) +#define PIN_PA25C_SERCOM3_PAD3 _L_(25) /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */ +#define MUX_PA25C_SERCOM3_PAD3 _L_(2) +#define PINMUX_PA25C_SERCOM3_PAD3 ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3) +#define PORT_PA25C_SERCOM3_PAD3 (_UL_(1) << 25) +/* ========== PORT definition for TCC0 peripheral ========== */ +#define PIN_PA20G_TCC0_WO0 _L_(20) /**< \brief TCC0 signal: WO0 on PA20 mux G */ +#define MUX_PA20G_TCC0_WO0 _L_(6) +#define PINMUX_PA20G_TCC0_WO0 ((PIN_PA20G_TCC0_WO0 << 16) | MUX_PA20G_TCC0_WO0) +#define PORT_PA20G_TCC0_WO0 (_UL_(1) << 20) +#define PIN_PB12G_TCC0_WO0 _L_(44) /**< \brief TCC0 signal: WO0 on PB12 mux G */ +#define MUX_PB12G_TCC0_WO0 _L_(6) +#define PINMUX_PB12G_TCC0_WO0 ((PIN_PB12G_TCC0_WO0 << 16) | MUX_PB12G_TCC0_WO0) +#define PORT_PB12G_TCC0_WO0 (_UL_(1) << 12) +#define PIN_PA08F_TCC0_WO0 _L_(8) /**< \brief TCC0 signal: WO0 on PA08 mux F */ +#define MUX_PA08F_TCC0_WO0 _L_(5) +#define PINMUX_PA08F_TCC0_WO0 ((PIN_PA08F_TCC0_WO0 << 16) | MUX_PA08F_TCC0_WO0) +#define PORT_PA08F_TCC0_WO0 (_UL_(1) << 8) +#define PIN_PC10F_TCC0_WO0 _L_(74) /**< \brief TCC0 signal: WO0 on PC10 mux F */ +#define MUX_PC10F_TCC0_WO0 _L_(5) +#define PINMUX_PC10F_TCC0_WO0 ((PIN_PC10F_TCC0_WO0 << 16) | MUX_PC10F_TCC0_WO0) +#define PORT_PC10F_TCC0_WO0 (_UL_(1) << 10) +#define PIN_PC16F_TCC0_WO0 _L_(80) /**< \brief TCC0 signal: WO0 on PC16 mux F */ +#define MUX_PC16F_TCC0_WO0 _L_(5) +#define PINMUX_PC16F_TCC0_WO0 ((PIN_PC16F_TCC0_WO0 << 16) | MUX_PC16F_TCC0_WO0) +#define PORT_PC16F_TCC0_WO0 (_UL_(1) << 16) +#define PIN_PA21G_TCC0_WO1 _L_(21) /**< \brief TCC0 signal: WO1 on PA21 mux G */ +#define MUX_PA21G_TCC0_WO1 _L_(6) +#define PINMUX_PA21G_TCC0_WO1 ((PIN_PA21G_TCC0_WO1 << 16) | MUX_PA21G_TCC0_WO1) +#define PORT_PA21G_TCC0_WO1 (_UL_(1) << 21) +#define PIN_PB13G_TCC0_WO1 _L_(45) /**< \brief TCC0 signal: WO1 on PB13 mux G */ +#define MUX_PB13G_TCC0_WO1 _L_(6) +#define PINMUX_PB13G_TCC0_WO1 ((PIN_PB13G_TCC0_WO1 << 16) | MUX_PB13G_TCC0_WO1) +#define PORT_PB13G_TCC0_WO1 (_UL_(1) << 13) +#define PIN_PA09F_TCC0_WO1 _L_(9) /**< \brief TCC0 signal: WO1 on PA09 mux F */ +#define MUX_PA09F_TCC0_WO1 _L_(5) +#define PINMUX_PA09F_TCC0_WO1 ((PIN_PA09F_TCC0_WO1 << 16) | MUX_PA09F_TCC0_WO1) +#define PORT_PA09F_TCC0_WO1 (_UL_(1) << 9) +#define PIN_PC11F_TCC0_WO1 _L_(75) /**< \brief TCC0 signal: WO1 on PC11 mux F */ +#define MUX_PC11F_TCC0_WO1 _L_(5) +#define PINMUX_PC11F_TCC0_WO1 ((PIN_PC11F_TCC0_WO1 << 16) | MUX_PC11F_TCC0_WO1) +#define PORT_PC11F_TCC0_WO1 (_UL_(1) << 11) +#define PIN_PC17F_TCC0_WO1 _L_(81) /**< \brief TCC0 signal: WO1 on PC17 mux F */ +#define MUX_PC17F_TCC0_WO1 _L_(5) +#define PINMUX_PC17F_TCC0_WO1 ((PIN_PC17F_TCC0_WO1 << 16) | MUX_PC17F_TCC0_WO1) +#define PORT_PC17F_TCC0_WO1 (_UL_(1) << 17) +#define PIN_PA22G_TCC0_WO2 _L_(22) /**< \brief TCC0 signal: WO2 on PA22 mux G */ +#define MUX_PA22G_TCC0_WO2 _L_(6) +#define PINMUX_PA22G_TCC0_WO2 ((PIN_PA22G_TCC0_WO2 << 16) | MUX_PA22G_TCC0_WO2) +#define PORT_PA22G_TCC0_WO2 (_UL_(1) << 22) +#define PIN_PB14G_TCC0_WO2 _L_(46) /**< \brief TCC0 signal: WO2 on PB14 mux G */ +#define MUX_PB14G_TCC0_WO2 _L_(6) +#define PINMUX_PB14G_TCC0_WO2 ((PIN_PB14G_TCC0_WO2 << 16) | MUX_PB14G_TCC0_WO2) +#define PORT_PB14G_TCC0_WO2 (_UL_(1) << 14) +#define PIN_PA10F_TCC0_WO2 _L_(10) /**< \brief TCC0 signal: WO2 on PA10 mux F */ +#define MUX_PA10F_TCC0_WO2 _L_(5) +#define PINMUX_PA10F_TCC0_WO2 ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2) +#define PORT_PA10F_TCC0_WO2 (_UL_(1) << 10) +#define PIN_PC12F_TCC0_WO2 _L_(76) /**< \brief TCC0 signal: WO2 on PC12 mux F */ +#define MUX_PC12F_TCC0_WO2 _L_(5) +#define PINMUX_PC12F_TCC0_WO2 ((PIN_PC12F_TCC0_WO2 << 16) | MUX_PC12F_TCC0_WO2) +#define PORT_PC12F_TCC0_WO2 (_UL_(1) << 12) +#define PIN_PC18F_TCC0_WO2 _L_(82) /**< \brief TCC0 signal: WO2 on PC18 mux F */ +#define MUX_PC18F_TCC0_WO2 _L_(5) +#define PINMUX_PC18F_TCC0_WO2 ((PIN_PC18F_TCC0_WO2 << 16) | MUX_PC18F_TCC0_WO2) +#define PORT_PC18F_TCC0_WO2 (_UL_(1) << 18) +#define PIN_PA23G_TCC0_WO3 _L_(23) /**< \brief TCC0 signal: WO3 on PA23 mux G */ +#define MUX_PA23G_TCC0_WO3 _L_(6) +#define PINMUX_PA23G_TCC0_WO3 ((PIN_PA23G_TCC0_WO3 << 16) | MUX_PA23G_TCC0_WO3) +#define PORT_PA23G_TCC0_WO3 (_UL_(1) << 23) +#define PIN_PB15G_TCC0_WO3 _L_(47) /**< \brief TCC0 signal: WO3 on PB15 mux G */ +#define MUX_PB15G_TCC0_WO3 _L_(6) +#define PINMUX_PB15G_TCC0_WO3 ((PIN_PB15G_TCC0_WO3 << 16) | MUX_PB15G_TCC0_WO3) +#define PORT_PB15G_TCC0_WO3 (_UL_(1) << 15) +#define PIN_PA11F_TCC0_WO3 _L_(11) /**< \brief TCC0 signal: WO3 on PA11 mux F */ +#define MUX_PA11F_TCC0_WO3 _L_(5) +#define PINMUX_PA11F_TCC0_WO3 ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3) +#define PORT_PA11F_TCC0_WO3 (_UL_(1) << 11) +#define PIN_PC13F_TCC0_WO3 _L_(77) /**< \brief TCC0 signal: WO3 on PC13 mux F */ +#define MUX_PC13F_TCC0_WO3 _L_(5) +#define PINMUX_PC13F_TCC0_WO3 ((PIN_PC13F_TCC0_WO3 << 16) | MUX_PC13F_TCC0_WO3) +#define PORT_PC13F_TCC0_WO3 (_UL_(1) << 13) +#define PIN_PC19F_TCC0_WO3 _L_(83) /**< \brief TCC0 signal: WO3 on PC19 mux F */ +#define MUX_PC19F_TCC0_WO3 _L_(5) +#define PINMUX_PC19F_TCC0_WO3 ((PIN_PC19F_TCC0_WO3 << 16) | MUX_PC19F_TCC0_WO3) +#define PORT_PC19F_TCC0_WO3 (_UL_(1) << 19) +#define PIN_PA16G_TCC0_WO4 _L_(16) /**< \brief TCC0 signal: WO4 on PA16 mux G */ +#define MUX_PA16G_TCC0_WO4 _L_(6) +#define PINMUX_PA16G_TCC0_WO4 ((PIN_PA16G_TCC0_WO4 << 16) | MUX_PA16G_TCC0_WO4) +#define PORT_PA16G_TCC0_WO4 (_UL_(1) << 16) +#define PIN_PB16G_TCC0_WO4 _L_(48) /**< \brief TCC0 signal: WO4 on PB16 mux G */ +#define MUX_PB16G_TCC0_WO4 _L_(6) +#define PINMUX_PB16G_TCC0_WO4 ((PIN_PB16G_TCC0_WO4 << 16) | MUX_PB16G_TCC0_WO4) +#define PORT_PB16G_TCC0_WO4 (_UL_(1) << 16) +#define PIN_PB10F_TCC0_WO4 _L_(42) /**< \brief TCC0 signal: WO4 on PB10 mux F */ +#define MUX_PB10F_TCC0_WO4 _L_(5) +#define PINMUX_PB10F_TCC0_WO4 ((PIN_PB10F_TCC0_WO4 << 16) | MUX_PB10F_TCC0_WO4) +#define PORT_PB10F_TCC0_WO4 (_UL_(1) << 10) +#define PIN_PC14F_TCC0_WO4 _L_(78) /**< \brief TCC0 signal: WO4 on PC14 mux F */ +#define MUX_PC14F_TCC0_WO4 _L_(5) +#define PINMUX_PC14F_TCC0_WO4 ((PIN_PC14F_TCC0_WO4 << 16) | MUX_PC14F_TCC0_WO4) +#define PORT_PC14F_TCC0_WO4 (_UL_(1) << 14) +#define PIN_PC20F_TCC0_WO4 _L_(84) /**< \brief TCC0 signal: WO4 on PC20 mux F */ +#define MUX_PC20F_TCC0_WO4 _L_(5) +#define PINMUX_PC20F_TCC0_WO4 ((PIN_PC20F_TCC0_WO4 << 16) | MUX_PC20F_TCC0_WO4) +#define PORT_PC20F_TCC0_WO4 (_UL_(1) << 20) +#define PIN_PA17G_TCC0_WO5 _L_(17) /**< \brief TCC0 signal: WO5 on PA17 mux G */ +#define MUX_PA17G_TCC0_WO5 _L_(6) +#define PINMUX_PA17G_TCC0_WO5 ((PIN_PA17G_TCC0_WO5 << 16) | MUX_PA17G_TCC0_WO5) +#define PORT_PA17G_TCC0_WO5 (_UL_(1) << 17) +#define PIN_PB17G_TCC0_WO5 _L_(49) /**< \brief TCC0 signal: WO5 on PB17 mux G */ +#define MUX_PB17G_TCC0_WO5 _L_(6) +#define PINMUX_PB17G_TCC0_WO5 ((PIN_PB17G_TCC0_WO5 << 16) | MUX_PB17G_TCC0_WO5) +#define PORT_PB17G_TCC0_WO5 (_UL_(1) << 17) +#define PIN_PB11F_TCC0_WO5 _L_(43) /**< \brief TCC0 signal: WO5 on PB11 mux F */ +#define MUX_PB11F_TCC0_WO5 _L_(5) +#define PINMUX_PB11F_TCC0_WO5 ((PIN_PB11F_TCC0_WO5 << 16) | MUX_PB11F_TCC0_WO5) +#define PORT_PB11F_TCC0_WO5 (_UL_(1) << 11) +#define PIN_PC15F_TCC0_WO5 _L_(79) /**< \brief TCC0 signal: WO5 on PC15 mux F */ +#define MUX_PC15F_TCC0_WO5 _L_(5) +#define PINMUX_PC15F_TCC0_WO5 ((PIN_PC15F_TCC0_WO5 << 16) | MUX_PC15F_TCC0_WO5) +#define PORT_PC15F_TCC0_WO5 (_UL_(1) << 15) +#define PIN_PC21F_TCC0_WO5 _L_(85) /**< \brief TCC0 signal: WO5 on PC21 mux F */ +#define MUX_PC21F_TCC0_WO5 _L_(5) +#define PINMUX_PC21F_TCC0_WO5 ((PIN_PC21F_TCC0_WO5 << 16) | MUX_PC21F_TCC0_WO5) +#define PORT_PC21F_TCC0_WO5 (_UL_(1) << 21) +#define PIN_PA18G_TCC0_WO6 _L_(18) /**< \brief TCC0 signal: WO6 on PA18 mux G */ +#define MUX_PA18G_TCC0_WO6 _L_(6) +#define PINMUX_PA18G_TCC0_WO6 ((PIN_PA18G_TCC0_WO6 << 16) | MUX_PA18G_TCC0_WO6) +#define PORT_PA18G_TCC0_WO6 (_UL_(1) << 18) +#define PIN_PB30G_TCC0_WO6 _L_(62) /**< \brief TCC0 signal: WO6 on PB30 mux G */ +#define MUX_PB30G_TCC0_WO6 _L_(6) +#define PINMUX_PB30G_TCC0_WO6 ((PIN_PB30G_TCC0_WO6 << 16) | MUX_PB30G_TCC0_WO6) +#define PORT_PB30G_TCC0_WO6 (_UL_(1) << 30) +#define PIN_PA12F_TCC0_WO6 _L_(12) /**< \brief TCC0 signal: WO6 on PA12 mux F */ +#define MUX_PA12F_TCC0_WO6 _L_(5) +#define PINMUX_PA12F_TCC0_WO6 ((PIN_PA12F_TCC0_WO6 << 16) | MUX_PA12F_TCC0_WO6) +#define PORT_PA12F_TCC0_WO6 (_UL_(1) << 12) +#define PIN_PA19G_TCC0_WO7 _L_(19) /**< \brief TCC0 signal: WO7 on PA19 mux G */ +#define MUX_PA19G_TCC0_WO7 _L_(6) +#define PINMUX_PA19G_TCC0_WO7 ((PIN_PA19G_TCC0_WO7 << 16) | MUX_PA19G_TCC0_WO7) +#define PORT_PA19G_TCC0_WO7 (_UL_(1) << 19) +#define PIN_PB31G_TCC0_WO7 _L_(63) /**< \brief TCC0 signal: WO7 on PB31 mux G */ +#define MUX_PB31G_TCC0_WO7 _L_(6) +#define PINMUX_PB31G_TCC0_WO7 ((PIN_PB31G_TCC0_WO7 << 16) | MUX_PB31G_TCC0_WO7) +#define PORT_PB31G_TCC0_WO7 (_UL_(1) << 31) +#define PIN_PA13F_TCC0_WO7 _L_(13) /**< \brief TCC0 signal: WO7 on PA13 mux F */ +#define MUX_PA13F_TCC0_WO7 _L_(5) +#define PINMUX_PA13F_TCC0_WO7 ((PIN_PA13F_TCC0_WO7 << 16) | MUX_PA13F_TCC0_WO7) +#define PORT_PA13F_TCC0_WO7 (_UL_(1) << 13) +/* ========== PORT definition for TCC1 peripheral ========== */ +#define PIN_PB10G_TCC1_WO0 _L_(42) /**< \brief TCC1 signal: WO0 on PB10 mux G */ +#define MUX_PB10G_TCC1_WO0 _L_(6) +#define PINMUX_PB10G_TCC1_WO0 ((PIN_PB10G_TCC1_WO0 << 16) | MUX_PB10G_TCC1_WO0) +#define PORT_PB10G_TCC1_WO0 (_UL_(1) << 10) +#define PIN_PC14G_TCC1_WO0 _L_(78) /**< \brief TCC1 signal: WO0 on PC14 mux G */ +#define MUX_PC14G_TCC1_WO0 _L_(6) +#define PINMUX_PC14G_TCC1_WO0 ((PIN_PC14G_TCC1_WO0 << 16) | MUX_PC14G_TCC1_WO0) +#define PORT_PC14G_TCC1_WO0 (_UL_(1) << 14) +#define PIN_PA16F_TCC1_WO0 _L_(16) /**< \brief TCC1 signal: WO0 on PA16 mux F */ +#define MUX_PA16F_TCC1_WO0 _L_(5) +#define PINMUX_PA16F_TCC1_WO0 ((PIN_PA16F_TCC1_WO0 << 16) | MUX_PA16F_TCC1_WO0) +#define PORT_PA16F_TCC1_WO0 (_UL_(1) << 16) +#define PIN_PB18F_TCC1_WO0 _L_(50) /**< \brief TCC1 signal: WO0 on PB18 mux F */ +#define MUX_PB18F_TCC1_WO0 _L_(5) +#define PINMUX_PB18F_TCC1_WO0 ((PIN_PB18F_TCC1_WO0 << 16) | MUX_PB18F_TCC1_WO0) +#define PORT_PB18F_TCC1_WO0 (_UL_(1) << 18) +#define PIN_PB11G_TCC1_WO1 _L_(43) /**< \brief TCC1 signal: WO1 on PB11 mux G */ +#define MUX_PB11G_TCC1_WO1 _L_(6) +#define PINMUX_PB11G_TCC1_WO1 ((PIN_PB11G_TCC1_WO1 << 16) | MUX_PB11G_TCC1_WO1) +#define PORT_PB11G_TCC1_WO1 (_UL_(1) << 11) +#define PIN_PC15G_TCC1_WO1 _L_(79) /**< \brief TCC1 signal: WO1 on PC15 mux G */ +#define MUX_PC15G_TCC1_WO1 _L_(6) +#define PINMUX_PC15G_TCC1_WO1 ((PIN_PC15G_TCC1_WO1 << 16) | MUX_PC15G_TCC1_WO1) +#define PORT_PC15G_TCC1_WO1 (_UL_(1) << 15) +#define PIN_PA17F_TCC1_WO1 _L_(17) /**< \brief TCC1 signal: WO1 on PA17 mux F */ +#define MUX_PA17F_TCC1_WO1 _L_(5) +#define PINMUX_PA17F_TCC1_WO1 ((PIN_PA17F_TCC1_WO1 << 16) | MUX_PA17F_TCC1_WO1) +#define PORT_PA17F_TCC1_WO1 (_UL_(1) << 17) +#define PIN_PB19F_TCC1_WO1 _L_(51) /**< \brief TCC1 signal: WO1 on PB19 mux F */ +#define MUX_PB19F_TCC1_WO1 _L_(5) +#define PINMUX_PB19F_TCC1_WO1 ((PIN_PB19F_TCC1_WO1 << 16) | MUX_PB19F_TCC1_WO1) +#define PORT_PB19F_TCC1_WO1 (_UL_(1) << 19) +#define PIN_PA12G_TCC1_WO2 _L_(12) /**< \brief TCC1 signal: WO2 on PA12 mux G */ +#define MUX_PA12G_TCC1_WO2 _L_(6) +#define PINMUX_PA12G_TCC1_WO2 ((PIN_PA12G_TCC1_WO2 << 16) | MUX_PA12G_TCC1_WO2) +#define PORT_PA12G_TCC1_WO2 (_UL_(1) << 12) +#define PIN_PA14G_TCC1_WO2 _L_(14) /**< \brief TCC1 signal: WO2 on PA14 mux G */ +#define MUX_PA14G_TCC1_WO2 _L_(6) +#define PINMUX_PA14G_TCC1_WO2 ((PIN_PA14G_TCC1_WO2 << 16) | MUX_PA14G_TCC1_WO2) +#define PORT_PA14G_TCC1_WO2 (_UL_(1) << 14) +#define PIN_PA18F_TCC1_WO2 _L_(18) /**< \brief TCC1 signal: WO2 on PA18 mux F */ +#define MUX_PA18F_TCC1_WO2 _L_(5) +#define PINMUX_PA18F_TCC1_WO2 ((PIN_PA18F_TCC1_WO2 << 16) | MUX_PA18F_TCC1_WO2) +#define PORT_PA18F_TCC1_WO2 (_UL_(1) << 18) +#define PIN_PB20F_TCC1_WO2 _L_(52) /**< \brief TCC1 signal: WO2 on PB20 mux F */ +#define MUX_PB20F_TCC1_WO2 _L_(5) +#define PINMUX_PB20F_TCC1_WO2 ((PIN_PB20F_TCC1_WO2 << 16) | MUX_PB20F_TCC1_WO2) +#define PORT_PB20F_TCC1_WO2 (_UL_(1) << 20) +#define PIN_PA13G_TCC1_WO3 _L_(13) /**< \brief TCC1 signal: WO3 on PA13 mux G */ +#define MUX_PA13G_TCC1_WO3 _L_(6) +#define PINMUX_PA13G_TCC1_WO3 ((PIN_PA13G_TCC1_WO3 << 16) | MUX_PA13G_TCC1_WO3) +#define PORT_PA13G_TCC1_WO3 (_UL_(1) << 13) +#define PIN_PA15G_TCC1_WO3 _L_(15) /**< \brief TCC1 signal: WO3 on PA15 mux G */ +#define MUX_PA15G_TCC1_WO3 _L_(6) +#define PINMUX_PA15G_TCC1_WO3 ((PIN_PA15G_TCC1_WO3 << 16) | MUX_PA15G_TCC1_WO3) +#define PORT_PA15G_TCC1_WO3 (_UL_(1) << 15) +#define PIN_PA19F_TCC1_WO3 _L_(19) /**< \brief TCC1 signal: WO3 on PA19 mux F */ +#define MUX_PA19F_TCC1_WO3 _L_(5) +#define PINMUX_PA19F_TCC1_WO3 ((PIN_PA19F_TCC1_WO3 << 16) | MUX_PA19F_TCC1_WO3) +#define PORT_PA19F_TCC1_WO3 (_UL_(1) << 19) +#define PIN_PB21F_TCC1_WO3 _L_(53) /**< \brief TCC1 signal: WO3 on PB21 mux F */ +#define MUX_PB21F_TCC1_WO3 _L_(5) +#define PINMUX_PB21F_TCC1_WO3 ((PIN_PB21F_TCC1_WO3 << 16) | MUX_PB21F_TCC1_WO3) +#define PORT_PB21F_TCC1_WO3 (_UL_(1) << 21) +#define PIN_PA08G_TCC1_WO4 _L_(8) /**< \brief TCC1 signal: WO4 on PA08 mux G */ +#define MUX_PA08G_TCC1_WO4 _L_(6) +#define PINMUX_PA08G_TCC1_WO4 ((PIN_PA08G_TCC1_WO4 << 16) | MUX_PA08G_TCC1_WO4) +#define PORT_PA08G_TCC1_WO4 (_UL_(1) << 8) +#define PIN_PC10G_TCC1_WO4 _L_(74) /**< \brief TCC1 signal: WO4 on PC10 mux G */ +#define MUX_PC10G_TCC1_WO4 _L_(6) +#define PINMUX_PC10G_TCC1_WO4 ((PIN_PC10G_TCC1_WO4 << 16) | MUX_PC10G_TCC1_WO4) +#define PORT_PC10G_TCC1_WO4 (_UL_(1) << 10) +#define PIN_PA20F_TCC1_WO4 _L_(20) /**< \brief TCC1 signal: WO4 on PA20 mux F */ +#define MUX_PA20F_TCC1_WO4 _L_(5) +#define PINMUX_PA20F_TCC1_WO4 ((PIN_PA20F_TCC1_WO4 << 16) | MUX_PA20F_TCC1_WO4) +#define PORT_PA20F_TCC1_WO4 (_UL_(1) << 20) +#define PIN_PA09G_TCC1_WO5 _L_(9) /**< \brief TCC1 signal: WO5 on PA09 mux G */ +#define MUX_PA09G_TCC1_WO5 _L_(6) +#define PINMUX_PA09G_TCC1_WO5 ((PIN_PA09G_TCC1_WO5 << 16) | MUX_PA09G_TCC1_WO5) +#define PORT_PA09G_TCC1_WO5 (_UL_(1) << 9) +#define PIN_PC11G_TCC1_WO5 _L_(75) /**< \brief TCC1 signal: WO5 on PC11 mux G */ +#define MUX_PC11G_TCC1_WO5 _L_(6) +#define PINMUX_PC11G_TCC1_WO5 ((PIN_PC11G_TCC1_WO5 << 16) | MUX_PC11G_TCC1_WO5) +#define PORT_PC11G_TCC1_WO5 (_UL_(1) << 11) +#define PIN_PA21F_TCC1_WO5 _L_(21) /**< \brief TCC1 signal: WO5 on PA21 mux F */ +#define MUX_PA21F_TCC1_WO5 _L_(5) +#define PINMUX_PA21F_TCC1_WO5 ((PIN_PA21F_TCC1_WO5 << 16) | MUX_PA21F_TCC1_WO5) +#define PORT_PA21F_TCC1_WO5 (_UL_(1) << 21) +#define PIN_PA10G_TCC1_WO6 _L_(10) /**< \brief TCC1 signal: WO6 on PA10 mux G */ +#define MUX_PA10G_TCC1_WO6 _L_(6) +#define PINMUX_PA10G_TCC1_WO6 ((PIN_PA10G_TCC1_WO6 << 16) | MUX_PA10G_TCC1_WO6) +#define PORT_PA10G_TCC1_WO6 (_UL_(1) << 10) +#define PIN_PC12G_TCC1_WO6 _L_(76) /**< \brief TCC1 signal: WO6 on PC12 mux G */ +#define MUX_PC12G_TCC1_WO6 _L_(6) +#define PINMUX_PC12G_TCC1_WO6 ((PIN_PC12G_TCC1_WO6 << 16) | MUX_PC12G_TCC1_WO6) +#define PORT_PC12G_TCC1_WO6 (_UL_(1) << 12) +#define PIN_PA22F_TCC1_WO6 _L_(22) /**< \brief TCC1 signal: WO6 on PA22 mux F */ +#define MUX_PA22F_TCC1_WO6 _L_(5) +#define PINMUX_PA22F_TCC1_WO6 ((PIN_PA22F_TCC1_WO6 << 16) | MUX_PA22F_TCC1_WO6) +#define PORT_PA22F_TCC1_WO6 (_UL_(1) << 22) +#define PIN_PA11G_TCC1_WO7 _L_(11) /**< \brief TCC1 signal: WO7 on PA11 mux G */ +#define MUX_PA11G_TCC1_WO7 _L_(6) +#define PINMUX_PA11G_TCC1_WO7 ((PIN_PA11G_TCC1_WO7 << 16) | MUX_PA11G_TCC1_WO7) +#define PORT_PA11G_TCC1_WO7 (_UL_(1) << 11) +#define PIN_PC13G_TCC1_WO7 _L_(77) /**< \brief TCC1 signal: WO7 on PC13 mux G */ +#define MUX_PC13G_TCC1_WO7 _L_(6) +#define PINMUX_PC13G_TCC1_WO7 ((PIN_PC13G_TCC1_WO7 << 16) | MUX_PC13G_TCC1_WO7) +#define PORT_PC13G_TCC1_WO7 (_UL_(1) << 13) +#define PIN_PA23F_TCC1_WO7 _L_(23) /**< \brief TCC1 signal: WO7 on PA23 mux F */ +#define MUX_PA23F_TCC1_WO7 _L_(5) +#define PINMUX_PA23F_TCC1_WO7 ((PIN_PA23F_TCC1_WO7 << 16) | MUX_PA23F_TCC1_WO7) +#define PORT_PA23F_TCC1_WO7 (_UL_(1) << 23) +/* ========== PORT definition for TC2 peripheral ========== */ +#define PIN_PA12E_TC2_WO0 _L_(12) /**< \brief TC2 signal: WO0 on PA12 mux E */ +#define MUX_PA12E_TC2_WO0 _L_(4) +#define PINMUX_PA12E_TC2_WO0 ((PIN_PA12E_TC2_WO0 << 16) | MUX_PA12E_TC2_WO0) +#define PORT_PA12E_TC2_WO0 (_UL_(1) << 12) +#define PIN_PA16E_TC2_WO0 _L_(16) /**< \brief TC2 signal: WO0 on PA16 mux E */ +#define MUX_PA16E_TC2_WO0 _L_(4) +#define PINMUX_PA16E_TC2_WO0 ((PIN_PA16E_TC2_WO0 << 16) | MUX_PA16E_TC2_WO0) +#define PORT_PA16E_TC2_WO0 (_UL_(1) << 16) +#define PIN_PA00E_TC2_WO0 _L_(0) /**< \brief TC2 signal: WO0 on PA00 mux E */ +#define MUX_PA00E_TC2_WO0 _L_(4) +#define PINMUX_PA00E_TC2_WO0 ((PIN_PA00E_TC2_WO0 << 16) | MUX_PA00E_TC2_WO0) +#define PORT_PA00E_TC2_WO0 (_UL_(1) << 0) +#define PIN_PA01E_TC2_WO1 _L_(1) /**< \brief TC2 signal: WO1 on PA01 mux E */ +#define MUX_PA01E_TC2_WO1 _L_(4) +#define PINMUX_PA01E_TC2_WO1 ((PIN_PA01E_TC2_WO1 << 16) | MUX_PA01E_TC2_WO1) +#define PORT_PA01E_TC2_WO1 (_UL_(1) << 1) +#define PIN_PA13E_TC2_WO1 _L_(13) /**< \brief TC2 signal: WO1 on PA13 mux E */ +#define MUX_PA13E_TC2_WO1 _L_(4) +#define PINMUX_PA13E_TC2_WO1 ((PIN_PA13E_TC2_WO1 << 16) | MUX_PA13E_TC2_WO1) +#define PORT_PA13E_TC2_WO1 (_UL_(1) << 13) +#define PIN_PA17E_TC2_WO1 _L_(17) /**< \brief TC2 signal: WO1 on PA17 mux E */ +#define MUX_PA17E_TC2_WO1 _L_(4) +#define PINMUX_PA17E_TC2_WO1 ((PIN_PA17E_TC2_WO1 << 16) | MUX_PA17E_TC2_WO1) +#define PORT_PA17E_TC2_WO1 (_UL_(1) << 17) +/* ========== PORT definition for TC3 peripheral ========== */ +#define PIN_PA18E_TC3_WO0 _L_(18) /**< \brief TC3 signal: WO0 on PA18 mux E */ +#define MUX_PA18E_TC3_WO0 _L_(4) +#define PINMUX_PA18E_TC3_WO0 ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0) +#define PORT_PA18E_TC3_WO0 (_UL_(1) << 18) +#define PIN_PA14E_TC3_WO0 _L_(14) /**< \brief TC3 signal: WO0 on PA14 mux E */ +#define MUX_PA14E_TC3_WO0 _L_(4) +#define PINMUX_PA14E_TC3_WO0 ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0) +#define PORT_PA14E_TC3_WO0 (_UL_(1) << 14) +#define PIN_PA15E_TC3_WO1 _L_(15) /**< \brief TC3 signal: WO1 on PA15 mux E */ +#define MUX_PA15E_TC3_WO1 _L_(4) +#define PINMUX_PA15E_TC3_WO1 ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1) +#define PORT_PA15E_TC3_WO1 (_UL_(1) << 15) +#define PIN_PA19E_TC3_WO1 _L_(19) /**< \brief TC3 signal: WO1 on PA19 mux E */ +#define MUX_PA19E_TC3_WO1 _L_(4) +#define PINMUX_PA19E_TC3_WO1 ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1) +#define PORT_PA19E_TC3_WO1 (_UL_(1) << 19) +/* ========== PORT definition for CAN0 peripheral ========== */ +#define PIN_PA23I_CAN0_RX _L_(23) /**< \brief CAN0 signal: RX on PA23 mux I */ +#define MUX_PA23I_CAN0_RX _L_(8) +#define PINMUX_PA23I_CAN0_RX ((PIN_PA23I_CAN0_RX << 16) | MUX_PA23I_CAN0_RX) +#define PORT_PA23I_CAN0_RX (_UL_(1) << 23) +#define PIN_PA25I_CAN0_RX _L_(25) /**< \brief CAN0 signal: RX on PA25 mux I */ +#define MUX_PA25I_CAN0_RX _L_(8) +#define PINMUX_PA25I_CAN0_RX ((PIN_PA25I_CAN0_RX << 16) | MUX_PA25I_CAN0_RX) +#define PORT_PA25I_CAN0_RX (_UL_(1) << 25) +#define PIN_PA22I_CAN0_TX _L_(22) /**< \brief CAN0 signal: TX on PA22 mux I */ +#define MUX_PA22I_CAN0_TX _L_(8) +#define PINMUX_PA22I_CAN0_TX ((PIN_PA22I_CAN0_TX << 16) | MUX_PA22I_CAN0_TX) +#define PORT_PA22I_CAN0_TX (_UL_(1) << 22) +#define PIN_PA24I_CAN0_TX _L_(24) /**< \brief CAN0 signal: TX on PA24 mux I */ +#define MUX_PA24I_CAN0_TX _L_(8) +#define PINMUX_PA24I_CAN0_TX ((PIN_PA24I_CAN0_TX << 16) | MUX_PA24I_CAN0_TX) +#define PORT_PA24I_CAN0_TX (_UL_(1) << 24) +/* ========== PORT definition for CAN1 peripheral ========== */ +#define PIN_PB13H_CAN1_RX _L_(45) /**< \brief CAN1 signal: RX on PB13 mux H */ +#define MUX_PB13H_CAN1_RX _L_(7) +#define PINMUX_PB13H_CAN1_RX ((PIN_PB13H_CAN1_RX << 16) | MUX_PB13H_CAN1_RX) +#define PORT_PB13H_CAN1_RX (_UL_(1) << 13) +#define PIN_PB15H_CAN1_RX _L_(47) /**< \brief CAN1 signal: RX on PB15 mux H */ +#define MUX_PB15H_CAN1_RX _L_(7) +#define PINMUX_PB15H_CAN1_RX ((PIN_PB15H_CAN1_RX << 16) | MUX_PB15H_CAN1_RX) +#define PORT_PB15H_CAN1_RX (_UL_(1) << 15) +#define PIN_PB12H_CAN1_TX _L_(44) /**< \brief CAN1 signal: TX on PB12 mux H */ +#define MUX_PB12H_CAN1_TX _L_(7) +#define PINMUX_PB12H_CAN1_TX ((PIN_PB12H_CAN1_TX << 16) | MUX_PB12H_CAN1_TX) +#define PORT_PB12H_CAN1_TX (_UL_(1) << 12) +#define PIN_PB14H_CAN1_TX _L_(46) /**< \brief CAN1 signal: TX on PB14 mux H */ +#define MUX_PB14H_CAN1_TX _L_(7) +#define PINMUX_PB14H_CAN1_TX ((PIN_PB14H_CAN1_TX << 16) | MUX_PB14H_CAN1_TX) +#define PORT_PB14H_CAN1_TX (_UL_(1) << 14) +/* ========== PORT definition for GMAC peripheral ========== */ +#define PIN_PC21L_GMAC_GCOL _L_(85) /**< \brief GMAC signal: GCOL on PC21 mux L */ +#define MUX_PC21L_GMAC_GCOL _L_(11) +#define PINMUX_PC21L_GMAC_GCOL ((PIN_PC21L_GMAC_GCOL << 16) | MUX_PC21L_GMAC_GCOL) +#define PORT_PC21L_GMAC_GCOL (_UL_(1) << 21) +#define PIN_PA16L_GMAC_GCRS _L_(16) /**< \brief GMAC signal: GCRS on PA16 mux L */ +#define MUX_PA16L_GMAC_GCRS _L_(11) +#define PINMUX_PA16L_GMAC_GCRS ((PIN_PA16L_GMAC_GCRS << 16) | MUX_PA16L_GMAC_GCRS) +#define PORT_PA16L_GMAC_GCRS (_UL_(1) << 16) +#define PIN_PA20L_GMAC_GMDC _L_(20) /**< \brief GMAC signal: GMDC on PA20 mux L */ +#define MUX_PA20L_GMAC_GMDC _L_(11) +#define PINMUX_PA20L_GMAC_GMDC ((PIN_PA20L_GMAC_GMDC << 16) | MUX_PA20L_GMAC_GMDC) +#define PORT_PA20L_GMAC_GMDC (_UL_(1) << 20) +#define PIN_PB14L_GMAC_GMDC _L_(46) /**< \brief GMAC signal: GMDC on PB14 mux L */ +#define MUX_PB14L_GMAC_GMDC _L_(11) +#define PINMUX_PB14L_GMAC_GMDC ((PIN_PB14L_GMAC_GMDC << 16) | MUX_PB14L_GMAC_GMDC) +#define PORT_PB14L_GMAC_GMDC (_UL_(1) << 14) +#define PIN_PC11L_GMAC_GMDC _L_(75) /**< \brief GMAC signal: GMDC on PC11 mux L */ +#define MUX_PC11L_GMAC_GMDC _L_(11) +#define PINMUX_PC11L_GMAC_GMDC ((PIN_PC11L_GMAC_GMDC << 16) | MUX_PC11L_GMAC_GMDC) +#define PORT_PC11L_GMAC_GMDC (_UL_(1) << 11) +#define PIN_PA21L_GMAC_GMDIO _L_(21) /**< \brief GMAC signal: GMDIO on PA21 mux L */ +#define MUX_PA21L_GMAC_GMDIO _L_(11) +#define PINMUX_PA21L_GMAC_GMDIO ((PIN_PA21L_GMAC_GMDIO << 16) | MUX_PA21L_GMAC_GMDIO) +#define PORT_PA21L_GMAC_GMDIO (_UL_(1) << 21) +#define PIN_PB15L_GMAC_GMDIO _L_(47) /**< \brief GMAC signal: GMDIO on PB15 mux L */ +#define MUX_PB15L_GMAC_GMDIO _L_(11) +#define PINMUX_PB15L_GMAC_GMDIO ((PIN_PB15L_GMAC_GMDIO << 16) | MUX_PB15L_GMAC_GMDIO) +#define PORT_PB15L_GMAC_GMDIO (_UL_(1) << 15) +#define PIN_PC12L_GMAC_GMDIO _L_(76) /**< \brief GMAC signal: GMDIO on PC12 mux L */ +#define MUX_PC12L_GMAC_GMDIO _L_(11) +#define PINMUX_PC12L_GMAC_GMDIO ((PIN_PC12L_GMAC_GMDIO << 16) | MUX_PC12L_GMAC_GMDIO) +#define PORT_PC12L_GMAC_GMDIO (_UL_(1) << 12) +#define PIN_PA13L_GMAC_GRX0 _L_(13) /**< \brief GMAC signal: GRX0 on PA13 mux L */ +#define MUX_PA13L_GMAC_GRX0 _L_(11) +#define PINMUX_PA13L_GMAC_GRX0 ((PIN_PA13L_GMAC_GRX0 << 16) | MUX_PA13L_GMAC_GRX0) +#define PORT_PA13L_GMAC_GRX0 (_UL_(1) << 13) +#define PIN_PA12L_GMAC_GRX1 _L_(12) /**< \brief GMAC signal: GRX1 on PA12 mux L */ +#define MUX_PA12L_GMAC_GRX1 _L_(11) +#define PINMUX_PA12L_GMAC_GRX1 ((PIN_PA12L_GMAC_GRX1 << 16) | MUX_PA12L_GMAC_GRX1) +#define PORT_PA12L_GMAC_GRX1 (_UL_(1) << 12) +#define PIN_PC15L_GMAC_GRX2 _L_(79) /**< \brief GMAC signal: GRX2 on PC15 mux L */ +#define MUX_PC15L_GMAC_GRX2 _L_(11) +#define PINMUX_PC15L_GMAC_GRX2 ((PIN_PC15L_GMAC_GRX2 << 16) | MUX_PC15L_GMAC_GRX2) +#define PORT_PC15L_GMAC_GRX2 (_UL_(1) << 15) +#define PIN_PC14L_GMAC_GRX3 _L_(78) /**< \brief GMAC signal: GRX3 on PC14 mux L */ +#define MUX_PC14L_GMAC_GRX3 _L_(11) +#define PINMUX_PC14L_GMAC_GRX3 ((PIN_PC14L_GMAC_GRX3 << 16) | MUX_PC14L_GMAC_GRX3) +#define PORT_PC14L_GMAC_GRX3 (_UL_(1) << 14) +#define PIN_PC18L_GMAC_GRXCK _L_(82) /**< \brief GMAC signal: GRXCK on PC18 mux L */ +#define MUX_PC18L_GMAC_GRXCK _L_(11) +#define PINMUX_PC18L_GMAC_GRXCK ((PIN_PC18L_GMAC_GRXCK << 16) | MUX_PC18L_GMAC_GRXCK) +#define PORT_PC18L_GMAC_GRXCK (_UL_(1) << 18) +#define PIN_PC20L_GMAC_GRXDV _L_(84) /**< \brief GMAC signal: GRXDV on PC20 mux L */ +#define MUX_PC20L_GMAC_GRXDV _L_(11) +#define PINMUX_PC20L_GMAC_GRXDV ((PIN_PC20L_GMAC_GRXDV << 16) | MUX_PC20L_GMAC_GRXDV) +#define PORT_PC20L_GMAC_GRXDV (_UL_(1) << 20) +#define PIN_PA15L_GMAC_GRXER _L_(15) /**< \brief GMAC signal: GRXER on PA15 mux L */ +#define MUX_PA15L_GMAC_GRXER _L_(11) +#define PINMUX_PA15L_GMAC_GRXER ((PIN_PA15L_GMAC_GRXER << 16) | MUX_PA15L_GMAC_GRXER) +#define PORT_PA15L_GMAC_GRXER (_UL_(1) << 15) +#define PIN_PA18L_GMAC_GTX0 _L_(18) /**< \brief GMAC signal: GTX0 on PA18 mux L */ +#define MUX_PA18L_GMAC_GTX0 _L_(11) +#define PINMUX_PA18L_GMAC_GTX0 ((PIN_PA18L_GMAC_GTX0 << 16) | MUX_PA18L_GMAC_GTX0) +#define PORT_PA18L_GMAC_GTX0 (_UL_(1) << 18) +#define PIN_PA19L_GMAC_GTX1 _L_(19) /**< \brief GMAC signal: GTX1 on PA19 mux L */ +#define MUX_PA19L_GMAC_GTX1 _L_(11) +#define PINMUX_PA19L_GMAC_GTX1 ((PIN_PA19L_GMAC_GTX1 << 16) | MUX_PA19L_GMAC_GTX1) +#define PORT_PA19L_GMAC_GTX1 (_UL_(1) << 19) +#define PIN_PC16L_GMAC_GTX2 _L_(80) /**< \brief GMAC signal: GTX2 on PC16 mux L */ +#define MUX_PC16L_GMAC_GTX2 _L_(11) +#define PINMUX_PC16L_GMAC_GTX2 ((PIN_PC16L_GMAC_GTX2 << 16) | MUX_PC16L_GMAC_GTX2) +#define PORT_PC16L_GMAC_GTX2 (_UL_(1) << 16) +#define PIN_PC17L_GMAC_GTX3 _L_(81) /**< \brief GMAC signal: GTX3 on PC17 mux L */ +#define MUX_PC17L_GMAC_GTX3 _L_(11) +#define PINMUX_PC17L_GMAC_GTX3 ((PIN_PC17L_GMAC_GTX3 << 16) | MUX_PC17L_GMAC_GTX3) +#define PORT_PC17L_GMAC_GTX3 (_UL_(1) << 17) +#define PIN_PA14L_GMAC_GTXCK _L_(14) /**< \brief GMAC signal: GTXCK on PA14 mux L */ +#define MUX_PA14L_GMAC_GTXCK _L_(11) +#define PINMUX_PA14L_GMAC_GTXCK ((PIN_PA14L_GMAC_GTXCK << 16) | MUX_PA14L_GMAC_GTXCK) +#define PORT_PA14L_GMAC_GTXCK (_UL_(1) << 14) +#define PIN_PA17L_GMAC_GTXEN _L_(17) /**< \brief GMAC signal: GTXEN on PA17 mux L */ +#define MUX_PA17L_GMAC_GTXEN _L_(11) +#define PINMUX_PA17L_GMAC_GTXEN ((PIN_PA17L_GMAC_GTXEN << 16) | MUX_PA17L_GMAC_GTXEN) +#define PORT_PA17L_GMAC_GTXEN (_UL_(1) << 17) +#define PIN_PC19L_GMAC_GTXER _L_(83) /**< \brief GMAC signal: GTXER on PC19 mux L */ +#define MUX_PC19L_GMAC_GTXER _L_(11) +#define PINMUX_PC19L_GMAC_GTXER ((PIN_PC19L_GMAC_GTXER << 16) | MUX_PC19L_GMAC_GTXER) +#define PORT_PC19L_GMAC_GTXER (_UL_(1) << 19) +/* ========== PORT definition for TCC2 peripheral ========== */ +#define PIN_PA14F_TCC2_WO0 _L_(14) /**< \brief TCC2 signal: WO0 on PA14 mux F */ +#define MUX_PA14F_TCC2_WO0 _L_(5) +#define PINMUX_PA14F_TCC2_WO0 ((PIN_PA14F_TCC2_WO0 << 16) | MUX_PA14F_TCC2_WO0) +#define PORT_PA14F_TCC2_WO0 (_UL_(1) << 14) +#define PIN_PA30F_TCC2_WO0 _L_(30) /**< \brief TCC2 signal: WO0 on PA30 mux F */ +#define MUX_PA30F_TCC2_WO0 _L_(5) +#define PINMUX_PA30F_TCC2_WO0 ((PIN_PA30F_TCC2_WO0 << 16) | MUX_PA30F_TCC2_WO0) +#define PORT_PA30F_TCC2_WO0 (_UL_(1) << 30) +#define PIN_PA15F_TCC2_WO1 _L_(15) /**< \brief TCC2 signal: WO1 on PA15 mux F */ +#define MUX_PA15F_TCC2_WO1 _L_(5) +#define PINMUX_PA15F_TCC2_WO1 ((PIN_PA15F_TCC2_WO1 << 16) | MUX_PA15F_TCC2_WO1) +#define PORT_PA15F_TCC2_WO1 (_UL_(1) << 15) +#define PIN_PA31F_TCC2_WO1 _L_(31) /**< \brief TCC2 signal: WO1 on PA31 mux F */ +#define MUX_PA31F_TCC2_WO1 _L_(5) +#define PINMUX_PA31F_TCC2_WO1 ((PIN_PA31F_TCC2_WO1 << 16) | MUX_PA31F_TCC2_WO1) +#define PORT_PA31F_TCC2_WO1 (_UL_(1) << 31) +#define PIN_PA24F_TCC2_WO2 _L_(24) /**< \brief TCC2 signal: WO2 on PA24 mux F */ +#define MUX_PA24F_TCC2_WO2 _L_(5) +#define PINMUX_PA24F_TCC2_WO2 ((PIN_PA24F_TCC2_WO2 << 16) | MUX_PA24F_TCC2_WO2) +#define PORT_PA24F_TCC2_WO2 (_UL_(1) << 24) +#define PIN_PB02F_TCC2_WO2 _L_(34) /**< \brief TCC2 signal: WO2 on PB02 mux F */ +#define MUX_PB02F_TCC2_WO2 _L_(5) +#define PINMUX_PB02F_TCC2_WO2 ((PIN_PB02F_TCC2_WO2 << 16) | MUX_PB02F_TCC2_WO2) +#define PORT_PB02F_TCC2_WO2 (_UL_(1) << 2) +/* ========== PORT definition for TCC3 peripheral ========== */ +#define PIN_PB12F_TCC3_WO0 _L_(44) /**< \brief TCC3 signal: WO0 on PB12 mux F */ +#define MUX_PB12F_TCC3_WO0 _L_(5) +#define PINMUX_PB12F_TCC3_WO0 ((PIN_PB12F_TCC3_WO0 << 16) | MUX_PB12F_TCC3_WO0) +#define PORT_PB12F_TCC3_WO0 (_UL_(1) << 12) +#define PIN_PB16F_TCC3_WO0 _L_(48) /**< \brief TCC3 signal: WO0 on PB16 mux F */ +#define MUX_PB16F_TCC3_WO0 _L_(5) +#define PINMUX_PB16F_TCC3_WO0 ((PIN_PB16F_TCC3_WO0 << 16) | MUX_PB16F_TCC3_WO0) +#define PORT_PB16F_TCC3_WO0 (_UL_(1) << 16) +#define PIN_PB13F_TCC3_WO1 _L_(45) /**< \brief TCC3 signal: WO1 on PB13 mux F */ +#define MUX_PB13F_TCC3_WO1 _L_(5) +#define PINMUX_PB13F_TCC3_WO1 ((PIN_PB13F_TCC3_WO1 << 16) | MUX_PB13F_TCC3_WO1) +#define PORT_PB13F_TCC3_WO1 (_UL_(1) << 13) +#define PIN_PB17F_TCC3_WO1 _L_(49) /**< \brief TCC3 signal: WO1 on PB17 mux F */ +#define MUX_PB17F_TCC3_WO1 _L_(5) +#define PINMUX_PB17F_TCC3_WO1 ((PIN_PB17F_TCC3_WO1 << 16) | MUX_PB17F_TCC3_WO1) +#define PORT_PB17F_TCC3_WO1 (_UL_(1) << 17) +/* ========== PORT definition for TC4 peripheral ========== */ +#define PIN_PA22E_TC4_WO0 _L_(22) /**< \brief TC4 signal: WO0 on PA22 mux E */ +#define MUX_PA22E_TC4_WO0 _L_(4) +#define PINMUX_PA22E_TC4_WO0 ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0) +#define PORT_PA22E_TC4_WO0 (_UL_(1) << 22) +#define PIN_PB08E_TC4_WO0 _L_(40) /**< \brief TC4 signal: WO0 on PB08 mux E */ +#define MUX_PB08E_TC4_WO0 _L_(4) +#define PINMUX_PB08E_TC4_WO0 ((PIN_PB08E_TC4_WO0 << 16) | MUX_PB08E_TC4_WO0) +#define PORT_PB08E_TC4_WO0 (_UL_(1) << 8) +#define PIN_PB12E_TC4_WO0 _L_(44) /**< \brief TC4 signal: WO0 on PB12 mux E */ +#define MUX_PB12E_TC4_WO0 _L_(4) +#define PINMUX_PB12E_TC4_WO0 ((PIN_PB12E_TC4_WO0 << 16) | MUX_PB12E_TC4_WO0) +#define PORT_PB12E_TC4_WO0 (_UL_(1) << 12) +#define PIN_PA23E_TC4_WO1 _L_(23) /**< \brief TC4 signal: WO1 on PA23 mux E */ +#define MUX_PA23E_TC4_WO1 _L_(4) +#define PINMUX_PA23E_TC4_WO1 ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1) +#define PORT_PA23E_TC4_WO1 (_UL_(1) << 23) +#define PIN_PB09E_TC4_WO1 _L_(41) /**< \brief TC4 signal: WO1 on PB09 mux E */ +#define MUX_PB09E_TC4_WO1 _L_(4) +#define PINMUX_PB09E_TC4_WO1 ((PIN_PB09E_TC4_WO1 << 16) | MUX_PB09E_TC4_WO1) +#define PORT_PB09E_TC4_WO1 (_UL_(1) << 9) +#define PIN_PB13E_TC4_WO1 _L_(45) /**< \brief TC4 signal: WO1 on PB13 mux E */ +#define MUX_PB13E_TC4_WO1 _L_(4) +#define PINMUX_PB13E_TC4_WO1 ((PIN_PB13E_TC4_WO1 << 16) | MUX_PB13E_TC4_WO1) +#define PORT_PB13E_TC4_WO1 (_UL_(1) << 13) +/* ========== PORT definition for TC5 peripheral ========== */ +#define PIN_PA24E_TC5_WO0 _L_(24) /**< \brief TC5 signal: WO0 on PA24 mux E */ +#define MUX_PA24E_TC5_WO0 _L_(4) +#define PINMUX_PA24E_TC5_WO0 ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0) +#define PORT_PA24E_TC5_WO0 (_UL_(1) << 24) +#define PIN_PB10E_TC5_WO0 _L_(42) /**< \brief TC5 signal: WO0 on PB10 mux E */ +#define MUX_PB10E_TC5_WO0 _L_(4) +#define PINMUX_PB10E_TC5_WO0 ((PIN_PB10E_TC5_WO0 << 16) | MUX_PB10E_TC5_WO0) +#define PORT_PB10E_TC5_WO0 (_UL_(1) << 10) +#define PIN_PB14E_TC5_WO0 _L_(46) /**< \brief TC5 signal: WO0 on PB14 mux E */ +#define MUX_PB14E_TC5_WO0 _L_(4) +#define PINMUX_PB14E_TC5_WO0 ((PIN_PB14E_TC5_WO0 << 16) | MUX_PB14E_TC5_WO0) +#define PORT_PB14E_TC5_WO0 (_UL_(1) << 14) +#define PIN_PA25E_TC5_WO1 _L_(25) /**< \brief TC5 signal: WO1 on PA25 mux E */ +#define MUX_PA25E_TC5_WO1 _L_(4) +#define PINMUX_PA25E_TC5_WO1 ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1) +#define PORT_PA25E_TC5_WO1 (_UL_(1) << 25) +#define PIN_PB11E_TC5_WO1 _L_(43) /**< \brief TC5 signal: WO1 on PB11 mux E */ +#define MUX_PB11E_TC5_WO1 _L_(4) +#define PINMUX_PB11E_TC5_WO1 ((PIN_PB11E_TC5_WO1 << 16) | MUX_PB11E_TC5_WO1) +#define PORT_PB11E_TC5_WO1 (_UL_(1) << 11) +#define PIN_PB15E_TC5_WO1 _L_(47) /**< \brief TC5 signal: WO1 on PB15 mux E */ +#define MUX_PB15E_TC5_WO1 _L_(4) +#define PINMUX_PB15E_TC5_WO1 ((PIN_PB15E_TC5_WO1 << 16) | MUX_PB15E_TC5_WO1) +#define PORT_PB15E_TC5_WO1 (_UL_(1) << 15) +/* ========== PORT definition for PDEC peripheral ========== */ +#define PIN_PB18G_PDEC_QDI0 _L_(50) /**< \brief PDEC signal: QDI0 on PB18 mux G */ +#define MUX_PB18G_PDEC_QDI0 _L_(6) +#define PINMUX_PB18G_PDEC_QDI0 ((PIN_PB18G_PDEC_QDI0 << 16) | MUX_PB18G_PDEC_QDI0) +#define PORT_PB18G_PDEC_QDI0 (_UL_(1) << 18) +#define PIN_PB23G_PDEC_QDI0 _L_(55) /**< \brief PDEC signal: QDI0 on PB23 mux G */ +#define MUX_PB23G_PDEC_QDI0 _L_(6) +#define PINMUX_PB23G_PDEC_QDI0 ((PIN_PB23G_PDEC_QDI0 << 16) | MUX_PB23G_PDEC_QDI0) +#define PORT_PB23G_PDEC_QDI0 (_UL_(1) << 23) +#define PIN_PC16G_PDEC_QDI0 _L_(80) /**< \brief PDEC signal: QDI0 on PC16 mux G */ +#define MUX_PC16G_PDEC_QDI0 _L_(6) +#define PINMUX_PC16G_PDEC_QDI0 ((PIN_PC16G_PDEC_QDI0 << 16) | MUX_PC16G_PDEC_QDI0) +#define PORT_PC16G_PDEC_QDI0 (_UL_(1) << 16) +#define PIN_PA24G_PDEC_QDI0 _L_(24) /**< \brief PDEC signal: QDI0 on PA24 mux G */ +#define MUX_PA24G_PDEC_QDI0 _L_(6) +#define PINMUX_PA24G_PDEC_QDI0 ((PIN_PA24G_PDEC_QDI0 << 16) | MUX_PA24G_PDEC_QDI0) +#define PORT_PA24G_PDEC_QDI0 (_UL_(1) << 24) +#define PIN_PB19G_PDEC_QDI1 _L_(51) /**< \brief PDEC signal: QDI1 on PB19 mux G */ +#define MUX_PB19G_PDEC_QDI1 _L_(6) +#define PINMUX_PB19G_PDEC_QDI1 ((PIN_PB19G_PDEC_QDI1 << 16) | MUX_PB19G_PDEC_QDI1) +#define PORT_PB19G_PDEC_QDI1 (_UL_(1) << 19) +#define PIN_PB24G_PDEC_QDI1 _L_(56) /**< \brief PDEC signal: QDI1 on PB24 mux G */ +#define MUX_PB24G_PDEC_QDI1 _L_(6) +#define PINMUX_PB24G_PDEC_QDI1 ((PIN_PB24G_PDEC_QDI1 << 16) | MUX_PB24G_PDEC_QDI1) +#define PORT_PB24G_PDEC_QDI1 (_UL_(1) << 24) +#define PIN_PC17G_PDEC_QDI1 _L_(81) /**< \brief PDEC signal: QDI1 on PC17 mux G */ +#define MUX_PC17G_PDEC_QDI1 _L_(6) +#define PINMUX_PC17G_PDEC_QDI1 ((PIN_PC17G_PDEC_QDI1 << 16) | MUX_PC17G_PDEC_QDI1) +#define PORT_PC17G_PDEC_QDI1 (_UL_(1) << 17) +#define PIN_PA25G_PDEC_QDI1 _L_(25) /**< \brief PDEC signal: QDI1 on PA25 mux G */ +#define MUX_PA25G_PDEC_QDI1 _L_(6) +#define PINMUX_PA25G_PDEC_QDI1 ((PIN_PA25G_PDEC_QDI1 << 16) | MUX_PA25G_PDEC_QDI1) +#define PORT_PA25G_PDEC_QDI1 (_UL_(1) << 25) +#define PIN_PB20G_PDEC_QDI2 _L_(52) /**< \brief PDEC signal: QDI2 on PB20 mux G */ +#define MUX_PB20G_PDEC_QDI2 _L_(6) +#define PINMUX_PB20G_PDEC_QDI2 ((PIN_PB20G_PDEC_QDI2 << 16) | MUX_PB20G_PDEC_QDI2) +#define PORT_PB20G_PDEC_QDI2 (_UL_(1) << 20) +#define PIN_PB25G_PDEC_QDI2 _L_(57) /**< \brief PDEC signal: QDI2 on PB25 mux G */ +#define MUX_PB25G_PDEC_QDI2 _L_(6) +#define PINMUX_PB25G_PDEC_QDI2 ((PIN_PB25G_PDEC_QDI2 << 16) | MUX_PB25G_PDEC_QDI2) +#define PORT_PB25G_PDEC_QDI2 (_UL_(1) << 25) +#define PIN_PC18G_PDEC_QDI2 _L_(82) /**< \brief PDEC signal: QDI2 on PC18 mux G */ +#define MUX_PC18G_PDEC_QDI2 _L_(6) +#define PINMUX_PC18G_PDEC_QDI2 ((PIN_PC18G_PDEC_QDI2 << 16) | MUX_PC18G_PDEC_QDI2) +#define PORT_PC18G_PDEC_QDI2 (_UL_(1) << 18) +#define PIN_PB22G_PDEC_QDI2 _L_(54) /**< \brief PDEC signal: QDI2 on PB22 mux G */ +#define MUX_PB22G_PDEC_QDI2 _L_(6) +#define PINMUX_PB22G_PDEC_QDI2 ((PIN_PB22G_PDEC_QDI2 << 16) | MUX_PB22G_PDEC_QDI2) +#define PORT_PB22G_PDEC_QDI2 (_UL_(1) << 22) +/* ========== PORT definition for AC peripheral ========== */ +#define PIN_PA04B_AC_AIN0 _L_(4) /**< \brief AC signal: AIN0 on PA04 mux B */ +#define MUX_PA04B_AC_AIN0 _L_(1) +#define PINMUX_PA04B_AC_AIN0 ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0) +#define PORT_PA04B_AC_AIN0 (_UL_(1) << 4) +#define PIN_PA05B_AC_AIN1 _L_(5) /**< \brief AC signal: AIN1 on PA05 mux B */ +#define MUX_PA05B_AC_AIN1 _L_(1) +#define PINMUX_PA05B_AC_AIN1 ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1) +#define PORT_PA05B_AC_AIN1 (_UL_(1) << 5) +#define PIN_PA06B_AC_AIN2 _L_(6) /**< \brief AC signal: AIN2 on PA06 mux B */ +#define MUX_PA06B_AC_AIN2 _L_(1) +#define PINMUX_PA06B_AC_AIN2 ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2) +#define PORT_PA06B_AC_AIN2 (_UL_(1) << 6) +#define PIN_PA07B_AC_AIN3 _L_(7) /**< \brief AC signal: AIN3 on PA07 mux B */ +#define MUX_PA07B_AC_AIN3 _L_(1) +#define PINMUX_PA07B_AC_AIN3 ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3) +#define PORT_PA07B_AC_AIN3 (_UL_(1) << 7) +#define PIN_PA12M_AC_CMP0 _L_(12) /**< \brief AC signal: CMP0 on PA12 mux M */ +#define MUX_PA12M_AC_CMP0 _L_(12) +#define PINMUX_PA12M_AC_CMP0 ((PIN_PA12M_AC_CMP0 << 16) | MUX_PA12M_AC_CMP0) +#define PORT_PA12M_AC_CMP0 (_UL_(1) << 12) +#define PIN_PA18M_AC_CMP0 _L_(18) /**< \brief AC signal: CMP0 on PA18 mux M */ +#define MUX_PA18M_AC_CMP0 _L_(12) +#define PINMUX_PA18M_AC_CMP0 ((PIN_PA18M_AC_CMP0 << 16) | MUX_PA18M_AC_CMP0) +#define PORT_PA18M_AC_CMP0 (_UL_(1) << 18) +#define PIN_PB24M_AC_CMP0 _L_(56) /**< \brief AC signal: CMP0 on PB24 mux M */ +#define MUX_PB24M_AC_CMP0 _L_(12) +#define PINMUX_PB24M_AC_CMP0 ((PIN_PB24M_AC_CMP0 << 16) | MUX_PB24M_AC_CMP0) +#define PORT_PB24M_AC_CMP0 (_UL_(1) << 24) +#define PIN_PA13M_AC_CMP1 _L_(13) /**< \brief AC signal: CMP1 on PA13 mux M */ +#define MUX_PA13M_AC_CMP1 _L_(12) +#define PINMUX_PA13M_AC_CMP1 ((PIN_PA13M_AC_CMP1 << 16) | MUX_PA13M_AC_CMP1) +#define PORT_PA13M_AC_CMP1 (_UL_(1) << 13) +#define PIN_PA19M_AC_CMP1 _L_(19) /**< \brief AC signal: CMP1 on PA19 mux M */ +#define MUX_PA19M_AC_CMP1 _L_(12) +#define PINMUX_PA19M_AC_CMP1 ((PIN_PA19M_AC_CMP1 << 16) | MUX_PA19M_AC_CMP1) +#define PORT_PA19M_AC_CMP1 (_UL_(1) << 19) +#define PIN_PB25M_AC_CMP1 _L_(57) /**< \brief AC signal: CMP1 on PB25 mux M */ +#define MUX_PB25M_AC_CMP1 _L_(12) +#define PINMUX_PB25M_AC_CMP1 ((PIN_PB25M_AC_CMP1 << 16) | MUX_PB25M_AC_CMP1) +#define PORT_PB25M_AC_CMP1 (_UL_(1) << 25) +/* ========== PORT definition for QSPI peripheral ========== */ +#define PIN_PB11H_QSPI_CS _L_(43) /**< \brief QSPI signal: CS on PB11 mux H */ +#define MUX_PB11H_QSPI_CS _L_(7) +#define PINMUX_PB11H_QSPI_CS ((PIN_PB11H_QSPI_CS << 16) | MUX_PB11H_QSPI_CS) +#define PORT_PB11H_QSPI_CS (_UL_(1) << 11) +#define PIN_PA08H_QSPI_DATA0 _L_(8) /**< \brief QSPI signal: DATA0 on PA08 mux H */ +#define MUX_PA08H_QSPI_DATA0 _L_(7) +#define PINMUX_PA08H_QSPI_DATA0 ((PIN_PA08H_QSPI_DATA0 << 16) | MUX_PA08H_QSPI_DATA0) +#define PORT_PA08H_QSPI_DATA0 (_UL_(1) << 8) +#define PIN_PA09H_QSPI_DATA1 _L_(9) /**< \brief QSPI signal: DATA1 on PA09 mux H */ +#define MUX_PA09H_QSPI_DATA1 _L_(7) +#define PINMUX_PA09H_QSPI_DATA1 ((PIN_PA09H_QSPI_DATA1 << 16) | MUX_PA09H_QSPI_DATA1) +#define PORT_PA09H_QSPI_DATA1 (_UL_(1) << 9) +#define PIN_PA10H_QSPI_DATA2 _L_(10) /**< \brief QSPI signal: DATA2 on PA10 mux H */ +#define MUX_PA10H_QSPI_DATA2 _L_(7) +#define PINMUX_PA10H_QSPI_DATA2 ((PIN_PA10H_QSPI_DATA2 << 16) | MUX_PA10H_QSPI_DATA2) +#define PORT_PA10H_QSPI_DATA2 (_UL_(1) << 10) +#define PIN_PA11H_QSPI_DATA3 _L_(11) /**< \brief QSPI signal: DATA3 on PA11 mux H */ +#define MUX_PA11H_QSPI_DATA3 _L_(7) +#define PINMUX_PA11H_QSPI_DATA3 ((PIN_PA11H_QSPI_DATA3 << 16) | MUX_PA11H_QSPI_DATA3) +#define PORT_PA11H_QSPI_DATA3 (_UL_(1) << 11) +#define PIN_PB10H_QSPI_SCK _L_(42) /**< \brief QSPI signal: SCK on PB10 mux H */ +#define MUX_PB10H_QSPI_SCK _L_(7) +#define PINMUX_PB10H_QSPI_SCK ((PIN_PB10H_QSPI_SCK << 16) | MUX_PB10H_QSPI_SCK) +#define PORT_PB10H_QSPI_SCK (_UL_(1) << 10) +/* ========== PORT definition for CCL peripheral ========== */ +#define PIN_PA04N_CCL_IN0 _L_(4) /**< \brief CCL signal: IN0 on PA04 mux N */ +#define MUX_PA04N_CCL_IN0 _L_(13) +#define PINMUX_PA04N_CCL_IN0 ((PIN_PA04N_CCL_IN0 << 16) | MUX_PA04N_CCL_IN0) +#define PORT_PA04N_CCL_IN0 (_UL_(1) << 4) +#define PIN_PA16N_CCL_IN0 _L_(16) /**< \brief CCL signal: IN0 on PA16 mux N */ +#define MUX_PA16N_CCL_IN0 _L_(13) +#define PINMUX_PA16N_CCL_IN0 ((PIN_PA16N_CCL_IN0 << 16) | MUX_PA16N_CCL_IN0) +#define PORT_PA16N_CCL_IN0 (_UL_(1) << 16) +#define PIN_PB22N_CCL_IN0 _L_(54) /**< \brief CCL signal: IN0 on PB22 mux N */ +#define MUX_PB22N_CCL_IN0 _L_(13) +#define PINMUX_PB22N_CCL_IN0 ((PIN_PB22N_CCL_IN0 << 16) | MUX_PB22N_CCL_IN0) +#define PORT_PB22N_CCL_IN0 (_UL_(1) << 22) +#define PIN_PA05N_CCL_IN1 _L_(5) /**< \brief CCL signal: IN1 on PA05 mux N */ +#define MUX_PA05N_CCL_IN1 _L_(13) +#define PINMUX_PA05N_CCL_IN1 ((PIN_PA05N_CCL_IN1 << 16) | MUX_PA05N_CCL_IN1) +#define PORT_PA05N_CCL_IN1 (_UL_(1) << 5) +#define PIN_PA17N_CCL_IN1 _L_(17) /**< \brief CCL signal: IN1 on PA17 mux N */ +#define MUX_PA17N_CCL_IN1 _L_(13) +#define PINMUX_PA17N_CCL_IN1 ((PIN_PA17N_CCL_IN1 << 16) | MUX_PA17N_CCL_IN1) +#define PORT_PA17N_CCL_IN1 (_UL_(1) << 17) +#define PIN_PB00N_CCL_IN1 _L_(32) /**< \brief CCL signal: IN1 on PB00 mux N */ +#define MUX_PB00N_CCL_IN1 _L_(13) +#define PINMUX_PB00N_CCL_IN1 ((PIN_PB00N_CCL_IN1 << 16) | MUX_PB00N_CCL_IN1) +#define PORT_PB00N_CCL_IN1 (_UL_(1) << 0) +#define PIN_PA06N_CCL_IN2 _L_(6) /**< \brief CCL signal: IN2 on PA06 mux N */ +#define MUX_PA06N_CCL_IN2 _L_(13) +#define PINMUX_PA06N_CCL_IN2 ((PIN_PA06N_CCL_IN2 << 16) | MUX_PA06N_CCL_IN2) +#define PORT_PA06N_CCL_IN2 (_UL_(1) << 6) +#define PIN_PA18N_CCL_IN2 _L_(18) /**< \brief CCL signal: IN2 on PA18 mux N */ +#define MUX_PA18N_CCL_IN2 _L_(13) +#define PINMUX_PA18N_CCL_IN2 ((PIN_PA18N_CCL_IN2 << 16) | MUX_PA18N_CCL_IN2) +#define PORT_PA18N_CCL_IN2 (_UL_(1) << 18) +#define PIN_PB01N_CCL_IN2 _L_(33) /**< \brief CCL signal: IN2 on PB01 mux N */ +#define MUX_PB01N_CCL_IN2 _L_(13) +#define PINMUX_PB01N_CCL_IN2 ((PIN_PB01N_CCL_IN2 << 16) | MUX_PB01N_CCL_IN2) +#define PORT_PB01N_CCL_IN2 (_UL_(1) << 1) +#define PIN_PA08N_CCL_IN3 _L_(8) /**< \brief CCL signal: IN3 on PA08 mux N */ +#define MUX_PA08N_CCL_IN3 _L_(13) +#define PINMUX_PA08N_CCL_IN3 ((PIN_PA08N_CCL_IN3 << 16) | MUX_PA08N_CCL_IN3) +#define PORT_PA08N_CCL_IN3 (_UL_(1) << 8) +#define PIN_PA30N_CCL_IN3 _L_(30) /**< \brief CCL signal: IN3 on PA30 mux N */ +#define MUX_PA30N_CCL_IN3 _L_(13) +#define PINMUX_PA30N_CCL_IN3 ((PIN_PA30N_CCL_IN3 << 16) | MUX_PA30N_CCL_IN3) +#define PORT_PA30N_CCL_IN3 (_UL_(1) << 30) +#define PIN_PA09N_CCL_IN4 _L_(9) /**< \brief CCL signal: IN4 on PA09 mux N */ +#define MUX_PA09N_CCL_IN4 _L_(13) +#define PINMUX_PA09N_CCL_IN4 ((PIN_PA09N_CCL_IN4 << 16) | MUX_PA09N_CCL_IN4) +#define PORT_PA09N_CCL_IN4 (_UL_(1) << 9) +#define PIN_PC27N_CCL_IN4 _L_(91) /**< \brief CCL signal: IN4 on PC27 mux N */ +#define MUX_PC27N_CCL_IN4 _L_(13) +#define PINMUX_PC27N_CCL_IN4 ((PIN_PC27N_CCL_IN4 << 16) | MUX_PC27N_CCL_IN4) +#define PORT_PC27N_CCL_IN4 (_UL_(1) << 27) +#define PIN_PA10N_CCL_IN5 _L_(10) /**< \brief CCL signal: IN5 on PA10 mux N */ +#define MUX_PA10N_CCL_IN5 _L_(13) +#define PINMUX_PA10N_CCL_IN5 ((PIN_PA10N_CCL_IN5 << 16) | MUX_PA10N_CCL_IN5) +#define PORT_PA10N_CCL_IN5 (_UL_(1) << 10) +#define PIN_PC28N_CCL_IN5 _L_(92) /**< \brief CCL signal: IN5 on PC28 mux N */ +#define MUX_PC28N_CCL_IN5 _L_(13) +#define PINMUX_PC28N_CCL_IN5 ((PIN_PC28N_CCL_IN5 << 16) | MUX_PC28N_CCL_IN5) +#define PORT_PC28N_CCL_IN5 (_UL_(1) << 28) +#define PIN_PA22N_CCL_IN6 _L_(22) /**< \brief CCL signal: IN6 on PA22 mux N */ +#define MUX_PA22N_CCL_IN6 _L_(13) +#define PINMUX_PA22N_CCL_IN6 ((PIN_PA22N_CCL_IN6 << 16) | MUX_PA22N_CCL_IN6) +#define PORT_PA22N_CCL_IN6 (_UL_(1) << 22) +#define PIN_PB06N_CCL_IN6 _L_(38) /**< \brief CCL signal: IN6 on PB06 mux N */ +#define MUX_PB06N_CCL_IN6 _L_(13) +#define PINMUX_PB06N_CCL_IN6 ((PIN_PB06N_CCL_IN6 << 16) | MUX_PB06N_CCL_IN6) +#define PORT_PB06N_CCL_IN6 (_UL_(1) << 6) +#define PIN_PA23N_CCL_IN7 _L_(23) /**< \brief CCL signal: IN7 on PA23 mux N */ +#define MUX_PA23N_CCL_IN7 _L_(13) +#define PINMUX_PA23N_CCL_IN7 ((PIN_PA23N_CCL_IN7 << 16) | MUX_PA23N_CCL_IN7) +#define PORT_PA23N_CCL_IN7 (_UL_(1) << 23) +#define PIN_PB07N_CCL_IN7 _L_(39) /**< \brief CCL signal: IN7 on PB07 mux N */ +#define MUX_PB07N_CCL_IN7 _L_(13) +#define PINMUX_PB07N_CCL_IN7 ((PIN_PB07N_CCL_IN7 << 16) | MUX_PB07N_CCL_IN7) +#define PORT_PB07N_CCL_IN7 (_UL_(1) << 7) +#define PIN_PA24N_CCL_IN8 _L_(24) /**< \brief CCL signal: IN8 on PA24 mux N */ +#define MUX_PA24N_CCL_IN8 _L_(13) +#define PINMUX_PA24N_CCL_IN8 ((PIN_PA24N_CCL_IN8 << 16) | MUX_PA24N_CCL_IN8) +#define PORT_PA24N_CCL_IN8 (_UL_(1) << 24) +#define PIN_PB08N_CCL_IN8 _L_(40) /**< \brief CCL signal: IN8 on PB08 mux N */ +#define MUX_PB08N_CCL_IN8 _L_(13) +#define PINMUX_PB08N_CCL_IN8 ((PIN_PB08N_CCL_IN8 << 16) | MUX_PB08N_CCL_IN8) +#define PORT_PB08N_CCL_IN8 (_UL_(1) << 8) +#define PIN_PB14N_CCL_IN9 _L_(46) /**< \brief CCL signal: IN9 on PB14 mux N */ +#define MUX_PB14N_CCL_IN9 _L_(13) +#define PINMUX_PB14N_CCL_IN9 ((PIN_PB14N_CCL_IN9 << 16) | MUX_PB14N_CCL_IN9) +#define PORT_PB14N_CCL_IN9 (_UL_(1) << 14) +#define PIN_PC20N_CCL_IN9 _L_(84) /**< \brief CCL signal: IN9 on PC20 mux N */ +#define MUX_PC20N_CCL_IN9 _L_(13) +#define PINMUX_PC20N_CCL_IN9 ((PIN_PC20N_CCL_IN9 << 16) | MUX_PC20N_CCL_IN9) +#define PORT_PC20N_CCL_IN9 (_UL_(1) << 20) +#define PIN_PB15N_CCL_IN10 _L_(47) /**< \brief CCL signal: IN10 on PB15 mux N */ +#define MUX_PB15N_CCL_IN10 _L_(13) +#define PINMUX_PB15N_CCL_IN10 ((PIN_PB15N_CCL_IN10 << 16) | MUX_PB15N_CCL_IN10) +#define PORT_PB15N_CCL_IN10 (_UL_(1) << 15) +#define PIN_PC21N_CCL_IN10 _L_(85) /**< \brief CCL signal: IN10 on PC21 mux N */ +#define MUX_PC21N_CCL_IN10 _L_(13) +#define PINMUX_PC21N_CCL_IN10 ((PIN_PC21N_CCL_IN10 << 16) | MUX_PC21N_CCL_IN10) +#define PORT_PC21N_CCL_IN10 (_UL_(1) << 21) +#define PIN_PB10N_CCL_IN11 _L_(42) /**< \brief CCL signal: IN11 on PB10 mux N */ +#define MUX_PB10N_CCL_IN11 _L_(13) +#define PINMUX_PB10N_CCL_IN11 ((PIN_PB10N_CCL_IN11 << 16) | MUX_PB10N_CCL_IN11) +#define PORT_PB10N_CCL_IN11 (_UL_(1) << 10) +#define PIN_PB16N_CCL_IN11 _L_(48) /**< \brief CCL signal: IN11 on PB16 mux N */ +#define MUX_PB16N_CCL_IN11 _L_(13) +#define PINMUX_PB16N_CCL_IN11 ((PIN_PB16N_CCL_IN11 << 16) | MUX_PB16N_CCL_IN11) +#define PORT_PB16N_CCL_IN11 (_UL_(1) << 16) +#define PIN_PA07N_CCL_OUT0 _L_(7) /**< \brief CCL signal: OUT0 on PA07 mux N */ +#define MUX_PA07N_CCL_OUT0 _L_(13) +#define PINMUX_PA07N_CCL_OUT0 ((PIN_PA07N_CCL_OUT0 << 16) | MUX_PA07N_CCL_OUT0) +#define PORT_PA07N_CCL_OUT0 (_UL_(1) << 7) +#define PIN_PA19N_CCL_OUT0 _L_(19) /**< \brief CCL signal: OUT0 on PA19 mux N */ +#define MUX_PA19N_CCL_OUT0 _L_(13) +#define PINMUX_PA19N_CCL_OUT0 ((PIN_PA19N_CCL_OUT0 << 16) | MUX_PA19N_CCL_OUT0) +#define PORT_PA19N_CCL_OUT0 (_UL_(1) << 19) +#define PIN_PB02N_CCL_OUT0 _L_(34) /**< \brief CCL signal: OUT0 on PB02 mux N */ +#define MUX_PB02N_CCL_OUT0 _L_(13) +#define PINMUX_PB02N_CCL_OUT0 ((PIN_PB02N_CCL_OUT0 << 16) | MUX_PB02N_CCL_OUT0) +#define PORT_PB02N_CCL_OUT0 (_UL_(1) << 2) +#define PIN_PB23N_CCL_OUT0 _L_(55) /**< \brief CCL signal: OUT0 on PB23 mux N */ +#define MUX_PB23N_CCL_OUT0 _L_(13) +#define PINMUX_PB23N_CCL_OUT0 ((PIN_PB23N_CCL_OUT0 << 16) | MUX_PB23N_CCL_OUT0) +#define PORT_PB23N_CCL_OUT0 (_UL_(1) << 23) +#define PIN_PA11N_CCL_OUT1 _L_(11) /**< \brief CCL signal: OUT1 on PA11 mux N */ +#define MUX_PA11N_CCL_OUT1 _L_(13) +#define PINMUX_PA11N_CCL_OUT1 ((PIN_PA11N_CCL_OUT1 << 16) | MUX_PA11N_CCL_OUT1) +#define PORT_PA11N_CCL_OUT1 (_UL_(1) << 11) +#define PIN_PA31N_CCL_OUT1 _L_(31) /**< \brief CCL signal: OUT1 on PA31 mux N */ +#define MUX_PA31N_CCL_OUT1 _L_(13) +#define PINMUX_PA31N_CCL_OUT1 ((PIN_PA31N_CCL_OUT1 << 16) | MUX_PA31N_CCL_OUT1) +#define PORT_PA31N_CCL_OUT1 (_UL_(1) << 31) +#define PIN_PB11N_CCL_OUT1 _L_(43) /**< \brief CCL signal: OUT1 on PB11 mux N */ +#define MUX_PB11N_CCL_OUT1 _L_(13) +#define PINMUX_PB11N_CCL_OUT1 ((PIN_PB11N_CCL_OUT1 << 16) | MUX_PB11N_CCL_OUT1) +#define PORT_PB11N_CCL_OUT1 (_UL_(1) << 11) +#define PIN_PA25N_CCL_OUT2 _L_(25) /**< \brief CCL signal: OUT2 on PA25 mux N */ +#define MUX_PA25N_CCL_OUT2 _L_(13) +#define PINMUX_PA25N_CCL_OUT2 ((PIN_PA25N_CCL_OUT2 << 16) | MUX_PA25N_CCL_OUT2) +#define PORT_PA25N_CCL_OUT2 (_UL_(1) << 25) +#define PIN_PB09N_CCL_OUT2 _L_(41) /**< \brief CCL signal: OUT2 on PB09 mux N */ +#define MUX_PB09N_CCL_OUT2 _L_(13) +#define PINMUX_PB09N_CCL_OUT2 ((PIN_PB09N_CCL_OUT2 << 16) | MUX_PB09N_CCL_OUT2) +#define PORT_PB09N_CCL_OUT2 (_UL_(1) << 9) +#define PIN_PB17N_CCL_OUT3 _L_(49) /**< \brief CCL signal: OUT3 on PB17 mux N */ +#define MUX_PB17N_CCL_OUT3 _L_(13) +#define PINMUX_PB17N_CCL_OUT3 ((PIN_PB17N_CCL_OUT3 << 16) | MUX_PB17N_CCL_OUT3) +#define PORT_PB17N_CCL_OUT3 (_UL_(1) << 17) +/* ========== PORT definition for SERCOM4 peripheral ========== */ +#define PIN_PA13D_SERCOM4_PAD0 _L_(13) /**< \brief SERCOM4 signal: PAD0 on PA13 mux D */ +#define MUX_PA13D_SERCOM4_PAD0 _L_(3) +#define PINMUX_PA13D_SERCOM4_PAD0 ((PIN_PA13D_SERCOM4_PAD0 << 16) | MUX_PA13D_SERCOM4_PAD0) +#define PORT_PA13D_SERCOM4_PAD0 (_UL_(1) << 13) +#define PIN_PB08D_SERCOM4_PAD0 _L_(40) /**< \brief SERCOM4 signal: PAD0 on PB08 mux D */ +#define MUX_PB08D_SERCOM4_PAD0 _L_(3) +#define PINMUX_PB08D_SERCOM4_PAD0 ((PIN_PB08D_SERCOM4_PAD0 << 16) | MUX_PB08D_SERCOM4_PAD0) +#define PORT_PB08D_SERCOM4_PAD0 (_UL_(1) << 8) +#define PIN_PB12C_SERCOM4_PAD0 _L_(44) /**< \brief SERCOM4 signal: PAD0 on PB12 mux C */ +#define MUX_PB12C_SERCOM4_PAD0 _L_(2) +#define PINMUX_PB12C_SERCOM4_PAD0 ((PIN_PB12C_SERCOM4_PAD0 << 16) | MUX_PB12C_SERCOM4_PAD0) +#define PORT_PB12C_SERCOM4_PAD0 (_UL_(1) << 12) +#define PIN_PA12D_SERCOM4_PAD1 _L_(12) /**< \brief SERCOM4 signal: PAD1 on PA12 mux D */ +#define MUX_PA12D_SERCOM4_PAD1 _L_(3) +#define PINMUX_PA12D_SERCOM4_PAD1 ((PIN_PA12D_SERCOM4_PAD1 << 16) | MUX_PA12D_SERCOM4_PAD1) +#define PORT_PA12D_SERCOM4_PAD1 (_UL_(1) << 12) +#define PIN_PB09D_SERCOM4_PAD1 _L_(41) /**< \brief SERCOM4 signal: PAD1 on PB09 mux D */ +#define MUX_PB09D_SERCOM4_PAD1 _L_(3) +#define PINMUX_PB09D_SERCOM4_PAD1 ((PIN_PB09D_SERCOM4_PAD1 << 16) | MUX_PB09D_SERCOM4_PAD1) +#define PORT_PB09D_SERCOM4_PAD1 (_UL_(1) << 9) +#define PIN_PB13C_SERCOM4_PAD1 _L_(45) /**< \brief SERCOM4 signal: PAD1 on PB13 mux C */ +#define MUX_PB13C_SERCOM4_PAD1 _L_(2) +#define PINMUX_PB13C_SERCOM4_PAD1 ((PIN_PB13C_SERCOM4_PAD1 << 16) | MUX_PB13C_SERCOM4_PAD1) +#define PORT_PB13C_SERCOM4_PAD1 (_UL_(1) << 13) +#define PIN_PA14D_SERCOM4_PAD2 _L_(14) /**< \brief SERCOM4 signal: PAD2 on PA14 mux D */ +#define MUX_PA14D_SERCOM4_PAD2 _L_(3) +#define PINMUX_PA14D_SERCOM4_PAD2 ((PIN_PA14D_SERCOM4_PAD2 << 16) | MUX_PA14D_SERCOM4_PAD2) +#define PORT_PA14D_SERCOM4_PAD2 (_UL_(1) << 14) +#define PIN_PB10D_SERCOM4_PAD2 _L_(42) /**< \brief SERCOM4 signal: PAD2 on PB10 mux D */ +#define MUX_PB10D_SERCOM4_PAD2 _L_(3) +#define PINMUX_PB10D_SERCOM4_PAD2 ((PIN_PB10D_SERCOM4_PAD2 << 16) | MUX_PB10D_SERCOM4_PAD2) +#define PORT_PB10D_SERCOM4_PAD2 (_UL_(1) << 10) +#define PIN_PB14C_SERCOM4_PAD2 _L_(46) /**< \brief SERCOM4 signal: PAD2 on PB14 mux C */ +#define MUX_PB14C_SERCOM4_PAD2 _L_(2) +#define PINMUX_PB14C_SERCOM4_PAD2 ((PIN_PB14C_SERCOM4_PAD2 << 16) | MUX_PB14C_SERCOM4_PAD2) +#define PORT_PB14C_SERCOM4_PAD2 (_UL_(1) << 14) +#define PIN_PB11D_SERCOM4_PAD3 _L_(43) /**< \brief SERCOM4 signal: PAD3 on PB11 mux D */ +#define MUX_PB11D_SERCOM4_PAD3 _L_(3) +#define PINMUX_PB11D_SERCOM4_PAD3 ((PIN_PB11D_SERCOM4_PAD3 << 16) | MUX_PB11D_SERCOM4_PAD3) +#define PORT_PB11D_SERCOM4_PAD3 (_UL_(1) << 11) +#define PIN_PA15D_SERCOM4_PAD3 _L_(15) /**< \brief SERCOM4 signal: PAD3 on PA15 mux D */ +#define MUX_PA15D_SERCOM4_PAD3 _L_(3) +#define PINMUX_PA15D_SERCOM4_PAD3 ((PIN_PA15D_SERCOM4_PAD3 << 16) | MUX_PA15D_SERCOM4_PAD3) +#define PORT_PA15D_SERCOM4_PAD3 (_UL_(1) << 15) +#define PIN_PB15C_SERCOM4_PAD3 _L_(47) /**< \brief SERCOM4 signal: PAD3 on PB15 mux C */ +#define MUX_PB15C_SERCOM4_PAD3 _L_(2) +#define PINMUX_PB15C_SERCOM4_PAD3 ((PIN_PB15C_SERCOM4_PAD3 << 16) | MUX_PB15C_SERCOM4_PAD3) +#define PORT_PB15C_SERCOM4_PAD3 (_UL_(1) << 15) +/* ========== PORT definition for SERCOM5 peripheral ========== */ +#define PIN_PA23D_SERCOM5_PAD0 _L_(23) /**< \brief SERCOM5 signal: PAD0 on PA23 mux D */ +#define MUX_PA23D_SERCOM5_PAD0 _L_(3) +#define PINMUX_PA23D_SERCOM5_PAD0 ((PIN_PA23D_SERCOM5_PAD0 << 16) | MUX_PA23D_SERCOM5_PAD0) +#define PORT_PA23D_SERCOM5_PAD0 (_UL_(1) << 23) +#define PIN_PB02D_SERCOM5_PAD0 _L_(34) /**< \brief SERCOM5 signal: PAD0 on PB02 mux D */ +#define MUX_PB02D_SERCOM5_PAD0 _L_(3) +#define PINMUX_PB02D_SERCOM5_PAD0 ((PIN_PB02D_SERCOM5_PAD0 << 16) | MUX_PB02D_SERCOM5_PAD0) +#define PORT_PB02D_SERCOM5_PAD0 (_UL_(1) << 2) +#define PIN_PB31D_SERCOM5_PAD0 _L_(63) /**< \brief SERCOM5 signal: PAD0 on PB31 mux D */ +#define MUX_PB31D_SERCOM5_PAD0 _L_(3) +#define PINMUX_PB31D_SERCOM5_PAD0 ((PIN_PB31D_SERCOM5_PAD0 << 16) | MUX_PB31D_SERCOM5_PAD0) +#define PORT_PB31D_SERCOM5_PAD0 (_UL_(1) << 31) +#define PIN_PB16C_SERCOM5_PAD0 _L_(48) /**< \brief SERCOM5 signal: PAD0 on PB16 mux C */ +#define MUX_PB16C_SERCOM5_PAD0 _L_(2) +#define PINMUX_PB16C_SERCOM5_PAD0 ((PIN_PB16C_SERCOM5_PAD0 << 16) | MUX_PB16C_SERCOM5_PAD0) +#define PORT_PB16C_SERCOM5_PAD0 (_UL_(1) << 16) +#define PIN_PA22D_SERCOM5_PAD1 _L_(22) /**< \brief SERCOM5 signal: PAD1 on PA22 mux D */ +#define MUX_PA22D_SERCOM5_PAD1 _L_(3) +#define PINMUX_PA22D_SERCOM5_PAD1 ((PIN_PA22D_SERCOM5_PAD1 << 16) | MUX_PA22D_SERCOM5_PAD1) +#define PORT_PA22D_SERCOM5_PAD1 (_UL_(1) << 22) +#define PIN_PB03D_SERCOM5_PAD1 _L_(35) /**< \brief SERCOM5 signal: PAD1 on PB03 mux D */ +#define MUX_PB03D_SERCOM5_PAD1 _L_(3) +#define PINMUX_PB03D_SERCOM5_PAD1 ((PIN_PB03D_SERCOM5_PAD1 << 16) | MUX_PB03D_SERCOM5_PAD1) +#define PORT_PB03D_SERCOM5_PAD1 (_UL_(1) << 3) +#define PIN_PB30D_SERCOM5_PAD1 _L_(62) /**< \brief SERCOM5 signal: PAD1 on PB30 mux D */ +#define MUX_PB30D_SERCOM5_PAD1 _L_(3) +#define PINMUX_PB30D_SERCOM5_PAD1 ((PIN_PB30D_SERCOM5_PAD1 << 16) | MUX_PB30D_SERCOM5_PAD1) +#define PORT_PB30D_SERCOM5_PAD1 (_UL_(1) << 30) +#define PIN_PB17C_SERCOM5_PAD1 _L_(49) /**< \brief SERCOM5 signal: PAD1 on PB17 mux C */ +#define MUX_PB17C_SERCOM5_PAD1 _L_(2) +#define PINMUX_PB17C_SERCOM5_PAD1 ((PIN_PB17C_SERCOM5_PAD1 << 16) | MUX_PB17C_SERCOM5_PAD1) +#define PORT_PB17C_SERCOM5_PAD1 (_UL_(1) << 17) +#define PIN_PA24D_SERCOM5_PAD2 _L_(24) /**< \brief SERCOM5 signal: PAD2 on PA24 mux D */ +#define MUX_PA24D_SERCOM5_PAD2 _L_(3) +#define PINMUX_PA24D_SERCOM5_PAD2 ((PIN_PA24D_SERCOM5_PAD2 << 16) | MUX_PA24D_SERCOM5_PAD2) +#define PORT_PA24D_SERCOM5_PAD2 (_UL_(1) << 24) +#define PIN_PB00D_SERCOM5_PAD2 _L_(32) /**< \brief SERCOM5 signal: PAD2 on PB00 mux D */ +#define MUX_PB00D_SERCOM5_PAD2 _L_(3) +#define PINMUX_PB00D_SERCOM5_PAD2 ((PIN_PB00D_SERCOM5_PAD2 << 16) | MUX_PB00D_SERCOM5_PAD2) +#define PORT_PB00D_SERCOM5_PAD2 (_UL_(1) << 0) +#define PIN_PB22D_SERCOM5_PAD2 _L_(54) /**< \brief SERCOM5 signal: PAD2 on PB22 mux D */ +#define MUX_PB22D_SERCOM5_PAD2 _L_(3) +#define PINMUX_PB22D_SERCOM5_PAD2 ((PIN_PB22D_SERCOM5_PAD2 << 16) | MUX_PB22D_SERCOM5_PAD2) +#define PORT_PB22D_SERCOM5_PAD2 (_UL_(1) << 22) +#define PIN_PA20C_SERCOM5_PAD2 _L_(20) /**< \brief SERCOM5 signal: PAD2 on PA20 mux C */ +#define MUX_PA20C_SERCOM5_PAD2 _L_(2) +#define PINMUX_PA20C_SERCOM5_PAD2 ((PIN_PA20C_SERCOM5_PAD2 << 16) | MUX_PA20C_SERCOM5_PAD2) +#define PORT_PA20C_SERCOM5_PAD2 (_UL_(1) << 20) +#define PIN_PB18C_SERCOM5_PAD2 _L_(50) /**< \brief SERCOM5 signal: PAD2 on PB18 mux C */ +#define MUX_PB18C_SERCOM5_PAD2 _L_(2) +#define PINMUX_PB18C_SERCOM5_PAD2 ((PIN_PB18C_SERCOM5_PAD2 << 16) | MUX_PB18C_SERCOM5_PAD2) +#define PORT_PB18C_SERCOM5_PAD2 (_UL_(1) << 18) +#define PIN_PA25D_SERCOM5_PAD3 _L_(25) /**< \brief SERCOM5 signal: PAD3 on PA25 mux D */ +#define MUX_PA25D_SERCOM5_PAD3 _L_(3) +#define PINMUX_PA25D_SERCOM5_PAD3 ((PIN_PA25D_SERCOM5_PAD3 << 16) | MUX_PA25D_SERCOM5_PAD3) +#define PORT_PA25D_SERCOM5_PAD3 (_UL_(1) << 25) +#define PIN_PB01D_SERCOM5_PAD3 _L_(33) /**< \brief SERCOM5 signal: PAD3 on PB01 mux D */ +#define MUX_PB01D_SERCOM5_PAD3 _L_(3) +#define PINMUX_PB01D_SERCOM5_PAD3 ((PIN_PB01D_SERCOM5_PAD3 << 16) | MUX_PB01D_SERCOM5_PAD3) +#define PORT_PB01D_SERCOM5_PAD3 (_UL_(1) << 1) +#define PIN_PB23D_SERCOM5_PAD3 _L_(55) /**< \brief SERCOM5 signal: PAD3 on PB23 mux D */ +#define MUX_PB23D_SERCOM5_PAD3 _L_(3) +#define PINMUX_PB23D_SERCOM5_PAD3 ((PIN_PB23D_SERCOM5_PAD3 << 16) | MUX_PB23D_SERCOM5_PAD3) +#define PORT_PB23D_SERCOM5_PAD3 (_UL_(1) << 23) +#define PIN_PA21C_SERCOM5_PAD3 _L_(21) /**< \brief SERCOM5 signal: PAD3 on PA21 mux C */ +#define MUX_PA21C_SERCOM5_PAD3 _L_(2) +#define PINMUX_PA21C_SERCOM5_PAD3 ((PIN_PA21C_SERCOM5_PAD3 << 16) | MUX_PA21C_SERCOM5_PAD3) +#define PORT_PA21C_SERCOM5_PAD3 (_UL_(1) << 21) +#define PIN_PB19C_SERCOM5_PAD3 _L_(51) /**< \brief SERCOM5 signal: PAD3 on PB19 mux C */ +#define MUX_PB19C_SERCOM5_PAD3 _L_(2) +#define PINMUX_PB19C_SERCOM5_PAD3 ((PIN_PB19C_SERCOM5_PAD3 << 16) | MUX_PB19C_SERCOM5_PAD3) +#define PORT_PB19C_SERCOM5_PAD3 (_UL_(1) << 19) +/* ========== PORT definition for SERCOM6 peripheral ========== */ +#define PIN_PC13D_SERCOM6_PAD0 _L_(77) /**< \brief SERCOM6 signal: PAD0 on PC13 mux D */ +#define MUX_PC13D_SERCOM6_PAD0 _L_(3) +#define PINMUX_PC13D_SERCOM6_PAD0 ((PIN_PC13D_SERCOM6_PAD0 << 16) | MUX_PC13D_SERCOM6_PAD0) +#define PORT_PC13D_SERCOM6_PAD0 (_UL_(1) << 13) +#define PIN_PC16C_SERCOM6_PAD0 _L_(80) /**< \brief SERCOM6 signal: PAD0 on PC16 mux C */ +#define MUX_PC16C_SERCOM6_PAD0 _L_(2) +#define PINMUX_PC16C_SERCOM6_PAD0 ((PIN_PC16C_SERCOM6_PAD0 << 16) | MUX_PC16C_SERCOM6_PAD0) +#define PORT_PC16C_SERCOM6_PAD0 (_UL_(1) << 16) +#define PIN_PC12D_SERCOM6_PAD1 _L_(76) /**< \brief SERCOM6 signal: PAD1 on PC12 mux D */ +#define MUX_PC12D_SERCOM6_PAD1 _L_(3) +#define PINMUX_PC12D_SERCOM6_PAD1 ((PIN_PC12D_SERCOM6_PAD1 << 16) | MUX_PC12D_SERCOM6_PAD1) +#define PORT_PC12D_SERCOM6_PAD1 (_UL_(1) << 12) +#define PIN_PC05C_SERCOM6_PAD1 _L_(69) /**< \brief SERCOM6 signal: PAD1 on PC05 mux C */ +#define MUX_PC05C_SERCOM6_PAD1 _L_(2) +#define PINMUX_PC05C_SERCOM6_PAD1 ((PIN_PC05C_SERCOM6_PAD1 << 16) | MUX_PC05C_SERCOM6_PAD1) +#define PORT_PC05C_SERCOM6_PAD1 (_UL_(1) << 5) +#define PIN_PC17C_SERCOM6_PAD1 _L_(81) /**< \brief SERCOM6 signal: PAD1 on PC17 mux C */ +#define MUX_PC17C_SERCOM6_PAD1 _L_(2) +#define PINMUX_PC17C_SERCOM6_PAD1 ((PIN_PC17C_SERCOM6_PAD1 << 16) | MUX_PC17C_SERCOM6_PAD1) +#define PORT_PC17C_SERCOM6_PAD1 (_UL_(1) << 17) +#define PIN_PC14D_SERCOM6_PAD2 _L_(78) /**< \brief SERCOM6 signal: PAD2 on PC14 mux D */ +#define MUX_PC14D_SERCOM6_PAD2 _L_(3) +#define PINMUX_PC14D_SERCOM6_PAD2 ((PIN_PC14D_SERCOM6_PAD2 << 16) | MUX_PC14D_SERCOM6_PAD2) +#define PORT_PC14D_SERCOM6_PAD2 (_UL_(1) << 14) +#define PIN_PC06C_SERCOM6_PAD2 _L_(70) /**< \brief SERCOM6 signal: PAD2 on PC06 mux C */ +#define MUX_PC06C_SERCOM6_PAD2 _L_(2) +#define PINMUX_PC06C_SERCOM6_PAD2 ((PIN_PC06C_SERCOM6_PAD2 << 16) | MUX_PC06C_SERCOM6_PAD2) +#define PORT_PC06C_SERCOM6_PAD2 (_UL_(1) << 6) +#define PIN_PC10C_SERCOM6_PAD2 _L_(74) /**< \brief SERCOM6 signal: PAD2 on PC10 mux C */ +#define MUX_PC10C_SERCOM6_PAD2 _L_(2) +#define PINMUX_PC10C_SERCOM6_PAD2 ((PIN_PC10C_SERCOM6_PAD2 << 16) | MUX_PC10C_SERCOM6_PAD2) +#define PORT_PC10C_SERCOM6_PAD2 (_UL_(1) << 10) +#define PIN_PC18C_SERCOM6_PAD2 _L_(82) /**< \brief SERCOM6 signal: PAD2 on PC18 mux C */ +#define MUX_PC18C_SERCOM6_PAD2 _L_(2) +#define PINMUX_PC18C_SERCOM6_PAD2 ((PIN_PC18C_SERCOM6_PAD2 << 16) | MUX_PC18C_SERCOM6_PAD2) +#define PORT_PC18C_SERCOM6_PAD2 (_UL_(1) << 18) +#define PIN_PC15D_SERCOM6_PAD3 _L_(79) /**< \brief SERCOM6 signal: PAD3 on PC15 mux D */ +#define MUX_PC15D_SERCOM6_PAD3 _L_(3) +#define PINMUX_PC15D_SERCOM6_PAD3 ((PIN_PC15D_SERCOM6_PAD3 << 16) | MUX_PC15D_SERCOM6_PAD3) +#define PORT_PC15D_SERCOM6_PAD3 (_UL_(1) << 15) +#define PIN_PC07C_SERCOM6_PAD3 _L_(71) /**< \brief SERCOM6 signal: PAD3 on PC07 mux C */ +#define MUX_PC07C_SERCOM6_PAD3 _L_(2) +#define PINMUX_PC07C_SERCOM6_PAD3 ((PIN_PC07C_SERCOM6_PAD3 << 16) | MUX_PC07C_SERCOM6_PAD3) +#define PORT_PC07C_SERCOM6_PAD3 (_UL_(1) << 7) +#define PIN_PC11C_SERCOM6_PAD3 _L_(75) /**< \brief SERCOM6 signal: PAD3 on PC11 mux C */ +#define MUX_PC11C_SERCOM6_PAD3 _L_(2) +#define PINMUX_PC11C_SERCOM6_PAD3 ((PIN_PC11C_SERCOM6_PAD3 << 16) | MUX_PC11C_SERCOM6_PAD3) +#define PORT_PC11C_SERCOM6_PAD3 (_UL_(1) << 11) +#define PIN_PC19C_SERCOM6_PAD3 _L_(83) /**< \brief SERCOM6 signal: PAD3 on PC19 mux C */ +#define MUX_PC19C_SERCOM6_PAD3 _L_(2) +#define PINMUX_PC19C_SERCOM6_PAD3 ((PIN_PC19C_SERCOM6_PAD3 << 16) | MUX_PC19C_SERCOM6_PAD3) +#define PORT_PC19C_SERCOM6_PAD3 (_UL_(1) << 19) +/* ========== PORT definition for SERCOM7 peripheral ========== */ +#define PIN_PB21D_SERCOM7_PAD0 _L_(53) /**< \brief SERCOM7 signal: PAD0 on PB21 mux D */ +#define MUX_PB21D_SERCOM7_PAD0 _L_(3) +#define PINMUX_PB21D_SERCOM7_PAD0 ((PIN_PB21D_SERCOM7_PAD0 << 16) | MUX_PB21D_SERCOM7_PAD0) +#define PORT_PB21D_SERCOM7_PAD0 (_UL_(1) << 21) +#define PIN_PB30C_SERCOM7_PAD0 _L_(62) /**< \brief SERCOM7 signal: PAD0 on PB30 mux C */ +#define MUX_PB30C_SERCOM7_PAD0 _L_(2) +#define PINMUX_PB30C_SERCOM7_PAD0 ((PIN_PB30C_SERCOM7_PAD0 << 16) | MUX_PB30C_SERCOM7_PAD0) +#define PORT_PB30C_SERCOM7_PAD0 (_UL_(1) << 30) +#define PIN_PC12C_SERCOM7_PAD0 _L_(76) /**< \brief SERCOM7 signal: PAD0 on PC12 mux C */ +#define MUX_PC12C_SERCOM7_PAD0 _L_(2) +#define PINMUX_PC12C_SERCOM7_PAD0 ((PIN_PC12C_SERCOM7_PAD0 << 16) | MUX_PC12C_SERCOM7_PAD0) +#define PORT_PC12C_SERCOM7_PAD0 (_UL_(1) << 12) +#define PIN_PB20D_SERCOM7_PAD1 _L_(52) /**< \brief SERCOM7 signal: PAD1 on PB20 mux D */ +#define MUX_PB20D_SERCOM7_PAD1 _L_(3) +#define PINMUX_PB20D_SERCOM7_PAD1 ((PIN_PB20D_SERCOM7_PAD1 << 16) | MUX_PB20D_SERCOM7_PAD1) +#define PORT_PB20D_SERCOM7_PAD1 (_UL_(1) << 20) +#define PIN_PB31C_SERCOM7_PAD1 _L_(63) /**< \brief SERCOM7 signal: PAD1 on PB31 mux C */ +#define MUX_PB31C_SERCOM7_PAD1 _L_(2) +#define PINMUX_PB31C_SERCOM7_PAD1 ((PIN_PB31C_SERCOM7_PAD1 << 16) | MUX_PB31C_SERCOM7_PAD1) +#define PORT_PB31C_SERCOM7_PAD1 (_UL_(1) << 31) +#define PIN_PC13C_SERCOM7_PAD1 _L_(77) /**< \brief SERCOM7 signal: PAD1 on PC13 mux C */ +#define MUX_PC13C_SERCOM7_PAD1 _L_(2) +#define PINMUX_PC13C_SERCOM7_PAD1 ((PIN_PC13C_SERCOM7_PAD1 << 16) | MUX_PC13C_SERCOM7_PAD1) +#define PORT_PC13C_SERCOM7_PAD1 (_UL_(1) << 13) +#define PIN_PB18D_SERCOM7_PAD2 _L_(50) /**< \brief SERCOM7 signal: PAD2 on PB18 mux D */ +#define MUX_PB18D_SERCOM7_PAD2 _L_(3) +#define PINMUX_PB18D_SERCOM7_PAD2 ((PIN_PB18D_SERCOM7_PAD2 << 16) | MUX_PB18D_SERCOM7_PAD2) +#define PORT_PB18D_SERCOM7_PAD2 (_UL_(1) << 18) +#define PIN_PC10D_SERCOM7_PAD2 _L_(74) /**< \brief SERCOM7 signal: PAD2 on PC10 mux D */ +#define MUX_PC10D_SERCOM7_PAD2 _L_(3) +#define PINMUX_PC10D_SERCOM7_PAD2 ((PIN_PC10D_SERCOM7_PAD2 << 16) | MUX_PC10D_SERCOM7_PAD2) +#define PORT_PC10D_SERCOM7_PAD2 (_UL_(1) << 10) +#define PIN_PC14C_SERCOM7_PAD2 _L_(78) /**< \brief SERCOM7 signal: PAD2 on PC14 mux C */ +#define MUX_PC14C_SERCOM7_PAD2 _L_(2) +#define PINMUX_PC14C_SERCOM7_PAD2 ((PIN_PC14C_SERCOM7_PAD2 << 16) | MUX_PC14C_SERCOM7_PAD2) +#define PORT_PC14C_SERCOM7_PAD2 (_UL_(1) << 14) +#define PIN_PA30C_SERCOM7_PAD2 _L_(30) /**< \brief SERCOM7 signal: PAD2 on PA30 mux C */ +#define MUX_PA30C_SERCOM7_PAD2 _L_(2) +#define PINMUX_PA30C_SERCOM7_PAD2 ((PIN_PA30C_SERCOM7_PAD2 << 16) | MUX_PA30C_SERCOM7_PAD2) +#define PORT_PA30C_SERCOM7_PAD2 (_UL_(1) << 30) +#define PIN_PB19D_SERCOM7_PAD3 _L_(51) /**< \brief SERCOM7 signal: PAD3 on PB19 mux D */ +#define MUX_PB19D_SERCOM7_PAD3 _L_(3) +#define PINMUX_PB19D_SERCOM7_PAD3 ((PIN_PB19D_SERCOM7_PAD3 << 16) | MUX_PB19D_SERCOM7_PAD3) +#define PORT_PB19D_SERCOM7_PAD3 (_UL_(1) << 19) +#define PIN_PC11D_SERCOM7_PAD3 _L_(75) /**< \brief SERCOM7 signal: PAD3 on PC11 mux D */ +#define MUX_PC11D_SERCOM7_PAD3 _L_(3) +#define PINMUX_PC11D_SERCOM7_PAD3 ((PIN_PC11D_SERCOM7_PAD3 << 16) | MUX_PC11D_SERCOM7_PAD3) +#define PORT_PC11D_SERCOM7_PAD3 (_UL_(1) << 11) +#define PIN_PC15C_SERCOM7_PAD3 _L_(79) /**< \brief SERCOM7 signal: PAD3 on PC15 mux C */ +#define MUX_PC15C_SERCOM7_PAD3 _L_(2) +#define PINMUX_PC15C_SERCOM7_PAD3 ((PIN_PC15C_SERCOM7_PAD3 << 16) | MUX_PC15C_SERCOM7_PAD3) +#define PORT_PC15C_SERCOM7_PAD3 (_UL_(1) << 15) +#define PIN_PA31C_SERCOM7_PAD3 _L_(31) /**< \brief SERCOM7 signal: PAD3 on PA31 mux C */ +#define MUX_PA31C_SERCOM7_PAD3 _L_(2) +#define PINMUX_PA31C_SERCOM7_PAD3 ((PIN_PA31C_SERCOM7_PAD3 << 16) | MUX_PA31C_SERCOM7_PAD3) +#define PORT_PA31C_SERCOM7_PAD3 (_UL_(1) << 31) +/* ========== PORT definition for TCC4 peripheral ========== */ +#define PIN_PB14F_TCC4_WO0 _L_(46) /**< \brief TCC4 signal: WO0 on PB14 mux F */ +#define MUX_PB14F_TCC4_WO0 _L_(5) +#define PINMUX_PB14F_TCC4_WO0 ((PIN_PB14F_TCC4_WO0 << 16) | MUX_PB14F_TCC4_WO0) +#define PORT_PB14F_TCC4_WO0 (_UL_(1) << 14) +#define PIN_PB30F_TCC4_WO0 _L_(62) /**< \brief TCC4 signal: WO0 on PB30 mux F */ +#define MUX_PB30F_TCC4_WO0 _L_(5) +#define PINMUX_PB30F_TCC4_WO0 ((PIN_PB30F_TCC4_WO0 << 16) | MUX_PB30F_TCC4_WO0) +#define PORT_PB30F_TCC4_WO0 (_UL_(1) << 30) +#define PIN_PB15F_TCC4_WO1 _L_(47) /**< \brief TCC4 signal: WO1 on PB15 mux F */ +#define MUX_PB15F_TCC4_WO1 _L_(5) +#define PINMUX_PB15F_TCC4_WO1 ((PIN_PB15F_TCC4_WO1 << 16) | MUX_PB15F_TCC4_WO1) +#define PORT_PB15F_TCC4_WO1 (_UL_(1) << 15) +#define PIN_PB31F_TCC4_WO1 _L_(63) /**< \brief TCC4 signal: WO1 on PB31 mux F */ +#define MUX_PB31F_TCC4_WO1 _L_(5) +#define PINMUX_PB31F_TCC4_WO1 ((PIN_PB31F_TCC4_WO1 << 16) | MUX_PB31F_TCC4_WO1) +#define PORT_PB31F_TCC4_WO1 (_UL_(1) << 31) +/* ========== PORT definition for TC6 peripheral ========== */ +#define PIN_PA30E_TC6_WO0 _L_(30) /**< \brief TC6 signal: WO0 on PA30 mux E */ +#define MUX_PA30E_TC6_WO0 _L_(4) +#define PINMUX_PA30E_TC6_WO0 ((PIN_PA30E_TC6_WO0 << 16) | MUX_PA30E_TC6_WO0) +#define PORT_PA30E_TC6_WO0 (_UL_(1) << 30) +#define PIN_PB02E_TC6_WO0 _L_(34) /**< \brief TC6 signal: WO0 on PB02 mux E */ +#define MUX_PB02E_TC6_WO0 _L_(4) +#define PINMUX_PB02E_TC6_WO0 ((PIN_PB02E_TC6_WO0 << 16) | MUX_PB02E_TC6_WO0) +#define PORT_PB02E_TC6_WO0 (_UL_(1) << 2) +#define PIN_PB16E_TC6_WO0 _L_(48) /**< \brief TC6 signal: WO0 on PB16 mux E */ +#define MUX_PB16E_TC6_WO0 _L_(4) +#define PINMUX_PB16E_TC6_WO0 ((PIN_PB16E_TC6_WO0 << 16) | MUX_PB16E_TC6_WO0) +#define PORT_PB16E_TC6_WO0 (_UL_(1) << 16) +#define PIN_PA31E_TC6_WO1 _L_(31) /**< \brief TC6 signal: WO1 on PA31 mux E */ +#define MUX_PA31E_TC6_WO1 _L_(4) +#define PINMUX_PA31E_TC6_WO1 ((PIN_PA31E_TC6_WO1 << 16) | MUX_PA31E_TC6_WO1) +#define PORT_PA31E_TC6_WO1 (_UL_(1) << 31) +#define PIN_PB03E_TC6_WO1 _L_(35) /**< \brief TC6 signal: WO1 on PB03 mux E */ +#define MUX_PB03E_TC6_WO1 _L_(4) +#define PINMUX_PB03E_TC6_WO1 ((PIN_PB03E_TC6_WO1 << 16) | MUX_PB03E_TC6_WO1) +#define PORT_PB03E_TC6_WO1 (_UL_(1) << 3) +#define PIN_PB17E_TC6_WO1 _L_(49) /**< \brief TC6 signal: WO1 on PB17 mux E */ +#define MUX_PB17E_TC6_WO1 _L_(4) +#define PINMUX_PB17E_TC6_WO1 ((PIN_PB17E_TC6_WO1 << 16) | MUX_PB17E_TC6_WO1) +#define PORT_PB17E_TC6_WO1 (_UL_(1) << 17) +/* ========== PORT definition for TC7 peripheral ========== */ +#define PIN_PA20E_TC7_WO0 _L_(20) /**< \brief TC7 signal: WO0 on PA20 mux E */ +#define MUX_PA20E_TC7_WO0 _L_(4) +#define PINMUX_PA20E_TC7_WO0 ((PIN_PA20E_TC7_WO0 << 16) | MUX_PA20E_TC7_WO0) +#define PORT_PA20E_TC7_WO0 (_UL_(1) << 20) +#define PIN_PB00E_TC7_WO0 _L_(32) /**< \brief TC7 signal: WO0 on PB00 mux E */ +#define MUX_PB00E_TC7_WO0 _L_(4) +#define PINMUX_PB00E_TC7_WO0 ((PIN_PB00E_TC7_WO0 << 16) | MUX_PB00E_TC7_WO0) +#define PORT_PB00E_TC7_WO0 (_UL_(1) << 0) +#define PIN_PB22E_TC7_WO0 _L_(54) /**< \brief TC7 signal: WO0 on PB22 mux E */ +#define MUX_PB22E_TC7_WO0 _L_(4) +#define PINMUX_PB22E_TC7_WO0 ((PIN_PB22E_TC7_WO0 << 16) | MUX_PB22E_TC7_WO0) +#define PORT_PB22E_TC7_WO0 (_UL_(1) << 22) +#define PIN_PA21E_TC7_WO1 _L_(21) /**< \brief TC7 signal: WO1 on PA21 mux E */ +#define MUX_PA21E_TC7_WO1 _L_(4) +#define PINMUX_PA21E_TC7_WO1 ((PIN_PA21E_TC7_WO1 << 16) | MUX_PA21E_TC7_WO1) +#define PORT_PA21E_TC7_WO1 (_UL_(1) << 21) +#define PIN_PB01E_TC7_WO1 _L_(33) /**< \brief TC7 signal: WO1 on PB01 mux E */ +#define MUX_PB01E_TC7_WO1 _L_(4) +#define PINMUX_PB01E_TC7_WO1 ((PIN_PB01E_TC7_WO1 << 16) | MUX_PB01E_TC7_WO1) +#define PORT_PB01E_TC7_WO1 (_UL_(1) << 1) +#define PIN_PB23E_TC7_WO1 _L_(55) /**< \brief TC7 signal: WO1 on PB23 mux E */ +#define MUX_PB23E_TC7_WO1 _L_(4) +#define PINMUX_PB23E_TC7_WO1 ((PIN_PB23E_TC7_WO1 << 16) | MUX_PB23E_TC7_WO1) +#define PORT_PB23E_TC7_WO1 (_UL_(1) << 23) +/* ========== PORT definition for ADC0 peripheral ========== */ +#define PIN_PA02B_ADC0_AIN0 _L_(2) /**< \brief ADC0 signal: AIN0 on PA02 mux B */ +#define MUX_PA02B_ADC0_AIN0 _L_(1) +#define PINMUX_PA02B_ADC0_AIN0 ((PIN_PA02B_ADC0_AIN0 << 16) | MUX_PA02B_ADC0_AIN0) +#define PORT_PA02B_ADC0_AIN0 (_UL_(1) << 2) +#define PIN_PA03B_ADC0_AIN1 _L_(3) /**< \brief ADC0 signal: AIN1 on PA03 mux B */ +#define MUX_PA03B_ADC0_AIN1 _L_(1) +#define PINMUX_PA03B_ADC0_AIN1 ((PIN_PA03B_ADC0_AIN1 << 16) | MUX_PA03B_ADC0_AIN1) +#define PORT_PA03B_ADC0_AIN1 (_UL_(1) << 3) +#define PIN_PB08B_ADC0_AIN2 _L_(40) /**< \brief ADC0 signal: AIN2 on PB08 mux B */ +#define MUX_PB08B_ADC0_AIN2 _L_(1) +#define PINMUX_PB08B_ADC0_AIN2 ((PIN_PB08B_ADC0_AIN2 << 16) | MUX_PB08B_ADC0_AIN2) +#define PORT_PB08B_ADC0_AIN2 (_UL_(1) << 8) +#define PIN_PB09B_ADC0_AIN3 _L_(41) /**< \brief ADC0 signal: AIN3 on PB09 mux B */ +#define MUX_PB09B_ADC0_AIN3 _L_(1) +#define PINMUX_PB09B_ADC0_AIN3 ((PIN_PB09B_ADC0_AIN3 << 16) | MUX_PB09B_ADC0_AIN3) +#define PORT_PB09B_ADC0_AIN3 (_UL_(1) << 9) +#define PIN_PA04B_ADC0_AIN4 _L_(4) /**< \brief ADC0 signal: AIN4 on PA04 mux B */ +#define MUX_PA04B_ADC0_AIN4 _L_(1) +#define PINMUX_PA04B_ADC0_AIN4 ((PIN_PA04B_ADC0_AIN4 << 16) | MUX_PA04B_ADC0_AIN4) +#define PORT_PA04B_ADC0_AIN4 (_UL_(1) << 4) +#define PIN_PA05B_ADC0_AIN5 _L_(5) /**< \brief ADC0 signal: AIN5 on PA05 mux B */ +#define MUX_PA05B_ADC0_AIN5 _L_(1) +#define PINMUX_PA05B_ADC0_AIN5 ((PIN_PA05B_ADC0_AIN5 << 16) | MUX_PA05B_ADC0_AIN5) +#define PORT_PA05B_ADC0_AIN5 (_UL_(1) << 5) +#define PIN_PA06B_ADC0_AIN6 _L_(6) /**< \brief ADC0 signal: AIN6 on PA06 mux B */ +#define MUX_PA06B_ADC0_AIN6 _L_(1) +#define PINMUX_PA06B_ADC0_AIN6 ((PIN_PA06B_ADC0_AIN6 << 16) | MUX_PA06B_ADC0_AIN6) +#define PORT_PA06B_ADC0_AIN6 (_UL_(1) << 6) +#define PIN_PA07B_ADC0_AIN7 _L_(7) /**< \brief ADC0 signal: AIN7 on PA07 mux B */ +#define MUX_PA07B_ADC0_AIN7 _L_(1) +#define PINMUX_PA07B_ADC0_AIN7 ((PIN_PA07B_ADC0_AIN7 << 16) | MUX_PA07B_ADC0_AIN7) +#define PORT_PA07B_ADC0_AIN7 (_UL_(1) << 7) +#define PIN_PA08B_ADC0_AIN8 _L_(8) /**< \brief ADC0 signal: AIN8 on PA08 mux B */ +#define MUX_PA08B_ADC0_AIN8 _L_(1) +#define PINMUX_PA08B_ADC0_AIN8 ((PIN_PA08B_ADC0_AIN8 << 16) | MUX_PA08B_ADC0_AIN8) +#define PORT_PA08B_ADC0_AIN8 (_UL_(1) << 8) +#define PIN_PA09B_ADC0_AIN9 _L_(9) /**< \brief ADC0 signal: AIN9 on PA09 mux B */ +#define MUX_PA09B_ADC0_AIN9 _L_(1) +#define PINMUX_PA09B_ADC0_AIN9 ((PIN_PA09B_ADC0_AIN9 << 16) | MUX_PA09B_ADC0_AIN9) +#define PORT_PA09B_ADC0_AIN9 (_UL_(1) << 9) +#define PIN_PA10B_ADC0_AIN10 _L_(10) /**< \brief ADC0 signal: AIN10 on PA10 mux B */ +#define MUX_PA10B_ADC0_AIN10 _L_(1) +#define PINMUX_PA10B_ADC0_AIN10 ((PIN_PA10B_ADC0_AIN10 << 16) | MUX_PA10B_ADC0_AIN10) +#define PORT_PA10B_ADC0_AIN10 (_UL_(1) << 10) +#define PIN_PA11B_ADC0_AIN11 _L_(11) /**< \brief ADC0 signal: AIN11 on PA11 mux B */ +#define MUX_PA11B_ADC0_AIN11 _L_(1) +#define PINMUX_PA11B_ADC0_AIN11 ((PIN_PA11B_ADC0_AIN11 << 16) | MUX_PA11B_ADC0_AIN11) +#define PORT_PA11B_ADC0_AIN11 (_UL_(1) << 11) +#define PIN_PB00B_ADC0_AIN12 _L_(32) /**< \brief ADC0 signal: AIN12 on PB00 mux B */ +#define MUX_PB00B_ADC0_AIN12 _L_(1) +#define PINMUX_PB00B_ADC0_AIN12 ((PIN_PB00B_ADC0_AIN12 << 16) | MUX_PB00B_ADC0_AIN12) +#define PORT_PB00B_ADC0_AIN12 (_UL_(1) << 0) +#define PIN_PB01B_ADC0_AIN13 _L_(33) /**< \brief ADC0 signal: AIN13 on PB01 mux B */ +#define MUX_PB01B_ADC0_AIN13 _L_(1) +#define PINMUX_PB01B_ADC0_AIN13 ((PIN_PB01B_ADC0_AIN13 << 16) | MUX_PB01B_ADC0_AIN13) +#define PORT_PB01B_ADC0_AIN13 (_UL_(1) << 1) +#define PIN_PB02B_ADC0_AIN14 _L_(34) /**< \brief ADC0 signal: AIN14 on PB02 mux B */ +#define MUX_PB02B_ADC0_AIN14 _L_(1) +#define PINMUX_PB02B_ADC0_AIN14 ((PIN_PB02B_ADC0_AIN14 << 16) | MUX_PB02B_ADC0_AIN14) +#define PORT_PB02B_ADC0_AIN14 (_UL_(1) << 2) +#define PIN_PB03B_ADC0_AIN15 _L_(35) /**< \brief ADC0 signal: AIN15 on PB03 mux B */ +#define MUX_PB03B_ADC0_AIN15 _L_(1) +#define PINMUX_PB03B_ADC0_AIN15 ((PIN_PB03B_ADC0_AIN15 << 16) | MUX_PB03B_ADC0_AIN15) +#define PORT_PB03B_ADC0_AIN15 (_UL_(1) << 3) +#define PIN_PA03O_ADC0_DRV0 _L_(3) /**< \brief ADC0 signal: DRV0 on PA03 mux O */ +#define MUX_PA03O_ADC0_DRV0 _L_(14) +#define PINMUX_PA03O_ADC0_DRV0 ((PIN_PA03O_ADC0_DRV0 << 16) | MUX_PA03O_ADC0_DRV0) +#define PORT_PA03O_ADC0_DRV0 (_UL_(1) << 3) +#define PIN_PB08O_ADC0_DRV1 _L_(40) /**< \brief ADC0 signal: DRV1 on PB08 mux O */ +#define MUX_PB08O_ADC0_DRV1 _L_(14) +#define PINMUX_PB08O_ADC0_DRV1 ((PIN_PB08O_ADC0_DRV1 << 16) | MUX_PB08O_ADC0_DRV1) +#define PORT_PB08O_ADC0_DRV1 (_UL_(1) << 8) +#define PIN_PB09O_ADC0_DRV2 _L_(41) /**< \brief ADC0 signal: DRV2 on PB09 mux O */ +#define MUX_PB09O_ADC0_DRV2 _L_(14) +#define PINMUX_PB09O_ADC0_DRV2 ((PIN_PB09O_ADC0_DRV2 << 16) | MUX_PB09O_ADC0_DRV2) +#define PORT_PB09O_ADC0_DRV2 (_UL_(1) << 9) +#define PIN_PA04O_ADC0_DRV3 _L_(4) /**< \brief ADC0 signal: DRV3 on PA04 mux O */ +#define MUX_PA04O_ADC0_DRV3 _L_(14) +#define PINMUX_PA04O_ADC0_DRV3 ((PIN_PA04O_ADC0_DRV3 << 16) | MUX_PA04O_ADC0_DRV3) +#define PORT_PA04O_ADC0_DRV3 (_UL_(1) << 4) +#define PIN_PA06O_ADC0_DRV4 _L_(6) /**< \brief ADC0 signal: DRV4 on PA06 mux O */ +#define MUX_PA06O_ADC0_DRV4 _L_(14) +#define PINMUX_PA06O_ADC0_DRV4 ((PIN_PA06O_ADC0_DRV4 << 16) | MUX_PA06O_ADC0_DRV4) +#define PORT_PA06O_ADC0_DRV4 (_UL_(1) << 6) +#define PIN_PA07O_ADC0_DRV5 _L_(7) /**< \brief ADC0 signal: DRV5 on PA07 mux O */ +#define MUX_PA07O_ADC0_DRV5 _L_(14) +#define PINMUX_PA07O_ADC0_DRV5 ((PIN_PA07O_ADC0_DRV5 << 16) | MUX_PA07O_ADC0_DRV5) +#define PORT_PA07O_ADC0_DRV5 (_UL_(1) << 7) +#define PIN_PA08O_ADC0_DRV6 _L_(8) /**< \brief ADC0 signal: DRV6 on PA08 mux O */ +#define MUX_PA08O_ADC0_DRV6 _L_(14) +#define PINMUX_PA08O_ADC0_DRV6 ((PIN_PA08O_ADC0_DRV6 << 16) | MUX_PA08O_ADC0_DRV6) +#define PORT_PA08O_ADC0_DRV6 (_UL_(1) << 8) +#define PIN_PA09O_ADC0_DRV7 _L_(9) /**< \brief ADC0 signal: DRV7 on PA09 mux O */ +#define MUX_PA09O_ADC0_DRV7 _L_(14) +#define PINMUX_PA09O_ADC0_DRV7 ((PIN_PA09O_ADC0_DRV7 << 16) | MUX_PA09O_ADC0_DRV7) +#define PORT_PA09O_ADC0_DRV7 (_UL_(1) << 9) +#define PIN_PA10O_ADC0_DRV8 _L_(10) /**< \brief ADC0 signal: DRV8 on PA10 mux O */ +#define MUX_PA10O_ADC0_DRV8 _L_(14) +#define PINMUX_PA10O_ADC0_DRV8 ((PIN_PA10O_ADC0_DRV8 << 16) | MUX_PA10O_ADC0_DRV8) +#define PORT_PA10O_ADC0_DRV8 (_UL_(1) << 10) +#define PIN_PA11O_ADC0_DRV9 _L_(11) /**< \brief ADC0 signal: DRV9 on PA11 mux O */ +#define MUX_PA11O_ADC0_DRV9 _L_(14) +#define PINMUX_PA11O_ADC0_DRV9 ((PIN_PA11O_ADC0_DRV9 << 16) | MUX_PA11O_ADC0_DRV9) +#define PORT_PA11O_ADC0_DRV9 (_UL_(1) << 11) +#define PIN_PA16O_ADC0_DRV10 _L_(16) /**< \brief ADC0 signal: DRV10 on PA16 mux O */ +#define MUX_PA16O_ADC0_DRV10 _L_(14) +#define PINMUX_PA16O_ADC0_DRV10 ((PIN_PA16O_ADC0_DRV10 << 16) | MUX_PA16O_ADC0_DRV10) +#define PORT_PA16O_ADC0_DRV10 (_UL_(1) << 16) +#define PIN_PA17O_ADC0_DRV11 _L_(17) /**< \brief ADC0 signal: DRV11 on PA17 mux O */ +#define MUX_PA17O_ADC0_DRV11 _L_(14) +#define PINMUX_PA17O_ADC0_DRV11 ((PIN_PA17O_ADC0_DRV11 << 16) | MUX_PA17O_ADC0_DRV11) +#define PORT_PA17O_ADC0_DRV11 (_UL_(1) << 17) +#define PIN_PA18O_ADC0_DRV12 _L_(18) /**< \brief ADC0 signal: DRV12 on PA18 mux O */ +#define MUX_PA18O_ADC0_DRV12 _L_(14) +#define PINMUX_PA18O_ADC0_DRV12 ((PIN_PA18O_ADC0_DRV12 << 16) | MUX_PA18O_ADC0_DRV12) +#define PORT_PA18O_ADC0_DRV12 (_UL_(1) << 18) +#define PIN_PA19O_ADC0_DRV13 _L_(19) /**< \brief ADC0 signal: DRV13 on PA19 mux O */ +#define MUX_PA19O_ADC0_DRV13 _L_(14) +#define PINMUX_PA19O_ADC0_DRV13 ((PIN_PA19O_ADC0_DRV13 << 16) | MUX_PA19O_ADC0_DRV13) +#define PORT_PA19O_ADC0_DRV13 (_UL_(1) << 19) +#define PIN_PA20O_ADC0_DRV14 _L_(20) /**< \brief ADC0 signal: DRV14 on PA20 mux O */ +#define MUX_PA20O_ADC0_DRV14 _L_(14) +#define PINMUX_PA20O_ADC0_DRV14 ((PIN_PA20O_ADC0_DRV14 << 16) | MUX_PA20O_ADC0_DRV14) +#define PORT_PA20O_ADC0_DRV14 (_UL_(1) << 20) +#define PIN_PA21O_ADC0_DRV15 _L_(21) /**< \brief ADC0 signal: DRV15 on PA21 mux O */ +#define MUX_PA21O_ADC0_DRV15 _L_(14) +#define PINMUX_PA21O_ADC0_DRV15 ((PIN_PA21O_ADC0_DRV15 << 16) | MUX_PA21O_ADC0_DRV15) +#define PORT_PA21O_ADC0_DRV15 (_UL_(1) << 21) +#define PIN_PA22O_ADC0_DRV16 _L_(22) /**< \brief ADC0 signal: DRV16 on PA22 mux O */ +#define MUX_PA22O_ADC0_DRV16 _L_(14) +#define PINMUX_PA22O_ADC0_DRV16 ((PIN_PA22O_ADC0_DRV16 << 16) | MUX_PA22O_ADC0_DRV16) +#define PORT_PA22O_ADC0_DRV16 (_UL_(1) << 22) +#define PIN_PA23O_ADC0_DRV17 _L_(23) /**< \brief ADC0 signal: DRV17 on PA23 mux O */ +#define MUX_PA23O_ADC0_DRV17 _L_(14) +#define PINMUX_PA23O_ADC0_DRV17 ((PIN_PA23O_ADC0_DRV17 << 16) | MUX_PA23O_ADC0_DRV17) +#define PORT_PA23O_ADC0_DRV17 (_UL_(1) << 23) +#define PIN_PA27O_ADC0_DRV18 _L_(27) /**< \brief ADC0 signal: DRV18 on PA27 mux O */ +#define MUX_PA27O_ADC0_DRV18 _L_(14) +#define PINMUX_PA27O_ADC0_DRV18 ((PIN_PA27O_ADC0_DRV18 << 16) | MUX_PA27O_ADC0_DRV18) +#define PORT_PA27O_ADC0_DRV18 (_UL_(1) << 27) +#define PIN_PA30O_ADC0_DRV19 _L_(30) /**< \brief ADC0 signal: DRV19 on PA30 mux O */ +#define MUX_PA30O_ADC0_DRV19 _L_(14) +#define PINMUX_PA30O_ADC0_DRV19 ((PIN_PA30O_ADC0_DRV19 << 16) | MUX_PA30O_ADC0_DRV19) +#define PORT_PA30O_ADC0_DRV19 (_UL_(1) << 30) +#define PIN_PB02O_ADC0_DRV20 _L_(34) /**< \brief ADC0 signal: DRV20 on PB02 mux O */ +#define MUX_PB02O_ADC0_DRV20 _L_(14) +#define PINMUX_PB02O_ADC0_DRV20 ((PIN_PB02O_ADC0_DRV20 << 16) | MUX_PB02O_ADC0_DRV20) +#define PORT_PB02O_ADC0_DRV20 (_UL_(1) << 2) +#define PIN_PB03O_ADC0_DRV21 _L_(35) /**< \brief ADC0 signal: DRV21 on PB03 mux O */ +#define MUX_PB03O_ADC0_DRV21 _L_(14) +#define PINMUX_PB03O_ADC0_DRV21 ((PIN_PB03O_ADC0_DRV21 << 16) | MUX_PB03O_ADC0_DRV21) +#define PORT_PB03O_ADC0_DRV21 (_UL_(1) << 3) +#define PIN_PB04O_ADC0_DRV22 _L_(36) /**< \brief ADC0 signal: DRV22 on PB04 mux O */ +#define MUX_PB04O_ADC0_DRV22 _L_(14) +#define PINMUX_PB04O_ADC0_DRV22 ((PIN_PB04O_ADC0_DRV22 << 16) | MUX_PB04O_ADC0_DRV22) +#define PORT_PB04O_ADC0_DRV22 (_UL_(1) << 4) +#define PIN_PB05O_ADC0_DRV23 _L_(37) /**< \brief ADC0 signal: DRV23 on PB05 mux O */ +#define MUX_PB05O_ADC0_DRV23 _L_(14) +#define PINMUX_PB05O_ADC0_DRV23 ((PIN_PB05O_ADC0_DRV23 << 16) | MUX_PB05O_ADC0_DRV23) +#define PORT_PB05O_ADC0_DRV23 (_UL_(1) << 5) +#define PIN_PB06O_ADC0_DRV24 _L_(38) /**< \brief ADC0 signal: DRV24 on PB06 mux O */ +#define MUX_PB06O_ADC0_DRV24 _L_(14) +#define PINMUX_PB06O_ADC0_DRV24 ((PIN_PB06O_ADC0_DRV24 << 16) | MUX_PB06O_ADC0_DRV24) +#define PORT_PB06O_ADC0_DRV24 (_UL_(1) << 6) +#define PIN_PB07O_ADC0_DRV25 _L_(39) /**< \brief ADC0 signal: DRV25 on PB07 mux O */ +#define MUX_PB07O_ADC0_DRV25 _L_(14) +#define PINMUX_PB07O_ADC0_DRV25 ((PIN_PB07O_ADC0_DRV25 << 16) | MUX_PB07O_ADC0_DRV25) +#define PORT_PB07O_ADC0_DRV25 (_UL_(1) << 7) +#define PIN_PB12O_ADC0_DRV26 _L_(44) /**< \brief ADC0 signal: DRV26 on PB12 mux O */ +#define MUX_PB12O_ADC0_DRV26 _L_(14) +#define PINMUX_PB12O_ADC0_DRV26 ((PIN_PB12O_ADC0_DRV26 << 16) | MUX_PB12O_ADC0_DRV26) +#define PORT_PB12O_ADC0_DRV26 (_UL_(1) << 12) +#define PIN_PB13O_ADC0_DRV27 _L_(45) /**< \brief ADC0 signal: DRV27 on PB13 mux O */ +#define MUX_PB13O_ADC0_DRV27 _L_(14) +#define PINMUX_PB13O_ADC0_DRV27 ((PIN_PB13O_ADC0_DRV27 << 16) | MUX_PB13O_ADC0_DRV27) +#define PORT_PB13O_ADC0_DRV27 (_UL_(1) << 13) +#define PIN_PB14O_ADC0_DRV28 _L_(46) /**< \brief ADC0 signal: DRV28 on PB14 mux O */ +#define MUX_PB14O_ADC0_DRV28 _L_(14) +#define PINMUX_PB14O_ADC0_DRV28 ((PIN_PB14O_ADC0_DRV28 << 16) | MUX_PB14O_ADC0_DRV28) +#define PORT_PB14O_ADC0_DRV28 (_UL_(1) << 14) +#define PIN_PB15O_ADC0_DRV29 _L_(47) /**< \brief ADC0 signal: DRV29 on PB15 mux O */ +#define MUX_PB15O_ADC0_DRV29 _L_(14) +#define PINMUX_PB15O_ADC0_DRV29 ((PIN_PB15O_ADC0_DRV29 << 16) | MUX_PB15O_ADC0_DRV29) +#define PORT_PB15O_ADC0_DRV29 (_UL_(1) << 15) +#define PIN_PB00O_ADC0_DRV30 _L_(32) /**< \brief ADC0 signal: DRV30 on PB00 mux O */ +#define MUX_PB00O_ADC0_DRV30 _L_(14) +#define PINMUX_PB00O_ADC0_DRV30 ((PIN_PB00O_ADC0_DRV30 << 16) | MUX_PB00O_ADC0_DRV30) +#define PORT_PB00O_ADC0_DRV30 (_UL_(1) << 0) +#define PIN_PB01O_ADC0_DRV31 _L_(33) /**< \brief ADC0 signal: DRV31 on PB01 mux O */ +#define MUX_PB01O_ADC0_DRV31 _L_(14) +#define PINMUX_PB01O_ADC0_DRV31 ((PIN_PB01O_ADC0_DRV31 << 16) | MUX_PB01O_ADC0_DRV31) +#define PORT_PB01O_ADC0_DRV31 (_UL_(1) << 1) +#define PIN_PA03B_ADC0_PTCXY0 _L_(3) /**< \brief ADC0 signal: PTCXY0 on PA03 mux B */ +#define MUX_PA03B_ADC0_PTCXY0 _L_(1) +#define PINMUX_PA03B_ADC0_PTCXY0 ((PIN_PA03B_ADC0_PTCXY0 << 16) | MUX_PA03B_ADC0_PTCXY0) +#define PORT_PA03B_ADC0_PTCXY0 (_UL_(1) << 3) +#define PIN_PB08B_ADC0_PTCXY1 _L_(40) /**< \brief ADC0 signal: PTCXY1 on PB08 mux B */ +#define MUX_PB08B_ADC0_PTCXY1 _L_(1) +#define PINMUX_PB08B_ADC0_PTCXY1 ((PIN_PB08B_ADC0_PTCXY1 << 16) | MUX_PB08B_ADC0_PTCXY1) +#define PORT_PB08B_ADC0_PTCXY1 (_UL_(1) << 8) +#define PIN_PB09B_ADC0_PTCXY2 _L_(41) /**< \brief ADC0 signal: PTCXY2 on PB09 mux B */ +#define MUX_PB09B_ADC0_PTCXY2 _L_(1) +#define PINMUX_PB09B_ADC0_PTCXY2 ((PIN_PB09B_ADC0_PTCXY2 << 16) | MUX_PB09B_ADC0_PTCXY2) +#define PORT_PB09B_ADC0_PTCXY2 (_UL_(1) << 9) +#define PIN_PA04B_ADC0_PTCXY3 _L_(4) /**< \brief ADC0 signal: PTCXY3 on PA04 mux B */ +#define MUX_PA04B_ADC0_PTCXY3 _L_(1) +#define PINMUX_PA04B_ADC0_PTCXY3 ((PIN_PA04B_ADC0_PTCXY3 << 16) | MUX_PA04B_ADC0_PTCXY3) +#define PORT_PA04B_ADC0_PTCXY3 (_UL_(1) << 4) +#define PIN_PA06B_ADC0_PTCXY4 _L_(6) /**< \brief ADC0 signal: PTCXY4 on PA06 mux B */ +#define MUX_PA06B_ADC0_PTCXY4 _L_(1) +#define PINMUX_PA06B_ADC0_PTCXY4 ((PIN_PA06B_ADC0_PTCXY4 << 16) | MUX_PA06B_ADC0_PTCXY4) +#define PORT_PA06B_ADC0_PTCXY4 (_UL_(1) << 6) +#define PIN_PA07B_ADC0_PTCXY5 _L_(7) /**< \brief ADC0 signal: PTCXY5 on PA07 mux B */ +#define MUX_PA07B_ADC0_PTCXY5 _L_(1) +#define PINMUX_PA07B_ADC0_PTCXY5 ((PIN_PA07B_ADC0_PTCXY5 << 16) | MUX_PA07B_ADC0_PTCXY5) +#define PORT_PA07B_ADC0_PTCXY5 (_UL_(1) << 7) +#define PIN_PA08B_ADC0_PTCXY6 _L_(8) /**< \brief ADC0 signal: PTCXY6 on PA08 mux B */ +#define MUX_PA08B_ADC0_PTCXY6 _L_(1) +#define PINMUX_PA08B_ADC0_PTCXY6 ((PIN_PA08B_ADC0_PTCXY6 << 16) | MUX_PA08B_ADC0_PTCXY6) +#define PORT_PA08B_ADC0_PTCXY6 (_UL_(1) << 8) +#define PIN_PA09B_ADC0_PTCXY7 _L_(9) /**< \brief ADC0 signal: PTCXY7 on PA09 mux B */ +#define MUX_PA09B_ADC0_PTCXY7 _L_(1) +#define PINMUX_PA09B_ADC0_PTCXY7 ((PIN_PA09B_ADC0_PTCXY7 << 16) | MUX_PA09B_ADC0_PTCXY7) +#define PORT_PA09B_ADC0_PTCXY7 (_UL_(1) << 9) +#define PIN_PA10B_ADC0_PTCXY8 _L_(10) /**< \brief ADC0 signal: PTCXY8 on PA10 mux B */ +#define MUX_PA10B_ADC0_PTCXY8 _L_(1) +#define PINMUX_PA10B_ADC0_PTCXY8 ((PIN_PA10B_ADC0_PTCXY8 << 16) | MUX_PA10B_ADC0_PTCXY8) +#define PORT_PA10B_ADC0_PTCXY8 (_UL_(1) << 10) +#define PIN_PA11B_ADC0_PTCXY9 _L_(11) /**< \brief ADC0 signal: PTCXY9 on PA11 mux B */ +#define MUX_PA11B_ADC0_PTCXY9 _L_(1) +#define PINMUX_PA11B_ADC0_PTCXY9 ((PIN_PA11B_ADC0_PTCXY9 << 16) | MUX_PA11B_ADC0_PTCXY9) +#define PORT_PA11B_ADC0_PTCXY9 (_UL_(1) << 11) +#define PIN_PA16B_ADC0_PTCXY10 _L_(16) /**< \brief ADC0 signal: PTCXY10 on PA16 mux B */ +#define MUX_PA16B_ADC0_PTCXY10 _L_(1) +#define PINMUX_PA16B_ADC0_PTCXY10 ((PIN_PA16B_ADC0_PTCXY10 << 16) | MUX_PA16B_ADC0_PTCXY10) +#define PORT_PA16B_ADC0_PTCXY10 (_UL_(1) << 16) +#define PIN_PA17B_ADC0_PTCXY11 _L_(17) /**< \brief ADC0 signal: PTCXY11 on PA17 mux B */ +#define MUX_PA17B_ADC0_PTCXY11 _L_(1) +#define PINMUX_PA17B_ADC0_PTCXY11 ((PIN_PA17B_ADC0_PTCXY11 << 16) | MUX_PA17B_ADC0_PTCXY11) +#define PORT_PA17B_ADC0_PTCXY11 (_UL_(1) << 17) +#define PIN_PA18B_ADC0_PTCXY12 _L_(18) /**< \brief ADC0 signal: PTCXY12 on PA18 mux B */ +#define MUX_PA18B_ADC0_PTCXY12 _L_(1) +#define PINMUX_PA18B_ADC0_PTCXY12 ((PIN_PA18B_ADC0_PTCXY12 << 16) | MUX_PA18B_ADC0_PTCXY12) +#define PORT_PA18B_ADC0_PTCXY12 (_UL_(1) << 18) +#define PIN_PA19B_ADC0_PTCXY13 _L_(19) /**< \brief ADC0 signal: PTCXY13 on PA19 mux B */ +#define MUX_PA19B_ADC0_PTCXY13 _L_(1) +#define PINMUX_PA19B_ADC0_PTCXY13 ((PIN_PA19B_ADC0_PTCXY13 << 16) | MUX_PA19B_ADC0_PTCXY13) +#define PORT_PA19B_ADC0_PTCXY13 (_UL_(1) << 19) +#define PIN_PA20B_ADC0_PTCXY14 _L_(20) /**< \brief ADC0 signal: PTCXY14 on PA20 mux B */ +#define MUX_PA20B_ADC0_PTCXY14 _L_(1) +#define PINMUX_PA20B_ADC0_PTCXY14 ((PIN_PA20B_ADC0_PTCXY14 << 16) | MUX_PA20B_ADC0_PTCXY14) +#define PORT_PA20B_ADC0_PTCXY14 (_UL_(1) << 20) +#define PIN_PA21B_ADC0_PTCXY15 _L_(21) /**< \brief ADC0 signal: PTCXY15 on PA21 mux B */ +#define MUX_PA21B_ADC0_PTCXY15 _L_(1) +#define PINMUX_PA21B_ADC0_PTCXY15 ((PIN_PA21B_ADC0_PTCXY15 << 16) | MUX_PA21B_ADC0_PTCXY15) +#define PORT_PA21B_ADC0_PTCXY15 (_UL_(1) << 21) +#define PIN_PA22B_ADC0_PTCXY16 _L_(22) /**< \brief ADC0 signal: PTCXY16 on PA22 mux B */ +#define MUX_PA22B_ADC0_PTCXY16 _L_(1) +#define PINMUX_PA22B_ADC0_PTCXY16 ((PIN_PA22B_ADC0_PTCXY16 << 16) | MUX_PA22B_ADC0_PTCXY16) +#define PORT_PA22B_ADC0_PTCXY16 (_UL_(1) << 22) +#define PIN_PA23B_ADC0_PTCXY17 _L_(23) /**< \brief ADC0 signal: PTCXY17 on PA23 mux B */ +#define MUX_PA23B_ADC0_PTCXY17 _L_(1) +#define PINMUX_PA23B_ADC0_PTCXY17 ((PIN_PA23B_ADC0_PTCXY17 << 16) | MUX_PA23B_ADC0_PTCXY17) +#define PORT_PA23B_ADC0_PTCXY17 (_UL_(1) << 23) +#define PIN_PA27B_ADC0_PTCXY18 _L_(27) /**< \brief ADC0 signal: PTCXY18 on PA27 mux B */ +#define MUX_PA27B_ADC0_PTCXY18 _L_(1) +#define PINMUX_PA27B_ADC0_PTCXY18 ((PIN_PA27B_ADC0_PTCXY18 << 16) | MUX_PA27B_ADC0_PTCXY18) +#define PORT_PA27B_ADC0_PTCXY18 (_UL_(1) << 27) +#define PIN_PA30B_ADC0_PTCXY19 _L_(30) /**< \brief ADC0 signal: PTCXY19 on PA30 mux B */ +#define MUX_PA30B_ADC0_PTCXY19 _L_(1) +#define PINMUX_PA30B_ADC0_PTCXY19 ((PIN_PA30B_ADC0_PTCXY19 << 16) | MUX_PA30B_ADC0_PTCXY19) +#define PORT_PA30B_ADC0_PTCXY19 (_UL_(1) << 30) +#define PIN_PB02B_ADC0_PTCXY20 _L_(34) /**< \brief ADC0 signal: PTCXY20 on PB02 mux B */ +#define MUX_PB02B_ADC0_PTCXY20 _L_(1) +#define PINMUX_PB02B_ADC0_PTCXY20 ((PIN_PB02B_ADC0_PTCXY20 << 16) | MUX_PB02B_ADC0_PTCXY20) +#define PORT_PB02B_ADC0_PTCXY20 (_UL_(1) << 2) +#define PIN_PB03B_ADC0_PTCXY21 _L_(35) /**< \brief ADC0 signal: PTCXY21 on PB03 mux B */ +#define MUX_PB03B_ADC0_PTCXY21 _L_(1) +#define PINMUX_PB03B_ADC0_PTCXY21 ((PIN_PB03B_ADC0_PTCXY21 << 16) | MUX_PB03B_ADC0_PTCXY21) +#define PORT_PB03B_ADC0_PTCXY21 (_UL_(1) << 3) +#define PIN_PB04B_ADC0_PTCXY22 _L_(36) /**< \brief ADC0 signal: PTCXY22 on PB04 mux B */ +#define MUX_PB04B_ADC0_PTCXY22 _L_(1) +#define PINMUX_PB04B_ADC0_PTCXY22 ((PIN_PB04B_ADC0_PTCXY22 << 16) | MUX_PB04B_ADC0_PTCXY22) +#define PORT_PB04B_ADC0_PTCXY22 (_UL_(1) << 4) +#define PIN_PB05B_ADC0_PTCXY23 _L_(37) /**< \brief ADC0 signal: PTCXY23 on PB05 mux B */ +#define MUX_PB05B_ADC0_PTCXY23 _L_(1) +#define PINMUX_PB05B_ADC0_PTCXY23 ((PIN_PB05B_ADC0_PTCXY23 << 16) | MUX_PB05B_ADC0_PTCXY23) +#define PORT_PB05B_ADC0_PTCXY23 (_UL_(1) << 5) +#define PIN_PB06B_ADC0_PTCXY24 _L_(38) /**< \brief ADC0 signal: PTCXY24 on PB06 mux B */ +#define MUX_PB06B_ADC0_PTCXY24 _L_(1) +#define PINMUX_PB06B_ADC0_PTCXY24 ((PIN_PB06B_ADC0_PTCXY24 << 16) | MUX_PB06B_ADC0_PTCXY24) +#define PORT_PB06B_ADC0_PTCXY24 (_UL_(1) << 6) +#define PIN_PB07B_ADC0_PTCXY25 _L_(39) /**< \brief ADC0 signal: PTCXY25 on PB07 mux B */ +#define MUX_PB07B_ADC0_PTCXY25 _L_(1) +#define PINMUX_PB07B_ADC0_PTCXY25 ((PIN_PB07B_ADC0_PTCXY25 << 16) | MUX_PB07B_ADC0_PTCXY25) +#define PORT_PB07B_ADC0_PTCXY25 (_UL_(1) << 7) +#define PIN_PB12B_ADC0_PTCXY26 _L_(44) /**< \brief ADC0 signal: PTCXY26 on PB12 mux B */ +#define MUX_PB12B_ADC0_PTCXY26 _L_(1) +#define PINMUX_PB12B_ADC0_PTCXY26 ((PIN_PB12B_ADC0_PTCXY26 << 16) | MUX_PB12B_ADC0_PTCXY26) +#define PORT_PB12B_ADC0_PTCXY26 (_UL_(1) << 12) +#define PIN_PB13B_ADC0_PTCXY27 _L_(45) /**< \brief ADC0 signal: PTCXY27 on PB13 mux B */ +#define MUX_PB13B_ADC0_PTCXY27 _L_(1) +#define PINMUX_PB13B_ADC0_PTCXY27 ((PIN_PB13B_ADC0_PTCXY27 << 16) | MUX_PB13B_ADC0_PTCXY27) +#define PORT_PB13B_ADC0_PTCXY27 (_UL_(1) << 13) +#define PIN_PB14B_ADC0_PTCXY28 _L_(46) /**< \brief ADC0 signal: PTCXY28 on PB14 mux B */ +#define MUX_PB14B_ADC0_PTCXY28 _L_(1) +#define PINMUX_PB14B_ADC0_PTCXY28 ((PIN_PB14B_ADC0_PTCXY28 << 16) | MUX_PB14B_ADC0_PTCXY28) +#define PORT_PB14B_ADC0_PTCXY28 (_UL_(1) << 14) +#define PIN_PB15B_ADC0_PTCXY29 _L_(47) /**< \brief ADC0 signal: PTCXY29 on PB15 mux B */ +#define MUX_PB15B_ADC0_PTCXY29 _L_(1) +#define PINMUX_PB15B_ADC0_PTCXY29 ((PIN_PB15B_ADC0_PTCXY29 << 16) | MUX_PB15B_ADC0_PTCXY29) +#define PORT_PB15B_ADC0_PTCXY29 (_UL_(1) << 15) +#define PIN_PB00B_ADC0_PTCXY30 _L_(32) /**< \brief ADC0 signal: PTCXY30 on PB00 mux B */ +#define MUX_PB00B_ADC0_PTCXY30 _L_(1) +#define PINMUX_PB00B_ADC0_PTCXY30 ((PIN_PB00B_ADC0_PTCXY30 << 16) | MUX_PB00B_ADC0_PTCXY30) +#define PORT_PB00B_ADC0_PTCXY30 (_UL_(1) << 0) +#define PIN_PB01B_ADC0_PTCXY31 _L_(33) /**< \brief ADC0 signal: PTCXY31 on PB01 mux B */ +#define MUX_PB01B_ADC0_PTCXY31 _L_(1) +#define PINMUX_PB01B_ADC0_PTCXY31 ((PIN_PB01B_ADC0_PTCXY31 << 16) | MUX_PB01B_ADC0_PTCXY31) +#define PORT_PB01B_ADC0_PTCXY31 (_UL_(1) << 1) +/* ========== PORT definition for ADC1 peripheral ========== */ +#define PIN_PB08B_ADC1_AIN0 _L_(40) /**< \brief ADC1 signal: AIN0 on PB08 mux B */ +#define MUX_PB08B_ADC1_AIN0 _L_(1) +#define PINMUX_PB08B_ADC1_AIN0 ((PIN_PB08B_ADC1_AIN0 << 16) | MUX_PB08B_ADC1_AIN0) +#define PORT_PB08B_ADC1_AIN0 (_UL_(1) << 8) +#define PIN_PB09B_ADC1_AIN1 _L_(41) /**< \brief ADC1 signal: AIN1 on PB09 mux B */ +#define MUX_PB09B_ADC1_AIN1 _L_(1) +#define PINMUX_PB09B_ADC1_AIN1 ((PIN_PB09B_ADC1_AIN1 << 16) | MUX_PB09B_ADC1_AIN1) +#define PORT_PB09B_ADC1_AIN1 (_UL_(1) << 9) +#define PIN_PA08B_ADC1_AIN2 _L_(8) /**< \brief ADC1 signal: AIN2 on PA08 mux B */ +#define MUX_PA08B_ADC1_AIN2 _L_(1) +#define PINMUX_PA08B_ADC1_AIN2 ((PIN_PA08B_ADC1_AIN2 << 16) | MUX_PA08B_ADC1_AIN2) +#define PORT_PA08B_ADC1_AIN2 (_UL_(1) << 8) +#define PIN_PA09B_ADC1_AIN3 _L_(9) /**< \brief ADC1 signal: AIN3 on PA09 mux B */ +#define MUX_PA09B_ADC1_AIN3 _L_(1) +#define PINMUX_PA09B_ADC1_AIN3 ((PIN_PA09B_ADC1_AIN3 << 16) | MUX_PA09B_ADC1_AIN3) +#define PORT_PA09B_ADC1_AIN3 (_UL_(1) << 9) +#define PIN_PC02B_ADC1_AIN4 _L_(66) /**< \brief ADC1 signal: AIN4 on PC02 mux B */ +#define MUX_PC02B_ADC1_AIN4 _L_(1) +#define PINMUX_PC02B_ADC1_AIN4 ((PIN_PC02B_ADC1_AIN4 << 16) | MUX_PC02B_ADC1_AIN4) +#define PORT_PC02B_ADC1_AIN4 (_UL_(1) << 2) +#define PIN_PC03B_ADC1_AIN5 _L_(67) /**< \brief ADC1 signal: AIN5 on PC03 mux B */ +#define MUX_PC03B_ADC1_AIN5 _L_(1) +#define PINMUX_PC03B_ADC1_AIN5 ((PIN_PC03B_ADC1_AIN5 << 16) | MUX_PC03B_ADC1_AIN5) +#define PORT_PC03B_ADC1_AIN5 (_UL_(1) << 3) +#define PIN_PB04B_ADC1_AIN6 _L_(36) /**< \brief ADC1 signal: AIN6 on PB04 mux B */ +#define MUX_PB04B_ADC1_AIN6 _L_(1) +#define PINMUX_PB04B_ADC1_AIN6 ((PIN_PB04B_ADC1_AIN6 << 16) | MUX_PB04B_ADC1_AIN6) +#define PORT_PB04B_ADC1_AIN6 (_UL_(1) << 4) +#define PIN_PB05B_ADC1_AIN7 _L_(37) /**< \brief ADC1 signal: AIN7 on PB05 mux B */ +#define MUX_PB05B_ADC1_AIN7 _L_(1) +#define PINMUX_PB05B_ADC1_AIN7 ((PIN_PB05B_ADC1_AIN7 << 16) | MUX_PB05B_ADC1_AIN7) +#define PORT_PB05B_ADC1_AIN7 (_UL_(1) << 5) +#define PIN_PB06B_ADC1_AIN8 _L_(38) /**< \brief ADC1 signal: AIN8 on PB06 mux B */ +#define MUX_PB06B_ADC1_AIN8 _L_(1) +#define PINMUX_PB06B_ADC1_AIN8 ((PIN_PB06B_ADC1_AIN8 << 16) | MUX_PB06B_ADC1_AIN8) +#define PORT_PB06B_ADC1_AIN8 (_UL_(1) << 6) +#define PIN_PB07B_ADC1_AIN9 _L_(39) /**< \brief ADC1 signal: AIN9 on PB07 mux B */ +#define MUX_PB07B_ADC1_AIN9 _L_(1) +#define PINMUX_PB07B_ADC1_AIN9 ((PIN_PB07B_ADC1_AIN9 << 16) | MUX_PB07B_ADC1_AIN9) +#define PORT_PB07B_ADC1_AIN9 (_UL_(1) << 7) +#define PIN_PC00B_ADC1_AIN10 _L_(64) /**< \brief ADC1 signal: AIN10 on PC00 mux B */ +#define MUX_PC00B_ADC1_AIN10 _L_(1) +#define PINMUX_PC00B_ADC1_AIN10 ((PIN_PC00B_ADC1_AIN10 << 16) | MUX_PC00B_ADC1_AIN10) +#define PORT_PC00B_ADC1_AIN10 (_UL_(1) << 0) +#define PIN_PC01B_ADC1_AIN11 _L_(65) /**< \brief ADC1 signal: AIN11 on PC01 mux B */ +#define MUX_PC01B_ADC1_AIN11 _L_(1) +#define PINMUX_PC01B_ADC1_AIN11 ((PIN_PC01B_ADC1_AIN11 << 16) | MUX_PC01B_ADC1_AIN11) +#define PORT_PC01B_ADC1_AIN11 (_UL_(1) << 1) +/* ========== PORT definition for DAC peripheral ========== */ +#define PIN_PA02B_DAC_VOUT0 _L_(2) /**< \brief DAC signal: VOUT0 on PA02 mux B */ +#define MUX_PA02B_DAC_VOUT0 _L_(1) +#define PINMUX_PA02B_DAC_VOUT0 ((PIN_PA02B_DAC_VOUT0 << 16) | MUX_PA02B_DAC_VOUT0) +#define PORT_PA02B_DAC_VOUT0 (_UL_(1) << 2) +#define PIN_PA05B_DAC_VOUT1 _L_(5) /**< \brief DAC signal: VOUT1 on PA05 mux B */ +#define MUX_PA05B_DAC_VOUT1 _L_(1) +#define PINMUX_PA05B_DAC_VOUT1 ((PIN_PA05B_DAC_VOUT1 << 16) | MUX_PA05B_DAC_VOUT1) +#define PORT_PA05B_DAC_VOUT1 (_UL_(1) << 5) +/* ========== PORT definition for I2S peripheral ========== */ +#define PIN_PA09J_I2S_FS0 _L_(9) /**< \brief I2S signal: FS0 on PA09 mux J */ +#define MUX_PA09J_I2S_FS0 _L_(9) +#define PINMUX_PA09J_I2S_FS0 ((PIN_PA09J_I2S_FS0 << 16) | MUX_PA09J_I2S_FS0) +#define PORT_PA09J_I2S_FS0 (_UL_(1) << 9) +#define PIN_PA20J_I2S_FS0 _L_(20) /**< \brief I2S signal: FS0 on PA20 mux J */ +#define MUX_PA20J_I2S_FS0 _L_(9) +#define PINMUX_PA20J_I2S_FS0 ((PIN_PA20J_I2S_FS0 << 16) | MUX_PA20J_I2S_FS0) +#define PORT_PA20J_I2S_FS0 (_UL_(1) << 20) +#define PIN_PA23J_I2S_FS1 _L_(23) /**< \brief I2S signal: FS1 on PA23 mux J */ +#define MUX_PA23J_I2S_FS1 _L_(9) +#define PINMUX_PA23J_I2S_FS1 ((PIN_PA23J_I2S_FS1 << 16) | MUX_PA23J_I2S_FS1) +#define PORT_PA23J_I2S_FS1 (_UL_(1) << 23) +#define PIN_PB11J_I2S_FS1 _L_(43) /**< \brief I2S signal: FS1 on PB11 mux J */ +#define MUX_PB11J_I2S_FS1 _L_(9) +#define PINMUX_PB11J_I2S_FS1 ((PIN_PB11J_I2S_FS1 << 16) | MUX_PB11J_I2S_FS1) +#define PORT_PB11J_I2S_FS1 (_UL_(1) << 11) +#define PIN_PA08J_I2S_MCK0 _L_(8) /**< \brief I2S signal: MCK0 on PA08 mux J */ +#define MUX_PA08J_I2S_MCK0 _L_(9) +#define PINMUX_PA08J_I2S_MCK0 ((PIN_PA08J_I2S_MCK0 << 16) | MUX_PA08J_I2S_MCK0) +#define PORT_PA08J_I2S_MCK0 (_UL_(1) << 8) +#define PIN_PB17J_I2S_MCK0 _L_(49) /**< \brief I2S signal: MCK0 on PB17 mux J */ +#define MUX_PB17J_I2S_MCK0 _L_(9) +#define PINMUX_PB17J_I2S_MCK0 ((PIN_PB17J_I2S_MCK0 << 16) | MUX_PB17J_I2S_MCK0) +#define PORT_PB17J_I2S_MCK0 (_UL_(1) << 17) +#define PIN_PB13J_I2S_MCK1 _L_(45) /**< \brief I2S signal: MCK1 on PB13 mux J */ +#define MUX_PB13J_I2S_MCK1 _L_(9) +#define PINMUX_PB13J_I2S_MCK1 ((PIN_PB13J_I2S_MCK1 << 16) | MUX_PB13J_I2S_MCK1) +#define PORT_PB13J_I2S_MCK1 (_UL_(1) << 13) +#define PIN_PA10J_I2S_SCK0 _L_(10) /**< \brief I2S signal: SCK0 on PA10 mux J */ +#define MUX_PA10J_I2S_SCK0 _L_(9) +#define PINMUX_PA10J_I2S_SCK0 ((PIN_PA10J_I2S_SCK0 << 16) | MUX_PA10J_I2S_SCK0) +#define PORT_PA10J_I2S_SCK0 (_UL_(1) << 10) +#define PIN_PB16J_I2S_SCK0 _L_(48) /**< \brief I2S signal: SCK0 on PB16 mux J */ +#define MUX_PB16J_I2S_SCK0 _L_(9) +#define PINMUX_PB16J_I2S_SCK0 ((PIN_PB16J_I2S_SCK0 << 16) | MUX_PB16J_I2S_SCK0) +#define PORT_PB16J_I2S_SCK0 (_UL_(1) << 16) +#define PIN_PB12J_I2S_SCK1 _L_(44) /**< \brief I2S signal: SCK1 on PB12 mux J */ +#define MUX_PB12J_I2S_SCK1 _L_(9) +#define PINMUX_PB12J_I2S_SCK1 ((PIN_PB12J_I2S_SCK1 << 16) | MUX_PB12J_I2S_SCK1) +#define PORT_PB12J_I2S_SCK1 (_UL_(1) << 12) +#define PIN_PA22J_I2S_SDI _L_(22) /**< \brief I2S signal: SDI on PA22 mux J */ +#define MUX_PA22J_I2S_SDI _L_(9) +#define PINMUX_PA22J_I2S_SDI ((PIN_PA22J_I2S_SDI << 16) | MUX_PA22J_I2S_SDI) +#define PORT_PA22J_I2S_SDI (_UL_(1) << 22) +#define PIN_PB10J_I2S_SDI _L_(42) /**< \brief I2S signal: SDI on PB10 mux J */ +#define MUX_PB10J_I2S_SDI _L_(9) +#define PINMUX_PB10J_I2S_SDI ((PIN_PB10J_I2S_SDI << 16) | MUX_PB10J_I2S_SDI) +#define PORT_PB10J_I2S_SDI (_UL_(1) << 10) +#define PIN_PA11J_I2S_SDO _L_(11) /**< \brief I2S signal: SDO on PA11 mux J */ +#define MUX_PA11J_I2S_SDO _L_(9) +#define PINMUX_PA11J_I2S_SDO ((PIN_PA11J_I2S_SDO << 16) | MUX_PA11J_I2S_SDO) +#define PORT_PA11J_I2S_SDO (_UL_(1) << 11) +#define PIN_PA21J_I2S_SDO _L_(21) /**< \brief I2S signal: SDO on PA21 mux J */ +#define MUX_PA21J_I2S_SDO _L_(9) +#define PINMUX_PA21J_I2S_SDO ((PIN_PA21J_I2S_SDO << 16) | MUX_PA21J_I2S_SDO) +#define PORT_PA21J_I2S_SDO (_UL_(1) << 21) +/* ========== PORT definition for PCC peripheral ========== */ +#define PIN_PA14K_PCC_CLK _L_(14) /**< \brief PCC signal: CLK on PA14 mux K */ +#define MUX_PA14K_PCC_CLK _L_(10) +#define PINMUX_PA14K_PCC_CLK ((PIN_PA14K_PCC_CLK << 16) | MUX_PA14K_PCC_CLK) +#define PORT_PA14K_PCC_CLK (_UL_(1) << 14) +#define PIN_PA16K_PCC_DATA0 _L_(16) /**< \brief PCC signal: DATA0 on PA16 mux K */ +#define MUX_PA16K_PCC_DATA0 _L_(10) +#define PINMUX_PA16K_PCC_DATA0 ((PIN_PA16K_PCC_DATA0 << 16) | MUX_PA16K_PCC_DATA0) +#define PORT_PA16K_PCC_DATA0 (_UL_(1) << 16) +#define PIN_PA17K_PCC_DATA1 _L_(17) /**< \brief PCC signal: DATA1 on PA17 mux K */ +#define MUX_PA17K_PCC_DATA1 _L_(10) +#define PINMUX_PA17K_PCC_DATA1 ((PIN_PA17K_PCC_DATA1 << 16) | MUX_PA17K_PCC_DATA1) +#define PORT_PA17K_PCC_DATA1 (_UL_(1) << 17) +#define PIN_PA18K_PCC_DATA2 _L_(18) /**< \brief PCC signal: DATA2 on PA18 mux K */ +#define MUX_PA18K_PCC_DATA2 _L_(10) +#define PINMUX_PA18K_PCC_DATA2 ((PIN_PA18K_PCC_DATA2 << 16) | MUX_PA18K_PCC_DATA2) +#define PORT_PA18K_PCC_DATA2 (_UL_(1) << 18) +#define PIN_PA19K_PCC_DATA3 _L_(19) /**< \brief PCC signal: DATA3 on PA19 mux K */ +#define MUX_PA19K_PCC_DATA3 _L_(10) +#define PINMUX_PA19K_PCC_DATA3 ((PIN_PA19K_PCC_DATA3 << 16) | MUX_PA19K_PCC_DATA3) +#define PORT_PA19K_PCC_DATA3 (_UL_(1) << 19) +#define PIN_PA20K_PCC_DATA4 _L_(20) /**< \brief PCC signal: DATA4 on PA20 mux K */ +#define MUX_PA20K_PCC_DATA4 _L_(10) +#define PINMUX_PA20K_PCC_DATA4 ((PIN_PA20K_PCC_DATA4 << 16) | MUX_PA20K_PCC_DATA4) +#define PORT_PA20K_PCC_DATA4 (_UL_(1) << 20) +#define PIN_PA21K_PCC_DATA5 _L_(21) /**< \brief PCC signal: DATA5 on PA21 mux K */ +#define MUX_PA21K_PCC_DATA5 _L_(10) +#define PINMUX_PA21K_PCC_DATA5 ((PIN_PA21K_PCC_DATA5 << 16) | MUX_PA21K_PCC_DATA5) +#define PORT_PA21K_PCC_DATA5 (_UL_(1) << 21) +#define PIN_PA22K_PCC_DATA6 _L_(22) /**< \brief PCC signal: DATA6 on PA22 mux K */ +#define MUX_PA22K_PCC_DATA6 _L_(10) +#define PINMUX_PA22K_PCC_DATA6 ((PIN_PA22K_PCC_DATA6 << 16) | MUX_PA22K_PCC_DATA6) +#define PORT_PA22K_PCC_DATA6 (_UL_(1) << 22) +#define PIN_PA23K_PCC_DATA7 _L_(23) /**< \brief PCC signal: DATA7 on PA23 mux K */ +#define MUX_PA23K_PCC_DATA7 _L_(10) +#define PINMUX_PA23K_PCC_DATA7 ((PIN_PA23K_PCC_DATA7 << 16) | MUX_PA23K_PCC_DATA7) +#define PORT_PA23K_PCC_DATA7 (_UL_(1) << 23) +#define PIN_PB14K_PCC_DATA8 _L_(46) /**< \brief PCC signal: DATA8 on PB14 mux K */ +#define MUX_PB14K_PCC_DATA8 _L_(10) +#define PINMUX_PB14K_PCC_DATA8 ((PIN_PB14K_PCC_DATA8 << 16) | MUX_PB14K_PCC_DATA8) +#define PORT_PB14K_PCC_DATA8 (_UL_(1) << 14) +#define PIN_PB15K_PCC_DATA9 _L_(47) /**< \brief PCC signal: DATA9 on PB15 mux K */ +#define MUX_PB15K_PCC_DATA9 _L_(10) +#define PINMUX_PB15K_PCC_DATA9 ((PIN_PB15K_PCC_DATA9 << 16) | MUX_PB15K_PCC_DATA9) +#define PORT_PB15K_PCC_DATA9 (_UL_(1) << 15) +#define PIN_PC12K_PCC_DATA10 _L_(76) /**< \brief PCC signal: DATA10 on PC12 mux K */ +#define MUX_PC12K_PCC_DATA10 _L_(10) +#define PINMUX_PC12K_PCC_DATA10 ((PIN_PC12K_PCC_DATA10 << 16) | MUX_PC12K_PCC_DATA10) +#define PORT_PC12K_PCC_DATA10 (_UL_(1) << 12) +#define PIN_PC13K_PCC_DATA11 _L_(77) /**< \brief PCC signal: DATA11 on PC13 mux K */ +#define MUX_PC13K_PCC_DATA11 _L_(10) +#define PINMUX_PC13K_PCC_DATA11 ((PIN_PC13K_PCC_DATA11 << 16) | MUX_PC13K_PCC_DATA11) +#define PORT_PC13K_PCC_DATA11 (_UL_(1) << 13) +#define PIN_PC14K_PCC_DATA12 _L_(78) /**< \brief PCC signal: DATA12 on PC14 mux K */ +#define MUX_PC14K_PCC_DATA12 _L_(10) +#define PINMUX_PC14K_PCC_DATA12 ((PIN_PC14K_PCC_DATA12 << 16) | MUX_PC14K_PCC_DATA12) +#define PORT_PC14K_PCC_DATA12 (_UL_(1) << 14) +#define PIN_PC15K_PCC_DATA13 _L_(79) /**< \brief PCC signal: DATA13 on PC15 mux K */ +#define MUX_PC15K_PCC_DATA13 _L_(10) +#define PINMUX_PC15K_PCC_DATA13 ((PIN_PC15K_PCC_DATA13 << 16) | MUX_PC15K_PCC_DATA13) +#define PORT_PC15K_PCC_DATA13 (_UL_(1) << 15) +#define PIN_PA12K_PCC_DEN1 _L_(12) /**< \brief PCC signal: DEN1 on PA12 mux K */ +#define MUX_PA12K_PCC_DEN1 _L_(10) +#define PINMUX_PA12K_PCC_DEN1 ((PIN_PA12K_PCC_DEN1 << 16) | MUX_PA12K_PCC_DEN1) +#define PORT_PA12K_PCC_DEN1 (_UL_(1) << 12) +#define PIN_PA13K_PCC_DEN2 _L_(13) /**< \brief PCC signal: DEN2 on PA13 mux K */ +#define MUX_PA13K_PCC_DEN2 _L_(10) +#define PINMUX_PA13K_PCC_DEN2 ((PIN_PA13K_PCC_DEN2 << 16) | MUX_PA13K_PCC_DEN2) +#define PORT_PA13K_PCC_DEN2 (_UL_(1) << 13) +/* ========== PORT definition for SDHC0 peripheral ========== */ +#define PIN_PA06I_SDHC0_SDCD _L_(6) /**< \brief SDHC0 signal: SDCD on PA06 mux I */ +#define MUX_PA06I_SDHC0_SDCD _L_(8) +#define PINMUX_PA06I_SDHC0_SDCD ((PIN_PA06I_SDHC0_SDCD << 16) | MUX_PA06I_SDHC0_SDCD) +#define PORT_PA06I_SDHC0_SDCD (_UL_(1) << 6) +#define PIN_PA12I_SDHC0_SDCD _L_(12) /**< \brief SDHC0 signal: SDCD on PA12 mux I */ +#define MUX_PA12I_SDHC0_SDCD _L_(8) +#define PINMUX_PA12I_SDHC0_SDCD ((PIN_PA12I_SDHC0_SDCD << 16) | MUX_PA12I_SDHC0_SDCD) +#define PORT_PA12I_SDHC0_SDCD (_UL_(1) << 12) +#define PIN_PB12I_SDHC0_SDCD _L_(44) /**< \brief SDHC0 signal: SDCD on PB12 mux I */ +#define MUX_PB12I_SDHC0_SDCD _L_(8) +#define PINMUX_PB12I_SDHC0_SDCD ((PIN_PB12I_SDHC0_SDCD << 16) | MUX_PB12I_SDHC0_SDCD) +#define PORT_PB12I_SDHC0_SDCD (_UL_(1) << 12) +#define PIN_PC06I_SDHC0_SDCD _L_(70) /**< \brief SDHC0 signal: SDCD on PC06 mux I */ +#define MUX_PC06I_SDHC0_SDCD _L_(8) +#define PINMUX_PC06I_SDHC0_SDCD ((PIN_PC06I_SDHC0_SDCD << 16) | MUX_PC06I_SDHC0_SDCD) +#define PORT_PC06I_SDHC0_SDCD (_UL_(1) << 6) +#define PIN_PB11I_SDHC0_SDCK _L_(43) /**< \brief SDHC0 signal: SDCK on PB11 mux I */ +#define MUX_PB11I_SDHC0_SDCK _L_(8) +#define PINMUX_PB11I_SDHC0_SDCK ((PIN_PB11I_SDHC0_SDCK << 16) | MUX_PB11I_SDHC0_SDCK) +#define PORT_PB11I_SDHC0_SDCK (_UL_(1) << 11) +#define PIN_PA08I_SDHC0_SDCMD _L_(8) /**< \brief SDHC0 signal: SDCMD on PA08 mux I */ +#define MUX_PA08I_SDHC0_SDCMD _L_(8) +#define PINMUX_PA08I_SDHC0_SDCMD ((PIN_PA08I_SDHC0_SDCMD << 16) | MUX_PA08I_SDHC0_SDCMD) +#define PORT_PA08I_SDHC0_SDCMD (_UL_(1) << 8) +#define PIN_PA09I_SDHC0_SDDAT0 _L_(9) /**< \brief SDHC0 signal: SDDAT0 on PA09 mux I */ +#define MUX_PA09I_SDHC0_SDDAT0 _L_(8) +#define PINMUX_PA09I_SDHC0_SDDAT0 ((PIN_PA09I_SDHC0_SDDAT0 << 16) | MUX_PA09I_SDHC0_SDDAT0) +#define PORT_PA09I_SDHC0_SDDAT0 (_UL_(1) << 9) +#define PIN_PA10I_SDHC0_SDDAT1 _L_(10) /**< \brief SDHC0 signal: SDDAT1 on PA10 mux I */ +#define MUX_PA10I_SDHC0_SDDAT1 _L_(8) +#define PINMUX_PA10I_SDHC0_SDDAT1 ((PIN_PA10I_SDHC0_SDDAT1 << 16) | MUX_PA10I_SDHC0_SDDAT1) +#define PORT_PA10I_SDHC0_SDDAT1 (_UL_(1) << 10) +#define PIN_PA11I_SDHC0_SDDAT2 _L_(11) /**< \brief SDHC0 signal: SDDAT2 on PA11 mux I */ +#define MUX_PA11I_SDHC0_SDDAT2 _L_(8) +#define PINMUX_PA11I_SDHC0_SDDAT2 ((PIN_PA11I_SDHC0_SDDAT2 << 16) | MUX_PA11I_SDHC0_SDDAT2) +#define PORT_PA11I_SDHC0_SDDAT2 (_UL_(1) << 11) +#define PIN_PB10I_SDHC0_SDDAT3 _L_(42) /**< \brief SDHC0 signal: SDDAT3 on PB10 mux I */ +#define MUX_PB10I_SDHC0_SDDAT3 _L_(8) +#define PINMUX_PB10I_SDHC0_SDDAT3 ((PIN_PB10I_SDHC0_SDDAT3 << 16) | MUX_PB10I_SDHC0_SDDAT3) +#define PORT_PB10I_SDHC0_SDDAT3 (_UL_(1) << 10) +#define PIN_PA07I_SDHC0_SDWP _L_(7) /**< \brief SDHC0 signal: SDWP on PA07 mux I */ +#define MUX_PA07I_SDHC0_SDWP _L_(8) +#define PINMUX_PA07I_SDHC0_SDWP ((PIN_PA07I_SDHC0_SDWP << 16) | MUX_PA07I_SDHC0_SDWP) +#define PORT_PA07I_SDHC0_SDWP (_UL_(1) << 7) +#define PIN_PA13I_SDHC0_SDWP _L_(13) /**< \brief SDHC0 signal: SDWP on PA13 mux I */ +#define MUX_PA13I_SDHC0_SDWP _L_(8) +#define PINMUX_PA13I_SDHC0_SDWP ((PIN_PA13I_SDHC0_SDWP << 16) | MUX_PA13I_SDHC0_SDWP) +#define PORT_PA13I_SDHC0_SDWP (_UL_(1) << 13) +#define PIN_PB13I_SDHC0_SDWP _L_(45) /**< \brief SDHC0 signal: SDWP on PB13 mux I */ +#define MUX_PB13I_SDHC0_SDWP _L_(8) +#define PINMUX_PB13I_SDHC0_SDWP ((PIN_PB13I_SDHC0_SDWP << 16) | MUX_PB13I_SDHC0_SDWP) +#define PORT_PB13I_SDHC0_SDWP (_UL_(1) << 13) +#define PIN_PC07I_SDHC0_SDWP _L_(71) /**< \brief SDHC0 signal: SDWP on PC07 mux I */ +#define MUX_PC07I_SDHC0_SDWP _L_(8) +#define PINMUX_PC07I_SDHC0_SDWP ((PIN_PC07I_SDHC0_SDWP << 16) | MUX_PC07I_SDHC0_SDWP) +#define PORT_PC07I_SDHC0_SDWP (_UL_(1) << 7) +/* ========== PORT definition for SDHC1 peripheral ========== */ +#define PIN_PB16I_SDHC1_SDCD _L_(48) /**< \brief SDHC1 signal: SDCD on PB16 mux I */ +#define MUX_PB16I_SDHC1_SDCD _L_(8) +#define PINMUX_PB16I_SDHC1_SDCD ((PIN_PB16I_SDHC1_SDCD << 16) | MUX_PB16I_SDHC1_SDCD) +#define PORT_PB16I_SDHC1_SDCD (_UL_(1) << 16) +#define PIN_PC20I_SDHC1_SDCD _L_(84) /**< \brief SDHC1 signal: SDCD on PC20 mux I */ +#define MUX_PC20I_SDHC1_SDCD _L_(8) +#define PINMUX_PC20I_SDHC1_SDCD ((PIN_PC20I_SDHC1_SDCD << 16) | MUX_PC20I_SDHC1_SDCD) +#define PORT_PC20I_SDHC1_SDCD (_UL_(1) << 20) +#define PIN_PA21I_SDHC1_SDCK _L_(21) /**< \brief SDHC1 signal: SDCK on PA21 mux I */ +#define MUX_PA21I_SDHC1_SDCK _L_(8) +#define PINMUX_PA21I_SDHC1_SDCK ((PIN_PA21I_SDHC1_SDCK << 16) | MUX_PA21I_SDHC1_SDCK) +#define PORT_PA21I_SDHC1_SDCK (_UL_(1) << 21) +#define PIN_PA20I_SDHC1_SDCMD _L_(20) /**< \brief SDHC1 signal: SDCMD on PA20 mux I */ +#define MUX_PA20I_SDHC1_SDCMD _L_(8) +#define PINMUX_PA20I_SDHC1_SDCMD ((PIN_PA20I_SDHC1_SDCMD << 16) | MUX_PA20I_SDHC1_SDCMD) +#define PORT_PA20I_SDHC1_SDCMD (_UL_(1) << 20) +#define PIN_PB18I_SDHC1_SDDAT0 _L_(50) /**< \brief SDHC1 signal: SDDAT0 on PB18 mux I */ +#define MUX_PB18I_SDHC1_SDDAT0 _L_(8) +#define PINMUX_PB18I_SDHC1_SDDAT0 ((PIN_PB18I_SDHC1_SDDAT0 << 16) | MUX_PB18I_SDHC1_SDDAT0) +#define PORT_PB18I_SDHC1_SDDAT0 (_UL_(1) << 18) +#define PIN_PB19I_SDHC1_SDDAT1 _L_(51) /**< \brief SDHC1 signal: SDDAT1 on PB19 mux I */ +#define MUX_PB19I_SDHC1_SDDAT1 _L_(8) +#define PINMUX_PB19I_SDHC1_SDDAT1 ((PIN_PB19I_SDHC1_SDDAT1 << 16) | MUX_PB19I_SDHC1_SDDAT1) +#define PORT_PB19I_SDHC1_SDDAT1 (_UL_(1) << 19) +#define PIN_PB20I_SDHC1_SDDAT2 _L_(52) /**< \brief SDHC1 signal: SDDAT2 on PB20 mux I */ +#define MUX_PB20I_SDHC1_SDDAT2 _L_(8) +#define PINMUX_PB20I_SDHC1_SDDAT2 ((PIN_PB20I_SDHC1_SDDAT2 << 16) | MUX_PB20I_SDHC1_SDDAT2) +#define PORT_PB20I_SDHC1_SDDAT2 (_UL_(1) << 20) +#define PIN_PB21I_SDHC1_SDDAT3 _L_(53) /**< \brief SDHC1 signal: SDDAT3 on PB21 mux I */ +#define MUX_PB21I_SDHC1_SDDAT3 _L_(8) +#define PINMUX_PB21I_SDHC1_SDDAT3 ((PIN_PB21I_SDHC1_SDDAT3 << 16) | MUX_PB21I_SDHC1_SDDAT3) +#define PORT_PB21I_SDHC1_SDDAT3 (_UL_(1) << 21) +#define PIN_PB17I_SDHC1_SDWP _L_(49) /**< \brief SDHC1 signal: SDWP on PB17 mux I */ +#define MUX_PB17I_SDHC1_SDWP _L_(8) +#define PINMUX_PB17I_SDHC1_SDWP ((PIN_PB17I_SDHC1_SDWP << 16) | MUX_PB17I_SDHC1_SDWP) +#define PORT_PB17I_SDHC1_SDWP (_UL_(1) << 17) +#define PIN_PC21I_SDHC1_SDWP _L_(85) /**< \brief SDHC1 signal: SDWP on PC21 mux I */ +#define MUX_PC21I_SDHC1_SDWP _L_(8) +#define PINMUX_PC21I_SDHC1_SDWP ((PIN_PC21I_SDHC1_SDWP << 16) | MUX_PC21I_SDHC1_SDWP) +#define PORT_PC21I_SDHC1_SDWP (_UL_(1) << 21) + +#endif /* _SAME54N19A_PIO_ */ diff --git a/arch/arm/SAME54/SAME54A/mcu/inc/pio/same54n20a.h b/arch/arm/SAME54/SAME54A/mcu/inc/pio/same54n20a.h index 135c7713..d8a7ac4b 100644 --- a/arch/arm/SAME54/SAME54A/mcu/inc/pio/same54n20a.h +++ b/arch/arm/SAME54/SAME54A/mcu/inc/pio/same54n20a.h @@ -1,3239 +1,2688 @@ -/** - * \brief Peripheral I/O description for SAME54N20A - * - * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries. - * - * Subject to your compliance with these terms, you may use Microchip software and any derivatives - * exclusively with Microchip products. It is your responsibility to comply with third party license - * terms applicable to your use of third party software (including open source software) that may - * accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, - * APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND - * FITNESS FOR A PARTICULAR PURPOSE. - * - * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF - * MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT - * EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - */ - -/* file generated from device description version 2020-03-12T17:26:59Z */ -#ifndef _SAME54N20A_GPIO_H_ -#define _SAME54N20A_GPIO_H_ - -/* ========== Peripheral I/O pin numbers ========== */ -#define PIN_PA00 ( 0 ) /**< Pin Number for PA00 */ -#define PIN_PA01 ( 1 ) /**< Pin Number for PA01 */ -#define PIN_PA02 ( 2 ) /**< Pin Number for PA02 */ -#define PIN_PA03 ( 3 ) /**< Pin Number for PA03 */ -#define PIN_PA04 ( 4 ) /**< Pin Number for PA04 */ -#define PIN_PA05 ( 5 ) /**< Pin Number for PA05 */ -#define PIN_PA06 ( 6 ) /**< Pin Number for PA06 */ -#define PIN_PA07 ( 7 ) /**< Pin Number for PA07 */ -#define PIN_PA08 ( 8 ) /**< Pin Number for PA08 */ -#define PIN_PA09 ( 9 ) /**< Pin Number for PA09 */ -#define PIN_PA10 ( 10 ) /**< Pin Number for PA10 */ -#define PIN_PA11 ( 11 ) /**< Pin Number for PA11 */ -#define PIN_PA12 ( 12 ) /**< Pin Number for PA12 */ -#define PIN_PA13 ( 13 ) /**< Pin Number for PA13 */ -#define PIN_PA14 ( 14 ) /**< Pin Number for PA14 */ -#define PIN_PA15 ( 15 ) /**< Pin Number for PA15 */ -#define PIN_PA16 ( 16 ) /**< Pin Number for PA16 */ -#define PIN_PA17 ( 17 ) /**< Pin Number for PA17 */ -#define PIN_PA18 ( 18 ) /**< Pin Number for PA18 */ -#define PIN_PA19 ( 19 ) /**< Pin Number for PA19 */ -#define PIN_PA20 ( 20 ) /**< Pin Number for PA20 */ -#define PIN_PA21 ( 21 ) /**< Pin Number for PA21 */ -#define PIN_PA22 ( 22 ) /**< Pin Number for PA22 */ -#define PIN_PA23 ( 23 ) /**< Pin Number for PA23 */ -#define PIN_PA24 ( 24 ) /**< Pin Number for PA24 */ -#define PIN_PA25 ( 25 ) /**< Pin Number for PA25 */ -#define PIN_PA27 ( 27 ) /**< Pin Number for PA27 */ -#define PIN_PA30 ( 30 ) /**< Pin Number for PA30 */ -#define PIN_PA31 ( 31 ) /**< Pin Number for PA31 */ -#define PIN_PB00 ( 32 ) /**< Pin Number for PB00 */ -#define PIN_PB01 ( 33 ) /**< Pin Number for PB01 */ -#define PIN_PB02 ( 34 ) /**< Pin Number for PB02 */ -#define PIN_PB03 ( 35 ) /**< Pin Number for PB03 */ -#define PIN_PB04 ( 36 ) /**< Pin Number for PB04 */ -#define PIN_PB05 ( 37 ) /**< Pin Number for PB05 */ -#define PIN_PB06 ( 38 ) /**< Pin Number for PB06 */ -#define PIN_PB07 ( 39 ) /**< Pin Number for PB07 */ -#define PIN_PB08 ( 40 ) /**< Pin Number for PB08 */ -#define PIN_PB09 ( 41 ) /**< Pin Number for PB09 */ -#define PIN_PB10 ( 42 ) /**< Pin Number for PB10 */ -#define PIN_PB11 ( 43 ) /**< Pin Number for PB11 */ -#define PIN_PB12 ( 44 ) /**< Pin Number for PB12 */ -#define PIN_PB13 ( 45 ) /**< Pin Number for PB13 */ -#define PIN_PB14 ( 46 ) /**< Pin Number for PB14 */ -#define PIN_PB15 ( 47 ) /**< Pin Number for PB15 */ -#define PIN_PB16 ( 48 ) /**< Pin Number for PB16 */ -#define PIN_PB17 ( 49 ) /**< Pin Number for PB17 */ -#define PIN_PB18 ( 50 ) /**< Pin Number for PB18 */ -#define PIN_PB19 ( 51 ) /**< Pin Number for PB19 */ -#define PIN_PB20 ( 52 ) /**< Pin Number for PB20 */ -#define PIN_PB21 ( 53 ) /**< Pin Number for PB21 */ -#define PIN_PB22 ( 54 ) /**< Pin Number for PB22 */ -#define PIN_PB23 ( 55 ) /**< Pin Number for PB23 */ -#define PIN_PB24 ( 56 ) /**< Pin Number for PB24 */ -#define PIN_PB25 ( 57 ) /**< Pin Number for PB25 */ -#define PIN_PB30 ( 62 ) /**< Pin Number for PB30 */ -#define PIN_PB31 ( 63 ) /**< Pin Number for PB31 */ -#define PIN_PC00 ( 64 ) /**< Pin Number for PC00 */ -#define PIN_PC01 ( 65 ) /**< Pin Number for PC01 */ -#define PIN_PC02 ( 66 ) /**< Pin Number for PC02 */ -#define PIN_PC03 ( 67 ) /**< Pin Number for PC03 */ -#define PIN_PC05 ( 69 ) /**< Pin Number for PC05 */ -#define PIN_PC06 ( 70 ) /**< Pin Number for PC06 */ -#define PIN_PC07 ( 71 ) /**< Pin Number for PC07 */ -#define PIN_PC10 ( 74 ) /**< Pin Number for PC10 */ -#define PIN_PC11 ( 75 ) /**< Pin Number for PC11 */ -#define PIN_PC12 ( 76 ) /**< Pin Number for PC12 */ -#define PIN_PC13 ( 77 ) /**< Pin Number for PC13 */ -#define PIN_PC14 ( 78 ) /**< Pin Number for PC14 */ -#define PIN_PC15 ( 79 ) /**< Pin Number for PC15 */ -#define PIN_PC16 ( 80 ) /**< Pin Number for PC16 */ -#define PIN_PC17 ( 81 ) /**< Pin Number for PC17 */ -#define PIN_PC18 ( 82 ) /**< Pin Number for PC18 */ -#define PIN_PC19 ( 83 ) /**< Pin Number for PC19 */ -#define PIN_PC20 ( 84 ) /**< Pin Number for PC20 */ -#define PIN_PC21 ( 85 ) /**< Pin Number for PC21 */ -#define PIN_PC24 ( 88 ) /**< Pin Number for PC24 */ -#define PIN_PC25 ( 89 ) /**< Pin Number for PC25 */ -#define PIN_PC26 ( 90 ) /**< Pin Number for PC26 */ -#define PIN_PC27 ( 91 ) /**< Pin Number for PC27 */ -#define PIN_PC28 ( 92 ) /**< Pin Number for PC28 */ - -/* ========== Peripheral I/O masks ========== */ -#define PORT_PA00 (_U_(1) << 0) /**< PORT mask for PA00 */ -#define PORT_PA01 (_U_(1) << 1) /**< PORT mask for PA01 */ -#define PORT_PA02 (_U_(1) << 2) /**< PORT mask for PA02 */ -#define PORT_PA03 (_U_(1) << 3) /**< PORT mask for PA03 */ -#define PORT_PA04 (_U_(1) << 4) /**< PORT mask for PA04 */ -#define PORT_PA05 (_U_(1) << 5) /**< PORT mask for PA05 */ -#define PORT_PA06 (_U_(1) << 6) /**< PORT mask for PA06 */ -#define PORT_PA07 (_U_(1) << 7) /**< PORT mask for PA07 */ -#define PORT_PA08 (_U_(1) << 8) /**< PORT mask for PA08 */ -#define PORT_PA09 (_U_(1) << 9) /**< PORT mask for PA09 */ -#define PORT_PA10 (_U_(1) << 10) /**< PORT mask for PA10 */ -#define PORT_PA11 (_U_(1) << 11) /**< PORT mask for PA11 */ -#define PORT_PA12 (_U_(1) << 12) /**< PORT mask for PA12 */ -#define PORT_PA13 (_U_(1) << 13) /**< PORT mask for PA13 */ -#define PORT_PA14 (_U_(1) << 14) /**< PORT mask for PA14 */ -#define PORT_PA15 (_U_(1) << 15) /**< PORT mask for PA15 */ -#define PORT_PA16 (_U_(1) << 16) /**< PORT mask for PA16 */ -#define PORT_PA17 (_U_(1) << 17) /**< PORT mask for PA17 */ -#define PORT_PA18 (_U_(1) << 18) /**< PORT mask for PA18 */ -#define PORT_PA19 (_U_(1) << 19) /**< PORT mask for PA19 */ -#define PORT_PA20 (_U_(1) << 20) /**< PORT mask for PA20 */ -#define PORT_PA21 (_U_(1) << 21) /**< PORT mask for PA21 */ -#define PORT_PA22 (_U_(1) << 22) /**< PORT mask for PA22 */ -#define PORT_PA23 (_U_(1) << 23) /**< PORT mask for PA23 */ -#define PORT_PA24 (_U_(1) << 24) /**< PORT mask for PA24 */ -#define PORT_PA25 (_U_(1) << 25) /**< PORT mask for PA25 */ -#define PORT_PA27 (_U_(1) << 27) /**< PORT mask for PA27 */ -#define PORT_PA30 (_U_(1) << 30) /**< PORT mask for PA30 */ -#define PORT_PA31 (_U_(1) << 31) /**< PORT mask for PA31 */ -#define PORT_PB00 (_U_(1) << 0) /**< PORT mask for PB00 */ -#define PORT_PB01 (_U_(1) << 1) /**< PORT mask for PB01 */ -#define PORT_PB02 (_U_(1) << 2) /**< PORT mask for PB02 */ -#define PORT_PB03 (_U_(1) << 3) /**< PORT mask for PB03 */ -#define PORT_PB04 (_U_(1) << 4) /**< PORT mask for PB04 */ -#define PORT_PB05 (_U_(1) << 5) /**< PORT mask for PB05 */ -#define PORT_PB06 (_U_(1) << 6) /**< PORT mask for PB06 */ -#define PORT_PB07 (_U_(1) << 7) /**< PORT mask for PB07 */ -#define PORT_PB08 (_U_(1) << 8) /**< PORT mask for PB08 */ -#define PORT_PB09 (_U_(1) << 9) /**< PORT mask for PB09 */ -#define PORT_PB10 (_U_(1) << 10) /**< PORT mask for PB10 */ -#define PORT_PB11 (_U_(1) << 11) /**< PORT mask for PB11 */ -#define PORT_PB12 (_U_(1) << 12) /**< PORT mask for PB12 */ -#define PORT_PB13 (_U_(1) << 13) /**< PORT mask for PB13 */ -#define PORT_PB14 (_U_(1) << 14) /**< PORT mask for PB14 */ -#define PORT_PB15 (_U_(1) << 15) /**< PORT mask for PB15 */ -#define PORT_PB16 (_U_(1) << 16) /**< PORT mask for PB16 */ -#define PORT_PB17 (_U_(1) << 17) /**< PORT mask for PB17 */ -#define PORT_PB18 (_U_(1) << 18) /**< PORT mask for PB18 */ -#define PORT_PB19 (_U_(1) << 19) /**< PORT mask for PB19 */ -#define PORT_PB20 (_U_(1) << 20) /**< PORT mask for PB20 */ -#define PORT_PB21 (_U_(1) << 21) /**< PORT mask for PB21 */ -#define PORT_PB22 (_U_(1) << 22) /**< PORT mask for PB22 */ -#define PORT_PB23 (_U_(1) << 23) /**< PORT mask for PB23 */ -#define PORT_PB24 (_U_(1) << 24) /**< PORT mask for PB24 */ -#define PORT_PB25 (_U_(1) << 25) /**< PORT mask for PB25 */ -#define PORT_PB30 (_U_(1) << 30) /**< PORT mask for PB30 */ -#define PORT_PB31 (_U_(1) << 31) /**< PORT mask for PB31 */ -#define PORT_PC00 (_U_(1) << 0) /**< PORT mask for PC00 */ -#define PORT_PC01 (_U_(1) << 1) /**< PORT mask for PC01 */ -#define PORT_PC02 (_U_(1) << 2) /**< PORT mask for PC02 */ -#define PORT_PC03 (_U_(1) << 3) /**< PORT mask for PC03 */ -#define PORT_PC05 (_U_(1) << 5) /**< PORT mask for PC05 */ -#define PORT_PC06 (_U_(1) << 6) /**< PORT mask for PC06 */ -#define PORT_PC07 (_U_(1) << 7) /**< PORT mask for PC07 */ -#define PORT_PC10 (_U_(1) << 10) /**< PORT mask for PC10 */ -#define PORT_PC11 (_U_(1) << 11) /**< PORT mask for PC11 */ -#define PORT_PC12 (_U_(1) << 12) /**< PORT mask for PC12 */ -#define PORT_PC13 (_U_(1) << 13) /**< PORT mask for PC13 */ -#define PORT_PC14 (_U_(1) << 14) /**< PORT mask for PC14 */ -#define PORT_PC15 (_U_(1) << 15) /**< PORT mask for PC15 */ -#define PORT_PC16 (_U_(1) << 16) /**< PORT mask for PC16 */ -#define PORT_PC17 (_U_(1) << 17) /**< PORT mask for PC17 */ -#define PORT_PC18 (_U_(1) << 18) /**< PORT mask for PC18 */ -#define PORT_PC19 (_U_(1) << 19) /**< PORT mask for PC19 */ -#define PORT_PC20 (_U_(1) << 20) /**< PORT mask for PC20 */ -#define PORT_PC21 (_U_(1) << 21) /**< PORT mask for PC21 */ -#define PORT_PC24 (_U_(1) << 24) /**< PORT mask for PC24 */ -#define PORT_PC25 (_U_(1) << 25) /**< PORT mask for PC25 */ -#define PORT_PC26 (_U_(1) << 26) /**< PORT mask for PC26 */ -#define PORT_PC27 (_U_(1) << 27) /**< PORT mask for PC27 */ -#define PORT_PC28 (_U_(1) << 28) /**< PORT mask for PC28 */ - -/* ========== PORT definition for AC peripheral ========== */ -#define PIN_PA04B_AC_AIN0 (4L) -#define MUX_PA04B_AC_AIN0 (1L) -#define PINMUX_PA04B_AC_AIN0 ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0) -#define PORT_PA04B_AC_AIN0 ((1UL) << 4) - -#define PIN_PA05B_AC_AIN1 (5L) -#define MUX_PA05B_AC_AIN1 (1L) -#define PINMUX_PA05B_AC_AIN1 ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1) -#define PORT_PA05B_AC_AIN1 ((1UL) << 5) - -#define PIN_PA06B_AC_AIN2 (6L) -#define MUX_PA06B_AC_AIN2 (1L) -#define PINMUX_PA06B_AC_AIN2 ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2) -#define PORT_PA06B_AC_AIN2 ((1UL) << 6) - -#define PIN_PA07B_AC_AIN3 (7L) -#define MUX_PA07B_AC_AIN3 (1L) -#define PINMUX_PA07B_AC_AIN3 ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3) -#define PORT_PA07B_AC_AIN3 ((1UL) << 7) - -#define PIN_PA12M_AC_CMP0 (12L) -#define MUX_PA12M_AC_CMP0 (12L) -#define PINMUX_PA12M_AC_CMP0 ((PIN_PA12M_AC_CMP0 << 16) | MUX_PA12M_AC_CMP0) -#define PORT_PA12M_AC_CMP0 ((1UL) << 12) - -#define PIN_PA18M_AC_CMP0 (18L) -#define MUX_PA18M_AC_CMP0 (12L) -#define PINMUX_PA18M_AC_CMP0 ((PIN_PA18M_AC_CMP0 << 16) | MUX_PA18M_AC_CMP0) -#define PORT_PA18M_AC_CMP0 ((1UL) << 18) - -#define PIN_PB24M_AC_CMP0 (56L) -#define MUX_PB24M_AC_CMP0 (12L) -#define PINMUX_PB24M_AC_CMP0 ((PIN_PB24M_AC_CMP0 << 16) | MUX_PB24M_AC_CMP0) -#define PORT_PB24M_AC_CMP0 ((1UL) << 24) - -#define PIN_PA13M_AC_CMP1 (13L) -#define MUX_PA13M_AC_CMP1 (12L) -#define PINMUX_PA13M_AC_CMP1 ((PIN_PA13M_AC_CMP1 << 16) | MUX_PA13M_AC_CMP1) -#define PORT_PA13M_AC_CMP1 ((1UL) << 13) - -#define PIN_PA19M_AC_CMP1 (19L) -#define MUX_PA19M_AC_CMP1 (12L) -#define PINMUX_PA19M_AC_CMP1 ((PIN_PA19M_AC_CMP1 << 16) | MUX_PA19M_AC_CMP1) -#define PORT_PA19M_AC_CMP1 ((1UL) << 19) - -#define PIN_PB25M_AC_CMP1 (57L) -#define MUX_PB25M_AC_CMP1 (12L) -#define PINMUX_PB25M_AC_CMP1 ((PIN_PB25M_AC_CMP1 << 16) | MUX_PB25M_AC_CMP1) -#define PORT_PB25M_AC_CMP1 ((1UL) << 25) - -/* ========== PORT definition for ADC0 peripheral ========== */ -#define PIN_PA02B_ADC0_AIN0 (2L) -#define MUX_PA02B_ADC0_AIN0 (1L) -#define PINMUX_PA02B_ADC0_AIN0 ((PIN_PA02B_ADC0_AIN0 << 16) | MUX_PA02B_ADC0_AIN0) -#define PORT_PA02B_ADC0_AIN0 ((1UL) << 2) - -#define PIN_PA03B_ADC0_AIN1 (3L) -#define MUX_PA03B_ADC0_AIN1 (1L) -#define PINMUX_PA03B_ADC0_AIN1 ((PIN_PA03B_ADC0_AIN1 << 16) | MUX_PA03B_ADC0_AIN1) -#define PORT_PA03B_ADC0_AIN1 ((1UL) << 3) - -#define PIN_PB08B_ADC0_AIN2 (40L) -#define MUX_PB08B_ADC0_AIN2 (1L) -#define PINMUX_PB08B_ADC0_AIN2 ((PIN_PB08B_ADC0_AIN2 << 16) | MUX_PB08B_ADC0_AIN2) -#define PORT_PB08B_ADC0_AIN2 ((1UL) << 8) - -#define PIN_PB09B_ADC0_AIN3 (41L) -#define MUX_PB09B_ADC0_AIN3 (1L) -#define PINMUX_PB09B_ADC0_AIN3 ((PIN_PB09B_ADC0_AIN3 << 16) | MUX_PB09B_ADC0_AIN3) -#define PORT_PB09B_ADC0_AIN3 ((1UL) << 9) - -#define PIN_PA04B_ADC0_AIN4 (4L) -#define MUX_PA04B_ADC0_AIN4 (1L) -#define PINMUX_PA04B_ADC0_AIN4 ((PIN_PA04B_ADC0_AIN4 << 16) | MUX_PA04B_ADC0_AIN4) -#define PORT_PA04B_ADC0_AIN4 ((1UL) << 4) - -#define PIN_PA05B_ADC0_AIN5 (5L) -#define MUX_PA05B_ADC0_AIN5 (1L) -#define PINMUX_PA05B_ADC0_AIN5 ((PIN_PA05B_ADC0_AIN5 << 16) | MUX_PA05B_ADC0_AIN5) -#define PORT_PA05B_ADC0_AIN5 ((1UL) << 5) - -#define PIN_PA06B_ADC0_AIN6 (6L) -#define MUX_PA06B_ADC0_AIN6 (1L) -#define PINMUX_PA06B_ADC0_AIN6 ((PIN_PA06B_ADC0_AIN6 << 16) | MUX_PA06B_ADC0_AIN6) -#define PORT_PA06B_ADC0_AIN6 ((1UL) << 6) - -#define PIN_PA07B_ADC0_AIN7 (7L) -#define MUX_PA07B_ADC0_AIN7 (1L) -#define PINMUX_PA07B_ADC0_AIN7 ((PIN_PA07B_ADC0_AIN7 << 16) | MUX_PA07B_ADC0_AIN7) -#define PORT_PA07B_ADC0_AIN7 ((1UL) << 7) - -#define PIN_PA08B_ADC0_AIN8 (8L) -#define MUX_PA08B_ADC0_AIN8 (1L) -#define PINMUX_PA08B_ADC0_AIN8 ((PIN_PA08B_ADC0_AIN8 << 16) | MUX_PA08B_ADC0_AIN8) -#define PORT_PA08B_ADC0_AIN8 ((1UL) << 8) - -#define PIN_PA09B_ADC0_AIN9 (9L) -#define MUX_PA09B_ADC0_AIN9 (1L) -#define PINMUX_PA09B_ADC0_AIN9 ((PIN_PA09B_ADC0_AIN9 << 16) | MUX_PA09B_ADC0_AIN9) -#define PORT_PA09B_ADC0_AIN9 ((1UL) << 9) - -#define PIN_PA10B_ADC0_AIN10 (10L) -#define MUX_PA10B_ADC0_AIN10 (1L) -#define PINMUX_PA10B_ADC0_AIN10 ((PIN_PA10B_ADC0_AIN10 << 16) | MUX_PA10B_ADC0_AIN10) -#define PORT_PA10B_ADC0_AIN10 ((1UL) << 10) - -#define PIN_PA11B_ADC0_AIN11 (11L) -#define MUX_PA11B_ADC0_AIN11 (1L) -#define PINMUX_PA11B_ADC0_AIN11 ((PIN_PA11B_ADC0_AIN11 << 16) | MUX_PA11B_ADC0_AIN11) -#define PORT_PA11B_ADC0_AIN11 ((1UL) << 11) - -#define PIN_PB00B_ADC0_AIN12 (32L) -#define MUX_PB00B_ADC0_AIN12 (1L) -#define PINMUX_PB00B_ADC0_AIN12 ((PIN_PB00B_ADC0_AIN12 << 16) | MUX_PB00B_ADC0_AIN12) -#define PORT_PB00B_ADC0_AIN12 ((1UL) << 0) - -#define PIN_PB01B_ADC0_AIN13 (33L) -#define MUX_PB01B_ADC0_AIN13 (1L) -#define PINMUX_PB01B_ADC0_AIN13 ((PIN_PB01B_ADC0_AIN13 << 16) | MUX_PB01B_ADC0_AIN13) -#define PORT_PB01B_ADC0_AIN13 ((1UL) << 1) - -#define PIN_PB02B_ADC0_AIN14 (34L) -#define MUX_PB02B_ADC0_AIN14 (1L) -#define PINMUX_PB02B_ADC0_AIN14 ((PIN_PB02B_ADC0_AIN14 << 16) | MUX_PB02B_ADC0_AIN14) -#define PORT_PB02B_ADC0_AIN14 ((1UL) << 2) - -#define PIN_PB03B_ADC0_AIN15 (35L) -#define MUX_PB03B_ADC0_AIN15 (1L) -#define PINMUX_PB03B_ADC0_AIN15 ((PIN_PB03B_ADC0_AIN15 << 16) | MUX_PB03B_ADC0_AIN15) -#define PORT_PB03B_ADC0_AIN15 ((1UL) << 3) - -#define PIN_PA03B_ADC0_VREFA (3L) -#define MUX_PA03B_ADC0_VREFA (1L) -#define PINMUX_PA03B_ADC0_VREFA ((PIN_PA03B_ADC0_VREFA << 16) | MUX_PA03B_ADC0_VREFA) -#define PORT_PA03B_ADC0_VREFA ((1UL) << 3) - -#define PIN_PA04B_ADC0_VREFB (4L) -#define MUX_PA04B_ADC0_VREFB (1L) -#define PINMUX_PA04B_ADC0_VREFB ((PIN_PA04B_ADC0_VREFB << 16) | MUX_PA04B_ADC0_VREFB) -#define PORT_PA04B_ADC0_VREFB ((1UL) << 4) - -#define PIN_PA06B_ADC0_VREFC (6L) -#define MUX_PA06B_ADC0_VREFC (1L) -#define PINMUX_PA06B_ADC0_VREFC ((PIN_PA06B_ADC0_VREFC << 16) | MUX_PA06B_ADC0_VREFC) -#define PORT_PA06B_ADC0_VREFC ((1UL) << 6) - -#define PIN_PA03B_ADC0_X0 (3L) -#define MUX_PA03B_ADC0_X0 (1L) -#define PINMUX_PA03B_ADC0_X0 ((PIN_PA03B_ADC0_X0 << 16) | MUX_PA03B_ADC0_X0) -#define PORT_PA03B_ADC0_X0 ((1UL) << 3) - -#define PIN_PB08B_ADC0_X1 (40L) -#define MUX_PB08B_ADC0_X1 (1L) -#define PINMUX_PB08B_ADC0_X1 ((PIN_PB08B_ADC0_X1 << 16) | MUX_PB08B_ADC0_X1) -#define PORT_PB08B_ADC0_X1 ((1UL) << 8) - -#define PIN_PB09B_ADC0_X2 (41L) -#define MUX_PB09B_ADC0_X2 (1L) -#define PINMUX_PB09B_ADC0_X2 ((PIN_PB09B_ADC0_X2 << 16) | MUX_PB09B_ADC0_X2) -#define PORT_PB09B_ADC0_X2 ((1UL) << 9) - -#define PIN_PA04B_ADC0_X3 (4L) -#define MUX_PA04B_ADC0_X3 (1L) -#define PINMUX_PA04B_ADC0_X3 ((PIN_PA04B_ADC0_X3 << 16) | MUX_PA04B_ADC0_X3) -#define PORT_PA04B_ADC0_X3 ((1UL) << 4) - -#define PIN_PA06B_ADC0_X4 (6L) -#define MUX_PA06B_ADC0_X4 (1L) -#define PINMUX_PA06B_ADC0_X4 ((PIN_PA06B_ADC0_X4 << 16) | MUX_PA06B_ADC0_X4) -#define PORT_PA06B_ADC0_X4 ((1UL) << 6) - -#define PIN_PA07B_ADC0_X5 (7L) -#define MUX_PA07B_ADC0_X5 (1L) -#define PINMUX_PA07B_ADC0_X5 ((PIN_PA07B_ADC0_X5 << 16) | MUX_PA07B_ADC0_X5) -#define PORT_PA07B_ADC0_X5 ((1UL) << 7) - -#define PIN_PA08B_ADC0_X6 (8L) -#define MUX_PA08B_ADC0_X6 (1L) -#define PINMUX_PA08B_ADC0_X6 ((PIN_PA08B_ADC0_X6 << 16) | MUX_PA08B_ADC0_X6) -#define PORT_PA08B_ADC0_X6 ((1UL) << 8) - -#define PIN_PA09B_ADC0_X7 (9L) -#define MUX_PA09B_ADC0_X7 (1L) -#define PINMUX_PA09B_ADC0_X7 ((PIN_PA09B_ADC0_X7 << 16) | MUX_PA09B_ADC0_X7) -#define PORT_PA09B_ADC0_X7 ((1UL) << 9) - -#define PIN_PA10B_ADC0_X8 (10L) -#define MUX_PA10B_ADC0_X8 (1L) -#define PINMUX_PA10B_ADC0_X8 ((PIN_PA10B_ADC0_X8 << 16) | MUX_PA10B_ADC0_X8) -#define PORT_PA10B_ADC0_X8 ((1UL) << 10) - -#define PIN_PA11B_ADC0_X9 (11L) -#define MUX_PA11B_ADC0_X9 (1L) -#define PINMUX_PA11B_ADC0_X9 ((PIN_PA11B_ADC0_X9 << 16) | MUX_PA11B_ADC0_X9) -#define PORT_PA11B_ADC0_X9 ((1UL) << 11) - -#define PIN_PA16B_ADC0_X10 (16L) -#define MUX_PA16B_ADC0_X10 (1L) -#define PINMUX_PA16B_ADC0_X10 ((PIN_PA16B_ADC0_X10 << 16) | MUX_PA16B_ADC0_X10) -#define PORT_PA16B_ADC0_X10 ((1UL) << 16) - -#define PIN_PA17B_ADC0_X11 (17L) -#define MUX_PA17B_ADC0_X11 (1L) -#define PINMUX_PA17B_ADC0_X11 ((PIN_PA17B_ADC0_X11 << 16) | MUX_PA17B_ADC0_X11) -#define PORT_PA17B_ADC0_X11 ((1UL) << 17) - -#define PIN_PA18B_ADC0_X12 (18L) -#define MUX_PA18B_ADC0_X12 (1L) -#define PINMUX_PA18B_ADC0_X12 ((PIN_PA18B_ADC0_X12 << 16) | MUX_PA18B_ADC0_X12) -#define PORT_PA18B_ADC0_X12 ((1UL) << 18) - -#define PIN_PA19B_ADC0_X13 (19L) -#define MUX_PA19B_ADC0_X13 (1L) -#define PINMUX_PA19B_ADC0_X13 ((PIN_PA19B_ADC0_X13 << 16) | MUX_PA19B_ADC0_X13) -#define PORT_PA19B_ADC0_X13 ((1UL) << 19) - -#define PIN_PA20B_ADC0_X14 (20L) -#define MUX_PA20B_ADC0_X14 (1L) -#define PINMUX_PA20B_ADC0_X14 ((PIN_PA20B_ADC0_X14 << 16) | MUX_PA20B_ADC0_X14) -#define PORT_PA20B_ADC0_X14 ((1UL) << 20) - -#define PIN_PA21B_ADC0_X15 (21L) -#define MUX_PA21B_ADC0_X15 (1L) -#define PINMUX_PA21B_ADC0_X15 ((PIN_PA21B_ADC0_X15 << 16) | MUX_PA21B_ADC0_X15) -#define PORT_PA21B_ADC0_X15 ((1UL) << 21) - -#define PIN_PA22B_ADC0_X16 (22L) -#define MUX_PA22B_ADC0_X16 (1L) -#define PINMUX_PA22B_ADC0_X16 ((PIN_PA22B_ADC0_X16 << 16) | MUX_PA22B_ADC0_X16) -#define PORT_PA22B_ADC0_X16 ((1UL) << 22) - -#define PIN_PA23B_ADC0_X17 (23L) -#define MUX_PA23B_ADC0_X17 (1L) -#define PINMUX_PA23B_ADC0_X17 ((PIN_PA23B_ADC0_X17 << 16) | MUX_PA23B_ADC0_X17) -#define PORT_PA23B_ADC0_X17 ((1UL) << 23) - -#define PIN_PA27B_ADC0_X18 (27L) -#define MUX_PA27B_ADC0_X18 (1L) -#define PINMUX_PA27B_ADC0_X18 ((PIN_PA27B_ADC0_X18 << 16) | MUX_PA27B_ADC0_X18) -#define PORT_PA27B_ADC0_X18 ((1UL) << 27) - -#define PIN_PA30B_ADC0_X19 (30L) -#define MUX_PA30B_ADC0_X19 (1L) -#define PINMUX_PA30B_ADC0_X19 ((PIN_PA30B_ADC0_X19 << 16) | MUX_PA30B_ADC0_X19) -#define PORT_PA30B_ADC0_X19 ((1UL) << 30) - -#define PIN_PB02B_ADC0_X20 (34L) -#define MUX_PB02B_ADC0_X20 (1L) -#define PINMUX_PB02B_ADC0_X20 ((PIN_PB02B_ADC0_X20 << 16) | MUX_PB02B_ADC0_X20) -#define PORT_PB02B_ADC0_X20 ((1UL) << 2) - -#define PIN_PB03B_ADC0_X21 (35L) -#define MUX_PB03B_ADC0_X21 (1L) -#define PINMUX_PB03B_ADC0_X21 ((PIN_PB03B_ADC0_X21 << 16) | MUX_PB03B_ADC0_X21) -#define PORT_PB03B_ADC0_X21 ((1UL) << 3) - -#define PIN_PB04B_ADC0_X22 (36L) -#define MUX_PB04B_ADC0_X22 (1L) -#define PINMUX_PB04B_ADC0_X22 ((PIN_PB04B_ADC0_X22 << 16) | MUX_PB04B_ADC0_X22) -#define PORT_PB04B_ADC0_X22 ((1UL) << 4) - -#define PIN_PB05B_ADC0_X23 (37L) -#define MUX_PB05B_ADC0_X23 (1L) -#define PINMUX_PB05B_ADC0_X23 ((PIN_PB05B_ADC0_X23 << 16) | MUX_PB05B_ADC0_X23) -#define PORT_PB05B_ADC0_X23 ((1UL) << 5) - -#define PIN_PB06B_ADC0_X24 (38L) -#define MUX_PB06B_ADC0_X24 (1L) -#define PINMUX_PB06B_ADC0_X24 ((PIN_PB06B_ADC0_X24 << 16) | MUX_PB06B_ADC0_X24) -#define PORT_PB06B_ADC0_X24 ((1UL) << 6) - -#define PIN_PB07B_ADC0_X25 (39L) -#define MUX_PB07B_ADC0_X25 (1L) -#define PINMUX_PB07B_ADC0_X25 ((PIN_PB07B_ADC0_X25 << 16) | MUX_PB07B_ADC0_X25) -#define PORT_PB07B_ADC0_X25 ((1UL) << 7) - -#define PIN_PB12B_ADC0_X26 (44L) -#define MUX_PB12B_ADC0_X26 (1L) -#define PINMUX_PB12B_ADC0_X26 ((PIN_PB12B_ADC0_X26 << 16) | MUX_PB12B_ADC0_X26) -#define PORT_PB12B_ADC0_X26 ((1UL) << 12) - -#define PIN_PB13B_ADC0_X27 (45L) -#define MUX_PB13B_ADC0_X27 (1L) -#define PINMUX_PB13B_ADC0_X27 ((PIN_PB13B_ADC0_X27 << 16) | MUX_PB13B_ADC0_X27) -#define PORT_PB13B_ADC0_X27 ((1UL) << 13) - -#define PIN_PB14B_ADC0_X28 (46L) -#define MUX_PB14B_ADC0_X28 (1L) -#define PINMUX_PB14B_ADC0_X28 ((PIN_PB14B_ADC0_X28 << 16) | MUX_PB14B_ADC0_X28) -#define PORT_PB14B_ADC0_X28 ((1UL) << 14) - -#define PIN_PB15B_ADC0_X29 (47L) -#define MUX_PB15B_ADC0_X29 (1L) -#define PINMUX_PB15B_ADC0_X29 ((PIN_PB15B_ADC0_X29 << 16) | MUX_PB15B_ADC0_X29) -#define PORT_PB15B_ADC0_X29 ((1UL) << 15) - -#define PIN_PB00B_ADC0_X30 (32L) -#define MUX_PB00B_ADC0_X30 (1L) -#define PINMUX_PB00B_ADC0_X30 ((PIN_PB00B_ADC0_X30 << 16) | MUX_PB00B_ADC0_X30) -#define PORT_PB00B_ADC0_X30 ((1UL) << 0) - -#define PIN_PB01B_ADC0_X31 (33L) -#define MUX_PB01B_ADC0_X31 (1L) -#define PINMUX_PB01B_ADC0_X31 ((PIN_PB01B_ADC0_X31 << 16) | MUX_PB01B_ADC0_X31) -#define PORT_PB01B_ADC0_X31 ((1UL) << 1) - -#define PIN_PA03B_ADC0_Y0 (3L) -#define MUX_PA03B_ADC0_Y0 (1L) -#define PINMUX_PA03B_ADC0_Y0 ((PIN_PA03B_ADC0_Y0 << 16) | MUX_PA03B_ADC0_Y0) -#define PORT_PA03B_ADC0_Y0 ((1UL) << 3) - -#define PIN_PB08B_ADC0_Y1 (40L) -#define MUX_PB08B_ADC0_Y1 (1L) -#define PINMUX_PB08B_ADC0_Y1 ((PIN_PB08B_ADC0_Y1 << 16) | MUX_PB08B_ADC0_Y1) -#define PORT_PB08B_ADC0_Y1 ((1UL) << 8) - -#define PIN_PB09B_ADC0_Y2 (41L) -#define MUX_PB09B_ADC0_Y2 (1L) -#define PINMUX_PB09B_ADC0_Y2 ((PIN_PB09B_ADC0_Y2 << 16) | MUX_PB09B_ADC0_Y2) -#define PORT_PB09B_ADC0_Y2 ((1UL) << 9) - -#define PIN_PA04B_ADC0_Y3 (4L) -#define MUX_PA04B_ADC0_Y3 (1L) -#define PINMUX_PA04B_ADC0_Y3 ((PIN_PA04B_ADC0_Y3 << 16) | MUX_PA04B_ADC0_Y3) -#define PORT_PA04B_ADC0_Y3 ((1UL) << 4) - -#define PIN_PA06B_ADC0_Y4 (6L) -#define MUX_PA06B_ADC0_Y4 (1L) -#define PINMUX_PA06B_ADC0_Y4 ((PIN_PA06B_ADC0_Y4 << 16) | MUX_PA06B_ADC0_Y4) -#define PORT_PA06B_ADC0_Y4 ((1UL) << 6) - -#define PIN_PA07B_ADC0_Y5 (7L) -#define MUX_PA07B_ADC0_Y5 (1L) -#define PINMUX_PA07B_ADC0_Y5 ((PIN_PA07B_ADC0_Y5 << 16) | MUX_PA07B_ADC0_Y5) -#define PORT_PA07B_ADC0_Y5 ((1UL) << 7) - -#define PIN_PA08B_ADC0_Y6 (8L) -#define MUX_PA08B_ADC0_Y6 (1L) -#define PINMUX_PA08B_ADC0_Y6 ((PIN_PA08B_ADC0_Y6 << 16) | MUX_PA08B_ADC0_Y6) -#define PORT_PA08B_ADC0_Y6 ((1UL) << 8) - -#define PIN_PA09B_ADC0_Y7 (9L) -#define MUX_PA09B_ADC0_Y7 (1L) -#define PINMUX_PA09B_ADC0_Y7 ((PIN_PA09B_ADC0_Y7 << 16) | MUX_PA09B_ADC0_Y7) -#define PORT_PA09B_ADC0_Y7 ((1UL) << 9) - -#define PIN_PA10B_ADC0_Y8 (10L) -#define MUX_PA10B_ADC0_Y8 (1L) -#define PINMUX_PA10B_ADC0_Y8 ((PIN_PA10B_ADC0_Y8 << 16) | MUX_PA10B_ADC0_Y8) -#define PORT_PA10B_ADC0_Y8 ((1UL) << 10) - -#define PIN_PA11B_ADC0_Y9 (11L) -#define MUX_PA11B_ADC0_Y9 (1L) -#define PINMUX_PA11B_ADC0_Y9 ((PIN_PA11B_ADC0_Y9 << 16) | MUX_PA11B_ADC0_Y9) -#define PORT_PA11B_ADC0_Y9 ((1UL) << 11) - -#define PIN_PA16B_ADC0_Y10 (16L) -#define MUX_PA16B_ADC0_Y10 (1L) -#define PINMUX_PA16B_ADC0_Y10 ((PIN_PA16B_ADC0_Y10 << 16) | MUX_PA16B_ADC0_Y10) -#define PORT_PA16B_ADC0_Y10 ((1UL) << 16) - -#define PIN_PA17B_ADC0_Y11 (17L) -#define MUX_PA17B_ADC0_Y11 (1L) -#define PINMUX_PA17B_ADC0_Y11 ((PIN_PA17B_ADC0_Y11 << 16) | MUX_PA17B_ADC0_Y11) -#define PORT_PA17B_ADC0_Y11 ((1UL) << 17) - -#define PIN_PA18B_ADC0_Y12 (18L) -#define MUX_PA18B_ADC0_Y12 (1L) -#define PINMUX_PA18B_ADC0_Y12 ((PIN_PA18B_ADC0_Y12 << 16) | MUX_PA18B_ADC0_Y12) -#define PORT_PA18B_ADC0_Y12 ((1UL) << 18) - -#define PIN_PA19B_ADC0_Y13 (19L) -#define MUX_PA19B_ADC0_Y13 (1L) -#define PINMUX_PA19B_ADC0_Y13 ((PIN_PA19B_ADC0_Y13 << 16) | MUX_PA19B_ADC0_Y13) -#define PORT_PA19B_ADC0_Y13 ((1UL) << 19) - -#define PIN_PA20B_ADC0_Y14 (20L) -#define MUX_PA20B_ADC0_Y14 (1L) -#define PINMUX_PA20B_ADC0_Y14 ((PIN_PA20B_ADC0_Y14 << 16) | MUX_PA20B_ADC0_Y14) -#define PORT_PA20B_ADC0_Y14 ((1UL) << 20) - -#define PIN_PA21B_ADC0_Y15 (21L) -#define MUX_PA21B_ADC0_Y15 (1L) -#define PINMUX_PA21B_ADC0_Y15 ((PIN_PA21B_ADC0_Y15 << 16) | MUX_PA21B_ADC0_Y15) -#define PORT_PA21B_ADC0_Y15 ((1UL) << 21) - -#define PIN_PA22B_ADC0_Y16 (22L) -#define MUX_PA22B_ADC0_Y16 (1L) -#define PINMUX_PA22B_ADC0_Y16 ((PIN_PA22B_ADC0_Y16 << 16) | MUX_PA22B_ADC0_Y16) -#define PORT_PA22B_ADC0_Y16 ((1UL) << 22) - -#define PIN_PA23B_ADC0_Y17 (23L) -#define MUX_PA23B_ADC0_Y17 (1L) -#define PINMUX_PA23B_ADC0_Y17 ((PIN_PA23B_ADC0_Y17 << 16) | MUX_PA23B_ADC0_Y17) -#define PORT_PA23B_ADC0_Y17 ((1UL) << 23) - -#define PIN_PA27B_ADC0_Y18 (27L) -#define MUX_PA27B_ADC0_Y18 (1L) -#define PINMUX_PA27B_ADC0_Y18 ((PIN_PA27B_ADC0_Y18 << 16) | MUX_PA27B_ADC0_Y18) -#define PORT_PA27B_ADC0_Y18 ((1UL) << 27) - -#define PIN_PA30B_ADC0_Y19 (30L) -#define MUX_PA30B_ADC0_Y19 (1L) -#define PINMUX_PA30B_ADC0_Y19 ((PIN_PA30B_ADC0_Y19 << 16) | MUX_PA30B_ADC0_Y19) -#define PORT_PA30B_ADC0_Y19 ((1UL) << 30) - -#define PIN_PB02B_ADC0_Y20 (34L) -#define MUX_PB02B_ADC0_Y20 (1L) -#define PINMUX_PB02B_ADC0_Y20 ((PIN_PB02B_ADC0_Y20 << 16) | MUX_PB02B_ADC0_Y20) -#define PORT_PB02B_ADC0_Y20 ((1UL) << 2) - -#define PIN_PB03B_ADC0_Y21 (35L) -#define MUX_PB03B_ADC0_Y21 (1L) -#define PINMUX_PB03B_ADC0_Y21 ((PIN_PB03B_ADC0_Y21 << 16) | MUX_PB03B_ADC0_Y21) -#define PORT_PB03B_ADC0_Y21 ((1UL) << 3) - -#define PIN_PB04B_ADC0_Y22 (36L) -#define MUX_PB04B_ADC0_Y22 (1L) -#define PINMUX_PB04B_ADC0_Y22 ((PIN_PB04B_ADC0_Y22 << 16) | MUX_PB04B_ADC0_Y22) -#define PORT_PB04B_ADC0_Y22 ((1UL) << 4) - -#define PIN_PB05B_ADC0_Y23 (37L) -#define MUX_PB05B_ADC0_Y23 (1L) -#define PINMUX_PB05B_ADC0_Y23 ((PIN_PB05B_ADC0_Y23 << 16) | MUX_PB05B_ADC0_Y23) -#define PORT_PB05B_ADC0_Y23 ((1UL) << 5) - -#define PIN_PB06B_ADC0_Y24 (38L) -#define MUX_PB06B_ADC0_Y24 (1L) -#define PINMUX_PB06B_ADC0_Y24 ((PIN_PB06B_ADC0_Y24 << 16) | MUX_PB06B_ADC0_Y24) -#define PORT_PB06B_ADC0_Y24 ((1UL) << 6) - -#define PIN_PB07B_ADC0_Y25 (39L) -#define MUX_PB07B_ADC0_Y25 (1L) -#define PINMUX_PB07B_ADC0_Y25 ((PIN_PB07B_ADC0_Y25 << 16) | MUX_PB07B_ADC0_Y25) -#define PORT_PB07B_ADC0_Y25 ((1UL) << 7) - -#define PIN_PB12B_ADC0_Y26 (44L) -#define MUX_PB12B_ADC0_Y26 (1L) -#define PINMUX_PB12B_ADC0_Y26 ((PIN_PB12B_ADC0_Y26 << 16) | MUX_PB12B_ADC0_Y26) -#define PORT_PB12B_ADC0_Y26 ((1UL) << 12) - -#define PIN_PB13B_ADC0_Y27 (45L) -#define MUX_PB13B_ADC0_Y27 (1L) -#define PINMUX_PB13B_ADC0_Y27 ((PIN_PB13B_ADC0_Y27 << 16) | MUX_PB13B_ADC0_Y27) -#define PORT_PB13B_ADC0_Y27 ((1UL) << 13) - -#define PIN_PB14B_ADC0_Y28 (46L) -#define MUX_PB14B_ADC0_Y28 (1L) -#define PINMUX_PB14B_ADC0_Y28 ((PIN_PB14B_ADC0_Y28 << 16) | MUX_PB14B_ADC0_Y28) -#define PORT_PB14B_ADC0_Y28 ((1UL) << 14) - -#define PIN_PB15B_ADC0_Y29 (47L) -#define MUX_PB15B_ADC0_Y29 (1L) -#define PINMUX_PB15B_ADC0_Y29 ((PIN_PB15B_ADC0_Y29 << 16) | MUX_PB15B_ADC0_Y29) -#define PORT_PB15B_ADC0_Y29 ((1UL) << 15) - -#define PIN_PB00B_ADC0_Y30 (32L) -#define MUX_PB00B_ADC0_Y30 (1L) -#define PINMUX_PB00B_ADC0_Y30 ((PIN_PB00B_ADC0_Y30 << 16) | MUX_PB00B_ADC0_Y30) -#define PORT_PB00B_ADC0_Y30 ((1UL) << 0) - -#define PIN_PB01B_ADC0_Y31 (33L) -#define MUX_PB01B_ADC0_Y31 (1L) -#define PINMUX_PB01B_ADC0_Y31 ((PIN_PB01B_ADC0_Y31 << 16) | MUX_PB01B_ADC0_Y31) -#define PORT_PB01B_ADC0_Y31 ((1UL) << 1) - -/* ========== PORT definition for ADC1 peripheral ========== */ -#define PIN_PB08B_ADC1_AIN0 (40L) -#define MUX_PB08B_ADC1_AIN0 (1L) -#define PINMUX_PB08B_ADC1_AIN0 ((PIN_PB08B_ADC1_AIN0 << 16) | MUX_PB08B_ADC1_AIN0) -#define PORT_PB08B_ADC1_AIN0 ((1UL) << 8) - -#define PIN_PB09B_ADC1_AIN1 (41L) -#define MUX_PB09B_ADC1_AIN1 (1L) -#define PINMUX_PB09B_ADC1_AIN1 ((PIN_PB09B_ADC1_AIN1 << 16) | MUX_PB09B_ADC1_AIN1) -#define PORT_PB09B_ADC1_AIN1 ((1UL) << 9) - -#define PIN_PA08B_ADC1_AIN2 (8L) -#define MUX_PA08B_ADC1_AIN2 (1L) -#define PINMUX_PA08B_ADC1_AIN2 ((PIN_PA08B_ADC1_AIN2 << 16) | MUX_PA08B_ADC1_AIN2) -#define PORT_PA08B_ADC1_AIN2 ((1UL) << 8) - -#define PIN_PA09B_ADC1_AIN3 (9L) -#define MUX_PA09B_ADC1_AIN3 (1L) -#define PINMUX_PA09B_ADC1_AIN3 ((PIN_PA09B_ADC1_AIN3 << 16) | MUX_PA09B_ADC1_AIN3) -#define PORT_PA09B_ADC1_AIN3 ((1UL) << 9) - -#define PIN_PC02B_ADC1_AIN4 (66L) -#define MUX_PC02B_ADC1_AIN4 (1L) -#define PINMUX_PC02B_ADC1_AIN4 ((PIN_PC02B_ADC1_AIN4 << 16) | MUX_PC02B_ADC1_AIN4) -#define PORT_PC02B_ADC1_AIN4 ((1UL) << 2) - -#define PIN_PC03B_ADC1_AIN5 (67L) -#define MUX_PC03B_ADC1_AIN5 (1L) -#define PINMUX_PC03B_ADC1_AIN5 ((PIN_PC03B_ADC1_AIN5 << 16) | MUX_PC03B_ADC1_AIN5) -#define PORT_PC03B_ADC1_AIN5 ((1UL) << 3) - -#define PIN_PB04B_ADC1_AIN6 (36L) -#define MUX_PB04B_ADC1_AIN6 (1L) -#define PINMUX_PB04B_ADC1_AIN6 ((PIN_PB04B_ADC1_AIN6 << 16) | MUX_PB04B_ADC1_AIN6) -#define PORT_PB04B_ADC1_AIN6 ((1UL) << 4) - -#define PIN_PB05B_ADC1_AIN7 (37L) -#define MUX_PB05B_ADC1_AIN7 (1L) -#define PINMUX_PB05B_ADC1_AIN7 ((PIN_PB05B_ADC1_AIN7 << 16) | MUX_PB05B_ADC1_AIN7) -#define PORT_PB05B_ADC1_AIN7 ((1UL) << 5) - -#define PIN_PB06B_ADC1_AIN8 (38L) -#define MUX_PB06B_ADC1_AIN8 (1L) -#define PINMUX_PB06B_ADC1_AIN8 ((PIN_PB06B_ADC1_AIN8 << 16) | MUX_PB06B_ADC1_AIN8) -#define PORT_PB06B_ADC1_AIN8 ((1UL) << 6) - -#define PIN_PB07B_ADC1_AIN9 (39L) -#define MUX_PB07B_ADC1_AIN9 (1L) -#define PINMUX_PB07B_ADC1_AIN9 ((PIN_PB07B_ADC1_AIN9 << 16) | MUX_PB07B_ADC1_AIN9) -#define PORT_PB07B_ADC1_AIN9 ((1UL) << 7) - -#define PIN_PC00B_ADC1_AIN10 (64L) -#define MUX_PC00B_ADC1_AIN10 (1L) -#define PINMUX_PC00B_ADC1_AIN10 ((PIN_PC00B_ADC1_AIN10 << 16) | MUX_PC00B_ADC1_AIN10) -#define PORT_PC00B_ADC1_AIN10 ((1UL) << 0) - -#define PIN_PC01B_ADC1_AIN11 (65L) -#define MUX_PC01B_ADC1_AIN11 (1L) -#define PINMUX_PC01B_ADC1_AIN11 ((PIN_PC01B_ADC1_AIN11 << 16) | MUX_PC01B_ADC1_AIN11) -#define PORT_PC01B_ADC1_AIN11 ((1UL) << 1) - -/* ========== PORT definition for CAN0 peripheral ========== */ -#define PIN_PA23I_CAN0_RX (23L) -#define MUX_PA23I_CAN0_RX (8L) -#define PINMUX_PA23I_CAN0_RX ((PIN_PA23I_CAN0_RX << 16) | MUX_PA23I_CAN0_RX) -#define PORT_PA23I_CAN0_RX ((1UL) << 23) - -#define PIN_PA25I_CAN0_RX (25L) -#define MUX_PA25I_CAN0_RX (8L) -#define PINMUX_PA25I_CAN0_RX ((PIN_PA25I_CAN0_RX << 16) | MUX_PA25I_CAN0_RX) -#define PORT_PA25I_CAN0_RX ((1UL) << 25) - -#define PIN_PA22I_CAN0_TX (22L) -#define MUX_PA22I_CAN0_TX (8L) -#define PINMUX_PA22I_CAN0_TX ((PIN_PA22I_CAN0_TX << 16) | MUX_PA22I_CAN0_TX) -#define PORT_PA22I_CAN0_TX ((1UL) << 22) - -#define PIN_PA24I_CAN0_TX (24L) -#define MUX_PA24I_CAN0_TX (8L) -#define PINMUX_PA24I_CAN0_TX ((PIN_PA24I_CAN0_TX << 16) | MUX_PA24I_CAN0_TX) -#define PORT_PA24I_CAN0_TX ((1UL) << 24) - -/* ========== PORT definition for CAN1 peripheral ========== */ -#define PIN_PB13H_CAN1_RX (45L) -#define MUX_PB13H_CAN1_RX (7L) -#define PINMUX_PB13H_CAN1_RX ((PIN_PB13H_CAN1_RX << 16) | MUX_PB13H_CAN1_RX) -#define PORT_PB13H_CAN1_RX ((1UL) << 13) - -#define PIN_PB15H_CAN1_RX (47L) -#define MUX_PB15H_CAN1_RX (7L) -#define PINMUX_PB15H_CAN1_RX ((PIN_PB15H_CAN1_RX << 16) | MUX_PB15H_CAN1_RX) -#define PORT_PB15H_CAN1_RX ((1UL) << 15) - -#define PIN_PB12H_CAN1_TX (44L) -#define MUX_PB12H_CAN1_TX (7L) -#define PINMUX_PB12H_CAN1_TX ((PIN_PB12H_CAN1_TX << 16) | MUX_PB12H_CAN1_TX) -#define PORT_PB12H_CAN1_TX ((1UL) << 12) - -#define PIN_PB14H_CAN1_TX (46L) -#define MUX_PB14H_CAN1_TX (7L) -#define PINMUX_PB14H_CAN1_TX ((PIN_PB14H_CAN1_TX << 16) | MUX_PB14H_CAN1_TX) -#define PORT_PB14H_CAN1_TX ((1UL) << 14) - -/* ========== PORT definition for CCL peripheral ========== */ -#define PIN_PA04N_CCL_IN0 (4L) -#define MUX_PA04N_CCL_IN0 (13L) -#define PINMUX_PA04N_CCL_IN0 ((PIN_PA04N_CCL_IN0 << 16) | MUX_PA04N_CCL_IN0) -#define PORT_PA04N_CCL_IN0 ((1UL) << 4) - -#define PIN_PA16N_CCL_IN0 (16L) -#define MUX_PA16N_CCL_IN0 (13L) -#define PINMUX_PA16N_CCL_IN0 ((PIN_PA16N_CCL_IN0 << 16) | MUX_PA16N_CCL_IN0) -#define PORT_PA16N_CCL_IN0 ((1UL) << 16) - -#define PIN_PB22N_CCL_IN0 (54L) -#define MUX_PB22N_CCL_IN0 (13L) -#define PINMUX_PB22N_CCL_IN0 ((PIN_PB22N_CCL_IN0 << 16) | MUX_PB22N_CCL_IN0) -#define PORT_PB22N_CCL_IN0 ((1UL) << 22) - -#define PIN_PA05N_CCL_IN1 (5L) -#define MUX_PA05N_CCL_IN1 (13L) -#define PINMUX_PA05N_CCL_IN1 ((PIN_PA05N_CCL_IN1 << 16) | MUX_PA05N_CCL_IN1) -#define PORT_PA05N_CCL_IN1 ((1UL) << 5) - -#define PIN_PA17N_CCL_IN1 (17L) -#define MUX_PA17N_CCL_IN1 (13L) -#define PINMUX_PA17N_CCL_IN1 ((PIN_PA17N_CCL_IN1 << 16) | MUX_PA17N_CCL_IN1) -#define PORT_PA17N_CCL_IN1 ((1UL) << 17) - -#define PIN_PB00N_CCL_IN1 (32L) -#define MUX_PB00N_CCL_IN1 (13L) -#define PINMUX_PB00N_CCL_IN1 ((PIN_PB00N_CCL_IN1 << 16) | MUX_PB00N_CCL_IN1) -#define PORT_PB00N_CCL_IN1 ((1UL) << 0) - -#define PIN_PA06N_CCL_IN2 (6L) -#define MUX_PA06N_CCL_IN2 (13L) -#define PINMUX_PA06N_CCL_IN2 ((PIN_PA06N_CCL_IN2 << 16) | MUX_PA06N_CCL_IN2) -#define PORT_PA06N_CCL_IN2 ((1UL) << 6) - -#define PIN_PA18N_CCL_IN2 (18L) -#define MUX_PA18N_CCL_IN2 (13L) -#define PINMUX_PA18N_CCL_IN2 ((PIN_PA18N_CCL_IN2 << 16) | MUX_PA18N_CCL_IN2) -#define PORT_PA18N_CCL_IN2 ((1UL) << 18) - -#define PIN_PB01N_CCL_IN2 (33L) -#define MUX_PB01N_CCL_IN2 (13L) -#define PINMUX_PB01N_CCL_IN2 ((PIN_PB01N_CCL_IN2 << 16) | MUX_PB01N_CCL_IN2) -#define PORT_PB01N_CCL_IN2 ((1UL) << 1) - -#define PIN_PA08N_CCL_IN3 (8L) -#define MUX_PA08N_CCL_IN3 (13L) -#define PINMUX_PA08N_CCL_IN3 ((PIN_PA08N_CCL_IN3 << 16) | MUX_PA08N_CCL_IN3) -#define PORT_PA08N_CCL_IN3 ((1UL) << 8) - -#define PIN_PA30N_CCL_IN3 (30L) -#define MUX_PA30N_CCL_IN3 (13L) -#define PINMUX_PA30N_CCL_IN3 ((PIN_PA30N_CCL_IN3 << 16) | MUX_PA30N_CCL_IN3) -#define PORT_PA30N_CCL_IN3 ((1UL) << 30) - -#define PIN_PA09N_CCL_IN4 (9L) -#define MUX_PA09N_CCL_IN4 (13L) -#define PINMUX_PA09N_CCL_IN4 ((PIN_PA09N_CCL_IN4 << 16) | MUX_PA09N_CCL_IN4) -#define PORT_PA09N_CCL_IN4 ((1UL) << 9) - -#define PIN_PC27N_CCL_IN4 (91L) -#define MUX_PC27N_CCL_IN4 (13L) -#define PINMUX_PC27N_CCL_IN4 ((PIN_PC27N_CCL_IN4 << 16) | MUX_PC27N_CCL_IN4) -#define PORT_PC27N_CCL_IN4 ((1UL) << 27) - -#define PIN_PA10N_CCL_IN5 (10L) -#define MUX_PA10N_CCL_IN5 (13L) -#define PINMUX_PA10N_CCL_IN5 ((PIN_PA10N_CCL_IN5 << 16) | MUX_PA10N_CCL_IN5) -#define PORT_PA10N_CCL_IN5 ((1UL) << 10) - -#define PIN_PC28N_CCL_IN5 (92L) -#define MUX_PC28N_CCL_IN5 (13L) -#define PINMUX_PC28N_CCL_IN5 ((PIN_PC28N_CCL_IN5 << 16) | MUX_PC28N_CCL_IN5) -#define PORT_PC28N_CCL_IN5 ((1UL) << 28) - -#define PIN_PA22N_CCL_IN6 (22L) -#define MUX_PA22N_CCL_IN6 (13L) -#define PINMUX_PA22N_CCL_IN6 ((PIN_PA22N_CCL_IN6 << 16) | MUX_PA22N_CCL_IN6) -#define PORT_PA22N_CCL_IN6 ((1UL) << 22) - -#define PIN_PB06N_CCL_IN6 (38L) -#define MUX_PB06N_CCL_IN6 (13L) -#define PINMUX_PB06N_CCL_IN6 ((PIN_PB06N_CCL_IN6 << 16) | MUX_PB06N_CCL_IN6) -#define PORT_PB06N_CCL_IN6 ((1UL) << 6) - -#define PIN_PA23N_CCL_IN7 (23L) -#define MUX_PA23N_CCL_IN7 (13L) -#define PINMUX_PA23N_CCL_IN7 ((PIN_PA23N_CCL_IN7 << 16) | MUX_PA23N_CCL_IN7) -#define PORT_PA23N_CCL_IN7 ((1UL) << 23) - -#define PIN_PB07N_CCL_IN7 (39L) -#define MUX_PB07N_CCL_IN7 (13L) -#define PINMUX_PB07N_CCL_IN7 ((PIN_PB07N_CCL_IN7 << 16) | MUX_PB07N_CCL_IN7) -#define PORT_PB07N_CCL_IN7 ((1UL) << 7) - -#define PIN_PA24N_CCL_IN8 (24L) -#define MUX_PA24N_CCL_IN8 (13L) -#define PINMUX_PA24N_CCL_IN8 ((PIN_PA24N_CCL_IN8 << 16) | MUX_PA24N_CCL_IN8) -#define PORT_PA24N_CCL_IN8 ((1UL) << 24) - -#define PIN_PB08N_CCL_IN8 (40L) -#define MUX_PB08N_CCL_IN8 (13L) -#define PINMUX_PB08N_CCL_IN8 ((PIN_PB08N_CCL_IN8 << 16) | MUX_PB08N_CCL_IN8) -#define PORT_PB08N_CCL_IN8 ((1UL) << 8) - -#define PIN_PB14N_CCL_IN9 (46L) -#define MUX_PB14N_CCL_IN9 (13L) -#define PINMUX_PB14N_CCL_IN9 ((PIN_PB14N_CCL_IN9 << 16) | MUX_PB14N_CCL_IN9) -#define PORT_PB14N_CCL_IN9 ((1UL) << 14) - -#define PIN_PC20N_CCL_IN9 (84L) -#define MUX_PC20N_CCL_IN9 (13L) -#define PINMUX_PC20N_CCL_IN9 ((PIN_PC20N_CCL_IN9 << 16) | MUX_PC20N_CCL_IN9) -#define PORT_PC20N_CCL_IN9 ((1UL) << 20) - -#define PIN_PB15N_CCL_IN10 (47L) -#define MUX_PB15N_CCL_IN10 (13L) -#define PINMUX_PB15N_CCL_IN10 ((PIN_PB15N_CCL_IN10 << 16) | MUX_PB15N_CCL_IN10) -#define PORT_PB15N_CCL_IN10 ((1UL) << 15) - -#define PIN_PC21N_CCL_IN10 (85L) -#define MUX_PC21N_CCL_IN10 (13L) -#define PINMUX_PC21N_CCL_IN10 ((PIN_PC21N_CCL_IN10 << 16) | MUX_PC21N_CCL_IN10) -#define PORT_PC21N_CCL_IN10 ((1UL) << 21) - -#define PIN_PB10N_CCL_IN11 (42L) -#define MUX_PB10N_CCL_IN11 (13L) -#define PINMUX_PB10N_CCL_IN11 ((PIN_PB10N_CCL_IN11 << 16) | MUX_PB10N_CCL_IN11) -#define PORT_PB10N_CCL_IN11 ((1UL) << 10) - -#define PIN_PB16N_CCL_IN11 (48L) -#define MUX_PB16N_CCL_IN11 (13L) -#define PINMUX_PB16N_CCL_IN11 ((PIN_PB16N_CCL_IN11 << 16) | MUX_PB16N_CCL_IN11) -#define PORT_PB16N_CCL_IN11 ((1UL) << 16) - -#define PIN_PA07N_CCL_OUT0 (7L) -#define MUX_PA07N_CCL_OUT0 (13L) -#define PINMUX_PA07N_CCL_OUT0 ((PIN_PA07N_CCL_OUT0 << 16) | MUX_PA07N_CCL_OUT0) -#define PORT_PA07N_CCL_OUT0 ((1UL) << 7) - -#define PIN_PA19N_CCL_OUT0 (19L) -#define MUX_PA19N_CCL_OUT0 (13L) -#define PINMUX_PA19N_CCL_OUT0 ((PIN_PA19N_CCL_OUT0 << 16) | MUX_PA19N_CCL_OUT0) -#define PORT_PA19N_CCL_OUT0 ((1UL) << 19) - -#define PIN_PB02N_CCL_OUT0 (34L) -#define MUX_PB02N_CCL_OUT0 (13L) -#define PINMUX_PB02N_CCL_OUT0 ((PIN_PB02N_CCL_OUT0 << 16) | MUX_PB02N_CCL_OUT0) -#define PORT_PB02N_CCL_OUT0 ((1UL) << 2) - -#define PIN_PB23N_CCL_OUT0 (55L) -#define MUX_PB23N_CCL_OUT0 (13L) -#define PINMUX_PB23N_CCL_OUT0 ((PIN_PB23N_CCL_OUT0 << 16) | MUX_PB23N_CCL_OUT0) -#define PORT_PB23N_CCL_OUT0 ((1UL) << 23) - -#define PIN_PA11N_CCL_OUT1 (11L) -#define MUX_PA11N_CCL_OUT1 (13L) -#define PINMUX_PA11N_CCL_OUT1 ((PIN_PA11N_CCL_OUT1 << 16) | MUX_PA11N_CCL_OUT1) -#define PORT_PA11N_CCL_OUT1 ((1UL) << 11) - -#define PIN_PA31N_CCL_OUT1 (31L) -#define MUX_PA31N_CCL_OUT1 (13L) -#define PINMUX_PA31N_CCL_OUT1 ((PIN_PA31N_CCL_OUT1 << 16) | MUX_PA31N_CCL_OUT1) -#define PORT_PA31N_CCL_OUT1 ((1UL) << 31) - -#define PIN_PB11N_CCL_OUT1 (43L) -#define MUX_PB11N_CCL_OUT1 (13L) -#define PINMUX_PB11N_CCL_OUT1 ((PIN_PB11N_CCL_OUT1 << 16) | MUX_PB11N_CCL_OUT1) -#define PORT_PB11N_CCL_OUT1 ((1UL) << 11) - -#define PIN_PA25N_CCL_OUT2 (25L) -#define MUX_PA25N_CCL_OUT2 (13L) -#define PINMUX_PA25N_CCL_OUT2 ((PIN_PA25N_CCL_OUT2 << 16) | MUX_PA25N_CCL_OUT2) -#define PORT_PA25N_CCL_OUT2 ((1UL) << 25) - -#define PIN_PB09N_CCL_OUT2 (41L) -#define MUX_PB09N_CCL_OUT2 (13L) -#define PINMUX_PB09N_CCL_OUT2 ((PIN_PB09N_CCL_OUT2 << 16) | MUX_PB09N_CCL_OUT2) -#define PORT_PB09N_CCL_OUT2 ((1UL) << 9) - -#define PIN_PB17N_CCL_OUT3 (49L) -#define MUX_PB17N_CCL_OUT3 (13L) -#define PINMUX_PB17N_CCL_OUT3 ((PIN_PB17N_CCL_OUT3 << 16) | MUX_PB17N_CCL_OUT3) -#define PORT_PB17N_CCL_OUT3 ((1UL) << 17) - -/* ========== PORT definition for DAC peripheral ========== */ -#define PIN_PA02B_DAC_VOUT0 (2L) -#define MUX_PA02B_DAC_VOUT0 (1L) -#define PINMUX_PA02B_DAC_VOUT0 ((PIN_PA02B_DAC_VOUT0 << 16) | MUX_PA02B_DAC_VOUT0) -#define PORT_PA02B_DAC_VOUT0 ((1UL) << 2) - -#define PIN_PA05B_DAC_VOUT1 (5L) -#define MUX_PA05B_DAC_VOUT1 (1L) -#define PINMUX_PA05B_DAC_VOUT1 ((PIN_PA05B_DAC_VOUT1 << 16) | MUX_PA05B_DAC_VOUT1) -#define PORT_PA05B_DAC_VOUT1 ((1UL) << 5) - -/* ========== PORT definition for EIC peripheral ========== */ -#define PIN_PA00A_EIC_EXTINT0 (0L) -#define MUX_PA00A_EIC_EXTINT0 (0L) -#define PINMUX_PA00A_EIC_EXTINT0 ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0) -#define PORT_PA00A_EIC_EXTINT0 ((1UL) << 0) -#define PIN_PA00A_EIC_EXTINT_NUM _L_(0) /**< EIC signal: PIN_PA00 External Interrupt Line */ - -#define PIN_PA16A_EIC_EXTINT0 (16L) -#define MUX_PA16A_EIC_EXTINT0 (0L) -#define PINMUX_PA16A_EIC_EXTINT0 ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0) -#define PORT_PA16A_EIC_EXTINT0 ((1UL) << 16) -#define PIN_PA16A_EIC_EXTINT_NUM _L_(0) /**< EIC signal: PIN_PA16 External Interrupt Line */ - -#define PIN_PB00A_EIC_EXTINT0 (32L) -#define MUX_PB00A_EIC_EXTINT0 (0L) -#define PINMUX_PB00A_EIC_EXTINT0 ((PIN_PB00A_EIC_EXTINT0 << 16) | MUX_PB00A_EIC_EXTINT0) -#define PORT_PB00A_EIC_EXTINT0 ((1UL) << 0) -#define PIN_PB00A_EIC_EXTINT_NUM _L_(0) /**< EIC signal: PIN_PB00 External Interrupt Line */ - -#define PIN_PB16A_EIC_EXTINT0 (48L) -#define MUX_PB16A_EIC_EXTINT0 (0L) -#define PINMUX_PB16A_EIC_EXTINT0 ((PIN_PB16A_EIC_EXTINT0 << 16) | MUX_PB16A_EIC_EXTINT0) -#define PORT_PB16A_EIC_EXTINT0 ((1UL) << 16) -#define PIN_PB16A_EIC_EXTINT_NUM _L_(0) /**< EIC signal: PIN_PB16 External Interrupt Line */ - -#define PIN_PC00A_EIC_EXTINT0 (64L) -#define MUX_PC00A_EIC_EXTINT0 (0L) -#define PINMUX_PC00A_EIC_EXTINT0 ((PIN_PC00A_EIC_EXTINT0 << 16) | MUX_PC00A_EIC_EXTINT0) -#define PORT_PC00A_EIC_EXTINT0 ((1UL) << 0) -#define PIN_PC00A_EIC_EXTINT_NUM _L_(0) /**< EIC signal: PIN_PC00 External Interrupt Line */ - -#define PIN_PC16A_EIC_EXTINT0 (80L) -#define MUX_PC16A_EIC_EXTINT0 (0L) -#define PINMUX_PC16A_EIC_EXTINT0 ((PIN_PC16A_EIC_EXTINT0 << 16) | MUX_PC16A_EIC_EXTINT0) -#define PORT_PC16A_EIC_EXTINT0 ((1UL) << 16) -#define PIN_PC16A_EIC_EXTINT_NUM _L_(0) /**< EIC signal: PIN_PC16 External Interrupt Line */ - -#define PIN_PA01A_EIC_EXTINT1 (1L) -#define MUX_PA01A_EIC_EXTINT1 (0L) -#define PINMUX_PA01A_EIC_EXTINT1 ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1) -#define PORT_PA01A_EIC_EXTINT1 ((1UL) << 1) -#define PIN_PA01A_EIC_EXTINT_NUM _L_(1) /**< EIC signal: PIN_PA01 External Interrupt Line */ - -#define PIN_PA17A_EIC_EXTINT1 (17L) -#define MUX_PA17A_EIC_EXTINT1 (0L) -#define PINMUX_PA17A_EIC_EXTINT1 ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1) -#define PORT_PA17A_EIC_EXTINT1 ((1UL) << 17) -#define PIN_PA17A_EIC_EXTINT_NUM _L_(1) /**< EIC signal: PIN_PA17 External Interrupt Line */ - -#define PIN_PB01A_EIC_EXTINT1 (33L) -#define MUX_PB01A_EIC_EXTINT1 (0L) -#define PINMUX_PB01A_EIC_EXTINT1 ((PIN_PB01A_EIC_EXTINT1 << 16) | MUX_PB01A_EIC_EXTINT1) -#define PORT_PB01A_EIC_EXTINT1 ((1UL) << 1) -#define PIN_PB01A_EIC_EXTINT_NUM _L_(1) /**< EIC signal: PIN_PB01 External Interrupt Line */ - -#define PIN_PB17A_EIC_EXTINT1 (49L) -#define MUX_PB17A_EIC_EXTINT1 (0L) -#define PINMUX_PB17A_EIC_EXTINT1 ((PIN_PB17A_EIC_EXTINT1 << 16) | MUX_PB17A_EIC_EXTINT1) -#define PORT_PB17A_EIC_EXTINT1 ((1UL) << 17) -#define PIN_PB17A_EIC_EXTINT_NUM _L_(1) /**< EIC signal: PIN_PB17 External Interrupt Line */ - -#define PIN_PC01A_EIC_EXTINT1 (65L) -#define MUX_PC01A_EIC_EXTINT1 (0L) -#define PINMUX_PC01A_EIC_EXTINT1 ((PIN_PC01A_EIC_EXTINT1 << 16) | MUX_PC01A_EIC_EXTINT1) -#define PORT_PC01A_EIC_EXTINT1 ((1UL) << 1) -#define PIN_PC01A_EIC_EXTINT_NUM _L_(1) /**< EIC signal: PIN_PC01 External Interrupt Line */ - -#define PIN_PC17A_EIC_EXTINT1 (81L) -#define MUX_PC17A_EIC_EXTINT1 (0L) -#define PINMUX_PC17A_EIC_EXTINT1 ((PIN_PC17A_EIC_EXTINT1 << 16) | MUX_PC17A_EIC_EXTINT1) -#define PORT_PC17A_EIC_EXTINT1 ((1UL) << 17) -#define PIN_PC17A_EIC_EXTINT_NUM _L_(1) /**< EIC signal: PIN_PC17 External Interrupt Line */ - -#define PIN_PA02A_EIC_EXTINT2 (2L) -#define MUX_PA02A_EIC_EXTINT2 (0L) -#define PINMUX_PA02A_EIC_EXTINT2 ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2) -#define PORT_PA02A_EIC_EXTINT2 ((1UL) << 2) -#define PIN_PA02A_EIC_EXTINT_NUM _L_(2) /**< EIC signal: PIN_PA02 External Interrupt Line */ - -#define PIN_PA18A_EIC_EXTINT2 (18L) -#define MUX_PA18A_EIC_EXTINT2 (0L) -#define PINMUX_PA18A_EIC_EXTINT2 ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2) -#define PORT_PA18A_EIC_EXTINT2 ((1UL) << 18) -#define PIN_PA18A_EIC_EXTINT_NUM _L_(2) /**< EIC signal: PIN_PA18 External Interrupt Line */ - -#define PIN_PB02A_EIC_EXTINT2 (34L) -#define MUX_PB02A_EIC_EXTINT2 (0L) -#define PINMUX_PB02A_EIC_EXTINT2 ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2) -#define PORT_PB02A_EIC_EXTINT2 ((1UL) << 2) -#define PIN_PB02A_EIC_EXTINT_NUM _L_(2) /**< EIC signal: PIN_PB02 External Interrupt Line */ - -#define PIN_PB18A_EIC_EXTINT2 (50L) -#define MUX_PB18A_EIC_EXTINT2 (0L) -#define PINMUX_PB18A_EIC_EXTINT2 ((PIN_PB18A_EIC_EXTINT2 << 16) | MUX_PB18A_EIC_EXTINT2) -#define PORT_PB18A_EIC_EXTINT2 ((1UL) << 18) -#define PIN_PB18A_EIC_EXTINT_NUM _L_(2) /**< EIC signal: PIN_PB18 External Interrupt Line */ - -#define PIN_PC02A_EIC_EXTINT2 (66L) -#define MUX_PC02A_EIC_EXTINT2 (0L) -#define PINMUX_PC02A_EIC_EXTINT2 ((PIN_PC02A_EIC_EXTINT2 << 16) | MUX_PC02A_EIC_EXTINT2) -#define PORT_PC02A_EIC_EXTINT2 ((1UL) << 2) -#define PIN_PC02A_EIC_EXTINT_NUM _L_(2) /**< EIC signal: PIN_PC02 External Interrupt Line */ - -#define PIN_PC18A_EIC_EXTINT2 (82L) -#define MUX_PC18A_EIC_EXTINT2 (0L) -#define PINMUX_PC18A_EIC_EXTINT2 ((PIN_PC18A_EIC_EXTINT2 << 16) | MUX_PC18A_EIC_EXTINT2) -#define PORT_PC18A_EIC_EXTINT2 ((1UL) << 18) -#define PIN_PC18A_EIC_EXTINT_NUM _L_(2) /**< EIC signal: PIN_PC18 External Interrupt Line */ - -#define PIN_PA03A_EIC_EXTINT3 (3L) -#define MUX_PA03A_EIC_EXTINT3 (0L) -#define PINMUX_PA03A_EIC_EXTINT3 ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3) -#define PORT_PA03A_EIC_EXTINT3 ((1UL) << 3) -#define PIN_PA03A_EIC_EXTINT_NUM _L_(3) /**< EIC signal: PIN_PA03 External Interrupt Line */ - -#define PIN_PA19A_EIC_EXTINT3 (19L) -#define MUX_PA19A_EIC_EXTINT3 (0L) -#define PINMUX_PA19A_EIC_EXTINT3 ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3) -#define PORT_PA19A_EIC_EXTINT3 ((1UL) << 19) -#define PIN_PA19A_EIC_EXTINT_NUM _L_(3) /**< EIC signal: PIN_PA19 External Interrupt Line */ - -#define PIN_PB03A_EIC_EXTINT3 (35L) -#define MUX_PB03A_EIC_EXTINT3 (0L) -#define PINMUX_PB03A_EIC_EXTINT3 ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3) -#define PORT_PB03A_EIC_EXTINT3 ((1UL) << 3) -#define PIN_PB03A_EIC_EXTINT_NUM _L_(3) /**< EIC signal: PIN_PB03 External Interrupt Line */ - -#define PIN_PB19A_EIC_EXTINT3 (51L) -#define MUX_PB19A_EIC_EXTINT3 (0L) -#define PINMUX_PB19A_EIC_EXTINT3 ((PIN_PB19A_EIC_EXTINT3 << 16) | MUX_PB19A_EIC_EXTINT3) -#define PORT_PB19A_EIC_EXTINT3 ((1UL) << 19) -#define PIN_PB19A_EIC_EXTINT_NUM _L_(3) /**< EIC signal: PIN_PB19 External Interrupt Line */ - -#define PIN_PC03A_EIC_EXTINT3 (67L) -#define MUX_PC03A_EIC_EXTINT3 (0L) -#define PINMUX_PC03A_EIC_EXTINT3 ((PIN_PC03A_EIC_EXTINT3 << 16) | MUX_PC03A_EIC_EXTINT3) -#define PORT_PC03A_EIC_EXTINT3 ((1UL) << 3) -#define PIN_PC03A_EIC_EXTINT_NUM _L_(3) /**< EIC signal: PIN_PC03 External Interrupt Line */ - -#define PIN_PC19A_EIC_EXTINT3 (83L) -#define MUX_PC19A_EIC_EXTINT3 (0L) -#define PINMUX_PC19A_EIC_EXTINT3 ((PIN_PC19A_EIC_EXTINT3 << 16) | MUX_PC19A_EIC_EXTINT3) -#define PORT_PC19A_EIC_EXTINT3 ((1UL) << 19) -#define PIN_PC19A_EIC_EXTINT_NUM _L_(3) /**< EIC signal: PIN_PC19 External Interrupt Line */ - -#define PIN_PA04A_EIC_EXTINT4 (4L) -#define MUX_PA04A_EIC_EXTINT4 (0L) -#define PINMUX_PA04A_EIC_EXTINT4 ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4) -#define PORT_PA04A_EIC_EXTINT4 ((1UL) << 4) -#define PIN_PA04A_EIC_EXTINT_NUM _L_(4) /**< EIC signal: PIN_PA04 External Interrupt Line */ - -#define PIN_PA20A_EIC_EXTINT4 (20L) -#define MUX_PA20A_EIC_EXTINT4 (0L) -#define PINMUX_PA20A_EIC_EXTINT4 ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4) -#define PORT_PA20A_EIC_EXTINT4 ((1UL) << 20) -#define PIN_PA20A_EIC_EXTINT_NUM _L_(4) /**< EIC signal: PIN_PA20 External Interrupt Line */ - -#define PIN_PB04A_EIC_EXTINT4 (36L) -#define MUX_PB04A_EIC_EXTINT4 (0L) -#define PINMUX_PB04A_EIC_EXTINT4 ((PIN_PB04A_EIC_EXTINT4 << 16) | MUX_PB04A_EIC_EXTINT4) -#define PORT_PB04A_EIC_EXTINT4 ((1UL) << 4) -#define PIN_PB04A_EIC_EXTINT_NUM _L_(4) /**< EIC signal: PIN_PB04 External Interrupt Line */ - -#define PIN_PB20A_EIC_EXTINT4 (52L) -#define MUX_PB20A_EIC_EXTINT4 (0L) -#define PINMUX_PB20A_EIC_EXTINT4 ((PIN_PB20A_EIC_EXTINT4 << 16) | MUX_PB20A_EIC_EXTINT4) -#define PORT_PB20A_EIC_EXTINT4 ((1UL) << 20) -#define PIN_PB20A_EIC_EXTINT_NUM _L_(4) /**< EIC signal: PIN_PB20 External Interrupt Line */ - -#define PIN_PC20A_EIC_EXTINT4 (84L) -#define MUX_PC20A_EIC_EXTINT4 (0L) -#define PINMUX_PC20A_EIC_EXTINT4 ((PIN_PC20A_EIC_EXTINT4 << 16) | MUX_PC20A_EIC_EXTINT4) -#define PORT_PC20A_EIC_EXTINT4 ((1UL) << 20) -#define PIN_PC20A_EIC_EXTINT_NUM _L_(4) /**< EIC signal: PIN_PC20 External Interrupt Line */ - -#define PIN_PA05A_EIC_EXTINT5 (5L) -#define MUX_PA05A_EIC_EXTINT5 (0L) -#define PINMUX_PA05A_EIC_EXTINT5 ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5) -#define PORT_PA05A_EIC_EXTINT5 ((1UL) << 5) -#define PIN_PA05A_EIC_EXTINT_NUM _L_(5) /**< EIC signal: PIN_PA05 External Interrupt Line */ - -#define PIN_PA21A_EIC_EXTINT5 (21L) -#define MUX_PA21A_EIC_EXTINT5 (0L) -#define PINMUX_PA21A_EIC_EXTINT5 ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5) -#define PORT_PA21A_EIC_EXTINT5 ((1UL) << 21) -#define PIN_PA21A_EIC_EXTINT_NUM _L_(5) /**< EIC signal: PIN_PA21 External Interrupt Line */ - -#define PIN_PB05A_EIC_EXTINT5 (37L) -#define MUX_PB05A_EIC_EXTINT5 (0L) -#define PINMUX_PB05A_EIC_EXTINT5 ((PIN_PB05A_EIC_EXTINT5 << 16) | MUX_PB05A_EIC_EXTINT5) -#define PORT_PB05A_EIC_EXTINT5 ((1UL) << 5) -#define PIN_PB05A_EIC_EXTINT_NUM _L_(5) /**< EIC signal: PIN_PB05 External Interrupt Line */ - -#define PIN_PB21A_EIC_EXTINT5 (53L) -#define MUX_PB21A_EIC_EXTINT5 (0L) -#define PINMUX_PB21A_EIC_EXTINT5 ((PIN_PB21A_EIC_EXTINT5 << 16) | MUX_PB21A_EIC_EXTINT5) -#define PORT_PB21A_EIC_EXTINT5 ((1UL) << 21) -#define PIN_PB21A_EIC_EXTINT_NUM _L_(5) /**< EIC signal: PIN_PB21 External Interrupt Line */ - -#define PIN_PC05A_EIC_EXTINT5 (69L) -#define MUX_PC05A_EIC_EXTINT5 (0L) -#define PINMUX_PC05A_EIC_EXTINT5 ((PIN_PC05A_EIC_EXTINT5 << 16) | MUX_PC05A_EIC_EXTINT5) -#define PORT_PC05A_EIC_EXTINT5 ((1UL) << 5) -#define PIN_PC05A_EIC_EXTINT_NUM _L_(5) /**< EIC signal: PIN_PC05 External Interrupt Line */ - -#define PIN_PC21A_EIC_EXTINT5 (85L) -#define MUX_PC21A_EIC_EXTINT5 (0L) -#define PINMUX_PC21A_EIC_EXTINT5 ((PIN_PC21A_EIC_EXTINT5 << 16) | MUX_PC21A_EIC_EXTINT5) -#define PORT_PC21A_EIC_EXTINT5 ((1UL) << 21) -#define PIN_PC21A_EIC_EXTINT_NUM _L_(5) /**< EIC signal: PIN_PC21 External Interrupt Line */ - -#define PIN_PA06A_EIC_EXTINT6 (6L) -#define MUX_PA06A_EIC_EXTINT6 (0L) -#define PINMUX_PA06A_EIC_EXTINT6 ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6) -#define PORT_PA06A_EIC_EXTINT6 ((1UL) << 6) -#define PIN_PA06A_EIC_EXTINT_NUM _L_(6) /**< EIC signal: PIN_PA06 External Interrupt Line */ - -#define PIN_PA22A_EIC_EXTINT6 (22L) -#define MUX_PA22A_EIC_EXTINT6 (0L) -#define PINMUX_PA22A_EIC_EXTINT6 ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6) -#define PORT_PA22A_EIC_EXTINT6 ((1UL) << 22) -#define PIN_PA22A_EIC_EXTINT_NUM _L_(6) /**< EIC signal: PIN_PA22 External Interrupt Line */ - -#define PIN_PB06A_EIC_EXTINT6 (38L) -#define MUX_PB06A_EIC_EXTINT6 (0L) -#define PINMUX_PB06A_EIC_EXTINT6 ((PIN_PB06A_EIC_EXTINT6 << 16) | MUX_PB06A_EIC_EXTINT6) -#define PORT_PB06A_EIC_EXTINT6 ((1UL) << 6) -#define PIN_PB06A_EIC_EXTINT_NUM _L_(6) /**< EIC signal: PIN_PB06 External Interrupt Line */ - -#define PIN_PB22A_EIC_EXTINT6 (54L) -#define MUX_PB22A_EIC_EXTINT6 (0L) -#define PINMUX_PB22A_EIC_EXTINT6 ((PIN_PB22A_EIC_EXTINT6 << 16) | MUX_PB22A_EIC_EXTINT6) -#define PORT_PB22A_EIC_EXTINT6 ((1UL) << 22) -#define PIN_PB22A_EIC_EXTINT_NUM _L_(6) /**< EIC signal: PIN_PB22 External Interrupt Line */ - -#define PIN_PC06A_EIC_EXTINT6 (70L) -#define MUX_PC06A_EIC_EXTINT6 (0L) -#define PINMUX_PC06A_EIC_EXTINT6 ((PIN_PC06A_EIC_EXTINT6 << 16) | MUX_PC06A_EIC_EXTINT6) -#define PORT_PC06A_EIC_EXTINT6 ((1UL) << 6) -#define PIN_PC06A_EIC_EXTINT_NUM _L_(6) /**< EIC signal: PIN_PC06 External Interrupt Line */ - -#define PIN_PA07A_EIC_EXTINT7 (7L) -#define MUX_PA07A_EIC_EXTINT7 (0L) -#define PINMUX_PA07A_EIC_EXTINT7 ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7) -#define PORT_PA07A_EIC_EXTINT7 ((1UL) << 7) -#define PIN_PA07A_EIC_EXTINT_NUM _L_(7) /**< EIC signal: PIN_PA07 External Interrupt Line */ - -#define PIN_PA23A_EIC_EXTINT7 (23L) -#define MUX_PA23A_EIC_EXTINT7 (0L) -#define PINMUX_PA23A_EIC_EXTINT7 ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7) -#define PORT_PA23A_EIC_EXTINT7 ((1UL) << 23) -#define PIN_PA23A_EIC_EXTINT_NUM _L_(7) /**< EIC signal: PIN_PA23 External Interrupt Line */ - -#define PIN_PB07A_EIC_EXTINT7 (39L) -#define MUX_PB07A_EIC_EXTINT7 (0L) -#define PINMUX_PB07A_EIC_EXTINT7 ((PIN_PB07A_EIC_EXTINT7 << 16) | MUX_PB07A_EIC_EXTINT7) -#define PORT_PB07A_EIC_EXTINT7 ((1UL) << 7) -#define PIN_PB07A_EIC_EXTINT_NUM _L_(7) /**< EIC signal: PIN_PB07 External Interrupt Line */ - -#define PIN_PB23A_EIC_EXTINT7 (55L) -#define MUX_PB23A_EIC_EXTINT7 (0L) -#define PINMUX_PB23A_EIC_EXTINT7 ((PIN_PB23A_EIC_EXTINT7 << 16) | MUX_PB23A_EIC_EXTINT7) -#define PORT_PB23A_EIC_EXTINT7 ((1UL) << 23) -#define PIN_PB23A_EIC_EXTINT_NUM _L_(7) /**< EIC signal: PIN_PB23 External Interrupt Line */ - -#define PIN_PA24A_EIC_EXTINT8 (24L) -#define MUX_PA24A_EIC_EXTINT8 (0L) -#define PINMUX_PA24A_EIC_EXTINT8 ((PIN_PA24A_EIC_EXTINT8 << 16) | MUX_PA24A_EIC_EXTINT8) -#define PORT_PA24A_EIC_EXTINT8 ((1UL) << 24) -#define PIN_PA24A_EIC_EXTINT_NUM _L_(8) /**< EIC signal: PIN_PA24 External Interrupt Line */ - -#define PIN_PB08A_EIC_EXTINT8 (40L) -#define MUX_PB08A_EIC_EXTINT8 (0L) -#define PINMUX_PB08A_EIC_EXTINT8 ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8) -#define PORT_PB08A_EIC_EXTINT8 ((1UL) << 8) -#define PIN_PB08A_EIC_EXTINT_NUM _L_(8) /**< EIC signal: PIN_PB08 External Interrupt Line */ - -#define PIN_PB24A_EIC_EXTINT8 (56L) -#define MUX_PB24A_EIC_EXTINT8 (0L) -#define PINMUX_PB24A_EIC_EXTINT8 ((PIN_PB24A_EIC_EXTINT8 << 16) | MUX_PB24A_EIC_EXTINT8) -#define PORT_PB24A_EIC_EXTINT8 ((1UL) << 24) -#define PIN_PB24A_EIC_EXTINT_NUM _L_(8) /**< EIC signal: PIN_PB24 External Interrupt Line */ - -#define PIN_PC24A_EIC_EXTINT8 (88L) -#define MUX_PC24A_EIC_EXTINT8 (0L) -#define PINMUX_PC24A_EIC_EXTINT8 ((PIN_PC24A_EIC_EXTINT8 << 16) | MUX_PC24A_EIC_EXTINT8) -#define PORT_PC24A_EIC_EXTINT8 ((1UL) << 24) -#define PIN_PC24A_EIC_EXTINT_NUM _L_(8) /**< EIC signal: PIN_PC24 External Interrupt Line */ - -#define PIN_PA09A_EIC_EXTINT9 (9L) -#define MUX_PA09A_EIC_EXTINT9 (0L) -#define PINMUX_PA09A_EIC_EXTINT9 ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9) -#define PORT_PA09A_EIC_EXTINT9 ((1UL) << 9) -#define PIN_PA09A_EIC_EXTINT_NUM _L_(9) /**< EIC signal: PIN_PA09 External Interrupt Line */ - -#define PIN_PA25A_EIC_EXTINT9 (25L) -#define MUX_PA25A_EIC_EXTINT9 (0L) -#define PINMUX_PA25A_EIC_EXTINT9 ((PIN_PA25A_EIC_EXTINT9 << 16) | MUX_PA25A_EIC_EXTINT9) -#define PORT_PA25A_EIC_EXTINT9 ((1UL) << 25) -#define PIN_PA25A_EIC_EXTINT_NUM _L_(9) /**< EIC signal: PIN_PA25 External Interrupt Line */ - -#define PIN_PB09A_EIC_EXTINT9 (41L) -#define MUX_PB09A_EIC_EXTINT9 (0L) -#define PINMUX_PB09A_EIC_EXTINT9 ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9) -#define PORT_PB09A_EIC_EXTINT9 ((1UL) << 9) -#define PIN_PB09A_EIC_EXTINT_NUM _L_(9) /**< EIC signal: PIN_PB09 External Interrupt Line */ - -#define PIN_PB25A_EIC_EXTINT9 (57L) -#define MUX_PB25A_EIC_EXTINT9 (0L) -#define PINMUX_PB25A_EIC_EXTINT9 ((PIN_PB25A_EIC_EXTINT9 << 16) | MUX_PB25A_EIC_EXTINT9) -#define PORT_PB25A_EIC_EXTINT9 ((1UL) << 25) -#define PIN_PB25A_EIC_EXTINT_NUM _L_(9) /**< EIC signal: PIN_PB25 External Interrupt Line */ - -#define PIN_PC07A_EIC_EXTINT9 (71L) -#define MUX_PC07A_EIC_EXTINT9 (0L) -#define PINMUX_PC07A_EIC_EXTINT9 ((PIN_PC07A_EIC_EXTINT9 << 16) | MUX_PC07A_EIC_EXTINT9) -#define PORT_PC07A_EIC_EXTINT9 ((1UL) << 7) -#define PIN_PC07A_EIC_EXTINT_NUM _L_(9) /**< EIC signal: PIN_PC07 External Interrupt Line */ - -#define PIN_PC25A_EIC_EXTINT9 (89L) -#define MUX_PC25A_EIC_EXTINT9 (0L) -#define PINMUX_PC25A_EIC_EXTINT9 ((PIN_PC25A_EIC_EXTINT9 << 16) | MUX_PC25A_EIC_EXTINT9) -#define PORT_PC25A_EIC_EXTINT9 ((1UL) << 25) -#define PIN_PC25A_EIC_EXTINT_NUM _L_(9) /**< EIC signal: PIN_PC25 External Interrupt Line */ - -#define PIN_PA10A_EIC_EXTINT10 (10L) -#define MUX_PA10A_EIC_EXTINT10 (0L) -#define PINMUX_PA10A_EIC_EXTINT10 ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10) -#define PORT_PA10A_EIC_EXTINT10 ((1UL) << 10) -#define PIN_PA10A_EIC_EXTINT_NUM _L_(10) /**< EIC signal: PIN_PA10 External Interrupt Line */ - -#define PIN_PB10A_EIC_EXTINT10 (42L) -#define MUX_PB10A_EIC_EXTINT10 (0L) -#define PINMUX_PB10A_EIC_EXTINT10 ((PIN_PB10A_EIC_EXTINT10 << 16) | MUX_PB10A_EIC_EXTINT10) -#define PORT_PB10A_EIC_EXTINT10 ((1UL) << 10) -#define PIN_PB10A_EIC_EXTINT_NUM _L_(10) /**< EIC signal: PIN_PB10 External Interrupt Line */ - -#define PIN_PC10A_EIC_EXTINT10 (74L) -#define MUX_PC10A_EIC_EXTINT10 (0L) -#define PINMUX_PC10A_EIC_EXTINT10 ((PIN_PC10A_EIC_EXTINT10 << 16) | MUX_PC10A_EIC_EXTINT10) -#define PORT_PC10A_EIC_EXTINT10 ((1UL) << 10) -#define PIN_PC10A_EIC_EXTINT_NUM _L_(10) /**< EIC signal: PIN_PC10 External Interrupt Line */ - -#define PIN_PC26A_EIC_EXTINT10 (90L) -#define MUX_PC26A_EIC_EXTINT10 (0L) -#define PINMUX_PC26A_EIC_EXTINT10 ((PIN_PC26A_EIC_EXTINT10 << 16) | MUX_PC26A_EIC_EXTINT10) -#define PORT_PC26A_EIC_EXTINT10 ((1UL) << 26) -#define PIN_PC26A_EIC_EXTINT_NUM _L_(10) /**< EIC signal: PIN_PC26 External Interrupt Line */ - -#define PIN_PA11A_EIC_EXTINT11 (11L) -#define MUX_PA11A_EIC_EXTINT11 (0L) -#define PINMUX_PA11A_EIC_EXTINT11 ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11) -#define PORT_PA11A_EIC_EXTINT11 ((1UL) << 11) -#define PIN_PA11A_EIC_EXTINT_NUM _L_(11) /**< EIC signal: PIN_PA11 External Interrupt Line */ - -#define PIN_PA27A_EIC_EXTINT11 (27L) -#define MUX_PA27A_EIC_EXTINT11 (0L) -#define PINMUX_PA27A_EIC_EXTINT11 ((PIN_PA27A_EIC_EXTINT11 << 16) | MUX_PA27A_EIC_EXTINT11) -#define PORT_PA27A_EIC_EXTINT11 ((1UL) << 27) -#define PIN_PA27A_EIC_EXTINT_NUM _L_(11) /**< EIC signal: PIN_PA27 External Interrupt Line */ - -#define PIN_PB11A_EIC_EXTINT11 (43L) -#define MUX_PB11A_EIC_EXTINT11 (0L) -#define PINMUX_PB11A_EIC_EXTINT11 ((PIN_PB11A_EIC_EXTINT11 << 16) | MUX_PB11A_EIC_EXTINT11) -#define PORT_PB11A_EIC_EXTINT11 ((1UL) << 11) -#define PIN_PB11A_EIC_EXTINT_NUM _L_(11) /**< EIC signal: PIN_PB11 External Interrupt Line */ - -#define PIN_PC11A_EIC_EXTINT11 (75L) -#define MUX_PC11A_EIC_EXTINT11 (0L) -#define PINMUX_PC11A_EIC_EXTINT11 ((PIN_PC11A_EIC_EXTINT11 << 16) | MUX_PC11A_EIC_EXTINT11) -#define PORT_PC11A_EIC_EXTINT11 ((1UL) << 11) -#define PIN_PC11A_EIC_EXTINT_NUM _L_(11) /**< EIC signal: PIN_PC11 External Interrupt Line */ - -#define PIN_PC27A_EIC_EXTINT11 (91L) -#define MUX_PC27A_EIC_EXTINT11 (0L) -#define PINMUX_PC27A_EIC_EXTINT11 ((PIN_PC27A_EIC_EXTINT11 << 16) | MUX_PC27A_EIC_EXTINT11) -#define PORT_PC27A_EIC_EXTINT11 ((1UL) << 27) -#define PIN_PC27A_EIC_EXTINT_NUM _L_(11) /**< EIC signal: PIN_PC27 External Interrupt Line */ - -#define PIN_PA12A_EIC_EXTINT12 (12L) -#define MUX_PA12A_EIC_EXTINT12 (0L) -#define PINMUX_PA12A_EIC_EXTINT12 ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12) -#define PORT_PA12A_EIC_EXTINT12 ((1UL) << 12) -#define PIN_PA12A_EIC_EXTINT_NUM _L_(12) /**< EIC signal: PIN_PA12 External Interrupt Line */ - -#define PIN_PB12A_EIC_EXTINT12 (44L) -#define MUX_PB12A_EIC_EXTINT12 (0L) -#define PINMUX_PB12A_EIC_EXTINT12 ((PIN_PB12A_EIC_EXTINT12 << 16) | MUX_PB12A_EIC_EXTINT12) -#define PORT_PB12A_EIC_EXTINT12 ((1UL) << 12) -#define PIN_PB12A_EIC_EXTINT_NUM _L_(12) /**< EIC signal: PIN_PB12 External Interrupt Line */ - -#define PIN_PC12A_EIC_EXTINT12 (76L) -#define MUX_PC12A_EIC_EXTINT12 (0L) -#define PINMUX_PC12A_EIC_EXTINT12 ((PIN_PC12A_EIC_EXTINT12 << 16) | MUX_PC12A_EIC_EXTINT12) -#define PORT_PC12A_EIC_EXTINT12 ((1UL) << 12) -#define PIN_PC12A_EIC_EXTINT_NUM _L_(12) /**< EIC signal: PIN_PC12 External Interrupt Line */ - -#define PIN_PC28A_EIC_EXTINT12 (92L) -#define MUX_PC28A_EIC_EXTINT12 (0L) -#define PINMUX_PC28A_EIC_EXTINT12 ((PIN_PC28A_EIC_EXTINT12 << 16) | MUX_PC28A_EIC_EXTINT12) -#define PORT_PC28A_EIC_EXTINT12 ((1UL) << 28) -#define PIN_PC28A_EIC_EXTINT_NUM _L_(12) /**< EIC signal: PIN_PC28 External Interrupt Line */ - -#define PIN_PA13A_EIC_EXTINT13 (13L) -#define MUX_PA13A_EIC_EXTINT13 (0L) -#define PINMUX_PA13A_EIC_EXTINT13 ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13) -#define PORT_PA13A_EIC_EXTINT13 ((1UL) << 13) -#define PIN_PA13A_EIC_EXTINT_NUM _L_(13) /**< EIC signal: PIN_PA13 External Interrupt Line */ - -#define PIN_PB13A_EIC_EXTINT13 (45L) -#define MUX_PB13A_EIC_EXTINT13 (0L) -#define PINMUX_PB13A_EIC_EXTINT13 ((PIN_PB13A_EIC_EXTINT13 << 16) | MUX_PB13A_EIC_EXTINT13) -#define PORT_PB13A_EIC_EXTINT13 ((1UL) << 13) -#define PIN_PB13A_EIC_EXTINT_NUM _L_(13) /**< EIC signal: PIN_PB13 External Interrupt Line */ - -#define PIN_PC13A_EIC_EXTINT13 (77L) -#define MUX_PC13A_EIC_EXTINT13 (0L) -#define PINMUX_PC13A_EIC_EXTINT13 ((PIN_PC13A_EIC_EXTINT13 << 16) | MUX_PC13A_EIC_EXTINT13) -#define PORT_PC13A_EIC_EXTINT13 ((1UL) << 13) -#define PIN_PC13A_EIC_EXTINT_NUM _L_(13) /**< EIC signal: PIN_PC13 External Interrupt Line */ - -#define PIN_PA30A_EIC_EXTINT14 (30L) -#define MUX_PA30A_EIC_EXTINT14 (0L) -#define PINMUX_PA30A_EIC_EXTINT14 ((PIN_PA30A_EIC_EXTINT14 << 16) | MUX_PA30A_EIC_EXTINT14) -#define PORT_PA30A_EIC_EXTINT14 ((1UL) << 30) -#define PIN_PA30A_EIC_EXTINT_NUM _L_(14) /**< EIC signal: PIN_PA30 External Interrupt Line */ - -#define PIN_PB14A_EIC_EXTINT14 (46L) -#define MUX_PB14A_EIC_EXTINT14 (0L) -#define PINMUX_PB14A_EIC_EXTINT14 ((PIN_PB14A_EIC_EXTINT14 << 16) | MUX_PB14A_EIC_EXTINT14) -#define PORT_PB14A_EIC_EXTINT14 ((1UL) << 14) -#define PIN_PB14A_EIC_EXTINT_NUM _L_(14) /**< EIC signal: PIN_PB14 External Interrupt Line */ - -#define PIN_PB30A_EIC_EXTINT14 (62L) -#define MUX_PB30A_EIC_EXTINT14 (0L) -#define PINMUX_PB30A_EIC_EXTINT14 ((PIN_PB30A_EIC_EXTINT14 << 16) | MUX_PB30A_EIC_EXTINT14) -#define PORT_PB30A_EIC_EXTINT14 ((1UL) << 30) -#define PIN_PB30A_EIC_EXTINT_NUM _L_(14) /**< EIC signal: PIN_PB30 External Interrupt Line */ - -#define PIN_PC14A_EIC_EXTINT14 (78L) -#define MUX_PC14A_EIC_EXTINT14 (0L) -#define PINMUX_PC14A_EIC_EXTINT14 ((PIN_PC14A_EIC_EXTINT14 << 16) | MUX_PC14A_EIC_EXTINT14) -#define PORT_PC14A_EIC_EXTINT14 ((1UL) << 14) -#define PIN_PC14A_EIC_EXTINT_NUM _L_(14) /**< EIC signal: PIN_PC14 External Interrupt Line */ - -#define PIN_PA14A_EIC_EXTINT14 (14L) -#define MUX_PA14A_EIC_EXTINT14 (0L) -#define PINMUX_PA14A_EIC_EXTINT14 ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14) -#define PORT_PA14A_EIC_EXTINT14 ((1UL) << 14) -#define PIN_PA14A_EIC_EXTINT_NUM _L_(14) /**< EIC signal: PIN_PA14 External Interrupt Line */ - -#define PIN_PA15A_EIC_EXTINT15 (15L) -#define MUX_PA15A_EIC_EXTINT15 (0L) -#define PINMUX_PA15A_EIC_EXTINT15 ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15) -#define PORT_PA15A_EIC_EXTINT15 ((1UL) << 15) -#define PIN_PA15A_EIC_EXTINT_NUM _L_(15) /**< EIC signal: PIN_PA15 External Interrupt Line */ - -#define PIN_PA31A_EIC_EXTINT15 (31L) -#define MUX_PA31A_EIC_EXTINT15 (0L) -#define PINMUX_PA31A_EIC_EXTINT15 ((PIN_PA31A_EIC_EXTINT15 << 16) | MUX_PA31A_EIC_EXTINT15) -#define PORT_PA31A_EIC_EXTINT15 ((1UL) << 31) -#define PIN_PA31A_EIC_EXTINT_NUM _L_(15) /**< EIC signal: PIN_PA31 External Interrupt Line */ - -#define PIN_PB15A_EIC_EXTINT15 (47L) -#define MUX_PB15A_EIC_EXTINT15 (0L) -#define PINMUX_PB15A_EIC_EXTINT15 ((PIN_PB15A_EIC_EXTINT15 << 16) | MUX_PB15A_EIC_EXTINT15) -#define PORT_PB15A_EIC_EXTINT15 ((1UL) << 15) -#define PIN_PB15A_EIC_EXTINT_NUM _L_(15) /**< EIC signal: PIN_PB15 External Interrupt Line */ - -#define PIN_PB31A_EIC_EXTINT15 (63L) -#define MUX_PB31A_EIC_EXTINT15 (0L) -#define PINMUX_PB31A_EIC_EXTINT15 ((PIN_PB31A_EIC_EXTINT15 << 16) | MUX_PB31A_EIC_EXTINT15) -#define PORT_PB31A_EIC_EXTINT15 ((1UL) << 31) -#define PIN_PB31A_EIC_EXTINT_NUM _L_(15) /**< EIC signal: PIN_PB31 External Interrupt Line */ - -#define PIN_PC15A_EIC_EXTINT15 (79L) -#define MUX_PC15A_EIC_EXTINT15 (0L) -#define PINMUX_PC15A_EIC_EXTINT15 ((PIN_PC15A_EIC_EXTINT15 << 16) | MUX_PC15A_EIC_EXTINT15) -#define PORT_PC15A_EIC_EXTINT15 ((1UL) << 15) -#define PIN_PC15A_EIC_EXTINT_NUM _L_(15) /**< EIC signal: PIN_PC15 External Interrupt Line */ - -#define PIN_PA08A_EIC_NMI (8L) -#define MUX_PA08A_EIC_NMI (0L) -#define PINMUX_PA08A_EIC_NMI ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI) -#define PORT_PA08A_EIC_NMI ((1UL) << 8) - -/* ========== PORT definition for GCLK peripheral ========== */ -#define PIN_PA30M_GCLK_IO0 (30L) -#define MUX_PA30M_GCLK_IO0 (12L) -#define PINMUX_PA30M_GCLK_IO0 ((PIN_PA30M_GCLK_IO0 << 16) | MUX_PA30M_GCLK_IO0) -#define PORT_PA30M_GCLK_IO0 ((1UL) << 30) - -#define PIN_PB14M_GCLK_IO0 (46L) -#define MUX_PB14M_GCLK_IO0 (12L) -#define PINMUX_PB14M_GCLK_IO0 ((PIN_PB14M_GCLK_IO0 << 16) | MUX_PB14M_GCLK_IO0) -#define PORT_PB14M_GCLK_IO0 ((1UL) << 14) - -#define PIN_PA14M_GCLK_IO0 (14L) -#define MUX_PA14M_GCLK_IO0 (12L) -#define PINMUX_PA14M_GCLK_IO0 ((PIN_PA14M_GCLK_IO0 << 16) | MUX_PA14M_GCLK_IO0) -#define PORT_PA14M_GCLK_IO0 ((1UL) << 14) - -#define PIN_PB22M_GCLK_IO0 (54L) -#define MUX_PB22M_GCLK_IO0 (12L) -#define PINMUX_PB22M_GCLK_IO0 ((PIN_PB22M_GCLK_IO0 << 16) | MUX_PB22M_GCLK_IO0) -#define PORT_PB22M_GCLK_IO0 ((1UL) << 22) - -#define PIN_PB15M_GCLK_IO1 (47L) -#define MUX_PB15M_GCLK_IO1 (12L) -#define PINMUX_PB15M_GCLK_IO1 ((PIN_PB15M_GCLK_IO1 << 16) | MUX_PB15M_GCLK_IO1) -#define PORT_PB15M_GCLK_IO1 ((1UL) << 15) - -#define PIN_PA15M_GCLK_IO1 (15L) -#define MUX_PA15M_GCLK_IO1 (12L) -#define PINMUX_PA15M_GCLK_IO1 ((PIN_PA15M_GCLK_IO1 << 16) | MUX_PA15M_GCLK_IO1) -#define PORT_PA15M_GCLK_IO1 ((1UL) << 15) - -#define PIN_PB23M_GCLK_IO1 (55L) -#define MUX_PB23M_GCLK_IO1 (12L) -#define PINMUX_PB23M_GCLK_IO1 ((PIN_PB23M_GCLK_IO1 << 16) | MUX_PB23M_GCLK_IO1) -#define PORT_PB23M_GCLK_IO1 ((1UL) << 23) - -#define PIN_PA27M_GCLK_IO1 (27L) -#define MUX_PA27M_GCLK_IO1 (12L) -#define PINMUX_PA27M_GCLK_IO1 ((PIN_PA27M_GCLK_IO1 << 16) | MUX_PA27M_GCLK_IO1) -#define PORT_PA27M_GCLK_IO1 ((1UL) << 27) - -#define PIN_PA16M_GCLK_IO2 (16L) -#define MUX_PA16M_GCLK_IO2 (12L) -#define PINMUX_PA16M_GCLK_IO2 ((PIN_PA16M_GCLK_IO2 << 16) | MUX_PA16M_GCLK_IO2) -#define PORT_PA16M_GCLK_IO2 ((1UL) << 16) - -#define PIN_PB16M_GCLK_IO2 (48L) -#define MUX_PB16M_GCLK_IO2 (12L) -#define PINMUX_PB16M_GCLK_IO2 ((PIN_PB16M_GCLK_IO2 << 16) | MUX_PB16M_GCLK_IO2) -#define PORT_PB16M_GCLK_IO2 ((1UL) << 16) - -#define PIN_PA17M_GCLK_IO3 (17L) -#define MUX_PA17M_GCLK_IO3 (12L) -#define PINMUX_PA17M_GCLK_IO3 ((PIN_PA17M_GCLK_IO3 << 16) | MUX_PA17M_GCLK_IO3) -#define PORT_PA17M_GCLK_IO3 ((1UL) << 17) - -#define PIN_PB17M_GCLK_IO3 (49L) -#define MUX_PB17M_GCLK_IO3 (12L) -#define PINMUX_PB17M_GCLK_IO3 ((PIN_PB17M_GCLK_IO3 << 16) | MUX_PB17M_GCLK_IO3) -#define PORT_PB17M_GCLK_IO3 ((1UL) << 17) - -#define PIN_PA10M_GCLK_IO4 (10L) -#define MUX_PA10M_GCLK_IO4 (12L) -#define PINMUX_PA10M_GCLK_IO4 ((PIN_PA10M_GCLK_IO4 << 16) | MUX_PA10M_GCLK_IO4) -#define PORT_PA10M_GCLK_IO4 ((1UL) << 10) - -#define PIN_PB10M_GCLK_IO4 (42L) -#define MUX_PB10M_GCLK_IO4 (12L) -#define PINMUX_PB10M_GCLK_IO4 ((PIN_PB10M_GCLK_IO4 << 16) | MUX_PB10M_GCLK_IO4) -#define PORT_PB10M_GCLK_IO4 ((1UL) << 10) - -#define PIN_PB18M_GCLK_IO4 (50L) -#define MUX_PB18M_GCLK_IO4 (12L) -#define PINMUX_PB18M_GCLK_IO4 ((PIN_PB18M_GCLK_IO4 << 16) | MUX_PB18M_GCLK_IO4) -#define PORT_PB18M_GCLK_IO4 ((1UL) << 18) - -#define PIN_PA11M_GCLK_IO5 (11L) -#define MUX_PA11M_GCLK_IO5 (12L) -#define PINMUX_PA11M_GCLK_IO5 ((PIN_PA11M_GCLK_IO5 << 16) | MUX_PA11M_GCLK_IO5) -#define PORT_PA11M_GCLK_IO5 ((1UL) << 11) - -#define PIN_PB11M_GCLK_IO5 (43L) -#define MUX_PB11M_GCLK_IO5 (12L) -#define PINMUX_PB11M_GCLK_IO5 ((PIN_PB11M_GCLK_IO5 << 16) | MUX_PB11M_GCLK_IO5) -#define PORT_PB11M_GCLK_IO5 ((1UL) << 11) - -#define PIN_PB19M_GCLK_IO5 (51L) -#define MUX_PB19M_GCLK_IO5 (12L) -#define PINMUX_PB19M_GCLK_IO5 ((PIN_PB19M_GCLK_IO5 << 16) | MUX_PB19M_GCLK_IO5) -#define PORT_PB19M_GCLK_IO5 ((1UL) << 19) - -#define PIN_PB12M_GCLK_IO6 (44L) -#define MUX_PB12M_GCLK_IO6 (12L) -#define PINMUX_PB12M_GCLK_IO6 ((PIN_PB12M_GCLK_IO6 << 16) | MUX_PB12M_GCLK_IO6) -#define PORT_PB12M_GCLK_IO6 ((1UL) << 12) - -#define PIN_PB20M_GCLK_IO6 (52L) -#define MUX_PB20M_GCLK_IO6 (12L) -#define PINMUX_PB20M_GCLK_IO6 ((PIN_PB20M_GCLK_IO6 << 16) | MUX_PB20M_GCLK_IO6) -#define PORT_PB20M_GCLK_IO6 ((1UL) << 20) - -#define PIN_PB13M_GCLK_IO7 (45L) -#define MUX_PB13M_GCLK_IO7 (12L) -#define PINMUX_PB13M_GCLK_IO7 ((PIN_PB13M_GCLK_IO7 << 16) | MUX_PB13M_GCLK_IO7) -#define PORT_PB13M_GCLK_IO7 ((1UL) << 13) - -#define PIN_PB21M_GCLK_IO7 (53L) -#define MUX_PB21M_GCLK_IO7 (12L) -#define PINMUX_PB21M_GCLK_IO7 ((PIN_PB21M_GCLK_IO7 << 16) | MUX_PB21M_GCLK_IO7) -#define PORT_PB21M_GCLK_IO7 ((1UL) << 21) - -/* ========== PORT definition for GMAC peripheral ========== */ -#define PIN_PC21L_GMAC_GCOL (85L) -#define MUX_PC21L_GMAC_GCOL (11L) -#define PINMUX_PC21L_GMAC_GCOL ((PIN_PC21L_GMAC_GCOL << 16) | MUX_PC21L_GMAC_GCOL) -#define PORT_PC21L_GMAC_GCOL ((1UL) << 21) - -#define PIN_PA16L_GMAC_GCRS (16L) -#define MUX_PA16L_GMAC_GCRS (11L) -#define PINMUX_PA16L_GMAC_GCRS ((PIN_PA16L_GMAC_GCRS << 16) | MUX_PA16L_GMAC_GCRS) -#define PORT_PA16L_GMAC_GCRS ((1UL) << 16) - -#define PIN_PA20L_GMAC_GMDC (20L) -#define MUX_PA20L_GMAC_GMDC (11L) -#define PINMUX_PA20L_GMAC_GMDC ((PIN_PA20L_GMAC_GMDC << 16) | MUX_PA20L_GMAC_GMDC) -#define PORT_PA20L_GMAC_GMDC ((1UL) << 20) - -#define PIN_PB14L_GMAC_GMDC (46L) -#define MUX_PB14L_GMAC_GMDC (11L) -#define PINMUX_PB14L_GMAC_GMDC ((PIN_PB14L_GMAC_GMDC << 16) | MUX_PB14L_GMAC_GMDC) -#define PORT_PB14L_GMAC_GMDC ((1UL) << 14) - -#define PIN_PC11L_GMAC_GMDC (75L) -#define MUX_PC11L_GMAC_GMDC (11L) -#define PINMUX_PC11L_GMAC_GMDC ((PIN_PC11L_GMAC_GMDC << 16) | MUX_PC11L_GMAC_GMDC) -#define PORT_PC11L_GMAC_GMDC ((1UL) << 11) - -#define PIN_PA21L_GMAC_GMDIO (21L) -#define MUX_PA21L_GMAC_GMDIO (11L) -#define PINMUX_PA21L_GMAC_GMDIO ((PIN_PA21L_GMAC_GMDIO << 16) | MUX_PA21L_GMAC_GMDIO) -#define PORT_PA21L_GMAC_GMDIO ((1UL) << 21) - -#define PIN_PB15L_GMAC_GMDIO (47L) -#define MUX_PB15L_GMAC_GMDIO (11L) -#define PINMUX_PB15L_GMAC_GMDIO ((PIN_PB15L_GMAC_GMDIO << 16) | MUX_PB15L_GMAC_GMDIO) -#define PORT_PB15L_GMAC_GMDIO ((1UL) << 15) - -#define PIN_PC12L_GMAC_GMDIO (76L) -#define MUX_PC12L_GMAC_GMDIO (11L) -#define PINMUX_PC12L_GMAC_GMDIO ((PIN_PC12L_GMAC_GMDIO << 16) | MUX_PC12L_GMAC_GMDIO) -#define PORT_PC12L_GMAC_GMDIO ((1UL) << 12) - -#define PIN_PA13L_GMAC_GRX0 (13L) -#define MUX_PA13L_GMAC_GRX0 (11L) -#define PINMUX_PA13L_GMAC_GRX0 ((PIN_PA13L_GMAC_GRX0 << 16) | MUX_PA13L_GMAC_GRX0) -#define PORT_PA13L_GMAC_GRX0 ((1UL) << 13) - -#define PIN_PA12L_GMAC_GRX1 (12L) -#define MUX_PA12L_GMAC_GRX1 (11L) -#define PINMUX_PA12L_GMAC_GRX1 ((PIN_PA12L_GMAC_GRX1 << 16) | MUX_PA12L_GMAC_GRX1) -#define PORT_PA12L_GMAC_GRX1 ((1UL) << 12) - -#define PIN_PC15L_GMAC_GRX2 (79L) -#define MUX_PC15L_GMAC_GRX2 (11L) -#define PINMUX_PC15L_GMAC_GRX2 ((PIN_PC15L_GMAC_GRX2 << 16) | MUX_PC15L_GMAC_GRX2) -#define PORT_PC15L_GMAC_GRX2 ((1UL) << 15) - -#define PIN_PC14L_GMAC_GRX3 (78L) -#define MUX_PC14L_GMAC_GRX3 (11L) -#define PINMUX_PC14L_GMAC_GRX3 ((PIN_PC14L_GMAC_GRX3 << 16) | MUX_PC14L_GMAC_GRX3) -#define PORT_PC14L_GMAC_GRX3 ((1UL) << 14) - -#define PIN_PC18L_GMAC_GRXCK (82L) -#define MUX_PC18L_GMAC_GRXCK (11L) -#define PINMUX_PC18L_GMAC_GRXCK ((PIN_PC18L_GMAC_GRXCK << 16) | MUX_PC18L_GMAC_GRXCK) -#define PORT_PC18L_GMAC_GRXCK ((1UL) << 18) - -#define PIN_PC20L_GMAC_GRXDV (84L) -#define MUX_PC20L_GMAC_GRXDV (11L) -#define PINMUX_PC20L_GMAC_GRXDV ((PIN_PC20L_GMAC_GRXDV << 16) | MUX_PC20L_GMAC_GRXDV) -#define PORT_PC20L_GMAC_GRXDV ((1UL) << 20) - -#define PIN_PA15L_GMAC_GRXER (15L) -#define MUX_PA15L_GMAC_GRXER (11L) -#define PINMUX_PA15L_GMAC_GRXER ((PIN_PA15L_GMAC_GRXER << 16) | MUX_PA15L_GMAC_GRXER) -#define PORT_PA15L_GMAC_GRXER ((1UL) << 15) - -#define PIN_PA18L_GMAC_GTX0 (18L) -#define MUX_PA18L_GMAC_GTX0 (11L) -#define PINMUX_PA18L_GMAC_GTX0 ((PIN_PA18L_GMAC_GTX0 << 16) | MUX_PA18L_GMAC_GTX0) -#define PORT_PA18L_GMAC_GTX0 ((1UL) << 18) - -#define PIN_PA19L_GMAC_GTX1 (19L) -#define MUX_PA19L_GMAC_GTX1 (11L) -#define PINMUX_PA19L_GMAC_GTX1 ((PIN_PA19L_GMAC_GTX1 << 16) | MUX_PA19L_GMAC_GTX1) -#define PORT_PA19L_GMAC_GTX1 ((1UL) << 19) - -#define PIN_PC16L_GMAC_GTX2 (80L) -#define MUX_PC16L_GMAC_GTX2 (11L) -#define PINMUX_PC16L_GMAC_GTX2 ((PIN_PC16L_GMAC_GTX2 << 16) | MUX_PC16L_GMAC_GTX2) -#define PORT_PC16L_GMAC_GTX2 ((1UL) << 16) - -#define PIN_PC17L_GMAC_GTX3 (81L) -#define MUX_PC17L_GMAC_GTX3 (11L) -#define PINMUX_PC17L_GMAC_GTX3 ((PIN_PC17L_GMAC_GTX3 << 16) | MUX_PC17L_GMAC_GTX3) -#define PORT_PC17L_GMAC_GTX3 ((1UL) << 17) - -#define PIN_PA14L_GMAC_GTXCK (14L) -#define MUX_PA14L_GMAC_GTXCK (11L) -#define PINMUX_PA14L_GMAC_GTXCK ((PIN_PA14L_GMAC_GTXCK << 16) | MUX_PA14L_GMAC_GTXCK) -#define PORT_PA14L_GMAC_GTXCK ((1UL) << 14) - -#define PIN_PA17L_GMAC_GTXEN (17L) -#define MUX_PA17L_GMAC_GTXEN (11L) -#define PINMUX_PA17L_GMAC_GTXEN ((PIN_PA17L_GMAC_GTXEN << 16) | MUX_PA17L_GMAC_GTXEN) -#define PORT_PA17L_GMAC_GTXEN ((1UL) << 17) - -#define PIN_PC19L_GMAC_GTXER (83L) -#define MUX_PC19L_GMAC_GTXER (11L) -#define PINMUX_PC19L_GMAC_GTXER ((PIN_PC19L_GMAC_GTXER << 16) | MUX_PC19L_GMAC_GTXER) -#define PORT_PC19L_GMAC_GTXER ((1UL) << 19) - -/* ========== PORT definition for I2S peripheral ========== */ -#define PIN_PA09J_I2S_FS0 (9L) -#define MUX_PA09J_I2S_FS0 (9L) -#define PINMUX_PA09J_I2S_FS0 ((PIN_PA09J_I2S_FS0 << 16) | MUX_PA09J_I2S_FS0) -#define PORT_PA09J_I2S_FS0 ((1UL) << 9) - -#define PIN_PA20J_I2S_FS0 (20L) -#define MUX_PA20J_I2S_FS0 (9L) -#define PINMUX_PA20J_I2S_FS0 ((PIN_PA20J_I2S_FS0 << 16) | MUX_PA20J_I2S_FS0) -#define PORT_PA20J_I2S_FS0 ((1UL) << 20) - -#define PIN_PA23J_I2S_FS1 (23L) -#define MUX_PA23J_I2S_FS1 (9L) -#define PINMUX_PA23J_I2S_FS1 ((PIN_PA23J_I2S_FS1 << 16) | MUX_PA23J_I2S_FS1) -#define PORT_PA23J_I2S_FS1 ((1UL) << 23) - -#define PIN_PB11J_I2S_FS1 (43L) -#define MUX_PB11J_I2S_FS1 (9L) -#define PINMUX_PB11J_I2S_FS1 ((PIN_PB11J_I2S_FS1 << 16) | MUX_PB11J_I2S_FS1) -#define PORT_PB11J_I2S_FS1 ((1UL) << 11) - -#define PIN_PA08J_I2S_MCK0 (8L) -#define MUX_PA08J_I2S_MCK0 (9L) -#define PINMUX_PA08J_I2S_MCK0 ((PIN_PA08J_I2S_MCK0 << 16) | MUX_PA08J_I2S_MCK0) -#define PORT_PA08J_I2S_MCK0 ((1UL) << 8) - -#define PIN_PB17J_I2S_MCK0 (49L) -#define MUX_PB17J_I2S_MCK0 (9L) -#define PINMUX_PB17J_I2S_MCK0 ((PIN_PB17J_I2S_MCK0 << 16) | MUX_PB17J_I2S_MCK0) -#define PORT_PB17J_I2S_MCK0 ((1UL) << 17) - -#define PIN_PB13J_I2S_MCK1 (45L) -#define MUX_PB13J_I2S_MCK1 (9L) -#define PINMUX_PB13J_I2S_MCK1 ((PIN_PB13J_I2S_MCK1 << 16) | MUX_PB13J_I2S_MCK1) -#define PORT_PB13J_I2S_MCK1 ((1UL) << 13) - -#define PIN_PA10J_I2S_SCK0 (10L) -#define MUX_PA10J_I2S_SCK0 (9L) -#define PINMUX_PA10J_I2S_SCK0 ((PIN_PA10J_I2S_SCK0 << 16) | MUX_PA10J_I2S_SCK0) -#define PORT_PA10J_I2S_SCK0 ((1UL) << 10) - -#define PIN_PB16J_I2S_SCK0 (48L) -#define MUX_PB16J_I2S_SCK0 (9L) -#define PINMUX_PB16J_I2S_SCK0 ((PIN_PB16J_I2S_SCK0 << 16) | MUX_PB16J_I2S_SCK0) -#define PORT_PB16J_I2S_SCK0 ((1UL) << 16) - -#define PIN_PB12J_I2S_SCK1 (44L) -#define MUX_PB12J_I2S_SCK1 (9L) -#define PINMUX_PB12J_I2S_SCK1 ((PIN_PB12J_I2S_SCK1 << 16) | MUX_PB12J_I2S_SCK1) -#define PORT_PB12J_I2S_SCK1 ((1UL) << 12) - -#define PIN_PA22J_I2S_SDI (22L) -#define MUX_PA22J_I2S_SDI (9L) -#define PINMUX_PA22J_I2S_SDI ((PIN_PA22J_I2S_SDI << 16) | MUX_PA22J_I2S_SDI) -#define PORT_PA22J_I2S_SDI ((1UL) << 22) - -#define PIN_PB10J_I2S_SDI (42L) -#define MUX_PB10J_I2S_SDI (9L) -#define PINMUX_PB10J_I2S_SDI ((PIN_PB10J_I2S_SDI << 16) | MUX_PB10J_I2S_SDI) -#define PORT_PB10J_I2S_SDI ((1UL) << 10) - -#define PIN_PA11J_I2S_SDO (11L) -#define MUX_PA11J_I2S_SDO (9L) -#define PINMUX_PA11J_I2S_SDO ((PIN_PA11J_I2S_SDO << 16) | MUX_PA11J_I2S_SDO) -#define PORT_PA11J_I2S_SDO ((1UL) << 11) - -#define PIN_PA21J_I2S_SDO (21L) -#define MUX_PA21J_I2S_SDO (9L) -#define PINMUX_PA21J_I2S_SDO ((PIN_PA21J_I2S_SDO << 16) | MUX_PA21J_I2S_SDO) -#define PORT_PA21J_I2S_SDO ((1UL) << 21) - -/* ========== PORT definition for PCC peripheral ========== */ -#define PIN_PA14K_PCC_CLK (14L) -#define MUX_PA14K_PCC_CLK (10L) -#define PINMUX_PA14K_PCC_CLK ((PIN_PA14K_PCC_CLK << 16) | MUX_PA14K_PCC_CLK) -#define PORT_PA14K_PCC_CLK ((1UL) << 14) - -#define PIN_PA16K_PCC_DATA0 (16L) -#define MUX_PA16K_PCC_DATA0 (10L) -#define PINMUX_PA16K_PCC_DATA0 ((PIN_PA16K_PCC_DATA0 << 16) | MUX_PA16K_PCC_DATA0) -#define PORT_PA16K_PCC_DATA0 ((1UL) << 16) - -#define PIN_PA17K_PCC_DATA1 (17L) -#define MUX_PA17K_PCC_DATA1 (10L) -#define PINMUX_PA17K_PCC_DATA1 ((PIN_PA17K_PCC_DATA1 << 16) | MUX_PA17K_PCC_DATA1) -#define PORT_PA17K_PCC_DATA1 ((1UL) << 17) - -#define PIN_PA18K_PCC_DATA2 (18L) -#define MUX_PA18K_PCC_DATA2 (10L) -#define PINMUX_PA18K_PCC_DATA2 ((PIN_PA18K_PCC_DATA2 << 16) | MUX_PA18K_PCC_DATA2) -#define PORT_PA18K_PCC_DATA2 ((1UL) << 18) - -#define PIN_PA19K_PCC_DATA3 (19L) -#define MUX_PA19K_PCC_DATA3 (10L) -#define PINMUX_PA19K_PCC_DATA3 ((PIN_PA19K_PCC_DATA3 << 16) | MUX_PA19K_PCC_DATA3) -#define PORT_PA19K_PCC_DATA3 ((1UL) << 19) - -#define PIN_PA20K_PCC_DATA4 (20L) -#define MUX_PA20K_PCC_DATA4 (10L) -#define PINMUX_PA20K_PCC_DATA4 ((PIN_PA20K_PCC_DATA4 << 16) | MUX_PA20K_PCC_DATA4) -#define PORT_PA20K_PCC_DATA4 ((1UL) << 20) - -#define PIN_PA21K_PCC_DATA5 (21L) -#define MUX_PA21K_PCC_DATA5 (10L) -#define PINMUX_PA21K_PCC_DATA5 ((PIN_PA21K_PCC_DATA5 << 16) | MUX_PA21K_PCC_DATA5) -#define PORT_PA21K_PCC_DATA5 ((1UL) << 21) - -#define PIN_PA22K_PCC_DATA6 (22L) -#define MUX_PA22K_PCC_DATA6 (10L) -#define PINMUX_PA22K_PCC_DATA6 ((PIN_PA22K_PCC_DATA6 << 16) | MUX_PA22K_PCC_DATA6) -#define PORT_PA22K_PCC_DATA6 ((1UL) << 22) - -#define PIN_PA23K_PCC_DATA7 (23L) -#define MUX_PA23K_PCC_DATA7 (10L) -#define PINMUX_PA23K_PCC_DATA7 ((PIN_PA23K_PCC_DATA7 << 16) | MUX_PA23K_PCC_DATA7) -#define PORT_PA23K_PCC_DATA7 ((1UL) << 23) - -#define PIN_PB14K_PCC_DATA8 (46L) -#define MUX_PB14K_PCC_DATA8 (10L) -#define PINMUX_PB14K_PCC_DATA8 ((PIN_PB14K_PCC_DATA8 << 16) | MUX_PB14K_PCC_DATA8) -#define PORT_PB14K_PCC_DATA8 ((1UL) << 14) - -#define PIN_PB15K_PCC_DATA9 (47L) -#define MUX_PB15K_PCC_DATA9 (10L) -#define PINMUX_PB15K_PCC_DATA9 ((PIN_PB15K_PCC_DATA9 << 16) | MUX_PB15K_PCC_DATA9) -#define PORT_PB15K_PCC_DATA9 ((1UL) << 15) - -#define PIN_PC12K_PCC_DATA10 (76L) -#define MUX_PC12K_PCC_DATA10 (10L) -#define PINMUX_PC12K_PCC_DATA10 ((PIN_PC12K_PCC_DATA10 << 16) | MUX_PC12K_PCC_DATA10) -#define PORT_PC12K_PCC_DATA10 ((1UL) << 12) - -#define PIN_PC13K_PCC_DATA11 (77L) -#define MUX_PC13K_PCC_DATA11 (10L) -#define PINMUX_PC13K_PCC_DATA11 ((PIN_PC13K_PCC_DATA11 << 16) | MUX_PC13K_PCC_DATA11) -#define PORT_PC13K_PCC_DATA11 ((1UL) << 13) - -#define PIN_PC14K_PCC_DATA12 (78L) -#define MUX_PC14K_PCC_DATA12 (10L) -#define PINMUX_PC14K_PCC_DATA12 ((PIN_PC14K_PCC_DATA12 << 16) | MUX_PC14K_PCC_DATA12) -#define PORT_PC14K_PCC_DATA12 ((1UL) << 14) - -#define PIN_PC15K_PCC_DATA13 (79L) -#define MUX_PC15K_PCC_DATA13 (10L) -#define PINMUX_PC15K_PCC_DATA13 ((PIN_PC15K_PCC_DATA13 << 16) | MUX_PC15K_PCC_DATA13) -#define PORT_PC15K_PCC_DATA13 ((1UL) << 15) - -#define PIN_PA12K_PCC_DEN1 (12L) -#define MUX_PA12K_PCC_DEN1 (10L) -#define PINMUX_PA12K_PCC_DEN1 ((PIN_PA12K_PCC_DEN1 << 16) | MUX_PA12K_PCC_DEN1) -#define PORT_PA12K_PCC_DEN1 ((1UL) << 12) - -#define PIN_PA13K_PCC_DEN2 (13L) -#define MUX_PA13K_PCC_DEN2 (10L) -#define PINMUX_PA13K_PCC_DEN2 ((PIN_PA13K_PCC_DEN2 << 16) | MUX_PA13K_PCC_DEN2) -#define PORT_PA13K_PCC_DEN2 ((1UL) << 13) - -/* ========== PORT definition for PDEC peripheral ========== */ -#define PIN_PB18G_PDEC_QDI0 (50L) -#define MUX_PB18G_PDEC_QDI0 (6L) -#define PINMUX_PB18G_PDEC_QDI0 ((PIN_PB18G_PDEC_QDI0 << 16) | MUX_PB18G_PDEC_QDI0) -#define PORT_PB18G_PDEC_QDI0 ((1UL) << 18) - -#define PIN_PB23G_PDEC_QDI0 (55L) -#define MUX_PB23G_PDEC_QDI0 (6L) -#define PINMUX_PB23G_PDEC_QDI0 ((PIN_PB23G_PDEC_QDI0 << 16) | MUX_PB23G_PDEC_QDI0) -#define PORT_PB23G_PDEC_QDI0 ((1UL) << 23) - -#define PIN_PC16G_PDEC_QDI0 (80L) -#define MUX_PC16G_PDEC_QDI0 (6L) -#define PINMUX_PC16G_PDEC_QDI0 ((PIN_PC16G_PDEC_QDI0 << 16) | MUX_PC16G_PDEC_QDI0) -#define PORT_PC16G_PDEC_QDI0 ((1UL) << 16) - -#define PIN_PA24G_PDEC_QDI0 (24L) -#define MUX_PA24G_PDEC_QDI0 (6L) -#define PINMUX_PA24G_PDEC_QDI0 ((PIN_PA24G_PDEC_QDI0 << 16) | MUX_PA24G_PDEC_QDI0) -#define PORT_PA24G_PDEC_QDI0 ((1UL) << 24) - -#define PIN_PB19G_PDEC_QDI1 (51L) -#define MUX_PB19G_PDEC_QDI1 (6L) -#define PINMUX_PB19G_PDEC_QDI1 ((PIN_PB19G_PDEC_QDI1 << 16) | MUX_PB19G_PDEC_QDI1) -#define PORT_PB19G_PDEC_QDI1 ((1UL) << 19) - -#define PIN_PB24G_PDEC_QDI1 (56L) -#define MUX_PB24G_PDEC_QDI1 (6L) -#define PINMUX_PB24G_PDEC_QDI1 ((PIN_PB24G_PDEC_QDI1 << 16) | MUX_PB24G_PDEC_QDI1) -#define PORT_PB24G_PDEC_QDI1 ((1UL) << 24) - -#define PIN_PC17G_PDEC_QDI1 (81L) -#define MUX_PC17G_PDEC_QDI1 (6L) -#define PINMUX_PC17G_PDEC_QDI1 ((PIN_PC17G_PDEC_QDI1 << 16) | MUX_PC17G_PDEC_QDI1) -#define PORT_PC17G_PDEC_QDI1 ((1UL) << 17) - -#define PIN_PA25G_PDEC_QDI1 (25L) -#define MUX_PA25G_PDEC_QDI1 (6L) -#define PINMUX_PA25G_PDEC_QDI1 ((PIN_PA25G_PDEC_QDI1 << 16) | MUX_PA25G_PDEC_QDI1) -#define PORT_PA25G_PDEC_QDI1 ((1UL) << 25) - -#define PIN_PB20G_PDEC_QDI2 (52L) -#define MUX_PB20G_PDEC_QDI2 (6L) -#define PINMUX_PB20G_PDEC_QDI2 ((PIN_PB20G_PDEC_QDI2 << 16) | MUX_PB20G_PDEC_QDI2) -#define PORT_PB20G_PDEC_QDI2 ((1UL) << 20) - -#define PIN_PB25G_PDEC_QDI2 (57L) -#define MUX_PB25G_PDEC_QDI2 (6L) -#define PINMUX_PB25G_PDEC_QDI2 ((PIN_PB25G_PDEC_QDI2 << 16) | MUX_PB25G_PDEC_QDI2) -#define PORT_PB25G_PDEC_QDI2 ((1UL) << 25) - -#define PIN_PC18G_PDEC_QDI2 (82L) -#define MUX_PC18G_PDEC_QDI2 (6L) -#define PINMUX_PC18G_PDEC_QDI2 ((PIN_PC18G_PDEC_QDI2 << 16) | MUX_PC18G_PDEC_QDI2) -#define PORT_PC18G_PDEC_QDI2 ((1UL) << 18) - -#define PIN_PB22G_PDEC_QDI2 (54L) -#define MUX_PB22G_PDEC_QDI2 (6L) -#define PINMUX_PB22G_PDEC_QDI2 ((PIN_PB22G_PDEC_QDI2 << 16) | MUX_PB22G_PDEC_QDI2) -#define PORT_PB22G_PDEC_QDI2 ((1UL) << 22) - -/* ========== PORT definition for QSPI peripheral ========== */ -#define PIN_PB11H_QSPI_CS (43L) -#define MUX_PB11H_QSPI_CS (7L) -#define PINMUX_PB11H_QSPI_CS ((PIN_PB11H_QSPI_CS << 16) | MUX_PB11H_QSPI_CS) -#define PORT_PB11H_QSPI_CS ((1UL) << 11) - -#define PIN_PA08H_QSPI_DATA0 (8L) -#define MUX_PA08H_QSPI_DATA0 (7L) -#define PINMUX_PA08H_QSPI_DATA0 ((PIN_PA08H_QSPI_DATA0 << 16) | MUX_PA08H_QSPI_DATA0) -#define PORT_PA08H_QSPI_DATA0 ((1UL) << 8) - -#define PIN_PA09H_QSPI_DATA1 (9L) -#define MUX_PA09H_QSPI_DATA1 (7L) -#define PINMUX_PA09H_QSPI_DATA1 ((PIN_PA09H_QSPI_DATA1 << 16) | MUX_PA09H_QSPI_DATA1) -#define PORT_PA09H_QSPI_DATA1 ((1UL) << 9) - -#define PIN_PA10H_QSPI_DATA2 (10L) -#define MUX_PA10H_QSPI_DATA2 (7L) -#define PINMUX_PA10H_QSPI_DATA2 ((PIN_PA10H_QSPI_DATA2 << 16) | MUX_PA10H_QSPI_DATA2) -#define PORT_PA10H_QSPI_DATA2 ((1UL) << 10) - -#define PIN_PA11H_QSPI_DATA3 (11L) -#define MUX_PA11H_QSPI_DATA3 (7L) -#define PINMUX_PA11H_QSPI_DATA3 ((PIN_PA11H_QSPI_DATA3 << 16) | MUX_PA11H_QSPI_DATA3) -#define PORT_PA11H_QSPI_DATA3 ((1UL) << 11) - -#define PIN_PB10H_QSPI_SCK (42L) -#define MUX_PB10H_QSPI_SCK (7L) -#define PINMUX_PB10H_QSPI_SCK ((PIN_PB10H_QSPI_SCK << 16) | MUX_PB10H_QSPI_SCK) -#define PORT_PB10H_QSPI_SCK ((1UL) << 10) - -/* ========== PORT definition for SDHC0 peripheral ========== */ -#define PIN_PA06I_SDHC0_SDCD (6L) -#define MUX_PA06I_SDHC0_SDCD (8L) -#define PINMUX_PA06I_SDHC0_SDCD ((PIN_PA06I_SDHC0_SDCD << 16) | MUX_PA06I_SDHC0_SDCD) -#define PORT_PA06I_SDHC0_SDCD ((1UL) << 6) - -#define PIN_PA12I_SDHC0_SDCD (12L) -#define MUX_PA12I_SDHC0_SDCD (8L) -#define PINMUX_PA12I_SDHC0_SDCD ((PIN_PA12I_SDHC0_SDCD << 16) | MUX_PA12I_SDHC0_SDCD) -#define PORT_PA12I_SDHC0_SDCD ((1UL) << 12) - -#define PIN_PB12I_SDHC0_SDCD (44L) -#define MUX_PB12I_SDHC0_SDCD (8L) -#define PINMUX_PB12I_SDHC0_SDCD ((PIN_PB12I_SDHC0_SDCD << 16) | MUX_PB12I_SDHC0_SDCD) -#define PORT_PB12I_SDHC0_SDCD ((1UL) << 12) - -#define PIN_PC06I_SDHC0_SDCD (70L) -#define MUX_PC06I_SDHC0_SDCD (8L) -#define PINMUX_PC06I_SDHC0_SDCD ((PIN_PC06I_SDHC0_SDCD << 16) | MUX_PC06I_SDHC0_SDCD) -#define PORT_PC06I_SDHC0_SDCD ((1UL) << 6) - -#define PIN_PB11I_SDHC0_SDCK (43L) -#define MUX_PB11I_SDHC0_SDCK (8L) -#define PINMUX_PB11I_SDHC0_SDCK ((PIN_PB11I_SDHC0_SDCK << 16) | MUX_PB11I_SDHC0_SDCK) -#define PORT_PB11I_SDHC0_SDCK ((1UL) << 11) - -#define PIN_PA08I_SDHC0_SDCMD (8L) -#define MUX_PA08I_SDHC0_SDCMD (8L) -#define PINMUX_PA08I_SDHC0_SDCMD ((PIN_PA08I_SDHC0_SDCMD << 16) | MUX_PA08I_SDHC0_SDCMD) -#define PORT_PA08I_SDHC0_SDCMD ((1UL) << 8) - -#define PIN_PA09I_SDHC0_SDDAT0 (9L) -#define MUX_PA09I_SDHC0_SDDAT0 (8L) -#define PINMUX_PA09I_SDHC0_SDDAT0 ((PIN_PA09I_SDHC0_SDDAT0 << 16) | MUX_PA09I_SDHC0_SDDAT0) -#define PORT_PA09I_SDHC0_SDDAT0 ((1UL) << 9) - -#define PIN_PA10I_SDHC0_SDDAT1 (10L) -#define MUX_PA10I_SDHC0_SDDAT1 (8L) -#define PINMUX_PA10I_SDHC0_SDDAT1 ((PIN_PA10I_SDHC0_SDDAT1 << 16) | MUX_PA10I_SDHC0_SDDAT1) -#define PORT_PA10I_SDHC0_SDDAT1 ((1UL) << 10) - -#define PIN_PA11I_SDHC0_SDDAT2 (11L) -#define MUX_PA11I_SDHC0_SDDAT2 (8L) -#define PINMUX_PA11I_SDHC0_SDDAT2 ((PIN_PA11I_SDHC0_SDDAT2 << 16) | MUX_PA11I_SDHC0_SDDAT2) -#define PORT_PA11I_SDHC0_SDDAT2 ((1UL) << 11) - -#define PIN_PB10I_SDHC0_SDDAT3 (42L) -#define MUX_PB10I_SDHC0_SDDAT3 (8L) -#define PINMUX_PB10I_SDHC0_SDDAT3 ((PIN_PB10I_SDHC0_SDDAT3 << 16) | MUX_PB10I_SDHC0_SDDAT3) -#define PORT_PB10I_SDHC0_SDDAT3 ((1UL) << 10) - -#define PIN_PA07I_SDHC0_SDWP (7L) -#define MUX_PA07I_SDHC0_SDWP (8L) -#define PINMUX_PA07I_SDHC0_SDWP ((PIN_PA07I_SDHC0_SDWP << 16) | MUX_PA07I_SDHC0_SDWP) -#define PORT_PA07I_SDHC0_SDWP ((1UL) << 7) - -#define PIN_PA13I_SDHC0_SDWP (13L) -#define MUX_PA13I_SDHC0_SDWP (8L) -#define PINMUX_PA13I_SDHC0_SDWP ((PIN_PA13I_SDHC0_SDWP << 16) | MUX_PA13I_SDHC0_SDWP) -#define PORT_PA13I_SDHC0_SDWP ((1UL) << 13) - -#define PIN_PB13I_SDHC0_SDWP (45L) -#define MUX_PB13I_SDHC0_SDWP (8L) -#define PINMUX_PB13I_SDHC0_SDWP ((PIN_PB13I_SDHC0_SDWP << 16) | MUX_PB13I_SDHC0_SDWP) -#define PORT_PB13I_SDHC0_SDWP ((1UL) << 13) - -#define PIN_PC07I_SDHC0_SDWP (71L) -#define MUX_PC07I_SDHC0_SDWP (8L) -#define PINMUX_PC07I_SDHC0_SDWP ((PIN_PC07I_SDHC0_SDWP << 16) | MUX_PC07I_SDHC0_SDWP) -#define PORT_PC07I_SDHC0_SDWP ((1UL) << 7) - -/* ========== PORT definition for SDHC1 peripheral ========== */ -#define PIN_PB16I_SDHC1_SDCD (48L) -#define MUX_PB16I_SDHC1_SDCD (8L) -#define PINMUX_PB16I_SDHC1_SDCD ((PIN_PB16I_SDHC1_SDCD << 16) | MUX_PB16I_SDHC1_SDCD) -#define PORT_PB16I_SDHC1_SDCD ((1UL) << 16) - -#define PIN_PC20I_SDHC1_SDCD (84L) -#define MUX_PC20I_SDHC1_SDCD (8L) -#define PINMUX_PC20I_SDHC1_SDCD ((PIN_PC20I_SDHC1_SDCD << 16) | MUX_PC20I_SDHC1_SDCD) -#define PORT_PC20I_SDHC1_SDCD ((1UL) << 20) - -#define PIN_PA21I_SDHC1_SDCK (21L) -#define MUX_PA21I_SDHC1_SDCK (8L) -#define PINMUX_PA21I_SDHC1_SDCK ((PIN_PA21I_SDHC1_SDCK << 16) | MUX_PA21I_SDHC1_SDCK) -#define PORT_PA21I_SDHC1_SDCK ((1UL) << 21) - -#define PIN_PA20I_SDHC1_SDCMD (20L) -#define MUX_PA20I_SDHC1_SDCMD (8L) -#define PINMUX_PA20I_SDHC1_SDCMD ((PIN_PA20I_SDHC1_SDCMD << 16) | MUX_PA20I_SDHC1_SDCMD) -#define PORT_PA20I_SDHC1_SDCMD ((1UL) << 20) - -#define PIN_PB18I_SDHC1_SDDAT0 (50L) -#define MUX_PB18I_SDHC1_SDDAT0 (8L) -#define PINMUX_PB18I_SDHC1_SDDAT0 ((PIN_PB18I_SDHC1_SDDAT0 << 16) | MUX_PB18I_SDHC1_SDDAT0) -#define PORT_PB18I_SDHC1_SDDAT0 ((1UL) << 18) - -#define PIN_PB19I_SDHC1_SDDAT1 (51L) -#define MUX_PB19I_SDHC1_SDDAT1 (8L) -#define PINMUX_PB19I_SDHC1_SDDAT1 ((PIN_PB19I_SDHC1_SDDAT1 << 16) | MUX_PB19I_SDHC1_SDDAT1) -#define PORT_PB19I_SDHC1_SDDAT1 ((1UL) << 19) - -#define PIN_PB20I_SDHC1_SDDAT2 (52L) -#define MUX_PB20I_SDHC1_SDDAT2 (8L) -#define PINMUX_PB20I_SDHC1_SDDAT2 ((PIN_PB20I_SDHC1_SDDAT2 << 16) | MUX_PB20I_SDHC1_SDDAT2) -#define PORT_PB20I_SDHC1_SDDAT2 ((1UL) << 20) - -#define PIN_PB21I_SDHC1_SDDAT3 (53L) -#define MUX_PB21I_SDHC1_SDDAT3 (8L) -#define PINMUX_PB21I_SDHC1_SDDAT3 ((PIN_PB21I_SDHC1_SDDAT3 << 16) | MUX_PB21I_SDHC1_SDDAT3) -#define PORT_PB21I_SDHC1_SDDAT3 ((1UL) << 21) - -#define PIN_PB17I_SDHC1_SDWP (49L) -#define MUX_PB17I_SDHC1_SDWP (8L) -#define PINMUX_PB17I_SDHC1_SDWP ((PIN_PB17I_SDHC1_SDWP << 16) | MUX_PB17I_SDHC1_SDWP) -#define PORT_PB17I_SDHC1_SDWP ((1UL) << 17) - -#define PIN_PC21I_SDHC1_SDWP (85L) -#define MUX_PC21I_SDHC1_SDWP (8L) -#define PINMUX_PC21I_SDHC1_SDWP ((PIN_PC21I_SDHC1_SDWP << 16) | MUX_PC21I_SDHC1_SDWP) -#define PORT_PC21I_SDHC1_SDWP ((1UL) << 21) - -/* ========== PORT definition for SERCOM0 peripheral ========== */ -#define PIN_PA04D_SERCOM0_PAD0 (4L) -#define MUX_PA04D_SERCOM0_PAD0 (3L) -#define PINMUX_PA04D_SERCOM0_PAD0 ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0) -#define PORT_PA04D_SERCOM0_PAD0 ((1UL) << 4) - -#define PIN_PC17D_SERCOM0_PAD0 (81L) -#define MUX_PC17D_SERCOM0_PAD0 (3L) -#define PINMUX_PC17D_SERCOM0_PAD0 ((PIN_PC17D_SERCOM0_PAD0 << 16) | MUX_PC17D_SERCOM0_PAD0) -#define PORT_PC17D_SERCOM0_PAD0 ((1UL) << 17) - -#define PIN_PA08C_SERCOM0_PAD0 (8L) -#define MUX_PA08C_SERCOM0_PAD0 (2L) -#define PINMUX_PA08C_SERCOM0_PAD0 ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0) -#define PORT_PA08C_SERCOM0_PAD0 ((1UL) << 8) - -#define PIN_PB24C_SERCOM0_PAD0 (56L) -#define MUX_PB24C_SERCOM0_PAD0 (2L) -#define PINMUX_PB24C_SERCOM0_PAD0 ((PIN_PB24C_SERCOM0_PAD0 << 16) | MUX_PB24C_SERCOM0_PAD0) -#define PORT_PB24C_SERCOM0_PAD0 ((1UL) << 24) - -#define PIN_PA05D_SERCOM0_PAD1 (5L) -#define MUX_PA05D_SERCOM0_PAD1 (3L) -#define PINMUX_PA05D_SERCOM0_PAD1 ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1) -#define PORT_PA05D_SERCOM0_PAD1 ((1UL) << 5) - -#define PIN_PC16D_SERCOM0_PAD1 (80L) -#define MUX_PC16D_SERCOM0_PAD1 (3L) -#define PINMUX_PC16D_SERCOM0_PAD1 ((PIN_PC16D_SERCOM0_PAD1 << 16) | MUX_PC16D_SERCOM0_PAD1) -#define PORT_PC16D_SERCOM0_PAD1 ((1UL) << 16) - -#define PIN_PA09C_SERCOM0_PAD1 (9L) -#define MUX_PA09C_SERCOM0_PAD1 (2L) -#define PINMUX_PA09C_SERCOM0_PAD1 ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1) -#define PORT_PA09C_SERCOM0_PAD1 ((1UL) << 9) - -#define PIN_PB25C_SERCOM0_PAD1 (57L) -#define MUX_PB25C_SERCOM0_PAD1 (2L) -#define PINMUX_PB25C_SERCOM0_PAD1 ((PIN_PB25C_SERCOM0_PAD1 << 16) | MUX_PB25C_SERCOM0_PAD1) -#define PORT_PB25C_SERCOM0_PAD1 ((1UL) << 25) - -#define PIN_PA06D_SERCOM0_PAD2 (6L) -#define MUX_PA06D_SERCOM0_PAD2 (3L) -#define PINMUX_PA06D_SERCOM0_PAD2 ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2) -#define PORT_PA06D_SERCOM0_PAD2 ((1UL) << 6) - -#define PIN_PC18D_SERCOM0_PAD2 (82L) -#define MUX_PC18D_SERCOM0_PAD2 (3L) -#define PINMUX_PC18D_SERCOM0_PAD2 ((PIN_PC18D_SERCOM0_PAD2 << 16) | MUX_PC18D_SERCOM0_PAD2) -#define PORT_PC18D_SERCOM0_PAD2 ((1UL) << 18) - -#define PIN_PA10C_SERCOM0_PAD2 (10L) -#define MUX_PA10C_SERCOM0_PAD2 (2L) -#define PINMUX_PA10C_SERCOM0_PAD2 ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2) -#define PORT_PA10C_SERCOM0_PAD2 ((1UL) << 10) - -#define PIN_PC24C_SERCOM0_PAD2 (88L) -#define MUX_PC24C_SERCOM0_PAD2 (2L) -#define PINMUX_PC24C_SERCOM0_PAD2 ((PIN_PC24C_SERCOM0_PAD2 << 16) | MUX_PC24C_SERCOM0_PAD2) -#define PORT_PC24C_SERCOM0_PAD2 ((1UL) << 24) - -#define PIN_PA07D_SERCOM0_PAD3 (7L) -#define MUX_PA07D_SERCOM0_PAD3 (3L) -#define PINMUX_PA07D_SERCOM0_PAD3 ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3) -#define PORT_PA07D_SERCOM0_PAD3 ((1UL) << 7) - -#define PIN_PC19D_SERCOM0_PAD3 (83L) -#define MUX_PC19D_SERCOM0_PAD3 (3L) -#define PINMUX_PC19D_SERCOM0_PAD3 ((PIN_PC19D_SERCOM0_PAD3 << 16) | MUX_PC19D_SERCOM0_PAD3) -#define PORT_PC19D_SERCOM0_PAD3 ((1UL) << 19) - -#define PIN_PA11C_SERCOM0_PAD3 (11L) -#define MUX_PA11C_SERCOM0_PAD3 (2L) -#define PINMUX_PA11C_SERCOM0_PAD3 ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3) -#define PORT_PA11C_SERCOM0_PAD3 ((1UL) << 11) - -#define PIN_PC25C_SERCOM0_PAD3 (89L) -#define MUX_PC25C_SERCOM0_PAD3 (2L) -#define PINMUX_PC25C_SERCOM0_PAD3 ((PIN_PC25C_SERCOM0_PAD3 << 16) | MUX_PC25C_SERCOM0_PAD3) -#define PORT_PC25C_SERCOM0_PAD3 ((1UL) << 25) - -/* ========== PORT definition for SERCOM1 peripheral ========== */ -#define PIN_PA00D_SERCOM1_PAD0 (0L) -#define MUX_PA00D_SERCOM1_PAD0 (3L) -#define PINMUX_PA00D_SERCOM1_PAD0 ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0) -#define PORT_PA00D_SERCOM1_PAD0 ((1UL) << 0) - -#define PIN_PA16C_SERCOM1_PAD0 (16L) -#define MUX_PA16C_SERCOM1_PAD0 (2L) -#define PINMUX_PA16C_SERCOM1_PAD0 ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0) -#define PORT_PA16C_SERCOM1_PAD0 ((1UL) << 16) - -#define PIN_PC27C_SERCOM1_PAD0 (91L) -#define MUX_PC27C_SERCOM1_PAD0 (2L) -#define PINMUX_PC27C_SERCOM1_PAD0 ((PIN_PC27C_SERCOM1_PAD0 << 16) | MUX_PC27C_SERCOM1_PAD0) -#define PORT_PC27C_SERCOM1_PAD0 ((1UL) << 27) - -#define PIN_PA01D_SERCOM1_PAD1 (1L) -#define MUX_PA01D_SERCOM1_PAD1 (3L) -#define PINMUX_PA01D_SERCOM1_PAD1 ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1) -#define PORT_PA01D_SERCOM1_PAD1 ((1UL) << 1) - -#define PIN_PA17C_SERCOM1_PAD1 (17L) -#define MUX_PA17C_SERCOM1_PAD1 (2L) -#define PINMUX_PA17C_SERCOM1_PAD1 ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1) -#define PORT_PA17C_SERCOM1_PAD1 ((1UL) << 17) - -#define PIN_PC28C_SERCOM1_PAD1 (92L) -#define MUX_PC28C_SERCOM1_PAD1 (2L) -#define PINMUX_PC28C_SERCOM1_PAD1 ((PIN_PC28C_SERCOM1_PAD1 << 16) | MUX_PC28C_SERCOM1_PAD1) -#define PORT_PC28C_SERCOM1_PAD1 ((1UL) << 28) - -#define PIN_PA30D_SERCOM1_PAD2 (30L) -#define MUX_PA30D_SERCOM1_PAD2 (3L) -#define PINMUX_PA30D_SERCOM1_PAD2 ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2) -#define PORT_PA30D_SERCOM1_PAD2 ((1UL) << 30) - -#define PIN_PA18C_SERCOM1_PAD2 (18L) -#define MUX_PA18C_SERCOM1_PAD2 (2L) -#define PINMUX_PA18C_SERCOM1_PAD2 ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2) -#define PORT_PA18C_SERCOM1_PAD2 ((1UL) << 18) - -#define PIN_PB22C_SERCOM1_PAD2 (54L) -#define MUX_PB22C_SERCOM1_PAD2 (2L) -#define PINMUX_PB22C_SERCOM1_PAD2 ((PIN_PB22C_SERCOM1_PAD2 << 16) | MUX_PB22C_SERCOM1_PAD2) -#define PORT_PB22C_SERCOM1_PAD2 ((1UL) << 22) - -#define PIN_PA31D_SERCOM1_PAD3 (31L) -#define MUX_PA31D_SERCOM1_PAD3 (3L) -#define PINMUX_PA31D_SERCOM1_PAD3 ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3) -#define PORT_PA31D_SERCOM1_PAD3 ((1UL) << 31) - -#define PIN_PA19C_SERCOM1_PAD3 (19L) -#define MUX_PA19C_SERCOM1_PAD3 (2L) -#define PINMUX_PA19C_SERCOM1_PAD3 ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3) -#define PORT_PA19C_SERCOM1_PAD3 ((1UL) << 19) - -#define PIN_PB23C_SERCOM1_PAD3 (55L) -#define MUX_PB23C_SERCOM1_PAD3 (2L) -#define PINMUX_PB23C_SERCOM1_PAD3 ((PIN_PB23C_SERCOM1_PAD3 << 16) | MUX_PB23C_SERCOM1_PAD3) -#define PORT_PB23C_SERCOM1_PAD3 ((1UL) << 23) - -/* ========== PORT definition for SERCOM2 peripheral ========== */ -#define PIN_PA09D_SERCOM2_PAD0 (9L) -#define MUX_PA09D_SERCOM2_PAD0 (3L) -#define PINMUX_PA09D_SERCOM2_PAD0 ((PIN_PA09D_SERCOM2_PAD0 << 16) | MUX_PA09D_SERCOM2_PAD0) -#define PORT_PA09D_SERCOM2_PAD0 ((1UL) << 9) - -#define PIN_PB25D_SERCOM2_PAD0 (57L) -#define MUX_PB25D_SERCOM2_PAD0 (3L) -#define PINMUX_PB25D_SERCOM2_PAD0 ((PIN_PB25D_SERCOM2_PAD0 << 16) | MUX_PB25D_SERCOM2_PAD0) -#define PORT_PB25D_SERCOM2_PAD0 ((1UL) << 25) - -#define PIN_PA12C_SERCOM2_PAD0 (12L) -#define MUX_PA12C_SERCOM2_PAD0 (2L) -#define PINMUX_PA12C_SERCOM2_PAD0 ((PIN_PA12C_SERCOM2_PAD0 << 16) | MUX_PA12C_SERCOM2_PAD0) -#define PORT_PA12C_SERCOM2_PAD0 ((1UL) << 12) - -#define PIN_PA08D_SERCOM2_PAD1 (8L) -#define MUX_PA08D_SERCOM2_PAD1 (3L) -#define PINMUX_PA08D_SERCOM2_PAD1 ((PIN_PA08D_SERCOM2_PAD1 << 16) | MUX_PA08D_SERCOM2_PAD1) -#define PORT_PA08D_SERCOM2_PAD1 ((1UL) << 8) - -#define PIN_PB24D_SERCOM2_PAD1 (56L) -#define MUX_PB24D_SERCOM2_PAD1 (3L) -#define PINMUX_PB24D_SERCOM2_PAD1 ((PIN_PB24D_SERCOM2_PAD1 << 16) | MUX_PB24D_SERCOM2_PAD1) -#define PORT_PB24D_SERCOM2_PAD1 ((1UL) << 24) - -#define PIN_PA13C_SERCOM2_PAD1 (13L) -#define MUX_PA13C_SERCOM2_PAD1 (2L) -#define PINMUX_PA13C_SERCOM2_PAD1 ((PIN_PA13C_SERCOM2_PAD1 << 16) | MUX_PA13C_SERCOM2_PAD1) -#define PORT_PA13C_SERCOM2_PAD1 ((1UL) << 13) - -#define PIN_PA10D_SERCOM2_PAD2 (10L) -#define MUX_PA10D_SERCOM2_PAD2 (3L) -#define PINMUX_PA10D_SERCOM2_PAD2 ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2) -#define PORT_PA10D_SERCOM2_PAD2 ((1UL) << 10) - -#define PIN_PC24D_SERCOM2_PAD2 (88L) -#define MUX_PC24D_SERCOM2_PAD2 (3L) -#define PINMUX_PC24D_SERCOM2_PAD2 ((PIN_PC24D_SERCOM2_PAD2 << 16) | MUX_PC24D_SERCOM2_PAD2) -#define PORT_PC24D_SERCOM2_PAD2 ((1UL) << 24) - -#define PIN_PA14C_SERCOM2_PAD2 (14L) -#define MUX_PA14C_SERCOM2_PAD2 (2L) -#define PINMUX_PA14C_SERCOM2_PAD2 ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2) -#define PORT_PA14C_SERCOM2_PAD2 ((1UL) << 14) - -#define PIN_PA11D_SERCOM2_PAD3 (11L) -#define MUX_PA11D_SERCOM2_PAD3 (3L) -#define PINMUX_PA11D_SERCOM2_PAD3 ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3) -#define PORT_PA11D_SERCOM2_PAD3 ((1UL) << 11) - -#define PIN_PC25D_SERCOM2_PAD3 (89L) -#define MUX_PC25D_SERCOM2_PAD3 (3L) -#define PINMUX_PC25D_SERCOM2_PAD3 ((PIN_PC25D_SERCOM2_PAD3 << 16) | MUX_PC25D_SERCOM2_PAD3) -#define PORT_PC25D_SERCOM2_PAD3 ((1UL) << 25) - -#define PIN_PA15C_SERCOM2_PAD3 (15L) -#define MUX_PA15C_SERCOM2_PAD3 (2L) -#define PINMUX_PA15C_SERCOM2_PAD3 ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3) -#define PORT_PA15C_SERCOM2_PAD3 ((1UL) << 15) - -/* ========== PORT definition for SERCOM3 peripheral ========== */ -#define PIN_PA17D_SERCOM3_PAD0 (17L) -#define MUX_PA17D_SERCOM3_PAD0 (3L) -#define PINMUX_PA17D_SERCOM3_PAD0 ((PIN_PA17D_SERCOM3_PAD0 << 16) | MUX_PA17D_SERCOM3_PAD0) -#define PORT_PA17D_SERCOM3_PAD0 ((1UL) << 17) - -#define PIN_PA22C_SERCOM3_PAD0 (22L) -#define MUX_PA22C_SERCOM3_PAD0 (2L) -#define PINMUX_PA22C_SERCOM3_PAD0 ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0) -#define PORT_PA22C_SERCOM3_PAD0 ((1UL) << 22) - -#define PIN_PB20C_SERCOM3_PAD0 (52L) -#define MUX_PB20C_SERCOM3_PAD0 (2L) -#define PINMUX_PB20C_SERCOM3_PAD0 ((PIN_PB20C_SERCOM3_PAD0 << 16) | MUX_PB20C_SERCOM3_PAD0) -#define PORT_PB20C_SERCOM3_PAD0 ((1UL) << 20) - -#define PIN_PA16D_SERCOM3_PAD1 (16L) -#define MUX_PA16D_SERCOM3_PAD1 (3L) -#define PINMUX_PA16D_SERCOM3_PAD1 ((PIN_PA16D_SERCOM3_PAD1 << 16) | MUX_PA16D_SERCOM3_PAD1) -#define PORT_PA16D_SERCOM3_PAD1 ((1UL) << 16) - -#define PIN_PA23C_SERCOM3_PAD1 (23L) -#define MUX_PA23C_SERCOM3_PAD1 (2L) -#define PINMUX_PA23C_SERCOM3_PAD1 ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1) -#define PORT_PA23C_SERCOM3_PAD1 ((1UL) << 23) - -#define PIN_PB21C_SERCOM3_PAD1 (53L) -#define MUX_PB21C_SERCOM3_PAD1 (2L) -#define PINMUX_PB21C_SERCOM3_PAD1 ((PIN_PB21C_SERCOM3_PAD1 << 16) | MUX_PB21C_SERCOM3_PAD1) -#define PORT_PB21C_SERCOM3_PAD1 ((1UL) << 21) - -#define PIN_PA18D_SERCOM3_PAD2 (18L) -#define MUX_PA18D_SERCOM3_PAD2 (3L) -#define PINMUX_PA18D_SERCOM3_PAD2 ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2) -#define PORT_PA18D_SERCOM3_PAD2 ((1UL) << 18) - -#define PIN_PA20D_SERCOM3_PAD2 (20L) -#define MUX_PA20D_SERCOM3_PAD2 (3L) -#define PINMUX_PA20D_SERCOM3_PAD2 ((PIN_PA20D_SERCOM3_PAD2 << 16) | MUX_PA20D_SERCOM3_PAD2) -#define PORT_PA20D_SERCOM3_PAD2 ((1UL) << 20) - -#define PIN_PA24C_SERCOM3_PAD2 (24L) -#define MUX_PA24C_SERCOM3_PAD2 (2L) -#define PINMUX_PA24C_SERCOM3_PAD2 ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2) -#define PORT_PA24C_SERCOM3_PAD2 ((1UL) << 24) - -#define PIN_PA19D_SERCOM3_PAD3 (19L) -#define MUX_PA19D_SERCOM3_PAD3 (3L) -#define PINMUX_PA19D_SERCOM3_PAD3 ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3) -#define PORT_PA19D_SERCOM3_PAD3 ((1UL) << 19) - -#define PIN_PA21D_SERCOM3_PAD3 (21L) -#define MUX_PA21D_SERCOM3_PAD3 (3L) -#define PINMUX_PA21D_SERCOM3_PAD3 ((PIN_PA21D_SERCOM3_PAD3 << 16) | MUX_PA21D_SERCOM3_PAD3) -#define PORT_PA21D_SERCOM3_PAD3 ((1UL) << 21) - -#define PIN_PA25C_SERCOM3_PAD3 (25L) -#define MUX_PA25C_SERCOM3_PAD3 (2L) -#define PINMUX_PA25C_SERCOM3_PAD3 ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3) -#define PORT_PA25C_SERCOM3_PAD3 ((1UL) << 25) - -/* ========== PORT definition for SERCOM4 peripheral ========== */ -#define PIN_PA13D_SERCOM4_PAD0 (13L) -#define MUX_PA13D_SERCOM4_PAD0 (3L) -#define PINMUX_PA13D_SERCOM4_PAD0 ((PIN_PA13D_SERCOM4_PAD0 << 16) | MUX_PA13D_SERCOM4_PAD0) -#define PORT_PA13D_SERCOM4_PAD0 ((1UL) << 13) - -#define PIN_PB08D_SERCOM4_PAD0 (40L) -#define MUX_PB08D_SERCOM4_PAD0 (3L) -#define PINMUX_PB08D_SERCOM4_PAD0 ((PIN_PB08D_SERCOM4_PAD0 << 16) | MUX_PB08D_SERCOM4_PAD0) -#define PORT_PB08D_SERCOM4_PAD0 ((1UL) << 8) - -#define PIN_PB12C_SERCOM4_PAD0 (44L) -#define MUX_PB12C_SERCOM4_PAD0 (2L) -#define PINMUX_PB12C_SERCOM4_PAD0 ((PIN_PB12C_SERCOM4_PAD0 << 16) | MUX_PB12C_SERCOM4_PAD0) -#define PORT_PB12C_SERCOM4_PAD0 ((1UL) << 12) - -#define PIN_PA12D_SERCOM4_PAD1 (12L) -#define MUX_PA12D_SERCOM4_PAD1 (3L) -#define PINMUX_PA12D_SERCOM4_PAD1 ((PIN_PA12D_SERCOM4_PAD1 << 16) | MUX_PA12D_SERCOM4_PAD1) -#define PORT_PA12D_SERCOM4_PAD1 ((1UL) << 12) - -#define PIN_PB09D_SERCOM4_PAD1 (41L) -#define MUX_PB09D_SERCOM4_PAD1 (3L) -#define PINMUX_PB09D_SERCOM4_PAD1 ((PIN_PB09D_SERCOM4_PAD1 << 16) | MUX_PB09D_SERCOM4_PAD1) -#define PORT_PB09D_SERCOM4_PAD1 ((1UL) << 9) - -#define PIN_PB13C_SERCOM4_PAD1 (45L) -#define MUX_PB13C_SERCOM4_PAD1 (2L) -#define PINMUX_PB13C_SERCOM4_PAD1 ((PIN_PB13C_SERCOM4_PAD1 << 16) | MUX_PB13C_SERCOM4_PAD1) -#define PORT_PB13C_SERCOM4_PAD1 ((1UL) << 13) - -#define PIN_PA14D_SERCOM4_PAD2 (14L) -#define MUX_PA14D_SERCOM4_PAD2 (3L) -#define PINMUX_PA14D_SERCOM4_PAD2 ((PIN_PA14D_SERCOM4_PAD2 << 16) | MUX_PA14D_SERCOM4_PAD2) -#define PORT_PA14D_SERCOM4_PAD2 ((1UL) << 14) - -#define PIN_PB10D_SERCOM4_PAD2 (42L) -#define MUX_PB10D_SERCOM4_PAD2 (3L) -#define PINMUX_PB10D_SERCOM4_PAD2 ((PIN_PB10D_SERCOM4_PAD2 << 16) | MUX_PB10D_SERCOM4_PAD2) -#define PORT_PB10D_SERCOM4_PAD2 ((1UL) << 10) - -#define PIN_PB14C_SERCOM4_PAD2 (46L) -#define MUX_PB14C_SERCOM4_PAD2 (2L) -#define PINMUX_PB14C_SERCOM4_PAD2 ((PIN_PB14C_SERCOM4_PAD2 << 16) | MUX_PB14C_SERCOM4_PAD2) -#define PORT_PB14C_SERCOM4_PAD2 ((1UL) << 14) - -#define PIN_PB11D_SERCOM4_PAD3 (43L) -#define MUX_PB11D_SERCOM4_PAD3 (3L) -#define PINMUX_PB11D_SERCOM4_PAD3 ((PIN_PB11D_SERCOM4_PAD3 << 16) | MUX_PB11D_SERCOM4_PAD3) -#define PORT_PB11D_SERCOM4_PAD3 ((1UL) << 11) - -#define PIN_PA15D_SERCOM4_PAD3 (15L) -#define MUX_PA15D_SERCOM4_PAD3 (3L) -#define PINMUX_PA15D_SERCOM4_PAD3 ((PIN_PA15D_SERCOM4_PAD3 << 16) | MUX_PA15D_SERCOM4_PAD3) -#define PORT_PA15D_SERCOM4_PAD3 ((1UL) << 15) - -#define PIN_PB15C_SERCOM4_PAD3 (47L) -#define MUX_PB15C_SERCOM4_PAD3 (2L) -#define PINMUX_PB15C_SERCOM4_PAD3 ((PIN_PB15C_SERCOM4_PAD3 << 16) | MUX_PB15C_SERCOM4_PAD3) -#define PORT_PB15C_SERCOM4_PAD3 ((1UL) << 15) - -/* ========== PORT definition for SERCOM5 peripheral ========== */ -#define PIN_PA23D_SERCOM5_PAD0 (23L) -#define MUX_PA23D_SERCOM5_PAD0 (3L) -#define PINMUX_PA23D_SERCOM5_PAD0 ((PIN_PA23D_SERCOM5_PAD0 << 16) | MUX_PA23D_SERCOM5_PAD0) -#define PORT_PA23D_SERCOM5_PAD0 ((1UL) << 23) - -#define PIN_PB02D_SERCOM5_PAD0 (34L) -#define MUX_PB02D_SERCOM5_PAD0 (3L) -#define PINMUX_PB02D_SERCOM5_PAD0 ((PIN_PB02D_SERCOM5_PAD0 << 16) | MUX_PB02D_SERCOM5_PAD0) -#define PORT_PB02D_SERCOM5_PAD0 ((1UL) << 2) - -#define PIN_PB31D_SERCOM5_PAD0 (63L) -#define MUX_PB31D_SERCOM5_PAD0 (3L) -#define PINMUX_PB31D_SERCOM5_PAD0 ((PIN_PB31D_SERCOM5_PAD0 << 16) | MUX_PB31D_SERCOM5_PAD0) -#define PORT_PB31D_SERCOM5_PAD0 ((1UL) << 31) - -#define PIN_PB16C_SERCOM5_PAD0 (48L) -#define MUX_PB16C_SERCOM5_PAD0 (2L) -#define PINMUX_PB16C_SERCOM5_PAD0 ((PIN_PB16C_SERCOM5_PAD0 << 16) | MUX_PB16C_SERCOM5_PAD0) -#define PORT_PB16C_SERCOM5_PAD0 ((1UL) << 16) - -#define PIN_PA22D_SERCOM5_PAD1 (22L) -#define MUX_PA22D_SERCOM5_PAD1 (3L) -#define PINMUX_PA22D_SERCOM5_PAD1 ((PIN_PA22D_SERCOM5_PAD1 << 16) | MUX_PA22D_SERCOM5_PAD1) -#define PORT_PA22D_SERCOM5_PAD1 ((1UL) << 22) - -#define PIN_PB03D_SERCOM5_PAD1 (35L) -#define MUX_PB03D_SERCOM5_PAD1 (3L) -#define PINMUX_PB03D_SERCOM5_PAD1 ((PIN_PB03D_SERCOM5_PAD1 << 16) | MUX_PB03D_SERCOM5_PAD1) -#define PORT_PB03D_SERCOM5_PAD1 ((1UL) << 3) - -#define PIN_PB30D_SERCOM5_PAD1 (62L) -#define MUX_PB30D_SERCOM5_PAD1 (3L) -#define PINMUX_PB30D_SERCOM5_PAD1 ((PIN_PB30D_SERCOM5_PAD1 << 16) | MUX_PB30D_SERCOM5_PAD1) -#define PORT_PB30D_SERCOM5_PAD1 ((1UL) << 30) - -#define PIN_PB17C_SERCOM5_PAD1 (49L) -#define MUX_PB17C_SERCOM5_PAD1 (2L) -#define PINMUX_PB17C_SERCOM5_PAD1 ((PIN_PB17C_SERCOM5_PAD1 << 16) | MUX_PB17C_SERCOM5_PAD1) -#define PORT_PB17C_SERCOM5_PAD1 ((1UL) << 17) - -#define PIN_PA24D_SERCOM5_PAD2 (24L) -#define MUX_PA24D_SERCOM5_PAD2 (3L) -#define PINMUX_PA24D_SERCOM5_PAD2 ((PIN_PA24D_SERCOM5_PAD2 << 16) | MUX_PA24D_SERCOM5_PAD2) -#define PORT_PA24D_SERCOM5_PAD2 ((1UL) << 24) - -#define PIN_PB00D_SERCOM5_PAD2 (32L) -#define MUX_PB00D_SERCOM5_PAD2 (3L) -#define PINMUX_PB00D_SERCOM5_PAD2 ((PIN_PB00D_SERCOM5_PAD2 << 16) | MUX_PB00D_SERCOM5_PAD2) -#define PORT_PB00D_SERCOM5_PAD2 ((1UL) << 0) - -#define PIN_PB22D_SERCOM5_PAD2 (54L) -#define MUX_PB22D_SERCOM5_PAD2 (3L) -#define PINMUX_PB22D_SERCOM5_PAD2 ((PIN_PB22D_SERCOM5_PAD2 << 16) | MUX_PB22D_SERCOM5_PAD2) -#define PORT_PB22D_SERCOM5_PAD2 ((1UL) << 22) - -#define PIN_PA20C_SERCOM5_PAD2 (20L) -#define MUX_PA20C_SERCOM5_PAD2 (2L) -#define PINMUX_PA20C_SERCOM5_PAD2 ((PIN_PA20C_SERCOM5_PAD2 << 16) | MUX_PA20C_SERCOM5_PAD2) -#define PORT_PA20C_SERCOM5_PAD2 ((1UL) << 20) - -#define PIN_PB18C_SERCOM5_PAD2 (50L) -#define MUX_PB18C_SERCOM5_PAD2 (2L) -#define PINMUX_PB18C_SERCOM5_PAD2 ((PIN_PB18C_SERCOM5_PAD2 << 16) | MUX_PB18C_SERCOM5_PAD2) -#define PORT_PB18C_SERCOM5_PAD2 ((1UL) << 18) - -#define PIN_PA25D_SERCOM5_PAD3 (25L) -#define MUX_PA25D_SERCOM5_PAD3 (3L) -#define PINMUX_PA25D_SERCOM5_PAD3 ((PIN_PA25D_SERCOM5_PAD3 << 16) | MUX_PA25D_SERCOM5_PAD3) -#define PORT_PA25D_SERCOM5_PAD3 ((1UL) << 25) - -#define PIN_PB01D_SERCOM5_PAD3 (33L) -#define MUX_PB01D_SERCOM5_PAD3 (3L) -#define PINMUX_PB01D_SERCOM5_PAD3 ((PIN_PB01D_SERCOM5_PAD3 << 16) | MUX_PB01D_SERCOM5_PAD3) -#define PORT_PB01D_SERCOM5_PAD3 ((1UL) << 1) - -#define PIN_PB23D_SERCOM5_PAD3 (55L) -#define MUX_PB23D_SERCOM5_PAD3 (3L) -#define PINMUX_PB23D_SERCOM5_PAD3 ((PIN_PB23D_SERCOM5_PAD3 << 16) | MUX_PB23D_SERCOM5_PAD3) -#define PORT_PB23D_SERCOM5_PAD3 ((1UL) << 23) - -#define PIN_PA21C_SERCOM5_PAD3 (21L) -#define MUX_PA21C_SERCOM5_PAD3 (2L) -#define PINMUX_PA21C_SERCOM5_PAD3 ((PIN_PA21C_SERCOM5_PAD3 << 16) | MUX_PA21C_SERCOM5_PAD3) -#define PORT_PA21C_SERCOM5_PAD3 ((1UL) << 21) - -#define PIN_PB19C_SERCOM5_PAD3 (51L) -#define MUX_PB19C_SERCOM5_PAD3 (2L) -#define PINMUX_PB19C_SERCOM5_PAD3 ((PIN_PB19C_SERCOM5_PAD3 << 16) | MUX_PB19C_SERCOM5_PAD3) -#define PORT_PB19C_SERCOM5_PAD3 ((1UL) << 19) - -/* ========== PORT definition for SERCOM6 peripheral ========== */ -#define PIN_PC13D_SERCOM6_PAD0 (77L) -#define MUX_PC13D_SERCOM6_PAD0 (3L) -#define PINMUX_PC13D_SERCOM6_PAD0 ((PIN_PC13D_SERCOM6_PAD0 << 16) | MUX_PC13D_SERCOM6_PAD0) -#define PORT_PC13D_SERCOM6_PAD0 ((1UL) << 13) - -#define PIN_PC16C_SERCOM6_PAD0 (80L) -#define MUX_PC16C_SERCOM6_PAD0 (2L) -#define PINMUX_PC16C_SERCOM6_PAD0 ((PIN_PC16C_SERCOM6_PAD0 << 16) | MUX_PC16C_SERCOM6_PAD0) -#define PORT_PC16C_SERCOM6_PAD0 ((1UL) << 16) - -#define PIN_PC12D_SERCOM6_PAD1 (76L) -#define MUX_PC12D_SERCOM6_PAD1 (3L) -#define PINMUX_PC12D_SERCOM6_PAD1 ((PIN_PC12D_SERCOM6_PAD1 << 16) | MUX_PC12D_SERCOM6_PAD1) -#define PORT_PC12D_SERCOM6_PAD1 ((1UL) << 12) - -#define PIN_PC05C_SERCOM6_PAD1 (69L) -#define MUX_PC05C_SERCOM6_PAD1 (2L) -#define PINMUX_PC05C_SERCOM6_PAD1 ((PIN_PC05C_SERCOM6_PAD1 << 16) | MUX_PC05C_SERCOM6_PAD1) -#define PORT_PC05C_SERCOM6_PAD1 ((1UL) << 5) - -#define PIN_PC17C_SERCOM6_PAD1 (81L) -#define MUX_PC17C_SERCOM6_PAD1 (2L) -#define PINMUX_PC17C_SERCOM6_PAD1 ((PIN_PC17C_SERCOM6_PAD1 << 16) | MUX_PC17C_SERCOM6_PAD1) -#define PORT_PC17C_SERCOM6_PAD1 ((1UL) << 17) - -#define PIN_PC14D_SERCOM6_PAD2 (78L) -#define MUX_PC14D_SERCOM6_PAD2 (3L) -#define PINMUX_PC14D_SERCOM6_PAD2 ((PIN_PC14D_SERCOM6_PAD2 << 16) | MUX_PC14D_SERCOM6_PAD2) -#define PORT_PC14D_SERCOM6_PAD2 ((1UL) << 14) - -#define PIN_PC06C_SERCOM6_PAD2 (70L) -#define MUX_PC06C_SERCOM6_PAD2 (2L) -#define PINMUX_PC06C_SERCOM6_PAD2 ((PIN_PC06C_SERCOM6_PAD2 << 16) | MUX_PC06C_SERCOM6_PAD2) -#define PORT_PC06C_SERCOM6_PAD2 ((1UL) << 6) - -#define PIN_PC10C_SERCOM6_PAD2 (74L) -#define MUX_PC10C_SERCOM6_PAD2 (2L) -#define PINMUX_PC10C_SERCOM6_PAD2 ((PIN_PC10C_SERCOM6_PAD2 << 16) | MUX_PC10C_SERCOM6_PAD2) -#define PORT_PC10C_SERCOM6_PAD2 ((1UL) << 10) - -#define PIN_PC18C_SERCOM6_PAD2 (82L) -#define MUX_PC18C_SERCOM6_PAD2 (2L) -#define PINMUX_PC18C_SERCOM6_PAD2 ((PIN_PC18C_SERCOM6_PAD2 << 16) | MUX_PC18C_SERCOM6_PAD2) -#define PORT_PC18C_SERCOM6_PAD2 ((1UL) << 18) - -#define PIN_PC15D_SERCOM6_PAD3 (79L) -#define MUX_PC15D_SERCOM6_PAD3 (3L) -#define PINMUX_PC15D_SERCOM6_PAD3 ((PIN_PC15D_SERCOM6_PAD3 << 16) | MUX_PC15D_SERCOM6_PAD3) -#define PORT_PC15D_SERCOM6_PAD3 ((1UL) << 15) - -#define PIN_PC07C_SERCOM6_PAD3 (71L) -#define MUX_PC07C_SERCOM6_PAD3 (2L) -#define PINMUX_PC07C_SERCOM6_PAD3 ((PIN_PC07C_SERCOM6_PAD3 << 16) | MUX_PC07C_SERCOM6_PAD3) -#define PORT_PC07C_SERCOM6_PAD3 ((1UL) << 7) - -#define PIN_PC11C_SERCOM6_PAD3 (75L) -#define MUX_PC11C_SERCOM6_PAD3 (2L) -#define PINMUX_PC11C_SERCOM6_PAD3 ((PIN_PC11C_SERCOM6_PAD3 << 16) | MUX_PC11C_SERCOM6_PAD3) -#define PORT_PC11C_SERCOM6_PAD3 ((1UL) << 11) - -#define PIN_PC19C_SERCOM6_PAD3 (83L) -#define MUX_PC19C_SERCOM6_PAD3 (2L) -#define PINMUX_PC19C_SERCOM6_PAD3 ((PIN_PC19C_SERCOM6_PAD3 << 16) | MUX_PC19C_SERCOM6_PAD3) -#define PORT_PC19C_SERCOM6_PAD3 ((1UL) << 19) - -/* ========== PORT definition for SERCOM7 peripheral ========== */ -#define PIN_PB21D_SERCOM7_PAD0 (53L) -#define MUX_PB21D_SERCOM7_PAD0 (3L) -#define PINMUX_PB21D_SERCOM7_PAD0 ((PIN_PB21D_SERCOM7_PAD0 << 16) | MUX_PB21D_SERCOM7_PAD0) -#define PORT_PB21D_SERCOM7_PAD0 ((1UL) << 21) - -#define PIN_PB30C_SERCOM7_PAD0 (62L) -#define MUX_PB30C_SERCOM7_PAD0 (2L) -#define PINMUX_PB30C_SERCOM7_PAD0 ((PIN_PB30C_SERCOM7_PAD0 << 16) | MUX_PB30C_SERCOM7_PAD0) -#define PORT_PB30C_SERCOM7_PAD0 ((1UL) << 30) - -#define PIN_PC12C_SERCOM7_PAD0 (76L) -#define MUX_PC12C_SERCOM7_PAD0 (2L) -#define PINMUX_PC12C_SERCOM7_PAD0 ((PIN_PC12C_SERCOM7_PAD0 << 16) | MUX_PC12C_SERCOM7_PAD0) -#define PORT_PC12C_SERCOM7_PAD0 ((1UL) << 12) - -#define PIN_PB20D_SERCOM7_PAD1 (52L) -#define MUX_PB20D_SERCOM7_PAD1 (3L) -#define PINMUX_PB20D_SERCOM7_PAD1 ((PIN_PB20D_SERCOM7_PAD1 << 16) | MUX_PB20D_SERCOM7_PAD1) -#define PORT_PB20D_SERCOM7_PAD1 ((1UL) << 20) - -#define PIN_PB31C_SERCOM7_PAD1 (63L) -#define MUX_PB31C_SERCOM7_PAD1 (2L) -#define PINMUX_PB31C_SERCOM7_PAD1 ((PIN_PB31C_SERCOM7_PAD1 << 16) | MUX_PB31C_SERCOM7_PAD1) -#define PORT_PB31C_SERCOM7_PAD1 ((1UL) << 31) - -#define PIN_PC13C_SERCOM7_PAD1 (77L) -#define MUX_PC13C_SERCOM7_PAD1 (2L) -#define PINMUX_PC13C_SERCOM7_PAD1 ((PIN_PC13C_SERCOM7_PAD1 << 16) | MUX_PC13C_SERCOM7_PAD1) -#define PORT_PC13C_SERCOM7_PAD1 ((1UL) << 13) - -#define PIN_PB18D_SERCOM7_PAD2 (50L) -#define MUX_PB18D_SERCOM7_PAD2 (3L) -#define PINMUX_PB18D_SERCOM7_PAD2 ((PIN_PB18D_SERCOM7_PAD2 << 16) | MUX_PB18D_SERCOM7_PAD2) -#define PORT_PB18D_SERCOM7_PAD2 ((1UL) << 18) - -#define PIN_PC10D_SERCOM7_PAD2 (74L) -#define MUX_PC10D_SERCOM7_PAD2 (3L) -#define PINMUX_PC10D_SERCOM7_PAD2 ((PIN_PC10D_SERCOM7_PAD2 << 16) | MUX_PC10D_SERCOM7_PAD2) -#define PORT_PC10D_SERCOM7_PAD2 ((1UL) << 10) - -#define PIN_PC14C_SERCOM7_PAD2 (78L) -#define MUX_PC14C_SERCOM7_PAD2 (2L) -#define PINMUX_PC14C_SERCOM7_PAD2 ((PIN_PC14C_SERCOM7_PAD2 << 16) | MUX_PC14C_SERCOM7_PAD2) -#define PORT_PC14C_SERCOM7_PAD2 ((1UL) << 14) - -#define PIN_PA30C_SERCOM7_PAD2 (30L) -#define MUX_PA30C_SERCOM7_PAD2 (2L) -#define PINMUX_PA30C_SERCOM7_PAD2 ((PIN_PA30C_SERCOM7_PAD2 << 16) | MUX_PA30C_SERCOM7_PAD2) -#define PORT_PA30C_SERCOM7_PAD2 ((1UL) << 30) - -#define PIN_PB19D_SERCOM7_PAD3 (51L) -#define MUX_PB19D_SERCOM7_PAD3 (3L) -#define PINMUX_PB19D_SERCOM7_PAD3 ((PIN_PB19D_SERCOM7_PAD3 << 16) | MUX_PB19D_SERCOM7_PAD3) -#define PORT_PB19D_SERCOM7_PAD3 ((1UL) << 19) - -#define PIN_PC11D_SERCOM7_PAD3 (75L) -#define MUX_PC11D_SERCOM7_PAD3 (3L) -#define PINMUX_PC11D_SERCOM7_PAD3 ((PIN_PC11D_SERCOM7_PAD3 << 16) | MUX_PC11D_SERCOM7_PAD3) -#define PORT_PC11D_SERCOM7_PAD3 ((1UL) << 11) - -#define PIN_PC15C_SERCOM7_PAD3 (79L) -#define MUX_PC15C_SERCOM7_PAD3 (2L) -#define PINMUX_PC15C_SERCOM7_PAD3 ((PIN_PC15C_SERCOM7_PAD3 << 16) | MUX_PC15C_SERCOM7_PAD3) -#define PORT_PC15C_SERCOM7_PAD3 ((1UL) << 15) - -#define PIN_PA31C_SERCOM7_PAD3 (31L) -#define MUX_PA31C_SERCOM7_PAD3 (2L) -#define PINMUX_PA31C_SERCOM7_PAD3 ((PIN_PA31C_SERCOM7_PAD3 << 16) | MUX_PA31C_SERCOM7_PAD3) -#define PORT_PA31C_SERCOM7_PAD3 ((1UL) << 31) - -/* ========== PORT definition for TC0 peripheral ========== */ -#define PIN_PA04E_TC0_WO0 (4L) -#define MUX_PA04E_TC0_WO0 (4L) -#define PINMUX_PA04E_TC0_WO0 ((PIN_PA04E_TC0_WO0 << 16) | MUX_PA04E_TC0_WO0) -#define PORT_PA04E_TC0_WO0 ((1UL) << 4) - -#define PIN_PA08E_TC0_WO0 (8L) -#define MUX_PA08E_TC0_WO0 (4L) -#define PINMUX_PA08E_TC0_WO0 ((PIN_PA08E_TC0_WO0 << 16) | MUX_PA08E_TC0_WO0) -#define PORT_PA08E_TC0_WO0 ((1UL) << 8) - -#define PIN_PB30E_TC0_WO0 (62L) -#define MUX_PB30E_TC0_WO0 (4L) -#define PINMUX_PB30E_TC0_WO0 ((PIN_PB30E_TC0_WO0 << 16) | MUX_PB30E_TC0_WO0) -#define PORT_PB30E_TC0_WO0 ((1UL) << 30) - -#define PIN_PA05E_TC0_WO1 (5L) -#define MUX_PA05E_TC0_WO1 (4L) -#define PINMUX_PA05E_TC0_WO1 ((PIN_PA05E_TC0_WO1 << 16) | MUX_PA05E_TC0_WO1) -#define PORT_PA05E_TC0_WO1 ((1UL) << 5) - -#define PIN_PA09E_TC0_WO1 (9L) -#define MUX_PA09E_TC0_WO1 (4L) -#define PINMUX_PA09E_TC0_WO1 ((PIN_PA09E_TC0_WO1 << 16) | MUX_PA09E_TC0_WO1) -#define PORT_PA09E_TC0_WO1 ((1UL) << 9) - -#define PIN_PB31E_TC0_WO1 (63L) -#define MUX_PB31E_TC0_WO1 (4L) -#define PINMUX_PB31E_TC0_WO1 ((PIN_PB31E_TC0_WO1 << 16) | MUX_PB31E_TC0_WO1) -#define PORT_PB31E_TC0_WO1 ((1UL) << 31) - -/* ========== PORT definition for TC1 peripheral ========== */ -#define PIN_PA06E_TC1_WO0 (6L) -#define MUX_PA06E_TC1_WO0 (4L) -#define PINMUX_PA06E_TC1_WO0 ((PIN_PA06E_TC1_WO0 << 16) | MUX_PA06E_TC1_WO0) -#define PORT_PA06E_TC1_WO0 ((1UL) << 6) - -#define PIN_PA10E_TC1_WO0 (10L) -#define MUX_PA10E_TC1_WO0 (4L) -#define PINMUX_PA10E_TC1_WO0 ((PIN_PA10E_TC1_WO0 << 16) | MUX_PA10E_TC1_WO0) -#define PORT_PA10E_TC1_WO0 ((1UL) << 10) - -#define PIN_PA07E_TC1_WO1 (7L) -#define MUX_PA07E_TC1_WO1 (4L) -#define PINMUX_PA07E_TC1_WO1 ((PIN_PA07E_TC1_WO1 << 16) | MUX_PA07E_TC1_WO1) -#define PORT_PA07E_TC1_WO1 ((1UL) << 7) - -#define PIN_PA11E_TC1_WO1 (11L) -#define MUX_PA11E_TC1_WO1 (4L) -#define PINMUX_PA11E_TC1_WO1 ((PIN_PA11E_TC1_WO1 << 16) | MUX_PA11E_TC1_WO1) -#define PORT_PA11E_TC1_WO1 ((1UL) << 11) - -/* ========== PORT definition for TC2 peripheral ========== */ -#define PIN_PA12E_TC2_WO0 (12L) -#define MUX_PA12E_TC2_WO0 (4L) -#define PINMUX_PA12E_TC2_WO0 ((PIN_PA12E_TC2_WO0 << 16) | MUX_PA12E_TC2_WO0) -#define PORT_PA12E_TC2_WO0 ((1UL) << 12) - -#define PIN_PA16E_TC2_WO0 (16L) -#define MUX_PA16E_TC2_WO0 (4L) -#define PINMUX_PA16E_TC2_WO0 ((PIN_PA16E_TC2_WO0 << 16) | MUX_PA16E_TC2_WO0) -#define PORT_PA16E_TC2_WO0 ((1UL) << 16) - -#define PIN_PA00E_TC2_WO0 (0L) -#define MUX_PA00E_TC2_WO0 (4L) -#define PINMUX_PA00E_TC2_WO0 ((PIN_PA00E_TC2_WO0 << 16) | MUX_PA00E_TC2_WO0) -#define PORT_PA00E_TC2_WO0 ((1UL) << 0) - -#define PIN_PA01E_TC2_WO1 (1L) -#define MUX_PA01E_TC2_WO1 (4L) -#define PINMUX_PA01E_TC2_WO1 ((PIN_PA01E_TC2_WO1 << 16) | MUX_PA01E_TC2_WO1) -#define PORT_PA01E_TC2_WO1 ((1UL) << 1) - -#define PIN_PA13E_TC2_WO1 (13L) -#define MUX_PA13E_TC2_WO1 (4L) -#define PINMUX_PA13E_TC2_WO1 ((PIN_PA13E_TC2_WO1 << 16) | MUX_PA13E_TC2_WO1) -#define PORT_PA13E_TC2_WO1 ((1UL) << 13) - -#define PIN_PA17E_TC2_WO1 (17L) -#define MUX_PA17E_TC2_WO1 (4L) -#define PINMUX_PA17E_TC2_WO1 ((PIN_PA17E_TC2_WO1 << 16) | MUX_PA17E_TC2_WO1) -#define PORT_PA17E_TC2_WO1 ((1UL) << 17) - -/* ========== PORT definition for TC3 peripheral ========== */ -#define PIN_PA18E_TC3_WO0 (18L) -#define MUX_PA18E_TC3_WO0 (4L) -#define PINMUX_PA18E_TC3_WO0 ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0) -#define PORT_PA18E_TC3_WO0 ((1UL) << 18) - -#define PIN_PA14E_TC3_WO0 (14L) -#define MUX_PA14E_TC3_WO0 (4L) -#define PINMUX_PA14E_TC3_WO0 ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0) -#define PORT_PA14E_TC3_WO0 ((1UL) << 14) - -#define PIN_PA15E_TC3_WO1 (15L) -#define MUX_PA15E_TC3_WO1 (4L) -#define PINMUX_PA15E_TC3_WO1 ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1) -#define PORT_PA15E_TC3_WO1 ((1UL) << 15) - -#define PIN_PA19E_TC3_WO1 (19L) -#define MUX_PA19E_TC3_WO1 (4L) -#define PINMUX_PA19E_TC3_WO1 ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1) -#define PORT_PA19E_TC3_WO1 ((1UL) << 19) - -/* ========== PORT definition for TC4 peripheral ========== */ -#define PIN_PA22E_TC4_WO0 (22L) -#define MUX_PA22E_TC4_WO0 (4L) -#define PINMUX_PA22E_TC4_WO0 ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0) -#define PORT_PA22E_TC4_WO0 ((1UL) << 22) - -#define PIN_PB08E_TC4_WO0 (40L) -#define MUX_PB08E_TC4_WO0 (4L) -#define PINMUX_PB08E_TC4_WO0 ((PIN_PB08E_TC4_WO0 << 16) | MUX_PB08E_TC4_WO0) -#define PORT_PB08E_TC4_WO0 ((1UL) << 8) - -#define PIN_PB12E_TC4_WO0 (44L) -#define MUX_PB12E_TC4_WO0 (4L) -#define PINMUX_PB12E_TC4_WO0 ((PIN_PB12E_TC4_WO0 << 16) | MUX_PB12E_TC4_WO0) -#define PORT_PB12E_TC4_WO0 ((1UL) << 12) - -#define PIN_PA23E_TC4_WO1 (23L) -#define MUX_PA23E_TC4_WO1 (4L) -#define PINMUX_PA23E_TC4_WO1 ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1) -#define PORT_PA23E_TC4_WO1 ((1UL) << 23) - -#define PIN_PB09E_TC4_WO1 (41L) -#define MUX_PB09E_TC4_WO1 (4L) -#define PINMUX_PB09E_TC4_WO1 ((PIN_PB09E_TC4_WO1 << 16) | MUX_PB09E_TC4_WO1) -#define PORT_PB09E_TC4_WO1 ((1UL) << 9) - -#define PIN_PB13E_TC4_WO1 (45L) -#define MUX_PB13E_TC4_WO1 (4L) -#define PINMUX_PB13E_TC4_WO1 ((PIN_PB13E_TC4_WO1 << 16) | MUX_PB13E_TC4_WO1) -#define PORT_PB13E_TC4_WO1 ((1UL) << 13) - -/* ========== PORT definition for TC5 peripheral ========== */ -#define PIN_PA24E_TC5_WO0 (24L) -#define MUX_PA24E_TC5_WO0 (4L) -#define PINMUX_PA24E_TC5_WO0 ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0) -#define PORT_PA24E_TC5_WO0 ((1UL) << 24) - -#define PIN_PB10E_TC5_WO0 (42L) -#define MUX_PB10E_TC5_WO0 (4L) -#define PINMUX_PB10E_TC5_WO0 ((PIN_PB10E_TC5_WO0 << 16) | MUX_PB10E_TC5_WO0) -#define PORT_PB10E_TC5_WO0 ((1UL) << 10) - -#define PIN_PB14E_TC5_WO0 (46L) -#define MUX_PB14E_TC5_WO0 (4L) -#define PINMUX_PB14E_TC5_WO0 ((PIN_PB14E_TC5_WO0 << 16) | MUX_PB14E_TC5_WO0) -#define PORT_PB14E_TC5_WO0 ((1UL) << 14) - -#define PIN_PA25E_TC5_WO1 (25L) -#define MUX_PA25E_TC5_WO1 (4L) -#define PINMUX_PA25E_TC5_WO1 ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1) -#define PORT_PA25E_TC5_WO1 ((1UL) << 25) - -#define PIN_PB11E_TC5_WO1 (43L) -#define MUX_PB11E_TC5_WO1 (4L) -#define PINMUX_PB11E_TC5_WO1 ((PIN_PB11E_TC5_WO1 << 16) | MUX_PB11E_TC5_WO1) -#define PORT_PB11E_TC5_WO1 ((1UL) << 11) - -#define PIN_PB15E_TC5_WO1 (47L) -#define MUX_PB15E_TC5_WO1 (4L) -#define PINMUX_PB15E_TC5_WO1 ((PIN_PB15E_TC5_WO1 << 16) | MUX_PB15E_TC5_WO1) -#define PORT_PB15E_TC5_WO1 ((1UL) << 15) - -/* ========== PORT definition for TC6 peripheral ========== */ -#define PIN_PA30E_TC6_WO0 (30L) -#define MUX_PA30E_TC6_WO0 (4L) -#define PINMUX_PA30E_TC6_WO0 ((PIN_PA30E_TC6_WO0 << 16) | MUX_PA30E_TC6_WO0) -#define PORT_PA30E_TC6_WO0 ((1UL) << 30) - -#define PIN_PB02E_TC6_WO0 (34L) -#define MUX_PB02E_TC6_WO0 (4L) -#define PINMUX_PB02E_TC6_WO0 ((PIN_PB02E_TC6_WO0 << 16) | MUX_PB02E_TC6_WO0) -#define PORT_PB02E_TC6_WO0 ((1UL) << 2) - -#define PIN_PB16E_TC6_WO0 (48L) -#define MUX_PB16E_TC6_WO0 (4L) -#define PINMUX_PB16E_TC6_WO0 ((PIN_PB16E_TC6_WO0 << 16) | MUX_PB16E_TC6_WO0) -#define PORT_PB16E_TC6_WO0 ((1UL) << 16) - -#define PIN_PA31E_TC6_WO1 (31L) -#define MUX_PA31E_TC6_WO1 (4L) -#define PINMUX_PA31E_TC6_WO1 ((PIN_PA31E_TC6_WO1 << 16) | MUX_PA31E_TC6_WO1) -#define PORT_PA31E_TC6_WO1 ((1UL) << 31) - -#define PIN_PB03E_TC6_WO1 (35L) -#define MUX_PB03E_TC6_WO1 (4L) -#define PINMUX_PB03E_TC6_WO1 ((PIN_PB03E_TC6_WO1 << 16) | MUX_PB03E_TC6_WO1) -#define PORT_PB03E_TC6_WO1 ((1UL) << 3) - -#define PIN_PB17E_TC6_WO1 (49L) -#define MUX_PB17E_TC6_WO1 (4L) -#define PINMUX_PB17E_TC6_WO1 ((PIN_PB17E_TC6_WO1 << 16) | MUX_PB17E_TC6_WO1) -#define PORT_PB17E_TC6_WO1 ((1UL) << 17) - -/* ========== PORT definition for TC7 peripheral ========== */ -#define PIN_PA20E_TC7_WO0 (20L) -#define MUX_PA20E_TC7_WO0 (4L) -#define PINMUX_PA20E_TC7_WO0 ((PIN_PA20E_TC7_WO0 << 16) | MUX_PA20E_TC7_WO0) -#define PORT_PA20E_TC7_WO0 ((1UL) << 20) - -#define PIN_PB00E_TC7_WO0 (32L) -#define MUX_PB00E_TC7_WO0 (4L) -#define PINMUX_PB00E_TC7_WO0 ((PIN_PB00E_TC7_WO0 << 16) | MUX_PB00E_TC7_WO0) -#define PORT_PB00E_TC7_WO0 ((1UL) << 0) - -#define PIN_PB22E_TC7_WO0 (54L) -#define MUX_PB22E_TC7_WO0 (4L) -#define PINMUX_PB22E_TC7_WO0 ((PIN_PB22E_TC7_WO0 << 16) | MUX_PB22E_TC7_WO0) -#define PORT_PB22E_TC7_WO0 ((1UL) << 22) - -#define PIN_PA21E_TC7_WO1 (21L) -#define MUX_PA21E_TC7_WO1 (4L) -#define PINMUX_PA21E_TC7_WO1 ((PIN_PA21E_TC7_WO1 << 16) | MUX_PA21E_TC7_WO1) -#define PORT_PA21E_TC7_WO1 ((1UL) << 21) - -#define PIN_PB01E_TC7_WO1 (33L) -#define MUX_PB01E_TC7_WO1 (4L) -#define PINMUX_PB01E_TC7_WO1 ((PIN_PB01E_TC7_WO1 << 16) | MUX_PB01E_TC7_WO1) -#define PORT_PB01E_TC7_WO1 ((1UL) << 1) - -#define PIN_PB23E_TC7_WO1 (55L) -#define MUX_PB23E_TC7_WO1 (4L) -#define PINMUX_PB23E_TC7_WO1 ((PIN_PB23E_TC7_WO1 << 16) | MUX_PB23E_TC7_WO1) -#define PORT_PB23E_TC7_WO1 ((1UL) << 23) - -/* ========== PORT definition for TCC0 peripheral ========== */ -#define PIN_PA20G_TCC0_WO0 (20L) -#define MUX_PA20G_TCC0_WO0 (6L) -#define PINMUX_PA20G_TCC0_WO0 ((PIN_PA20G_TCC0_WO0 << 16) | MUX_PA20G_TCC0_WO0) -#define PORT_PA20G_TCC0_WO0 ((1UL) << 20) - -#define PIN_PB12G_TCC0_WO0 (44L) -#define MUX_PB12G_TCC0_WO0 (6L) -#define PINMUX_PB12G_TCC0_WO0 ((PIN_PB12G_TCC0_WO0 << 16) | MUX_PB12G_TCC0_WO0) -#define PORT_PB12G_TCC0_WO0 ((1UL) << 12) - -#define PIN_PA08F_TCC0_WO0 (8L) -#define MUX_PA08F_TCC0_WO0 (5L) -#define PINMUX_PA08F_TCC0_WO0 ((PIN_PA08F_TCC0_WO0 << 16) | MUX_PA08F_TCC0_WO0) -#define PORT_PA08F_TCC0_WO0 ((1UL) << 8) - -#define PIN_PC10F_TCC0_WO0 (74L) -#define MUX_PC10F_TCC0_WO0 (5L) -#define PINMUX_PC10F_TCC0_WO0 ((PIN_PC10F_TCC0_WO0 << 16) | MUX_PC10F_TCC0_WO0) -#define PORT_PC10F_TCC0_WO0 ((1UL) << 10) - -#define PIN_PC16F_TCC0_WO0 (80L) -#define MUX_PC16F_TCC0_WO0 (5L) -#define PINMUX_PC16F_TCC0_WO0 ((PIN_PC16F_TCC0_WO0 << 16) | MUX_PC16F_TCC0_WO0) -#define PORT_PC16F_TCC0_WO0 ((1UL) << 16) - -#define PIN_PA21G_TCC0_WO1 (21L) -#define MUX_PA21G_TCC0_WO1 (6L) -#define PINMUX_PA21G_TCC0_WO1 ((PIN_PA21G_TCC0_WO1 << 16) | MUX_PA21G_TCC0_WO1) -#define PORT_PA21G_TCC0_WO1 ((1UL) << 21) - -#define PIN_PB13G_TCC0_WO1 (45L) -#define MUX_PB13G_TCC0_WO1 (6L) -#define PINMUX_PB13G_TCC0_WO1 ((PIN_PB13G_TCC0_WO1 << 16) | MUX_PB13G_TCC0_WO1) -#define PORT_PB13G_TCC0_WO1 ((1UL) << 13) - -#define PIN_PA09F_TCC0_WO1 (9L) -#define MUX_PA09F_TCC0_WO1 (5L) -#define PINMUX_PA09F_TCC0_WO1 ((PIN_PA09F_TCC0_WO1 << 16) | MUX_PA09F_TCC0_WO1) -#define PORT_PA09F_TCC0_WO1 ((1UL) << 9) - -#define PIN_PC11F_TCC0_WO1 (75L) -#define MUX_PC11F_TCC0_WO1 (5L) -#define PINMUX_PC11F_TCC0_WO1 ((PIN_PC11F_TCC0_WO1 << 16) | MUX_PC11F_TCC0_WO1) -#define PORT_PC11F_TCC0_WO1 ((1UL) << 11) - -#define PIN_PC17F_TCC0_WO1 (81L) -#define MUX_PC17F_TCC0_WO1 (5L) -#define PINMUX_PC17F_TCC0_WO1 ((PIN_PC17F_TCC0_WO1 << 16) | MUX_PC17F_TCC0_WO1) -#define PORT_PC17F_TCC0_WO1 ((1UL) << 17) - -#define PIN_PA22G_TCC0_WO2 (22L) -#define MUX_PA22G_TCC0_WO2 (6L) -#define PINMUX_PA22G_TCC0_WO2 ((PIN_PA22G_TCC0_WO2 << 16) | MUX_PA22G_TCC0_WO2) -#define PORT_PA22G_TCC0_WO2 ((1UL) << 22) - -#define PIN_PB14G_TCC0_WO2 (46L) -#define MUX_PB14G_TCC0_WO2 (6L) -#define PINMUX_PB14G_TCC0_WO2 ((PIN_PB14G_TCC0_WO2 << 16) | MUX_PB14G_TCC0_WO2) -#define PORT_PB14G_TCC0_WO2 ((1UL) << 14) - -#define PIN_PA10F_TCC0_WO2 (10L) -#define MUX_PA10F_TCC0_WO2 (5L) -#define PINMUX_PA10F_TCC0_WO2 ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2) -#define PORT_PA10F_TCC0_WO2 ((1UL) << 10) - -#define PIN_PC12F_TCC0_WO2 (76L) -#define MUX_PC12F_TCC0_WO2 (5L) -#define PINMUX_PC12F_TCC0_WO2 ((PIN_PC12F_TCC0_WO2 << 16) | MUX_PC12F_TCC0_WO2) -#define PORT_PC12F_TCC0_WO2 ((1UL) << 12) - -#define PIN_PC18F_TCC0_WO2 (82L) -#define MUX_PC18F_TCC0_WO2 (5L) -#define PINMUX_PC18F_TCC0_WO2 ((PIN_PC18F_TCC0_WO2 << 16) | MUX_PC18F_TCC0_WO2) -#define PORT_PC18F_TCC0_WO2 ((1UL) << 18) - -#define PIN_PA23G_TCC0_WO3 (23L) -#define MUX_PA23G_TCC0_WO3 (6L) -#define PINMUX_PA23G_TCC0_WO3 ((PIN_PA23G_TCC0_WO3 << 16) | MUX_PA23G_TCC0_WO3) -#define PORT_PA23G_TCC0_WO3 ((1UL) << 23) - -#define PIN_PB15G_TCC0_WO3 (47L) -#define MUX_PB15G_TCC0_WO3 (6L) -#define PINMUX_PB15G_TCC0_WO3 ((PIN_PB15G_TCC0_WO3 << 16) | MUX_PB15G_TCC0_WO3) -#define PORT_PB15G_TCC0_WO3 ((1UL) << 15) - -#define PIN_PA11F_TCC0_WO3 (11L) -#define MUX_PA11F_TCC0_WO3 (5L) -#define PINMUX_PA11F_TCC0_WO3 ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3) -#define PORT_PA11F_TCC0_WO3 ((1UL) << 11) - -#define PIN_PC13F_TCC0_WO3 (77L) -#define MUX_PC13F_TCC0_WO3 (5L) -#define PINMUX_PC13F_TCC0_WO3 ((PIN_PC13F_TCC0_WO3 << 16) | MUX_PC13F_TCC0_WO3) -#define PORT_PC13F_TCC0_WO3 ((1UL) << 13) - -#define PIN_PC19F_TCC0_WO3 (83L) -#define MUX_PC19F_TCC0_WO3 (5L) -#define PINMUX_PC19F_TCC0_WO3 ((PIN_PC19F_TCC0_WO3 << 16) | MUX_PC19F_TCC0_WO3) -#define PORT_PC19F_TCC0_WO3 ((1UL) << 19) - -#define PIN_PA16G_TCC0_WO4 (16L) -#define MUX_PA16G_TCC0_WO4 (6L) -#define PINMUX_PA16G_TCC0_WO4 ((PIN_PA16G_TCC0_WO4 << 16) | MUX_PA16G_TCC0_WO4) -#define PORT_PA16G_TCC0_WO4 ((1UL) << 16) - -#define PIN_PB16G_TCC0_WO4 (48L) -#define MUX_PB16G_TCC0_WO4 (6L) -#define PINMUX_PB16G_TCC0_WO4 ((PIN_PB16G_TCC0_WO4 << 16) | MUX_PB16G_TCC0_WO4) -#define PORT_PB16G_TCC0_WO4 ((1UL) << 16) - -#define PIN_PB10F_TCC0_WO4 (42L) -#define MUX_PB10F_TCC0_WO4 (5L) -#define PINMUX_PB10F_TCC0_WO4 ((PIN_PB10F_TCC0_WO4 << 16) | MUX_PB10F_TCC0_WO4) -#define PORT_PB10F_TCC0_WO4 ((1UL) << 10) - -#define PIN_PC14F_TCC0_WO4 (78L) -#define MUX_PC14F_TCC0_WO4 (5L) -#define PINMUX_PC14F_TCC0_WO4 ((PIN_PC14F_TCC0_WO4 << 16) | MUX_PC14F_TCC0_WO4) -#define PORT_PC14F_TCC0_WO4 ((1UL) << 14) - -#define PIN_PC20F_TCC0_WO4 (84L) -#define MUX_PC20F_TCC0_WO4 (5L) -#define PINMUX_PC20F_TCC0_WO4 ((PIN_PC20F_TCC0_WO4 << 16) | MUX_PC20F_TCC0_WO4) -#define PORT_PC20F_TCC0_WO4 ((1UL) << 20) - -#define PIN_PA17G_TCC0_WO5 (17L) -#define MUX_PA17G_TCC0_WO5 (6L) -#define PINMUX_PA17G_TCC0_WO5 ((PIN_PA17G_TCC0_WO5 << 16) | MUX_PA17G_TCC0_WO5) -#define PORT_PA17G_TCC0_WO5 ((1UL) << 17) - -#define PIN_PB17G_TCC0_WO5 (49L) -#define MUX_PB17G_TCC0_WO5 (6L) -#define PINMUX_PB17G_TCC0_WO5 ((PIN_PB17G_TCC0_WO5 << 16) | MUX_PB17G_TCC0_WO5) -#define PORT_PB17G_TCC0_WO5 ((1UL) << 17) - -#define PIN_PB11F_TCC0_WO5 (43L) -#define MUX_PB11F_TCC0_WO5 (5L) -#define PINMUX_PB11F_TCC0_WO5 ((PIN_PB11F_TCC0_WO5 << 16) | MUX_PB11F_TCC0_WO5) -#define PORT_PB11F_TCC0_WO5 ((1UL) << 11) - -#define PIN_PC15F_TCC0_WO5 (79L) -#define MUX_PC15F_TCC0_WO5 (5L) -#define PINMUX_PC15F_TCC0_WO5 ((PIN_PC15F_TCC0_WO5 << 16) | MUX_PC15F_TCC0_WO5) -#define PORT_PC15F_TCC0_WO5 ((1UL) << 15) - -#define PIN_PC21F_TCC0_WO5 (85L) -#define MUX_PC21F_TCC0_WO5 (5L) -#define PINMUX_PC21F_TCC0_WO5 ((PIN_PC21F_TCC0_WO5 << 16) | MUX_PC21F_TCC0_WO5) -#define PORT_PC21F_TCC0_WO5 ((1UL) << 21) - -#define PIN_PA18G_TCC0_WO6 (18L) -#define MUX_PA18G_TCC0_WO6 (6L) -#define PINMUX_PA18G_TCC0_WO6 ((PIN_PA18G_TCC0_WO6 << 16) | MUX_PA18G_TCC0_WO6) -#define PORT_PA18G_TCC0_WO6 ((1UL) << 18) - -#define PIN_PB30G_TCC0_WO6 (62L) -#define MUX_PB30G_TCC0_WO6 (6L) -#define PINMUX_PB30G_TCC0_WO6 ((PIN_PB30G_TCC0_WO6 << 16) | MUX_PB30G_TCC0_WO6) -#define PORT_PB30G_TCC0_WO6 ((1UL) << 30) - -#define PIN_PA12F_TCC0_WO6 (12L) -#define MUX_PA12F_TCC0_WO6 (5L) -#define PINMUX_PA12F_TCC0_WO6 ((PIN_PA12F_TCC0_WO6 << 16) | MUX_PA12F_TCC0_WO6) -#define PORT_PA12F_TCC0_WO6 ((1UL) << 12) - -#define PIN_PA19G_TCC0_WO7 (19L) -#define MUX_PA19G_TCC0_WO7 (6L) -#define PINMUX_PA19G_TCC0_WO7 ((PIN_PA19G_TCC0_WO7 << 16) | MUX_PA19G_TCC0_WO7) -#define PORT_PA19G_TCC0_WO7 ((1UL) << 19) - -#define PIN_PB31G_TCC0_WO7 (63L) -#define MUX_PB31G_TCC0_WO7 (6L) -#define PINMUX_PB31G_TCC0_WO7 ((PIN_PB31G_TCC0_WO7 << 16) | MUX_PB31G_TCC0_WO7) -#define PORT_PB31G_TCC0_WO7 ((1UL) << 31) - -#define PIN_PA13F_TCC0_WO7 (13L) -#define MUX_PA13F_TCC0_WO7 (5L) -#define PINMUX_PA13F_TCC0_WO7 ((PIN_PA13F_TCC0_WO7 << 16) | MUX_PA13F_TCC0_WO7) -#define PORT_PA13F_TCC0_WO7 ((1UL) << 13) - -/* ========== PORT definition for TCC1 peripheral ========== */ -#define PIN_PB10G_TCC1_WO0 (42L) -#define MUX_PB10G_TCC1_WO0 (6L) -#define PINMUX_PB10G_TCC1_WO0 ((PIN_PB10G_TCC1_WO0 << 16) | MUX_PB10G_TCC1_WO0) -#define PORT_PB10G_TCC1_WO0 ((1UL) << 10) - -#define PIN_PC14G_TCC1_WO0 (78L) -#define MUX_PC14G_TCC1_WO0 (6L) -#define PINMUX_PC14G_TCC1_WO0 ((PIN_PC14G_TCC1_WO0 << 16) | MUX_PC14G_TCC1_WO0) -#define PORT_PC14G_TCC1_WO0 ((1UL) << 14) - -#define PIN_PA16F_TCC1_WO0 (16L) -#define MUX_PA16F_TCC1_WO0 (5L) -#define PINMUX_PA16F_TCC1_WO0 ((PIN_PA16F_TCC1_WO0 << 16) | MUX_PA16F_TCC1_WO0) -#define PORT_PA16F_TCC1_WO0 ((1UL) << 16) - -#define PIN_PB18F_TCC1_WO0 (50L) -#define MUX_PB18F_TCC1_WO0 (5L) -#define PINMUX_PB18F_TCC1_WO0 ((PIN_PB18F_TCC1_WO0 << 16) | MUX_PB18F_TCC1_WO0) -#define PORT_PB18F_TCC1_WO0 ((1UL) << 18) - -#define PIN_PB11G_TCC1_WO1 (43L) -#define MUX_PB11G_TCC1_WO1 (6L) -#define PINMUX_PB11G_TCC1_WO1 ((PIN_PB11G_TCC1_WO1 << 16) | MUX_PB11G_TCC1_WO1) -#define PORT_PB11G_TCC1_WO1 ((1UL) << 11) - -#define PIN_PC15G_TCC1_WO1 (79L) -#define MUX_PC15G_TCC1_WO1 (6L) -#define PINMUX_PC15G_TCC1_WO1 ((PIN_PC15G_TCC1_WO1 << 16) | MUX_PC15G_TCC1_WO1) -#define PORT_PC15G_TCC1_WO1 ((1UL) << 15) - -#define PIN_PA17F_TCC1_WO1 (17L) -#define MUX_PA17F_TCC1_WO1 (5L) -#define PINMUX_PA17F_TCC1_WO1 ((PIN_PA17F_TCC1_WO1 << 16) | MUX_PA17F_TCC1_WO1) -#define PORT_PA17F_TCC1_WO1 ((1UL) << 17) - -#define PIN_PB19F_TCC1_WO1 (51L) -#define MUX_PB19F_TCC1_WO1 (5L) -#define PINMUX_PB19F_TCC1_WO1 ((PIN_PB19F_TCC1_WO1 << 16) | MUX_PB19F_TCC1_WO1) -#define PORT_PB19F_TCC1_WO1 ((1UL) << 19) - -#define PIN_PA12G_TCC1_WO2 (12L) -#define MUX_PA12G_TCC1_WO2 (6L) -#define PINMUX_PA12G_TCC1_WO2 ((PIN_PA12G_TCC1_WO2 << 16) | MUX_PA12G_TCC1_WO2) -#define PORT_PA12G_TCC1_WO2 ((1UL) << 12) - -#define PIN_PA14G_TCC1_WO2 (14L) -#define MUX_PA14G_TCC1_WO2 (6L) -#define PINMUX_PA14G_TCC1_WO2 ((PIN_PA14G_TCC1_WO2 << 16) | MUX_PA14G_TCC1_WO2) -#define PORT_PA14G_TCC1_WO2 ((1UL) << 14) - -#define PIN_PA18F_TCC1_WO2 (18L) -#define MUX_PA18F_TCC1_WO2 (5L) -#define PINMUX_PA18F_TCC1_WO2 ((PIN_PA18F_TCC1_WO2 << 16) | MUX_PA18F_TCC1_WO2) -#define PORT_PA18F_TCC1_WO2 ((1UL) << 18) - -#define PIN_PB20F_TCC1_WO2 (52L) -#define MUX_PB20F_TCC1_WO2 (5L) -#define PINMUX_PB20F_TCC1_WO2 ((PIN_PB20F_TCC1_WO2 << 16) | MUX_PB20F_TCC1_WO2) -#define PORT_PB20F_TCC1_WO2 ((1UL) << 20) - -#define PIN_PA13G_TCC1_WO3 (13L) -#define MUX_PA13G_TCC1_WO3 (6L) -#define PINMUX_PA13G_TCC1_WO3 ((PIN_PA13G_TCC1_WO3 << 16) | MUX_PA13G_TCC1_WO3) -#define PORT_PA13G_TCC1_WO3 ((1UL) << 13) - -#define PIN_PA15G_TCC1_WO3 (15L) -#define MUX_PA15G_TCC1_WO3 (6L) -#define PINMUX_PA15G_TCC1_WO3 ((PIN_PA15G_TCC1_WO3 << 16) | MUX_PA15G_TCC1_WO3) -#define PORT_PA15G_TCC1_WO3 ((1UL) << 15) - -#define PIN_PA19F_TCC1_WO3 (19L) -#define MUX_PA19F_TCC1_WO3 (5L) -#define PINMUX_PA19F_TCC1_WO3 ((PIN_PA19F_TCC1_WO3 << 16) | MUX_PA19F_TCC1_WO3) -#define PORT_PA19F_TCC1_WO3 ((1UL) << 19) - -#define PIN_PB21F_TCC1_WO3 (53L) -#define MUX_PB21F_TCC1_WO3 (5L) -#define PINMUX_PB21F_TCC1_WO3 ((PIN_PB21F_TCC1_WO3 << 16) | MUX_PB21F_TCC1_WO3) -#define PORT_PB21F_TCC1_WO3 ((1UL) << 21) - -#define PIN_PA08G_TCC1_WO4 (8L) -#define MUX_PA08G_TCC1_WO4 (6L) -#define PINMUX_PA08G_TCC1_WO4 ((PIN_PA08G_TCC1_WO4 << 16) | MUX_PA08G_TCC1_WO4) -#define PORT_PA08G_TCC1_WO4 ((1UL) << 8) - -#define PIN_PC10G_TCC1_WO4 (74L) -#define MUX_PC10G_TCC1_WO4 (6L) -#define PINMUX_PC10G_TCC1_WO4 ((PIN_PC10G_TCC1_WO4 << 16) | MUX_PC10G_TCC1_WO4) -#define PORT_PC10G_TCC1_WO4 ((1UL) << 10) - -#define PIN_PA20F_TCC1_WO4 (20L) -#define MUX_PA20F_TCC1_WO4 (5L) -#define PINMUX_PA20F_TCC1_WO4 ((PIN_PA20F_TCC1_WO4 << 16) | MUX_PA20F_TCC1_WO4) -#define PORT_PA20F_TCC1_WO4 ((1UL) << 20) - -#define PIN_PA09G_TCC1_WO5 (9L) -#define MUX_PA09G_TCC1_WO5 (6L) -#define PINMUX_PA09G_TCC1_WO5 ((PIN_PA09G_TCC1_WO5 << 16) | MUX_PA09G_TCC1_WO5) -#define PORT_PA09G_TCC1_WO5 ((1UL) << 9) - -#define PIN_PC11G_TCC1_WO5 (75L) -#define MUX_PC11G_TCC1_WO5 (6L) -#define PINMUX_PC11G_TCC1_WO5 ((PIN_PC11G_TCC1_WO5 << 16) | MUX_PC11G_TCC1_WO5) -#define PORT_PC11G_TCC1_WO5 ((1UL) << 11) - -#define PIN_PA21F_TCC1_WO5 (21L) -#define MUX_PA21F_TCC1_WO5 (5L) -#define PINMUX_PA21F_TCC1_WO5 ((PIN_PA21F_TCC1_WO5 << 16) | MUX_PA21F_TCC1_WO5) -#define PORT_PA21F_TCC1_WO5 ((1UL) << 21) - -#define PIN_PA10G_TCC1_WO6 (10L) -#define MUX_PA10G_TCC1_WO6 (6L) -#define PINMUX_PA10G_TCC1_WO6 ((PIN_PA10G_TCC1_WO6 << 16) | MUX_PA10G_TCC1_WO6) -#define PORT_PA10G_TCC1_WO6 ((1UL) << 10) - -#define PIN_PC12G_TCC1_WO6 (76L) -#define MUX_PC12G_TCC1_WO6 (6L) -#define PINMUX_PC12G_TCC1_WO6 ((PIN_PC12G_TCC1_WO6 << 16) | MUX_PC12G_TCC1_WO6) -#define PORT_PC12G_TCC1_WO6 ((1UL) << 12) - -#define PIN_PA22F_TCC1_WO6 (22L) -#define MUX_PA22F_TCC1_WO6 (5L) -#define PINMUX_PA22F_TCC1_WO6 ((PIN_PA22F_TCC1_WO6 << 16) | MUX_PA22F_TCC1_WO6) -#define PORT_PA22F_TCC1_WO6 ((1UL) << 22) - -#define PIN_PA11G_TCC1_WO7 (11L) -#define MUX_PA11G_TCC1_WO7 (6L) -#define PINMUX_PA11G_TCC1_WO7 ((PIN_PA11G_TCC1_WO7 << 16) | MUX_PA11G_TCC1_WO7) -#define PORT_PA11G_TCC1_WO7 ((1UL) << 11) - -#define PIN_PC13G_TCC1_WO7 (77L) -#define MUX_PC13G_TCC1_WO7 (6L) -#define PINMUX_PC13G_TCC1_WO7 ((PIN_PC13G_TCC1_WO7 << 16) | MUX_PC13G_TCC1_WO7) -#define PORT_PC13G_TCC1_WO7 ((1UL) << 13) - -#define PIN_PA23F_TCC1_WO7 (23L) -#define MUX_PA23F_TCC1_WO7 (5L) -#define PINMUX_PA23F_TCC1_WO7 ((PIN_PA23F_TCC1_WO7 << 16) | MUX_PA23F_TCC1_WO7) -#define PORT_PA23F_TCC1_WO7 ((1UL) << 23) - -/* ========== PORT definition for TCC2 peripheral ========== */ -#define PIN_PA14F_TCC2_WO0 (14L) -#define MUX_PA14F_TCC2_WO0 (5L) -#define PINMUX_PA14F_TCC2_WO0 ((PIN_PA14F_TCC2_WO0 << 16) | MUX_PA14F_TCC2_WO0) -#define PORT_PA14F_TCC2_WO0 ((1UL) << 14) - -#define PIN_PA30F_TCC2_WO0 (30L) -#define MUX_PA30F_TCC2_WO0 (5L) -#define PINMUX_PA30F_TCC2_WO0 ((PIN_PA30F_TCC2_WO0 << 16) | MUX_PA30F_TCC2_WO0) -#define PORT_PA30F_TCC2_WO0 ((1UL) << 30) - -#define PIN_PA15F_TCC2_WO1 (15L) -#define MUX_PA15F_TCC2_WO1 (5L) -#define PINMUX_PA15F_TCC2_WO1 ((PIN_PA15F_TCC2_WO1 << 16) | MUX_PA15F_TCC2_WO1) -#define PORT_PA15F_TCC2_WO1 ((1UL) << 15) - -#define PIN_PA31F_TCC2_WO1 (31L) -#define MUX_PA31F_TCC2_WO1 (5L) -#define PINMUX_PA31F_TCC2_WO1 ((PIN_PA31F_TCC2_WO1 << 16) | MUX_PA31F_TCC2_WO1) -#define PORT_PA31F_TCC2_WO1 ((1UL) << 31) - -#define PIN_PA24F_TCC2_WO2 (24L) -#define MUX_PA24F_TCC2_WO2 (5L) -#define PINMUX_PA24F_TCC2_WO2 ((PIN_PA24F_TCC2_WO2 << 16) | MUX_PA24F_TCC2_WO2) -#define PORT_PA24F_TCC2_WO2 ((1UL) << 24) - -#define PIN_PB02F_TCC2_WO2 (34L) -#define MUX_PB02F_TCC2_WO2 (5L) -#define PINMUX_PB02F_TCC2_WO2 ((PIN_PB02F_TCC2_WO2 << 16) | MUX_PB02F_TCC2_WO2) -#define PORT_PB02F_TCC2_WO2 ((1UL) << 2) - -/* ========== PORT definition for TCC3 peripheral ========== */ -#define PIN_PB12F_TCC3_WO0 (44L) -#define MUX_PB12F_TCC3_WO0 (5L) -#define PINMUX_PB12F_TCC3_WO0 ((PIN_PB12F_TCC3_WO0 << 16) | MUX_PB12F_TCC3_WO0) -#define PORT_PB12F_TCC3_WO0 ((1UL) << 12) - -#define PIN_PB16F_TCC3_WO0 (48L) -#define MUX_PB16F_TCC3_WO0 (5L) -#define PINMUX_PB16F_TCC3_WO0 ((PIN_PB16F_TCC3_WO0 << 16) | MUX_PB16F_TCC3_WO0) -#define PORT_PB16F_TCC3_WO0 ((1UL) << 16) - -#define PIN_PB13F_TCC3_WO1 (45L) -#define MUX_PB13F_TCC3_WO1 (5L) -#define PINMUX_PB13F_TCC3_WO1 ((PIN_PB13F_TCC3_WO1 << 16) | MUX_PB13F_TCC3_WO1) -#define PORT_PB13F_TCC3_WO1 ((1UL) << 13) - -#define PIN_PB17F_TCC3_WO1 (49L) -#define MUX_PB17F_TCC3_WO1 (5L) -#define PINMUX_PB17F_TCC3_WO1 ((PIN_PB17F_TCC3_WO1 << 16) | MUX_PB17F_TCC3_WO1) -#define PORT_PB17F_TCC3_WO1 ((1UL) << 17) - -/* ========== PORT definition for TCC4 peripheral ========== */ -#define PIN_PB14F_TCC4_WO0 (46L) -#define MUX_PB14F_TCC4_WO0 (5L) -#define PINMUX_PB14F_TCC4_WO0 ((PIN_PB14F_TCC4_WO0 << 16) | MUX_PB14F_TCC4_WO0) -#define PORT_PB14F_TCC4_WO0 ((1UL) << 14) - -#define PIN_PB30F_TCC4_WO0 (62L) -#define MUX_PB30F_TCC4_WO0 (5L) -#define PINMUX_PB30F_TCC4_WO0 ((PIN_PB30F_TCC4_WO0 << 16) | MUX_PB30F_TCC4_WO0) -#define PORT_PB30F_TCC4_WO0 ((1UL) << 30) - -#define PIN_PB15F_TCC4_WO1 (47L) -#define MUX_PB15F_TCC4_WO1 (5L) -#define PINMUX_PB15F_TCC4_WO1 ((PIN_PB15F_TCC4_WO1 << 16) | MUX_PB15F_TCC4_WO1) -#define PORT_PB15F_TCC4_WO1 ((1UL) << 15) - -#define PIN_PB31F_TCC4_WO1 (63L) -#define MUX_PB31F_TCC4_WO1 (5L) -#define PINMUX_PB31F_TCC4_WO1 ((PIN_PB31F_TCC4_WO1 << 16) | MUX_PB31F_TCC4_WO1) -#define PORT_PB31F_TCC4_WO1 ((1UL) << 31) - -/* ========== PORT definition for USB peripheral ========== */ -#define PIN_PA24H_USB_DM (24L) -#define MUX_PA24H_USB_DM (7L) -#define PINMUX_PA24H_USB_DM ((PIN_PA24H_USB_DM << 16) | MUX_PA24H_USB_DM) -#define PORT_PA24H_USB_DM ((1UL) << 24) - -#define PIN_PA25H_USB_DP (25L) -#define MUX_PA25H_USB_DP (7L) -#define PINMUX_PA25H_USB_DP ((PIN_PA25H_USB_DP << 16) | MUX_PA25H_USB_DP) -#define PORT_PA25H_USB_DP ((1UL) << 25) - -#define PIN_PA23H_USB_SOF_1KHZ (23L) -#define MUX_PA23H_USB_SOF_1KHZ (7L) -#define PINMUX_PA23H_USB_SOF_1KHZ ((PIN_PA23H_USB_SOF_1KHZ << 16) | MUX_PA23H_USB_SOF_1KHZ) -#define PORT_PA23H_USB_SOF_1KHZ ((1UL) << 23) - -#define PIN_PB22H_USB_SOF_1KHZ (54L) -#define MUX_PB22H_USB_SOF_1KHZ (7L) -#define PINMUX_PB22H_USB_SOF_1KHZ ((PIN_PB22H_USB_SOF_1KHZ << 16) | MUX_PB22H_USB_SOF_1KHZ) -#define PORT_PB22H_USB_SOF_1KHZ ((1UL) << 22) - - - -#endif /* _SAME54N20A_GPIO_H_ */ - +/** + * \file + * + * \brief Peripheral I/O description for SAME54N20A + * + * Copyright (c) 2019 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAME54N20A_PIO_ +#define _SAME54N20A_PIO_ + +#define PIN_PA00 0 /**< \brief Pin Number for PA00 */ +#define PORT_PA00 (_UL_(1) << 0) /**< \brief PORT Mask for PA00 */ +#define PIN_PA01 1 /**< \brief Pin Number for PA01 */ +#define PORT_PA01 (_UL_(1) << 1) /**< \brief PORT Mask for PA01 */ +#define PIN_PA02 2 /**< \brief Pin Number for PA02 */ +#define PORT_PA02 (_UL_(1) << 2) /**< \brief PORT Mask for PA02 */ +#define PIN_PA03 3 /**< \brief Pin Number for PA03 */ +#define PORT_PA03 (_UL_(1) << 3) /**< \brief PORT Mask for PA03 */ +#define PIN_PA04 4 /**< \brief Pin Number for PA04 */ +#define PORT_PA04 (_UL_(1) << 4) /**< \brief PORT Mask for PA04 */ +#define PIN_PA05 5 /**< \brief Pin Number for PA05 */ +#define PORT_PA05 (_UL_(1) << 5) /**< \brief PORT Mask for PA05 */ +#define PIN_PA06 6 /**< \brief Pin Number for PA06 */ +#define PORT_PA06 (_UL_(1) << 6) /**< \brief PORT Mask for PA06 */ +#define PIN_PA07 7 /**< \brief Pin Number for PA07 */ +#define PORT_PA07 (_UL_(1) << 7) /**< \brief PORT Mask for PA07 */ +#define PIN_PA08 8 /**< \brief Pin Number for PA08 */ +#define PORT_PA08 (_UL_(1) << 8) /**< \brief PORT Mask for PA08 */ +#define PIN_PA09 9 /**< \brief Pin Number for PA09 */ +#define PORT_PA09 (_UL_(1) << 9) /**< \brief PORT Mask for PA09 */ +#define PIN_PA10 10 /**< \brief Pin Number for PA10 */ +#define PORT_PA10 (_UL_(1) << 10) /**< \brief PORT Mask for PA10 */ +#define PIN_PA11 11 /**< \brief Pin Number for PA11 */ +#define PORT_PA11 (_UL_(1) << 11) /**< \brief PORT Mask for PA11 */ +#define PIN_PA12 12 /**< \brief Pin Number for PA12 */ +#define PORT_PA12 (_UL_(1) << 12) /**< \brief PORT Mask for PA12 */ +#define PIN_PA13 13 /**< \brief Pin Number for PA13 */ +#define PORT_PA13 (_UL_(1) << 13) /**< \brief PORT Mask for PA13 */ +#define PIN_PA14 14 /**< \brief Pin Number for PA14 */ +#define PORT_PA14 (_UL_(1) << 14) /**< \brief PORT Mask for PA14 */ +#define PIN_PA15 15 /**< \brief Pin Number for PA15 */ +#define PORT_PA15 (_UL_(1) << 15) /**< \brief PORT Mask for PA15 */ +#define PIN_PA16 16 /**< \brief Pin Number for PA16 */ +#define PORT_PA16 (_UL_(1) << 16) /**< \brief PORT Mask for PA16 */ +#define PIN_PA17 17 /**< \brief Pin Number for PA17 */ +#define PORT_PA17 (_UL_(1) << 17) /**< \brief PORT Mask for PA17 */ +#define PIN_PA18 18 /**< \brief Pin Number for PA18 */ +#define PORT_PA18 (_UL_(1) << 18) /**< \brief PORT Mask for PA18 */ +#define PIN_PA19 19 /**< \brief Pin Number for PA19 */ +#define PORT_PA19 (_UL_(1) << 19) /**< \brief PORT Mask for PA19 */ +#define PIN_PA20 20 /**< \brief Pin Number for PA20 */ +#define PORT_PA20 (_UL_(1) << 20) /**< \brief PORT Mask for PA20 */ +#define PIN_PA21 21 /**< \brief Pin Number for PA21 */ +#define PORT_PA21 (_UL_(1) << 21) /**< \brief PORT Mask for PA21 */ +#define PIN_PA22 22 /**< \brief Pin Number for PA22 */ +#define PORT_PA22 (_UL_(1) << 22) /**< \brief PORT Mask for PA22 */ +#define PIN_PA23 23 /**< \brief Pin Number for PA23 */ +#define PORT_PA23 (_UL_(1) << 23) /**< \brief PORT Mask for PA23 */ +#define PIN_PA24 24 /**< \brief Pin Number for PA24 */ +#define PORT_PA24 (_UL_(1) << 24) /**< \brief PORT Mask for PA24 */ +#define PIN_PA25 25 /**< \brief Pin Number for PA25 */ +#define PORT_PA25 (_UL_(1) << 25) /**< \brief PORT Mask for PA25 */ +#define PIN_PA27 27 /**< \brief Pin Number for PA27 */ +#define PORT_PA27 (_UL_(1) << 27) /**< \brief PORT Mask for PA27 */ +#define PIN_PA30 30 /**< \brief Pin Number for PA30 */ +#define PORT_PA30 (_UL_(1) << 30) /**< \brief PORT Mask for PA30 */ +#define PIN_PA31 31 /**< \brief Pin Number for PA31 */ +#define PORT_PA31 (_UL_(1) << 31) /**< \brief PORT Mask for PA31 */ +#define PIN_PB00 32 /**< \brief Pin Number for PB00 */ +#define PORT_PB00 (_UL_(1) << 0) /**< \brief PORT Mask for PB00 */ +#define PIN_PB01 33 /**< \brief Pin Number for PB01 */ +#define PORT_PB01 (_UL_(1) << 1) /**< \brief PORT Mask for PB01 */ +#define PIN_PB02 34 /**< \brief Pin Number for PB02 */ +#define PORT_PB02 (_UL_(1) << 2) /**< \brief PORT Mask for PB02 */ +#define PIN_PB03 35 /**< \brief Pin Number for PB03 */ +#define PORT_PB03 (_UL_(1) << 3) /**< \brief PORT Mask for PB03 */ +#define PIN_PB04 36 /**< \brief Pin Number for PB04 */ +#define PORT_PB04 (_UL_(1) << 4) /**< \brief PORT Mask for PB04 */ +#define PIN_PB05 37 /**< \brief Pin Number for PB05 */ +#define PORT_PB05 (_UL_(1) << 5) /**< \brief PORT Mask for PB05 */ +#define PIN_PB06 38 /**< \brief Pin Number for PB06 */ +#define PORT_PB06 (_UL_(1) << 6) /**< \brief PORT Mask for PB06 */ +#define PIN_PB07 39 /**< \brief Pin Number for PB07 */ +#define PORT_PB07 (_UL_(1) << 7) /**< \brief PORT Mask for PB07 */ +#define PIN_PB08 40 /**< \brief Pin Number for PB08 */ +#define PORT_PB08 (_UL_(1) << 8) /**< \brief PORT Mask for PB08 */ +#define PIN_PB09 41 /**< \brief Pin Number for PB09 */ +#define PORT_PB09 (_UL_(1) << 9) /**< \brief PORT Mask for PB09 */ +#define PIN_PB10 42 /**< \brief Pin Number for PB10 */ +#define PORT_PB10 (_UL_(1) << 10) /**< \brief PORT Mask for PB10 */ +#define PIN_PB11 43 /**< \brief Pin Number for PB11 */ +#define PORT_PB11 (_UL_(1) << 11) /**< \brief PORT Mask for PB11 */ +#define PIN_PB12 44 /**< \brief Pin Number for PB12 */ +#define PORT_PB12 (_UL_(1) << 12) /**< \brief PORT Mask for PB12 */ +#define PIN_PB13 45 /**< \brief Pin Number for PB13 */ +#define PORT_PB13 (_UL_(1) << 13) /**< \brief PORT Mask for PB13 */ +#define PIN_PB14 46 /**< \brief Pin Number for PB14 */ +#define PORT_PB14 (_UL_(1) << 14) /**< \brief PORT Mask for PB14 */ +#define PIN_PB15 47 /**< \brief Pin Number for PB15 */ +#define PORT_PB15 (_UL_(1) << 15) /**< \brief PORT Mask for PB15 */ +#define PIN_PB16 48 /**< \brief Pin Number for PB16 */ +#define PORT_PB16 (_UL_(1) << 16) /**< \brief PORT Mask for PB16 */ +#define PIN_PB17 49 /**< \brief Pin Number for PB17 */ +#define PORT_PB17 (_UL_(1) << 17) /**< \brief PORT Mask for PB17 */ +#define PIN_PB18 50 /**< \brief Pin Number for PB18 */ +#define PORT_PB18 (_UL_(1) << 18) /**< \brief PORT Mask for PB18 */ +#define PIN_PB19 51 /**< \brief Pin Number for PB19 */ +#define PORT_PB19 (_UL_(1) << 19) /**< \brief PORT Mask for PB19 */ +#define PIN_PB20 52 /**< \brief Pin Number for PB20 */ +#define PORT_PB20 (_UL_(1) << 20) /**< \brief PORT Mask for PB20 */ +#define PIN_PB21 53 /**< \brief Pin Number for PB21 */ +#define PORT_PB21 (_UL_(1) << 21) /**< \brief PORT Mask for PB21 */ +#define PIN_PB22 54 /**< \brief Pin Number for PB22 */ +#define PORT_PB22 (_UL_(1) << 22) /**< \brief PORT Mask for PB22 */ +#define PIN_PB23 55 /**< \brief Pin Number for PB23 */ +#define PORT_PB23 (_UL_(1) << 23) /**< \brief PORT Mask for PB23 */ +#define PIN_PB24 56 /**< \brief Pin Number for PB24 */ +#define PORT_PB24 (_UL_(1) << 24) /**< \brief PORT Mask for PB24 */ +#define PIN_PB25 57 /**< \brief Pin Number for PB25 */ +#define PORT_PB25 (_UL_(1) << 25) /**< \brief PORT Mask for PB25 */ +#define PIN_PB30 62 /**< \brief Pin Number for PB30 */ +#define PORT_PB30 (_UL_(1) << 30) /**< \brief PORT Mask for PB30 */ +#define PIN_PB31 63 /**< \brief Pin Number for PB31 */ +#define PORT_PB31 (_UL_(1) << 31) /**< \brief PORT Mask for PB31 */ +#define PIN_PC00 64 /**< \brief Pin Number for PC00 */ +#define PORT_PC00 (_UL_(1) << 0) /**< \brief PORT Mask for PC00 */ +#define PIN_PC01 65 /**< \brief Pin Number for PC01 */ +#define PORT_PC01 (_UL_(1) << 1) /**< \brief PORT Mask for PC01 */ +#define PIN_PC02 66 /**< \brief Pin Number for PC02 */ +#define PORT_PC02 (_UL_(1) << 2) /**< \brief PORT Mask for PC02 */ +#define PIN_PC03 67 /**< \brief Pin Number for PC03 */ +#define PORT_PC03 (_UL_(1) << 3) /**< \brief PORT Mask for PC03 */ +#define PIN_PC05 69 /**< \brief Pin Number for PC05 */ +#define PORT_PC05 (_UL_(1) << 5) /**< \brief PORT Mask for PC05 */ +#define PIN_PC06 70 /**< \brief Pin Number for PC06 */ +#define PORT_PC06 (_UL_(1) << 6) /**< \brief PORT Mask for PC06 */ +#define PIN_PC07 71 /**< \brief Pin Number for PC07 */ +#define PORT_PC07 (_UL_(1) << 7) /**< \brief PORT Mask for PC07 */ +#define PIN_PC10 74 /**< \brief Pin Number for PC10 */ +#define PORT_PC10 (_UL_(1) << 10) /**< \brief PORT Mask for PC10 */ +#define PIN_PC11 75 /**< \brief Pin Number for PC11 */ +#define PORT_PC11 (_UL_(1) << 11) /**< \brief PORT Mask for PC11 */ +#define PIN_PC12 76 /**< \brief Pin Number for PC12 */ +#define PORT_PC12 (_UL_(1) << 12) /**< \brief PORT Mask for PC12 */ +#define PIN_PC13 77 /**< \brief Pin Number for PC13 */ +#define PORT_PC13 (_UL_(1) << 13) /**< \brief PORT Mask for PC13 */ +#define PIN_PC14 78 /**< \brief Pin Number for PC14 */ +#define PORT_PC14 (_UL_(1) << 14) /**< \brief PORT Mask for PC14 */ +#define PIN_PC15 79 /**< \brief Pin Number for PC15 */ +#define PORT_PC15 (_UL_(1) << 15) /**< \brief PORT Mask for PC15 */ +#define PIN_PC16 80 /**< \brief Pin Number for PC16 */ +#define PORT_PC16 (_UL_(1) << 16) /**< \brief PORT Mask for PC16 */ +#define PIN_PC17 81 /**< \brief Pin Number for PC17 */ +#define PORT_PC17 (_UL_(1) << 17) /**< \brief PORT Mask for PC17 */ +#define PIN_PC18 82 /**< \brief Pin Number for PC18 */ +#define PORT_PC18 (_UL_(1) << 18) /**< \brief PORT Mask for PC18 */ +#define PIN_PC19 83 /**< \brief Pin Number for PC19 */ +#define PORT_PC19 (_UL_(1) << 19) /**< \brief PORT Mask for PC19 */ +#define PIN_PC20 84 /**< \brief Pin Number for PC20 */ +#define PORT_PC20 (_UL_(1) << 20) /**< \brief PORT Mask for PC20 */ +#define PIN_PC21 85 /**< \brief Pin Number for PC21 */ +#define PORT_PC21 (_UL_(1) << 21) /**< \brief PORT Mask for PC21 */ +#define PIN_PC24 88 /**< \brief Pin Number for PC24 */ +#define PORT_PC24 (_UL_(1) << 24) /**< \brief PORT Mask for PC24 */ +#define PIN_PC25 89 /**< \brief Pin Number for PC25 */ +#define PORT_PC25 (_UL_(1) << 25) /**< \brief PORT Mask for PC25 */ +#define PIN_PC26 90 /**< \brief Pin Number for PC26 */ +#define PORT_PC26 (_UL_(1) << 26) /**< \brief PORT Mask for PC26 */ +#define PIN_PC27 91 /**< \brief Pin Number for PC27 */ +#define PORT_PC27 (_UL_(1) << 27) /**< \brief PORT Mask for PC27 */ +#define PIN_PC28 92 /**< \brief Pin Number for PC28 */ +#define PORT_PC28 (_UL_(1) << 28) /**< \brief PORT Mask for PC28 */ +/* ========== PORT definition for CM4 peripheral ========== */ +#define PIN_PA30H_CM4_SWCLK _L_(30) /**< \brief CM4 signal: SWCLK on PA30 mux H */ +#define MUX_PA30H_CM4_SWCLK _L_(7) +#define PINMUX_PA30H_CM4_SWCLK ((PIN_PA30H_CM4_SWCLK << 16) | MUX_PA30H_CM4_SWCLK) +#define PORT_PA30H_CM4_SWCLK (_UL_(1) << 30) +#define PIN_PC27M_CM4_SWO _L_(91) /**< \brief CM4 signal: SWO on PC27 mux M */ +#define MUX_PC27M_CM4_SWO _L_(12) +#define PINMUX_PC27M_CM4_SWO ((PIN_PC27M_CM4_SWO << 16) | MUX_PC27M_CM4_SWO) +#define PORT_PC27M_CM4_SWO (_UL_(1) << 27) +#define PIN_PB30H_CM4_SWO _L_(62) /**< \brief CM4 signal: SWO on PB30 mux H */ +#define MUX_PB30H_CM4_SWO _L_(7) +#define PINMUX_PB30H_CM4_SWO ((PIN_PB30H_CM4_SWO << 16) | MUX_PB30H_CM4_SWO) +#define PORT_PB30H_CM4_SWO (_UL_(1) << 30) +#define PIN_PC27H_CM4_TRACECLK _L_(91) /**< \brief CM4 signal: TRACECLK on PC27 mux H */ +#define MUX_PC27H_CM4_TRACECLK _L_(7) +#define PINMUX_PC27H_CM4_TRACECLK ((PIN_PC27H_CM4_TRACECLK << 16) | MUX_PC27H_CM4_TRACECLK) +#define PORT_PC27H_CM4_TRACECLK (_UL_(1) << 27) +#define PIN_PC28H_CM4_TRACEDATA0 _L_(92) /**< \brief CM4 signal: TRACEDATA0 on PC28 mux H */ +#define MUX_PC28H_CM4_TRACEDATA0 _L_(7) +#define PINMUX_PC28H_CM4_TRACEDATA0 ((PIN_PC28H_CM4_TRACEDATA0 << 16) | MUX_PC28H_CM4_TRACEDATA0) +#define PORT_PC28H_CM4_TRACEDATA0 (_UL_(1) << 28) +#define PIN_PC26H_CM4_TRACEDATA1 _L_(90) /**< \brief CM4 signal: TRACEDATA1 on PC26 mux H */ +#define MUX_PC26H_CM4_TRACEDATA1 _L_(7) +#define PINMUX_PC26H_CM4_TRACEDATA1 ((PIN_PC26H_CM4_TRACEDATA1 << 16) | MUX_PC26H_CM4_TRACEDATA1) +#define PORT_PC26H_CM4_TRACEDATA1 (_UL_(1) << 26) +#define PIN_PC25H_CM4_TRACEDATA2 _L_(89) /**< \brief CM4 signal: TRACEDATA2 on PC25 mux H */ +#define MUX_PC25H_CM4_TRACEDATA2 _L_(7) +#define PINMUX_PC25H_CM4_TRACEDATA2 ((PIN_PC25H_CM4_TRACEDATA2 << 16) | MUX_PC25H_CM4_TRACEDATA2) +#define PORT_PC25H_CM4_TRACEDATA2 (_UL_(1) << 25) +#define PIN_PC24H_CM4_TRACEDATA3 _L_(88) /**< \brief CM4 signal: TRACEDATA3 on PC24 mux H */ +#define MUX_PC24H_CM4_TRACEDATA3 _L_(7) +#define PINMUX_PC24H_CM4_TRACEDATA3 ((PIN_PC24H_CM4_TRACEDATA3 << 16) | MUX_PC24H_CM4_TRACEDATA3) +#define PORT_PC24H_CM4_TRACEDATA3 (_UL_(1) << 24) +/* ========== PORT definition for ANAREF peripheral ========== */ +#define PIN_PA03B_ANAREF_VREF0 _L_(3) /**< \brief ANAREF signal: VREF0 on PA03 mux B */ +#define MUX_PA03B_ANAREF_VREF0 _L_(1) +#define PINMUX_PA03B_ANAREF_VREF0 ((PIN_PA03B_ANAREF_VREF0 << 16) | MUX_PA03B_ANAREF_VREF0) +#define PORT_PA03B_ANAREF_VREF0 (_UL_(1) << 3) +#define PIN_PA04B_ANAREF_VREF1 _L_(4) /**< \brief ANAREF signal: VREF1 on PA04 mux B */ +#define MUX_PA04B_ANAREF_VREF1 _L_(1) +#define PINMUX_PA04B_ANAREF_VREF1 ((PIN_PA04B_ANAREF_VREF1 << 16) | MUX_PA04B_ANAREF_VREF1) +#define PORT_PA04B_ANAREF_VREF1 (_UL_(1) << 4) +#define PIN_PA06B_ANAREF_VREF2 _L_(6) /**< \brief ANAREF signal: VREF2 on PA06 mux B */ +#define MUX_PA06B_ANAREF_VREF2 _L_(1) +#define PINMUX_PA06B_ANAREF_VREF2 ((PIN_PA06B_ANAREF_VREF2 << 16) | MUX_PA06B_ANAREF_VREF2) +#define PORT_PA06B_ANAREF_VREF2 (_UL_(1) << 6) +/* ========== PORT definition for GCLK peripheral ========== */ +#define PIN_PA30M_GCLK_IO0 _L_(30) /**< \brief GCLK signal: IO0 on PA30 mux M */ +#define MUX_PA30M_GCLK_IO0 _L_(12) +#define PINMUX_PA30M_GCLK_IO0 ((PIN_PA30M_GCLK_IO0 << 16) | MUX_PA30M_GCLK_IO0) +#define PORT_PA30M_GCLK_IO0 (_UL_(1) << 30) +#define PIN_PB14M_GCLK_IO0 _L_(46) /**< \brief GCLK signal: IO0 on PB14 mux M */ +#define MUX_PB14M_GCLK_IO0 _L_(12) +#define PINMUX_PB14M_GCLK_IO0 ((PIN_PB14M_GCLK_IO0 << 16) | MUX_PB14M_GCLK_IO0) +#define PORT_PB14M_GCLK_IO0 (_UL_(1) << 14) +#define PIN_PA14M_GCLK_IO0 _L_(14) /**< \brief GCLK signal: IO0 on PA14 mux M */ +#define MUX_PA14M_GCLK_IO0 _L_(12) +#define PINMUX_PA14M_GCLK_IO0 ((PIN_PA14M_GCLK_IO0 << 16) | MUX_PA14M_GCLK_IO0) +#define PORT_PA14M_GCLK_IO0 (_UL_(1) << 14) +#define PIN_PB22M_GCLK_IO0 _L_(54) /**< \brief GCLK signal: IO0 on PB22 mux M */ +#define MUX_PB22M_GCLK_IO0 _L_(12) +#define PINMUX_PB22M_GCLK_IO0 ((PIN_PB22M_GCLK_IO0 << 16) | MUX_PB22M_GCLK_IO0) +#define PORT_PB22M_GCLK_IO0 (_UL_(1) << 22) +#define PIN_PB15M_GCLK_IO1 _L_(47) /**< \brief GCLK signal: IO1 on PB15 mux M */ +#define MUX_PB15M_GCLK_IO1 _L_(12) +#define PINMUX_PB15M_GCLK_IO1 ((PIN_PB15M_GCLK_IO1 << 16) | MUX_PB15M_GCLK_IO1) +#define PORT_PB15M_GCLK_IO1 (_UL_(1) << 15) +#define PIN_PA15M_GCLK_IO1 _L_(15) /**< \brief GCLK signal: IO1 on PA15 mux M */ +#define MUX_PA15M_GCLK_IO1 _L_(12) +#define PINMUX_PA15M_GCLK_IO1 ((PIN_PA15M_GCLK_IO1 << 16) | MUX_PA15M_GCLK_IO1) +#define PORT_PA15M_GCLK_IO1 (_UL_(1) << 15) +#define PIN_PB23M_GCLK_IO1 _L_(55) /**< \brief GCLK signal: IO1 on PB23 mux M */ +#define MUX_PB23M_GCLK_IO1 _L_(12) +#define PINMUX_PB23M_GCLK_IO1 ((PIN_PB23M_GCLK_IO1 << 16) | MUX_PB23M_GCLK_IO1) +#define PORT_PB23M_GCLK_IO1 (_UL_(1) << 23) +#define PIN_PA27M_GCLK_IO1 _L_(27) /**< \brief GCLK signal: IO1 on PA27 mux M */ +#define MUX_PA27M_GCLK_IO1 _L_(12) +#define PINMUX_PA27M_GCLK_IO1 ((PIN_PA27M_GCLK_IO1 << 16) | MUX_PA27M_GCLK_IO1) +#define PORT_PA27M_GCLK_IO1 (_UL_(1) << 27) +#define PIN_PA16M_GCLK_IO2 _L_(16) /**< \brief GCLK signal: IO2 on PA16 mux M */ +#define MUX_PA16M_GCLK_IO2 _L_(12) +#define PINMUX_PA16M_GCLK_IO2 ((PIN_PA16M_GCLK_IO2 << 16) | MUX_PA16M_GCLK_IO2) +#define PORT_PA16M_GCLK_IO2 (_UL_(1) << 16) +#define PIN_PB16M_GCLK_IO2 _L_(48) /**< \brief GCLK signal: IO2 on PB16 mux M */ +#define MUX_PB16M_GCLK_IO2 _L_(12) +#define PINMUX_PB16M_GCLK_IO2 ((PIN_PB16M_GCLK_IO2 << 16) | MUX_PB16M_GCLK_IO2) +#define PORT_PB16M_GCLK_IO2 (_UL_(1) << 16) +#define PIN_PA17M_GCLK_IO3 _L_(17) /**< \brief GCLK signal: IO3 on PA17 mux M */ +#define MUX_PA17M_GCLK_IO3 _L_(12) +#define PINMUX_PA17M_GCLK_IO3 ((PIN_PA17M_GCLK_IO3 << 16) | MUX_PA17M_GCLK_IO3) +#define PORT_PA17M_GCLK_IO3 (_UL_(1) << 17) +#define PIN_PB17M_GCLK_IO3 _L_(49) /**< \brief GCLK signal: IO3 on PB17 mux M */ +#define MUX_PB17M_GCLK_IO3 _L_(12) +#define PINMUX_PB17M_GCLK_IO3 ((PIN_PB17M_GCLK_IO3 << 16) | MUX_PB17M_GCLK_IO3) +#define PORT_PB17M_GCLK_IO3 (_UL_(1) << 17) +#define PIN_PA10M_GCLK_IO4 _L_(10) /**< \brief GCLK signal: IO4 on PA10 mux M */ +#define MUX_PA10M_GCLK_IO4 _L_(12) +#define PINMUX_PA10M_GCLK_IO4 ((PIN_PA10M_GCLK_IO4 << 16) | MUX_PA10M_GCLK_IO4) +#define PORT_PA10M_GCLK_IO4 (_UL_(1) << 10) +#define PIN_PB10M_GCLK_IO4 _L_(42) /**< \brief GCLK signal: IO4 on PB10 mux M */ +#define MUX_PB10M_GCLK_IO4 _L_(12) +#define PINMUX_PB10M_GCLK_IO4 ((PIN_PB10M_GCLK_IO4 << 16) | MUX_PB10M_GCLK_IO4) +#define PORT_PB10M_GCLK_IO4 (_UL_(1) << 10) +#define PIN_PB18M_GCLK_IO4 _L_(50) /**< \brief GCLK signal: IO4 on PB18 mux M */ +#define MUX_PB18M_GCLK_IO4 _L_(12) +#define PINMUX_PB18M_GCLK_IO4 ((PIN_PB18M_GCLK_IO4 << 16) | MUX_PB18M_GCLK_IO4) +#define PORT_PB18M_GCLK_IO4 (_UL_(1) << 18) +#define PIN_PA11M_GCLK_IO5 _L_(11) /**< \brief GCLK signal: IO5 on PA11 mux M */ +#define MUX_PA11M_GCLK_IO5 _L_(12) +#define PINMUX_PA11M_GCLK_IO5 ((PIN_PA11M_GCLK_IO5 << 16) | MUX_PA11M_GCLK_IO5) +#define PORT_PA11M_GCLK_IO5 (_UL_(1) << 11) +#define PIN_PB11M_GCLK_IO5 _L_(43) /**< \brief GCLK signal: IO5 on PB11 mux M */ +#define MUX_PB11M_GCLK_IO5 _L_(12) +#define PINMUX_PB11M_GCLK_IO5 ((PIN_PB11M_GCLK_IO5 << 16) | MUX_PB11M_GCLK_IO5) +#define PORT_PB11M_GCLK_IO5 (_UL_(1) << 11) +#define PIN_PB19M_GCLK_IO5 _L_(51) /**< \brief GCLK signal: IO5 on PB19 mux M */ +#define MUX_PB19M_GCLK_IO5 _L_(12) +#define PINMUX_PB19M_GCLK_IO5 ((PIN_PB19M_GCLK_IO5 << 16) | MUX_PB19M_GCLK_IO5) +#define PORT_PB19M_GCLK_IO5 (_UL_(1) << 19) +#define PIN_PB12M_GCLK_IO6 _L_(44) /**< \brief GCLK signal: IO6 on PB12 mux M */ +#define MUX_PB12M_GCLK_IO6 _L_(12) +#define PINMUX_PB12M_GCLK_IO6 ((PIN_PB12M_GCLK_IO6 << 16) | MUX_PB12M_GCLK_IO6) +#define PORT_PB12M_GCLK_IO6 (_UL_(1) << 12) +#define PIN_PB20M_GCLK_IO6 _L_(52) /**< \brief GCLK signal: IO6 on PB20 mux M */ +#define MUX_PB20M_GCLK_IO6 _L_(12) +#define PINMUX_PB20M_GCLK_IO6 ((PIN_PB20M_GCLK_IO6 << 16) | MUX_PB20M_GCLK_IO6) +#define PORT_PB20M_GCLK_IO6 (_UL_(1) << 20) +#define PIN_PB13M_GCLK_IO7 _L_(45) /**< \brief GCLK signal: IO7 on PB13 mux M */ +#define MUX_PB13M_GCLK_IO7 _L_(12) +#define PINMUX_PB13M_GCLK_IO7 ((PIN_PB13M_GCLK_IO7 << 16) | MUX_PB13M_GCLK_IO7) +#define PORT_PB13M_GCLK_IO7 (_UL_(1) << 13) +#define PIN_PB21M_GCLK_IO7 _L_(53) /**< \brief GCLK signal: IO7 on PB21 mux M */ +#define MUX_PB21M_GCLK_IO7 _L_(12) +#define PINMUX_PB21M_GCLK_IO7 ((PIN_PB21M_GCLK_IO7 << 16) | MUX_PB21M_GCLK_IO7) +#define PORT_PB21M_GCLK_IO7 (_UL_(1) << 21) +/* ========== PORT definition for EIC peripheral ========== */ +#define PIN_PA00A_EIC_EXTINT0 _L_(0) /**< \brief EIC signal: EXTINT0 on PA00 mux A */ +#define MUX_PA00A_EIC_EXTINT0 _L_(0) +#define PINMUX_PA00A_EIC_EXTINT0 ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0) +#define PORT_PA00A_EIC_EXTINT0 (_UL_(1) << 0) +#define PIN_PA00A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PA00 External Interrupt Line */ +#define PIN_PA16A_EIC_EXTINT0 _L_(16) /**< \brief EIC signal: EXTINT0 on PA16 mux A */ +#define MUX_PA16A_EIC_EXTINT0 _L_(0) +#define PINMUX_PA16A_EIC_EXTINT0 ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0) +#define PORT_PA16A_EIC_EXTINT0 (_UL_(1) << 16) +#define PIN_PA16A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PA16 External Interrupt Line */ +#define PIN_PB00A_EIC_EXTINT0 _L_(32) /**< \brief EIC signal: EXTINT0 on PB00 mux A */ +#define MUX_PB00A_EIC_EXTINT0 _L_(0) +#define PINMUX_PB00A_EIC_EXTINT0 ((PIN_PB00A_EIC_EXTINT0 << 16) | MUX_PB00A_EIC_EXTINT0) +#define PORT_PB00A_EIC_EXTINT0 (_UL_(1) << 0) +#define PIN_PB00A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PB00 External Interrupt Line */ +#define PIN_PB16A_EIC_EXTINT0 _L_(48) /**< \brief EIC signal: EXTINT0 on PB16 mux A */ +#define MUX_PB16A_EIC_EXTINT0 _L_(0) +#define PINMUX_PB16A_EIC_EXTINT0 ((PIN_PB16A_EIC_EXTINT0 << 16) | MUX_PB16A_EIC_EXTINT0) +#define PORT_PB16A_EIC_EXTINT0 (_UL_(1) << 16) +#define PIN_PB16A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PB16 External Interrupt Line */ +#define PIN_PC00A_EIC_EXTINT0 _L_(64) /**< \brief EIC signal: EXTINT0 on PC00 mux A */ +#define MUX_PC00A_EIC_EXTINT0 _L_(0) +#define PINMUX_PC00A_EIC_EXTINT0 ((PIN_PC00A_EIC_EXTINT0 << 16) | MUX_PC00A_EIC_EXTINT0) +#define PORT_PC00A_EIC_EXTINT0 (_UL_(1) << 0) +#define PIN_PC00A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PC00 External Interrupt Line */ +#define PIN_PC16A_EIC_EXTINT0 _L_(80) /**< \brief EIC signal: EXTINT0 on PC16 mux A */ +#define MUX_PC16A_EIC_EXTINT0 _L_(0) +#define PINMUX_PC16A_EIC_EXTINT0 ((PIN_PC16A_EIC_EXTINT0 << 16) | MUX_PC16A_EIC_EXTINT0) +#define PORT_PC16A_EIC_EXTINT0 (_UL_(1) << 16) +#define PIN_PC16A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PC16 External Interrupt Line */ +#define PIN_PA01A_EIC_EXTINT1 _L_(1) /**< \brief EIC signal: EXTINT1 on PA01 mux A */ +#define MUX_PA01A_EIC_EXTINT1 _L_(0) +#define PINMUX_PA01A_EIC_EXTINT1 ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1) +#define PORT_PA01A_EIC_EXTINT1 (_UL_(1) << 1) +#define PIN_PA01A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PA01 External Interrupt Line */ +#define PIN_PA17A_EIC_EXTINT1 _L_(17) /**< \brief EIC signal: EXTINT1 on PA17 mux A */ +#define MUX_PA17A_EIC_EXTINT1 _L_(0) +#define PINMUX_PA17A_EIC_EXTINT1 ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1) +#define PORT_PA17A_EIC_EXTINT1 (_UL_(1) << 17) +#define PIN_PA17A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PA17 External Interrupt Line */ +#define PIN_PB01A_EIC_EXTINT1 _L_(33) /**< \brief EIC signal: EXTINT1 on PB01 mux A */ +#define MUX_PB01A_EIC_EXTINT1 _L_(0) +#define PINMUX_PB01A_EIC_EXTINT1 ((PIN_PB01A_EIC_EXTINT1 << 16) | MUX_PB01A_EIC_EXTINT1) +#define PORT_PB01A_EIC_EXTINT1 (_UL_(1) << 1) +#define PIN_PB01A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PB01 External Interrupt Line */ +#define PIN_PB17A_EIC_EXTINT1 _L_(49) /**< \brief EIC signal: EXTINT1 on PB17 mux A */ +#define MUX_PB17A_EIC_EXTINT1 _L_(0) +#define PINMUX_PB17A_EIC_EXTINT1 ((PIN_PB17A_EIC_EXTINT1 << 16) | MUX_PB17A_EIC_EXTINT1) +#define PORT_PB17A_EIC_EXTINT1 (_UL_(1) << 17) +#define PIN_PB17A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PB17 External Interrupt Line */ +#define PIN_PC01A_EIC_EXTINT1 _L_(65) /**< \brief EIC signal: EXTINT1 on PC01 mux A */ +#define MUX_PC01A_EIC_EXTINT1 _L_(0) +#define PINMUX_PC01A_EIC_EXTINT1 ((PIN_PC01A_EIC_EXTINT1 << 16) | MUX_PC01A_EIC_EXTINT1) +#define PORT_PC01A_EIC_EXTINT1 (_UL_(1) << 1) +#define PIN_PC01A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PC01 External Interrupt Line */ +#define PIN_PC17A_EIC_EXTINT1 _L_(81) /**< \brief EIC signal: EXTINT1 on PC17 mux A */ +#define MUX_PC17A_EIC_EXTINT1 _L_(0) +#define PINMUX_PC17A_EIC_EXTINT1 ((PIN_PC17A_EIC_EXTINT1 << 16) | MUX_PC17A_EIC_EXTINT1) +#define PORT_PC17A_EIC_EXTINT1 (_UL_(1) << 17) +#define PIN_PC17A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PC17 External Interrupt Line */ +#define PIN_PA02A_EIC_EXTINT2 _L_(2) /**< \brief EIC signal: EXTINT2 on PA02 mux A */ +#define MUX_PA02A_EIC_EXTINT2 _L_(0) +#define PINMUX_PA02A_EIC_EXTINT2 ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2) +#define PORT_PA02A_EIC_EXTINT2 (_UL_(1) << 2) +#define PIN_PA02A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PA02 External Interrupt Line */ +#define PIN_PA18A_EIC_EXTINT2 _L_(18) /**< \brief EIC signal: EXTINT2 on PA18 mux A */ +#define MUX_PA18A_EIC_EXTINT2 _L_(0) +#define PINMUX_PA18A_EIC_EXTINT2 ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2) +#define PORT_PA18A_EIC_EXTINT2 (_UL_(1) << 18) +#define PIN_PA18A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PA18 External Interrupt Line */ +#define PIN_PB02A_EIC_EXTINT2 _L_(34) /**< \brief EIC signal: EXTINT2 on PB02 mux A */ +#define MUX_PB02A_EIC_EXTINT2 _L_(0) +#define PINMUX_PB02A_EIC_EXTINT2 ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2) +#define PORT_PB02A_EIC_EXTINT2 (_UL_(1) << 2) +#define PIN_PB02A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PB02 External Interrupt Line */ +#define PIN_PB18A_EIC_EXTINT2 _L_(50) /**< \brief EIC signal: EXTINT2 on PB18 mux A */ +#define MUX_PB18A_EIC_EXTINT2 _L_(0) +#define PINMUX_PB18A_EIC_EXTINT2 ((PIN_PB18A_EIC_EXTINT2 << 16) | MUX_PB18A_EIC_EXTINT2) +#define PORT_PB18A_EIC_EXTINT2 (_UL_(1) << 18) +#define PIN_PB18A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PB18 External Interrupt Line */ +#define PIN_PC02A_EIC_EXTINT2 _L_(66) /**< \brief EIC signal: EXTINT2 on PC02 mux A */ +#define MUX_PC02A_EIC_EXTINT2 _L_(0) +#define PINMUX_PC02A_EIC_EXTINT2 ((PIN_PC02A_EIC_EXTINT2 << 16) | MUX_PC02A_EIC_EXTINT2) +#define PORT_PC02A_EIC_EXTINT2 (_UL_(1) << 2) +#define PIN_PC02A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PC02 External Interrupt Line */ +#define PIN_PC18A_EIC_EXTINT2 _L_(82) /**< \brief EIC signal: EXTINT2 on PC18 mux A */ +#define MUX_PC18A_EIC_EXTINT2 _L_(0) +#define PINMUX_PC18A_EIC_EXTINT2 ((PIN_PC18A_EIC_EXTINT2 << 16) | MUX_PC18A_EIC_EXTINT2) +#define PORT_PC18A_EIC_EXTINT2 (_UL_(1) << 18) +#define PIN_PC18A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PC18 External Interrupt Line */ +#define PIN_PA03A_EIC_EXTINT3 _L_(3) /**< \brief EIC signal: EXTINT3 on PA03 mux A */ +#define MUX_PA03A_EIC_EXTINT3 _L_(0) +#define PINMUX_PA03A_EIC_EXTINT3 ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3) +#define PORT_PA03A_EIC_EXTINT3 (_UL_(1) << 3) +#define PIN_PA03A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PA03 External Interrupt Line */ +#define PIN_PA19A_EIC_EXTINT3 _L_(19) /**< \brief EIC signal: EXTINT3 on PA19 mux A */ +#define MUX_PA19A_EIC_EXTINT3 _L_(0) +#define PINMUX_PA19A_EIC_EXTINT3 ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3) +#define PORT_PA19A_EIC_EXTINT3 (_UL_(1) << 19) +#define PIN_PA19A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PA19 External Interrupt Line */ +#define PIN_PB03A_EIC_EXTINT3 _L_(35) /**< \brief EIC signal: EXTINT3 on PB03 mux A */ +#define MUX_PB03A_EIC_EXTINT3 _L_(0) +#define PINMUX_PB03A_EIC_EXTINT3 ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3) +#define PORT_PB03A_EIC_EXTINT3 (_UL_(1) << 3) +#define PIN_PB03A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PB03 External Interrupt Line */ +#define PIN_PB19A_EIC_EXTINT3 _L_(51) /**< \brief EIC signal: EXTINT3 on PB19 mux A */ +#define MUX_PB19A_EIC_EXTINT3 _L_(0) +#define PINMUX_PB19A_EIC_EXTINT3 ((PIN_PB19A_EIC_EXTINT3 << 16) | MUX_PB19A_EIC_EXTINT3) +#define PORT_PB19A_EIC_EXTINT3 (_UL_(1) << 19) +#define PIN_PB19A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PB19 External Interrupt Line */ +#define PIN_PC03A_EIC_EXTINT3 _L_(67) /**< \brief EIC signal: EXTINT3 on PC03 mux A */ +#define MUX_PC03A_EIC_EXTINT3 _L_(0) +#define PINMUX_PC03A_EIC_EXTINT3 ((PIN_PC03A_EIC_EXTINT3 << 16) | MUX_PC03A_EIC_EXTINT3) +#define PORT_PC03A_EIC_EXTINT3 (_UL_(1) << 3) +#define PIN_PC03A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PC03 External Interrupt Line */ +#define PIN_PC19A_EIC_EXTINT3 _L_(83) /**< \brief EIC signal: EXTINT3 on PC19 mux A */ +#define MUX_PC19A_EIC_EXTINT3 _L_(0) +#define PINMUX_PC19A_EIC_EXTINT3 ((PIN_PC19A_EIC_EXTINT3 << 16) | MUX_PC19A_EIC_EXTINT3) +#define PORT_PC19A_EIC_EXTINT3 (_UL_(1) << 19) +#define PIN_PC19A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PC19 External Interrupt Line */ +#define PIN_PA04A_EIC_EXTINT4 _L_(4) /**< \brief EIC signal: EXTINT4 on PA04 mux A */ +#define MUX_PA04A_EIC_EXTINT4 _L_(0) +#define PINMUX_PA04A_EIC_EXTINT4 ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4) +#define PORT_PA04A_EIC_EXTINT4 (_UL_(1) << 4) +#define PIN_PA04A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PA04 External Interrupt Line */ +#define PIN_PA20A_EIC_EXTINT4 _L_(20) /**< \brief EIC signal: EXTINT4 on PA20 mux A */ +#define MUX_PA20A_EIC_EXTINT4 _L_(0) +#define PINMUX_PA20A_EIC_EXTINT4 ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4) +#define PORT_PA20A_EIC_EXTINT4 (_UL_(1) << 20) +#define PIN_PA20A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PA20 External Interrupt Line */ +#define PIN_PB04A_EIC_EXTINT4 _L_(36) /**< \brief EIC signal: EXTINT4 on PB04 mux A */ +#define MUX_PB04A_EIC_EXTINT4 _L_(0) +#define PINMUX_PB04A_EIC_EXTINT4 ((PIN_PB04A_EIC_EXTINT4 << 16) | MUX_PB04A_EIC_EXTINT4) +#define PORT_PB04A_EIC_EXTINT4 (_UL_(1) << 4) +#define PIN_PB04A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PB04 External Interrupt Line */ +#define PIN_PB20A_EIC_EXTINT4 _L_(52) /**< \brief EIC signal: EXTINT4 on PB20 mux A */ +#define MUX_PB20A_EIC_EXTINT4 _L_(0) +#define PINMUX_PB20A_EIC_EXTINT4 ((PIN_PB20A_EIC_EXTINT4 << 16) | MUX_PB20A_EIC_EXTINT4) +#define PORT_PB20A_EIC_EXTINT4 (_UL_(1) << 20) +#define PIN_PB20A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PB20 External Interrupt Line */ +#define PIN_PC20A_EIC_EXTINT4 _L_(84) /**< \brief EIC signal: EXTINT4 on PC20 mux A */ +#define MUX_PC20A_EIC_EXTINT4 _L_(0) +#define PINMUX_PC20A_EIC_EXTINT4 ((PIN_PC20A_EIC_EXTINT4 << 16) | MUX_PC20A_EIC_EXTINT4) +#define PORT_PC20A_EIC_EXTINT4 (_UL_(1) << 20) +#define PIN_PC20A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PC20 External Interrupt Line */ +#define PIN_PA05A_EIC_EXTINT5 _L_(5) /**< \brief EIC signal: EXTINT5 on PA05 mux A */ +#define MUX_PA05A_EIC_EXTINT5 _L_(0) +#define PINMUX_PA05A_EIC_EXTINT5 ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5) +#define PORT_PA05A_EIC_EXTINT5 (_UL_(1) << 5) +#define PIN_PA05A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PA05 External Interrupt Line */ +#define PIN_PA21A_EIC_EXTINT5 _L_(21) /**< \brief EIC signal: EXTINT5 on PA21 mux A */ +#define MUX_PA21A_EIC_EXTINT5 _L_(0) +#define PINMUX_PA21A_EIC_EXTINT5 ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5) +#define PORT_PA21A_EIC_EXTINT5 (_UL_(1) << 21) +#define PIN_PA21A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PA21 External Interrupt Line */ +#define PIN_PB05A_EIC_EXTINT5 _L_(37) /**< \brief EIC signal: EXTINT5 on PB05 mux A */ +#define MUX_PB05A_EIC_EXTINT5 _L_(0) +#define PINMUX_PB05A_EIC_EXTINT5 ((PIN_PB05A_EIC_EXTINT5 << 16) | MUX_PB05A_EIC_EXTINT5) +#define PORT_PB05A_EIC_EXTINT5 (_UL_(1) << 5) +#define PIN_PB05A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PB05 External Interrupt Line */ +#define PIN_PB21A_EIC_EXTINT5 _L_(53) /**< \brief EIC signal: EXTINT5 on PB21 mux A */ +#define MUX_PB21A_EIC_EXTINT5 _L_(0) +#define PINMUX_PB21A_EIC_EXTINT5 ((PIN_PB21A_EIC_EXTINT5 << 16) | MUX_PB21A_EIC_EXTINT5) +#define PORT_PB21A_EIC_EXTINT5 (_UL_(1) << 21) +#define PIN_PB21A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PB21 External Interrupt Line */ +#define PIN_PC05A_EIC_EXTINT5 _L_(69) /**< \brief EIC signal: EXTINT5 on PC05 mux A */ +#define MUX_PC05A_EIC_EXTINT5 _L_(0) +#define PINMUX_PC05A_EIC_EXTINT5 ((PIN_PC05A_EIC_EXTINT5 << 16) | MUX_PC05A_EIC_EXTINT5) +#define PORT_PC05A_EIC_EXTINT5 (_UL_(1) << 5) +#define PIN_PC05A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PC05 External Interrupt Line */ +#define PIN_PC21A_EIC_EXTINT5 _L_(85) /**< \brief EIC signal: EXTINT5 on PC21 mux A */ +#define MUX_PC21A_EIC_EXTINT5 _L_(0) +#define PINMUX_PC21A_EIC_EXTINT5 ((PIN_PC21A_EIC_EXTINT5 << 16) | MUX_PC21A_EIC_EXTINT5) +#define PORT_PC21A_EIC_EXTINT5 (_UL_(1) << 21) +#define PIN_PC21A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PC21 External Interrupt Line */ +#define PIN_PA06A_EIC_EXTINT6 _L_(6) /**< \brief EIC signal: EXTINT6 on PA06 mux A */ +#define MUX_PA06A_EIC_EXTINT6 _L_(0) +#define PINMUX_PA06A_EIC_EXTINT6 ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6) +#define PORT_PA06A_EIC_EXTINT6 (_UL_(1) << 6) +#define PIN_PA06A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PA06 External Interrupt Line */ +#define PIN_PA22A_EIC_EXTINT6 _L_(22) /**< \brief EIC signal: EXTINT6 on PA22 mux A */ +#define MUX_PA22A_EIC_EXTINT6 _L_(0) +#define PINMUX_PA22A_EIC_EXTINT6 ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6) +#define PORT_PA22A_EIC_EXTINT6 (_UL_(1) << 22) +#define PIN_PA22A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PA22 External Interrupt Line */ +#define PIN_PB06A_EIC_EXTINT6 _L_(38) /**< \brief EIC signal: EXTINT6 on PB06 mux A */ +#define MUX_PB06A_EIC_EXTINT6 _L_(0) +#define PINMUX_PB06A_EIC_EXTINT6 ((PIN_PB06A_EIC_EXTINT6 << 16) | MUX_PB06A_EIC_EXTINT6) +#define PORT_PB06A_EIC_EXTINT6 (_UL_(1) << 6) +#define PIN_PB06A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PB06 External Interrupt Line */ +#define PIN_PB22A_EIC_EXTINT6 _L_(54) /**< \brief EIC signal: EXTINT6 on PB22 mux A */ +#define MUX_PB22A_EIC_EXTINT6 _L_(0) +#define PINMUX_PB22A_EIC_EXTINT6 ((PIN_PB22A_EIC_EXTINT6 << 16) | MUX_PB22A_EIC_EXTINT6) +#define PORT_PB22A_EIC_EXTINT6 (_UL_(1) << 22) +#define PIN_PB22A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PB22 External Interrupt Line */ +#define PIN_PC06A_EIC_EXTINT6 _L_(70) /**< \brief EIC signal: EXTINT6 on PC06 mux A */ +#define MUX_PC06A_EIC_EXTINT6 _L_(0) +#define PINMUX_PC06A_EIC_EXTINT6 ((PIN_PC06A_EIC_EXTINT6 << 16) | MUX_PC06A_EIC_EXTINT6) +#define PORT_PC06A_EIC_EXTINT6 (_UL_(1) << 6) +#define PIN_PC06A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PC06 External Interrupt Line */ +#define PIN_PA07A_EIC_EXTINT7 _L_(7) /**< \brief EIC signal: EXTINT7 on PA07 mux A */ +#define MUX_PA07A_EIC_EXTINT7 _L_(0) +#define PINMUX_PA07A_EIC_EXTINT7 ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7) +#define PORT_PA07A_EIC_EXTINT7 (_UL_(1) << 7) +#define PIN_PA07A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PA07 External Interrupt Line */ +#define PIN_PA23A_EIC_EXTINT7 _L_(23) /**< \brief EIC signal: EXTINT7 on PA23 mux A */ +#define MUX_PA23A_EIC_EXTINT7 _L_(0) +#define PINMUX_PA23A_EIC_EXTINT7 ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7) +#define PORT_PA23A_EIC_EXTINT7 (_UL_(1) << 23) +#define PIN_PA23A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PA23 External Interrupt Line */ +#define PIN_PB07A_EIC_EXTINT7 _L_(39) /**< \brief EIC signal: EXTINT7 on PB07 mux A */ +#define MUX_PB07A_EIC_EXTINT7 _L_(0) +#define PINMUX_PB07A_EIC_EXTINT7 ((PIN_PB07A_EIC_EXTINT7 << 16) | MUX_PB07A_EIC_EXTINT7) +#define PORT_PB07A_EIC_EXTINT7 (_UL_(1) << 7) +#define PIN_PB07A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PB07 External Interrupt Line */ +#define PIN_PB23A_EIC_EXTINT7 _L_(55) /**< \brief EIC signal: EXTINT7 on PB23 mux A */ +#define MUX_PB23A_EIC_EXTINT7 _L_(0) +#define PINMUX_PB23A_EIC_EXTINT7 ((PIN_PB23A_EIC_EXTINT7 << 16) | MUX_PB23A_EIC_EXTINT7) +#define PORT_PB23A_EIC_EXTINT7 (_UL_(1) << 23) +#define PIN_PB23A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PB23 External Interrupt Line */ +#define PIN_PA24A_EIC_EXTINT8 _L_(24) /**< \brief EIC signal: EXTINT8 on PA24 mux A */ +#define MUX_PA24A_EIC_EXTINT8 _L_(0) +#define PINMUX_PA24A_EIC_EXTINT8 ((PIN_PA24A_EIC_EXTINT8 << 16) | MUX_PA24A_EIC_EXTINT8) +#define PORT_PA24A_EIC_EXTINT8 (_UL_(1) << 24) +#define PIN_PA24A_EIC_EXTINT_NUM _L_(8) /**< \brief EIC signal: PIN_PA24 External Interrupt Line */ +#define PIN_PB08A_EIC_EXTINT8 _L_(40) /**< \brief EIC signal: EXTINT8 on PB08 mux A */ +#define MUX_PB08A_EIC_EXTINT8 _L_(0) +#define PINMUX_PB08A_EIC_EXTINT8 ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8) +#define PORT_PB08A_EIC_EXTINT8 (_UL_(1) << 8) +#define PIN_PB08A_EIC_EXTINT_NUM _L_(8) /**< \brief EIC signal: PIN_PB08 External Interrupt Line */ +#define PIN_PB24A_EIC_EXTINT8 _L_(56) /**< \brief EIC signal: EXTINT8 on PB24 mux A */ +#define MUX_PB24A_EIC_EXTINT8 _L_(0) +#define PINMUX_PB24A_EIC_EXTINT8 ((PIN_PB24A_EIC_EXTINT8 << 16) | MUX_PB24A_EIC_EXTINT8) +#define PORT_PB24A_EIC_EXTINT8 (_UL_(1) << 24) +#define PIN_PB24A_EIC_EXTINT_NUM _L_(8) /**< \brief EIC signal: PIN_PB24 External Interrupt Line */ +#define PIN_PC24A_EIC_EXTINT8 _L_(88) /**< \brief EIC signal: EXTINT8 on PC24 mux A */ +#define MUX_PC24A_EIC_EXTINT8 _L_(0) +#define PINMUX_PC24A_EIC_EXTINT8 ((PIN_PC24A_EIC_EXTINT8 << 16) | MUX_PC24A_EIC_EXTINT8) +#define PORT_PC24A_EIC_EXTINT8 (_UL_(1) << 24) +#define PIN_PC24A_EIC_EXTINT_NUM _L_(8) /**< \brief EIC signal: PIN_PC24 External Interrupt Line */ +#define PIN_PA09A_EIC_EXTINT9 _L_(9) /**< \brief EIC signal: EXTINT9 on PA09 mux A */ +#define MUX_PA09A_EIC_EXTINT9 _L_(0) +#define PINMUX_PA09A_EIC_EXTINT9 ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9) +#define PORT_PA09A_EIC_EXTINT9 (_UL_(1) << 9) +#define PIN_PA09A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PA09 External Interrupt Line */ +#define PIN_PA25A_EIC_EXTINT9 _L_(25) /**< \brief EIC signal: EXTINT9 on PA25 mux A */ +#define MUX_PA25A_EIC_EXTINT9 _L_(0) +#define PINMUX_PA25A_EIC_EXTINT9 ((PIN_PA25A_EIC_EXTINT9 << 16) | MUX_PA25A_EIC_EXTINT9) +#define PORT_PA25A_EIC_EXTINT9 (_UL_(1) << 25) +#define PIN_PA25A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PA25 External Interrupt Line */ +#define PIN_PB09A_EIC_EXTINT9 _L_(41) /**< \brief EIC signal: EXTINT9 on PB09 mux A */ +#define MUX_PB09A_EIC_EXTINT9 _L_(0) +#define PINMUX_PB09A_EIC_EXTINT9 ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9) +#define PORT_PB09A_EIC_EXTINT9 (_UL_(1) << 9) +#define PIN_PB09A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PB09 External Interrupt Line */ +#define PIN_PB25A_EIC_EXTINT9 _L_(57) /**< \brief EIC signal: EXTINT9 on PB25 mux A */ +#define MUX_PB25A_EIC_EXTINT9 _L_(0) +#define PINMUX_PB25A_EIC_EXTINT9 ((PIN_PB25A_EIC_EXTINT9 << 16) | MUX_PB25A_EIC_EXTINT9) +#define PORT_PB25A_EIC_EXTINT9 (_UL_(1) << 25) +#define PIN_PB25A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PB25 External Interrupt Line */ +#define PIN_PC07A_EIC_EXTINT9 _L_(71) /**< \brief EIC signal: EXTINT9 on PC07 mux A */ +#define MUX_PC07A_EIC_EXTINT9 _L_(0) +#define PINMUX_PC07A_EIC_EXTINT9 ((PIN_PC07A_EIC_EXTINT9 << 16) | MUX_PC07A_EIC_EXTINT9) +#define PORT_PC07A_EIC_EXTINT9 (_UL_(1) << 7) +#define PIN_PC07A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PC07 External Interrupt Line */ +#define PIN_PC25A_EIC_EXTINT9 _L_(89) /**< \brief EIC signal: EXTINT9 on PC25 mux A */ +#define MUX_PC25A_EIC_EXTINT9 _L_(0) +#define PINMUX_PC25A_EIC_EXTINT9 ((PIN_PC25A_EIC_EXTINT9 << 16) | MUX_PC25A_EIC_EXTINT9) +#define PORT_PC25A_EIC_EXTINT9 (_UL_(1) << 25) +#define PIN_PC25A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PC25 External Interrupt Line */ +#define PIN_PA10A_EIC_EXTINT10 _L_(10) /**< \brief EIC signal: EXTINT10 on PA10 mux A */ +#define MUX_PA10A_EIC_EXTINT10 _L_(0) +#define PINMUX_PA10A_EIC_EXTINT10 ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10) +#define PORT_PA10A_EIC_EXTINT10 (_UL_(1) << 10) +#define PIN_PA10A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PA10 External Interrupt Line */ +#define PIN_PB10A_EIC_EXTINT10 _L_(42) /**< \brief EIC signal: EXTINT10 on PB10 mux A */ +#define MUX_PB10A_EIC_EXTINT10 _L_(0) +#define PINMUX_PB10A_EIC_EXTINT10 ((PIN_PB10A_EIC_EXTINT10 << 16) | MUX_PB10A_EIC_EXTINT10) +#define PORT_PB10A_EIC_EXTINT10 (_UL_(1) << 10) +#define PIN_PB10A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PB10 External Interrupt Line */ +#define PIN_PC10A_EIC_EXTINT10 _L_(74) /**< \brief EIC signal: EXTINT10 on PC10 mux A */ +#define MUX_PC10A_EIC_EXTINT10 _L_(0) +#define PINMUX_PC10A_EIC_EXTINT10 ((PIN_PC10A_EIC_EXTINT10 << 16) | MUX_PC10A_EIC_EXTINT10) +#define PORT_PC10A_EIC_EXTINT10 (_UL_(1) << 10) +#define PIN_PC10A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PC10 External Interrupt Line */ +#define PIN_PC26A_EIC_EXTINT10 _L_(90) /**< \brief EIC signal: EXTINT10 on PC26 mux A */ +#define MUX_PC26A_EIC_EXTINT10 _L_(0) +#define PINMUX_PC26A_EIC_EXTINT10 ((PIN_PC26A_EIC_EXTINT10 << 16) | MUX_PC26A_EIC_EXTINT10) +#define PORT_PC26A_EIC_EXTINT10 (_UL_(1) << 26) +#define PIN_PC26A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PC26 External Interrupt Line */ +#define PIN_PA11A_EIC_EXTINT11 _L_(11) /**< \brief EIC signal: EXTINT11 on PA11 mux A */ +#define MUX_PA11A_EIC_EXTINT11 _L_(0) +#define PINMUX_PA11A_EIC_EXTINT11 ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11) +#define PORT_PA11A_EIC_EXTINT11 (_UL_(1) << 11) +#define PIN_PA11A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PA11 External Interrupt Line */ +#define PIN_PA27A_EIC_EXTINT11 _L_(27) /**< \brief EIC signal: EXTINT11 on PA27 mux A */ +#define MUX_PA27A_EIC_EXTINT11 _L_(0) +#define PINMUX_PA27A_EIC_EXTINT11 ((PIN_PA27A_EIC_EXTINT11 << 16) | MUX_PA27A_EIC_EXTINT11) +#define PORT_PA27A_EIC_EXTINT11 (_UL_(1) << 27) +#define PIN_PA27A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PA27 External Interrupt Line */ +#define PIN_PB11A_EIC_EXTINT11 _L_(43) /**< \brief EIC signal: EXTINT11 on PB11 mux A */ +#define MUX_PB11A_EIC_EXTINT11 _L_(0) +#define PINMUX_PB11A_EIC_EXTINT11 ((PIN_PB11A_EIC_EXTINT11 << 16) | MUX_PB11A_EIC_EXTINT11) +#define PORT_PB11A_EIC_EXTINT11 (_UL_(1) << 11) +#define PIN_PB11A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PB11 External Interrupt Line */ +#define PIN_PC11A_EIC_EXTINT11 _L_(75) /**< \brief EIC signal: EXTINT11 on PC11 mux A */ +#define MUX_PC11A_EIC_EXTINT11 _L_(0) +#define PINMUX_PC11A_EIC_EXTINT11 ((PIN_PC11A_EIC_EXTINT11 << 16) | MUX_PC11A_EIC_EXTINT11) +#define PORT_PC11A_EIC_EXTINT11 (_UL_(1) << 11) +#define PIN_PC11A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PC11 External Interrupt Line */ +#define PIN_PC27A_EIC_EXTINT11 _L_(91) /**< \brief EIC signal: EXTINT11 on PC27 mux A */ +#define MUX_PC27A_EIC_EXTINT11 _L_(0) +#define PINMUX_PC27A_EIC_EXTINT11 ((PIN_PC27A_EIC_EXTINT11 << 16) | MUX_PC27A_EIC_EXTINT11) +#define PORT_PC27A_EIC_EXTINT11 (_UL_(1) << 27) +#define PIN_PC27A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PC27 External Interrupt Line */ +#define PIN_PA12A_EIC_EXTINT12 _L_(12) /**< \brief EIC signal: EXTINT12 on PA12 mux A */ +#define MUX_PA12A_EIC_EXTINT12 _L_(0) +#define PINMUX_PA12A_EIC_EXTINT12 ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12) +#define PORT_PA12A_EIC_EXTINT12 (_UL_(1) << 12) +#define PIN_PA12A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PA12 External Interrupt Line */ +#define PIN_PB12A_EIC_EXTINT12 _L_(44) /**< \brief EIC signal: EXTINT12 on PB12 mux A */ +#define MUX_PB12A_EIC_EXTINT12 _L_(0) +#define PINMUX_PB12A_EIC_EXTINT12 ((PIN_PB12A_EIC_EXTINT12 << 16) | MUX_PB12A_EIC_EXTINT12) +#define PORT_PB12A_EIC_EXTINT12 (_UL_(1) << 12) +#define PIN_PB12A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PB12 External Interrupt Line */ +#define PIN_PC12A_EIC_EXTINT12 _L_(76) /**< \brief EIC signal: EXTINT12 on PC12 mux A */ +#define MUX_PC12A_EIC_EXTINT12 _L_(0) +#define PINMUX_PC12A_EIC_EXTINT12 ((PIN_PC12A_EIC_EXTINT12 << 16) | MUX_PC12A_EIC_EXTINT12) +#define PORT_PC12A_EIC_EXTINT12 (_UL_(1) << 12) +#define PIN_PC12A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PC12 External Interrupt Line */ +#define PIN_PC28A_EIC_EXTINT12 _L_(92) /**< \brief EIC signal: EXTINT12 on PC28 mux A */ +#define MUX_PC28A_EIC_EXTINT12 _L_(0) +#define PINMUX_PC28A_EIC_EXTINT12 ((PIN_PC28A_EIC_EXTINT12 << 16) | MUX_PC28A_EIC_EXTINT12) +#define PORT_PC28A_EIC_EXTINT12 (_UL_(1) << 28) +#define PIN_PC28A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PC28 External Interrupt Line */ +#define PIN_PA13A_EIC_EXTINT13 _L_(13) /**< \brief EIC signal: EXTINT13 on PA13 mux A */ +#define MUX_PA13A_EIC_EXTINT13 _L_(0) +#define PINMUX_PA13A_EIC_EXTINT13 ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13) +#define PORT_PA13A_EIC_EXTINT13 (_UL_(1) << 13) +#define PIN_PA13A_EIC_EXTINT_NUM _L_(13) /**< \brief EIC signal: PIN_PA13 External Interrupt Line */ +#define PIN_PB13A_EIC_EXTINT13 _L_(45) /**< \brief EIC signal: EXTINT13 on PB13 mux A */ +#define MUX_PB13A_EIC_EXTINT13 _L_(0) +#define PINMUX_PB13A_EIC_EXTINT13 ((PIN_PB13A_EIC_EXTINT13 << 16) | MUX_PB13A_EIC_EXTINT13) +#define PORT_PB13A_EIC_EXTINT13 (_UL_(1) << 13) +#define PIN_PB13A_EIC_EXTINT_NUM _L_(13) /**< \brief EIC signal: PIN_PB13 External Interrupt Line */ +#define PIN_PC13A_EIC_EXTINT13 _L_(77) /**< \brief EIC signal: EXTINT13 on PC13 mux A */ +#define MUX_PC13A_EIC_EXTINT13 _L_(0) +#define PINMUX_PC13A_EIC_EXTINT13 ((PIN_PC13A_EIC_EXTINT13 << 16) | MUX_PC13A_EIC_EXTINT13) +#define PORT_PC13A_EIC_EXTINT13 (_UL_(1) << 13) +#define PIN_PC13A_EIC_EXTINT_NUM _L_(13) /**< \brief EIC signal: PIN_PC13 External Interrupt Line */ +#define PIN_PA30A_EIC_EXTINT14 _L_(30) /**< \brief EIC signal: EXTINT14 on PA30 mux A */ +#define MUX_PA30A_EIC_EXTINT14 _L_(0) +#define PINMUX_PA30A_EIC_EXTINT14 ((PIN_PA30A_EIC_EXTINT14 << 16) | MUX_PA30A_EIC_EXTINT14) +#define PORT_PA30A_EIC_EXTINT14 (_UL_(1) << 30) +#define PIN_PA30A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PA30 External Interrupt Line */ +#define PIN_PB14A_EIC_EXTINT14 _L_(46) /**< \brief EIC signal: EXTINT14 on PB14 mux A */ +#define MUX_PB14A_EIC_EXTINT14 _L_(0) +#define PINMUX_PB14A_EIC_EXTINT14 ((PIN_PB14A_EIC_EXTINT14 << 16) | MUX_PB14A_EIC_EXTINT14) +#define PORT_PB14A_EIC_EXTINT14 (_UL_(1) << 14) +#define PIN_PB14A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PB14 External Interrupt Line */ +#define PIN_PB30A_EIC_EXTINT14 _L_(62) /**< \brief EIC signal: EXTINT14 on PB30 mux A */ +#define MUX_PB30A_EIC_EXTINT14 _L_(0) +#define PINMUX_PB30A_EIC_EXTINT14 ((PIN_PB30A_EIC_EXTINT14 << 16) | MUX_PB30A_EIC_EXTINT14) +#define PORT_PB30A_EIC_EXTINT14 (_UL_(1) << 30) +#define PIN_PB30A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PB30 External Interrupt Line */ +#define PIN_PC14A_EIC_EXTINT14 _L_(78) /**< \brief EIC signal: EXTINT14 on PC14 mux A */ +#define MUX_PC14A_EIC_EXTINT14 _L_(0) +#define PINMUX_PC14A_EIC_EXTINT14 ((PIN_PC14A_EIC_EXTINT14 << 16) | MUX_PC14A_EIC_EXTINT14) +#define PORT_PC14A_EIC_EXTINT14 (_UL_(1) << 14) +#define PIN_PC14A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PC14 External Interrupt Line */ +#define PIN_PA14A_EIC_EXTINT14 _L_(14) /**< \brief EIC signal: EXTINT14 on PA14 mux A */ +#define MUX_PA14A_EIC_EXTINT14 _L_(0) +#define PINMUX_PA14A_EIC_EXTINT14 ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14) +#define PORT_PA14A_EIC_EXTINT14 (_UL_(1) << 14) +#define PIN_PA14A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PA14 External Interrupt Line */ +#define PIN_PA15A_EIC_EXTINT15 _L_(15) /**< \brief EIC signal: EXTINT15 on PA15 mux A */ +#define MUX_PA15A_EIC_EXTINT15 _L_(0) +#define PINMUX_PA15A_EIC_EXTINT15 ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15) +#define PORT_PA15A_EIC_EXTINT15 (_UL_(1) << 15) +#define PIN_PA15A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PA15 External Interrupt Line */ +#define PIN_PA31A_EIC_EXTINT15 _L_(31) /**< \brief EIC signal: EXTINT15 on PA31 mux A */ +#define MUX_PA31A_EIC_EXTINT15 _L_(0) +#define PINMUX_PA31A_EIC_EXTINT15 ((PIN_PA31A_EIC_EXTINT15 << 16) | MUX_PA31A_EIC_EXTINT15) +#define PORT_PA31A_EIC_EXTINT15 (_UL_(1) << 31) +#define PIN_PA31A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PA31 External Interrupt Line */ +#define PIN_PB15A_EIC_EXTINT15 _L_(47) /**< \brief EIC signal: EXTINT15 on PB15 mux A */ +#define MUX_PB15A_EIC_EXTINT15 _L_(0) +#define PINMUX_PB15A_EIC_EXTINT15 ((PIN_PB15A_EIC_EXTINT15 << 16) | MUX_PB15A_EIC_EXTINT15) +#define PORT_PB15A_EIC_EXTINT15 (_UL_(1) << 15) +#define PIN_PB15A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PB15 External Interrupt Line */ +#define PIN_PB31A_EIC_EXTINT15 _L_(63) /**< \brief EIC signal: EXTINT15 on PB31 mux A */ +#define MUX_PB31A_EIC_EXTINT15 _L_(0) +#define PINMUX_PB31A_EIC_EXTINT15 ((PIN_PB31A_EIC_EXTINT15 << 16) | MUX_PB31A_EIC_EXTINT15) +#define PORT_PB31A_EIC_EXTINT15 (_UL_(1) << 31) +#define PIN_PB31A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PB31 External Interrupt Line */ +#define PIN_PC15A_EIC_EXTINT15 _L_(79) /**< \brief EIC signal: EXTINT15 on PC15 mux A */ +#define MUX_PC15A_EIC_EXTINT15 _L_(0) +#define PINMUX_PC15A_EIC_EXTINT15 ((PIN_PC15A_EIC_EXTINT15 << 16) | MUX_PC15A_EIC_EXTINT15) +#define PORT_PC15A_EIC_EXTINT15 (_UL_(1) << 15) +#define PIN_PC15A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PC15 External Interrupt Line */ +#define PIN_PA08A_EIC_NMI _L_(8) /**< \brief EIC signal: NMI on PA08 mux A */ +#define MUX_PA08A_EIC_NMI _L_(0) +#define PINMUX_PA08A_EIC_NMI ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI) +#define PORT_PA08A_EIC_NMI (_UL_(1) << 8) +/* ========== PORT definition for SERCOM0 peripheral ========== */ +#define PIN_PA04D_SERCOM0_PAD0 _L_(4) /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */ +#define MUX_PA04D_SERCOM0_PAD0 _L_(3) +#define PINMUX_PA04D_SERCOM0_PAD0 ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0) +#define PORT_PA04D_SERCOM0_PAD0 (_UL_(1) << 4) +#define PIN_PC17D_SERCOM0_PAD0 _L_(81) /**< \brief SERCOM0 signal: PAD0 on PC17 mux D */ +#define MUX_PC17D_SERCOM0_PAD0 _L_(3) +#define PINMUX_PC17D_SERCOM0_PAD0 ((PIN_PC17D_SERCOM0_PAD0 << 16) | MUX_PC17D_SERCOM0_PAD0) +#define PORT_PC17D_SERCOM0_PAD0 (_UL_(1) << 17) +#define PIN_PA08C_SERCOM0_PAD0 _L_(8) /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */ +#define MUX_PA08C_SERCOM0_PAD0 _L_(2) +#define PINMUX_PA08C_SERCOM0_PAD0 ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0) +#define PORT_PA08C_SERCOM0_PAD0 (_UL_(1) << 8) +#define PIN_PB24C_SERCOM0_PAD0 _L_(56) /**< \brief SERCOM0 signal: PAD0 on PB24 mux C */ +#define MUX_PB24C_SERCOM0_PAD0 _L_(2) +#define PINMUX_PB24C_SERCOM0_PAD0 ((PIN_PB24C_SERCOM0_PAD0 << 16) | MUX_PB24C_SERCOM0_PAD0) +#define PORT_PB24C_SERCOM0_PAD0 (_UL_(1) << 24) +#define PIN_PA05D_SERCOM0_PAD1 _L_(5) /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */ +#define MUX_PA05D_SERCOM0_PAD1 _L_(3) +#define PINMUX_PA05D_SERCOM0_PAD1 ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1) +#define PORT_PA05D_SERCOM0_PAD1 (_UL_(1) << 5) +#define PIN_PC16D_SERCOM0_PAD1 _L_(80) /**< \brief SERCOM0 signal: PAD1 on PC16 mux D */ +#define MUX_PC16D_SERCOM0_PAD1 _L_(3) +#define PINMUX_PC16D_SERCOM0_PAD1 ((PIN_PC16D_SERCOM0_PAD1 << 16) | MUX_PC16D_SERCOM0_PAD1) +#define PORT_PC16D_SERCOM0_PAD1 (_UL_(1) << 16) +#define PIN_PA09C_SERCOM0_PAD1 _L_(9) /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */ +#define MUX_PA09C_SERCOM0_PAD1 _L_(2) +#define PINMUX_PA09C_SERCOM0_PAD1 ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1) +#define PORT_PA09C_SERCOM0_PAD1 (_UL_(1) << 9) +#define PIN_PB25C_SERCOM0_PAD1 _L_(57) /**< \brief SERCOM0 signal: PAD1 on PB25 mux C */ +#define MUX_PB25C_SERCOM0_PAD1 _L_(2) +#define PINMUX_PB25C_SERCOM0_PAD1 ((PIN_PB25C_SERCOM0_PAD1 << 16) | MUX_PB25C_SERCOM0_PAD1) +#define PORT_PB25C_SERCOM0_PAD1 (_UL_(1) << 25) +#define PIN_PA06D_SERCOM0_PAD2 _L_(6) /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */ +#define MUX_PA06D_SERCOM0_PAD2 _L_(3) +#define PINMUX_PA06D_SERCOM0_PAD2 ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2) +#define PORT_PA06D_SERCOM0_PAD2 (_UL_(1) << 6) +#define PIN_PC18D_SERCOM0_PAD2 _L_(82) /**< \brief SERCOM0 signal: PAD2 on PC18 mux D */ +#define MUX_PC18D_SERCOM0_PAD2 _L_(3) +#define PINMUX_PC18D_SERCOM0_PAD2 ((PIN_PC18D_SERCOM0_PAD2 << 16) | MUX_PC18D_SERCOM0_PAD2) +#define PORT_PC18D_SERCOM0_PAD2 (_UL_(1) << 18) +#define PIN_PA10C_SERCOM0_PAD2 _L_(10) /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */ +#define MUX_PA10C_SERCOM0_PAD2 _L_(2) +#define PINMUX_PA10C_SERCOM0_PAD2 ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2) +#define PORT_PA10C_SERCOM0_PAD2 (_UL_(1) << 10) +#define PIN_PC24C_SERCOM0_PAD2 _L_(88) /**< \brief SERCOM0 signal: PAD2 on PC24 mux C */ +#define MUX_PC24C_SERCOM0_PAD2 _L_(2) +#define PINMUX_PC24C_SERCOM0_PAD2 ((PIN_PC24C_SERCOM0_PAD2 << 16) | MUX_PC24C_SERCOM0_PAD2) +#define PORT_PC24C_SERCOM0_PAD2 (_UL_(1) << 24) +#define PIN_PA07D_SERCOM0_PAD3 _L_(7) /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */ +#define MUX_PA07D_SERCOM0_PAD3 _L_(3) +#define PINMUX_PA07D_SERCOM0_PAD3 ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3) +#define PORT_PA07D_SERCOM0_PAD3 (_UL_(1) << 7) +#define PIN_PC19D_SERCOM0_PAD3 _L_(83) /**< \brief SERCOM0 signal: PAD3 on PC19 mux D */ +#define MUX_PC19D_SERCOM0_PAD3 _L_(3) +#define PINMUX_PC19D_SERCOM0_PAD3 ((PIN_PC19D_SERCOM0_PAD3 << 16) | MUX_PC19D_SERCOM0_PAD3) +#define PORT_PC19D_SERCOM0_PAD3 (_UL_(1) << 19) +#define PIN_PA11C_SERCOM0_PAD3 _L_(11) /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */ +#define MUX_PA11C_SERCOM0_PAD3 _L_(2) +#define PINMUX_PA11C_SERCOM0_PAD3 ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3) +#define PORT_PA11C_SERCOM0_PAD3 (_UL_(1) << 11) +#define PIN_PC25C_SERCOM0_PAD3 _L_(89) /**< \brief SERCOM0 signal: PAD3 on PC25 mux C */ +#define MUX_PC25C_SERCOM0_PAD3 _L_(2) +#define PINMUX_PC25C_SERCOM0_PAD3 ((PIN_PC25C_SERCOM0_PAD3 << 16) | MUX_PC25C_SERCOM0_PAD3) +#define PORT_PC25C_SERCOM0_PAD3 (_UL_(1) << 25) +/* ========== PORT definition for SERCOM1 peripheral ========== */ +#define PIN_PA00D_SERCOM1_PAD0 _L_(0) /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */ +#define MUX_PA00D_SERCOM1_PAD0 _L_(3) +#define PINMUX_PA00D_SERCOM1_PAD0 ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0) +#define PORT_PA00D_SERCOM1_PAD0 (_UL_(1) << 0) +#define PIN_PA16C_SERCOM1_PAD0 _L_(16) /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */ +#define MUX_PA16C_SERCOM1_PAD0 _L_(2) +#define PINMUX_PA16C_SERCOM1_PAD0 ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0) +#define PORT_PA16C_SERCOM1_PAD0 (_UL_(1) << 16) +#define PIN_PC27C_SERCOM1_PAD0 _L_(91) /**< \brief SERCOM1 signal: PAD0 on PC27 mux C */ +#define MUX_PC27C_SERCOM1_PAD0 _L_(2) +#define PINMUX_PC27C_SERCOM1_PAD0 ((PIN_PC27C_SERCOM1_PAD0 << 16) | MUX_PC27C_SERCOM1_PAD0) +#define PORT_PC27C_SERCOM1_PAD0 (_UL_(1) << 27) +#define PIN_PA01D_SERCOM1_PAD1 _L_(1) /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */ +#define MUX_PA01D_SERCOM1_PAD1 _L_(3) +#define PINMUX_PA01D_SERCOM1_PAD1 ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1) +#define PORT_PA01D_SERCOM1_PAD1 (_UL_(1) << 1) +#define PIN_PA17C_SERCOM1_PAD1 _L_(17) /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */ +#define MUX_PA17C_SERCOM1_PAD1 _L_(2) +#define PINMUX_PA17C_SERCOM1_PAD1 ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1) +#define PORT_PA17C_SERCOM1_PAD1 (_UL_(1) << 17) +#define PIN_PC28C_SERCOM1_PAD1 _L_(92) /**< \brief SERCOM1 signal: PAD1 on PC28 mux C */ +#define MUX_PC28C_SERCOM1_PAD1 _L_(2) +#define PINMUX_PC28C_SERCOM1_PAD1 ((PIN_PC28C_SERCOM1_PAD1 << 16) | MUX_PC28C_SERCOM1_PAD1) +#define PORT_PC28C_SERCOM1_PAD1 (_UL_(1) << 28) +#define PIN_PA30D_SERCOM1_PAD2 _L_(30) /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */ +#define MUX_PA30D_SERCOM1_PAD2 _L_(3) +#define PINMUX_PA30D_SERCOM1_PAD2 ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2) +#define PORT_PA30D_SERCOM1_PAD2 (_UL_(1) << 30) +#define PIN_PA18C_SERCOM1_PAD2 _L_(18) /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */ +#define MUX_PA18C_SERCOM1_PAD2 _L_(2) +#define PINMUX_PA18C_SERCOM1_PAD2 ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2) +#define PORT_PA18C_SERCOM1_PAD2 (_UL_(1) << 18) +#define PIN_PB22C_SERCOM1_PAD2 _L_(54) /**< \brief SERCOM1 signal: PAD2 on PB22 mux C */ +#define MUX_PB22C_SERCOM1_PAD2 _L_(2) +#define PINMUX_PB22C_SERCOM1_PAD2 ((PIN_PB22C_SERCOM1_PAD2 << 16) | MUX_PB22C_SERCOM1_PAD2) +#define PORT_PB22C_SERCOM1_PAD2 (_UL_(1) << 22) +#define PIN_PA31D_SERCOM1_PAD3 _L_(31) /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */ +#define MUX_PA31D_SERCOM1_PAD3 _L_(3) +#define PINMUX_PA31D_SERCOM1_PAD3 ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3) +#define PORT_PA31D_SERCOM1_PAD3 (_UL_(1) << 31) +#define PIN_PA19C_SERCOM1_PAD3 _L_(19) /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */ +#define MUX_PA19C_SERCOM1_PAD3 _L_(2) +#define PINMUX_PA19C_SERCOM1_PAD3 ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3) +#define PORT_PA19C_SERCOM1_PAD3 (_UL_(1) << 19) +#define PIN_PB23C_SERCOM1_PAD3 _L_(55) /**< \brief SERCOM1 signal: PAD3 on PB23 mux C */ +#define MUX_PB23C_SERCOM1_PAD3 _L_(2) +#define PINMUX_PB23C_SERCOM1_PAD3 ((PIN_PB23C_SERCOM1_PAD3 << 16) | MUX_PB23C_SERCOM1_PAD3) +#define PORT_PB23C_SERCOM1_PAD3 (_UL_(1) << 23) +/* ========== PORT definition for TC0 peripheral ========== */ +#define PIN_PA04E_TC0_WO0 _L_(4) /**< \brief TC0 signal: WO0 on PA04 mux E */ +#define MUX_PA04E_TC0_WO0 _L_(4) +#define PINMUX_PA04E_TC0_WO0 ((PIN_PA04E_TC0_WO0 << 16) | MUX_PA04E_TC0_WO0) +#define PORT_PA04E_TC0_WO0 (_UL_(1) << 4) +#define PIN_PA08E_TC0_WO0 _L_(8) /**< \brief TC0 signal: WO0 on PA08 mux E */ +#define MUX_PA08E_TC0_WO0 _L_(4) +#define PINMUX_PA08E_TC0_WO0 ((PIN_PA08E_TC0_WO0 << 16) | MUX_PA08E_TC0_WO0) +#define PORT_PA08E_TC0_WO0 (_UL_(1) << 8) +#define PIN_PB30E_TC0_WO0 _L_(62) /**< \brief TC0 signal: WO0 on PB30 mux E */ +#define MUX_PB30E_TC0_WO0 _L_(4) +#define PINMUX_PB30E_TC0_WO0 ((PIN_PB30E_TC0_WO0 << 16) | MUX_PB30E_TC0_WO0) +#define PORT_PB30E_TC0_WO0 (_UL_(1) << 30) +#define PIN_PA05E_TC0_WO1 _L_(5) /**< \brief TC0 signal: WO1 on PA05 mux E */ +#define MUX_PA05E_TC0_WO1 _L_(4) +#define PINMUX_PA05E_TC0_WO1 ((PIN_PA05E_TC0_WO1 << 16) | MUX_PA05E_TC0_WO1) +#define PORT_PA05E_TC0_WO1 (_UL_(1) << 5) +#define PIN_PA09E_TC0_WO1 _L_(9) /**< \brief TC0 signal: WO1 on PA09 mux E */ +#define MUX_PA09E_TC0_WO1 _L_(4) +#define PINMUX_PA09E_TC0_WO1 ((PIN_PA09E_TC0_WO1 << 16) | MUX_PA09E_TC0_WO1) +#define PORT_PA09E_TC0_WO1 (_UL_(1) << 9) +#define PIN_PB31E_TC0_WO1 _L_(63) /**< \brief TC0 signal: WO1 on PB31 mux E */ +#define MUX_PB31E_TC0_WO1 _L_(4) +#define PINMUX_PB31E_TC0_WO1 ((PIN_PB31E_TC0_WO1 << 16) | MUX_PB31E_TC0_WO1) +#define PORT_PB31E_TC0_WO1 (_UL_(1) << 31) +/* ========== PORT definition for TC1 peripheral ========== */ +#define PIN_PA06E_TC1_WO0 _L_(6) /**< \brief TC1 signal: WO0 on PA06 mux E */ +#define MUX_PA06E_TC1_WO0 _L_(4) +#define PINMUX_PA06E_TC1_WO0 ((PIN_PA06E_TC1_WO0 << 16) | MUX_PA06E_TC1_WO0) +#define PORT_PA06E_TC1_WO0 (_UL_(1) << 6) +#define PIN_PA10E_TC1_WO0 _L_(10) /**< \brief TC1 signal: WO0 on PA10 mux E */ +#define MUX_PA10E_TC1_WO0 _L_(4) +#define PINMUX_PA10E_TC1_WO0 ((PIN_PA10E_TC1_WO0 << 16) | MUX_PA10E_TC1_WO0) +#define PORT_PA10E_TC1_WO0 (_UL_(1) << 10) +#define PIN_PA07E_TC1_WO1 _L_(7) /**< \brief TC1 signal: WO1 on PA07 mux E */ +#define MUX_PA07E_TC1_WO1 _L_(4) +#define PINMUX_PA07E_TC1_WO1 ((PIN_PA07E_TC1_WO1 << 16) | MUX_PA07E_TC1_WO1) +#define PORT_PA07E_TC1_WO1 (_UL_(1) << 7) +#define PIN_PA11E_TC1_WO1 _L_(11) /**< \brief TC1 signal: WO1 on PA11 mux E */ +#define MUX_PA11E_TC1_WO1 _L_(4) +#define PINMUX_PA11E_TC1_WO1 ((PIN_PA11E_TC1_WO1 << 16) | MUX_PA11E_TC1_WO1) +#define PORT_PA11E_TC1_WO1 (_UL_(1) << 11) +/* ========== PORT definition for USB peripheral ========== */ +#define PIN_PA24H_USB_DM _L_(24) /**< \brief USB signal: DM on PA24 mux H */ +#define MUX_PA24H_USB_DM _L_(7) +#define PINMUX_PA24H_USB_DM ((PIN_PA24H_USB_DM << 16) | MUX_PA24H_USB_DM) +#define PORT_PA24H_USB_DM (_UL_(1) << 24) +#define PIN_PA25H_USB_DP _L_(25) /**< \brief USB signal: DP on PA25 mux H */ +#define MUX_PA25H_USB_DP _L_(7) +#define PINMUX_PA25H_USB_DP ((PIN_PA25H_USB_DP << 16) | MUX_PA25H_USB_DP) +#define PORT_PA25H_USB_DP (_UL_(1) << 25) +#define PIN_PA23H_USB_SOF_1KHZ _L_(23) /**< \brief USB signal: SOF_1KHZ on PA23 mux H */ +#define MUX_PA23H_USB_SOF_1KHZ _L_(7) +#define PINMUX_PA23H_USB_SOF_1KHZ ((PIN_PA23H_USB_SOF_1KHZ << 16) | MUX_PA23H_USB_SOF_1KHZ) +#define PORT_PA23H_USB_SOF_1KHZ (_UL_(1) << 23) +#define PIN_PB22H_USB_SOF_1KHZ _L_(54) /**< \brief USB signal: SOF_1KHZ on PB22 mux H */ +#define MUX_PB22H_USB_SOF_1KHZ _L_(7) +#define PINMUX_PB22H_USB_SOF_1KHZ ((PIN_PB22H_USB_SOF_1KHZ << 16) | MUX_PB22H_USB_SOF_1KHZ) +#define PORT_PB22H_USB_SOF_1KHZ (_UL_(1) << 22) +/* ========== PORT definition for SERCOM2 peripheral ========== */ +#define PIN_PA09D_SERCOM2_PAD0 _L_(9) /**< \brief SERCOM2 signal: PAD0 on PA09 mux D */ +#define MUX_PA09D_SERCOM2_PAD0 _L_(3) +#define PINMUX_PA09D_SERCOM2_PAD0 ((PIN_PA09D_SERCOM2_PAD0 << 16) | MUX_PA09D_SERCOM2_PAD0) +#define PORT_PA09D_SERCOM2_PAD0 (_UL_(1) << 9) +#define PIN_PB25D_SERCOM2_PAD0 _L_(57) /**< \brief SERCOM2 signal: PAD0 on PB25 mux D */ +#define MUX_PB25D_SERCOM2_PAD0 _L_(3) +#define PINMUX_PB25D_SERCOM2_PAD0 ((PIN_PB25D_SERCOM2_PAD0 << 16) | MUX_PB25D_SERCOM2_PAD0) +#define PORT_PB25D_SERCOM2_PAD0 (_UL_(1) << 25) +#define PIN_PA12C_SERCOM2_PAD0 _L_(12) /**< \brief SERCOM2 signal: PAD0 on PA12 mux C */ +#define MUX_PA12C_SERCOM2_PAD0 _L_(2) +#define PINMUX_PA12C_SERCOM2_PAD0 ((PIN_PA12C_SERCOM2_PAD0 << 16) | MUX_PA12C_SERCOM2_PAD0) +#define PORT_PA12C_SERCOM2_PAD0 (_UL_(1) << 12) +#define PIN_PA08D_SERCOM2_PAD1 _L_(8) /**< \brief SERCOM2 signal: PAD1 on PA08 mux D */ +#define MUX_PA08D_SERCOM2_PAD1 _L_(3) +#define PINMUX_PA08D_SERCOM2_PAD1 ((PIN_PA08D_SERCOM2_PAD1 << 16) | MUX_PA08D_SERCOM2_PAD1) +#define PORT_PA08D_SERCOM2_PAD1 (_UL_(1) << 8) +#define PIN_PB24D_SERCOM2_PAD1 _L_(56) /**< \brief SERCOM2 signal: PAD1 on PB24 mux D */ +#define MUX_PB24D_SERCOM2_PAD1 _L_(3) +#define PINMUX_PB24D_SERCOM2_PAD1 ((PIN_PB24D_SERCOM2_PAD1 << 16) | MUX_PB24D_SERCOM2_PAD1) +#define PORT_PB24D_SERCOM2_PAD1 (_UL_(1) << 24) +#define PIN_PA13C_SERCOM2_PAD1 _L_(13) /**< \brief SERCOM2 signal: PAD1 on PA13 mux C */ +#define MUX_PA13C_SERCOM2_PAD1 _L_(2) +#define PINMUX_PA13C_SERCOM2_PAD1 ((PIN_PA13C_SERCOM2_PAD1 << 16) | MUX_PA13C_SERCOM2_PAD1) +#define PORT_PA13C_SERCOM2_PAD1 (_UL_(1) << 13) +#define PIN_PA10D_SERCOM2_PAD2 _L_(10) /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */ +#define MUX_PA10D_SERCOM2_PAD2 _L_(3) +#define PINMUX_PA10D_SERCOM2_PAD2 ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2) +#define PORT_PA10D_SERCOM2_PAD2 (_UL_(1) << 10) +#define PIN_PC24D_SERCOM2_PAD2 _L_(88) /**< \brief SERCOM2 signal: PAD2 on PC24 mux D */ +#define MUX_PC24D_SERCOM2_PAD2 _L_(3) +#define PINMUX_PC24D_SERCOM2_PAD2 ((PIN_PC24D_SERCOM2_PAD2 << 16) | MUX_PC24D_SERCOM2_PAD2) +#define PORT_PC24D_SERCOM2_PAD2 (_UL_(1) << 24) +#define PIN_PA14C_SERCOM2_PAD2 _L_(14) /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */ +#define MUX_PA14C_SERCOM2_PAD2 _L_(2) +#define PINMUX_PA14C_SERCOM2_PAD2 ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2) +#define PORT_PA14C_SERCOM2_PAD2 (_UL_(1) << 14) +#define PIN_PA11D_SERCOM2_PAD3 _L_(11) /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */ +#define MUX_PA11D_SERCOM2_PAD3 _L_(3) +#define PINMUX_PA11D_SERCOM2_PAD3 ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3) +#define PORT_PA11D_SERCOM2_PAD3 (_UL_(1) << 11) +#define PIN_PC25D_SERCOM2_PAD3 _L_(89) /**< \brief SERCOM2 signal: PAD3 on PC25 mux D */ +#define MUX_PC25D_SERCOM2_PAD3 _L_(3) +#define PINMUX_PC25D_SERCOM2_PAD3 ((PIN_PC25D_SERCOM2_PAD3 << 16) | MUX_PC25D_SERCOM2_PAD3) +#define PORT_PC25D_SERCOM2_PAD3 (_UL_(1) << 25) +#define PIN_PA15C_SERCOM2_PAD3 _L_(15) /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */ +#define MUX_PA15C_SERCOM2_PAD3 _L_(2) +#define PINMUX_PA15C_SERCOM2_PAD3 ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3) +#define PORT_PA15C_SERCOM2_PAD3 (_UL_(1) << 15) +/* ========== PORT definition for SERCOM3 peripheral ========== */ +#define PIN_PA17D_SERCOM3_PAD0 _L_(17) /**< \brief SERCOM3 signal: PAD0 on PA17 mux D */ +#define MUX_PA17D_SERCOM3_PAD0 _L_(3) +#define PINMUX_PA17D_SERCOM3_PAD0 ((PIN_PA17D_SERCOM3_PAD0 << 16) | MUX_PA17D_SERCOM3_PAD0) +#define PORT_PA17D_SERCOM3_PAD0 (_UL_(1) << 17) +#define PIN_PA22C_SERCOM3_PAD0 _L_(22) /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */ +#define MUX_PA22C_SERCOM3_PAD0 _L_(2) +#define PINMUX_PA22C_SERCOM3_PAD0 ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0) +#define PORT_PA22C_SERCOM3_PAD0 (_UL_(1) << 22) +#define PIN_PB20C_SERCOM3_PAD0 _L_(52) /**< \brief SERCOM3 signal: PAD0 on PB20 mux C */ +#define MUX_PB20C_SERCOM3_PAD0 _L_(2) +#define PINMUX_PB20C_SERCOM3_PAD0 ((PIN_PB20C_SERCOM3_PAD0 << 16) | MUX_PB20C_SERCOM3_PAD0) +#define PORT_PB20C_SERCOM3_PAD0 (_UL_(1) << 20) +#define PIN_PA16D_SERCOM3_PAD1 _L_(16) /**< \brief SERCOM3 signal: PAD1 on PA16 mux D */ +#define MUX_PA16D_SERCOM3_PAD1 _L_(3) +#define PINMUX_PA16D_SERCOM3_PAD1 ((PIN_PA16D_SERCOM3_PAD1 << 16) | MUX_PA16D_SERCOM3_PAD1) +#define PORT_PA16D_SERCOM3_PAD1 (_UL_(1) << 16) +#define PIN_PA23C_SERCOM3_PAD1 _L_(23) /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */ +#define MUX_PA23C_SERCOM3_PAD1 _L_(2) +#define PINMUX_PA23C_SERCOM3_PAD1 ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1) +#define PORT_PA23C_SERCOM3_PAD1 (_UL_(1) << 23) +#define PIN_PB21C_SERCOM3_PAD1 _L_(53) /**< \brief SERCOM3 signal: PAD1 on PB21 mux C */ +#define MUX_PB21C_SERCOM3_PAD1 _L_(2) +#define PINMUX_PB21C_SERCOM3_PAD1 ((PIN_PB21C_SERCOM3_PAD1 << 16) | MUX_PB21C_SERCOM3_PAD1) +#define PORT_PB21C_SERCOM3_PAD1 (_UL_(1) << 21) +#define PIN_PA18D_SERCOM3_PAD2 _L_(18) /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */ +#define MUX_PA18D_SERCOM3_PAD2 _L_(3) +#define PINMUX_PA18D_SERCOM3_PAD2 ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2) +#define PORT_PA18D_SERCOM3_PAD2 (_UL_(1) << 18) +#define PIN_PA20D_SERCOM3_PAD2 _L_(20) /**< \brief SERCOM3 signal: PAD2 on PA20 mux D */ +#define MUX_PA20D_SERCOM3_PAD2 _L_(3) +#define PINMUX_PA20D_SERCOM3_PAD2 ((PIN_PA20D_SERCOM3_PAD2 << 16) | MUX_PA20D_SERCOM3_PAD2) +#define PORT_PA20D_SERCOM3_PAD2 (_UL_(1) << 20) +#define PIN_PA24C_SERCOM3_PAD2 _L_(24) /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */ +#define MUX_PA24C_SERCOM3_PAD2 _L_(2) +#define PINMUX_PA24C_SERCOM3_PAD2 ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2) +#define PORT_PA24C_SERCOM3_PAD2 (_UL_(1) << 24) +#define PIN_PA19D_SERCOM3_PAD3 _L_(19) /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */ +#define MUX_PA19D_SERCOM3_PAD3 _L_(3) +#define PINMUX_PA19D_SERCOM3_PAD3 ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3) +#define PORT_PA19D_SERCOM3_PAD3 (_UL_(1) << 19) +#define PIN_PA21D_SERCOM3_PAD3 _L_(21) /**< \brief SERCOM3 signal: PAD3 on PA21 mux D */ +#define MUX_PA21D_SERCOM3_PAD3 _L_(3) +#define PINMUX_PA21D_SERCOM3_PAD3 ((PIN_PA21D_SERCOM3_PAD3 << 16) | MUX_PA21D_SERCOM3_PAD3) +#define PORT_PA21D_SERCOM3_PAD3 (_UL_(1) << 21) +#define PIN_PA25C_SERCOM3_PAD3 _L_(25) /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */ +#define MUX_PA25C_SERCOM3_PAD3 _L_(2) +#define PINMUX_PA25C_SERCOM3_PAD3 ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3) +#define PORT_PA25C_SERCOM3_PAD3 (_UL_(1) << 25) +/* ========== PORT definition for TCC0 peripheral ========== */ +#define PIN_PA20G_TCC0_WO0 _L_(20) /**< \brief TCC0 signal: WO0 on PA20 mux G */ +#define MUX_PA20G_TCC0_WO0 _L_(6) +#define PINMUX_PA20G_TCC0_WO0 ((PIN_PA20G_TCC0_WO0 << 16) | MUX_PA20G_TCC0_WO0) +#define PORT_PA20G_TCC0_WO0 (_UL_(1) << 20) +#define PIN_PB12G_TCC0_WO0 _L_(44) /**< \brief TCC0 signal: WO0 on PB12 mux G */ +#define MUX_PB12G_TCC0_WO0 _L_(6) +#define PINMUX_PB12G_TCC0_WO0 ((PIN_PB12G_TCC0_WO0 << 16) | MUX_PB12G_TCC0_WO0) +#define PORT_PB12G_TCC0_WO0 (_UL_(1) << 12) +#define PIN_PA08F_TCC0_WO0 _L_(8) /**< \brief TCC0 signal: WO0 on PA08 mux F */ +#define MUX_PA08F_TCC0_WO0 _L_(5) +#define PINMUX_PA08F_TCC0_WO0 ((PIN_PA08F_TCC0_WO0 << 16) | MUX_PA08F_TCC0_WO0) +#define PORT_PA08F_TCC0_WO0 (_UL_(1) << 8) +#define PIN_PC10F_TCC0_WO0 _L_(74) /**< \brief TCC0 signal: WO0 on PC10 mux F */ +#define MUX_PC10F_TCC0_WO0 _L_(5) +#define PINMUX_PC10F_TCC0_WO0 ((PIN_PC10F_TCC0_WO0 << 16) | MUX_PC10F_TCC0_WO0) +#define PORT_PC10F_TCC0_WO0 (_UL_(1) << 10) +#define PIN_PC16F_TCC0_WO0 _L_(80) /**< \brief TCC0 signal: WO0 on PC16 mux F */ +#define MUX_PC16F_TCC0_WO0 _L_(5) +#define PINMUX_PC16F_TCC0_WO0 ((PIN_PC16F_TCC0_WO0 << 16) | MUX_PC16F_TCC0_WO0) +#define PORT_PC16F_TCC0_WO0 (_UL_(1) << 16) +#define PIN_PA21G_TCC0_WO1 _L_(21) /**< \brief TCC0 signal: WO1 on PA21 mux G */ +#define MUX_PA21G_TCC0_WO1 _L_(6) +#define PINMUX_PA21G_TCC0_WO1 ((PIN_PA21G_TCC0_WO1 << 16) | MUX_PA21G_TCC0_WO1) +#define PORT_PA21G_TCC0_WO1 (_UL_(1) << 21) +#define PIN_PB13G_TCC0_WO1 _L_(45) /**< \brief TCC0 signal: WO1 on PB13 mux G */ +#define MUX_PB13G_TCC0_WO1 _L_(6) +#define PINMUX_PB13G_TCC0_WO1 ((PIN_PB13G_TCC0_WO1 << 16) | MUX_PB13G_TCC0_WO1) +#define PORT_PB13G_TCC0_WO1 (_UL_(1) << 13) +#define PIN_PA09F_TCC0_WO1 _L_(9) /**< \brief TCC0 signal: WO1 on PA09 mux F */ +#define MUX_PA09F_TCC0_WO1 _L_(5) +#define PINMUX_PA09F_TCC0_WO1 ((PIN_PA09F_TCC0_WO1 << 16) | MUX_PA09F_TCC0_WO1) +#define PORT_PA09F_TCC0_WO1 (_UL_(1) << 9) +#define PIN_PC11F_TCC0_WO1 _L_(75) /**< \brief TCC0 signal: WO1 on PC11 mux F */ +#define MUX_PC11F_TCC0_WO1 _L_(5) +#define PINMUX_PC11F_TCC0_WO1 ((PIN_PC11F_TCC0_WO1 << 16) | MUX_PC11F_TCC0_WO1) +#define PORT_PC11F_TCC0_WO1 (_UL_(1) << 11) +#define PIN_PC17F_TCC0_WO1 _L_(81) /**< \brief TCC0 signal: WO1 on PC17 mux F */ +#define MUX_PC17F_TCC0_WO1 _L_(5) +#define PINMUX_PC17F_TCC0_WO1 ((PIN_PC17F_TCC0_WO1 << 16) | MUX_PC17F_TCC0_WO1) +#define PORT_PC17F_TCC0_WO1 (_UL_(1) << 17) +#define PIN_PA22G_TCC0_WO2 _L_(22) /**< \brief TCC0 signal: WO2 on PA22 mux G */ +#define MUX_PA22G_TCC0_WO2 _L_(6) +#define PINMUX_PA22G_TCC0_WO2 ((PIN_PA22G_TCC0_WO2 << 16) | MUX_PA22G_TCC0_WO2) +#define PORT_PA22G_TCC0_WO2 (_UL_(1) << 22) +#define PIN_PB14G_TCC0_WO2 _L_(46) /**< \brief TCC0 signal: WO2 on PB14 mux G */ +#define MUX_PB14G_TCC0_WO2 _L_(6) +#define PINMUX_PB14G_TCC0_WO2 ((PIN_PB14G_TCC0_WO2 << 16) | MUX_PB14G_TCC0_WO2) +#define PORT_PB14G_TCC0_WO2 (_UL_(1) << 14) +#define PIN_PA10F_TCC0_WO2 _L_(10) /**< \brief TCC0 signal: WO2 on PA10 mux F */ +#define MUX_PA10F_TCC0_WO2 _L_(5) +#define PINMUX_PA10F_TCC0_WO2 ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2) +#define PORT_PA10F_TCC0_WO2 (_UL_(1) << 10) +#define PIN_PC12F_TCC0_WO2 _L_(76) /**< \brief TCC0 signal: WO2 on PC12 mux F */ +#define MUX_PC12F_TCC0_WO2 _L_(5) +#define PINMUX_PC12F_TCC0_WO2 ((PIN_PC12F_TCC0_WO2 << 16) | MUX_PC12F_TCC0_WO2) +#define PORT_PC12F_TCC0_WO2 (_UL_(1) << 12) +#define PIN_PC18F_TCC0_WO2 _L_(82) /**< \brief TCC0 signal: WO2 on PC18 mux F */ +#define MUX_PC18F_TCC0_WO2 _L_(5) +#define PINMUX_PC18F_TCC0_WO2 ((PIN_PC18F_TCC0_WO2 << 16) | MUX_PC18F_TCC0_WO2) +#define PORT_PC18F_TCC0_WO2 (_UL_(1) << 18) +#define PIN_PA23G_TCC0_WO3 _L_(23) /**< \brief TCC0 signal: WO3 on PA23 mux G */ +#define MUX_PA23G_TCC0_WO3 _L_(6) +#define PINMUX_PA23G_TCC0_WO3 ((PIN_PA23G_TCC0_WO3 << 16) | MUX_PA23G_TCC0_WO3) +#define PORT_PA23G_TCC0_WO3 (_UL_(1) << 23) +#define PIN_PB15G_TCC0_WO3 _L_(47) /**< \brief TCC0 signal: WO3 on PB15 mux G */ +#define MUX_PB15G_TCC0_WO3 _L_(6) +#define PINMUX_PB15G_TCC0_WO3 ((PIN_PB15G_TCC0_WO3 << 16) | MUX_PB15G_TCC0_WO3) +#define PORT_PB15G_TCC0_WO3 (_UL_(1) << 15) +#define PIN_PA11F_TCC0_WO3 _L_(11) /**< \brief TCC0 signal: WO3 on PA11 mux F */ +#define MUX_PA11F_TCC0_WO3 _L_(5) +#define PINMUX_PA11F_TCC0_WO3 ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3) +#define PORT_PA11F_TCC0_WO3 (_UL_(1) << 11) +#define PIN_PC13F_TCC0_WO3 _L_(77) /**< \brief TCC0 signal: WO3 on PC13 mux F */ +#define MUX_PC13F_TCC0_WO3 _L_(5) +#define PINMUX_PC13F_TCC0_WO3 ((PIN_PC13F_TCC0_WO3 << 16) | MUX_PC13F_TCC0_WO3) +#define PORT_PC13F_TCC0_WO3 (_UL_(1) << 13) +#define PIN_PC19F_TCC0_WO3 _L_(83) /**< \brief TCC0 signal: WO3 on PC19 mux F */ +#define MUX_PC19F_TCC0_WO3 _L_(5) +#define PINMUX_PC19F_TCC0_WO3 ((PIN_PC19F_TCC0_WO3 << 16) | MUX_PC19F_TCC0_WO3) +#define PORT_PC19F_TCC0_WO3 (_UL_(1) << 19) +#define PIN_PA16G_TCC0_WO4 _L_(16) /**< \brief TCC0 signal: WO4 on PA16 mux G */ +#define MUX_PA16G_TCC0_WO4 _L_(6) +#define PINMUX_PA16G_TCC0_WO4 ((PIN_PA16G_TCC0_WO4 << 16) | MUX_PA16G_TCC0_WO4) +#define PORT_PA16G_TCC0_WO4 (_UL_(1) << 16) +#define PIN_PB16G_TCC0_WO4 _L_(48) /**< \brief TCC0 signal: WO4 on PB16 mux G */ +#define MUX_PB16G_TCC0_WO4 _L_(6) +#define PINMUX_PB16G_TCC0_WO4 ((PIN_PB16G_TCC0_WO4 << 16) | MUX_PB16G_TCC0_WO4) +#define PORT_PB16G_TCC0_WO4 (_UL_(1) << 16) +#define PIN_PB10F_TCC0_WO4 _L_(42) /**< \brief TCC0 signal: WO4 on PB10 mux F */ +#define MUX_PB10F_TCC0_WO4 _L_(5) +#define PINMUX_PB10F_TCC0_WO4 ((PIN_PB10F_TCC0_WO4 << 16) | MUX_PB10F_TCC0_WO4) +#define PORT_PB10F_TCC0_WO4 (_UL_(1) << 10) +#define PIN_PC14F_TCC0_WO4 _L_(78) /**< \brief TCC0 signal: WO4 on PC14 mux F */ +#define MUX_PC14F_TCC0_WO4 _L_(5) +#define PINMUX_PC14F_TCC0_WO4 ((PIN_PC14F_TCC0_WO4 << 16) | MUX_PC14F_TCC0_WO4) +#define PORT_PC14F_TCC0_WO4 (_UL_(1) << 14) +#define PIN_PC20F_TCC0_WO4 _L_(84) /**< \brief TCC0 signal: WO4 on PC20 mux F */ +#define MUX_PC20F_TCC0_WO4 _L_(5) +#define PINMUX_PC20F_TCC0_WO4 ((PIN_PC20F_TCC0_WO4 << 16) | MUX_PC20F_TCC0_WO4) +#define PORT_PC20F_TCC0_WO4 (_UL_(1) << 20) +#define PIN_PA17G_TCC0_WO5 _L_(17) /**< \brief TCC0 signal: WO5 on PA17 mux G */ +#define MUX_PA17G_TCC0_WO5 _L_(6) +#define PINMUX_PA17G_TCC0_WO5 ((PIN_PA17G_TCC0_WO5 << 16) | MUX_PA17G_TCC0_WO5) +#define PORT_PA17G_TCC0_WO5 (_UL_(1) << 17) +#define PIN_PB17G_TCC0_WO5 _L_(49) /**< \brief TCC0 signal: WO5 on PB17 mux G */ +#define MUX_PB17G_TCC0_WO5 _L_(6) +#define PINMUX_PB17G_TCC0_WO5 ((PIN_PB17G_TCC0_WO5 << 16) | MUX_PB17G_TCC0_WO5) +#define PORT_PB17G_TCC0_WO5 (_UL_(1) << 17) +#define PIN_PB11F_TCC0_WO5 _L_(43) /**< \brief TCC0 signal: WO5 on PB11 mux F */ +#define MUX_PB11F_TCC0_WO5 _L_(5) +#define PINMUX_PB11F_TCC0_WO5 ((PIN_PB11F_TCC0_WO5 << 16) | MUX_PB11F_TCC0_WO5) +#define PORT_PB11F_TCC0_WO5 (_UL_(1) << 11) +#define PIN_PC15F_TCC0_WO5 _L_(79) /**< \brief TCC0 signal: WO5 on PC15 mux F */ +#define MUX_PC15F_TCC0_WO5 _L_(5) +#define PINMUX_PC15F_TCC0_WO5 ((PIN_PC15F_TCC0_WO5 << 16) | MUX_PC15F_TCC0_WO5) +#define PORT_PC15F_TCC0_WO5 (_UL_(1) << 15) +#define PIN_PC21F_TCC0_WO5 _L_(85) /**< \brief TCC0 signal: WO5 on PC21 mux F */ +#define MUX_PC21F_TCC0_WO5 _L_(5) +#define PINMUX_PC21F_TCC0_WO5 ((PIN_PC21F_TCC0_WO5 << 16) | MUX_PC21F_TCC0_WO5) +#define PORT_PC21F_TCC0_WO5 (_UL_(1) << 21) +#define PIN_PA18G_TCC0_WO6 _L_(18) /**< \brief TCC0 signal: WO6 on PA18 mux G */ +#define MUX_PA18G_TCC0_WO6 _L_(6) +#define PINMUX_PA18G_TCC0_WO6 ((PIN_PA18G_TCC0_WO6 << 16) | MUX_PA18G_TCC0_WO6) +#define PORT_PA18G_TCC0_WO6 (_UL_(1) << 18) +#define PIN_PB30G_TCC0_WO6 _L_(62) /**< \brief TCC0 signal: WO6 on PB30 mux G */ +#define MUX_PB30G_TCC0_WO6 _L_(6) +#define PINMUX_PB30G_TCC0_WO6 ((PIN_PB30G_TCC0_WO6 << 16) | MUX_PB30G_TCC0_WO6) +#define PORT_PB30G_TCC0_WO6 (_UL_(1) << 30) +#define PIN_PA12F_TCC0_WO6 _L_(12) /**< \brief TCC0 signal: WO6 on PA12 mux F */ +#define MUX_PA12F_TCC0_WO6 _L_(5) +#define PINMUX_PA12F_TCC0_WO6 ((PIN_PA12F_TCC0_WO6 << 16) | MUX_PA12F_TCC0_WO6) +#define PORT_PA12F_TCC0_WO6 (_UL_(1) << 12) +#define PIN_PA19G_TCC0_WO7 _L_(19) /**< \brief TCC0 signal: WO7 on PA19 mux G */ +#define MUX_PA19G_TCC0_WO7 _L_(6) +#define PINMUX_PA19G_TCC0_WO7 ((PIN_PA19G_TCC0_WO7 << 16) | MUX_PA19G_TCC0_WO7) +#define PORT_PA19G_TCC0_WO7 (_UL_(1) << 19) +#define PIN_PB31G_TCC0_WO7 _L_(63) /**< \brief TCC0 signal: WO7 on PB31 mux G */ +#define MUX_PB31G_TCC0_WO7 _L_(6) +#define PINMUX_PB31G_TCC0_WO7 ((PIN_PB31G_TCC0_WO7 << 16) | MUX_PB31G_TCC0_WO7) +#define PORT_PB31G_TCC0_WO7 (_UL_(1) << 31) +#define PIN_PA13F_TCC0_WO7 _L_(13) /**< \brief TCC0 signal: WO7 on PA13 mux F */ +#define MUX_PA13F_TCC0_WO7 _L_(5) +#define PINMUX_PA13F_TCC0_WO7 ((PIN_PA13F_TCC0_WO7 << 16) | MUX_PA13F_TCC0_WO7) +#define PORT_PA13F_TCC0_WO7 (_UL_(1) << 13) +/* ========== PORT definition for TCC1 peripheral ========== */ +#define PIN_PB10G_TCC1_WO0 _L_(42) /**< \brief TCC1 signal: WO0 on PB10 mux G */ +#define MUX_PB10G_TCC1_WO0 _L_(6) +#define PINMUX_PB10G_TCC1_WO0 ((PIN_PB10G_TCC1_WO0 << 16) | MUX_PB10G_TCC1_WO0) +#define PORT_PB10G_TCC1_WO0 (_UL_(1) << 10) +#define PIN_PC14G_TCC1_WO0 _L_(78) /**< \brief TCC1 signal: WO0 on PC14 mux G */ +#define MUX_PC14G_TCC1_WO0 _L_(6) +#define PINMUX_PC14G_TCC1_WO0 ((PIN_PC14G_TCC1_WO0 << 16) | MUX_PC14G_TCC1_WO0) +#define PORT_PC14G_TCC1_WO0 (_UL_(1) << 14) +#define PIN_PA16F_TCC1_WO0 _L_(16) /**< \brief TCC1 signal: WO0 on PA16 mux F */ +#define MUX_PA16F_TCC1_WO0 _L_(5) +#define PINMUX_PA16F_TCC1_WO0 ((PIN_PA16F_TCC1_WO0 << 16) | MUX_PA16F_TCC1_WO0) +#define PORT_PA16F_TCC1_WO0 (_UL_(1) << 16) +#define PIN_PB18F_TCC1_WO0 _L_(50) /**< \brief TCC1 signal: WO0 on PB18 mux F */ +#define MUX_PB18F_TCC1_WO0 _L_(5) +#define PINMUX_PB18F_TCC1_WO0 ((PIN_PB18F_TCC1_WO0 << 16) | MUX_PB18F_TCC1_WO0) +#define PORT_PB18F_TCC1_WO0 (_UL_(1) << 18) +#define PIN_PB11G_TCC1_WO1 _L_(43) /**< \brief TCC1 signal: WO1 on PB11 mux G */ +#define MUX_PB11G_TCC1_WO1 _L_(6) +#define PINMUX_PB11G_TCC1_WO1 ((PIN_PB11G_TCC1_WO1 << 16) | MUX_PB11G_TCC1_WO1) +#define PORT_PB11G_TCC1_WO1 (_UL_(1) << 11) +#define PIN_PC15G_TCC1_WO1 _L_(79) /**< \brief TCC1 signal: WO1 on PC15 mux G */ +#define MUX_PC15G_TCC1_WO1 _L_(6) +#define PINMUX_PC15G_TCC1_WO1 ((PIN_PC15G_TCC1_WO1 << 16) | MUX_PC15G_TCC1_WO1) +#define PORT_PC15G_TCC1_WO1 (_UL_(1) << 15) +#define PIN_PA17F_TCC1_WO1 _L_(17) /**< \brief TCC1 signal: WO1 on PA17 mux F */ +#define MUX_PA17F_TCC1_WO1 _L_(5) +#define PINMUX_PA17F_TCC1_WO1 ((PIN_PA17F_TCC1_WO1 << 16) | MUX_PA17F_TCC1_WO1) +#define PORT_PA17F_TCC1_WO1 (_UL_(1) << 17) +#define PIN_PB19F_TCC1_WO1 _L_(51) /**< \brief TCC1 signal: WO1 on PB19 mux F */ +#define MUX_PB19F_TCC1_WO1 _L_(5) +#define PINMUX_PB19F_TCC1_WO1 ((PIN_PB19F_TCC1_WO1 << 16) | MUX_PB19F_TCC1_WO1) +#define PORT_PB19F_TCC1_WO1 (_UL_(1) << 19) +#define PIN_PA12G_TCC1_WO2 _L_(12) /**< \brief TCC1 signal: WO2 on PA12 mux G */ +#define MUX_PA12G_TCC1_WO2 _L_(6) +#define PINMUX_PA12G_TCC1_WO2 ((PIN_PA12G_TCC1_WO2 << 16) | MUX_PA12G_TCC1_WO2) +#define PORT_PA12G_TCC1_WO2 (_UL_(1) << 12) +#define PIN_PA14G_TCC1_WO2 _L_(14) /**< \brief TCC1 signal: WO2 on PA14 mux G */ +#define MUX_PA14G_TCC1_WO2 _L_(6) +#define PINMUX_PA14G_TCC1_WO2 ((PIN_PA14G_TCC1_WO2 << 16) | MUX_PA14G_TCC1_WO2) +#define PORT_PA14G_TCC1_WO2 (_UL_(1) << 14) +#define PIN_PA18F_TCC1_WO2 _L_(18) /**< \brief TCC1 signal: WO2 on PA18 mux F */ +#define MUX_PA18F_TCC1_WO2 _L_(5) +#define PINMUX_PA18F_TCC1_WO2 ((PIN_PA18F_TCC1_WO2 << 16) | MUX_PA18F_TCC1_WO2) +#define PORT_PA18F_TCC1_WO2 (_UL_(1) << 18) +#define PIN_PB20F_TCC1_WO2 _L_(52) /**< \brief TCC1 signal: WO2 on PB20 mux F */ +#define MUX_PB20F_TCC1_WO2 _L_(5) +#define PINMUX_PB20F_TCC1_WO2 ((PIN_PB20F_TCC1_WO2 << 16) | MUX_PB20F_TCC1_WO2) +#define PORT_PB20F_TCC1_WO2 (_UL_(1) << 20) +#define PIN_PA13G_TCC1_WO3 _L_(13) /**< \brief TCC1 signal: WO3 on PA13 mux G */ +#define MUX_PA13G_TCC1_WO3 _L_(6) +#define PINMUX_PA13G_TCC1_WO3 ((PIN_PA13G_TCC1_WO3 << 16) | MUX_PA13G_TCC1_WO3) +#define PORT_PA13G_TCC1_WO3 (_UL_(1) << 13) +#define PIN_PA15G_TCC1_WO3 _L_(15) /**< \brief TCC1 signal: WO3 on PA15 mux G */ +#define MUX_PA15G_TCC1_WO3 _L_(6) +#define PINMUX_PA15G_TCC1_WO3 ((PIN_PA15G_TCC1_WO3 << 16) | MUX_PA15G_TCC1_WO3) +#define PORT_PA15G_TCC1_WO3 (_UL_(1) << 15) +#define PIN_PA19F_TCC1_WO3 _L_(19) /**< \brief TCC1 signal: WO3 on PA19 mux F */ +#define MUX_PA19F_TCC1_WO3 _L_(5) +#define PINMUX_PA19F_TCC1_WO3 ((PIN_PA19F_TCC1_WO3 << 16) | MUX_PA19F_TCC1_WO3) +#define PORT_PA19F_TCC1_WO3 (_UL_(1) << 19) +#define PIN_PB21F_TCC1_WO3 _L_(53) /**< \brief TCC1 signal: WO3 on PB21 mux F */ +#define MUX_PB21F_TCC1_WO3 _L_(5) +#define PINMUX_PB21F_TCC1_WO3 ((PIN_PB21F_TCC1_WO3 << 16) | MUX_PB21F_TCC1_WO3) +#define PORT_PB21F_TCC1_WO3 (_UL_(1) << 21) +#define PIN_PA08G_TCC1_WO4 _L_(8) /**< \brief TCC1 signal: WO4 on PA08 mux G */ +#define MUX_PA08G_TCC1_WO4 _L_(6) +#define PINMUX_PA08G_TCC1_WO4 ((PIN_PA08G_TCC1_WO4 << 16) | MUX_PA08G_TCC1_WO4) +#define PORT_PA08G_TCC1_WO4 (_UL_(1) << 8) +#define PIN_PC10G_TCC1_WO4 _L_(74) /**< \brief TCC1 signal: WO4 on PC10 mux G */ +#define MUX_PC10G_TCC1_WO4 _L_(6) +#define PINMUX_PC10G_TCC1_WO4 ((PIN_PC10G_TCC1_WO4 << 16) | MUX_PC10G_TCC1_WO4) +#define PORT_PC10G_TCC1_WO4 (_UL_(1) << 10) +#define PIN_PA20F_TCC1_WO4 _L_(20) /**< \brief TCC1 signal: WO4 on PA20 mux F */ +#define MUX_PA20F_TCC1_WO4 _L_(5) +#define PINMUX_PA20F_TCC1_WO4 ((PIN_PA20F_TCC1_WO4 << 16) | MUX_PA20F_TCC1_WO4) +#define PORT_PA20F_TCC1_WO4 (_UL_(1) << 20) +#define PIN_PA09G_TCC1_WO5 _L_(9) /**< \brief TCC1 signal: WO5 on PA09 mux G */ +#define MUX_PA09G_TCC1_WO5 _L_(6) +#define PINMUX_PA09G_TCC1_WO5 ((PIN_PA09G_TCC1_WO5 << 16) | MUX_PA09G_TCC1_WO5) +#define PORT_PA09G_TCC1_WO5 (_UL_(1) << 9) +#define PIN_PC11G_TCC1_WO5 _L_(75) /**< \brief TCC1 signal: WO5 on PC11 mux G */ +#define MUX_PC11G_TCC1_WO5 _L_(6) +#define PINMUX_PC11G_TCC1_WO5 ((PIN_PC11G_TCC1_WO5 << 16) | MUX_PC11G_TCC1_WO5) +#define PORT_PC11G_TCC1_WO5 (_UL_(1) << 11) +#define PIN_PA21F_TCC1_WO5 _L_(21) /**< \brief TCC1 signal: WO5 on PA21 mux F */ +#define MUX_PA21F_TCC1_WO5 _L_(5) +#define PINMUX_PA21F_TCC1_WO5 ((PIN_PA21F_TCC1_WO5 << 16) | MUX_PA21F_TCC1_WO5) +#define PORT_PA21F_TCC1_WO5 (_UL_(1) << 21) +#define PIN_PA10G_TCC1_WO6 _L_(10) /**< \brief TCC1 signal: WO6 on PA10 mux G */ +#define MUX_PA10G_TCC1_WO6 _L_(6) +#define PINMUX_PA10G_TCC1_WO6 ((PIN_PA10G_TCC1_WO6 << 16) | MUX_PA10G_TCC1_WO6) +#define PORT_PA10G_TCC1_WO6 (_UL_(1) << 10) +#define PIN_PC12G_TCC1_WO6 _L_(76) /**< \brief TCC1 signal: WO6 on PC12 mux G */ +#define MUX_PC12G_TCC1_WO6 _L_(6) +#define PINMUX_PC12G_TCC1_WO6 ((PIN_PC12G_TCC1_WO6 << 16) | MUX_PC12G_TCC1_WO6) +#define PORT_PC12G_TCC1_WO6 (_UL_(1) << 12) +#define PIN_PA22F_TCC1_WO6 _L_(22) /**< \brief TCC1 signal: WO6 on PA22 mux F */ +#define MUX_PA22F_TCC1_WO6 _L_(5) +#define PINMUX_PA22F_TCC1_WO6 ((PIN_PA22F_TCC1_WO6 << 16) | MUX_PA22F_TCC1_WO6) +#define PORT_PA22F_TCC1_WO6 (_UL_(1) << 22) +#define PIN_PA11G_TCC1_WO7 _L_(11) /**< \brief TCC1 signal: WO7 on PA11 mux G */ +#define MUX_PA11G_TCC1_WO7 _L_(6) +#define PINMUX_PA11G_TCC1_WO7 ((PIN_PA11G_TCC1_WO7 << 16) | MUX_PA11G_TCC1_WO7) +#define PORT_PA11G_TCC1_WO7 (_UL_(1) << 11) +#define PIN_PC13G_TCC1_WO7 _L_(77) /**< \brief TCC1 signal: WO7 on PC13 mux G */ +#define MUX_PC13G_TCC1_WO7 _L_(6) +#define PINMUX_PC13G_TCC1_WO7 ((PIN_PC13G_TCC1_WO7 << 16) | MUX_PC13G_TCC1_WO7) +#define PORT_PC13G_TCC1_WO7 (_UL_(1) << 13) +#define PIN_PA23F_TCC1_WO7 _L_(23) /**< \brief TCC1 signal: WO7 on PA23 mux F */ +#define MUX_PA23F_TCC1_WO7 _L_(5) +#define PINMUX_PA23F_TCC1_WO7 ((PIN_PA23F_TCC1_WO7 << 16) | MUX_PA23F_TCC1_WO7) +#define PORT_PA23F_TCC1_WO7 (_UL_(1) << 23) +/* ========== PORT definition for TC2 peripheral ========== */ +#define PIN_PA12E_TC2_WO0 _L_(12) /**< \brief TC2 signal: WO0 on PA12 mux E */ +#define MUX_PA12E_TC2_WO0 _L_(4) +#define PINMUX_PA12E_TC2_WO0 ((PIN_PA12E_TC2_WO0 << 16) | MUX_PA12E_TC2_WO0) +#define PORT_PA12E_TC2_WO0 (_UL_(1) << 12) +#define PIN_PA16E_TC2_WO0 _L_(16) /**< \brief TC2 signal: WO0 on PA16 mux E */ +#define MUX_PA16E_TC2_WO0 _L_(4) +#define PINMUX_PA16E_TC2_WO0 ((PIN_PA16E_TC2_WO0 << 16) | MUX_PA16E_TC2_WO0) +#define PORT_PA16E_TC2_WO0 (_UL_(1) << 16) +#define PIN_PA00E_TC2_WO0 _L_(0) /**< \brief TC2 signal: WO0 on PA00 mux E */ +#define MUX_PA00E_TC2_WO0 _L_(4) +#define PINMUX_PA00E_TC2_WO0 ((PIN_PA00E_TC2_WO0 << 16) | MUX_PA00E_TC2_WO0) +#define PORT_PA00E_TC2_WO0 (_UL_(1) << 0) +#define PIN_PA01E_TC2_WO1 _L_(1) /**< \brief TC2 signal: WO1 on PA01 mux E */ +#define MUX_PA01E_TC2_WO1 _L_(4) +#define PINMUX_PA01E_TC2_WO1 ((PIN_PA01E_TC2_WO1 << 16) | MUX_PA01E_TC2_WO1) +#define PORT_PA01E_TC2_WO1 (_UL_(1) << 1) +#define PIN_PA13E_TC2_WO1 _L_(13) /**< \brief TC2 signal: WO1 on PA13 mux E */ +#define MUX_PA13E_TC2_WO1 _L_(4) +#define PINMUX_PA13E_TC2_WO1 ((PIN_PA13E_TC2_WO1 << 16) | MUX_PA13E_TC2_WO1) +#define PORT_PA13E_TC2_WO1 (_UL_(1) << 13) +#define PIN_PA17E_TC2_WO1 _L_(17) /**< \brief TC2 signal: WO1 on PA17 mux E */ +#define MUX_PA17E_TC2_WO1 _L_(4) +#define PINMUX_PA17E_TC2_WO1 ((PIN_PA17E_TC2_WO1 << 16) | MUX_PA17E_TC2_WO1) +#define PORT_PA17E_TC2_WO1 (_UL_(1) << 17) +/* ========== PORT definition for TC3 peripheral ========== */ +#define PIN_PA18E_TC3_WO0 _L_(18) /**< \brief TC3 signal: WO0 on PA18 mux E */ +#define MUX_PA18E_TC3_WO0 _L_(4) +#define PINMUX_PA18E_TC3_WO0 ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0) +#define PORT_PA18E_TC3_WO0 (_UL_(1) << 18) +#define PIN_PA14E_TC3_WO0 _L_(14) /**< \brief TC3 signal: WO0 on PA14 mux E */ +#define MUX_PA14E_TC3_WO0 _L_(4) +#define PINMUX_PA14E_TC3_WO0 ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0) +#define PORT_PA14E_TC3_WO0 (_UL_(1) << 14) +#define PIN_PA15E_TC3_WO1 _L_(15) /**< \brief TC3 signal: WO1 on PA15 mux E */ +#define MUX_PA15E_TC3_WO1 _L_(4) +#define PINMUX_PA15E_TC3_WO1 ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1) +#define PORT_PA15E_TC3_WO1 (_UL_(1) << 15) +#define PIN_PA19E_TC3_WO1 _L_(19) /**< \brief TC3 signal: WO1 on PA19 mux E */ +#define MUX_PA19E_TC3_WO1 _L_(4) +#define PINMUX_PA19E_TC3_WO1 ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1) +#define PORT_PA19E_TC3_WO1 (_UL_(1) << 19) +/* ========== PORT definition for CAN0 peripheral ========== */ +#define PIN_PA23I_CAN0_RX _L_(23) /**< \brief CAN0 signal: RX on PA23 mux I */ +#define MUX_PA23I_CAN0_RX _L_(8) +#define PINMUX_PA23I_CAN0_RX ((PIN_PA23I_CAN0_RX << 16) | MUX_PA23I_CAN0_RX) +#define PORT_PA23I_CAN0_RX (_UL_(1) << 23) +#define PIN_PA25I_CAN0_RX _L_(25) /**< \brief CAN0 signal: RX on PA25 mux I */ +#define MUX_PA25I_CAN0_RX _L_(8) +#define PINMUX_PA25I_CAN0_RX ((PIN_PA25I_CAN0_RX << 16) | MUX_PA25I_CAN0_RX) +#define PORT_PA25I_CAN0_RX (_UL_(1) << 25) +#define PIN_PA22I_CAN0_TX _L_(22) /**< \brief CAN0 signal: TX on PA22 mux I */ +#define MUX_PA22I_CAN0_TX _L_(8) +#define PINMUX_PA22I_CAN0_TX ((PIN_PA22I_CAN0_TX << 16) | MUX_PA22I_CAN0_TX) +#define PORT_PA22I_CAN0_TX (_UL_(1) << 22) +#define PIN_PA24I_CAN0_TX _L_(24) /**< \brief CAN0 signal: TX on PA24 mux I */ +#define MUX_PA24I_CAN0_TX _L_(8) +#define PINMUX_PA24I_CAN0_TX ((PIN_PA24I_CAN0_TX << 16) | MUX_PA24I_CAN0_TX) +#define PORT_PA24I_CAN0_TX (_UL_(1) << 24) +/* ========== PORT definition for CAN1 peripheral ========== */ +#define PIN_PB13H_CAN1_RX _L_(45) /**< \brief CAN1 signal: RX on PB13 mux H */ +#define MUX_PB13H_CAN1_RX _L_(7) +#define PINMUX_PB13H_CAN1_RX ((PIN_PB13H_CAN1_RX << 16) | MUX_PB13H_CAN1_RX) +#define PORT_PB13H_CAN1_RX (_UL_(1) << 13) +#define PIN_PB15H_CAN1_RX _L_(47) /**< \brief CAN1 signal: RX on PB15 mux H */ +#define MUX_PB15H_CAN1_RX _L_(7) +#define PINMUX_PB15H_CAN1_RX ((PIN_PB15H_CAN1_RX << 16) | MUX_PB15H_CAN1_RX) +#define PORT_PB15H_CAN1_RX (_UL_(1) << 15) +#define PIN_PB12H_CAN1_TX _L_(44) /**< \brief CAN1 signal: TX on PB12 mux H */ +#define MUX_PB12H_CAN1_TX _L_(7) +#define PINMUX_PB12H_CAN1_TX ((PIN_PB12H_CAN1_TX << 16) | MUX_PB12H_CAN1_TX) +#define PORT_PB12H_CAN1_TX (_UL_(1) << 12) +#define PIN_PB14H_CAN1_TX _L_(46) /**< \brief CAN1 signal: TX on PB14 mux H */ +#define MUX_PB14H_CAN1_TX _L_(7) +#define PINMUX_PB14H_CAN1_TX ((PIN_PB14H_CAN1_TX << 16) | MUX_PB14H_CAN1_TX) +#define PORT_PB14H_CAN1_TX (_UL_(1) << 14) +/* ========== PORT definition for GMAC peripheral ========== */ +#define PIN_PC21L_GMAC_GCOL _L_(85) /**< \brief GMAC signal: GCOL on PC21 mux L */ +#define MUX_PC21L_GMAC_GCOL _L_(11) +#define PINMUX_PC21L_GMAC_GCOL ((PIN_PC21L_GMAC_GCOL << 16) | MUX_PC21L_GMAC_GCOL) +#define PORT_PC21L_GMAC_GCOL (_UL_(1) << 21) +#define PIN_PA16L_GMAC_GCRS _L_(16) /**< \brief GMAC signal: GCRS on PA16 mux L */ +#define MUX_PA16L_GMAC_GCRS _L_(11) +#define PINMUX_PA16L_GMAC_GCRS ((PIN_PA16L_GMAC_GCRS << 16) | MUX_PA16L_GMAC_GCRS) +#define PORT_PA16L_GMAC_GCRS (_UL_(1) << 16) +#define PIN_PA20L_GMAC_GMDC _L_(20) /**< \brief GMAC signal: GMDC on PA20 mux L */ +#define MUX_PA20L_GMAC_GMDC _L_(11) +#define PINMUX_PA20L_GMAC_GMDC ((PIN_PA20L_GMAC_GMDC << 16) | MUX_PA20L_GMAC_GMDC) +#define PORT_PA20L_GMAC_GMDC (_UL_(1) << 20) +#define PIN_PB14L_GMAC_GMDC _L_(46) /**< \brief GMAC signal: GMDC on PB14 mux L */ +#define MUX_PB14L_GMAC_GMDC _L_(11) +#define PINMUX_PB14L_GMAC_GMDC ((PIN_PB14L_GMAC_GMDC << 16) | MUX_PB14L_GMAC_GMDC) +#define PORT_PB14L_GMAC_GMDC (_UL_(1) << 14) +#define PIN_PC11L_GMAC_GMDC _L_(75) /**< \brief GMAC signal: GMDC on PC11 mux L */ +#define MUX_PC11L_GMAC_GMDC _L_(11) +#define PINMUX_PC11L_GMAC_GMDC ((PIN_PC11L_GMAC_GMDC << 16) | MUX_PC11L_GMAC_GMDC) +#define PORT_PC11L_GMAC_GMDC (_UL_(1) << 11) +#define PIN_PA21L_GMAC_GMDIO _L_(21) /**< \brief GMAC signal: GMDIO on PA21 mux L */ +#define MUX_PA21L_GMAC_GMDIO _L_(11) +#define PINMUX_PA21L_GMAC_GMDIO ((PIN_PA21L_GMAC_GMDIO << 16) | MUX_PA21L_GMAC_GMDIO) +#define PORT_PA21L_GMAC_GMDIO (_UL_(1) << 21) +#define PIN_PB15L_GMAC_GMDIO _L_(47) /**< \brief GMAC signal: GMDIO on PB15 mux L */ +#define MUX_PB15L_GMAC_GMDIO _L_(11) +#define PINMUX_PB15L_GMAC_GMDIO ((PIN_PB15L_GMAC_GMDIO << 16) | MUX_PB15L_GMAC_GMDIO) +#define PORT_PB15L_GMAC_GMDIO (_UL_(1) << 15) +#define PIN_PC12L_GMAC_GMDIO _L_(76) /**< \brief GMAC signal: GMDIO on PC12 mux L */ +#define MUX_PC12L_GMAC_GMDIO _L_(11) +#define PINMUX_PC12L_GMAC_GMDIO ((PIN_PC12L_GMAC_GMDIO << 16) | MUX_PC12L_GMAC_GMDIO) +#define PORT_PC12L_GMAC_GMDIO (_UL_(1) << 12) +#define PIN_PA13L_GMAC_GRX0 _L_(13) /**< \brief GMAC signal: GRX0 on PA13 mux L */ +#define MUX_PA13L_GMAC_GRX0 _L_(11) +#define PINMUX_PA13L_GMAC_GRX0 ((PIN_PA13L_GMAC_GRX0 << 16) | MUX_PA13L_GMAC_GRX0) +#define PORT_PA13L_GMAC_GRX0 (_UL_(1) << 13) +#define PIN_PA12L_GMAC_GRX1 _L_(12) /**< \brief GMAC signal: GRX1 on PA12 mux L */ +#define MUX_PA12L_GMAC_GRX1 _L_(11) +#define PINMUX_PA12L_GMAC_GRX1 ((PIN_PA12L_GMAC_GRX1 << 16) | MUX_PA12L_GMAC_GRX1) +#define PORT_PA12L_GMAC_GRX1 (_UL_(1) << 12) +#define PIN_PC15L_GMAC_GRX2 _L_(79) /**< \brief GMAC signal: GRX2 on PC15 mux L */ +#define MUX_PC15L_GMAC_GRX2 _L_(11) +#define PINMUX_PC15L_GMAC_GRX2 ((PIN_PC15L_GMAC_GRX2 << 16) | MUX_PC15L_GMAC_GRX2) +#define PORT_PC15L_GMAC_GRX2 (_UL_(1) << 15) +#define PIN_PC14L_GMAC_GRX3 _L_(78) /**< \brief GMAC signal: GRX3 on PC14 mux L */ +#define MUX_PC14L_GMAC_GRX3 _L_(11) +#define PINMUX_PC14L_GMAC_GRX3 ((PIN_PC14L_GMAC_GRX3 << 16) | MUX_PC14L_GMAC_GRX3) +#define PORT_PC14L_GMAC_GRX3 (_UL_(1) << 14) +#define PIN_PC18L_GMAC_GRXCK _L_(82) /**< \brief GMAC signal: GRXCK on PC18 mux L */ +#define MUX_PC18L_GMAC_GRXCK _L_(11) +#define PINMUX_PC18L_GMAC_GRXCK ((PIN_PC18L_GMAC_GRXCK << 16) | MUX_PC18L_GMAC_GRXCK) +#define PORT_PC18L_GMAC_GRXCK (_UL_(1) << 18) +#define PIN_PC20L_GMAC_GRXDV _L_(84) /**< \brief GMAC signal: GRXDV on PC20 mux L */ +#define MUX_PC20L_GMAC_GRXDV _L_(11) +#define PINMUX_PC20L_GMAC_GRXDV ((PIN_PC20L_GMAC_GRXDV << 16) | MUX_PC20L_GMAC_GRXDV) +#define PORT_PC20L_GMAC_GRXDV (_UL_(1) << 20) +#define PIN_PA15L_GMAC_GRXER _L_(15) /**< \brief GMAC signal: GRXER on PA15 mux L */ +#define MUX_PA15L_GMAC_GRXER _L_(11) +#define PINMUX_PA15L_GMAC_GRXER ((PIN_PA15L_GMAC_GRXER << 16) | MUX_PA15L_GMAC_GRXER) +#define PORT_PA15L_GMAC_GRXER (_UL_(1) << 15) +#define PIN_PA18L_GMAC_GTX0 _L_(18) /**< \brief GMAC signal: GTX0 on PA18 mux L */ +#define MUX_PA18L_GMAC_GTX0 _L_(11) +#define PINMUX_PA18L_GMAC_GTX0 ((PIN_PA18L_GMAC_GTX0 << 16) | MUX_PA18L_GMAC_GTX0) +#define PORT_PA18L_GMAC_GTX0 (_UL_(1) << 18) +#define PIN_PA19L_GMAC_GTX1 _L_(19) /**< \brief GMAC signal: GTX1 on PA19 mux L */ +#define MUX_PA19L_GMAC_GTX1 _L_(11) +#define PINMUX_PA19L_GMAC_GTX1 ((PIN_PA19L_GMAC_GTX1 << 16) | MUX_PA19L_GMAC_GTX1) +#define PORT_PA19L_GMAC_GTX1 (_UL_(1) << 19) +#define PIN_PC16L_GMAC_GTX2 _L_(80) /**< \brief GMAC signal: GTX2 on PC16 mux L */ +#define MUX_PC16L_GMAC_GTX2 _L_(11) +#define PINMUX_PC16L_GMAC_GTX2 ((PIN_PC16L_GMAC_GTX2 << 16) | MUX_PC16L_GMAC_GTX2) +#define PORT_PC16L_GMAC_GTX2 (_UL_(1) << 16) +#define PIN_PC17L_GMAC_GTX3 _L_(81) /**< \brief GMAC signal: GTX3 on PC17 mux L */ +#define MUX_PC17L_GMAC_GTX3 _L_(11) +#define PINMUX_PC17L_GMAC_GTX3 ((PIN_PC17L_GMAC_GTX3 << 16) | MUX_PC17L_GMAC_GTX3) +#define PORT_PC17L_GMAC_GTX3 (_UL_(1) << 17) +#define PIN_PA14L_GMAC_GTXCK _L_(14) /**< \brief GMAC signal: GTXCK on PA14 mux L */ +#define MUX_PA14L_GMAC_GTXCK _L_(11) +#define PINMUX_PA14L_GMAC_GTXCK ((PIN_PA14L_GMAC_GTXCK << 16) | MUX_PA14L_GMAC_GTXCK) +#define PORT_PA14L_GMAC_GTXCK (_UL_(1) << 14) +#define PIN_PA17L_GMAC_GTXEN _L_(17) /**< \brief GMAC signal: GTXEN on PA17 mux L */ +#define MUX_PA17L_GMAC_GTXEN _L_(11) +#define PINMUX_PA17L_GMAC_GTXEN ((PIN_PA17L_GMAC_GTXEN << 16) | MUX_PA17L_GMAC_GTXEN) +#define PORT_PA17L_GMAC_GTXEN (_UL_(1) << 17) +#define PIN_PC19L_GMAC_GTXER _L_(83) /**< \brief GMAC signal: GTXER on PC19 mux L */ +#define MUX_PC19L_GMAC_GTXER _L_(11) +#define PINMUX_PC19L_GMAC_GTXER ((PIN_PC19L_GMAC_GTXER << 16) | MUX_PC19L_GMAC_GTXER) +#define PORT_PC19L_GMAC_GTXER (_UL_(1) << 19) +/* ========== PORT definition for TCC2 peripheral ========== */ +#define PIN_PA14F_TCC2_WO0 _L_(14) /**< \brief TCC2 signal: WO0 on PA14 mux F */ +#define MUX_PA14F_TCC2_WO0 _L_(5) +#define PINMUX_PA14F_TCC2_WO0 ((PIN_PA14F_TCC2_WO0 << 16) | MUX_PA14F_TCC2_WO0) +#define PORT_PA14F_TCC2_WO0 (_UL_(1) << 14) +#define PIN_PA30F_TCC2_WO0 _L_(30) /**< \brief TCC2 signal: WO0 on PA30 mux F */ +#define MUX_PA30F_TCC2_WO0 _L_(5) +#define PINMUX_PA30F_TCC2_WO0 ((PIN_PA30F_TCC2_WO0 << 16) | MUX_PA30F_TCC2_WO0) +#define PORT_PA30F_TCC2_WO0 (_UL_(1) << 30) +#define PIN_PA15F_TCC2_WO1 _L_(15) /**< \brief TCC2 signal: WO1 on PA15 mux F */ +#define MUX_PA15F_TCC2_WO1 _L_(5) +#define PINMUX_PA15F_TCC2_WO1 ((PIN_PA15F_TCC2_WO1 << 16) | MUX_PA15F_TCC2_WO1) +#define PORT_PA15F_TCC2_WO1 (_UL_(1) << 15) +#define PIN_PA31F_TCC2_WO1 _L_(31) /**< \brief TCC2 signal: WO1 on PA31 mux F */ +#define MUX_PA31F_TCC2_WO1 _L_(5) +#define PINMUX_PA31F_TCC2_WO1 ((PIN_PA31F_TCC2_WO1 << 16) | MUX_PA31F_TCC2_WO1) +#define PORT_PA31F_TCC2_WO1 (_UL_(1) << 31) +#define PIN_PA24F_TCC2_WO2 _L_(24) /**< \brief TCC2 signal: WO2 on PA24 mux F */ +#define MUX_PA24F_TCC2_WO2 _L_(5) +#define PINMUX_PA24F_TCC2_WO2 ((PIN_PA24F_TCC2_WO2 << 16) | MUX_PA24F_TCC2_WO2) +#define PORT_PA24F_TCC2_WO2 (_UL_(1) << 24) +#define PIN_PB02F_TCC2_WO2 _L_(34) /**< \brief TCC2 signal: WO2 on PB02 mux F */ +#define MUX_PB02F_TCC2_WO2 _L_(5) +#define PINMUX_PB02F_TCC2_WO2 ((PIN_PB02F_TCC2_WO2 << 16) | MUX_PB02F_TCC2_WO2) +#define PORT_PB02F_TCC2_WO2 (_UL_(1) << 2) +/* ========== PORT definition for TCC3 peripheral ========== */ +#define PIN_PB12F_TCC3_WO0 _L_(44) /**< \brief TCC3 signal: WO0 on PB12 mux F */ +#define MUX_PB12F_TCC3_WO0 _L_(5) +#define PINMUX_PB12F_TCC3_WO0 ((PIN_PB12F_TCC3_WO0 << 16) | MUX_PB12F_TCC3_WO0) +#define PORT_PB12F_TCC3_WO0 (_UL_(1) << 12) +#define PIN_PB16F_TCC3_WO0 _L_(48) /**< \brief TCC3 signal: WO0 on PB16 mux F */ +#define MUX_PB16F_TCC3_WO0 _L_(5) +#define PINMUX_PB16F_TCC3_WO0 ((PIN_PB16F_TCC3_WO0 << 16) | MUX_PB16F_TCC3_WO0) +#define PORT_PB16F_TCC3_WO0 (_UL_(1) << 16) +#define PIN_PB13F_TCC3_WO1 _L_(45) /**< \brief TCC3 signal: WO1 on PB13 mux F */ +#define MUX_PB13F_TCC3_WO1 _L_(5) +#define PINMUX_PB13F_TCC3_WO1 ((PIN_PB13F_TCC3_WO1 << 16) | MUX_PB13F_TCC3_WO1) +#define PORT_PB13F_TCC3_WO1 (_UL_(1) << 13) +#define PIN_PB17F_TCC3_WO1 _L_(49) /**< \brief TCC3 signal: WO1 on PB17 mux F */ +#define MUX_PB17F_TCC3_WO1 _L_(5) +#define PINMUX_PB17F_TCC3_WO1 ((PIN_PB17F_TCC3_WO1 << 16) | MUX_PB17F_TCC3_WO1) +#define PORT_PB17F_TCC3_WO1 (_UL_(1) << 17) +/* ========== PORT definition for TC4 peripheral ========== */ +#define PIN_PA22E_TC4_WO0 _L_(22) /**< \brief TC4 signal: WO0 on PA22 mux E */ +#define MUX_PA22E_TC4_WO0 _L_(4) +#define PINMUX_PA22E_TC4_WO0 ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0) +#define PORT_PA22E_TC4_WO0 (_UL_(1) << 22) +#define PIN_PB08E_TC4_WO0 _L_(40) /**< \brief TC4 signal: WO0 on PB08 mux E */ +#define MUX_PB08E_TC4_WO0 _L_(4) +#define PINMUX_PB08E_TC4_WO0 ((PIN_PB08E_TC4_WO0 << 16) | MUX_PB08E_TC4_WO0) +#define PORT_PB08E_TC4_WO0 (_UL_(1) << 8) +#define PIN_PB12E_TC4_WO0 _L_(44) /**< \brief TC4 signal: WO0 on PB12 mux E */ +#define MUX_PB12E_TC4_WO0 _L_(4) +#define PINMUX_PB12E_TC4_WO0 ((PIN_PB12E_TC4_WO0 << 16) | MUX_PB12E_TC4_WO0) +#define PORT_PB12E_TC4_WO0 (_UL_(1) << 12) +#define PIN_PA23E_TC4_WO1 _L_(23) /**< \brief TC4 signal: WO1 on PA23 mux E */ +#define MUX_PA23E_TC4_WO1 _L_(4) +#define PINMUX_PA23E_TC4_WO1 ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1) +#define PORT_PA23E_TC4_WO1 (_UL_(1) << 23) +#define PIN_PB09E_TC4_WO1 _L_(41) /**< \brief TC4 signal: WO1 on PB09 mux E */ +#define MUX_PB09E_TC4_WO1 _L_(4) +#define PINMUX_PB09E_TC4_WO1 ((PIN_PB09E_TC4_WO1 << 16) | MUX_PB09E_TC4_WO1) +#define PORT_PB09E_TC4_WO1 (_UL_(1) << 9) +#define PIN_PB13E_TC4_WO1 _L_(45) /**< \brief TC4 signal: WO1 on PB13 mux E */ +#define MUX_PB13E_TC4_WO1 _L_(4) +#define PINMUX_PB13E_TC4_WO1 ((PIN_PB13E_TC4_WO1 << 16) | MUX_PB13E_TC4_WO1) +#define PORT_PB13E_TC4_WO1 (_UL_(1) << 13) +/* ========== PORT definition for TC5 peripheral ========== */ +#define PIN_PA24E_TC5_WO0 _L_(24) /**< \brief TC5 signal: WO0 on PA24 mux E */ +#define MUX_PA24E_TC5_WO0 _L_(4) +#define PINMUX_PA24E_TC5_WO0 ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0) +#define PORT_PA24E_TC5_WO0 (_UL_(1) << 24) +#define PIN_PB10E_TC5_WO0 _L_(42) /**< \brief TC5 signal: WO0 on PB10 mux E */ +#define MUX_PB10E_TC5_WO0 _L_(4) +#define PINMUX_PB10E_TC5_WO0 ((PIN_PB10E_TC5_WO0 << 16) | MUX_PB10E_TC5_WO0) +#define PORT_PB10E_TC5_WO0 (_UL_(1) << 10) +#define PIN_PB14E_TC5_WO0 _L_(46) /**< \brief TC5 signal: WO0 on PB14 mux E */ +#define MUX_PB14E_TC5_WO0 _L_(4) +#define PINMUX_PB14E_TC5_WO0 ((PIN_PB14E_TC5_WO0 << 16) | MUX_PB14E_TC5_WO0) +#define PORT_PB14E_TC5_WO0 (_UL_(1) << 14) +#define PIN_PA25E_TC5_WO1 _L_(25) /**< \brief TC5 signal: WO1 on PA25 mux E */ +#define MUX_PA25E_TC5_WO1 _L_(4) +#define PINMUX_PA25E_TC5_WO1 ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1) +#define PORT_PA25E_TC5_WO1 (_UL_(1) << 25) +#define PIN_PB11E_TC5_WO1 _L_(43) /**< \brief TC5 signal: WO1 on PB11 mux E */ +#define MUX_PB11E_TC5_WO1 _L_(4) +#define PINMUX_PB11E_TC5_WO1 ((PIN_PB11E_TC5_WO1 << 16) | MUX_PB11E_TC5_WO1) +#define PORT_PB11E_TC5_WO1 (_UL_(1) << 11) +#define PIN_PB15E_TC5_WO1 _L_(47) /**< \brief TC5 signal: WO1 on PB15 mux E */ +#define MUX_PB15E_TC5_WO1 _L_(4) +#define PINMUX_PB15E_TC5_WO1 ((PIN_PB15E_TC5_WO1 << 16) | MUX_PB15E_TC5_WO1) +#define PORT_PB15E_TC5_WO1 (_UL_(1) << 15) +/* ========== PORT definition for PDEC peripheral ========== */ +#define PIN_PB18G_PDEC_QDI0 _L_(50) /**< \brief PDEC signal: QDI0 on PB18 mux G */ +#define MUX_PB18G_PDEC_QDI0 _L_(6) +#define PINMUX_PB18G_PDEC_QDI0 ((PIN_PB18G_PDEC_QDI0 << 16) | MUX_PB18G_PDEC_QDI0) +#define PORT_PB18G_PDEC_QDI0 (_UL_(1) << 18) +#define PIN_PB23G_PDEC_QDI0 _L_(55) /**< \brief PDEC signal: QDI0 on PB23 mux G */ +#define MUX_PB23G_PDEC_QDI0 _L_(6) +#define PINMUX_PB23G_PDEC_QDI0 ((PIN_PB23G_PDEC_QDI0 << 16) | MUX_PB23G_PDEC_QDI0) +#define PORT_PB23G_PDEC_QDI0 (_UL_(1) << 23) +#define PIN_PC16G_PDEC_QDI0 _L_(80) /**< \brief PDEC signal: QDI0 on PC16 mux G */ +#define MUX_PC16G_PDEC_QDI0 _L_(6) +#define PINMUX_PC16G_PDEC_QDI0 ((PIN_PC16G_PDEC_QDI0 << 16) | MUX_PC16G_PDEC_QDI0) +#define PORT_PC16G_PDEC_QDI0 (_UL_(1) << 16) +#define PIN_PA24G_PDEC_QDI0 _L_(24) /**< \brief PDEC signal: QDI0 on PA24 mux G */ +#define MUX_PA24G_PDEC_QDI0 _L_(6) +#define PINMUX_PA24G_PDEC_QDI0 ((PIN_PA24G_PDEC_QDI0 << 16) | MUX_PA24G_PDEC_QDI0) +#define PORT_PA24G_PDEC_QDI0 (_UL_(1) << 24) +#define PIN_PB19G_PDEC_QDI1 _L_(51) /**< \brief PDEC signal: QDI1 on PB19 mux G */ +#define MUX_PB19G_PDEC_QDI1 _L_(6) +#define PINMUX_PB19G_PDEC_QDI1 ((PIN_PB19G_PDEC_QDI1 << 16) | MUX_PB19G_PDEC_QDI1) +#define PORT_PB19G_PDEC_QDI1 (_UL_(1) << 19) +#define PIN_PB24G_PDEC_QDI1 _L_(56) /**< \brief PDEC signal: QDI1 on PB24 mux G */ +#define MUX_PB24G_PDEC_QDI1 _L_(6) +#define PINMUX_PB24G_PDEC_QDI1 ((PIN_PB24G_PDEC_QDI1 << 16) | MUX_PB24G_PDEC_QDI1) +#define PORT_PB24G_PDEC_QDI1 (_UL_(1) << 24) +#define PIN_PC17G_PDEC_QDI1 _L_(81) /**< \brief PDEC signal: QDI1 on PC17 mux G */ +#define MUX_PC17G_PDEC_QDI1 _L_(6) +#define PINMUX_PC17G_PDEC_QDI1 ((PIN_PC17G_PDEC_QDI1 << 16) | MUX_PC17G_PDEC_QDI1) +#define PORT_PC17G_PDEC_QDI1 (_UL_(1) << 17) +#define PIN_PA25G_PDEC_QDI1 _L_(25) /**< \brief PDEC signal: QDI1 on PA25 mux G */ +#define MUX_PA25G_PDEC_QDI1 _L_(6) +#define PINMUX_PA25G_PDEC_QDI1 ((PIN_PA25G_PDEC_QDI1 << 16) | MUX_PA25G_PDEC_QDI1) +#define PORT_PA25G_PDEC_QDI1 (_UL_(1) << 25) +#define PIN_PB20G_PDEC_QDI2 _L_(52) /**< \brief PDEC signal: QDI2 on PB20 mux G */ +#define MUX_PB20G_PDEC_QDI2 _L_(6) +#define PINMUX_PB20G_PDEC_QDI2 ((PIN_PB20G_PDEC_QDI2 << 16) | MUX_PB20G_PDEC_QDI2) +#define PORT_PB20G_PDEC_QDI2 (_UL_(1) << 20) +#define PIN_PB25G_PDEC_QDI2 _L_(57) /**< \brief PDEC signal: QDI2 on PB25 mux G */ +#define MUX_PB25G_PDEC_QDI2 _L_(6) +#define PINMUX_PB25G_PDEC_QDI2 ((PIN_PB25G_PDEC_QDI2 << 16) | MUX_PB25G_PDEC_QDI2) +#define PORT_PB25G_PDEC_QDI2 (_UL_(1) << 25) +#define PIN_PC18G_PDEC_QDI2 _L_(82) /**< \brief PDEC signal: QDI2 on PC18 mux G */ +#define MUX_PC18G_PDEC_QDI2 _L_(6) +#define PINMUX_PC18G_PDEC_QDI2 ((PIN_PC18G_PDEC_QDI2 << 16) | MUX_PC18G_PDEC_QDI2) +#define PORT_PC18G_PDEC_QDI2 (_UL_(1) << 18) +#define PIN_PB22G_PDEC_QDI2 _L_(54) /**< \brief PDEC signal: QDI2 on PB22 mux G */ +#define MUX_PB22G_PDEC_QDI2 _L_(6) +#define PINMUX_PB22G_PDEC_QDI2 ((PIN_PB22G_PDEC_QDI2 << 16) | MUX_PB22G_PDEC_QDI2) +#define PORT_PB22G_PDEC_QDI2 (_UL_(1) << 22) +/* ========== PORT definition for AC peripheral ========== */ +#define PIN_PA04B_AC_AIN0 _L_(4) /**< \brief AC signal: AIN0 on PA04 mux B */ +#define MUX_PA04B_AC_AIN0 _L_(1) +#define PINMUX_PA04B_AC_AIN0 ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0) +#define PORT_PA04B_AC_AIN0 (_UL_(1) << 4) +#define PIN_PA05B_AC_AIN1 _L_(5) /**< \brief AC signal: AIN1 on PA05 mux B */ +#define MUX_PA05B_AC_AIN1 _L_(1) +#define PINMUX_PA05B_AC_AIN1 ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1) +#define PORT_PA05B_AC_AIN1 (_UL_(1) << 5) +#define PIN_PA06B_AC_AIN2 _L_(6) /**< \brief AC signal: AIN2 on PA06 mux B */ +#define MUX_PA06B_AC_AIN2 _L_(1) +#define PINMUX_PA06B_AC_AIN2 ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2) +#define PORT_PA06B_AC_AIN2 (_UL_(1) << 6) +#define PIN_PA07B_AC_AIN3 _L_(7) /**< \brief AC signal: AIN3 on PA07 mux B */ +#define MUX_PA07B_AC_AIN3 _L_(1) +#define PINMUX_PA07B_AC_AIN3 ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3) +#define PORT_PA07B_AC_AIN3 (_UL_(1) << 7) +#define PIN_PA12M_AC_CMP0 _L_(12) /**< \brief AC signal: CMP0 on PA12 mux M */ +#define MUX_PA12M_AC_CMP0 _L_(12) +#define PINMUX_PA12M_AC_CMP0 ((PIN_PA12M_AC_CMP0 << 16) | MUX_PA12M_AC_CMP0) +#define PORT_PA12M_AC_CMP0 (_UL_(1) << 12) +#define PIN_PA18M_AC_CMP0 _L_(18) /**< \brief AC signal: CMP0 on PA18 mux M */ +#define MUX_PA18M_AC_CMP0 _L_(12) +#define PINMUX_PA18M_AC_CMP0 ((PIN_PA18M_AC_CMP0 << 16) | MUX_PA18M_AC_CMP0) +#define PORT_PA18M_AC_CMP0 (_UL_(1) << 18) +#define PIN_PB24M_AC_CMP0 _L_(56) /**< \brief AC signal: CMP0 on PB24 mux M */ +#define MUX_PB24M_AC_CMP0 _L_(12) +#define PINMUX_PB24M_AC_CMP0 ((PIN_PB24M_AC_CMP0 << 16) | MUX_PB24M_AC_CMP0) +#define PORT_PB24M_AC_CMP0 (_UL_(1) << 24) +#define PIN_PA13M_AC_CMP1 _L_(13) /**< \brief AC signal: CMP1 on PA13 mux M */ +#define MUX_PA13M_AC_CMP1 _L_(12) +#define PINMUX_PA13M_AC_CMP1 ((PIN_PA13M_AC_CMP1 << 16) | MUX_PA13M_AC_CMP1) +#define PORT_PA13M_AC_CMP1 (_UL_(1) << 13) +#define PIN_PA19M_AC_CMP1 _L_(19) /**< \brief AC signal: CMP1 on PA19 mux M */ +#define MUX_PA19M_AC_CMP1 _L_(12) +#define PINMUX_PA19M_AC_CMP1 ((PIN_PA19M_AC_CMP1 << 16) | MUX_PA19M_AC_CMP1) +#define PORT_PA19M_AC_CMP1 (_UL_(1) << 19) +#define PIN_PB25M_AC_CMP1 _L_(57) /**< \brief AC signal: CMP1 on PB25 mux M */ +#define MUX_PB25M_AC_CMP1 _L_(12) +#define PINMUX_PB25M_AC_CMP1 ((PIN_PB25M_AC_CMP1 << 16) | MUX_PB25M_AC_CMP1) +#define PORT_PB25M_AC_CMP1 (_UL_(1) << 25) +/* ========== PORT definition for QSPI peripheral ========== */ +#define PIN_PB11H_QSPI_CS _L_(43) /**< \brief QSPI signal: CS on PB11 mux H */ +#define MUX_PB11H_QSPI_CS _L_(7) +#define PINMUX_PB11H_QSPI_CS ((PIN_PB11H_QSPI_CS << 16) | MUX_PB11H_QSPI_CS) +#define PORT_PB11H_QSPI_CS (_UL_(1) << 11) +#define PIN_PA08H_QSPI_DATA0 _L_(8) /**< \brief QSPI signal: DATA0 on PA08 mux H */ +#define MUX_PA08H_QSPI_DATA0 _L_(7) +#define PINMUX_PA08H_QSPI_DATA0 ((PIN_PA08H_QSPI_DATA0 << 16) | MUX_PA08H_QSPI_DATA0) +#define PORT_PA08H_QSPI_DATA0 (_UL_(1) << 8) +#define PIN_PA09H_QSPI_DATA1 _L_(9) /**< \brief QSPI signal: DATA1 on PA09 mux H */ +#define MUX_PA09H_QSPI_DATA1 _L_(7) +#define PINMUX_PA09H_QSPI_DATA1 ((PIN_PA09H_QSPI_DATA1 << 16) | MUX_PA09H_QSPI_DATA1) +#define PORT_PA09H_QSPI_DATA1 (_UL_(1) << 9) +#define PIN_PA10H_QSPI_DATA2 _L_(10) /**< \brief QSPI signal: DATA2 on PA10 mux H */ +#define MUX_PA10H_QSPI_DATA2 _L_(7) +#define PINMUX_PA10H_QSPI_DATA2 ((PIN_PA10H_QSPI_DATA2 << 16) | MUX_PA10H_QSPI_DATA2) +#define PORT_PA10H_QSPI_DATA2 (_UL_(1) << 10) +#define PIN_PA11H_QSPI_DATA3 _L_(11) /**< \brief QSPI signal: DATA3 on PA11 mux H */ +#define MUX_PA11H_QSPI_DATA3 _L_(7) +#define PINMUX_PA11H_QSPI_DATA3 ((PIN_PA11H_QSPI_DATA3 << 16) | MUX_PA11H_QSPI_DATA3) +#define PORT_PA11H_QSPI_DATA3 (_UL_(1) << 11) +#define PIN_PB10H_QSPI_SCK _L_(42) /**< \brief QSPI signal: SCK on PB10 mux H */ +#define MUX_PB10H_QSPI_SCK _L_(7) +#define PINMUX_PB10H_QSPI_SCK ((PIN_PB10H_QSPI_SCK << 16) | MUX_PB10H_QSPI_SCK) +#define PORT_PB10H_QSPI_SCK (_UL_(1) << 10) +/* ========== PORT definition for CCL peripheral ========== */ +#define PIN_PA04N_CCL_IN0 _L_(4) /**< \brief CCL signal: IN0 on PA04 mux N */ +#define MUX_PA04N_CCL_IN0 _L_(13) +#define PINMUX_PA04N_CCL_IN0 ((PIN_PA04N_CCL_IN0 << 16) | MUX_PA04N_CCL_IN0) +#define PORT_PA04N_CCL_IN0 (_UL_(1) << 4) +#define PIN_PA16N_CCL_IN0 _L_(16) /**< \brief CCL signal: IN0 on PA16 mux N */ +#define MUX_PA16N_CCL_IN0 _L_(13) +#define PINMUX_PA16N_CCL_IN0 ((PIN_PA16N_CCL_IN0 << 16) | MUX_PA16N_CCL_IN0) +#define PORT_PA16N_CCL_IN0 (_UL_(1) << 16) +#define PIN_PB22N_CCL_IN0 _L_(54) /**< \brief CCL signal: IN0 on PB22 mux N */ +#define MUX_PB22N_CCL_IN0 _L_(13) +#define PINMUX_PB22N_CCL_IN0 ((PIN_PB22N_CCL_IN0 << 16) | MUX_PB22N_CCL_IN0) +#define PORT_PB22N_CCL_IN0 (_UL_(1) << 22) +#define PIN_PA05N_CCL_IN1 _L_(5) /**< \brief CCL signal: IN1 on PA05 mux N */ +#define MUX_PA05N_CCL_IN1 _L_(13) +#define PINMUX_PA05N_CCL_IN1 ((PIN_PA05N_CCL_IN1 << 16) | MUX_PA05N_CCL_IN1) +#define PORT_PA05N_CCL_IN1 (_UL_(1) << 5) +#define PIN_PA17N_CCL_IN1 _L_(17) /**< \brief CCL signal: IN1 on PA17 mux N */ +#define MUX_PA17N_CCL_IN1 _L_(13) +#define PINMUX_PA17N_CCL_IN1 ((PIN_PA17N_CCL_IN1 << 16) | MUX_PA17N_CCL_IN1) +#define PORT_PA17N_CCL_IN1 (_UL_(1) << 17) +#define PIN_PB00N_CCL_IN1 _L_(32) /**< \brief CCL signal: IN1 on PB00 mux N */ +#define MUX_PB00N_CCL_IN1 _L_(13) +#define PINMUX_PB00N_CCL_IN1 ((PIN_PB00N_CCL_IN1 << 16) | MUX_PB00N_CCL_IN1) +#define PORT_PB00N_CCL_IN1 (_UL_(1) << 0) +#define PIN_PA06N_CCL_IN2 _L_(6) /**< \brief CCL signal: IN2 on PA06 mux N */ +#define MUX_PA06N_CCL_IN2 _L_(13) +#define PINMUX_PA06N_CCL_IN2 ((PIN_PA06N_CCL_IN2 << 16) | MUX_PA06N_CCL_IN2) +#define PORT_PA06N_CCL_IN2 (_UL_(1) << 6) +#define PIN_PA18N_CCL_IN2 _L_(18) /**< \brief CCL signal: IN2 on PA18 mux N */ +#define MUX_PA18N_CCL_IN2 _L_(13) +#define PINMUX_PA18N_CCL_IN2 ((PIN_PA18N_CCL_IN2 << 16) | MUX_PA18N_CCL_IN2) +#define PORT_PA18N_CCL_IN2 (_UL_(1) << 18) +#define PIN_PB01N_CCL_IN2 _L_(33) /**< \brief CCL signal: IN2 on PB01 mux N */ +#define MUX_PB01N_CCL_IN2 _L_(13) +#define PINMUX_PB01N_CCL_IN2 ((PIN_PB01N_CCL_IN2 << 16) | MUX_PB01N_CCL_IN2) +#define PORT_PB01N_CCL_IN2 (_UL_(1) << 1) +#define PIN_PA08N_CCL_IN3 _L_(8) /**< \brief CCL signal: IN3 on PA08 mux N */ +#define MUX_PA08N_CCL_IN3 _L_(13) +#define PINMUX_PA08N_CCL_IN3 ((PIN_PA08N_CCL_IN3 << 16) | MUX_PA08N_CCL_IN3) +#define PORT_PA08N_CCL_IN3 (_UL_(1) << 8) +#define PIN_PA30N_CCL_IN3 _L_(30) /**< \brief CCL signal: IN3 on PA30 mux N */ +#define MUX_PA30N_CCL_IN3 _L_(13) +#define PINMUX_PA30N_CCL_IN3 ((PIN_PA30N_CCL_IN3 << 16) | MUX_PA30N_CCL_IN3) +#define PORT_PA30N_CCL_IN3 (_UL_(1) << 30) +#define PIN_PA09N_CCL_IN4 _L_(9) /**< \brief CCL signal: IN4 on PA09 mux N */ +#define MUX_PA09N_CCL_IN4 _L_(13) +#define PINMUX_PA09N_CCL_IN4 ((PIN_PA09N_CCL_IN4 << 16) | MUX_PA09N_CCL_IN4) +#define PORT_PA09N_CCL_IN4 (_UL_(1) << 9) +#define PIN_PC27N_CCL_IN4 _L_(91) /**< \brief CCL signal: IN4 on PC27 mux N */ +#define MUX_PC27N_CCL_IN4 _L_(13) +#define PINMUX_PC27N_CCL_IN4 ((PIN_PC27N_CCL_IN4 << 16) | MUX_PC27N_CCL_IN4) +#define PORT_PC27N_CCL_IN4 (_UL_(1) << 27) +#define PIN_PA10N_CCL_IN5 _L_(10) /**< \brief CCL signal: IN5 on PA10 mux N */ +#define MUX_PA10N_CCL_IN5 _L_(13) +#define PINMUX_PA10N_CCL_IN5 ((PIN_PA10N_CCL_IN5 << 16) | MUX_PA10N_CCL_IN5) +#define PORT_PA10N_CCL_IN5 (_UL_(1) << 10) +#define PIN_PC28N_CCL_IN5 _L_(92) /**< \brief CCL signal: IN5 on PC28 mux N */ +#define MUX_PC28N_CCL_IN5 _L_(13) +#define PINMUX_PC28N_CCL_IN5 ((PIN_PC28N_CCL_IN5 << 16) | MUX_PC28N_CCL_IN5) +#define PORT_PC28N_CCL_IN5 (_UL_(1) << 28) +#define PIN_PA22N_CCL_IN6 _L_(22) /**< \brief CCL signal: IN6 on PA22 mux N */ +#define MUX_PA22N_CCL_IN6 _L_(13) +#define PINMUX_PA22N_CCL_IN6 ((PIN_PA22N_CCL_IN6 << 16) | MUX_PA22N_CCL_IN6) +#define PORT_PA22N_CCL_IN6 (_UL_(1) << 22) +#define PIN_PB06N_CCL_IN6 _L_(38) /**< \brief CCL signal: IN6 on PB06 mux N */ +#define MUX_PB06N_CCL_IN6 _L_(13) +#define PINMUX_PB06N_CCL_IN6 ((PIN_PB06N_CCL_IN6 << 16) | MUX_PB06N_CCL_IN6) +#define PORT_PB06N_CCL_IN6 (_UL_(1) << 6) +#define PIN_PA23N_CCL_IN7 _L_(23) /**< \brief CCL signal: IN7 on PA23 mux N */ +#define MUX_PA23N_CCL_IN7 _L_(13) +#define PINMUX_PA23N_CCL_IN7 ((PIN_PA23N_CCL_IN7 << 16) | MUX_PA23N_CCL_IN7) +#define PORT_PA23N_CCL_IN7 (_UL_(1) << 23) +#define PIN_PB07N_CCL_IN7 _L_(39) /**< \brief CCL signal: IN7 on PB07 mux N */ +#define MUX_PB07N_CCL_IN7 _L_(13) +#define PINMUX_PB07N_CCL_IN7 ((PIN_PB07N_CCL_IN7 << 16) | MUX_PB07N_CCL_IN7) +#define PORT_PB07N_CCL_IN7 (_UL_(1) << 7) +#define PIN_PA24N_CCL_IN8 _L_(24) /**< \brief CCL signal: IN8 on PA24 mux N */ +#define MUX_PA24N_CCL_IN8 _L_(13) +#define PINMUX_PA24N_CCL_IN8 ((PIN_PA24N_CCL_IN8 << 16) | MUX_PA24N_CCL_IN8) +#define PORT_PA24N_CCL_IN8 (_UL_(1) << 24) +#define PIN_PB08N_CCL_IN8 _L_(40) /**< \brief CCL signal: IN8 on PB08 mux N */ +#define MUX_PB08N_CCL_IN8 _L_(13) +#define PINMUX_PB08N_CCL_IN8 ((PIN_PB08N_CCL_IN8 << 16) | MUX_PB08N_CCL_IN8) +#define PORT_PB08N_CCL_IN8 (_UL_(1) << 8) +#define PIN_PB14N_CCL_IN9 _L_(46) /**< \brief CCL signal: IN9 on PB14 mux N */ +#define MUX_PB14N_CCL_IN9 _L_(13) +#define PINMUX_PB14N_CCL_IN9 ((PIN_PB14N_CCL_IN9 << 16) | MUX_PB14N_CCL_IN9) +#define PORT_PB14N_CCL_IN9 (_UL_(1) << 14) +#define PIN_PC20N_CCL_IN9 _L_(84) /**< \brief CCL signal: IN9 on PC20 mux N */ +#define MUX_PC20N_CCL_IN9 _L_(13) +#define PINMUX_PC20N_CCL_IN9 ((PIN_PC20N_CCL_IN9 << 16) | MUX_PC20N_CCL_IN9) +#define PORT_PC20N_CCL_IN9 (_UL_(1) << 20) +#define PIN_PB15N_CCL_IN10 _L_(47) /**< \brief CCL signal: IN10 on PB15 mux N */ +#define MUX_PB15N_CCL_IN10 _L_(13) +#define PINMUX_PB15N_CCL_IN10 ((PIN_PB15N_CCL_IN10 << 16) | MUX_PB15N_CCL_IN10) +#define PORT_PB15N_CCL_IN10 (_UL_(1) << 15) +#define PIN_PC21N_CCL_IN10 _L_(85) /**< \brief CCL signal: IN10 on PC21 mux N */ +#define MUX_PC21N_CCL_IN10 _L_(13) +#define PINMUX_PC21N_CCL_IN10 ((PIN_PC21N_CCL_IN10 << 16) | MUX_PC21N_CCL_IN10) +#define PORT_PC21N_CCL_IN10 (_UL_(1) << 21) +#define PIN_PB10N_CCL_IN11 _L_(42) /**< \brief CCL signal: IN11 on PB10 mux N */ +#define MUX_PB10N_CCL_IN11 _L_(13) +#define PINMUX_PB10N_CCL_IN11 ((PIN_PB10N_CCL_IN11 << 16) | MUX_PB10N_CCL_IN11) +#define PORT_PB10N_CCL_IN11 (_UL_(1) << 10) +#define PIN_PB16N_CCL_IN11 _L_(48) /**< \brief CCL signal: IN11 on PB16 mux N */ +#define MUX_PB16N_CCL_IN11 _L_(13) +#define PINMUX_PB16N_CCL_IN11 ((PIN_PB16N_CCL_IN11 << 16) | MUX_PB16N_CCL_IN11) +#define PORT_PB16N_CCL_IN11 (_UL_(1) << 16) +#define PIN_PA07N_CCL_OUT0 _L_(7) /**< \brief CCL signal: OUT0 on PA07 mux N */ +#define MUX_PA07N_CCL_OUT0 _L_(13) +#define PINMUX_PA07N_CCL_OUT0 ((PIN_PA07N_CCL_OUT0 << 16) | MUX_PA07N_CCL_OUT0) +#define PORT_PA07N_CCL_OUT0 (_UL_(1) << 7) +#define PIN_PA19N_CCL_OUT0 _L_(19) /**< \brief CCL signal: OUT0 on PA19 mux N */ +#define MUX_PA19N_CCL_OUT0 _L_(13) +#define PINMUX_PA19N_CCL_OUT0 ((PIN_PA19N_CCL_OUT0 << 16) | MUX_PA19N_CCL_OUT0) +#define PORT_PA19N_CCL_OUT0 (_UL_(1) << 19) +#define PIN_PB02N_CCL_OUT0 _L_(34) /**< \brief CCL signal: OUT0 on PB02 mux N */ +#define MUX_PB02N_CCL_OUT0 _L_(13) +#define PINMUX_PB02N_CCL_OUT0 ((PIN_PB02N_CCL_OUT0 << 16) | MUX_PB02N_CCL_OUT0) +#define PORT_PB02N_CCL_OUT0 (_UL_(1) << 2) +#define PIN_PB23N_CCL_OUT0 _L_(55) /**< \brief CCL signal: OUT0 on PB23 mux N */ +#define MUX_PB23N_CCL_OUT0 _L_(13) +#define PINMUX_PB23N_CCL_OUT0 ((PIN_PB23N_CCL_OUT0 << 16) | MUX_PB23N_CCL_OUT0) +#define PORT_PB23N_CCL_OUT0 (_UL_(1) << 23) +#define PIN_PA11N_CCL_OUT1 _L_(11) /**< \brief CCL signal: OUT1 on PA11 mux N */ +#define MUX_PA11N_CCL_OUT1 _L_(13) +#define PINMUX_PA11N_CCL_OUT1 ((PIN_PA11N_CCL_OUT1 << 16) | MUX_PA11N_CCL_OUT1) +#define PORT_PA11N_CCL_OUT1 (_UL_(1) << 11) +#define PIN_PA31N_CCL_OUT1 _L_(31) /**< \brief CCL signal: OUT1 on PA31 mux N */ +#define MUX_PA31N_CCL_OUT1 _L_(13) +#define PINMUX_PA31N_CCL_OUT1 ((PIN_PA31N_CCL_OUT1 << 16) | MUX_PA31N_CCL_OUT1) +#define PORT_PA31N_CCL_OUT1 (_UL_(1) << 31) +#define PIN_PB11N_CCL_OUT1 _L_(43) /**< \brief CCL signal: OUT1 on PB11 mux N */ +#define MUX_PB11N_CCL_OUT1 _L_(13) +#define PINMUX_PB11N_CCL_OUT1 ((PIN_PB11N_CCL_OUT1 << 16) | MUX_PB11N_CCL_OUT1) +#define PORT_PB11N_CCL_OUT1 (_UL_(1) << 11) +#define PIN_PA25N_CCL_OUT2 _L_(25) /**< \brief CCL signal: OUT2 on PA25 mux N */ +#define MUX_PA25N_CCL_OUT2 _L_(13) +#define PINMUX_PA25N_CCL_OUT2 ((PIN_PA25N_CCL_OUT2 << 16) | MUX_PA25N_CCL_OUT2) +#define PORT_PA25N_CCL_OUT2 (_UL_(1) << 25) +#define PIN_PB09N_CCL_OUT2 _L_(41) /**< \brief CCL signal: OUT2 on PB09 mux N */ +#define MUX_PB09N_CCL_OUT2 _L_(13) +#define PINMUX_PB09N_CCL_OUT2 ((PIN_PB09N_CCL_OUT2 << 16) | MUX_PB09N_CCL_OUT2) +#define PORT_PB09N_CCL_OUT2 (_UL_(1) << 9) +#define PIN_PB17N_CCL_OUT3 _L_(49) /**< \brief CCL signal: OUT3 on PB17 mux N */ +#define MUX_PB17N_CCL_OUT3 _L_(13) +#define PINMUX_PB17N_CCL_OUT3 ((PIN_PB17N_CCL_OUT3 << 16) | MUX_PB17N_CCL_OUT3) +#define PORT_PB17N_CCL_OUT3 (_UL_(1) << 17) +/* ========== PORT definition for SERCOM4 peripheral ========== */ +#define PIN_PA13D_SERCOM4_PAD0 _L_(13) /**< \brief SERCOM4 signal: PAD0 on PA13 mux D */ +#define MUX_PA13D_SERCOM4_PAD0 _L_(3) +#define PINMUX_PA13D_SERCOM4_PAD0 ((PIN_PA13D_SERCOM4_PAD0 << 16) | MUX_PA13D_SERCOM4_PAD0) +#define PORT_PA13D_SERCOM4_PAD0 (_UL_(1) << 13) +#define PIN_PB08D_SERCOM4_PAD0 _L_(40) /**< \brief SERCOM4 signal: PAD0 on PB08 mux D */ +#define MUX_PB08D_SERCOM4_PAD0 _L_(3) +#define PINMUX_PB08D_SERCOM4_PAD0 ((PIN_PB08D_SERCOM4_PAD0 << 16) | MUX_PB08D_SERCOM4_PAD0) +#define PORT_PB08D_SERCOM4_PAD0 (_UL_(1) << 8) +#define PIN_PB12C_SERCOM4_PAD0 _L_(44) /**< \brief SERCOM4 signal: PAD0 on PB12 mux C */ +#define MUX_PB12C_SERCOM4_PAD0 _L_(2) +#define PINMUX_PB12C_SERCOM4_PAD0 ((PIN_PB12C_SERCOM4_PAD0 << 16) | MUX_PB12C_SERCOM4_PAD0) +#define PORT_PB12C_SERCOM4_PAD0 (_UL_(1) << 12) +#define PIN_PA12D_SERCOM4_PAD1 _L_(12) /**< \brief SERCOM4 signal: PAD1 on PA12 mux D */ +#define MUX_PA12D_SERCOM4_PAD1 _L_(3) +#define PINMUX_PA12D_SERCOM4_PAD1 ((PIN_PA12D_SERCOM4_PAD1 << 16) | MUX_PA12D_SERCOM4_PAD1) +#define PORT_PA12D_SERCOM4_PAD1 (_UL_(1) << 12) +#define PIN_PB09D_SERCOM4_PAD1 _L_(41) /**< \brief SERCOM4 signal: PAD1 on PB09 mux D */ +#define MUX_PB09D_SERCOM4_PAD1 _L_(3) +#define PINMUX_PB09D_SERCOM4_PAD1 ((PIN_PB09D_SERCOM4_PAD1 << 16) | MUX_PB09D_SERCOM4_PAD1) +#define PORT_PB09D_SERCOM4_PAD1 (_UL_(1) << 9) +#define PIN_PB13C_SERCOM4_PAD1 _L_(45) /**< \brief SERCOM4 signal: PAD1 on PB13 mux C */ +#define MUX_PB13C_SERCOM4_PAD1 _L_(2) +#define PINMUX_PB13C_SERCOM4_PAD1 ((PIN_PB13C_SERCOM4_PAD1 << 16) | MUX_PB13C_SERCOM4_PAD1) +#define PORT_PB13C_SERCOM4_PAD1 (_UL_(1) << 13) +#define PIN_PA14D_SERCOM4_PAD2 _L_(14) /**< \brief SERCOM4 signal: PAD2 on PA14 mux D */ +#define MUX_PA14D_SERCOM4_PAD2 _L_(3) +#define PINMUX_PA14D_SERCOM4_PAD2 ((PIN_PA14D_SERCOM4_PAD2 << 16) | MUX_PA14D_SERCOM4_PAD2) +#define PORT_PA14D_SERCOM4_PAD2 (_UL_(1) << 14) +#define PIN_PB10D_SERCOM4_PAD2 _L_(42) /**< \brief SERCOM4 signal: PAD2 on PB10 mux D */ +#define MUX_PB10D_SERCOM4_PAD2 _L_(3) +#define PINMUX_PB10D_SERCOM4_PAD2 ((PIN_PB10D_SERCOM4_PAD2 << 16) | MUX_PB10D_SERCOM4_PAD2) +#define PORT_PB10D_SERCOM4_PAD2 (_UL_(1) << 10) +#define PIN_PB14C_SERCOM4_PAD2 _L_(46) /**< \brief SERCOM4 signal: PAD2 on PB14 mux C */ +#define MUX_PB14C_SERCOM4_PAD2 _L_(2) +#define PINMUX_PB14C_SERCOM4_PAD2 ((PIN_PB14C_SERCOM4_PAD2 << 16) | MUX_PB14C_SERCOM4_PAD2) +#define PORT_PB14C_SERCOM4_PAD2 (_UL_(1) << 14) +#define PIN_PB11D_SERCOM4_PAD3 _L_(43) /**< \brief SERCOM4 signal: PAD3 on PB11 mux D */ +#define MUX_PB11D_SERCOM4_PAD3 _L_(3) +#define PINMUX_PB11D_SERCOM4_PAD3 ((PIN_PB11D_SERCOM4_PAD3 << 16) | MUX_PB11D_SERCOM4_PAD3) +#define PORT_PB11D_SERCOM4_PAD3 (_UL_(1) << 11) +#define PIN_PA15D_SERCOM4_PAD3 _L_(15) /**< \brief SERCOM4 signal: PAD3 on PA15 mux D */ +#define MUX_PA15D_SERCOM4_PAD3 _L_(3) +#define PINMUX_PA15D_SERCOM4_PAD3 ((PIN_PA15D_SERCOM4_PAD3 << 16) | MUX_PA15D_SERCOM4_PAD3) +#define PORT_PA15D_SERCOM4_PAD3 (_UL_(1) << 15) +#define PIN_PB15C_SERCOM4_PAD3 _L_(47) /**< \brief SERCOM4 signal: PAD3 on PB15 mux C */ +#define MUX_PB15C_SERCOM4_PAD3 _L_(2) +#define PINMUX_PB15C_SERCOM4_PAD3 ((PIN_PB15C_SERCOM4_PAD3 << 16) | MUX_PB15C_SERCOM4_PAD3) +#define PORT_PB15C_SERCOM4_PAD3 (_UL_(1) << 15) +/* ========== PORT definition for SERCOM5 peripheral ========== */ +#define PIN_PA23D_SERCOM5_PAD0 _L_(23) /**< \brief SERCOM5 signal: PAD0 on PA23 mux D */ +#define MUX_PA23D_SERCOM5_PAD0 _L_(3) +#define PINMUX_PA23D_SERCOM5_PAD0 ((PIN_PA23D_SERCOM5_PAD0 << 16) | MUX_PA23D_SERCOM5_PAD0) +#define PORT_PA23D_SERCOM5_PAD0 (_UL_(1) << 23) +#define PIN_PB02D_SERCOM5_PAD0 _L_(34) /**< \brief SERCOM5 signal: PAD0 on PB02 mux D */ +#define MUX_PB02D_SERCOM5_PAD0 _L_(3) +#define PINMUX_PB02D_SERCOM5_PAD0 ((PIN_PB02D_SERCOM5_PAD0 << 16) | MUX_PB02D_SERCOM5_PAD0) +#define PORT_PB02D_SERCOM5_PAD0 (_UL_(1) << 2) +#define PIN_PB31D_SERCOM5_PAD0 _L_(63) /**< \brief SERCOM5 signal: PAD0 on PB31 mux D */ +#define MUX_PB31D_SERCOM5_PAD0 _L_(3) +#define PINMUX_PB31D_SERCOM5_PAD0 ((PIN_PB31D_SERCOM5_PAD0 << 16) | MUX_PB31D_SERCOM5_PAD0) +#define PORT_PB31D_SERCOM5_PAD0 (_UL_(1) << 31) +#define PIN_PB16C_SERCOM5_PAD0 _L_(48) /**< \brief SERCOM5 signal: PAD0 on PB16 mux C */ +#define MUX_PB16C_SERCOM5_PAD0 _L_(2) +#define PINMUX_PB16C_SERCOM5_PAD0 ((PIN_PB16C_SERCOM5_PAD0 << 16) | MUX_PB16C_SERCOM5_PAD0) +#define PORT_PB16C_SERCOM5_PAD0 (_UL_(1) << 16) +#define PIN_PA22D_SERCOM5_PAD1 _L_(22) /**< \brief SERCOM5 signal: PAD1 on PA22 mux D */ +#define MUX_PA22D_SERCOM5_PAD1 _L_(3) +#define PINMUX_PA22D_SERCOM5_PAD1 ((PIN_PA22D_SERCOM5_PAD1 << 16) | MUX_PA22D_SERCOM5_PAD1) +#define PORT_PA22D_SERCOM5_PAD1 (_UL_(1) << 22) +#define PIN_PB03D_SERCOM5_PAD1 _L_(35) /**< \brief SERCOM5 signal: PAD1 on PB03 mux D */ +#define MUX_PB03D_SERCOM5_PAD1 _L_(3) +#define PINMUX_PB03D_SERCOM5_PAD1 ((PIN_PB03D_SERCOM5_PAD1 << 16) | MUX_PB03D_SERCOM5_PAD1) +#define PORT_PB03D_SERCOM5_PAD1 (_UL_(1) << 3) +#define PIN_PB30D_SERCOM5_PAD1 _L_(62) /**< \brief SERCOM5 signal: PAD1 on PB30 mux D */ +#define MUX_PB30D_SERCOM5_PAD1 _L_(3) +#define PINMUX_PB30D_SERCOM5_PAD1 ((PIN_PB30D_SERCOM5_PAD1 << 16) | MUX_PB30D_SERCOM5_PAD1) +#define PORT_PB30D_SERCOM5_PAD1 (_UL_(1) << 30) +#define PIN_PB17C_SERCOM5_PAD1 _L_(49) /**< \brief SERCOM5 signal: PAD1 on PB17 mux C */ +#define MUX_PB17C_SERCOM5_PAD1 _L_(2) +#define PINMUX_PB17C_SERCOM5_PAD1 ((PIN_PB17C_SERCOM5_PAD1 << 16) | MUX_PB17C_SERCOM5_PAD1) +#define PORT_PB17C_SERCOM5_PAD1 (_UL_(1) << 17) +#define PIN_PA24D_SERCOM5_PAD2 _L_(24) /**< \brief SERCOM5 signal: PAD2 on PA24 mux D */ +#define MUX_PA24D_SERCOM5_PAD2 _L_(3) +#define PINMUX_PA24D_SERCOM5_PAD2 ((PIN_PA24D_SERCOM5_PAD2 << 16) | MUX_PA24D_SERCOM5_PAD2) +#define PORT_PA24D_SERCOM5_PAD2 (_UL_(1) << 24) +#define PIN_PB00D_SERCOM5_PAD2 _L_(32) /**< \brief SERCOM5 signal: PAD2 on PB00 mux D */ +#define MUX_PB00D_SERCOM5_PAD2 _L_(3) +#define PINMUX_PB00D_SERCOM5_PAD2 ((PIN_PB00D_SERCOM5_PAD2 << 16) | MUX_PB00D_SERCOM5_PAD2) +#define PORT_PB00D_SERCOM5_PAD2 (_UL_(1) << 0) +#define PIN_PB22D_SERCOM5_PAD2 _L_(54) /**< \brief SERCOM5 signal: PAD2 on PB22 mux D */ +#define MUX_PB22D_SERCOM5_PAD2 _L_(3) +#define PINMUX_PB22D_SERCOM5_PAD2 ((PIN_PB22D_SERCOM5_PAD2 << 16) | MUX_PB22D_SERCOM5_PAD2) +#define PORT_PB22D_SERCOM5_PAD2 (_UL_(1) << 22) +#define PIN_PA20C_SERCOM5_PAD2 _L_(20) /**< \brief SERCOM5 signal: PAD2 on PA20 mux C */ +#define MUX_PA20C_SERCOM5_PAD2 _L_(2) +#define PINMUX_PA20C_SERCOM5_PAD2 ((PIN_PA20C_SERCOM5_PAD2 << 16) | MUX_PA20C_SERCOM5_PAD2) +#define PORT_PA20C_SERCOM5_PAD2 (_UL_(1) << 20) +#define PIN_PB18C_SERCOM5_PAD2 _L_(50) /**< \brief SERCOM5 signal: PAD2 on PB18 mux C */ +#define MUX_PB18C_SERCOM5_PAD2 _L_(2) +#define PINMUX_PB18C_SERCOM5_PAD2 ((PIN_PB18C_SERCOM5_PAD2 << 16) | MUX_PB18C_SERCOM5_PAD2) +#define PORT_PB18C_SERCOM5_PAD2 (_UL_(1) << 18) +#define PIN_PA25D_SERCOM5_PAD3 _L_(25) /**< \brief SERCOM5 signal: PAD3 on PA25 mux D */ +#define MUX_PA25D_SERCOM5_PAD3 _L_(3) +#define PINMUX_PA25D_SERCOM5_PAD3 ((PIN_PA25D_SERCOM5_PAD3 << 16) | MUX_PA25D_SERCOM5_PAD3) +#define PORT_PA25D_SERCOM5_PAD3 (_UL_(1) << 25) +#define PIN_PB01D_SERCOM5_PAD3 _L_(33) /**< \brief SERCOM5 signal: PAD3 on PB01 mux D */ +#define MUX_PB01D_SERCOM5_PAD3 _L_(3) +#define PINMUX_PB01D_SERCOM5_PAD3 ((PIN_PB01D_SERCOM5_PAD3 << 16) | MUX_PB01D_SERCOM5_PAD3) +#define PORT_PB01D_SERCOM5_PAD3 (_UL_(1) << 1) +#define PIN_PB23D_SERCOM5_PAD3 _L_(55) /**< \brief SERCOM5 signal: PAD3 on PB23 mux D */ +#define MUX_PB23D_SERCOM5_PAD3 _L_(3) +#define PINMUX_PB23D_SERCOM5_PAD3 ((PIN_PB23D_SERCOM5_PAD3 << 16) | MUX_PB23D_SERCOM5_PAD3) +#define PORT_PB23D_SERCOM5_PAD3 (_UL_(1) << 23) +#define PIN_PA21C_SERCOM5_PAD3 _L_(21) /**< \brief SERCOM5 signal: PAD3 on PA21 mux C */ +#define MUX_PA21C_SERCOM5_PAD3 _L_(2) +#define PINMUX_PA21C_SERCOM5_PAD3 ((PIN_PA21C_SERCOM5_PAD3 << 16) | MUX_PA21C_SERCOM5_PAD3) +#define PORT_PA21C_SERCOM5_PAD3 (_UL_(1) << 21) +#define PIN_PB19C_SERCOM5_PAD3 _L_(51) /**< \brief SERCOM5 signal: PAD3 on PB19 mux C */ +#define MUX_PB19C_SERCOM5_PAD3 _L_(2) +#define PINMUX_PB19C_SERCOM5_PAD3 ((PIN_PB19C_SERCOM5_PAD3 << 16) | MUX_PB19C_SERCOM5_PAD3) +#define PORT_PB19C_SERCOM5_PAD3 (_UL_(1) << 19) +/* ========== PORT definition for SERCOM6 peripheral ========== */ +#define PIN_PC13D_SERCOM6_PAD0 _L_(77) /**< \brief SERCOM6 signal: PAD0 on PC13 mux D */ +#define MUX_PC13D_SERCOM6_PAD0 _L_(3) +#define PINMUX_PC13D_SERCOM6_PAD0 ((PIN_PC13D_SERCOM6_PAD0 << 16) | MUX_PC13D_SERCOM6_PAD0) +#define PORT_PC13D_SERCOM6_PAD0 (_UL_(1) << 13) +#define PIN_PC16C_SERCOM6_PAD0 _L_(80) /**< \brief SERCOM6 signal: PAD0 on PC16 mux C */ +#define MUX_PC16C_SERCOM6_PAD0 _L_(2) +#define PINMUX_PC16C_SERCOM6_PAD0 ((PIN_PC16C_SERCOM6_PAD0 << 16) | MUX_PC16C_SERCOM6_PAD0) +#define PORT_PC16C_SERCOM6_PAD0 (_UL_(1) << 16) +#define PIN_PC12D_SERCOM6_PAD1 _L_(76) /**< \brief SERCOM6 signal: PAD1 on PC12 mux D */ +#define MUX_PC12D_SERCOM6_PAD1 _L_(3) +#define PINMUX_PC12D_SERCOM6_PAD1 ((PIN_PC12D_SERCOM6_PAD1 << 16) | MUX_PC12D_SERCOM6_PAD1) +#define PORT_PC12D_SERCOM6_PAD1 (_UL_(1) << 12) +#define PIN_PC05C_SERCOM6_PAD1 _L_(69) /**< \brief SERCOM6 signal: PAD1 on PC05 mux C */ +#define MUX_PC05C_SERCOM6_PAD1 _L_(2) +#define PINMUX_PC05C_SERCOM6_PAD1 ((PIN_PC05C_SERCOM6_PAD1 << 16) | MUX_PC05C_SERCOM6_PAD1) +#define PORT_PC05C_SERCOM6_PAD1 (_UL_(1) << 5) +#define PIN_PC17C_SERCOM6_PAD1 _L_(81) /**< \brief SERCOM6 signal: PAD1 on PC17 mux C */ +#define MUX_PC17C_SERCOM6_PAD1 _L_(2) +#define PINMUX_PC17C_SERCOM6_PAD1 ((PIN_PC17C_SERCOM6_PAD1 << 16) | MUX_PC17C_SERCOM6_PAD1) +#define PORT_PC17C_SERCOM6_PAD1 (_UL_(1) << 17) +#define PIN_PC14D_SERCOM6_PAD2 _L_(78) /**< \brief SERCOM6 signal: PAD2 on PC14 mux D */ +#define MUX_PC14D_SERCOM6_PAD2 _L_(3) +#define PINMUX_PC14D_SERCOM6_PAD2 ((PIN_PC14D_SERCOM6_PAD2 << 16) | MUX_PC14D_SERCOM6_PAD2) +#define PORT_PC14D_SERCOM6_PAD2 (_UL_(1) << 14) +#define PIN_PC06C_SERCOM6_PAD2 _L_(70) /**< \brief SERCOM6 signal: PAD2 on PC06 mux C */ +#define MUX_PC06C_SERCOM6_PAD2 _L_(2) +#define PINMUX_PC06C_SERCOM6_PAD2 ((PIN_PC06C_SERCOM6_PAD2 << 16) | MUX_PC06C_SERCOM6_PAD2) +#define PORT_PC06C_SERCOM6_PAD2 (_UL_(1) << 6) +#define PIN_PC10C_SERCOM6_PAD2 _L_(74) /**< \brief SERCOM6 signal: PAD2 on PC10 mux C */ +#define MUX_PC10C_SERCOM6_PAD2 _L_(2) +#define PINMUX_PC10C_SERCOM6_PAD2 ((PIN_PC10C_SERCOM6_PAD2 << 16) | MUX_PC10C_SERCOM6_PAD2) +#define PORT_PC10C_SERCOM6_PAD2 (_UL_(1) << 10) +#define PIN_PC18C_SERCOM6_PAD2 _L_(82) /**< \brief SERCOM6 signal: PAD2 on PC18 mux C */ +#define MUX_PC18C_SERCOM6_PAD2 _L_(2) +#define PINMUX_PC18C_SERCOM6_PAD2 ((PIN_PC18C_SERCOM6_PAD2 << 16) | MUX_PC18C_SERCOM6_PAD2) +#define PORT_PC18C_SERCOM6_PAD2 (_UL_(1) << 18) +#define PIN_PC15D_SERCOM6_PAD3 _L_(79) /**< \brief SERCOM6 signal: PAD3 on PC15 mux D */ +#define MUX_PC15D_SERCOM6_PAD3 _L_(3) +#define PINMUX_PC15D_SERCOM6_PAD3 ((PIN_PC15D_SERCOM6_PAD3 << 16) | MUX_PC15D_SERCOM6_PAD3) +#define PORT_PC15D_SERCOM6_PAD3 (_UL_(1) << 15) +#define PIN_PC07C_SERCOM6_PAD3 _L_(71) /**< \brief SERCOM6 signal: PAD3 on PC07 mux C */ +#define MUX_PC07C_SERCOM6_PAD3 _L_(2) +#define PINMUX_PC07C_SERCOM6_PAD3 ((PIN_PC07C_SERCOM6_PAD3 << 16) | MUX_PC07C_SERCOM6_PAD3) +#define PORT_PC07C_SERCOM6_PAD3 (_UL_(1) << 7) +#define PIN_PC11C_SERCOM6_PAD3 _L_(75) /**< \brief SERCOM6 signal: PAD3 on PC11 mux C */ +#define MUX_PC11C_SERCOM6_PAD3 _L_(2) +#define PINMUX_PC11C_SERCOM6_PAD3 ((PIN_PC11C_SERCOM6_PAD3 << 16) | MUX_PC11C_SERCOM6_PAD3) +#define PORT_PC11C_SERCOM6_PAD3 (_UL_(1) << 11) +#define PIN_PC19C_SERCOM6_PAD3 _L_(83) /**< \brief SERCOM6 signal: PAD3 on PC19 mux C */ +#define MUX_PC19C_SERCOM6_PAD3 _L_(2) +#define PINMUX_PC19C_SERCOM6_PAD3 ((PIN_PC19C_SERCOM6_PAD3 << 16) | MUX_PC19C_SERCOM6_PAD3) +#define PORT_PC19C_SERCOM6_PAD3 (_UL_(1) << 19) +/* ========== PORT definition for SERCOM7 peripheral ========== */ +#define PIN_PB21D_SERCOM7_PAD0 _L_(53) /**< \brief SERCOM7 signal: PAD0 on PB21 mux D */ +#define MUX_PB21D_SERCOM7_PAD0 _L_(3) +#define PINMUX_PB21D_SERCOM7_PAD0 ((PIN_PB21D_SERCOM7_PAD0 << 16) | MUX_PB21D_SERCOM7_PAD0) +#define PORT_PB21D_SERCOM7_PAD0 (_UL_(1) << 21) +#define PIN_PB30C_SERCOM7_PAD0 _L_(62) /**< \brief SERCOM7 signal: PAD0 on PB30 mux C */ +#define MUX_PB30C_SERCOM7_PAD0 _L_(2) +#define PINMUX_PB30C_SERCOM7_PAD0 ((PIN_PB30C_SERCOM7_PAD0 << 16) | MUX_PB30C_SERCOM7_PAD0) +#define PORT_PB30C_SERCOM7_PAD0 (_UL_(1) << 30) +#define PIN_PC12C_SERCOM7_PAD0 _L_(76) /**< \brief SERCOM7 signal: PAD0 on PC12 mux C */ +#define MUX_PC12C_SERCOM7_PAD0 _L_(2) +#define PINMUX_PC12C_SERCOM7_PAD0 ((PIN_PC12C_SERCOM7_PAD0 << 16) | MUX_PC12C_SERCOM7_PAD0) +#define PORT_PC12C_SERCOM7_PAD0 (_UL_(1) << 12) +#define PIN_PB20D_SERCOM7_PAD1 _L_(52) /**< \brief SERCOM7 signal: PAD1 on PB20 mux D */ +#define MUX_PB20D_SERCOM7_PAD1 _L_(3) +#define PINMUX_PB20D_SERCOM7_PAD1 ((PIN_PB20D_SERCOM7_PAD1 << 16) | MUX_PB20D_SERCOM7_PAD1) +#define PORT_PB20D_SERCOM7_PAD1 (_UL_(1) << 20) +#define PIN_PB31C_SERCOM7_PAD1 _L_(63) /**< \brief SERCOM7 signal: PAD1 on PB31 mux C */ +#define MUX_PB31C_SERCOM7_PAD1 _L_(2) +#define PINMUX_PB31C_SERCOM7_PAD1 ((PIN_PB31C_SERCOM7_PAD1 << 16) | MUX_PB31C_SERCOM7_PAD1) +#define PORT_PB31C_SERCOM7_PAD1 (_UL_(1) << 31) +#define PIN_PC13C_SERCOM7_PAD1 _L_(77) /**< \brief SERCOM7 signal: PAD1 on PC13 mux C */ +#define MUX_PC13C_SERCOM7_PAD1 _L_(2) +#define PINMUX_PC13C_SERCOM7_PAD1 ((PIN_PC13C_SERCOM7_PAD1 << 16) | MUX_PC13C_SERCOM7_PAD1) +#define PORT_PC13C_SERCOM7_PAD1 (_UL_(1) << 13) +#define PIN_PB18D_SERCOM7_PAD2 _L_(50) /**< \brief SERCOM7 signal: PAD2 on PB18 mux D */ +#define MUX_PB18D_SERCOM7_PAD2 _L_(3) +#define PINMUX_PB18D_SERCOM7_PAD2 ((PIN_PB18D_SERCOM7_PAD2 << 16) | MUX_PB18D_SERCOM7_PAD2) +#define PORT_PB18D_SERCOM7_PAD2 (_UL_(1) << 18) +#define PIN_PC10D_SERCOM7_PAD2 _L_(74) /**< \brief SERCOM7 signal: PAD2 on PC10 mux D */ +#define MUX_PC10D_SERCOM7_PAD2 _L_(3) +#define PINMUX_PC10D_SERCOM7_PAD2 ((PIN_PC10D_SERCOM7_PAD2 << 16) | MUX_PC10D_SERCOM7_PAD2) +#define PORT_PC10D_SERCOM7_PAD2 (_UL_(1) << 10) +#define PIN_PC14C_SERCOM7_PAD2 _L_(78) /**< \brief SERCOM7 signal: PAD2 on PC14 mux C */ +#define MUX_PC14C_SERCOM7_PAD2 _L_(2) +#define PINMUX_PC14C_SERCOM7_PAD2 ((PIN_PC14C_SERCOM7_PAD2 << 16) | MUX_PC14C_SERCOM7_PAD2) +#define PORT_PC14C_SERCOM7_PAD2 (_UL_(1) << 14) +#define PIN_PA30C_SERCOM7_PAD2 _L_(30) /**< \brief SERCOM7 signal: PAD2 on PA30 mux C */ +#define MUX_PA30C_SERCOM7_PAD2 _L_(2) +#define PINMUX_PA30C_SERCOM7_PAD2 ((PIN_PA30C_SERCOM7_PAD2 << 16) | MUX_PA30C_SERCOM7_PAD2) +#define PORT_PA30C_SERCOM7_PAD2 (_UL_(1) << 30) +#define PIN_PB19D_SERCOM7_PAD3 _L_(51) /**< \brief SERCOM7 signal: PAD3 on PB19 mux D */ +#define MUX_PB19D_SERCOM7_PAD3 _L_(3) +#define PINMUX_PB19D_SERCOM7_PAD3 ((PIN_PB19D_SERCOM7_PAD3 << 16) | MUX_PB19D_SERCOM7_PAD3) +#define PORT_PB19D_SERCOM7_PAD3 (_UL_(1) << 19) +#define PIN_PC11D_SERCOM7_PAD3 _L_(75) /**< \brief SERCOM7 signal: PAD3 on PC11 mux D */ +#define MUX_PC11D_SERCOM7_PAD3 _L_(3) +#define PINMUX_PC11D_SERCOM7_PAD3 ((PIN_PC11D_SERCOM7_PAD3 << 16) | MUX_PC11D_SERCOM7_PAD3) +#define PORT_PC11D_SERCOM7_PAD3 (_UL_(1) << 11) +#define PIN_PC15C_SERCOM7_PAD3 _L_(79) /**< \brief SERCOM7 signal: PAD3 on PC15 mux C */ +#define MUX_PC15C_SERCOM7_PAD3 _L_(2) +#define PINMUX_PC15C_SERCOM7_PAD3 ((PIN_PC15C_SERCOM7_PAD3 << 16) | MUX_PC15C_SERCOM7_PAD3) +#define PORT_PC15C_SERCOM7_PAD3 (_UL_(1) << 15) +#define PIN_PA31C_SERCOM7_PAD3 _L_(31) /**< \brief SERCOM7 signal: PAD3 on PA31 mux C */ +#define MUX_PA31C_SERCOM7_PAD3 _L_(2) +#define PINMUX_PA31C_SERCOM7_PAD3 ((PIN_PA31C_SERCOM7_PAD3 << 16) | MUX_PA31C_SERCOM7_PAD3) +#define PORT_PA31C_SERCOM7_PAD3 (_UL_(1) << 31) +/* ========== PORT definition for TCC4 peripheral ========== */ +#define PIN_PB14F_TCC4_WO0 _L_(46) /**< \brief TCC4 signal: WO0 on PB14 mux F */ +#define MUX_PB14F_TCC4_WO0 _L_(5) +#define PINMUX_PB14F_TCC4_WO0 ((PIN_PB14F_TCC4_WO0 << 16) | MUX_PB14F_TCC4_WO0) +#define PORT_PB14F_TCC4_WO0 (_UL_(1) << 14) +#define PIN_PB30F_TCC4_WO0 _L_(62) /**< \brief TCC4 signal: WO0 on PB30 mux F */ +#define MUX_PB30F_TCC4_WO0 _L_(5) +#define PINMUX_PB30F_TCC4_WO0 ((PIN_PB30F_TCC4_WO0 << 16) | MUX_PB30F_TCC4_WO0) +#define PORT_PB30F_TCC4_WO0 (_UL_(1) << 30) +#define PIN_PB15F_TCC4_WO1 _L_(47) /**< \brief TCC4 signal: WO1 on PB15 mux F */ +#define MUX_PB15F_TCC4_WO1 _L_(5) +#define PINMUX_PB15F_TCC4_WO1 ((PIN_PB15F_TCC4_WO1 << 16) | MUX_PB15F_TCC4_WO1) +#define PORT_PB15F_TCC4_WO1 (_UL_(1) << 15) +#define PIN_PB31F_TCC4_WO1 _L_(63) /**< \brief TCC4 signal: WO1 on PB31 mux F */ +#define MUX_PB31F_TCC4_WO1 _L_(5) +#define PINMUX_PB31F_TCC4_WO1 ((PIN_PB31F_TCC4_WO1 << 16) | MUX_PB31F_TCC4_WO1) +#define PORT_PB31F_TCC4_WO1 (_UL_(1) << 31) +/* ========== PORT definition for TC6 peripheral ========== */ +#define PIN_PA30E_TC6_WO0 _L_(30) /**< \brief TC6 signal: WO0 on PA30 mux E */ +#define MUX_PA30E_TC6_WO0 _L_(4) +#define PINMUX_PA30E_TC6_WO0 ((PIN_PA30E_TC6_WO0 << 16) | MUX_PA30E_TC6_WO0) +#define PORT_PA30E_TC6_WO0 (_UL_(1) << 30) +#define PIN_PB02E_TC6_WO0 _L_(34) /**< \brief TC6 signal: WO0 on PB02 mux E */ +#define MUX_PB02E_TC6_WO0 _L_(4) +#define PINMUX_PB02E_TC6_WO0 ((PIN_PB02E_TC6_WO0 << 16) | MUX_PB02E_TC6_WO0) +#define PORT_PB02E_TC6_WO0 (_UL_(1) << 2) +#define PIN_PB16E_TC6_WO0 _L_(48) /**< \brief TC6 signal: WO0 on PB16 mux E */ +#define MUX_PB16E_TC6_WO0 _L_(4) +#define PINMUX_PB16E_TC6_WO0 ((PIN_PB16E_TC6_WO0 << 16) | MUX_PB16E_TC6_WO0) +#define PORT_PB16E_TC6_WO0 (_UL_(1) << 16) +#define PIN_PA31E_TC6_WO1 _L_(31) /**< \brief TC6 signal: WO1 on PA31 mux E */ +#define MUX_PA31E_TC6_WO1 _L_(4) +#define PINMUX_PA31E_TC6_WO1 ((PIN_PA31E_TC6_WO1 << 16) | MUX_PA31E_TC6_WO1) +#define PORT_PA31E_TC6_WO1 (_UL_(1) << 31) +#define PIN_PB03E_TC6_WO1 _L_(35) /**< \brief TC6 signal: WO1 on PB03 mux E */ +#define MUX_PB03E_TC6_WO1 _L_(4) +#define PINMUX_PB03E_TC6_WO1 ((PIN_PB03E_TC6_WO1 << 16) | MUX_PB03E_TC6_WO1) +#define PORT_PB03E_TC6_WO1 (_UL_(1) << 3) +#define PIN_PB17E_TC6_WO1 _L_(49) /**< \brief TC6 signal: WO1 on PB17 mux E */ +#define MUX_PB17E_TC6_WO1 _L_(4) +#define PINMUX_PB17E_TC6_WO1 ((PIN_PB17E_TC6_WO1 << 16) | MUX_PB17E_TC6_WO1) +#define PORT_PB17E_TC6_WO1 (_UL_(1) << 17) +/* ========== PORT definition for TC7 peripheral ========== */ +#define PIN_PA20E_TC7_WO0 _L_(20) /**< \brief TC7 signal: WO0 on PA20 mux E */ +#define MUX_PA20E_TC7_WO0 _L_(4) +#define PINMUX_PA20E_TC7_WO0 ((PIN_PA20E_TC7_WO0 << 16) | MUX_PA20E_TC7_WO0) +#define PORT_PA20E_TC7_WO0 (_UL_(1) << 20) +#define PIN_PB00E_TC7_WO0 _L_(32) /**< \brief TC7 signal: WO0 on PB00 mux E */ +#define MUX_PB00E_TC7_WO0 _L_(4) +#define PINMUX_PB00E_TC7_WO0 ((PIN_PB00E_TC7_WO0 << 16) | MUX_PB00E_TC7_WO0) +#define PORT_PB00E_TC7_WO0 (_UL_(1) << 0) +#define PIN_PB22E_TC7_WO0 _L_(54) /**< \brief TC7 signal: WO0 on PB22 mux E */ +#define MUX_PB22E_TC7_WO0 _L_(4) +#define PINMUX_PB22E_TC7_WO0 ((PIN_PB22E_TC7_WO0 << 16) | MUX_PB22E_TC7_WO0) +#define PORT_PB22E_TC7_WO0 (_UL_(1) << 22) +#define PIN_PA21E_TC7_WO1 _L_(21) /**< \brief TC7 signal: WO1 on PA21 mux E */ +#define MUX_PA21E_TC7_WO1 _L_(4) +#define PINMUX_PA21E_TC7_WO1 ((PIN_PA21E_TC7_WO1 << 16) | MUX_PA21E_TC7_WO1) +#define PORT_PA21E_TC7_WO1 (_UL_(1) << 21) +#define PIN_PB01E_TC7_WO1 _L_(33) /**< \brief TC7 signal: WO1 on PB01 mux E */ +#define MUX_PB01E_TC7_WO1 _L_(4) +#define PINMUX_PB01E_TC7_WO1 ((PIN_PB01E_TC7_WO1 << 16) | MUX_PB01E_TC7_WO1) +#define PORT_PB01E_TC7_WO1 (_UL_(1) << 1) +#define PIN_PB23E_TC7_WO1 _L_(55) /**< \brief TC7 signal: WO1 on PB23 mux E */ +#define MUX_PB23E_TC7_WO1 _L_(4) +#define PINMUX_PB23E_TC7_WO1 ((PIN_PB23E_TC7_WO1 << 16) | MUX_PB23E_TC7_WO1) +#define PORT_PB23E_TC7_WO1 (_UL_(1) << 23) +/* ========== PORT definition for ADC0 peripheral ========== */ +#define PIN_PA02B_ADC0_AIN0 _L_(2) /**< \brief ADC0 signal: AIN0 on PA02 mux B */ +#define MUX_PA02B_ADC0_AIN0 _L_(1) +#define PINMUX_PA02B_ADC0_AIN0 ((PIN_PA02B_ADC0_AIN0 << 16) | MUX_PA02B_ADC0_AIN0) +#define PORT_PA02B_ADC0_AIN0 (_UL_(1) << 2) +#define PIN_PA03B_ADC0_AIN1 _L_(3) /**< \brief ADC0 signal: AIN1 on PA03 mux B */ +#define MUX_PA03B_ADC0_AIN1 _L_(1) +#define PINMUX_PA03B_ADC0_AIN1 ((PIN_PA03B_ADC0_AIN1 << 16) | MUX_PA03B_ADC0_AIN1) +#define PORT_PA03B_ADC0_AIN1 (_UL_(1) << 3) +#define PIN_PB08B_ADC0_AIN2 _L_(40) /**< \brief ADC0 signal: AIN2 on PB08 mux B */ +#define MUX_PB08B_ADC0_AIN2 _L_(1) +#define PINMUX_PB08B_ADC0_AIN2 ((PIN_PB08B_ADC0_AIN2 << 16) | MUX_PB08B_ADC0_AIN2) +#define PORT_PB08B_ADC0_AIN2 (_UL_(1) << 8) +#define PIN_PB09B_ADC0_AIN3 _L_(41) /**< \brief ADC0 signal: AIN3 on PB09 mux B */ +#define MUX_PB09B_ADC0_AIN3 _L_(1) +#define PINMUX_PB09B_ADC0_AIN3 ((PIN_PB09B_ADC0_AIN3 << 16) | MUX_PB09B_ADC0_AIN3) +#define PORT_PB09B_ADC0_AIN3 (_UL_(1) << 9) +#define PIN_PA04B_ADC0_AIN4 _L_(4) /**< \brief ADC0 signal: AIN4 on PA04 mux B */ +#define MUX_PA04B_ADC0_AIN4 _L_(1) +#define PINMUX_PA04B_ADC0_AIN4 ((PIN_PA04B_ADC0_AIN4 << 16) | MUX_PA04B_ADC0_AIN4) +#define PORT_PA04B_ADC0_AIN4 (_UL_(1) << 4) +#define PIN_PA05B_ADC0_AIN5 _L_(5) /**< \brief ADC0 signal: AIN5 on PA05 mux B */ +#define MUX_PA05B_ADC0_AIN5 _L_(1) +#define PINMUX_PA05B_ADC0_AIN5 ((PIN_PA05B_ADC0_AIN5 << 16) | MUX_PA05B_ADC0_AIN5) +#define PORT_PA05B_ADC0_AIN5 (_UL_(1) << 5) +#define PIN_PA06B_ADC0_AIN6 _L_(6) /**< \brief ADC0 signal: AIN6 on PA06 mux B */ +#define MUX_PA06B_ADC0_AIN6 _L_(1) +#define PINMUX_PA06B_ADC0_AIN6 ((PIN_PA06B_ADC0_AIN6 << 16) | MUX_PA06B_ADC0_AIN6) +#define PORT_PA06B_ADC0_AIN6 (_UL_(1) << 6) +#define PIN_PA07B_ADC0_AIN7 _L_(7) /**< \brief ADC0 signal: AIN7 on PA07 mux B */ +#define MUX_PA07B_ADC0_AIN7 _L_(1) +#define PINMUX_PA07B_ADC0_AIN7 ((PIN_PA07B_ADC0_AIN7 << 16) | MUX_PA07B_ADC0_AIN7) +#define PORT_PA07B_ADC0_AIN7 (_UL_(1) << 7) +#define PIN_PA08B_ADC0_AIN8 _L_(8) /**< \brief ADC0 signal: AIN8 on PA08 mux B */ +#define MUX_PA08B_ADC0_AIN8 _L_(1) +#define PINMUX_PA08B_ADC0_AIN8 ((PIN_PA08B_ADC0_AIN8 << 16) | MUX_PA08B_ADC0_AIN8) +#define PORT_PA08B_ADC0_AIN8 (_UL_(1) << 8) +#define PIN_PA09B_ADC0_AIN9 _L_(9) /**< \brief ADC0 signal: AIN9 on PA09 mux B */ +#define MUX_PA09B_ADC0_AIN9 _L_(1) +#define PINMUX_PA09B_ADC0_AIN9 ((PIN_PA09B_ADC0_AIN9 << 16) | MUX_PA09B_ADC0_AIN9) +#define PORT_PA09B_ADC0_AIN9 (_UL_(1) << 9) +#define PIN_PA10B_ADC0_AIN10 _L_(10) /**< \brief ADC0 signal: AIN10 on PA10 mux B */ +#define MUX_PA10B_ADC0_AIN10 _L_(1) +#define PINMUX_PA10B_ADC0_AIN10 ((PIN_PA10B_ADC0_AIN10 << 16) | MUX_PA10B_ADC0_AIN10) +#define PORT_PA10B_ADC0_AIN10 (_UL_(1) << 10) +#define PIN_PA11B_ADC0_AIN11 _L_(11) /**< \brief ADC0 signal: AIN11 on PA11 mux B */ +#define MUX_PA11B_ADC0_AIN11 _L_(1) +#define PINMUX_PA11B_ADC0_AIN11 ((PIN_PA11B_ADC0_AIN11 << 16) | MUX_PA11B_ADC0_AIN11) +#define PORT_PA11B_ADC0_AIN11 (_UL_(1) << 11) +#define PIN_PB00B_ADC0_AIN12 _L_(32) /**< \brief ADC0 signal: AIN12 on PB00 mux B */ +#define MUX_PB00B_ADC0_AIN12 _L_(1) +#define PINMUX_PB00B_ADC0_AIN12 ((PIN_PB00B_ADC0_AIN12 << 16) | MUX_PB00B_ADC0_AIN12) +#define PORT_PB00B_ADC0_AIN12 (_UL_(1) << 0) +#define PIN_PB01B_ADC0_AIN13 _L_(33) /**< \brief ADC0 signal: AIN13 on PB01 mux B */ +#define MUX_PB01B_ADC0_AIN13 _L_(1) +#define PINMUX_PB01B_ADC0_AIN13 ((PIN_PB01B_ADC0_AIN13 << 16) | MUX_PB01B_ADC0_AIN13) +#define PORT_PB01B_ADC0_AIN13 (_UL_(1) << 1) +#define PIN_PB02B_ADC0_AIN14 _L_(34) /**< \brief ADC0 signal: AIN14 on PB02 mux B */ +#define MUX_PB02B_ADC0_AIN14 _L_(1) +#define PINMUX_PB02B_ADC0_AIN14 ((PIN_PB02B_ADC0_AIN14 << 16) | MUX_PB02B_ADC0_AIN14) +#define PORT_PB02B_ADC0_AIN14 (_UL_(1) << 2) +#define PIN_PB03B_ADC0_AIN15 _L_(35) /**< \brief ADC0 signal: AIN15 on PB03 mux B */ +#define MUX_PB03B_ADC0_AIN15 _L_(1) +#define PINMUX_PB03B_ADC0_AIN15 ((PIN_PB03B_ADC0_AIN15 << 16) | MUX_PB03B_ADC0_AIN15) +#define PORT_PB03B_ADC0_AIN15 (_UL_(1) << 3) +#define PIN_PA03O_ADC0_DRV0 _L_(3) /**< \brief ADC0 signal: DRV0 on PA03 mux O */ +#define MUX_PA03O_ADC0_DRV0 _L_(14) +#define PINMUX_PA03O_ADC0_DRV0 ((PIN_PA03O_ADC0_DRV0 << 16) | MUX_PA03O_ADC0_DRV0) +#define PORT_PA03O_ADC0_DRV0 (_UL_(1) << 3) +#define PIN_PB08O_ADC0_DRV1 _L_(40) /**< \brief ADC0 signal: DRV1 on PB08 mux O */ +#define MUX_PB08O_ADC0_DRV1 _L_(14) +#define PINMUX_PB08O_ADC0_DRV1 ((PIN_PB08O_ADC0_DRV1 << 16) | MUX_PB08O_ADC0_DRV1) +#define PORT_PB08O_ADC0_DRV1 (_UL_(1) << 8) +#define PIN_PB09O_ADC0_DRV2 _L_(41) /**< \brief ADC0 signal: DRV2 on PB09 mux O */ +#define MUX_PB09O_ADC0_DRV2 _L_(14) +#define PINMUX_PB09O_ADC0_DRV2 ((PIN_PB09O_ADC0_DRV2 << 16) | MUX_PB09O_ADC0_DRV2) +#define PORT_PB09O_ADC0_DRV2 (_UL_(1) << 9) +#define PIN_PA04O_ADC0_DRV3 _L_(4) /**< \brief ADC0 signal: DRV3 on PA04 mux O */ +#define MUX_PA04O_ADC0_DRV3 _L_(14) +#define PINMUX_PA04O_ADC0_DRV3 ((PIN_PA04O_ADC0_DRV3 << 16) | MUX_PA04O_ADC0_DRV3) +#define PORT_PA04O_ADC0_DRV3 (_UL_(1) << 4) +#define PIN_PA06O_ADC0_DRV4 _L_(6) /**< \brief ADC0 signal: DRV4 on PA06 mux O */ +#define MUX_PA06O_ADC0_DRV4 _L_(14) +#define PINMUX_PA06O_ADC0_DRV4 ((PIN_PA06O_ADC0_DRV4 << 16) | MUX_PA06O_ADC0_DRV4) +#define PORT_PA06O_ADC0_DRV4 (_UL_(1) << 6) +#define PIN_PA07O_ADC0_DRV5 _L_(7) /**< \brief ADC0 signal: DRV5 on PA07 mux O */ +#define MUX_PA07O_ADC0_DRV5 _L_(14) +#define PINMUX_PA07O_ADC0_DRV5 ((PIN_PA07O_ADC0_DRV5 << 16) | MUX_PA07O_ADC0_DRV5) +#define PORT_PA07O_ADC0_DRV5 (_UL_(1) << 7) +#define PIN_PA08O_ADC0_DRV6 _L_(8) /**< \brief ADC0 signal: DRV6 on PA08 mux O */ +#define MUX_PA08O_ADC0_DRV6 _L_(14) +#define PINMUX_PA08O_ADC0_DRV6 ((PIN_PA08O_ADC0_DRV6 << 16) | MUX_PA08O_ADC0_DRV6) +#define PORT_PA08O_ADC0_DRV6 (_UL_(1) << 8) +#define PIN_PA09O_ADC0_DRV7 _L_(9) /**< \brief ADC0 signal: DRV7 on PA09 mux O */ +#define MUX_PA09O_ADC0_DRV7 _L_(14) +#define PINMUX_PA09O_ADC0_DRV7 ((PIN_PA09O_ADC0_DRV7 << 16) | MUX_PA09O_ADC0_DRV7) +#define PORT_PA09O_ADC0_DRV7 (_UL_(1) << 9) +#define PIN_PA10O_ADC0_DRV8 _L_(10) /**< \brief ADC0 signal: DRV8 on PA10 mux O */ +#define MUX_PA10O_ADC0_DRV8 _L_(14) +#define PINMUX_PA10O_ADC0_DRV8 ((PIN_PA10O_ADC0_DRV8 << 16) | MUX_PA10O_ADC0_DRV8) +#define PORT_PA10O_ADC0_DRV8 (_UL_(1) << 10) +#define PIN_PA11O_ADC0_DRV9 _L_(11) /**< \brief ADC0 signal: DRV9 on PA11 mux O */ +#define MUX_PA11O_ADC0_DRV9 _L_(14) +#define PINMUX_PA11O_ADC0_DRV9 ((PIN_PA11O_ADC0_DRV9 << 16) | MUX_PA11O_ADC0_DRV9) +#define PORT_PA11O_ADC0_DRV9 (_UL_(1) << 11) +#define PIN_PA16O_ADC0_DRV10 _L_(16) /**< \brief ADC0 signal: DRV10 on PA16 mux O */ +#define MUX_PA16O_ADC0_DRV10 _L_(14) +#define PINMUX_PA16O_ADC0_DRV10 ((PIN_PA16O_ADC0_DRV10 << 16) | MUX_PA16O_ADC0_DRV10) +#define PORT_PA16O_ADC0_DRV10 (_UL_(1) << 16) +#define PIN_PA17O_ADC0_DRV11 _L_(17) /**< \brief ADC0 signal: DRV11 on PA17 mux O */ +#define MUX_PA17O_ADC0_DRV11 _L_(14) +#define PINMUX_PA17O_ADC0_DRV11 ((PIN_PA17O_ADC0_DRV11 << 16) | MUX_PA17O_ADC0_DRV11) +#define PORT_PA17O_ADC0_DRV11 (_UL_(1) << 17) +#define PIN_PA18O_ADC0_DRV12 _L_(18) /**< \brief ADC0 signal: DRV12 on PA18 mux O */ +#define MUX_PA18O_ADC0_DRV12 _L_(14) +#define PINMUX_PA18O_ADC0_DRV12 ((PIN_PA18O_ADC0_DRV12 << 16) | MUX_PA18O_ADC0_DRV12) +#define PORT_PA18O_ADC0_DRV12 (_UL_(1) << 18) +#define PIN_PA19O_ADC0_DRV13 _L_(19) /**< \brief ADC0 signal: DRV13 on PA19 mux O */ +#define MUX_PA19O_ADC0_DRV13 _L_(14) +#define PINMUX_PA19O_ADC0_DRV13 ((PIN_PA19O_ADC0_DRV13 << 16) | MUX_PA19O_ADC0_DRV13) +#define PORT_PA19O_ADC0_DRV13 (_UL_(1) << 19) +#define PIN_PA20O_ADC0_DRV14 _L_(20) /**< \brief ADC0 signal: DRV14 on PA20 mux O */ +#define MUX_PA20O_ADC0_DRV14 _L_(14) +#define PINMUX_PA20O_ADC0_DRV14 ((PIN_PA20O_ADC0_DRV14 << 16) | MUX_PA20O_ADC0_DRV14) +#define PORT_PA20O_ADC0_DRV14 (_UL_(1) << 20) +#define PIN_PA21O_ADC0_DRV15 _L_(21) /**< \brief ADC0 signal: DRV15 on PA21 mux O */ +#define MUX_PA21O_ADC0_DRV15 _L_(14) +#define PINMUX_PA21O_ADC0_DRV15 ((PIN_PA21O_ADC0_DRV15 << 16) | MUX_PA21O_ADC0_DRV15) +#define PORT_PA21O_ADC0_DRV15 (_UL_(1) << 21) +#define PIN_PA22O_ADC0_DRV16 _L_(22) /**< \brief ADC0 signal: DRV16 on PA22 mux O */ +#define MUX_PA22O_ADC0_DRV16 _L_(14) +#define PINMUX_PA22O_ADC0_DRV16 ((PIN_PA22O_ADC0_DRV16 << 16) | MUX_PA22O_ADC0_DRV16) +#define PORT_PA22O_ADC0_DRV16 (_UL_(1) << 22) +#define PIN_PA23O_ADC0_DRV17 _L_(23) /**< \brief ADC0 signal: DRV17 on PA23 mux O */ +#define MUX_PA23O_ADC0_DRV17 _L_(14) +#define PINMUX_PA23O_ADC0_DRV17 ((PIN_PA23O_ADC0_DRV17 << 16) | MUX_PA23O_ADC0_DRV17) +#define PORT_PA23O_ADC0_DRV17 (_UL_(1) << 23) +#define PIN_PA27O_ADC0_DRV18 _L_(27) /**< \brief ADC0 signal: DRV18 on PA27 mux O */ +#define MUX_PA27O_ADC0_DRV18 _L_(14) +#define PINMUX_PA27O_ADC0_DRV18 ((PIN_PA27O_ADC0_DRV18 << 16) | MUX_PA27O_ADC0_DRV18) +#define PORT_PA27O_ADC0_DRV18 (_UL_(1) << 27) +#define PIN_PA30O_ADC0_DRV19 _L_(30) /**< \brief ADC0 signal: DRV19 on PA30 mux O */ +#define MUX_PA30O_ADC0_DRV19 _L_(14) +#define PINMUX_PA30O_ADC0_DRV19 ((PIN_PA30O_ADC0_DRV19 << 16) | MUX_PA30O_ADC0_DRV19) +#define PORT_PA30O_ADC0_DRV19 (_UL_(1) << 30) +#define PIN_PB02O_ADC0_DRV20 _L_(34) /**< \brief ADC0 signal: DRV20 on PB02 mux O */ +#define MUX_PB02O_ADC0_DRV20 _L_(14) +#define PINMUX_PB02O_ADC0_DRV20 ((PIN_PB02O_ADC0_DRV20 << 16) | MUX_PB02O_ADC0_DRV20) +#define PORT_PB02O_ADC0_DRV20 (_UL_(1) << 2) +#define PIN_PB03O_ADC0_DRV21 _L_(35) /**< \brief ADC0 signal: DRV21 on PB03 mux O */ +#define MUX_PB03O_ADC0_DRV21 _L_(14) +#define PINMUX_PB03O_ADC0_DRV21 ((PIN_PB03O_ADC0_DRV21 << 16) | MUX_PB03O_ADC0_DRV21) +#define PORT_PB03O_ADC0_DRV21 (_UL_(1) << 3) +#define PIN_PB04O_ADC0_DRV22 _L_(36) /**< \brief ADC0 signal: DRV22 on PB04 mux O */ +#define MUX_PB04O_ADC0_DRV22 _L_(14) +#define PINMUX_PB04O_ADC0_DRV22 ((PIN_PB04O_ADC0_DRV22 << 16) | MUX_PB04O_ADC0_DRV22) +#define PORT_PB04O_ADC0_DRV22 (_UL_(1) << 4) +#define PIN_PB05O_ADC0_DRV23 _L_(37) /**< \brief ADC0 signal: DRV23 on PB05 mux O */ +#define MUX_PB05O_ADC0_DRV23 _L_(14) +#define PINMUX_PB05O_ADC0_DRV23 ((PIN_PB05O_ADC0_DRV23 << 16) | MUX_PB05O_ADC0_DRV23) +#define PORT_PB05O_ADC0_DRV23 (_UL_(1) << 5) +#define PIN_PB06O_ADC0_DRV24 _L_(38) /**< \brief ADC0 signal: DRV24 on PB06 mux O */ +#define MUX_PB06O_ADC0_DRV24 _L_(14) +#define PINMUX_PB06O_ADC0_DRV24 ((PIN_PB06O_ADC0_DRV24 << 16) | MUX_PB06O_ADC0_DRV24) +#define PORT_PB06O_ADC0_DRV24 (_UL_(1) << 6) +#define PIN_PB07O_ADC0_DRV25 _L_(39) /**< \brief ADC0 signal: DRV25 on PB07 mux O */ +#define MUX_PB07O_ADC0_DRV25 _L_(14) +#define PINMUX_PB07O_ADC0_DRV25 ((PIN_PB07O_ADC0_DRV25 << 16) | MUX_PB07O_ADC0_DRV25) +#define PORT_PB07O_ADC0_DRV25 (_UL_(1) << 7) +#define PIN_PB12O_ADC0_DRV26 _L_(44) /**< \brief ADC0 signal: DRV26 on PB12 mux O */ +#define MUX_PB12O_ADC0_DRV26 _L_(14) +#define PINMUX_PB12O_ADC0_DRV26 ((PIN_PB12O_ADC0_DRV26 << 16) | MUX_PB12O_ADC0_DRV26) +#define PORT_PB12O_ADC0_DRV26 (_UL_(1) << 12) +#define PIN_PB13O_ADC0_DRV27 _L_(45) /**< \brief ADC0 signal: DRV27 on PB13 mux O */ +#define MUX_PB13O_ADC0_DRV27 _L_(14) +#define PINMUX_PB13O_ADC0_DRV27 ((PIN_PB13O_ADC0_DRV27 << 16) | MUX_PB13O_ADC0_DRV27) +#define PORT_PB13O_ADC0_DRV27 (_UL_(1) << 13) +#define PIN_PB14O_ADC0_DRV28 _L_(46) /**< \brief ADC0 signal: DRV28 on PB14 mux O */ +#define MUX_PB14O_ADC0_DRV28 _L_(14) +#define PINMUX_PB14O_ADC0_DRV28 ((PIN_PB14O_ADC0_DRV28 << 16) | MUX_PB14O_ADC0_DRV28) +#define PORT_PB14O_ADC0_DRV28 (_UL_(1) << 14) +#define PIN_PB15O_ADC0_DRV29 _L_(47) /**< \brief ADC0 signal: DRV29 on PB15 mux O */ +#define MUX_PB15O_ADC0_DRV29 _L_(14) +#define PINMUX_PB15O_ADC0_DRV29 ((PIN_PB15O_ADC0_DRV29 << 16) | MUX_PB15O_ADC0_DRV29) +#define PORT_PB15O_ADC0_DRV29 (_UL_(1) << 15) +#define PIN_PB00O_ADC0_DRV30 _L_(32) /**< \brief ADC0 signal: DRV30 on PB00 mux O */ +#define MUX_PB00O_ADC0_DRV30 _L_(14) +#define PINMUX_PB00O_ADC0_DRV30 ((PIN_PB00O_ADC0_DRV30 << 16) | MUX_PB00O_ADC0_DRV30) +#define PORT_PB00O_ADC0_DRV30 (_UL_(1) << 0) +#define PIN_PB01O_ADC0_DRV31 _L_(33) /**< \brief ADC0 signal: DRV31 on PB01 mux O */ +#define MUX_PB01O_ADC0_DRV31 _L_(14) +#define PINMUX_PB01O_ADC0_DRV31 ((PIN_PB01O_ADC0_DRV31 << 16) | MUX_PB01O_ADC0_DRV31) +#define PORT_PB01O_ADC0_DRV31 (_UL_(1) << 1) +#define PIN_PA03B_ADC0_PTCXY0 _L_(3) /**< \brief ADC0 signal: PTCXY0 on PA03 mux B */ +#define MUX_PA03B_ADC0_PTCXY0 _L_(1) +#define PINMUX_PA03B_ADC0_PTCXY0 ((PIN_PA03B_ADC0_PTCXY0 << 16) | MUX_PA03B_ADC0_PTCXY0) +#define PORT_PA03B_ADC0_PTCXY0 (_UL_(1) << 3) +#define PIN_PB08B_ADC0_PTCXY1 _L_(40) /**< \brief ADC0 signal: PTCXY1 on PB08 mux B */ +#define MUX_PB08B_ADC0_PTCXY1 _L_(1) +#define PINMUX_PB08B_ADC0_PTCXY1 ((PIN_PB08B_ADC0_PTCXY1 << 16) | MUX_PB08B_ADC0_PTCXY1) +#define PORT_PB08B_ADC0_PTCXY1 (_UL_(1) << 8) +#define PIN_PB09B_ADC0_PTCXY2 _L_(41) /**< \brief ADC0 signal: PTCXY2 on PB09 mux B */ +#define MUX_PB09B_ADC0_PTCXY2 _L_(1) +#define PINMUX_PB09B_ADC0_PTCXY2 ((PIN_PB09B_ADC0_PTCXY2 << 16) | MUX_PB09B_ADC0_PTCXY2) +#define PORT_PB09B_ADC0_PTCXY2 (_UL_(1) << 9) +#define PIN_PA04B_ADC0_PTCXY3 _L_(4) /**< \brief ADC0 signal: PTCXY3 on PA04 mux B */ +#define MUX_PA04B_ADC0_PTCXY3 _L_(1) +#define PINMUX_PA04B_ADC0_PTCXY3 ((PIN_PA04B_ADC0_PTCXY3 << 16) | MUX_PA04B_ADC0_PTCXY3) +#define PORT_PA04B_ADC0_PTCXY3 (_UL_(1) << 4) +#define PIN_PA06B_ADC0_PTCXY4 _L_(6) /**< \brief ADC0 signal: PTCXY4 on PA06 mux B */ +#define MUX_PA06B_ADC0_PTCXY4 _L_(1) +#define PINMUX_PA06B_ADC0_PTCXY4 ((PIN_PA06B_ADC0_PTCXY4 << 16) | MUX_PA06B_ADC0_PTCXY4) +#define PORT_PA06B_ADC0_PTCXY4 (_UL_(1) << 6) +#define PIN_PA07B_ADC0_PTCXY5 _L_(7) /**< \brief ADC0 signal: PTCXY5 on PA07 mux B */ +#define MUX_PA07B_ADC0_PTCXY5 _L_(1) +#define PINMUX_PA07B_ADC0_PTCXY5 ((PIN_PA07B_ADC0_PTCXY5 << 16) | MUX_PA07B_ADC0_PTCXY5) +#define PORT_PA07B_ADC0_PTCXY5 (_UL_(1) << 7) +#define PIN_PA08B_ADC0_PTCXY6 _L_(8) /**< \brief ADC0 signal: PTCXY6 on PA08 mux B */ +#define MUX_PA08B_ADC0_PTCXY6 _L_(1) +#define PINMUX_PA08B_ADC0_PTCXY6 ((PIN_PA08B_ADC0_PTCXY6 << 16) | MUX_PA08B_ADC0_PTCXY6) +#define PORT_PA08B_ADC0_PTCXY6 (_UL_(1) << 8) +#define PIN_PA09B_ADC0_PTCXY7 _L_(9) /**< \brief ADC0 signal: PTCXY7 on PA09 mux B */ +#define MUX_PA09B_ADC0_PTCXY7 _L_(1) +#define PINMUX_PA09B_ADC0_PTCXY7 ((PIN_PA09B_ADC0_PTCXY7 << 16) | MUX_PA09B_ADC0_PTCXY7) +#define PORT_PA09B_ADC0_PTCXY7 (_UL_(1) << 9) +#define PIN_PA10B_ADC0_PTCXY8 _L_(10) /**< \brief ADC0 signal: PTCXY8 on PA10 mux B */ +#define MUX_PA10B_ADC0_PTCXY8 _L_(1) +#define PINMUX_PA10B_ADC0_PTCXY8 ((PIN_PA10B_ADC0_PTCXY8 << 16) | MUX_PA10B_ADC0_PTCXY8) +#define PORT_PA10B_ADC0_PTCXY8 (_UL_(1) << 10) +#define PIN_PA11B_ADC0_PTCXY9 _L_(11) /**< \brief ADC0 signal: PTCXY9 on PA11 mux B */ +#define MUX_PA11B_ADC0_PTCXY9 _L_(1) +#define PINMUX_PA11B_ADC0_PTCXY9 ((PIN_PA11B_ADC0_PTCXY9 << 16) | MUX_PA11B_ADC0_PTCXY9) +#define PORT_PA11B_ADC0_PTCXY9 (_UL_(1) << 11) +#define PIN_PA16B_ADC0_PTCXY10 _L_(16) /**< \brief ADC0 signal: PTCXY10 on PA16 mux B */ +#define MUX_PA16B_ADC0_PTCXY10 _L_(1) +#define PINMUX_PA16B_ADC0_PTCXY10 ((PIN_PA16B_ADC0_PTCXY10 << 16) | MUX_PA16B_ADC0_PTCXY10) +#define PORT_PA16B_ADC0_PTCXY10 (_UL_(1) << 16) +#define PIN_PA17B_ADC0_PTCXY11 _L_(17) /**< \brief ADC0 signal: PTCXY11 on PA17 mux B */ +#define MUX_PA17B_ADC0_PTCXY11 _L_(1) +#define PINMUX_PA17B_ADC0_PTCXY11 ((PIN_PA17B_ADC0_PTCXY11 << 16) | MUX_PA17B_ADC0_PTCXY11) +#define PORT_PA17B_ADC0_PTCXY11 (_UL_(1) << 17) +#define PIN_PA18B_ADC0_PTCXY12 _L_(18) /**< \brief ADC0 signal: PTCXY12 on PA18 mux B */ +#define MUX_PA18B_ADC0_PTCXY12 _L_(1) +#define PINMUX_PA18B_ADC0_PTCXY12 ((PIN_PA18B_ADC0_PTCXY12 << 16) | MUX_PA18B_ADC0_PTCXY12) +#define PORT_PA18B_ADC0_PTCXY12 (_UL_(1) << 18) +#define PIN_PA19B_ADC0_PTCXY13 _L_(19) /**< \brief ADC0 signal: PTCXY13 on PA19 mux B */ +#define MUX_PA19B_ADC0_PTCXY13 _L_(1) +#define PINMUX_PA19B_ADC0_PTCXY13 ((PIN_PA19B_ADC0_PTCXY13 << 16) | MUX_PA19B_ADC0_PTCXY13) +#define PORT_PA19B_ADC0_PTCXY13 (_UL_(1) << 19) +#define PIN_PA20B_ADC0_PTCXY14 _L_(20) /**< \brief ADC0 signal: PTCXY14 on PA20 mux B */ +#define MUX_PA20B_ADC0_PTCXY14 _L_(1) +#define PINMUX_PA20B_ADC0_PTCXY14 ((PIN_PA20B_ADC0_PTCXY14 << 16) | MUX_PA20B_ADC0_PTCXY14) +#define PORT_PA20B_ADC0_PTCXY14 (_UL_(1) << 20) +#define PIN_PA21B_ADC0_PTCXY15 _L_(21) /**< \brief ADC0 signal: PTCXY15 on PA21 mux B */ +#define MUX_PA21B_ADC0_PTCXY15 _L_(1) +#define PINMUX_PA21B_ADC0_PTCXY15 ((PIN_PA21B_ADC0_PTCXY15 << 16) | MUX_PA21B_ADC0_PTCXY15) +#define PORT_PA21B_ADC0_PTCXY15 (_UL_(1) << 21) +#define PIN_PA22B_ADC0_PTCXY16 _L_(22) /**< \brief ADC0 signal: PTCXY16 on PA22 mux B */ +#define MUX_PA22B_ADC0_PTCXY16 _L_(1) +#define PINMUX_PA22B_ADC0_PTCXY16 ((PIN_PA22B_ADC0_PTCXY16 << 16) | MUX_PA22B_ADC0_PTCXY16) +#define PORT_PA22B_ADC0_PTCXY16 (_UL_(1) << 22) +#define PIN_PA23B_ADC0_PTCXY17 _L_(23) /**< \brief ADC0 signal: PTCXY17 on PA23 mux B */ +#define MUX_PA23B_ADC0_PTCXY17 _L_(1) +#define PINMUX_PA23B_ADC0_PTCXY17 ((PIN_PA23B_ADC0_PTCXY17 << 16) | MUX_PA23B_ADC0_PTCXY17) +#define PORT_PA23B_ADC0_PTCXY17 (_UL_(1) << 23) +#define PIN_PA27B_ADC0_PTCXY18 _L_(27) /**< \brief ADC0 signal: PTCXY18 on PA27 mux B */ +#define MUX_PA27B_ADC0_PTCXY18 _L_(1) +#define PINMUX_PA27B_ADC0_PTCXY18 ((PIN_PA27B_ADC0_PTCXY18 << 16) | MUX_PA27B_ADC0_PTCXY18) +#define PORT_PA27B_ADC0_PTCXY18 (_UL_(1) << 27) +#define PIN_PA30B_ADC0_PTCXY19 _L_(30) /**< \brief ADC0 signal: PTCXY19 on PA30 mux B */ +#define MUX_PA30B_ADC0_PTCXY19 _L_(1) +#define PINMUX_PA30B_ADC0_PTCXY19 ((PIN_PA30B_ADC0_PTCXY19 << 16) | MUX_PA30B_ADC0_PTCXY19) +#define PORT_PA30B_ADC0_PTCXY19 (_UL_(1) << 30) +#define PIN_PB02B_ADC0_PTCXY20 _L_(34) /**< \brief ADC0 signal: PTCXY20 on PB02 mux B */ +#define MUX_PB02B_ADC0_PTCXY20 _L_(1) +#define PINMUX_PB02B_ADC0_PTCXY20 ((PIN_PB02B_ADC0_PTCXY20 << 16) | MUX_PB02B_ADC0_PTCXY20) +#define PORT_PB02B_ADC0_PTCXY20 (_UL_(1) << 2) +#define PIN_PB03B_ADC0_PTCXY21 _L_(35) /**< \brief ADC0 signal: PTCXY21 on PB03 mux B */ +#define MUX_PB03B_ADC0_PTCXY21 _L_(1) +#define PINMUX_PB03B_ADC0_PTCXY21 ((PIN_PB03B_ADC0_PTCXY21 << 16) | MUX_PB03B_ADC0_PTCXY21) +#define PORT_PB03B_ADC0_PTCXY21 (_UL_(1) << 3) +#define PIN_PB04B_ADC0_PTCXY22 _L_(36) /**< \brief ADC0 signal: PTCXY22 on PB04 mux B */ +#define MUX_PB04B_ADC0_PTCXY22 _L_(1) +#define PINMUX_PB04B_ADC0_PTCXY22 ((PIN_PB04B_ADC0_PTCXY22 << 16) | MUX_PB04B_ADC0_PTCXY22) +#define PORT_PB04B_ADC0_PTCXY22 (_UL_(1) << 4) +#define PIN_PB05B_ADC0_PTCXY23 _L_(37) /**< \brief ADC0 signal: PTCXY23 on PB05 mux B */ +#define MUX_PB05B_ADC0_PTCXY23 _L_(1) +#define PINMUX_PB05B_ADC0_PTCXY23 ((PIN_PB05B_ADC0_PTCXY23 << 16) | MUX_PB05B_ADC0_PTCXY23) +#define PORT_PB05B_ADC0_PTCXY23 (_UL_(1) << 5) +#define PIN_PB06B_ADC0_PTCXY24 _L_(38) /**< \brief ADC0 signal: PTCXY24 on PB06 mux B */ +#define MUX_PB06B_ADC0_PTCXY24 _L_(1) +#define PINMUX_PB06B_ADC0_PTCXY24 ((PIN_PB06B_ADC0_PTCXY24 << 16) | MUX_PB06B_ADC0_PTCXY24) +#define PORT_PB06B_ADC0_PTCXY24 (_UL_(1) << 6) +#define PIN_PB07B_ADC0_PTCXY25 _L_(39) /**< \brief ADC0 signal: PTCXY25 on PB07 mux B */ +#define MUX_PB07B_ADC0_PTCXY25 _L_(1) +#define PINMUX_PB07B_ADC0_PTCXY25 ((PIN_PB07B_ADC0_PTCXY25 << 16) | MUX_PB07B_ADC0_PTCXY25) +#define PORT_PB07B_ADC0_PTCXY25 (_UL_(1) << 7) +#define PIN_PB12B_ADC0_PTCXY26 _L_(44) /**< \brief ADC0 signal: PTCXY26 on PB12 mux B */ +#define MUX_PB12B_ADC0_PTCXY26 _L_(1) +#define PINMUX_PB12B_ADC0_PTCXY26 ((PIN_PB12B_ADC0_PTCXY26 << 16) | MUX_PB12B_ADC0_PTCXY26) +#define PORT_PB12B_ADC0_PTCXY26 (_UL_(1) << 12) +#define PIN_PB13B_ADC0_PTCXY27 _L_(45) /**< \brief ADC0 signal: PTCXY27 on PB13 mux B */ +#define MUX_PB13B_ADC0_PTCXY27 _L_(1) +#define PINMUX_PB13B_ADC0_PTCXY27 ((PIN_PB13B_ADC0_PTCXY27 << 16) | MUX_PB13B_ADC0_PTCXY27) +#define PORT_PB13B_ADC0_PTCXY27 (_UL_(1) << 13) +#define PIN_PB14B_ADC0_PTCXY28 _L_(46) /**< \brief ADC0 signal: PTCXY28 on PB14 mux B */ +#define MUX_PB14B_ADC0_PTCXY28 _L_(1) +#define PINMUX_PB14B_ADC0_PTCXY28 ((PIN_PB14B_ADC0_PTCXY28 << 16) | MUX_PB14B_ADC0_PTCXY28) +#define PORT_PB14B_ADC0_PTCXY28 (_UL_(1) << 14) +#define PIN_PB15B_ADC0_PTCXY29 _L_(47) /**< \brief ADC0 signal: PTCXY29 on PB15 mux B */ +#define MUX_PB15B_ADC0_PTCXY29 _L_(1) +#define PINMUX_PB15B_ADC0_PTCXY29 ((PIN_PB15B_ADC0_PTCXY29 << 16) | MUX_PB15B_ADC0_PTCXY29) +#define PORT_PB15B_ADC0_PTCXY29 (_UL_(1) << 15) +#define PIN_PB00B_ADC0_PTCXY30 _L_(32) /**< \brief ADC0 signal: PTCXY30 on PB00 mux B */ +#define MUX_PB00B_ADC0_PTCXY30 _L_(1) +#define PINMUX_PB00B_ADC0_PTCXY30 ((PIN_PB00B_ADC0_PTCXY30 << 16) | MUX_PB00B_ADC0_PTCXY30) +#define PORT_PB00B_ADC0_PTCXY30 (_UL_(1) << 0) +#define PIN_PB01B_ADC0_PTCXY31 _L_(33) /**< \brief ADC0 signal: PTCXY31 on PB01 mux B */ +#define MUX_PB01B_ADC0_PTCXY31 _L_(1) +#define PINMUX_PB01B_ADC0_PTCXY31 ((PIN_PB01B_ADC0_PTCXY31 << 16) | MUX_PB01B_ADC0_PTCXY31) +#define PORT_PB01B_ADC0_PTCXY31 (_UL_(1) << 1) +/* ========== PORT definition for ADC1 peripheral ========== */ +#define PIN_PB08B_ADC1_AIN0 _L_(40) /**< \brief ADC1 signal: AIN0 on PB08 mux B */ +#define MUX_PB08B_ADC1_AIN0 _L_(1) +#define PINMUX_PB08B_ADC1_AIN0 ((PIN_PB08B_ADC1_AIN0 << 16) | MUX_PB08B_ADC1_AIN0) +#define PORT_PB08B_ADC1_AIN0 (_UL_(1) << 8) +#define PIN_PB09B_ADC1_AIN1 _L_(41) /**< \brief ADC1 signal: AIN1 on PB09 mux B */ +#define MUX_PB09B_ADC1_AIN1 _L_(1) +#define PINMUX_PB09B_ADC1_AIN1 ((PIN_PB09B_ADC1_AIN1 << 16) | MUX_PB09B_ADC1_AIN1) +#define PORT_PB09B_ADC1_AIN1 (_UL_(1) << 9) +#define PIN_PA08B_ADC1_AIN2 _L_(8) /**< \brief ADC1 signal: AIN2 on PA08 mux B */ +#define MUX_PA08B_ADC1_AIN2 _L_(1) +#define PINMUX_PA08B_ADC1_AIN2 ((PIN_PA08B_ADC1_AIN2 << 16) | MUX_PA08B_ADC1_AIN2) +#define PORT_PA08B_ADC1_AIN2 (_UL_(1) << 8) +#define PIN_PA09B_ADC1_AIN3 _L_(9) /**< \brief ADC1 signal: AIN3 on PA09 mux B */ +#define MUX_PA09B_ADC1_AIN3 _L_(1) +#define PINMUX_PA09B_ADC1_AIN3 ((PIN_PA09B_ADC1_AIN3 << 16) | MUX_PA09B_ADC1_AIN3) +#define PORT_PA09B_ADC1_AIN3 (_UL_(1) << 9) +#define PIN_PC02B_ADC1_AIN4 _L_(66) /**< \brief ADC1 signal: AIN4 on PC02 mux B */ +#define MUX_PC02B_ADC1_AIN4 _L_(1) +#define PINMUX_PC02B_ADC1_AIN4 ((PIN_PC02B_ADC1_AIN4 << 16) | MUX_PC02B_ADC1_AIN4) +#define PORT_PC02B_ADC1_AIN4 (_UL_(1) << 2) +#define PIN_PC03B_ADC1_AIN5 _L_(67) /**< \brief ADC1 signal: AIN5 on PC03 mux B */ +#define MUX_PC03B_ADC1_AIN5 _L_(1) +#define PINMUX_PC03B_ADC1_AIN5 ((PIN_PC03B_ADC1_AIN5 << 16) | MUX_PC03B_ADC1_AIN5) +#define PORT_PC03B_ADC1_AIN5 (_UL_(1) << 3) +#define PIN_PB04B_ADC1_AIN6 _L_(36) /**< \brief ADC1 signal: AIN6 on PB04 mux B */ +#define MUX_PB04B_ADC1_AIN6 _L_(1) +#define PINMUX_PB04B_ADC1_AIN6 ((PIN_PB04B_ADC1_AIN6 << 16) | MUX_PB04B_ADC1_AIN6) +#define PORT_PB04B_ADC1_AIN6 (_UL_(1) << 4) +#define PIN_PB05B_ADC1_AIN7 _L_(37) /**< \brief ADC1 signal: AIN7 on PB05 mux B */ +#define MUX_PB05B_ADC1_AIN7 _L_(1) +#define PINMUX_PB05B_ADC1_AIN7 ((PIN_PB05B_ADC1_AIN7 << 16) | MUX_PB05B_ADC1_AIN7) +#define PORT_PB05B_ADC1_AIN7 (_UL_(1) << 5) +#define PIN_PB06B_ADC1_AIN8 _L_(38) /**< \brief ADC1 signal: AIN8 on PB06 mux B */ +#define MUX_PB06B_ADC1_AIN8 _L_(1) +#define PINMUX_PB06B_ADC1_AIN8 ((PIN_PB06B_ADC1_AIN8 << 16) | MUX_PB06B_ADC1_AIN8) +#define PORT_PB06B_ADC1_AIN8 (_UL_(1) << 6) +#define PIN_PB07B_ADC1_AIN9 _L_(39) /**< \brief ADC1 signal: AIN9 on PB07 mux B */ +#define MUX_PB07B_ADC1_AIN9 _L_(1) +#define PINMUX_PB07B_ADC1_AIN9 ((PIN_PB07B_ADC1_AIN9 << 16) | MUX_PB07B_ADC1_AIN9) +#define PORT_PB07B_ADC1_AIN9 (_UL_(1) << 7) +#define PIN_PC00B_ADC1_AIN10 _L_(64) /**< \brief ADC1 signal: AIN10 on PC00 mux B */ +#define MUX_PC00B_ADC1_AIN10 _L_(1) +#define PINMUX_PC00B_ADC1_AIN10 ((PIN_PC00B_ADC1_AIN10 << 16) | MUX_PC00B_ADC1_AIN10) +#define PORT_PC00B_ADC1_AIN10 (_UL_(1) << 0) +#define PIN_PC01B_ADC1_AIN11 _L_(65) /**< \brief ADC1 signal: AIN11 on PC01 mux B */ +#define MUX_PC01B_ADC1_AIN11 _L_(1) +#define PINMUX_PC01B_ADC1_AIN11 ((PIN_PC01B_ADC1_AIN11 << 16) | MUX_PC01B_ADC1_AIN11) +#define PORT_PC01B_ADC1_AIN11 (_UL_(1) << 1) +/* ========== PORT definition for DAC peripheral ========== */ +#define PIN_PA02B_DAC_VOUT0 _L_(2) /**< \brief DAC signal: VOUT0 on PA02 mux B */ +#define MUX_PA02B_DAC_VOUT0 _L_(1) +#define PINMUX_PA02B_DAC_VOUT0 ((PIN_PA02B_DAC_VOUT0 << 16) | MUX_PA02B_DAC_VOUT0) +#define PORT_PA02B_DAC_VOUT0 (_UL_(1) << 2) +#define PIN_PA05B_DAC_VOUT1 _L_(5) /**< \brief DAC signal: VOUT1 on PA05 mux B */ +#define MUX_PA05B_DAC_VOUT1 _L_(1) +#define PINMUX_PA05B_DAC_VOUT1 ((PIN_PA05B_DAC_VOUT1 << 16) | MUX_PA05B_DAC_VOUT1) +#define PORT_PA05B_DAC_VOUT1 (_UL_(1) << 5) +/* ========== PORT definition for I2S peripheral ========== */ +#define PIN_PA09J_I2S_FS0 _L_(9) /**< \brief I2S signal: FS0 on PA09 mux J */ +#define MUX_PA09J_I2S_FS0 _L_(9) +#define PINMUX_PA09J_I2S_FS0 ((PIN_PA09J_I2S_FS0 << 16) | MUX_PA09J_I2S_FS0) +#define PORT_PA09J_I2S_FS0 (_UL_(1) << 9) +#define PIN_PA20J_I2S_FS0 _L_(20) /**< \brief I2S signal: FS0 on PA20 mux J */ +#define MUX_PA20J_I2S_FS0 _L_(9) +#define PINMUX_PA20J_I2S_FS0 ((PIN_PA20J_I2S_FS0 << 16) | MUX_PA20J_I2S_FS0) +#define PORT_PA20J_I2S_FS0 (_UL_(1) << 20) +#define PIN_PA23J_I2S_FS1 _L_(23) /**< \brief I2S signal: FS1 on PA23 mux J */ +#define MUX_PA23J_I2S_FS1 _L_(9) +#define PINMUX_PA23J_I2S_FS1 ((PIN_PA23J_I2S_FS1 << 16) | MUX_PA23J_I2S_FS1) +#define PORT_PA23J_I2S_FS1 (_UL_(1) << 23) +#define PIN_PB11J_I2S_FS1 _L_(43) /**< \brief I2S signal: FS1 on PB11 mux J */ +#define MUX_PB11J_I2S_FS1 _L_(9) +#define PINMUX_PB11J_I2S_FS1 ((PIN_PB11J_I2S_FS1 << 16) | MUX_PB11J_I2S_FS1) +#define PORT_PB11J_I2S_FS1 (_UL_(1) << 11) +#define PIN_PA08J_I2S_MCK0 _L_(8) /**< \brief I2S signal: MCK0 on PA08 mux J */ +#define MUX_PA08J_I2S_MCK0 _L_(9) +#define PINMUX_PA08J_I2S_MCK0 ((PIN_PA08J_I2S_MCK0 << 16) | MUX_PA08J_I2S_MCK0) +#define PORT_PA08J_I2S_MCK0 (_UL_(1) << 8) +#define PIN_PB17J_I2S_MCK0 _L_(49) /**< \brief I2S signal: MCK0 on PB17 mux J */ +#define MUX_PB17J_I2S_MCK0 _L_(9) +#define PINMUX_PB17J_I2S_MCK0 ((PIN_PB17J_I2S_MCK0 << 16) | MUX_PB17J_I2S_MCK0) +#define PORT_PB17J_I2S_MCK0 (_UL_(1) << 17) +#define PIN_PB13J_I2S_MCK1 _L_(45) /**< \brief I2S signal: MCK1 on PB13 mux J */ +#define MUX_PB13J_I2S_MCK1 _L_(9) +#define PINMUX_PB13J_I2S_MCK1 ((PIN_PB13J_I2S_MCK1 << 16) | MUX_PB13J_I2S_MCK1) +#define PORT_PB13J_I2S_MCK1 (_UL_(1) << 13) +#define PIN_PA10J_I2S_SCK0 _L_(10) /**< \brief I2S signal: SCK0 on PA10 mux J */ +#define MUX_PA10J_I2S_SCK0 _L_(9) +#define PINMUX_PA10J_I2S_SCK0 ((PIN_PA10J_I2S_SCK0 << 16) | MUX_PA10J_I2S_SCK0) +#define PORT_PA10J_I2S_SCK0 (_UL_(1) << 10) +#define PIN_PB16J_I2S_SCK0 _L_(48) /**< \brief I2S signal: SCK0 on PB16 mux J */ +#define MUX_PB16J_I2S_SCK0 _L_(9) +#define PINMUX_PB16J_I2S_SCK0 ((PIN_PB16J_I2S_SCK0 << 16) | MUX_PB16J_I2S_SCK0) +#define PORT_PB16J_I2S_SCK0 (_UL_(1) << 16) +#define PIN_PB12J_I2S_SCK1 _L_(44) /**< \brief I2S signal: SCK1 on PB12 mux J */ +#define MUX_PB12J_I2S_SCK1 _L_(9) +#define PINMUX_PB12J_I2S_SCK1 ((PIN_PB12J_I2S_SCK1 << 16) | MUX_PB12J_I2S_SCK1) +#define PORT_PB12J_I2S_SCK1 (_UL_(1) << 12) +#define PIN_PA22J_I2S_SDI _L_(22) /**< \brief I2S signal: SDI on PA22 mux J */ +#define MUX_PA22J_I2S_SDI _L_(9) +#define PINMUX_PA22J_I2S_SDI ((PIN_PA22J_I2S_SDI << 16) | MUX_PA22J_I2S_SDI) +#define PORT_PA22J_I2S_SDI (_UL_(1) << 22) +#define PIN_PB10J_I2S_SDI _L_(42) /**< \brief I2S signal: SDI on PB10 mux J */ +#define MUX_PB10J_I2S_SDI _L_(9) +#define PINMUX_PB10J_I2S_SDI ((PIN_PB10J_I2S_SDI << 16) | MUX_PB10J_I2S_SDI) +#define PORT_PB10J_I2S_SDI (_UL_(1) << 10) +#define PIN_PA11J_I2S_SDO _L_(11) /**< \brief I2S signal: SDO on PA11 mux J */ +#define MUX_PA11J_I2S_SDO _L_(9) +#define PINMUX_PA11J_I2S_SDO ((PIN_PA11J_I2S_SDO << 16) | MUX_PA11J_I2S_SDO) +#define PORT_PA11J_I2S_SDO (_UL_(1) << 11) +#define PIN_PA21J_I2S_SDO _L_(21) /**< \brief I2S signal: SDO on PA21 mux J */ +#define MUX_PA21J_I2S_SDO _L_(9) +#define PINMUX_PA21J_I2S_SDO ((PIN_PA21J_I2S_SDO << 16) | MUX_PA21J_I2S_SDO) +#define PORT_PA21J_I2S_SDO (_UL_(1) << 21) +/* ========== PORT definition for PCC peripheral ========== */ +#define PIN_PA14K_PCC_CLK _L_(14) /**< \brief PCC signal: CLK on PA14 mux K */ +#define MUX_PA14K_PCC_CLK _L_(10) +#define PINMUX_PA14K_PCC_CLK ((PIN_PA14K_PCC_CLK << 16) | MUX_PA14K_PCC_CLK) +#define PORT_PA14K_PCC_CLK (_UL_(1) << 14) +#define PIN_PA16K_PCC_DATA0 _L_(16) /**< \brief PCC signal: DATA0 on PA16 mux K */ +#define MUX_PA16K_PCC_DATA0 _L_(10) +#define PINMUX_PA16K_PCC_DATA0 ((PIN_PA16K_PCC_DATA0 << 16) | MUX_PA16K_PCC_DATA0) +#define PORT_PA16K_PCC_DATA0 (_UL_(1) << 16) +#define PIN_PA17K_PCC_DATA1 _L_(17) /**< \brief PCC signal: DATA1 on PA17 mux K */ +#define MUX_PA17K_PCC_DATA1 _L_(10) +#define PINMUX_PA17K_PCC_DATA1 ((PIN_PA17K_PCC_DATA1 << 16) | MUX_PA17K_PCC_DATA1) +#define PORT_PA17K_PCC_DATA1 (_UL_(1) << 17) +#define PIN_PA18K_PCC_DATA2 _L_(18) /**< \brief PCC signal: DATA2 on PA18 mux K */ +#define MUX_PA18K_PCC_DATA2 _L_(10) +#define PINMUX_PA18K_PCC_DATA2 ((PIN_PA18K_PCC_DATA2 << 16) | MUX_PA18K_PCC_DATA2) +#define PORT_PA18K_PCC_DATA2 (_UL_(1) << 18) +#define PIN_PA19K_PCC_DATA3 _L_(19) /**< \brief PCC signal: DATA3 on PA19 mux K */ +#define MUX_PA19K_PCC_DATA3 _L_(10) +#define PINMUX_PA19K_PCC_DATA3 ((PIN_PA19K_PCC_DATA3 << 16) | MUX_PA19K_PCC_DATA3) +#define PORT_PA19K_PCC_DATA3 (_UL_(1) << 19) +#define PIN_PA20K_PCC_DATA4 _L_(20) /**< \brief PCC signal: DATA4 on PA20 mux K */ +#define MUX_PA20K_PCC_DATA4 _L_(10) +#define PINMUX_PA20K_PCC_DATA4 ((PIN_PA20K_PCC_DATA4 << 16) | MUX_PA20K_PCC_DATA4) +#define PORT_PA20K_PCC_DATA4 (_UL_(1) << 20) +#define PIN_PA21K_PCC_DATA5 _L_(21) /**< \brief PCC signal: DATA5 on PA21 mux K */ +#define MUX_PA21K_PCC_DATA5 _L_(10) +#define PINMUX_PA21K_PCC_DATA5 ((PIN_PA21K_PCC_DATA5 << 16) | MUX_PA21K_PCC_DATA5) +#define PORT_PA21K_PCC_DATA5 (_UL_(1) << 21) +#define PIN_PA22K_PCC_DATA6 _L_(22) /**< \brief PCC signal: DATA6 on PA22 mux K */ +#define MUX_PA22K_PCC_DATA6 _L_(10) +#define PINMUX_PA22K_PCC_DATA6 ((PIN_PA22K_PCC_DATA6 << 16) | MUX_PA22K_PCC_DATA6) +#define PORT_PA22K_PCC_DATA6 (_UL_(1) << 22) +#define PIN_PA23K_PCC_DATA7 _L_(23) /**< \brief PCC signal: DATA7 on PA23 mux K */ +#define MUX_PA23K_PCC_DATA7 _L_(10) +#define PINMUX_PA23K_PCC_DATA7 ((PIN_PA23K_PCC_DATA7 << 16) | MUX_PA23K_PCC_DATA7) +#define PORT_PA23K_PCC_DATA7 (_UL_(1) << 23) +#define PIN_PB14K_PCC_DATA8 _L_(46) /**< \brief PCC signal: DATA8 on PB14 mux K */ +#define MUX_PB14K_PCC_DATA8 _L_(10) +#define PINMUX_PB14K_PCC_DATA8 ((PIN_PB14K_PCC_DATA8 << 16) | MUX_PB14K_PCC_DATA8) +#define PORT_PB14K_PCC_DATA8 (_UL_(1) << 14) +#define PIN_PB15K_PCC_DATA9 _L_(47) /**< \brief PCC signal: DATA9 on PB15 mux K */ +#define MUX_PB15K_PCC_DATA9 _L_(10) +#define PINMUX_PB15K_PCC_DATA9 ((PIN_PB15K_PCC_DATA9 << 16) | MUX_PB15K_PCC_DATA9) +#define PORT_PB15K_PCC_DATA9 (_UL_(1) << 15) +#define PIN_PC12K_PCC_DATA10 _L_(76) /**< \brief PCC signal: DATA10 on PC12 mux K */ +#define MUX_PC12K_PCC_DATA10 _L_(10) +#define PINMUX_PC12K_PCC_DATA10 ((PIN_PC12K_PCC_DATA10 << 16) | MUX_PC12K_PCC_DATA10) +#define PORT_PC12K_PCC_DATA10 (_UL_(1) << 12) +#define PIN_PC13K_PCC_DATA11 _L_(77) /**< \brief PCC signal: DATA11 on PC13 mux K */ +#define MUX_PC13K_PCC_DATA11 _L_(10) +#define PINMUX_PC13K_PCC_DATA11 ((PIN_PC13K_PCC_DATA11 << 16) | MUX_PC13K_PCC_DATA11) +#define PORT_PC13K_PCC_DATA11 (_UL_(1) << 13) +#define PIN_PC14K_PCC_DATA12 _L_(78) /**< \brief PCC signal: DATA12 on PC14 mux K */ +#define MUX_PC14K_PCC_DATA12 _L_(10) +#define PINMUX_PC14K_PCC_DATA12 ((PIN_PC14K_PCC_DATA12 << 16) | MUX_PC14K_PCC_DATA12) +#define PORT_PC14K_PCC_DATA12 (_UL_(1) << 14) +#define PIN_PC15K_PCC_DATA13 _L_(79) /**< \brief PCC signal: DATA13 on PC15 mux K */ +#define MUX_PC15K_PCC_DATA13 _L_(10) +#define PINMUX_PC15K_PCC_DATA13 ((PIN_PC15K_PCC_DATA13 << 16) | MUX_PC15K_PCC_DATA13) +#define PORT_PC15K_PCC_DATA13 (_UL_(1) << 15) +#define PIN_PA12K_PCC_DEN1 _L_(12) /**< \brief PCC signal: DEN1 on PA12 mux K */ +#define MUX_PA12K_PCC_DEN1 _L_(10) +#define PINMUX_PA12K_PCC_DEN1 ((PIN_PA12K_PCC_DEN1 << 16) | MUX_PA12K_PCC_DEN1) +#define PORT_PA12K_PCC_DEN1 (_UL_(1) << 12) +#define PIN_PA13K_PCC_DEN2 _L_(13) /**< \brief PCC signal: DEN2 on PA13 mux K */ +#define MUX_PA13K_PCC_DEN2 _L_(10) +#define PINMUX_PA13K_PCC_DEN2 ((PIN_PA13K_PCC_DEN2 << 16) | MUX_PA13K_PCC_DEN2) +#define PORT_PA13K_PCC_DEN2 (_UL_(1) << 13) +/* ========== PORT definition for SDHC0 peripheral ========== */ +#define PIN_PA06I_SDHC0_SDCD _L_(6) /**< \brief SDHC0 signal: SDCD on PA06 mux I */ +#define MUX_PA06I_SDHC0_SDCD _L_(8) +#define PINMUX_PA06I_SDHC0_SDCD ((PIN_PA06I_SDHC0_SDCD << 16) | MUX_PA06I_SDHC0_SDCD) +#define PORT_PA06I_SDHC0_SDCD (_UL_(1) << 6) +#define PIN_PA12I_SDHC0_SDCD _L_(12) /**< \brief SDHC0 signal: SDCD on PA12 mux I */ +#define MUX_PA12I_SDHC0_SDCD _L_(8) +#define PINMUX_PA12I_SDHC0_SDCD ((PIN_PA12I_SDHC0_SDCD << 16) | MUX_PA12I_SDHC0_SDCD) +#define PORT_PA12I_SDHC0_SDCD (_UL_(1) << 12) +#define PIN_PB12I_SDHC0_SDCD _L_(44) /**< \brief SDHC0 signal: SDCD on PB12 mux I */ +#define MUX_PB12I_SDHC0_SDCD _L_(8) +#define PINMUX_PB12I_SDHC0_SDCD ((PIN_PB12I_SDHC0_SDCD << 16) | MUX_PB12I_SDHC0_SDCD) +#define PORT_PB12I_SDHC0_SDCD (_UL_(1) << 12) +#define PIN_PC06I_SDHC0_SDCD _L_(70) /**< \brief SDHC0 signal: SDCD on PC06 mux I */ +#define MUX_PC06I_SDHC0_SDCD _L_(8) +#define PINMUX_PC06I_SDHC0_SDCD ((PIN_PC06I_SDHC0_SDCD << 16) | MUX_PC06I_SDHC0_SDCD) +#define PORT_PC06I_SDHC0_SDCD (_UL_(1) << 6) +#define PIN_PB11I_SDHC0_SDCK _L_(43) /**< \brief SDHC0 signal: SDCK on PB11 mux I */ +#define MUX_PB11I_SDHC0_SDCK _L_(8) +#define PINMUX_PB11I_SDHC0_SDCK ((PIN_PB11I_SDHC0_SDCK << 16) | MUX_PB11I_SDHC0_SDCK) +#define PORT_PB11I_SDHC0_SDCK (_UL_(1) << 11) +#define PIN_PA08I_SDHC0_SDCMD _L_(8) /**< \brief SDHC0 signal: SDCMD on PA08 mux I */ +#define MUX_PA08I_SDHC0_SDCMD _L_(8) +#define PINMUX_PA08I_SDHC0_SDCMD ((PIN_PA08I_SDHC0_SDCMD << 16) | MUX_PA08I_SDHC0_SDCMD) +#define PORT_PA08I_SDHC0_SDCMD (_UL_(1) << 8) +#define PIN_PA09I_SDHC0_SDDAT0 _L_(9) /**< \brief SDHC0 signal: SDDAT0 on PA09 mux I */ +#define MUX_PA09I_SDHC0_SDDAT0 _L_(8) +#define PINMUX_PA09I_SDHC0_SDDAT0 ((PIN_PA09I_SDHC0_SDDAT0 << 16) | MUX_PA09I_SDHC0_SDDAT0) +#define PORT_PA09I_SDHC0_SDDAT0 (_UL_(1) << 9) +#define PIN_PA10I_SDHC0_SDDAT1 _L_(10) /**< \brief SDHC0 signal: SDDAT1 on PA10 mux I */ +#define MUX_PA10I_SDHC0_SDDAT1 _L_(8) +#define PINMUX_PA10I_SDHC0_SDDAT1 ((PIN_PA10I_SDHC0_SDDAT1 << 16) | MUX_PA10I_SDHC0_SDDAT1) +#define PORT_PA10I_SDHC0_SDDAT1 (_UL_(1) << 10) +#define PIN_PA11I_SDHC0_SDDAT2 _L_(11) /**< \brief SDHC0 signal: SDDAT2 on PA11 mux I */ +#define MUX_PA11I_SDHC0_SDDAT2 _L_(8) +#define PINMUX_PA11I_SDHC0_SDDAT2 ((PIN_PA11I_SDHC0_SDDAT2 << 16) | MUX_PA11I_SDHC0_SDDAT2) +#define PORT_PA11I_SDHC0_SDDAT2 (_UL_(1) << 11) +#define PIN_PB10I_SDHC0_SDDAT3 _L_(42) /**< \brief SDHC0 signal: SDDAT3 on PB10 mux I */ +#define MUX_PB10I_SDHC0_SDDAT3 _L_(8) +#define PINMUX_PB10I_SDHC0_SDDAT3 ((PIN_PB10I_SDHC0_SDDAT3 << 16) | MUX_PB10I_SDHC0_SDDAT3) +#define PORT_PB10I_SDHC0_SDDAT3 (_UL_(1) << 10) +#define PIN_PA07I_SDHC0_SDWP _L_(7) /**< \brief SDHC0 signal: SDWP on PA07 mux I */ +#define MUX_PA07I_SDHC0_SDWP _L_(8) +#define PINMUX_PA07I_SDHC0_SDWP ((PIN_PA07I_SDHC0_SDWP << 16) | MUX_PA07I_SDHC0_SDWP) +#define PORT_PA07I_SDHC0_SDWP (_UL_(1) << 7) +#define PIN_PA13I_SDHC0_SDWP _L_(13) /**< \brief SDHC0 signal: SDWP on PA13 mux I */ +#define MUX_PA13I_SDHC0_SDWP _L_(8) +#define PINMUX_PA13I_SDHC0_SDWP ((PIN_PA13I_SDHC0_SDWP << 16) | MUX_PA13I_SDHC0_SDWP) +#define PORT_PA13I_SDHC0_SDWP (_UL_(1) << 13) +#define PIN_PB13I_SDHC0_SDWP _L_(45) /**< \brief SDHC0 signal: SDWP on PB13 mux I */ +#define MUX_PB13I_SDHC0_SDWP _L_(8) +#define PINMUX_PB13I_SDHC0_SDWP ((PIN_PB13I_SDHC0_SDWP << 16) | MUX_PB13I_SDHC0_SDWP) +#define PORT_PB13I_SDHC0_SDWP (_UL_(1) << 13) +#define PIN_PC07I_SDHC0_SDWP _L_(71) /**< \brief SDHC0 signal: SDWP on PC07 mux I */ +#define MUX_PC07I_SDHC0_SDWP _L_(8) +#define PINMUX_PC07I_SDHC0_SDWP ((PIN_PC07I_SDHC0_SDWP << 16) | MUX_PC07I_SDHC0_SDWP) +#define PORT_PC07I_SDHC0_SDWP (_UL_(1) << 7) +/* ========== PORT definition for SDHC1 peripheral ========== */ +#define PIN_PB16I_SDHC1_SDCD _L_(48) /**< \brief SDHC1 signal: SDCD on PB16 mux I */ +#define MUX_PB16I_SDHC1_SDCD _L_(8) +#define PINMUX_PB16I_SDHC1_SDCD ((PIN_PB16I_SDHC1_SDCD << 16) | MUX_PB16I_SDHC1_SDCD) +#define PORT_PB16I_SDHC1_SDCD (_UL_(1) << 16) +#define PIN_PC20I_SDHC1_SDCD _L_(84) /**< \brief SDHC1 signal: SDCD on PC20 mux I */ +#define MUX_PC20I_SDHC1_SDCD _L_(8) +#define PINMUX_PC20I_SDHC1_SDCD ((PIN_PC20I_SDHC1_SDCD << 16) | MUX_PC20I_SDHC1_SDCD) +#define PORT_PC20I_SDHC1_SDCD (_UL_(1) << 20) +#define PIN_PA21I_SDHC1_SDCK _L_(21) /**< \brief SDHC1 signal: SDCK on PA21 mux I */ +#define MUX_PA21I_SDHC1_SDCK _L_(8) +#define PINMUX_PA21I_SDHC1_SDCK ((PIN_PA21I_SDHC1_SDCK << 16) | MUX_PA21I_SDHC1_SDCK) +#define PORT_PA21I_SDHC1_SDCK (_UL_(1) << 21) +#define PIN_PA20I_SDHC1_SDCMD _L_(20) /**< \brief SDHC1 signal: SDCMD on PA20 mux I */ +#define MUX_PA20I_SDHC1_SDCMD _L_(8) +#define PINMUX_PA20I_SDHC1_SDCMD ((PIN_PA20I_SDHC1_SDCMD << 16) | MUX_PA20I_SDHC1_SDCMD) +#define PORT_PA20I_SDHC1_SDCMD (_UL_(1) << 20) +#define PIN_PB18I_SDHC1_SDDAT0 _L_(50) /**< \brief SDHC1 signal: SDDAT0 on PB18 mux I */ +#define MUX_PB18I_SDHC1_SDDAT0 _L_(8) +#define PINMUX_PB18I_SDHC1_SDDAT0 ((PIN_PB18I_SDHC1_SDDAT0 << 16) | MUX_PB18I_SDHC1_SDDAT0) +#define PORT_PB18I_SDHC1_SDDAT0 (_UL_(1) << 18) +#define PIN_PB19I_SDHC1_SDDAT1 _L_(51) /**< \brief SDHC1 signal: SDDAT1 on PB19 mux I */ +#define MUX_PB19I_SDHC1_SDDAT1 _L_(8) +#define PINMUX_PB19I_SDHC1_SDDAT1 ((PIN_PB19I_SDHC1_SDDAT1 << 16) | MUX_PB19I_SDHC1_SDDAT1) +#define PORT_PB19I_SDHC1_SDDAT1 (_UL_(1) << 19) +#define PIN_PB20I_SDHC1_SDDAT2 _L_(52) /**< \brief SDHC1 signal: SDDAT2 on PB20 mux I */ +#define MUX_PB20I_SDHC1_SDDAT2 _L_(8) +#define PINMUX_PB20I_SDHC1_SDDAT2 ((PIN_PB20I_SDHC1_SDDAT2 << 16) | MUX_PB20I_SDHC1_SDDAT2) +#define PORT_PB20I_SDHC1_SDDAT2 (_UL_(1) << 20) +#define PIN_PB21I_SDHC1_SDDAT3 _L_(53) /**< \brief SDHC1 signal: SDDAT3 on PB21 mux I */ +#define MUX_PB21I_SDHC1_SDDAT3 _L_(8) +#define PINMUX_PB21I_SDHC1_SDDAT3 ((PIN_PB21I_SDHC1_SDDAT3 << 16) | MUX_PB21I_SDHC1_SDDAT3) +#define PORT_PB21I_SDHC1_SDDAT3 (_UL_(1) << 21) +#define PIN_PB17I_SDHC1_SDWP _L_(49) /**< \brief SDHC1 signal: SDWP on PB17 mux I */ +#define MUX_PB17I_SDHC1_SDWP _L_(8) +#define PINMUX_PB17I_SDHC1_SDWP ((PIN_PB17I_SDHC1_SDWP << 16) | MUX_PB17I_SDHC1_SDWP) +#define PORT_PB17I_SDHC1_SDWP (_UL_(1) << 17) +#define PIN_PC21I_SDHC1_SDWP _L_(85) /**< \brief SDHC1 signal: SDWP on PC21 mux I */ +#define MUX_PC21I_SDHC1_SDWP _L_(8) +#define PINMUX_PC21I_SDHC1_SDWP ((PIN_PC21I_SDHC1_SDWP << 16) | MUX_PC21I_SDHC1_SDWP) +#define PORT_PC21I_SDHC1_SDWP (_UL_(1) << 21) + +#endif /* _SAME54N20A_PIO_ */ diff --git a/arch/arm/SAME54/SAME54A/mcu/inc/pio/same54p19a.h b/arch/arm/SAME54/SAME54A/mcu/inc/pio/same54p19a.h index 51840c49..93afbcc8 100644 --- a/arch/arm/SAME54/SAME54A/mcu/inc/pio/same54p19a.h +++ b/arch/arm/SAME54/SAME54A/mcu/inc/pio/same54p19a.h @@ -1,3628 +1,3010 @@ -/** - * \brief Peripheral I/O description for SAME54P19A - * - * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries. - * - * Subject to your compliance with these terms, you may use Microchip software and any derivatives - * exclusively with Microchip products. It is your responsibility to comply with third party license - * terms applicable to your use of third party software (including open source software) that may - * accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, - * APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND - * FITNESS FOR A PARTICULAR PURPOSE. - * - * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF - * MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT - * EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - */ - -/* file generated from device description version 2020-03-12T17:27:01Z */ -#ifndef _SAME54P19A_GPIO_H_ -#define _SAME54P19A_GPIO_H_ - -/* ========== Peripheral I/O pin numbers ========== */ -#define PIN_PA00 ( 0 ) /**< Pin Number for PA00 */ -#define PIN_PA01 ( 1 ) /**< Pin Number for PA01 */ -#define PIN_PA02 ( 2 ) /**< Pin Number for PA02 */ -#define PIN_PA03 ( 3 ) /**< Pin Number for PA03 */ -#define PIN_PA04 ( 4 ) /**< Pin Number for PA04 */ -#define PIN_PA05 ( 5 ) /**< Pin Number for PA05 */ -#define PIN_PA06 ( 6 ) /**< Pin Number for PA06 */ -#define PIN_PA07 ( 7 ) /**< Pin Number for PA07 */ -#define PIN_PA08 ( 8 ) /**< Pin Number for PA08 */ -#define PIN_PA09 ( 9 ) /**< Pin Number for PA09 */ -#define PIN_PA10 ( 10 ) /**< Pin Number for PA10 */ -#define PIN_PA11 ( 11 ) /**< Pin Number for PA11 */ -#define PIN_PA12 ( 12 ) /**< Pin Number for PA12 */ -#define PIN_PA13 ( 13 ) /**< Pin Number for PA13 */ -#define PIN_PA14 ( 14 ) /**< Pin Number for PA14 */ -#define PIN_PA15 ( 15 ) /**< Pin Number for PA15 */ -#define PIN_PA16 ( 16 ) /**< Pin Number for PA16 */ -#define PIN_PA17 ( 17 ) /**< Pin Number for PA17 */ -#define PIN_PA18 ( 18 ) /**< Pin Number for PA18 */ -#define PIN_PA19 ( 19 ) /**< Pin Number for PA19 */ -#define PIN_PA20 ( 20 ) /**< Pin Number for PA20 */ -#define PIN_PA21 ( 21 ) /**< Pin Number for PA21 */ -#define PIN_PA22 ( 22 ) /**< Pin Number for PA22 */ -#define PIN_PA23 ( 23 ) /**< Pin Number for PA23 */ -#define PIN_PA24 ( 24 ) /**< Pin Number for PA24 */ -#define PIN_PA25 ( 25 ) /**< Pin Number for PA25 */ -#define PIN_PA27 ( 27 ) /**< Pin Number for PA27 */ -#define PIN_PA30 ( 30 ) /**< Pin Number for PA30 */ -#define PIN_PA31 ( 31 ) /**< Pin Number for PA31 */ -#define PIN_PB00 ( 32 ) /**< Pin Number for PB00 */ -#define PIN_PB01 ( 33 ) /**< Pin Number for PB01 */ -#define PIN_PB02 ( 34 ) /**< Pin Number for PB02 */ -#define PIN_PB03 ( 35 ) /**< Pin Number for PB03 */ -#define PIN_PB04 ( 36 ) /**< Pin Number for PB04 */ -#define PIN_PB05 ( 37 ) /**< Pin Number for PB05 */ -#define PIN_PB06 ( 38 ) /**< Pin Number for PB06 */ -#define PIN_PB07 ( 39 ) /**< Pin Number for PB07 */ -#define PIN_PB08 ( 40 ) /**< Pin Number for PB08 */ -#define PIN_PB09 ( 41 ) /**< Pin Number for PB09 */ -#define PIN_PB10 ( 42 ) /**< Pin Number for PB10 */ -#define PIN_PB11 ( 43 ) /**< Pin Number for PB11 */ -#define PIN_PB12 ( 44 ) /**< Pin Number for PB12 */ -#define PIN_PB13 ( 45 ) /**< Pin Number for PB13 */ -#define PIN_PB14 ( 46 ) /**< Pin Number for PB14 */ -#define PIN_PB15 ( 47 ) /**< Pin Number for PB15 */ -#define PIN_PB16 ( 48 ) /**< Pin Number for PB16 */ -#define PIN_PB17 ( 49 ) /**< Pin Number for PB17 */ -#define PIN_PB18 ( 50 ) /**< Pin Number for PB18 */ -#define PIN_PB19 ( 51 ) /**< Pin Number for PB19 */ -#define PIN_PB20 ( 52 ) /**< Pin Number for PB20 */ -#define PIN_PB21 ( 53 ) /**< Pin Number for PB21 */ -#define PIN_PB22 ( 54 ) /**< Pin Number for PB22 */ -#define PIN_PB23 ( 55 ) /**< Pin Number for PB23 */ -#define PIN_PB24 ( 56 ) /**< Pin Number for PB24 */ -#define PIN_PB25 ( 57 ) /**< Pin Number for PB25 */ -#define PIN_PB26 ( 58 ) /**< Pin Number for PB26 */ -#define PIN_PB27 ( 59 ) /**< Pin Number for PB27 */ -#define PIN_PB28 ( 60 ) /**< Pin Number for PB28 */ -#define PIN_PB29 ( 61 ) /**< Pin Number for PB29 */ -#define PIN_PB30 ( 62 ) /**< Pin Number for PB30 */ -#define PIN_PB31 ( 63 ) /**< Pin Number for PB31 */ -#define PIN_PC00 ( 64 ) /**< Pin Number for PC00 */ -#define PIN_PC01 ( 65 ) /**< Pin Number for PC01 */ -#define PIN_PC02 ( 66 ) /**< Pin Number for PC02 */ -#define PIN_PC03 ( 67 ) /**< Pin Number for PC03 */ -#define PIN_PC04 ( 68 ) /**< Pin Number for PC04 */ -#define PIN_PC05 ( 69 ) /**< Pin Number for PC05 */ -#define PIN_PC06 ( 70 ) /**< Pin Number for PC06 */ -#define PIN_PC07 ( 71 ) /**< Pin Number for PC07 */ -#define PIN_PC10 ( 74 ) /**< Pin Number for PC10 */ -#define PIN_PC11 ( 75 ) /**< Pin Number for PC11 */ -#define PIN_PC12 ( 76 ) /**< Pin Number for PC12 */ -#define PIN_PC13 ( 77 ) /**< Pin Number for PC13 */ -#define PIN_PC14 ( 78 ) /**< Pin Number for PC14 */ -#define PIN_PC15 ( 79 ) /**< Pin Number for PC15 */ -#define PIN_PC16 ( 80 ) /**< Pin Number for PC16 */ -#define PIN_PC17 ( 81 ) /**< Pin Number for PC17 */ -#define PIN_PC18 ( 82 ) /**< Pin Number for PC18 */ -#define PIN_PC19 ( 83 ) /**< Pin Number for PC19 */ -#define PIN_PC20 ( 84 ) /**< Pin Number for PC20 */ -#define PIN_PC21 ( 85 ) /**< Pin Number for PC21 */ -#define PIN_PC22 ( 86 ) /**< Pin Number for PC22 */ -#define PIN_PC23 ( 87 ) /**< Pin Number for PC23 */ -#define PIN_PC24 ( 88 ) /**< Pin Number for PC24 */ -#define PIN_PC25 ( 89 ) /**< Pin Number for PC25 */ -#define PIN_PC26 ( 90 ) /**< Pin Number for PC26 */ -#define PIN_PC27 ( 91 ) /**< Pin Number for PC27 */ -#define PIN_PC28 ( 92 ) /**< Pin Number for PC28 */ -#define PIN_PC30 ( 94 ) /**< Pin Number for PC30 */ -#define PIN_PC31 ( 95 ) /**< Pin Number for PC31 */ -#define PIN_PD00 ( 96 ) /**< Pin Number for PD00 */ -#define PIN_PD01 ( 97 ) /**< Pin Number for PD01 */ -#define PIN_PD08 (104 ) /**< Pin Number for PD08 */ -#define PIN_PD09 (105 ) /**< Pin Number for PD09 */ -#define PIN_PD10 (106 ) /**< Pin Number for PD10 */ -#define PIN_PD11 (107 ) /**< Pin Number for PD11 */ -#define PIN_PD12 (108 ) /**< Pin Number for PD12 */ -#define PIN_PD20 (116 ) /**< Pin Number for PD20 */ -#define PIN_PD21 (117 ) /**< Pin Number for PD21 */ - -/* ========== Peripheral I/O masks ========== */ -#define PORT_PA00 (_U_(1) << 0) /**< PORT mask for PA00 */ -#define PORT_PA01 (_U_(1) << 1) /**< PORT mask for PA01 */ -#define PORT_PA02 (_U_(1) << 2) /**< PORT mask for PA02 */ -#define PORT_PA03 (_U_(1) << 3) /**< PORT mask for PA03 */ -#define PORT_PA04 (_U_(1) << 4) /**< PORT mask for PA04 */ -#define PORT_PA05 (_U_(1) << 5) /**< PORT mask for PA05 */ -#define PORT_PA06 (_U_(1) << 6) /**< PORT mask for PA06 */ -#define PORT_PA07 (_U_(1) << 7) /**< PORT mask for PA07 */ -#define PORT_PA08 (_U_(1) << 8) /**< PORT mask for PA08 */ -#define PORT_PA09 (_U_(1) << 9) /**< PORT mask for PA09 */ -#define PORT_PA10 (_U_(1) << 10) /**< PORT mask for PA10 */ -#define PORT_PA11 (_U_(1) << 11) /**< PORT mask for PA11 */ -#define PORT_PA12 (_U_(1) << 12) /**< PORT mask for PA12 */ -#define PORT_PA13 (_U_(1) << 13) /**< PORT mask for PA13 */ -#define PORT_PA14 (_U_(1) << 14) /**< PORT mask for PA14 */ -#define PORT_PA15 (_U_(1) << 15) /**< PORT mask for PA15 */ -#define PORT_PA16 (_U_(1) << 16) /**< PORT mask for PA16 */ -#define PORT_PA17 (_U_(1) << 17) /**< PORT mask for PA17 */ -#define PORT_PA18 (_U_(1) << 18) /**< PORT mask for PA18 */ -#define PORT_PA19 (_U_(1) << 19) /**< PORT mask for PA19 */ -#define PORT_PA20 (_U_(1) << 20) /**< PORT mask for PA20 */ -#define PORT_PA21 (_U_(1) << 21) /**< PORT mask for PA21 */ -#define PORT_PA22 (_U_(1) << 22) /**< PORT mask for PA22 */ -#define PORT_PA23 (_U_(1) << 23) /**< PORT mask for PA23 */ -#define PORT_PA24 (_U_(1) << 24) /**< PORT mask for PA24 */ -#define PORT_PA25 (_U_(1) << 25) /**< PORT mask for PA25 */ -#define PORT_PA27 (_U_(1) << 27) /**< PORT mask for PA27 */ -#define PORT_PA30 (_U_(1) << 30) /**< PORT mask for PA30 */ -#define PORT_PA31 (_U_(1) << 31) /**< PORT mask for PA31 */ -#define PORT_PB00 (_U_(1) << 0) /**< PORT mask for PB00 */ -#define PORT_PB01 (_U_(1) << 1) /**< PORT mask for PB01 */ -#define PORT_PB02 (_U_(1) << 2) /**< PORT mask for PB02 */ -#define PORT_PB03 (_U_(1) << 3) /**< PORT mask for PB03 */ -#define PORT_PB04 (_U_(1) << 4) /**< PORT mask for PB04 */ -#define PORT_PB05 (_U_(1) << 5) /**< PORT mask for PB05 */ -#define PORT_PB06 (_U_(1) << 6) /**< PORT mask for PB06 */ -#define PORT_PB07 (_U_(1) << 7) /**< PORT mask for PB07 */ -#define PORT_PB08 (_U_(1) << 8) /**< PORT mask for PB08 */ -#define PORT_PB09 (_U_(1) << 9) /**< PORT mask for PB09 */ -#define PORT_PB10 (_U_(1) << 10) /**< PORT mask for PB10 */ -#define PORT_PB11 (_U_(1) << 11) /**< PORT mask for PB11 */ -#define PORT_PB12 (_U_(1) << 12) /**< PORT mask for PB12 */ -#define PORT_PB13 (_U_(1) << 13) /**< PORT mask for PB13 */ -#define PORT_PB14 (_U_(1) << 14) /**< PORT mask for PB14 */ -#define PORT_PB15 (_U_(1) << 15) /**< PORT mask for PB15 */ -#define PORT_PB16 (_U_(1) << 16) /**< PORT mask for PB16 */ -#define PORT_PB17 (_U_(1) << 17) /**< PORT mask for PB17 */ -#define PORT_PB18 (_U_(1) << 18) /**< PORT mask for PB18 */ -#define PORT_PB19 (_U_(1) << 19) /**< PORT mask for PB19 */ -#define PORT_PB20 (_U_(1) << 20) /**< PORT mask for PB20 */ -#define PORT_PB21 (_U_(1) << 21) /**< PORT mask for PB21 */ -#define PORT_PB22 (_U_(1) << 22) /**< PORT mask for PB22 */ -#define PORT_PB23 (_U_(1) << 23) /**< PORT mask for PB23 */ -#define PORT_PB24 (_U_(1) << 24) /**< PORT mask for PB24 */ -#define PORT_PB25 (_U_(1) << 25) /**< PORT mask for PB25 */ -#define PORT_PB26 (_U_(1) << 26) /**< PORT mask for PB26 */ -#define PORT_PB27 (_U_(1) << 27) /**< PORT mask for PB27 */ -#define PORT_PB28 (_U_(1) << 28) /**< PORT mask for PB28 */ -#define PORT_PB29 (_U_(1) << 29) /**< PORT mask for PB29 */ -#define PORT_PB30 (_U_(1) << 30) /**< PORT mask for PB30 */ -#define PORT_PB31 (_U_(1) << 31) /**< PORT mask for PB31 */ -#define PORT_PC00 (_U_(1) << 0) /**< PORT mask for PC00 */ -#define PORT_PC01 (_U_(1) << 1) /**< PORT mask for PC01 */ -#define PORT_PC02 (_U_(1) << 2) /**< PORT mask for PC02 */ -#define PORT_PC03 (_U_(1) << 3) /**< PORT mask for PC03 */ -#define PORT_PC04 (_U_(1) << 4) /**< PORT mask for PC04 */ -#define PORT_PC05 (_U_(1) << 5) /**< PORT mask for PC05 */ -#define PORT_PC06 (_U_(1) << 6) /**< PORT mask for PC06 */ -#define PORT_PC07 (_U_(1) << 7) /**< PORT mask for PC07 */ -#define PORT_PC10 (_U_(1) << 10) /**< PORT mask for PC10 */ -#define PORT_PC11 (_U_(1) << 11) /**< PORT mask for PC11 */ -#define PORT_PC12 (_U_(1) << 12) /**< PORT mask for PC12 */ -#define PORT_PC13 (_U_(1) << 13) /**< PORT mask for PC13 */ -#define PORT_PC14 (_U_(1) << 14) /**< PORT mask for PC14 */ -#define PORT_PC15 (_U_(1) << 15) /**< PORT mask for PC15 */ -#define PORT_PC16 (_U_(1) << 16) /**< PORT mask for PC16 */ -#define PORT_PC17 (_U_(1) << 17) /**< PORT mask for PC17 */ -#define PORT_PC18 (_U_(1) << 18) /**< PORT mask for PC18 */ -#define PORT_PC19 (_U_(1) << 19) /**< PORT mask for PC19 */ -#define PORT_PC20 (_U_(1) << 20) /**< PORT mask for PC20 */ -#define PORT_PC21 (_U_(1) << 21) /**< PORT mask for PC21 */ -#define PORT_PC22 (_U_(1) << 22) /**< PORT mask for PC22 */ -#define PORT_PC23 (_U_(1) << 23) /**< PORT mask for PC23 */ -#define PORT_PC24 (_U_(1) << 24) /**< PORT mask for PC24 */ -#define PORT_PC25 (_U_(1) << 25) /**< PORT mask for PC25 */ -#define PORT_PC26 (_U_(1) << 26) /**< PORT mask for PC26 */ -#define PORT_PC27 (_U_(1) << 27) /**< PORT mask for PC27 */ -#define PORT_PC28 (_U_(1) << 28) /**< PORT mask for PC28 */ -#define PORT_PC30 (_U_(1) << 30) /**< PORT mask for PC30 */ -#define PORT_PC31 (_U_(1) << 31) /**< PORT mask for PC31 */ -#define PORT_PD00 (_U_(1) << 0) /**< PORT mask for PD00 */ -#define PORT_PD01 (_U_(1) << 1) /**< PORT mask for PD01 */ -#define PORT_PD08 (_U_(1) << 8) /**< PORT mask for PD08 */ -#define PORT_PD09 (_U_(1) << 9) /**< PORT mask for PD09 */ -#define PORT_PD10 (_U_(1) << 10) /**< PORT mask for PD10 */ -#define PORT_PD11 (_U_(1) << 11) /**< PORT mask for PD11 */ -#define PORT_PD12 (_U_(1) << 12) /**< PORT mask for PD12 */ -#define PORT_PD20 (_U_(1) << 20) /**< PORT mask for PD20 */ -#define PORT_PD21 (_U_(1) << 21) /**< PORT mask for PD21 */ - -/* ========== PORT definition for AC peripheral ========== */ -#define PIN_PA04B_AC_AIN0 (4L) -#define MUX_PA04B_AC_AIN0 (1L) -#define PINMUX_PA04B_AC_AIN0 ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0) -#define PORT_PA04B_AC_AIN0 ((1UL) << 4) - -#define PIN_PA05B_AC_AIN1 (5L) -#define MUX_PA05B_AC_AIN1 (1L) -#define PINMUX_PA05B_AC_AIN1 ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1) -#define PORT_PA05B_AC_AIN1 ((1UL) << 5) - -#define PIN_PA06B_AC_AIN2 (6L) -#define MUX_PA06B_AC_AIN2 (1L) -#define PINMUX_PA06B_AC_AIN2 ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2) -#define PORT_PA06B_AC_AIN2 ((1UL) << 6) - -#define PIN_PA07B_AC_AIN3 (7L) -#define MUX_PA07B_AC_AIN3 (1L) -#define PINMUX_PA07B_AC_AIN3 ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3) -#define PORT_PA07B_AC_AIN3 ((1UL) << 7) - -#define PIN_PA12M_AC_CMP0 (12L) -#define MUX_PA12M_AC_CMP0 (12L) -#define PINMUX_PA12M_AC_CMP0 ((PIN_PA12M_AC_CMP0 << 16) | MUX_PA12M_AC_CMP0) -#define PORT_PA12M_AC_CMP0 ((1UL) << 12) - -#define PIN_PA18M_AC_CMP0 (18L) -#define MUX_PA18M_AC_CMP0 (12L) -#define PINMUX_PA18M_AC_CMP0 ((PIN_PA18M_AC_CMP0 << 16) | MUX_PA18M_AC_CMP0) -#define PORT_PA18M_AC_CMP0 ((1UL) << 18) - -#define PIN_PB24M_AC_CMP0 (56L) -#define MUX_PB24M_AC_CMP0 (12L) -#define PINMUX_PB24M_AC_CMP0 ((PIN_PB24M_AC_CMP0 << 16) | MUX_PB24M_AC_CMP0) -#define PORT_PB24M_AC_CMP0 ((1UL) << 24) - -#define PIN_PA13M_AC_CMP1 (13L) -#define MUX_PA13M_AC_CMP1 (12L) -#define PINMUX_PA13M_AC_CMP1 ((PIN_PA13M_AC_CMP1 << 16) | MUX_PA13M_AC_CMP1) -#define PORT_PA13M_AC_CMP1 ((1UL) << 13) - -#define PIN_PA19M_AC_CMP1 (19L) -#define MUX_PA19M_AC_CMP1 (12L) -#define PINMUX_PA19M_AC_CMP1 ((PIN_PA19M_AC_CMP1 << 16) | MUX_PA19M_AC_CMP1) -#define PORT_PA19M_AC_CMP1 ((1UL) << 19) - -#define PIN_PB25M_AC_CMP1 (57L) -#define MUX_PB25M_AC_CMP1 (12L) -#define PINMUX_PB25M_AC_CMP1 ((PIN_PB25M_AC_CMP1 << 16) | MUX_PB25M_AC_CMP1) -#define PORT_PB25M_AC_CMP1 ((1UL) << 25) - -/* ========== PORT definition for ADC0 peripheral ========== */ -#define PIN_PA02B_ADC0_AIN0 (2L) -#define MUX_PA02B_ADC0_AIN0 (1L) -#define PINMUX_PA02B_ADC0_AIN0 ((PIN_PA02B_ADC0_AIN0 << 16) | MUX_PA02B_ADC0_AIN0) -#define PORT_PA02B_ADC0_AIN0 ((1UL) << 2) - -#define PIN_PA03B_ADC0_AIN1 (3L) -#define MUX_PA03B_ADC0_AIN1 (1L) -#define PINMUX_PA03B_ADC0_AIN1 ((PIN_PA03B_ADC0_AIN1 << 16) | MUX_PA03B_ADC0_AIN1) -#define PORT_PA03B_ADC0_AIN1 ((1UL) << 3) - -#define PIN_PB08B_ADC0_AIN2 (40L) -#define MUX_PB08B_ADC0_AIN2 (1L) -#define PINMUX_PB08B_ADC0_AIN2 ((PIN_PB08B_ADC0_AIN2 << 16) | MUX_PB08B_ADC0_AIN2) -#define PORT_PB08B_ADC0_AIN2 ((1UL) << 8) - -#define PIN_PB09B_ADC0_AIN3 (41L) -#define MUX_PB09B_ADC0_AIN3 (1L) -#define PINMUX_PB09B_ADC0_AIN3 ((PIN_PB09B_ADC0_AIN3 << 16) | MUX_PB09B_ADC0_AIN3) -#define PORT_PB09B_ADC0_AIN3 ((1UL) << 9) - -#define PIN_PA04B_ADC0_AIN4 (4L) -#define MUX_PA04B_ADC0_AIN4 (1L) -#define PINMUX_PA04B_ADC0_AIN4 ((PIN_PA04B_ADC0_AIN4 << 16) | MUX_PA04B_ADC0_AIN4) -#define PORT_PA04B_ADC0_AIN4 ((1UL) << 4) - -#define PIN_PA05B_ADC0_AIN5 (5L) -#define MUX_PA05B_ADC0_AIN5 (1L) -#define PINMUX_PA05B_ADC0_AIN5 ((PIN_PA05B_ADC0_AIN5 << 16) | MUX_PA05B_ADC0_AIN5) -#define PORT_PA05B_ADC0_AIN5 ((1UL) << 5) - -#define PIN_PA06B_ADC0_AIN6 (6L) -#define MUX_PA06B_ADC0_AIN6 (1L) -#define PINMUX_PA06B_ADC0_AIN6 ((PIN_PA06B_ADC0_AIN6 << 16) | MUX_PA06B_ADC0_AIN6) -#define PORT_PA06B_ADC0_AIN6 ((1UL) << 6) - -#define PIN_PA07B_ADC0_AIN7 (7L) -#define MUX_PA07B_ADC0_AIN7 (1L) -#define PINMUX_PA07B_ADC0_AIN7 ((PIN_PA07B_ADC0_AIN7 << 16) | MUX_PA07B_ADC0_AIN7) -#define PORT_PA07B_ADC0_AIN7 ((1UL) << 7) - -#define PIN_PA08B_ADC0_AIN8 (8L) -#define MUX_PA08B_ADC0_AIN8 (1L) -#define PINMUX_PA08B_ADC0_AIN8 ((PIN_PA08B_ADC0_AIN8 << 16) | MUX_PA08B_ADC0_AIN8) -#define PORT_PA08B_ADC0_AIN8 ((1UL) << 8) - -#define PIN_PA09B_ADC0_AIN9 (9L) -#define MUX_PA09B_ADC0_AIN9 (1L) -#define PINMUX_PA09B_ADC0_AIN9 ((PIN_PA09B_ADC0_AIN9 << 16) | MUX_PA09B_ADC0_AIN9) -#define PORT_PA09B_ADC0_AIN9 ((1UL) << 9) - -#define PIN_PA10B_ADC0_AIN10 (10L) -#define MUX_PA10B_ADC0_AIN10 (1L) -#define PINMUX_PA10B_ADC0_AIN10 ((PIN_PA10B_ADC0_AIN10 << 16) | MUX_PA10B_ADC0_AIN10) -#define PORT_PA10B_ADC0_AIN10 ((1UL) << 10) - -#define PIN_PA11B_ADC0_AIN11 (11L) -#define MUX_PA11B_ADC0_AIN11 (1L) -#define PINMUX_PA11B_ADC0_AIN11 ((PIN_PA11B_ADC0_AIN11 << 16) | MUX_PA11B_ADC0_AIN11) -#define PORT_PA11B_ADC0_AIN11 ((1UL) << 11) - -#define PIN_PB00B_ADC0_AIN12 (32L) -#define MUX_PB00B_ADC0_AIN12 (1L) -#define PINMUX_PB00B_ADC0_AIN12 ((PIN_PB00B_ADC0_AIN12 << 16) | MUX_PB00B_ADC0_AIN12) -#define PORT_PB00B_ADC0_AIN12 ((1UL) << 0) - -#define PIN_PB01B_ADC0_AIN13 (33L) -#define MUX_PB01B_ADC0_AIN13 (1L) -#define PINMUX_PB01B_ADC0_AIN13 ((PIN_PB01B_ADC0_AIN13 << 16) | MUX_PB01B_ADC0_AIN13) -#define PORT_PB01B_ADC0_AIN13 ((1UL) << 1) - -#define PIN_PB02B_ADC0_AIN14 (34L) -#define MUX_PB02B_ADC0_AIN14 (1L) -#define PINMUX_PB02B_ADC0_AIN14 ((PIN_PB02B_ADC0_AIN14 << 16) | MUX_PB02B_ADC0_AIN14) -#define PORT_PB02B_ADC0_AIN14 ((1UL) << 2) - -#define PIN_PB03B_ADC0_AIN15 (35L) -#define MUX_PB03B_ADC0_AIN15 (1L) -#define PINMUX_PB03B_ADC0_AIN15 ((PIN_PB03B_ADC0_AIN15 << 16) | MUX_PB03B_ADC0_AIN15) -#define PORT_PB03B_ADC0_AIN15 ((1UL) << 3) - -#define PIN_PA03B_ADC0_VREFA (3L) -#define MUX_PA03B_ADC0_VREFA (1L) -#define PINMUX_PA03B_ADC0_VREFA ((PIN_PA03B_ADC0_VREFA << 16) | MUX_PA03B_ADC0_VREFA) -#define PORT_PA03B_ADC0_VREFA ((1UL) << 3) - -#define PIN_PA04B_ADC0_VREFB (4L) -#define MUX_PA04B_ADC0_VREFB (1L) -#define PINMUX_PA04B_ADC0_VREFB ((PIN_PA04B_ADC0_VREFB << 16) | MUX_PA04B_ADC0_VREFB) -#define PORT_PA04B_ADC0_VREFB ((1UL) << 4) - -#define PIN_PA06B_ADC0_VREFC (6L) -#define MUX_PA06B_ADC0_VREFC (1L) -#define PINMUX_PA06B_ADC0_VREFC ((PIN_PA06B_ADC0_VREFC << 16) | MUX_PA06B_ADC0_VREFC) -#define PORT_PA06B_ADC0_VREFC ((1UL) << 6) - -#define PIN_PA03B_ADC0_X0 (3L) -#define MUX_PA03B_ADC0_X0 (1L) -#define PINMUX_PA03B_ADC0_X0 ((PIN_PA03B_ADC0_X0 << 16) | MUX_PA03B_ADC0_X0) -#define PORT_PA03B_ADC0_X0 ((1UL) << 3) - -#define PIN_PB08B_ADC0_X1 (40L) -#define MUX_PB08B_ADC0_X1 (1L) -#define PINMUX_PB08B_ADC0_X1 ((PIN_PB08B_ADC0_X1 << 16) | MUX_PB08B_ADC0_X1) -#define PORT_PB08B_ADC0_X1 ((1UL) << 8) - -#define PIN_PB09B_ADC0_X2 (41L) -#define MUX_PB09B_ADC0_X2 (1L) -#define PINMUX_PB09B_ADC0_X2 ((PIN_PB09B_ADC0_X2 << 16) | MUX_PB09B_ADC0_X2) -#define PORT_PB09B_ADC0_X2 ((1UL) << 9) - -#define PIN_PA04B_ADC0_X3 (4L) -#define MUX_PA04B_ADC0_X3 (1L) -#define PINMUX_PA04B_ADC0_X3 ((PIN_PA04B_ADC0_X3 << 16) | MUX_PA04B_ADC0_X3) -#define PORT_PA04B_ADC0_X3 ((1UL) << 4) - -#define PIN_PA06B_ADC0_X4 (6L) -#define MUX_PA06B_ADC0_X4 (1L) -#define PINMUX_PA06B_ADC0_X4 ((PIN_PA06B_ADC0_X4 << 16) | MUX_PA06B_ADC0_X4) -#define PORT_PA06B_ADC0_X4 ((1UL) << 6) - -#define PIN_PA07B_ADC0_X5 (7L) -#define MUX_PA07B_ADC0_X5 (1L) -#define PINMUX_PA07B_ADC0_X5 ((PIN_PA07B_ADC0_X5 << 16) | MUX_PA07B_ADC0_X5) -#define PORT_PA07B_ADC0_X5 ((1UL) << 7) - -#define PIN_PA08B_ADC0_X6 (8L) -#define MUX_PA08B_ADC0_X6 (1L) -#define PINMUX_PA08B_ADC0_X6 ((PIN_PA08B_ADC0_X6 << 16) | MUX_PA08B_ADC0_X6) -#define PORT_PA08B_ADC0_X6 ((1UL) << 8) - -#define PIN_PA09B_ADC0_X7 (9L) -#define MUX_PA09B_ADC0_X7 (1L) -#define PINMUX_PA09B_ADC0_X7 ((PIN_PA09B_ADC0_X7 << 16) | MUX_PA09B_ADC0_X7) -#define PORT_PA09B_ADC0_X7 ((1UL) << 9) - -#define PIN_PA10B_ADC0_X8 (10L) -#define MUX_PA10B_ADC0_X8 (1L) -#define PINMUX_PA10B_ADC0_X8 ((PIN_PA10B_ADC0_X8 << 16) | MUX_PA10B_ADC0_X8) -#define PORT_PA10B_ADC0_X8 ((1UL) << 10) - -#define PIN_PA11B_ADC0_X9 (11L) -#define MUX_PA11B_ADC0_X9 (1L) -#define PINMUX_PA11B_ADC0_X9 ((PIN_PA11B_ADC0_X9 << 16) | MUX_PA11B_ADC0_X9) -#define PORT_PA11B_ADC0_X9 ((1UL) << 11) - -#define PIN_PA16B_ADC0_X10 (16L) -#define MUX_PA16B_ADC0_X10 (1L) -#define PINMUX_PA16B_ADC0_X10 ((PIN_PA16B_ADC0_X10 << 16) | MUX_PA16B_ADC0_X10) -#define PORT_PA16B_ADC0_X10 ((1UL) << 16) - -#define PIN_PA17B_ADC0_X11 (17L) -#define MUX_PA17B_ADC0_X11 (1L) -#define PINMUX_PA17B_ADC0_X11 ((PIN_PA17B_ADC0_X11 << 16) | MUX_PA17B_ADC0_X11) -#define PORT_PA17B_ADC0_X11 ((1UL) << 17) - -#define PIN_PA18B_ADC0_X12 (18L) -#define MUX_PA18B_ADC0_X12 (1L) -#define PINMUX_PA18B_ADC0_X12 ((PIN_PA18B_ADC0_X12 << 16) | MUX_PA18B_ADC0_X12) -#define PORT_PA18B_ADC0_X12 ((1UL) << 18) - -#define PIN_PA19B_ADC0_X13 (19L) -#define MUX_PA19B_ADC0_X13 (1L) -#define PINMUX_PA19B_ADC0_X13 ((PIN_PA19B_ADC0_X13 << 16) | MUX_PA19B_ADC0_X13) -#define PORT_PA19B_ADC0_X13 ((1UL) << 19) - -#define PIN_PA20B_ADC0_X14 (20L) -#define MUX_PA20B_ADC0_X14 (1L) -#define PINMUX_PA20B_ADC0_X14 ((PIN_PA20B_ADC0_X14 << 16) | MUX_PA20B_ADC0_X14) -#define PORT_PA20B_ADC0_X14 ((1UL) << 20) - -#define PIN_PA21B_ADC0_X15 (21L) -#define MUX_PA21B_ADC0_X15 (1L) -#define PINMUX_PA21B_ADC0_X15 ((PIN_PA21B_ADC0_X15 << 16) | MUX_PA21B_ADC0_X15) -#define PORT_PA21B_ADC0_X15 ((1UL) << 21) - -#define PIN_PA22B_ADC0_X16 (22L) -#define MUX_PA22B_ADC0_X16 (1L) -#define PINMUX_PA22B_ADC0_X16 ((PIN_PA22B_ADC0_X16 << 16) | MUX_PA22B_ADC0_X16) -#define PORT_PA22B_ADC0_X16 ((1UL) << 22) - -#define PIN_PA23B_ADC0_X17 (23L) -#define MUX_PA23B_ADC0_X17 (1L) -#define PINMUX_PA23B_ADC0_X17 ((PIN_PA23B_ADC0_X17 << 16) | MUX_PA23B_ADC0_X17) -#define PORT_PA23B_ADC0_X17 ((1UL) << 23) - -#define PIN_PA27B_ADC0_X18 (27L) -#define MUX_PA27B_ADC0_X18 (1L) -#define PINMUX_PA27B_ADC0_X18 ((PIN_PA27B_ADC0_X18 << 16) | MUX_PA27B_ADC0_X18) -#define PORT_PA27B_ADC0_X18 ((1UL) << 27) - -#define PIN_PA30B_ADC0_X19 (30L) -#define MUX_PA30B_ADC0_X19 (1L) -#define PINMUX_PA30B_ADC0_X19 ((PIN_PA30B_ADC0_X19 << 16) | MUX_PA30B_ADC0_X19) -#define PORT_PA30B_ADC0_X19 ((1UL) << 30) - -#define PIN_PB02B_ADC0_X20 (34L) -#define MUX_PB02B_ADC0_X20 (1L) -#define PINMUX_PB02B_ADC0_X20 ((PIN_PB02B_ADC0_X20 << 16) | MUX_PB02B_ADC0_X20) -#define PORT_PB02B_ADC0_X20 ((1UL) << 2) - -#define PIN_PB03B_ADC0_X21 (35L) -#define MUX_PB03B_ADC0_X21 (1L) -#define PINMUX_PB03B_ADC0_X21 ((PIN_PB03B_ADC0_X21 << 16) | MUX_PB03B_ADC0_X21) -#define PORT_PB03B_ADC0_X21 ((1UL) << 3) - -#define PIN_PB04B_ADC0_X22 (36L) -#define MUX_PB04B_ADC0_X22 (1L) -#define PINMUX_PB04B_ADC0_X22 ((PIN_PB04B_ADC0_X22 << 16) | MUX_PB04B_ADC0_X22) -#define PORT_PB04B_ADC0_X22 ((1UL) << 4) - -#define PIN_PB05B_ADC0_X23 (37L) -#define MUX_PB05B_ADC0_X23 (1L) -#define PINMUX_PB05B_ADC0_X23 ((PIN_PB05B_ADC0_X23 << 16) | MUX_PB05B_ADC0_X23) -#define PORT_PB05B_ADC0_X23 ((1UL) << 5) - -#define PIN_PB06B_ADC0_X24 (38L) -#define MUX_PB06B_ADC0_X24 (1L) -#define PINMUX_PB06B_ADC0_X24 ((PIN_PB06B_ADC0_X24 << 16) | MUX_PB06B_ADC0_X24) -#define PORT_PB06B_ADC0_X24 ((1UL) << 6) - -#define PIN_PB07B_ADC0_X25 (39L) -#define MUX_PB07B_ADC0_X25 (1L) -#define PINMUX_PB07B_ADC0_X25 ((PIN_PB07B_ADC0_X25 << 16) | MUX_PB07B_ADC0_X25) -#define PORT_PB07B_ADC0_X25 ((1UL) << 7) - -#define PIN_PB12B_ADC0_X26 (44L) -#define MUX_PB12B_ADC0_X26 (1L) -#define PINMUX_PB12B_ADC0_X26 ((PIN_PB12B_ADC0_X26 << 16) | MUX_PB12B_ADC0_X26) -#define PORT_PB12B_ADC0_X26 ((1UL) << 12) - -#define PIN_PB13B_ADC0_X27 (45L) -#define MUX_PB13B_ADC0_X27 (1L) -#define PINMUX_PB13B_ADC0_X27 ((PIN_PB13B_ADC0_X27 << 16) | MUX_PB13B_ADC0_X27) -#define PORT_PB13B_ADC0_X27 ((1UL) << 13) - -#define PIN_PB14B_ADC0_X28 (46L) -#define MUX_PB14B_ADC0_X28 (1L) -#define PINMUX_PB14B_ADC0_X28 ((PIN_PB14B_ADC0_X28 << 16) | MUX_PB14B_ADC0_X28) -#define PORT_PB14B_ADC0_X28 ((1UL) << 14) - -#define PIN_PB15B_ADC0_X29 (47L) -#define MUX_PB15B_ADC0_X29 (1L) -#define PINMUX_PB15B_ADC0_X29 ((PIN_PB15B_ADC0_X29 << 16) | MUX_PB15B_ADC0_X29) -#define PORT_PB15B_ADC0_X29 ((1UL) << 15) - -#define PIN_PB00B_ADC0_X30 (32L) -#define MUX_PB00B_ADC0_X30 (1L) -#define PINMUX_PB00B_ADC0_X30 ((PIN_PB00B_ADC0_X30 << 16) | MUX_PB00B_ADC0_X30) -#define PORT_PB00B_ADC0_X30 ((1UL) << 0) - -#define PIN_PB01B_ADC0_X31 (33L) -#define MUX_PB01B_ADC0_X31 (1L) -#define PINMUX_PB01B_ADC0_X31 ((PIN_PB01B_ADC0_X31 << 16) | MUX_PB01B_ADC0_X31) -#define PORT_PB01B_ADC0_X31 ((1UL) << 1) - -#define PIN_PA03B_ADC0_Y0 (3L) -#define MUX_PA03B_ADC0_Y0 (1L) -#define PINMUX_PA03B_ADC0_Y0 ((PIN_PA03B_ADC0_Y0 << 16) | MUX_PA03B_ADC0_Y0) -#define PORT_PA03B_ADC0_Y0 ((1UL) << 3) - -#define PIN_PB08B_ADC0_Y1 (40L) -#define MUX_PB08B_ADC0_Y1 (1L) -#define PINMUX_PB08B_ADC0_Y1 ((PIN_PB08B_ADC0_Y1 << 16) | MUX_PB08B_ADC0_Y1) -#define PORT_PB08B_ADC0_Y1 ((1UL) << 8) - -#define PIN_PB09B_ADC0_Y2 (41L) -#define MUX_PB09B_ADC0_Y2 (1L) -#define PINMUX_PB09B_ADC0_Y2 ((PIN_PB09B_ADC0_Y2 << 16) | MUX_PB09B_ADC0_Y2) -#define PORT_PB09B_ADC0_Y2 ((1UL) << 9) - -#define PIN_PA04B_ADC0_Y3 (4L) -#define MUX_PA04B_ADC0_Y3 (1L) -#define PINMUX_PA04B_ADC0_Y3 ((PIN_PA04B_ADC0_Y3 << 16) | MUX_PA04B_ADC0_Y3) -#define PORT_PA04B_ADC0_Y3 ((1UL) << 4) - -#define PIN_PA06B_ADC0_Y4 (6L) -#define MUX_PA06B_ADC0_Y4 (1L) -#define PINMUX_PA06B_ADC0_Y4 ((PIN_PA06B_ADC0_Y4 << 16) | MUX_PA06B_ADC0_Y4) -#define PORT_PA06B_ADC0_Y4 ((1UL) << 6) - -#define PIN_PA07B_ADC0_Y5 (7L) -#define MUX_PA07B_ADC0_Y5 (1L) -#define PINMUX_PA07B_ADC0_Y5 ((PIN_PA07B_ADC0_Y5 << 16) | MUX_PA07B_ADC0_Y5) -#define PORT_PA07B_ADC0_Y5 ((1UL) << 7) - -#define PIN_PA08B_ADC0_Y6 (8L) -#define MUX_PA08B_ADC0_Y6 (1L) -#define PINMUX_PA08B_ADC0_Y6 ((PIN_PA08B_ADC0_Y6 << 16) | MUX_PA08B_ADC0_Y6) -#define PORT_PA08B_ADC0_Y6 ((1UL) << 8) - -#define PIN_PA09B_ADC0_Y7 (9L) -#define MUX_PA09B_ADC0_Y7 (1L) -#define PINMUX_PA09B_ADC0_Y7 ((PIN_PA09B_ADC0_Y7 << 16) | MUX_PA09B_ADC0_Y7) -#define PORT_PA09B_ADC0_Y7 ((1UL) << 9) - -#define PIN_PA10B_ADC0_Y8 (10L) -#define MUX_PA10B_ADC0_Y8 (1L) -#define PINMUX_PA10B_ADC0_Y8 ((PIN_PA10B_ADC0_Y8 << 16) | MUX_PA10B_ADC0_Y8) -#define PORT_PA10B_ADC0_Y8 ((1UL) << 10) - -#define PIN_PA11B_ADC0_Y9 (11L) -#define MUX_PA11B_ADC0_Y9 (1L) -#define PINMUX_PA11B_ADC0_Y9 ((PIN_PA11B_ADC0_Y9 << 16) | MUX_PA11B_ADC0_Y9) -#define PORT_PA11B_ADC0_Y9 ((1UL) << 11) - -#define PIN_PA16B_ADC0_Y10 (16L) -#define MUX_PA16B_ADC0_Y10 (1L) -#define PINMUX_PA16B_ADC0_Y10 ((PIN_PA16B_ADC0_Y10 << 16) | MUX_PA16B_ADC0_Y10) -#define PORT_PA16B_ADC0_Y10 ((1UL) << 16) - -#define PIN_PA17B_ADC0_Y11 (17L) -#define MUX_PA17B_ADC0_Y11 (1L) -#define PINMUX_PA17B_ADC0_Y11 ((PIN_PA17B_ADC0_Y11 << 16) | MUX_PA17B_ADC0_Y11) -#define PORT_PA17B_ADC0_Y11 ((1UL) << 17) - -#define PIN_PA18B_ADC0_Y12 (18L) -#define MUX_PA18B_ADC0_Y12 (1L) -#define PINMUX_PA18B_ADC0_Y12 ((PIN_PA18B_ADC0_Y12 << 16) | MUX_PA18B_ADC0_Y12) -#define PORT_PA18B_ADC0_Y12 ((1UL) << 18) - -#define PIN_PA19B_ADC0_Y13 (19L) -#define MUX_PA19B_ADC0_Y13 (1L) -#define PINMUX_PA19B_ADC0_Y13 ((PIN_PA19B_ADC0_Y13 << 16) | MUX_PA19B_ADC0_Y13) -#define PORT_PA19B_ADC0_Y13 ((1UL) << 19) - -#define PIN_PA20B_ADC0_Y14 (20L) -#define MUX_PA20B_ADC0_Y14 (1L) -#define PINMUX_PA20B_ADC0_Y14 ((PIN_PA20B_ADC0_Y14 << 16) | MUX_PA20B_ADC0_Y14) -#define PORT_PA20B_ADC0_Y14 ((1UL) << 20) - -#define PIN_PA21B_ADC0_Y15 (21L) -#define MUX_PA21B_ADC0_Y15 (1L) -#define PINMUX_PA21B_ADC0_Y15 ((PIN_PA21B_ADC0_Y15 << 16) | MUX_PA21B_ADC0_Y15) -#define PORT_PA21B_ADC0_Y15 ((1UL) << 21) - -#define PIN_PA22B_ADC0_Y16 (22L) -#define MUX_PA22B_ADC0_Y16 (1L) -#define PINMUX_PA22B_ADC0_Y16 ((PIN_PA22B_ADC0_Y16 << 16) | MUX_PA22B_ADC0_Y16) -#define PORT_PA22B_ADC0_Y16 ((1UL) << 22) - -#define PIN_PA23B_ADC0_Y17 (23L) -#define MUX_PA23B_ADC0_Y17 (1L) -#define PINMUX_PA23B_ADC0_Y17 ((PIN_PA23B_ADC0_Y17 << 16) | MUX_PA23B_ADC0_Y17) -#define PORT_PA23B_ADC0_Y17 ((1UL) << 23) - -#define PIN_PA27B_ADC0_Y18 (27L) -#define MUX_PA27B_ADC0_Y18 (1L) -#define PINMUX_PA27B_ADC0_Y18 ((PIN_PA27B_ADC0_Y18 << 16) | MUX_PA27B_ADC0_Y18) -#define PORT_PA27B_ADC0_Y18 ((1UL) << 27) - -#define PIN_PA30B_ADC0_Y19 (30L) -#define MUX_PA30B_ADC0_Y19 (1L) -#define PINMUX_PA30B_ADC0_Y19 ((PIN_PA30B_ADC0_Y19 << 16) | MUX_PA30B_ADC0_Y19) -#define PORT_PA30B_ADC0_Y19 ((1UL) << 30) - -#define PIN_PB02B_ADC0_Y20 (34L) -#define MUX_PB02B_ADC0_Y20 (1L) -#define PINMUX_PB02B_ADC0_Y20 ((PIN_PB02B_ADC0_Y20 << 16) | MUX_PB02B_ADC0_Y20) -#define PORT_PB02B_ADC0_Y20 ((1UL) << 2) - -#define PIN_PB03B_ADC0_Y21 (35L) -#define MUX_PB03B_ADC0_Y21 (1L) -#define PINMUX_PB03B_ADC0_Y21 ((PIN_PB03B_ADC0_Y21 << 16) | MUX_PB03B_ADC0_Y21) -#define PORT_PB03B_ADC0_Y21 ((1UL) << 3) - -#define PIN_PB04B_ADC0_Y22 (36L) -#define MUX_PB04B_ADC0_Y22 (1L) -#define PINMUX_PB04B_ADC0_Y22 ((PIN_PB04B_ADC0_Y22 << 16) | MUX_PB04B_ADC0_Y22) -#define PORT_PB04B_ADC0_Y22 ((1UL) << 4) - -#define PIN_PB05B_ADC0_Y23 (37L) -#define MUX_PB05B_ADC0_Y23 (1L) -#define PINMUX_PB05B_ADC0_Y23 ((PIN_PB05B_ADC0_Y23 << 16) | MUX_PB05B_ADC0_Y23) -#define PORT_PB05B_ADC0_Y23 ((1UL) << 5) - -#define PIN_PB06B_ADC0_Y24 (38L) -#define MUX_PB06B_ADC0_Y24 (1L) -#define PINMUX_PB06B_ADC0_Y24 ((PIN_PB06B_ADC0_Y24 << 16) | MUX_PB06B_ADC0_Y24) -#define PORT_PB06B_ADC0_Y24 ((1UL) << 6) - -#define PIN_PB07B_ADC0_Y25 (39L) -#define MUX_PB07B_ADC0_Y25 (1L) -#define PINMUX_PB07B_ADC0_Y25 ((PIN_PB07B_ADC0_Y25 << 16) | MUX_PB07B_ADC0_Y25) -#define PORT_PB07B_ADC0_Y25 ((1UL) << 7) - -#define PIN_PB12B_ADC0_Y26 (44L) -#define MUX_PB12B_ADC0_Y26 (1L) -#define PINMUX_PB12B_ADC0_Y26 ((PIN_PB12B_ADC0_Y26 << 16) | MUX_PB12B_ADC0_Y26) -#define PORT_PB12B_ADC0_Y26 ((1UL) << 12) - -#define PIN_PB13B_ADC0_Y27 (45L) -#define MUX_PB13B_ADC0_Y27 (1L) -#define PINMUX_PB13B_ADC0_Y27 ((PIN_PB13B_ADC0_Y27 << 16) | MUX_PB13B_ADC0_Y27) -#define PORT_PB13B_ADC0_Y27 ((1UL) << 13) - -#define PIN_PB14B_ADC0_Y28 (46L) -#define MUX_PB14B_ADC0_Y28 (1L) -#define PINMUX_PB14B_ADC0_Y28 ((PIN_PB14B_ADC0_Y28 << 16) | MUX_PB14B_ADC0_Y28) -#define PORT_PB14B_ADC0_Y28 ((1UL) << 14) - -#define PIN_PB15B_ADC0_Y29 (47L) -#define MUX_PB15B_ADC0_Y29 (1L) -#define PINMUX_PB15B_ADC0_Y29 ((PIN_PB15B_ADC0_Y29 << 16) | MUX_PB15B_ADC0_Y29) -#define PORT_PB15B_ADC0_Y29 ((1UL) << 15) - -#define PIN_PB00B_ADC0_Y30 (32L) -#define MUX_PB00B_ADC0_Y30 (1L) -#define PINMUX_PB00B_ADC0_Y30 ((PIN_PB00B_ADC0_Y30 << 16) | MUX_PB00B_ADC0_Y30) -#define PORT_PB00B_ADC0_Y30 ((1UL) << 0) - -#define PIN_PB01B_ADC0_Y31 (33L) -#define MUX_PB01B_ADC0_Y31 (1L) -#define PINMUX_PB01B_ADC0_Y31 ((PIN_PB01B_ADC0_Y31 << 16) | MUX_PB01B_ADC0_Y31) -#define PORT_PB01B_ADC0_Y31 ((1UL) << 1) - -/* ========== PORT definition for ADC1 peripheral ========== */ -#define PIN_PB08B_ADC1_AIN0 (40L) -#define MUX_PB08B_ADC1_AIN0 (1L) -#define PINMUX_PB08B_ADC1_AIN0 ((PIN_PB08B_ADC1_AIN0 << 16) | MUX_PB08B_ADC1_AIN0) -#define PORT_PB08B_ADC1_AIN0 ((1UL) << 8) - -#define PIN_PB09B_ADC1_AIN1 (41L) -#define MUX_PB09B_ADC1_AIN1 (1L) -#define PINMUX_PB09B_ADC1_AIN1 ((PIN_PB09B_ADC1_AIN1 << 16) | MUX_PB09B_ADC1_AIN1) -#define PORT_PB09B_ADC1_AIN1 ((1UL) << 9) - -#define PIN_PA08B_ADC1_AIN2 (8L) -#define MUX_PA08B_ADC1_AIN2 (1L) -#define PINMUX_PA08B_ADC1_AIN2 ((PIN_PA08B_ADC1_AIN2 << 16) | MUX_PA08B_ADC1_AIN2) -#define PORT_PA08B_ADC1_AIN2 ((1UL) << 8) - -#define PIN_PA09B_ADC1_AIN3 (9L) -#define MUX_PA09B_ADC1_AIN3 (1L) -#define PINMUX_PA09B_ADC1_AIN3 ((PIN_PA09B_ADC1_AIN3 << 16) | MUX_PA09B_ADC1_AIN3) -#define PORT_PA09B_ADC1_AIN3 ((1UL) << 9) - -#define PIN_PC02B_ADC1_AIN4 (66L) -#define MUX_PC02B_ADC1_AIN4 (1L) -#define PINMUX_PC02B_ADC1_AIN4 ((PIN_PC02B_ADC1_AIN4 << 16) | MUX_PC02B_ADC1_AIN4) -#define PORT_PC02B_ADC1_AIN4 ((1UL) << 2) - -#define PIN_PC03B_ADC1_AIN5 (67L) -#define MUX_PC03B_ADC1_AIN5 (1L) -#define PINMUX_PC03B_ADC1_AIN5 ((PIN_PC03B_ADC1_AIN5 << 16) | MUX_PC03B_ADC1_AIN5) -#define PORT_PC03B_ADC1_AIN5 ((1UL) << 3) - -#define PIN_PB04B_ADC1_AIN6 (36L) -#define MUX_PB04B_ADC1_AIN6 (1L) -#define PINMUX_PB04B_ADC1_AIN6 ((PIN_PB04B_ADC1_AIN6 << 16) | MUX_PB04B_ADC1_AIN6) -#define PORT_PB04B_ADC1_AIN6 ((1UL) << 4) - -#define PIN_PB05B_ADC1_AIN7 (37L) -#define MUX_PB05B_ADC1_AIN7 (1L) -#define PINMUX_PB05B_ADC1_AIN7 ((PIN_PB05B_ADC1_AIN7 << 16) | MUX_PB05B_ADC1_AIN7) -#define PORT_PB05B_ADC1_AIN7 ((1UL) << 5) - -#define PIN_PB06B_ADC1_AIN8 (38L) -#define MUX_PB06B_ADC1_AIN8 (1L) -#define PINMUX_PB06B_ADC1_AIN8 ((PIN_PB06B_ADC1_AIN8 << 16) | MUX_PB06B_ADC1_AIN8) -#define PORT_PB06B_ADC1_AIN8 ((1UL) << 6) - -#define PIN_PB07B_ADC1_AIN9 (39L) -#define MUX_PB07B_ADC1_AIN9 (1L) -#define PINMUX_PB07B_ADC1_AIN9 ((PIN_PB07B_ADC1_AIN9 << 16) | MUX_PB07B_ADC1_AIN9) -#define PORT_PB07B_ADC1_AIN9 ((1UL) << 7) - -#define PIN_PC00B_ADC1_AIN10 (64L) -#define MUX_PC00B_ADC1_AIN10 (1L) -#define PINMUX_PC00B_ADC1_AIN10 ((PIN_PC00B_ADC1_AIN10 << 16) | MUX_PC00B_ADC1_AIN10) -#define PORT_PC00B_ADC1_AIN10 ((1UL) << 0) - -#define PIN_PC01B_ADC1_AIN11 (65L) -#define MUX_PC01B_ADC1_AIN11 (1L) -#define PINMUX_PC01B_ADC1_AIN11 ((PIN_PC01B_ADC1_AIN11 << 16) | MUX_PC01B_ADC1_AIN11) -#define PORT_PC01B_ADC1_AIN11 ((1UL) << 1) - -#define PIN_PC30B_ADC1_AIN12 (94L) -#define MUX_PC30B_ADC1_AIN12 (1L) -#define PINMUX_PC30B_ADC1_AIN12 ((PIN_PC30B_ADC1_AIN12 << 16) | MUX_PC30B_ADC1_AIN12) -#define PORT_PC30B_ADC1_AIN12 ((1UL) << 30) - -#define PIN_PC31B_ADC1_AIN13 (95L) -#define MUX_PC31B_ADC1_AIN13 (1L) -#define PINMUX_PC31B_ADC1_AIN13 ((PIN_PC31B_ADC1_AIN13 << 16) | MUX_PC31B_ADC1_AIN13) -#define PORT_PC31B_ADC1_AIN13 ((1UL) << 31) - -#define PIN_PD00B_ADC1_AIN14 (96L) -#define MUX_PD00B_ADC1_AIN14 (1L) -#define PINMUX_PD00B_ADC1_AIN14 ((PIN_PD00B_ADC1_AIN14 << 16) | MUX_PD00B_ADC1_AIN14) -#define PORT_PD00B_ADC1_AIN14 ((1UL) << 0) - -#define PIN_PD01B_ADC1_AIN15 (97L) -#define MUX_PD01B_ADC1_AIN15 (1L) -#define PINMUX_PD01B_ADC1_AIN15 ((PIN_PD01B_ADC1_AIN15 << 16) | MUX_PD01B_ADC1_AIN15) -#define PORT_PD01B_ADC1_AIN15 ((1UL) << 1) - -/* ========== PORT definition for CAN0 peripheral ========== */ -#define PIN_PA23I_CAN0_RX (23L) -#define MUX_PA23I_CAN0_RX (8L) -#define PINMUX_PA23I_CAN0_RX ((PIN_PA23I_CAN0_RX << 16) | MUX_PA23I_CAN0_RX) -#define PORT_PA23I_CAN0_RX ((1UL) << 23) - -#define PIN_PA25I_CAN0_RX (25L) -#define MUX_PA25I_CAN0_RX (8L) -#define PINMUX_PA25I_CAN0_RX ((PIN_PA25I_CAN0_RX << 16) | MUX_PA25I_CAN0_RX) -#define PORT_PA25I_CAN0_RX ((1UL) << 25) - -#define PIN_PA22I_CAN0_TX (22L) -#define MUX_PA22I_CAN0_TX (8L) -#define PINMUX_PA22I_CAN0_TX ((PIN_PA22I_CAN0_TX << 16) | MUX_PA22I_CAN0_TX) -#define PORT_PA22I_CAN0_TX ((1UL) << 22) - -#define PIN_PA24I_CAN0_TX (24L) -#define MUX_PA24I_CAN0_TX (8L) -#define PINMUX_PA24I_CAN0_TX ((PIN_PA24I_CAN0_TX << 16) | MUX_PA24I_CAN0_TX) -#define PORT_PA24I_CAN0_TX ((1UL) << 24) - -/* ========== PORT definition for CAN1 peripheral ========== */ -#define PIN_PB13H_CAN1_RX (45L) -#define MUX_PB13H_CAN1_RX (7L) -#define PINMUX_PB13H_CAN1_RX ((PIN_PB13H_CAN1_RX << 16) | MUX_PB13H_CAN1_RX) -#define PORT_PB13H_CAN1_RX ((1UL) << 13) - -#define PIN_PB15H_CAN1_RX (47L) -#define MUX_PB15H_CAN1_RX (7L) -#define PINMUX_PB15H_CAN1_RX ((PIN_PB15H_CAN1_RX << 16) | MUX_PB15H_CAN1_RX) -#define PORT_PB15H_CAN1_RX ((1UL) << 15) - -#define PIN_PB12H_CAN1_TX (44L) -#define MUX_PB12H_CAN1_TX (7L) -#define PINMUX_PB12H_CAN1_TX ((PIN_PB12H_CAN1_TX << 16) | MUX_PB12H_CAN1_TX) -#define PORT_PB12H_CAN1_TX ((1UL) << 12) - -#define PIN_PB14H_CAN1_TX (46L) -#define MUX_PB14H_CAN1_TX (7L) -#define PINMUX_PB14H_CAN1_TX ((PIN_PB14H_CAN1_TX << 16) | MUX_PB14H_CAN1_TX) -#define PORT_PB14H_CAN1_TX ((1UL) << 14) - -/* ========== PORT definition for CCL peripheral ========== */ -#define PIN_PA04N_CCL_IN0 (4L) -#define MUX_PA04N_CCL_IN0 (13L) -#define PINMUX_PA04N_CCL_IN0 ((PIN_PA04N_CCL_IN0 << 16) | MUX_PA04N_CCL_IN0) -#define PORT_PA04N_CCL_IN0 ((1UL) << 4) - -#define PIN_PA16N_CCL_IN0 (16L) -#define MUX_PA16N_CCL_IN0 (13L) -#define PINMUX_PA16N_CCL_IN0 ((PIN_PA16N_CCL_IN0 << 16) | MUX_PA16N_CCL_IN0) -#define PORT_PA16N_CCL_IN0 ((1UL) << 16) - -#define PIN_PB22N_CCL_IN0 (54L) -#define MUX_PB22N_CCL_IN0 (13L) -#define PINMUX_PB22N_CCL_IN0 ((PIN_PB22N_CCL_IN0 << 16) | MUX_PB22N_CCL_IN0) -#define PORT_PB22N_CCL_IN0 ((1UL) << 22) - -#define PIN_PA05N_CCL_IN1 (5L) -#define MUX_PA05N_CCL_IN1 (13L) -#define PINMUX_PA05N_CCL_IN1 ((PIN_PA05N_CCL_IN1 << 16) | MUX_PA05N_CCL_IN1) -#define PORT_PA05N_CCL_IN1 ((1UL) << 5) - -#define PIN_PA17N_CCL_IN1 (17L) -#define MUX_PA17N_CCL_IN1 (13L) -#define PINMUX_PA17N_CCL_IN1 ((PIN_PA17N_CCL_IN1 << 16) | MUX_PA17N_CCL_IN1) -#define PORT_PA17N_CCL_IN1 ((1UL) << 17) - -#define PIN_PB00N_CCL_IN1 (32L) -#define MUX_PB00N_CCL_IN1 (13L) -#define PINMUX_PB00N_CCL_IN1 ((PIN_PB00N_CCL_IN1 << 16) | MUX_PB00N_CCL_IN1) -#define PORT_PB00N_CCL_IN1 ((1UL) << 0) - -#define PIN_PA06N_CCL_IN2 (6L) -#define MUX_PA06N_CCL_IN2 (13L) -#define PINMUX_PA06N_CCL_IN2 ((PIN_PA06N_CCL_IN2 << 16) | MUX_PA06N_CCL_IN2) -#define PORT_PA06N_CCL_IN2 ((1UL) << 6) - -#define PIN_PA18N_CCL_IN2 (18L) -#define MUX_PA18N_CCL_IN2 (13L) -#define PINMUX_PA18N_CCL_IN2 ((PIN_PA18N_CCL_IN2 << 16) | MUX_PA18N_CCL_IN2) -#define PORT_PA18N_CCL_IN2 ((1UL) << 18) - -#define PIN_PB01N_CCL_IN2 (33L) -#define MUX_PB01N_CCL_IN2 (13L) -#define PINMUX_PB01N_CCL_IN2 ((PIN_PB01N_CCL_IN2 << 16) | MUX_PB01N_CCL_IN2) -#define PORT_PB01N_CCL_IN2 ((1UL) << 1) - -#define PIN_PA08N_CCL_IN3 (8L) -#define MUX_PA08N_CCL_IN3 (13L) -#define PINMUX_PA08N_CCL_IN3 ((PIN_PA08N_CCL_IN3 << 16) | MUX_PA08N_CCL_IN3) -#define PORT_PA08N_CCL_IN3 ((1UL) << 8) - -#define PIN_PA30N_CCL_IN3 (30L) -#define MUX_PA30N_CCL_IN3 (13L) -#define PINMUX_PA30N_CCL_IN3 ((PIN_PA30N_CCL_IN3 << 16) | MUX_PA30N_CCL_IN3) -#define PORT_PA30N_CCL_IN3 ((1UL) << 30) - -#define PIN_PA09N_CCL_IN4 (9L) -#define MUX_PA09N_CCL_IN4 (13L) -#define PINMUX_PA09N_CCL_IN4 ((PIN_PA09N_CCL_IN4 << 16) | MUX_PA09N_CCL_IN4) -#define PORT_PA09N_CCL_IN4 ((1UL) << 9) - -#define PIN_PC27N_CCL_IN4 (91L) -#define MUX_PC27N_CCL_IN4 (13L) -#define PINMUX_PC27N_CCL_IN4 ((PIN_PC27N_CCL_IN4 << 16) | MUX_PC27N_CCL_IN4) -#define PORT_PC27N_CCL_IN4 ((1UL) << 27) - -#define PIN_PA10N_CCL_IN5 (10L) -#define MUX_PA10N_CCL_IN5 (13L) -#define PINMUX_PA10N_CCL_IN5 ((PIN_PA10N_CCL_IN5 << 16) | MUX_PA10N_CCL_IN5) -#define PORT_PA10N_CCL_IN5 ((1UL) << 10) - -#define PIN_PC28N_CCL_IN5 (92L) -#define MUX_PC28N_CCL_IN5 (13L) -#define PINMUX_PC28N_CCL_IN5 ((PIN_PC28N_CCL_IN5 << 16) | MUX_PC28N_CCL_IN5) -#define PORT_PC28N_CCL_IN5 ((1UL) << 28) - -#define PIN_PA22N_CCL_IN6 (22L) -#define MUX_PA22N_CCL_IN6 (13L) -#define PINMUX_PA22N_CCL_IN6 ((PIN_PA22N_CCL_IN6 << 16) | MUX_PA22N_CCL_IN6) -#define PORT_PA22N_CCL_IN6 ((1UL) << 22) - -#define PIN_PB06N_CCL_IN6 (38L) -#define MUX_PB06N_CCL_IN6 (13L) -#define PINMUX_PB06N_CCL_IN6 ((PIN_PB06N_CCL_IN6 << 16) | MUX_PB06N_CCL_IN6) -#define PORT_PB06N_CCL_IN6 ((1UL) << 6) - -#define PIN_PA23N_CCL_IN7 (23L) -#define MUX_PA23N_CCL_IN7 (13L) -#define PINMUX_PA23N_CCL_IN7 ((PIN_PA23N_CCL_IN7 << 16) | MUX_PA23N_CCL_IN7) -#define PORT_PA23N_CCL_IN7 ((1UL) << 23) - -#define PIN_PB07N_CCL_IN7 (39L) -#define MUX_PB07N_CCL_IN7 (13L) -#define PINMUX_PB07N_CCL_IN7 ((PIN_PB07N_CCL_IN7 << 16) | MUX_PB07N_CCL_IN7) -#define PORT_PB07N_CCL_IN7 ((1UL) << 7) - -#define PIN_PA24N_CCL_IN8 (24L) -#define MUX_PA24N_CCL_IN8 (13L) -#define PINMUX_PA24N_CCL_IN8 ((PIN_PA24N_CCL_IN8 << 16) | MUX_PA24N_CCL_IN8) -#define PORT_PA24N_CCL_IN8 ((1UL) << 24) - -#define PIN_PB08N_CCL_IN8 (40L) -#define MUX_PB08N_CCL_IN8 (13L) -#define PINMUX_PB08N_CCL_IN8 ((PIN_PB08N_CCL_IN8 << 16) | MUX_PB08N_CCL_IN8) -#define PORT_PB08N_CCL_IN8 ((1UL) << 8) - -#define PIN_PB14N_CCL_IN9 (46L) -#define MUX_PB14N_CCL_IN9 (13L) -#define PINMUX_PB14N_CCL_IN9 ((PIN_PB14N_CCL_IN9 << 16) | MUX_PB14N_CCL_IN9) -#define PORT_PB14N_CCL_IN9 ((1UL) << 14) - -#define PIN_PC20N_CCL_IN9 (84L) -#define MUX_PC20N_CCL_IN9 (13L) -#define PINMUX_PC20N_CCL_IN9 ((PIN_PC20N_CCL_IN9 << 16) | MUX_PC20N_CCL_IN9) -#define PORT_PC20N_CCL_IN9 ((1UL) << 20) - -#define PIN_PB15N_CCL_IN10 (47L) -#define MUX_PB15N_CCL_IN10 (13L) -#define PINMUX_PB15N_CCL_IN10 ((PIN_PB15N_CCL_IN10 << 16) | MUX_PB15N_CCL_IN10) -#define PORT_PB15N_CCL_IN10 ((1UL) << 15) - -#define PIN_PC21N_CCL_IN10 (85L) -#define MUX_PC21N_CCL_IN10 (13L) -#define PINMUX_PC21N_CCL_IN10 ((PIN_PC21N_CCL_IN10 << 16) | MUX_PC21N_CCL_IN10) -#define PORT_PC21N_CCL_IN10 ((1UL) << 21) - -#define PIN_PB10N_CCL_IN11 (42L) -#define MUX_PB10N_CCL_IN11 (13L) -#define PINMUX_PB10N_CCL_IN11 ((PIN_PB10N_CCL_IN11 << 16) | MUX_PB10N_CCL_IN11) -#define PORT_PB10N_CCL_IN11 ((1UL) << 10) - -#define PIN_PB16N_CCL_IN11 (48L) -#define MUX_PB16N_CCL_IN11 (13L) -#define PINMUX_PB16N_CCL_IN11 ((PIN_PB16N_CCL_IN11 << 16) | MUX_PB16N_CCL_IN11) -#define PORT_PB16N_CCL_IN11 ((1UL) << 16) - -#define PIN_PA07N_CCL_OUT0 (7L) -#define MUX_PA07N_CCL_OUT0 (13L) -#define PINMUX_PA07N_CCL_OUT0 ((PIN_PA07N_CCL_OUT0 << 16) | MUX_PA07N_CCL_OUT0) -#define PORT_PA07N_CCL_OUT0 ((1UL) << 7) - -#define PIN_PA19N_CCL_OUT0 (19L) -#define MUX_PA19N_CCL_OUT0 (13L) -#define PINMUX_PA19N_CCL_OUT0 ((PIN_PA19N_CCL_OUT0 << 16) | MUX_PA19N_CCL_OUT0) -#define PORT_PA19N_CCL_OUT0 ((1UL) << 19) - -#define PIN_PB02N_CCL_OUT0 (34L) -#define MUX_PB02N_CCL_OUT0 (13L) -#define PINMUX_PB02N_CCL_OUT0 ((PIN_PB02N_CCL_OUT0 << 16) | MUX_PB02N_CCL_OUT0) -#define PORT_PB02N_CCL_OUT0 ((1UL) << 2) - -#define PIN_PB23N_CCL_OUT0 (55L) -#define MUX_PB23N_CCL_OUT0 (13L) -#define PINMUX_PB23N_CCL_OUT0 ((PIN_PB23N_CCL_OUT0 << 16) | MUX_PB23N_CCL_OUT0) -#define PORT_PB23N_CCL_OUT0 ((1UL) << 23) - -#define PIN_PA11N_CCL_OUT1 (11L) -#define MUX_PA11N_CCL_OUT1 (13L) -#define PINMUX_PA11N_CCL_OUT1 ((PIN_PA11N_CCL_OUT1 << 16) | MUX_PA11N_CCL_OUT1) -#define PORT_PA11N_CCL_OUT1 ((1UL) << 11) - -#define PIN_PA31N_CCL_OUT1 (31L) -#define MUX_PA31N_CCL_OUT1 (13L) -#define PINMUX_PA31N_CCL_OUT1 ((PIN_PA31N_CCL_OUT1 << 16) | MUX_PA31N_CCL_OUT1) -#define PORT_PA31N_CCL_OUT1 ((1UL) << 31) - -#define PIN_PB11N_CCL_OUT1 (43L) -#define MUX_PB11N_CCL_OUT1 (13L) -#define PINMUX_PB11N_CCL_OUT1 ((PIN_PB11N_CCL_OUT1 << 16) | MUX_PB11N_CCL_OUT1) -#define PORT_PB11N_CCL_OUT1 ((1UL) << 11) - -#define PIN_PA25N_CCL_OUT2 (25L) -#define MUX_PA25N_CCL_OUT2 (13L) -#define PINMUX_PA25N_CCL_OUT2 ((PIN_PA25N_CCL_OUT2 << 16) | MUX_PA25N_CCL_OUT2) -#define PORT_PA25N_CCL_OUT2 ((1UL) << 25) - -#define PIN_PB09N_CCL_OUT2 (41L) -#define MUX_PB09N_CCL_OUT2 (13L) -#define PINMUX_PB09N_CCL_OUT2 ((PIN_PB09N_CCL_OUT2 << 16) | MUX_PB09N_CCL_OUT2) -#define PORT_PB09N_CCL_OUT2 ((1UL) << 9) - -#define PIN_PB17N_CCL_OUT3 (49L) -#define MUX_PB17N_CCL_OUT3 (13L) -#define PINMUX_PB17N_CCL_OUT3 ((PIN_PB17N_CCL_OUT3 << 16) | MUX_PB17N_CCL_OUT3) -#define PORT_PB17N_CCL_OUT3 ((1UL) << 17) - -/* ========== PORT definition for DAC peripheral ========== */ -#define PIN_PA02B_DAC_VOUT0 (2L) -#define MUX_PA02B_DAC_VOUT0 (1L) -#define PINMUX_PA02B_DAC_VOUT0 ((PIN_PA02B_DAC_VOUT0 << 16) | MUX_PA02B_DAC_VOUT0) -#define PORT_PA02B_DAC_VOUT0 ((1UL) << 2) - -#define PIN_PA05B_DAC_VOUT1 (5L) -#define MUX_PA05B_DAC_VOUT1 (1L) -#define PINMUX_PA05B_DAC_VOUT1 ((PIN_PA05B_DAC_VOUT1 << 16) | MUX_PA05B_DAC_VOUT1) -#define PORT_PA05B_DAC_VOUT1 ((1UL) << 5) - -/* ========== PORT definition for EIC peripheral ========== */ -#define PIN_PA00A_EIC_EXTINT0 (0L) -#define MUX_PA00A_EIC_EXTINT0 (0L) -#define PINMUX_PA00A_EIC_EXTINT0 ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0) -#define PORT_PA00A_EIC_EXTINT0 ((1UL) << 0) -#define PIN_PA00A_EIC_EXTINT_NUM _L_(0) /**< EIC signal: PIN_PA00 External Interrupt Line */ - -#define PIN_PA16A_EIC_EXTINT0 (16L) -#define MUX_PA16A_EIC_EXTINT0 (0L) -#define PINMUX_PA16A_EIC_EXTINT0 ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0) -#define PORT_PA16A_EIC_EXTINT0 ((1UL) << 16) -#define PIN_PA16A_EIC_EXTINT_NUM _L_(0) /**< EIC signal: PIN_PA16 External Interrupt Line */ - -#define PIN_PB00A_EIC_EXTINT0 (32L) -#define MUX_PB00A_EIC_EXTINT0 (0L) -#define PINMUX_PB00A_EIC_EXTINT0 ((PIN_PB00A_EIC_EXTINT0 << 16) | MUX_PB00A_EIC_EXTINT0) -#define PORT_PB00A_EIC_EXTINT0 ((1UL) << 0) -#define PIN_PB00A_EIC_EXTINT_NUM _L_(0) /**< EIC signal: PIN_PB00 External Interrupt Line */ - -#define PIN_PB16A_EIC_EXTINT0 (48L) -#define MUX_PB16A_EIC_EXTINT0 (0L) -#define PINMUX_PB16A_EIC_EXTINT0 ((PIN_PB16A_EIC_EXTINT0 << 16) | MUX_PB16A_EIC_EXTINT0) -#define PORT_PB16A_EIC_EXTINT0 ((1UL) << 16) -#define PIN_PB16A_EIC_EXTINT_NUM _L_(0) /**< EIC signal: PIN_PB16 External Interrupt Line */ - -#define PIN_PC00A_EIC_EXTINT0 (64L) -#define MUX_PC00A_EIC_EXTINT0 (0L) -#define PINMUX_PC00A_EIC_EXTINT0 ((PIN_PC00A_EIC_EXTINT0 << 16) | MUX_PC00A_EIC_EXTINT0) -#define PORT_PC00A_EIC_EXTINT0 ((1UL) << 0) -#define PIN_PC00A_EIC_EXTINT_NUM _L_(0) /**< EIC signal: PIN_PC00 External Interrupt Line */ - -#define PIN_PC16A_EIC_EXTINT0 (80L) -#define MUX_PC16A_EIC_EXTINT0 (0L) -#define PINMUX_PC16A_EIC_EXTINT0 ((PIN_PC16A_EIC_EXTINT0 << 16) | MUX_PC16A_EIC_EXTINT0) -#define PORT_PC16A_EIC_EXTINT0 ((1UL) << 16) -#define PIN_PC16A_EIC_EXTINT_NUM _L_(0) /**< EIC signal: PIN_PC16 External Interrupt Line */ - -#define PIN_PD00A_EIC_EXTINT0 (96L) -#define MUX_PD00A_EIC_EXTINT0 (0L) -#define PINMUX_PD00A_EIC_EXTINT0 ((PIN_PD00A_EIC_EXTINT0 << 16) | MUX_PD00A_EIC_EXTINT0) -#define PORT_PD00A_EIC_EXTINT0 ((1UL) << 0) -#define PIN_PD00A_EIC_EXTINT_NUM _L_(0) /**< EIC signal: PIN_PD00 External Interrupt Line */ - -#define PIN_PA01A_EIC_EXTINT1 (1L) -#define MUX_PA01A_EIC_EXTINT1 (0L) -#define PINMUX_PA01A_EIC_EXTINT1 ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1) -#define PORT_PA01A_EIC_EXTINT1 ((1UL) << 1) -#define PIN_PA01A_EIC_EXTINT_NUM _L_(1) /**< EIC signal: PIN_PA01 External Interrupt Line */ - -#define PIN_PA17A_EIC_EXTINT1 (17L) -#define MUX_PA17A_EIC_EXTINT1 (0L) -#define PINMUX_PA17A_EIC_EXTINT1 ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1) -#define PORT_PA17A_EIC_EXTINT1 ((1UL) << 17) -#define PIN_PA17A_EIC_EXTINT_NUM _L_(1) /**< EIC signal: PIN_PA17 External Interrupt Line */ - -#define PIN_PB01A_EIC_EXTINT1 (33L) -#define MUX_PB01A_EIC_EXTINT1 (0L) -#define PINMUX_PB01A_EIC_EXTINT1 ((PIN_PB01A_EIC_EXTINT1 << 16) | MUX_PB01A_EIC_EXTINT1) -#define PORT_PB01A_EIC_EXTINT1 ((1UL) << 1) -#define PIN_PB01A_EIC_EXTINT_NUM _L_(1) /**< EIC signal: PIN_PB01 External Interrupt Line */ - -#define PIN_PB17A_EIC_EXTINT1 (49L) -#define MUX_PB17A_EIC_EXTINT1 (0L) -#define PINMUX_PB17A_EIC_EXTINT1 ((PIN_PB17A_EIC_EXTINT1 << 16) | MUX_PB17A_EIC_EXTINT1) -#define PORT_PB17A_EIC_EXTINT1 ((1UL) << 17) -#define PIN_PB17A_EIC_EXTINT_NUM _L_(1) /**< EIC signal: PIN_PB17 External Interrupt Line */ - -#define PIN_PC01A_EIC_EXTINT1 (65L) -#define MUX_PC01A_EIC_EXTINT1 (0L) -#define PINMUX_PC01A_EIC_EXTINT1 ((PIN_PC01A_EIC_EXTINT1 << 16) | MUX_PC01A_EIC_EXTINT1) -#define PORT_PC01A_EIC_EXTINT1 ((1UL) << 1) -#define PIN_PC01A_EIC_EXTINT_NUM _L_(1) /**< EIC signal: PIN_PC01 External Interrupt Line */ - -#define PIN_PC17A_EIC_EXTINT1 (81L) -#define MUX_PC17A_EIC_EXTINT1 (0L) -#define PINMUX_PC17A_EIC_EXTINT1 ((PIN_PC17A_EIC_EXTINT1 << 16) | MUX_PC17A_EIC_EXTINT1) -#define PORT_PC17A_EIC_EXTINT1 ((1UL) << 17) -#define PIN_PC17A_EIC_EXTINT_NUM _L_(1) /**< EIC signal: PIN_PC17 External Interrupt Line */ - -#define PIN_PD01A_EIC_EXTINT1 (97L) -#define MUX_PD01A_EIC_EXTINT1 (0L) -#define PINMUX_PD01A_EIC_EXTINT1 ((PIN_PD01A_EIC_EXTINT1 << 16) | MUX_PD01A_EIC_EXTINT1) -#define PORT_PD01A_EIC_EXTINT1 ((1UL) << 1) -#define PIN_PD01A_EIC_EXTINT_NUM _L_(1) /**< EIC signal: PIN_PD01 External Interrupt Line */ - -#define PIN_PA02A_EIC_EXTINT2 (2L) -#define MUX_PA02A_EIC_EXTINT2 (0L) -#define PINMUX_PA02A_EIC_EXTINT2 ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2) -#define PORT_PA02A_EIC_EXTINT2 ((1UL) << 2) -#define PIN_PA02A_EIC_EXTINT_NUM _L_(2) /**< EIC signal: PIN_PA02 External Interrupt Line */ - -#define PIN_PA18A_EIC_EXTINT2 (18L) -#define MUX_PA18A_EIC_EXTINT2 (0L) -#define PINMUX_PA18A_EIC_EXTINT2 ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2) -#define PORT_PA18A_EIC_EXTINT2 ((1UL) << 18) -#define PIN_PA18A_EIC_EXTINT_NUM _L_(2) /**< EIC signal: PIN_PA18 External Interrupt Line */ - -#define PIN_PB02A_EIC_EXTINT2 (34L) -#define MUX_PB02A_EIC_EXTINT2 (0L) -#define PINMUX_PB02A_EIC_EXTINT2 ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2) -#define PORT_PB02A_EIC_EXTINT2 ((1UL) << 2) -#define PIN_PB02A_EIC_EXTINT_NUM _L_(2) /**< EIC signal: PIN_PB02 External Interrupt Line */ - -#define PIN_PB18A_EIC_EXTINT2 (50L) -#define MUX_PB18A_EIC_EXTINT2 (0L) -#define PINMUX_PB18A_EIC_EXTINT2 ((PIN_PB18A_EIC_EXTINT2 << 16) | MUX_PB18A_EIC_EXTINT2) -#define PORT_PB18A_EIC_EXTINT2 ((1UL) << 18) -#define PIN_PB18A_EIC_EXTINT_NUM _L_(2) /**< EIC signal: PIN_PB18 External Interrupt Line */ - -#define PIN_PC02A_EIC_EXTINT2 (66L) -#define MUX_PC02A_EIC_EXTINT2 (0L) -#define PINMUX_PC02A_EIC_EXTINT2 ((PIN_PC02A_EIC_EXTINT2 << 16) | MUX_PC02A_EIC_EXTINT2) -#define PORT_PC02A_EIC_EXTINT2 ((1UL) << 2) -#define PIN_PC02A_EIC_EXTINT_NUM _L_(2) /**< EIC signal: PIN_PC02 External Interrupt Line */ - -#define PIN_PC18A_EIC_EXTINT2 (82L) -#define MUX_PC18A_EIC_EXTINT2 (0L) -#define PINMUX_PC18A_EIC_EXTINT2 ((PIN_PC18A_EIC_EXTINT2 << 16) | MUX_PC18A_EIC_EXTINT2) -#define PORT_PC18A_EIC_EXTINT2 ((1UL) << 18) -#define PIN_PC18A_EIC_EXTINT_NUM _L_(2) /**< EIC signal: PIN_PC18 External Interrupt Line */ - -#define PIN_PA03A_EIC_EXTINT3 (3L) -#define MUX_PA03A_EIC_EXTINT3 (0L) -#define PINMUX_PA03A_EIC_EXTINT3 ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3) -#define PORT_PA03A_EIC_EXTINT3 ((1UL) << 3) -#define PIN_PA03A_EIC_EXTINT_NUM _L_(3) /**< EIC signal: PIN_PA03 External Interrupt Line */ - -#define PIN_PA19A_EIC_EXTINT3 (19L) -#define MUX_PA19A_EIC_EXTINT3 (0L) -#define PINMUX_PA19A_EIC_EXTINT3 ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3) -#define PORT_PA19A_EIC_EXTINT3 ((1UL) << 19) -#define PIN_PA19A_EIC_EXTINT_NUM _L_(3) /**< EIC signal: PIN_PA19 External Interrupt Line */ - -#define PIN_PB03A_EIC_EXTINT3 (35L) -#define MUX_PB03A_EIC_EXTINT3 (0L) -#define PINMUX_PB03A_EIC_EXTINT3 ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3) -#define PORT_PB03A_EIC_EXTINT3 ((1UL) << 3) -#define PIN_PB03A_EIC_EXTINT_NUM _L_(3) /**< EIC signal: PIN_PB03 External Interrupt Line */ - -#define PIN_PB19A_EIC_EXTINT3 (51L) -#define MUX_PB19A_EIC_EXTINT3 (0L) -#define PINMUX_PB19A_EIC_EXTINT3 ((PIN_PB19A_EIC_EXTINT3 << 16) | MUX_PB19A_EIC_EXTINT3) -#define PORT_PB19A_EIC_EXTINT3 ((1UL) << 19) -#define PIN_PB19A_EIC_EXTINT_NUM _L_(3) /**< EIC signal: PIN_PB19 External Interrupt Line */ - -#define PIN_PC03A_EIC_EXTINT3 (67L) -#define MUX_PC03A_EIC_EXTINT3 (0L) -#define PINMUX_PC03A_EIC_EXTINT3 ((PIN_PC03A_EIC_EXTINT3 << 16) | MUX_PC03A_EIC_EXTINT3) -#define PORT_PC03A_EIC_EXTINT3 ((1UL) << 3) -#define PIN_PC03A_EIC_EXTINT_NUM _L_(3) /**< EIC signal: PIN_PC03 External Interrupt Line */ - -#define PIN_PC19A_EIC_EXTINT3 (83L) -#define MUX_PC19A_EIC_EXTINT3 (0L) -#define PINMUX_PC19A_EIC_EXTINT3 ((PIN_PC19A_EIC_EXTINT3 << 16) | MUX_PC19A_EIC_EXTINT3) -#define PORT_PC19A_EIC_EXTINT3 ((1UL) << 19) -#define PIN_PC19A_EIC_EXTINT_NUM _L_(3) /**< EIC signal: PIN_PC19 External Interrupt Line */ - -#define PIN_PD08A_EIC_EXTINT3 (104L) -#define MUX_PD08A_EIC_EXTINT3 (0L) -#define PINMUX_PD08A_EIC_EXTINT3 ((PIN_PD08A_EIC_EXTINT3 << 16) | MUX_PD08A_EIC_EXTINT3) -#define PORT_PD08A_EIC_EXTINT3 ((1UL) << 8) -#define PIN_PD08A_EIC_EXTINT_NUM _L_(3) /**< EIC signal: PIN_PD08 External Interrupt Line */ - -#define PIN_PA04A_EIC_EXTINT4 (4L) -#define MUX_PA04A_EIC_EXTINT4 (0L) -#define PINMUX_PA04A_EIC_EXTINT4 ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4) -#define PORT_PA04A_EIC_EXTINT4 ((1UL) << 4) -#define PIN_PA04A_EIC_EXTINT_NUM _L_(4) /**< EIC signal: PIN_PA04 External Interrupt Line */ - -#define PIN_PA20A_EIC_EXTINT4 (20L) -#define MUX_PA20A_EIC_EXTINT4 (0L) -#define PINMUX_PA20A_EIC_EXTINT4 ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4) -#define PORT_PA20A_EIC_EXTINT4 ((1UL) << 20) -#define PIN_PA20A_EIC_EXTINT_NUM _L_(4) /**< EIC signal: PIN_PA20 External Interrupt Line */ - -#define PIN_PB04A_EIC_EXTINT4 (36L) -#define MUX_PB04A_EIC_EXTINT4 (0L) -#define PINMUX_PB04A_EIC_EXTINT4 ((PIN_PB04A_EIC_EXTINT4 << 16) | MUX_PB04A_EIC_EXTINT4) -#define PORT_PB04A_EIC_EXTINT4 ((1UL) << 4) -#define PIN_PB04A_EIC_EXTINT_NUM _L_(4) /**< EIC signal: PIN_PB04 External Interrupt Line */ - -#define PIN_PB20A_EIC_EXTINT4 (52L) -#define MUX_PB20A_EIC_EXTINT4 (0L) -#define PINMUX_PB20A_EIC_EXTINT4 ((PIN_PB20A_EIC_EXTINT4 << 16) | MUX_PB20A_EIC_EXTINT4) -#define PORT_PB20A_EIC_EXTINT4 ((1UL) << 20) -#define PIN_PB20A_EIC_EXTINT_NUM _L_(4) /**< EIC signal: PIN_PB20 External Interrupt Line */ - -#define PIN_PC04A_EIC_EXTINT4 (68L) -#define MUX_PC04A_EIC_EXTINT4 (0L) -#define PINMUX_PC04A_EIC_EXTINT4 ((PIN_PC04A_EIC_EXTINT4 << 16) | MUX_PC04A_EIC_EXTINT4) -#define PORT_PC04A_EIC_EXTINT4 ((1UL) << 4) -#define PIN_PC04A_EIC_EXTINT_NUM _L_(4) /**< EIC signal: PIN_PC04 External Interrupt Line */ - -#define PIN_PC20A_EIC_EXTINT4 (84L) -#define MUX_PC20A_EIC_EXTINT4 (0L) -#define PINMUX_PC20A_EIC_EXTINT4 ((PIN_PC20A_EIC_EXTINT4 << 16) | MUX_PC20A_EIC_EXTINT4) -#define PORT_PC20A_EIC_EXTINT4 ((1UL) << 20) -#define PIN_PC20A_EIC_EXTINT_NUM _L_(4) /**< EIC signal: PIN_PC20 External Interrupt Line */ - -#define PIN_PD09A_EIC_EXTINT4 (105L) -#define MUX_PD09A_EIC_EXTINT4 (0L) -#define PINMUX_PD09A_EIC_EXTINT4 ((PIN_PD09A_EIC_EXTINT4 << 16) | MUX_PD09A_EIC_EXTINT4) -#define PORT_PD09A_EIC_EXTINT4 ((1UL) << 9) -#define PIN_PD09A_EIC_EXTINT_NUM _L_(4) /**< EIC signal: PIN_PD09 External Interrupt Line */ - -#define PIN_PA05A_EIC_EXTINT5 (5L) -#define MUX_PA05A_EIC_EXTINT5 (0L) -#define PINMUX_PA05A_EIC_EXTINT5 ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5) -#define PORT_PA05A_EIC_EXTINT5 ((1UL) << 5) -#define PIN_PA05A_EIC_EXTINT_NUM _L_(5) /**< EIC signal: PIN_PA05 External Interrupt Line */ - -#define PIN_PA21A_EIC_EXTINT5 (21L) -#define MUX_PA21A_EIC_EXTINT5 (0L) -#define PINMUX_PA21A_EIC_EXTINT5 ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5) -#define PORT_PA21A_EIC_EXTINT5 ((1UL) << 21) -#define PIN_PA21A_EIC_EXTINT_NUM _L_(5) /**< EIC signal: PIN_PA21 External Interrupt Line */ - -#define PIN_PB05A_EIC_EXTINT5 (37L) -#define MUX_PB05A_EIC_EXTINT5 (0L) -#define PINMUX_PB05A_EIC_EXTINT5 ((PIN_PB05A_EIC_EXTINT5 << 16) | MUX_PB05A_EIC_EXTINT5) -#define PORT_PB05A_EIC_EXTINT5 ((1UL) << 5) -#define PIN_PB05A_EIC_EXTINT_NUM _L_(5) /**< EIC signal: PIN_PB05 External Interrupt Line */ - -#define PIN_PB21A_EIC_EXTINT5 (53L) -#define MUX_PB21A_EIC_EXTINT5 (0L) -#define PINMUX_PB21A_EIC_EXTINT5 ((PIN_PB21A_EIC_EXTINT5 << 16) | MUX_PB21A_EIC_EXTINT5) -#define PORT_PB21A_EIC_EXTINT5 ((1UL) << 21) -#define PIN_PB21A_EIC_EXTINT_NUM _L_(5) /**< EIC signal: PIN_PB21 External Interrupt Line */ - -#define PIN_PC05A_EIC_EXTINT5 (69L) -#define MUX_PC05A_EIC_EXTINT5 (0L) -#define PINMUX_PC05A_EIC_EXTINT5 ((PIN_PC05A_EIC_EXTINT5 << 16) | MUX_PC05A_EIC_EXTINT5) -#define PORT_PC05A_EIC_EXTINT5 ((1UL) << 5) -#define PIN_PC05A_EIC_EXTINT_NUM _L_(5) /**< EIC signal: PIN_PC05 External Interrupt Line */ - -#define PIN_PC21A_EIC_EXTINT5 (85L) -#define MUX_PC21A_EIC_EXTINT5 (0L) -#define PINMUX_PC21A_EIC_EXTINT5 ((PIN_PC21A_EIC_EXTINT5 << 16) | MUX_PC21A_EIC_EXTINT5) -#define PORT_PC21A_EIC_EXTINT5 ((1UL) << 21) -#define PIN_PC21A_EIC_EXTINT_NUM _L_(5) /**< EIC signal: PIN_PC21 External Interrupt Line */ - -#define PIN_PD10A_EIC_EXTINT5 (106L) -#define MUX_PD10A_EIC_EXTINT5 (0L) -#define PINMUX_PD10A_EIC_EXTINT5 ((PIN_PD10A_EIC_EXTINT5 << 16) | MUX_PD10A_EIC_EXTINT5) -#define PORT_PD10A_EIC_EXTINT5 ((1UL) << 10) -#define PIN_PD10A_EIC_EXTINT_NUM _L_(5) /**< EIC signal: PIN_PD10 External Interrupt Line */ - -#define PIN_PA06A_EIC_EXTINT6 (6L) -#define MUX_PA06A_EIC_EXTINT6 (0L) -#define PINMUX_PA06A_EIC_EXTINT6 ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6) -#define PORT_PA06A_EIC_EXTINT6 ((1UL) << 6) -#define PIN_PA06A_EIC_EXTINT_NUM _L_(6) /**< EIC signal: PIN_PA06 External Interrupt Line */ - -#define PIN_PA22A_EIC_EXTINT6 (22L) -#define MUX_PA22A_EIC_EXTINT6 (0L) -#define PINMUX_PA22A_EIC_EXTINT6 ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6) -#define PORT_PA22A_EIC_EXTINT6 ((1UL) << 22) -#define PIN_PA22A_EIC_EXTINT_NUM _L_(6) /**< EIC signal: PIN_PA22 External Interrupt Line */ - -#define PIN_PB06A_EIC_EXTINT6 (38L) -#define MUX_PB06A_EIC_EXTINT6 (0L) -#define PINMUX_PB06A_EIC_EXTINT6 ((PIN_PB06A_EIC_EXTINT6 << 16) | MUX_PB06A_EIC_EXTINT6) -#define PORT_PB06A_EIC_EXTINT6 ((1UL) << 6) -#define PIN_PB06A_EIC_EXTINT_NUM _L_(6) /**< EIC signal: PIN_PB06 External Interrupt Line */ - -#define PIN_PB22A_EIC_EXTINT6 (54L) -#define MUX_PB22A_EIC_EXTINT6 (0L) -#define PINMUX_PB22A_EIC_EXTINT6 ((PIN_PB22A_EIC_EXTINT6 << 16) | MUX_PB22A_EIC_EXTINT6) -#define PORT_PB22A_EIC_EXTINT6 ((1UL) << 22) -#define PIN_PB22A_EIC_EXTINT_NUM _L_(6) /**< EIC signal: PIN_PB22 External Interrupt Line */ - -#define PIN_PC06A_EIC_EXTINT6 (70L) -#define MUX_PC06A_EIC_EXTINT6 (0L) -#define PINMUX_PC06A_EIC_EXTINT6 ((PIN_PC06A_EIC_EXTINT6 << 16) | MUX_PC06A_EIC_EXTINT6) -#define PORT_PC06A_EIC_EXTINT6 ((1UL) << 6) -#define PIN_PC06A_EIC_EXTINT_NUM _L_(6) /**< EIC signal: PIN_PC06 External Interrupt Line */ - -#define PIN_PC22A_EIC_EXTINT6 (86L) -#define MUX_PC22A_EIC_EXTINT6 (0L) -#define PINMUX_PC22A_EIC_EXTINT6 ((PIN_PC22A_EIC_EXTINT6 << 16) | MUX_PC22A_EIC_EXTINT6) -#define PORT_PC22A_EIC_EXTINT6 ((1UL) << 22) -#define PIN_PC22A_EIC_EXTINT_NUM _L_(6) /**< EIC signal: PIN_PC22 External Interrupt Line */ - -#define PIN_PD11A_EIC_EXTINT6 (107L) -#define MUX_PD11A_EIC_EXTINT6 (0L) -#define PINMUX_PD11A_EIC_EXTINT6 ((PIN_PD11A_EIC_EXTINT6 << 16) | MUX_PD11A_EIC_EXTINT6) -#define PORT_PD11A_EIC_EXTINT6 ((1UL) << 11) -#define PIN_PD11A_EIC_EXTINT_NUM _L_(6) /**< EIC signal: PIN_PD11 External Interrupt Line */ - -#define PIN_PA07A_EIC_EXTINT7 (7L) -#define MUX_PA07A_EIC_EXTINT7 (0L) -#define PINMUX_PA07A_EIC_EXTINT7 ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7) -#define PORT_PA07A_EIC_EXTINT7 ((1UL) << 7) -#define PIN_PA07A_EIC_EXTINT_NUM _L_(7) /**< EIC signal: PIN_PA07 External Interrupt Line */ - -#define PIN_PA23A_EIC_EXTINT7 (23L) -#define MUX_PA23A_EIC_EXTINT7 (0L) -#define PINMUX_PA23A_EIC_EXTINT7 ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7) -#define PORT_PA23A_EIC_EXTINT7 ((1UL) << 23) -#define PIN_PA23A_EIC_EXTINT_NUM _L_(7) /**< EIC signal: PIN_PA23 External Interrupt Line */ - -#define PIN_PB07A_EIC_EXTINT7 (39L) -#define MUX_PB07A_EIC_EXTINT7 (0L) -#define PINMUX_PB07A_EIC_EXTINT7 ((PIN_PB07A_EIC_EXTINT7 << 16) | MUX_PB07A_EIC_EXTINT7) -#define PORT_PB07A_EIC_EXTINT7 ((1UL) << 7) -#define PIN_PB07A_EIC_EXTINT_NUM _L_(7) /**< EIC signal: PIN_PB07 External Interrupt Line */ - -#define PIN_PB23A_EIC_EXTINT7 (55L) -#define MUX_PB23A_EIC_EXTINT7 (0L) -#define PINMUX_PB23A_EIC_EXTINT7 ((PIN_PB23A_EIC_EXTINT7 << 16) | MUX_PB23A_EIC_EXTINT7) -#define PORT_PB23A_EIC_EXTINT7 ((1UL) << 23) -#define PIN_PB23A_EIC_EXTINT_NUM _L_(7) /**< EIC signal: PIN_PB23 External Interrupt Line */ - -#define PIN_PC23A_EIC_EXTINT7 (87L) -#define MUX_PC23A_EIC_EXTINT7 (0L) -#define PINMUX_PC23A_EIC_EXTINT7 ((PIN_PC23A_EIC_EXTINT7 << 16) | MUX_PC23A_EIC_EXTINT7) -#define PORT_PC23A_EIC_EXTINT7 ((1UL) << 23) -#define PIN_PC23A_EIC_EXTINT_NUM _L_(7) /**< EIC signal: PIN_PC23 External Interrupt Line */ - -#define PIN_PD12A_EIC_EXTINT7 (108L) -#define MUX_PD12A_EIC_EXTINT7 (0L) -#define PINMUX_PD12A_EIC_EXTINT7 ((PIN_PD12A_EIC_EXTINT7 << 16) | MUX_PD12A_EIC_EXTINT7) -#define PORT_PD12A_EIC_EXTINT7 ((1UL) << 12) -#define PIN_PD12A_EIC_EXTINT_NUM _L_(7) /**< EIC signal: PIN_PD12 External Interrupt Line */ - -#define PIN_PA24A_EIC_EXTINT8 (24L) -#define MUX_PA24A_EIC_EXTINT8 (0L) -#define PINMUX_PA24A_EIC_EXTINT8 ((PIN_PA24A_EIC_EXTINT8 << 16) | MUX_PA24A_EIC_EXTINT8) -#define PORT_PA24A_EIC_EXTINT8 ((1UL) << 24) -#define PIN_PA24A_EIC_EXTINT_NUM _L_(8) /**< EIC signal: PIN_PA24 External Interrupt Line */ - -#define PIN_PB08A_EIC_EXTINT8 (40L) -#define MUX_PB08A_EIC_EXTINT8 (0L) -#define PINMUX_PB08A_EIC_EXTINT8 ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8) -#define PORT_PB08A_EIC_EXTINT8 ((1UL) << 8) -#define PIN_PB08A_EIC_EXTINT_NUM _L_(8) /**< EIC signal: PIN_PB08 External Interrupt Line */ - -#define PIN_PB24A_EIC_EXTINT8 (56L) -#define MUX_PB24A_EIC_EXTINT8 (0L) -#define PINMUX_PB24A_EIC_EXTINT8 ((PIN_PB24A_EIC_EXTINT8 << 16) | MUX_PB24A_EIC_EXTINT8) -#define PORT_PB24A_EIC_EXTINT8 ((1UL) << 24) -#define PIN_PB24A_EIC_EXTINT_NUM _L_(8) /**< EIC signal: PIN_PB24 External Interrupt Line */ - -#define PIN_PC24A_EIC_EXTINT8 (88L) -#define MUX_PC24A_EIC_EXTINT8 (0L) -#define PINMUX_PC24A_EIC_EXTINT8 ((PIN_PC24A_EIC_EXTINT8 << 16) | MUX_PC24A_EIC_EXTINT8) -#define PORT_PC24A_EIC_EXTINT8 ((1UL) << 24) -#define PIN_PC24A_EIC_EXTINT_NUM _L_(8) /**< EIC signal: PIN_PC24 External Interrupt Line */ - -#define PIN_PA09A_EIC_EXTINT9 (9L) -#define MUX_PA09A_EIC_EXTINT9 (0L) -#define PINMUX_PA09A_EIC_EXTINT9 ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9) -#define PORT_PA09A_EIC_EXTINT9 ((1UL) << 9) -#define PIN_PA09A_EIC_EXTINT_NUM _L_(9) /**< EIC signal: PIN_PA09 External Interrupt Line */ - -#define PIN_PA25A_EIC_EXTINT9 (25L) -#define MUX_PA25A_EIC_EXTINT9 (0L) -#define PINMUX_PA25A_EIC_EXTINT9 ((PIN_PA25A_EIC_EXTINT9 << 16) | MUX_PA25A_EIC_EXTINT9) -#define PORT_PA25A_EIC_EXTINT9 ((1UL) << 25) -#define PIN_PA25A_EIC_EXTINT_NUM _L_(9) /**< EIC signal: PIN_PA25 External Interrupt Line */ - -#define PIN_PB09A_EIC_EXTINT9 (41L) -#define MUX_PB09A_EIC_EXTINT9 (0L) -#define PINMUX_PB09A_EIC_EXTINT9 ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9) -#define PORT_PB09A_EIC_EXTINT9 ((1UL) << 9) -#define PIN_PB09A_EIC_EXTINT_NUM _L_(9) /**< EIC signal: PIN_PB09 External Interrupt Line */ - -#define PIN_PB25A_EIC_EXTINT9 (57L) -#define MUX_PB25A_EIC_EXTINT9 (0L) -#define PINMUX_PB25A_EIC_EXTINT9 ((PIN_PB25A_EIC_EXTINT9 << 16) | MUX_PB25A_EIC_EXTINT9) -#define PORT_PB25A_EIC_EXTINT9 ((1UL) << 25) -#define PIN_PB25A_EIC_EXTINT_NUM _L_(9) /**< EIC signal: PIN_PB25 External Interrupt Line */ - -#define PIN_PC07A_EIC_EXTINT9 (71L) -#define MUX_PC07A_EIC_EXTINT9 (0L) -#define PINMUX_PC07A_EIC_EXTINT9 ((PIN_PC07A_EIC_EXTINT9 << 16) | MUX_PC07A_EIC_EXTINT9) -#define PORT_PC07A_EIC_EXTINT9 ((1UL) << 7) -#define PIN_PC07A_EIC_EXTINT_NUM _L_(9) /**< EIC signal: PIN_PC07 External Interrupt Line */ - -#define PIN_PC25A_EIC_EXTINT9 (89L) -#define MUX_PC25A_EIC_EXTINT9 (0L) -#define PINMUX_PC25A_EIC_EXTINT9 ((PIN_PC25A_EIC_EXTINT9 << 16) | MUX_PC25A_EIC_EXTINT9) -#define PORT_PC25A_EIC_EXTINT9 ((1UL) << 25) -#define PIN_PC25A_EIC_EXTINT_NUM _L_(9) /**< EIC signal: PIN_PC25 External Interrupt Line */ - -#define PIN_PA10A_EIC_EXTINT10 (10L) -#define MUX_PA10A_EIC_EXTINT10 (0L) -#define PINMUX_PA10A_EIC_EXTINT10 ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10) -#define PORT_PA10A_EIC_EXTINT10 ((1UL) << 10) -#define PIN_PA10A_EIC_EXTINT_NUM _L_(10) /**< EIC signal: PIN_PA10 External Interrupt Line */ - -#define PIN_PB10A_EIC_EXTINT10 (42L) -#define MUX_PB10A_EIC_EXTINT10 (0L) -#define PINMUX_PB10A_EIC_EXTINT10 ((PIN_PB10A_EIC_EXTINT10 << 16) | MUX_PB10A_EIC_EXTINT10) -#define PORT_PB10A_EIC_EXTINT10 ((1UL) << 10) -#define PIN_PB10A_EIC_EXTINT_NUM _L_(10) /**< EIC signal: PIN_PB10 External Interrupt Line */ - -#define PIN_PC10A_EIC_EXTINT10 (74L) -#define MUX_PC10A_EIC_EXTINT10 (0L) -#define PINMUX_PC10A_EIC_EXTINT10 ((PIN_PC10A_EIC_EXTINT10 << 16) | MUX_PC10A_EIC_EXTINT10) -#define PORT_PC10A_EIC_EXTINT10 ((1UL) << 10) -#define PIN_PC10A_EIC_EXTINT_NUM _L_(10) /**< EIC signal: PIN_PC10 External Interrupt Line */ - -#define PIN_PC26A_EIC_EXTINT10 (90L) -#define MUX_PC26A_EIC_EXTINT10 (0L) -#define PINMUX_PC26A_EIC_EXTINT10 ((PIN_PC26A_EIC_EXTINT10 << 16) | MUX_PC26A_EIC_EXTINT10) -#define PORT_PC26A_EIC_EXTINT10 ((1UL) << 26) -#define PIN_PC26A_EIC_EXTINT_NUM _L_(10) /**< EIC signal: PIN_PC26 External Interrupt Line */ - -#define PIN_PD20A_EIC_EXTINT10 (116L) -#define MUX_PD20A_EIC_EXTINT10 (0L) -#define PINMUX_PD20A_EIC_EXTINT10 ((PIN_PD20A_EIC_EXTINT10 << 16) | MUX_PD20A_EIC_EXTINT10) -#define PORT_PD20A_EIC_EXTINT10 ((1UL) << 20) -#define PIN_PD20A_EIC_EXTINT_NUM _L_(10) /**< EIC signal: PIN_PD20 External Interrupt Line */ - -#define PIN_PA11A_EIC_EXTINT11 (11L) -#define MUX_PA11A_EIC_EXTINT11 (0L) -#define PINMUX_PA11A_EIC_EXTINT11 ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11) -#define PORT_PA11A_EIC_EXTINT11 ((1UL) << 11) -#define PIN_PA11A_EIC_EXTINT_NUM _L_(11) /**< EIC signal: PIN_PA11 External Interrupt Line */ - -#define PIN_PA27A_EIC_EXTINT11 (27L) -#define MUX_PA27A_EIC_EXTINT11 (0L) -#define PINMUX_PA27A_EIC_EXTINT11 ((PIN_PA27A_EIC_EXTINT11 << 16) | MUX_PA27A_EIC_EXTINT11) -#define PORT_PA27A_EIC_EXTINT11 ((1UL) << 27) -#define PIN_PA27A_EIC_EXTINT_NUM _L_(11) /**< EIC signal: PIN_PA27 External Interrupt Line */ - -#define PIN_PB11A_EIC_EXTINT11 (43L) -#define MUX_PB11A_EIC_EXTINT11 (0L) -#define PINMUX_PB11A_EIC_EXTINT11 ((PIN_PB11A_EIC_EXTINT11 << 16) | MUX_PB11A_EIC_EXTINT11) -#define PORT_PB11A_EIC_EXTINT11 ((1UL) << 11) -#define PIN_PB11A_EIC_EXTINT_NUM _L_(11) /**< EIC signal: PIN_PB11 External Interrupt Line */ - -#define PIN_PC11A_EIC_EXTINT11 (75L) -#define MUX_PC11A_EIC_EXTINT11 (0L) -#define PINMUX_PC11A_EIC_EXTINT11 ((PIN_PC11A_EIC_EXTINT11 << 16) | MUX_PC11A_EIC_EXTINT11) -#define PORT_PC11A_EIC_EXTINT11 ((1UL) << 11) -#define PIN_PC11A_EIC_EXTINT_NUM _L_(11) /**< EIC signal: PIN_PC11 External Interrupt Line */ - -#define PIN_PC27A_EIC_EXTINT11 (91L) -#define MUX_PC27A_EIC_EXTINT11 (0L) -#define PINMUX_PC27A_EIC_EXTINT11 ((PIN_PC27A_EIC_EXTINT11 << 16) | MUX_PC27A_EIC_EXTINT11) -#define PORT_PC27A_EIC_EXTINT11 ((1UL) << 27) -#define PIN_PC27A_EIC_EXTINT_NUM _L_(11) /**< EIC signal: PIN_PC27 External Interrupt Line */ - -#define PIN_PD21A_EIC_EXTINT11 (117L) -#define MUX_PD21A_EIC_EXTINT11 (0L) -#define PINMUX_PD21A_EIC_EXTINT11 ((PIN_PD21A_EIC_EXTINT11 << 16) | MUX_PD21A_EIC_EXTINT11) -#define PORT_PD21A_EIC_EXTINT11 ((1UL) << 21) -#define PIN_PD21A_EIC_EXTINT_NUM _L_(11) /**< EIC signal: PIN_PD21 External Interrupt Line */ - -#define PIN_PA12A_EIC_EXTINT12 (12L) -#define MUX_PA12A_EIC_EXTINT12 (0L) -#define PINMUX_PA12A_EIC_EXTINT12 ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12) -#define PORT_PA12A_EIC_EXTINT12 ((1UL) << 12) -#define PIN_PA12A_EIC_EXTINT_NUM _L_(12) /**< EIC signal: PIN_PA12 External Interrupt Line */ - -#define PIN_PB12A_EIC_EXTINT12 (44L) -#define MUX_PB12A_EIC_EXTINT12 (0L) -#define PINMUX_PB12A_EIC_EXTINT12 ((PIN_PB12A_EIC_EXTINT12 << 16) | MUX_PB12A_EIC_EXTINT12) -#define PORT_PB12A_EIC_EXTINT12 ((1UL) << 12) -#define PIN_PB12A_EIC_EXTINT_NUM _L_(12) /**< EIC signal: PIN_PB12 External Interrupt Line */ - -#define PIN_PB26A_EIC_EXTINT12 (58L) -#define MUX_PB26A_EIC_EXTINT12 (0L) -#define PINMUX_PB26A_EIC_EXTINT12 ((PIN_PB26A_EIC_EXTINT12 << 16) | MUX_PB26A_EIC_EXTINT12) -#define PORT_PB26A_EIC_EXTINT12 ((1UL) << 26) -#define PIN_PB26A_EIC_EXTINT_NUM _L_(12) /**< EIC signal: PIN_PB26 External Interrupt Line */ - -#define PIN_PC12A_EIC_EXTINT12 (76L) -#define MUX_PC12A_EIC_EXTINT12 (0L) -#define PINMUX_PC12A_EIC_EXTINT12 ((PIN_PC12A_EIC_EXTINT12 << 16) | MUX_PC12A_EIC_EXTINT12) -#define PORT_PC12A_EIC_EXTINT12 ((1UL) << 12) -#define PIN_PC12A_EIC_EXTINT_NUM _L_(12) /**< EIC signal: PIN_PC12 External Interrupt Line */ - -#define PIN_PC28A_EIC_EXTINT12 (92L) -#define MUX_PC28A_EIC_EXTINT12 (0L) -#define PINMUX_PC28A_EIC_EXTINT12 ((PIN_PC28A_EIC_EXTINT12 << 16) | MUX_PC28A_EIC_EXTINT12) -#define PORT_PC28A_EIC_EXTINT12 ((1UL) << 28) -#define PIN_PC28A_EIC_EXTINT_NUM _L_(12) /**< EIC signal: PIN_PC28 External Interrupt Line */ - -#define PIN_PA13A_EIC_EXTINT13 (13L) -#define MUX_PA13A_EIC_EXTINT13 (0L) -#define PINMUX_PA13A_EIC_EXTINT13 ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13) -#define PORT_PA13A_EIC_EXTINT13 ((1UL) << 13) -#define PIN_PA13A_EIC_EXTINT_NUM _L_(13) /**< EIC signal: PIN_PA13 External Interrupt Line */ - -#define PIN_PB13A_EIC_EXTINT13 (45L) -#define MUX_PB13A_EIC_EXTINT13 (0L) -#define PINMUX_PB13A_EIC_EXTINT13 ((PIN_PB13A_EIC_EXTINT13 << 16) | MUX_PB13A_EIC_EXTINT13) -#define PORT_PB13A_EIC_EXTINT13 ((1UL) << 13) -#define PIN_PB13A_EIC_EXTINT_NUM _L_(13) /**< EIC signal: PIN_PB13 External Interrupt Line */ - -#define PIN_PB27A_EIC_EXTINT13 (59L) -#define MUX_PB27A_EIC_EXTINT13 (0L) -#define PINMUX_PB27A_EIC_EXTINT13 ((PIN_PB27A_EIC_EXTINT13 << 16) | MUX_PB27A_EIC_EXTINT13) -#define PORT_PB27A_EIC_EXTINT13 ((1UL) << 27) -#define PIN_PB27A_EIC_EXTINT_NUM _L_(13) /**< EIC signal: PIN_PB27 External Interrupt Line */ - -#define PIN_PC13A_EIC_EXTINT13 (77L) -#define MUX_PC13A_EIC_EXTINT13 (0L) -#define PINMUX_PC13A_EIC_EXTINT13 ((PIN_PC13A_EIC_EXTINT13 << 16) | MUX_PC13A_EIC_EXTINT13) -#define PORT_PC13A_EIC_EXTINT13 ((1UL) << 13) -#define PIN_PC13A_EIC_EXTINT_NUM _L_(13) /**< EIC signal: PIN_PC13 External Interrupt Line */ - -#define PIN_PA30A_EIC_EXTINT14 (30L) -#define MUX_PA30A_EIC_EXTINT14 (0L) -#define PINMUX_PA30A_EIC_EXTINT14 ((PIN_PA30A_EIC_EXTINT14 << 16) | MUX_PA30A_EIC_EXTINT14) -#define PORT_PA30A_EIC_EXTINT14 ((1UL) << 30) -#define PIN_PA30A_EIC_EXTINT_NUM _L_(14) /**< EIC signal: PIN_PA30 External Interrupt Line */ - -#define PIN_PB14A_EIC_EXTINT14 (46L) -#define MUX_PB14A_EIC_EXTINT14 (0L) -#define PINMUX_PB14A_EIC_EXTINT14 ((PIN_PB14A_EIC_EXTINT14 << 16) | MUX_PB14A_EIC_EXTINT14) -#define PORT_PB14A_EIC_EXTINT14 ((1UL) << 14) -#define PIN_PB14A_EIC_EXTINT_NUM _L_(14) /**< EIC signal: PIN_PB14 External Interrupt Line */ - -#define PIN_PB28A_EIC_EXTINT14 (60L) -#define MUX_PB28A_EIC_EXTINT14 (0L) -#define PINMUX_PB28A_EIC_EXTINT14 ((PIN_PB28A_EIC_EXTINT14 << 16) | MUX_PB28A_EIC_EXTINT14) -#define PORT_PB28A_EIC_EXTINT14 ((1UL) << 28) -#define PIN_PB28A_EIC_EXTINT_NUM _L_(14) /**< EIC signal: PIN_PB28 External Interrupt Line */ - -#define PIN_PB30A_EIC_EXTINT14 (62L) -#define MUX_PB30A_EIC_EXTINT14 (0L) -#define PINMUX_PB30A_EIC_EXTINT14 ((PIN_PB30A_EIC_EXTINT14 << 16) | MUX_PB30A_EIC_EXTINT14) -#define PORT_PB30A_EIC_EXTINT14 ((1UL) << 30) -#define PIN_PB30A_EIC_EXTINT_NUM _L_(14) /**< EIC signal: PIN_PB30 External Interrupt Line */ - -#define PIN_PC14A_EIC_EXTINT14 (78L) -#define MUX_PC14A_EIC_EXTINT14 (0L) -#define PINMUX_PC14A_EIC_EXTINT14 ((PIN_PC14A_EIC_EXTINT14 << 16) | MUX_PC14A_EIC_EXTINT14) -#define PORT_PC14A_EIC_EXTINT14 ((1UL) << 14) -#define PIN_PC14A_EIC_EXTINT_NUM _L_(14) /**< EIC signal: PIN_PC14 External Interrupt Line */ - -#define PIN_PC30A_EIC_EXTINT14 (94L) -#define MUX_PC30A_EIC_EXTINT14 (0L) -#define PINMUX_PC30A_EIC_EXTINT14 ((PIN_PC30A_EIC_EXTINT14 << 16) | MUX_PC30A_EIC_EXTINT14) -#define PORT_PC30A_EIC_EXTINT14 ((1UL) << 30) -#define PIN_PC30A_EIC_EXTINT_NUM _L_(14) /**< EIC signal: PIN_PC30 External Interrupt Line */ - -#define PIN_PA14A_EIC_EXTINT14 (14L) -#define MUX_PA14A_EIC_EXTINT14 (0L) -#define PINMUX_PA14A_EIC_EXTINT14 ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14) -#define PORT_PA14A_EIC_EXTINT14 ((1UL) << 14) -#define PIN_PA14A_EIC_EXTINT_NUM _L_(14) /**< EIC signal: PIN_PA14 External Interrupt Line */ - -#define PIN_PA15A_EIC_EXTINT15 (15L) -#define MUX_PA15A_EIC_EXTINT15 (0L) -#define PINMUX_PA15A_EIC_EXTINT15 ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15) -#define PORT_PA15A_EIC_EXTINT15 ((1UL) << 15) -#define PIN_PA15A_EIC_EXTINT_NUM _L_(15) /**< EIC signal: PIN_PA15 External Interrupt Line */ - -#define PIN_PA31A_EIC_EXTINT15 (31L) -#define MUX_PA31A_EIC_EXTINT15 (0L) -#define PINMUX_PA31A_EIC_EXTINT15 ((PIN_PA31A_EIC_EXTINT15 << 16) | MUX_PA31A_EIC_EXTINT15) -#define PORT_PA31A_EIC_EXTINT15 ((1UL) << 31) -#define PIN_PA31A_EIC_EXTINT_NUM _L_(15) /**< EIC signal: PIN_PA31 External Interrupt Line */ - -#define PIN_PB15A_EIC_EXTINT15 (47L) -#define MUX_PB15A_EIC_EXTINT15 (0L) -#define PINMUX_PB15A_EIC_EXTINT15 ((PIN_PB15A_EIC_EXTINT15 << 16) | MUX_PB15A_EIC_EXTINT15) -#define PORT_PB15A_EIC_EXTINT15 ((1UL) << 15) -#define PIN_PB15A_EIC_EXTINT_NUM _L_(15) /**< EIC signal: PIN_PB15 External Interrupt Line */ - -#define PIN_PB29A_EIC_EXTINT15 (61L) -#define MUX_PB29A_EIC_EXTINT15 (0L) -#define PINMUX_PB29A_EIC_EXTINT15 ((PIN_PB29A_EIC_EXTINT15 << 16) | MUX_PB29A_EIC_EXTINT15) -#define PORT_PB29A_EIC_EXTINT15 ((1UL) << 29) -#define PIN_PB29A_EIC_EXTINT_NUM _L_(15) /**< EIC signal: PIN_PB29 External Interrupt Line */ - -#define PIN_PB31A_EIC_EXTINT15 (63L) -#define MUX_PB31A_EIC_EXTINT15 (0L) -#define PINMUX_PB31A_EIC_EXTINT15 ((PIN_PB31A_EIC_EXTINT15 << 16) | MUX_PB31A_EIC_EXTINT15) -#define PORT_PB31A_EIC_EXTINT15 ((1UL) << 31) -#define PIN_PB31A_EIC_EXTINT_NUM _L_(15) /**< EIC signal: PIN_PB31 External Interrupt Line */ - -#define PIN_PC15A_EIC_EXTINT15 (79L) -#define MUX_PC15A_EIC_EXTINT15 (0L) -#define PINMUX_PC15A_EIC_EXTINT15 ((PIN_PC15A_EIC_EXTINT15 << 16) | MUX_PC15A_EIC_EXTINT15) -#define PORT_PC15A_EIC_EXTINT15 ((1UL) << 15) -#define PIN_PC15A_EIC_EXTINT_NUM _L_(15) /**< EIC signal: PIN_PC15 External Interrupt Line */ - -#define PIN_PC31A_EIC_EXTINT15 (95L) -#define MUX_PC31A_EIC_EXTINT15 (0L) -#define PINMUX_PC31A_EIC_EXTINT15 ((PIN_PC31A_EIC_EXTINT15 << 16) | MUX_PC31A_EIC_EXTINT15) -#define PORT_PC31A_EIC_EXTINT15 ((1UL) << 31) -#define PIN_PC31A_EIC_EXTINT_NUM _L_(15) /**< EIC signal: PIN_PC31 External Interrupt Line */ - -#define PIN_PA08A_EIC_NMI (8L) -#define MUX_PA08A_EIC_NMI (0L) -#define PINMUX_PA08A_EIC_NMI ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI) -#define PORT_PA08A_EIC_NMI ((1UL) << 8) - -/* ========== PORT definition for GCLK peripheral ========== */ -#define PIN_PA30M_GCLK_IO0 (30L) -#define MUX_PA30M_GCLK_IO0 (12L) -#define PINMUX_PA30M_GCLK_IO0 ((PIN_PA30M_GCLK_IO0 << 16) | MUX_PA30M_GCLK_IO0) -#define PORT_PA30M_GCLK_IO0 ((1UL) << 30) - -#define PIN_PB14M_GCLK_IO0 (46L) -#define MUX_PB14M_GCLK_IO0 (12L) -#define PINMUX_PB14M_GCLK_IO0 ((PIN_PB14M_GCLK_IO0 << 16) | MUX_PB14M_GCLK_IO0) -#define PORT_PB14M_GCLK_IO0 ((1UL) << 14) - -#define PIN_PA14M_GCLK_IO0 (14L) -#define MUX_PA14M_GCLK_IO0 (12L) -#define PINMUX_PA14M_GCLK_IO0 ((PIN_PA14M_GCLK_IO0 << 16) | MUX_PA14M_GCLK_IO0) -#define PORT_PA14M_GCLK_IO0 ((1UL) << 14) - -#define PIN_PB22M_GCLK_IO0 (54L) -#define MUX_PB22M_GCLK_IO0 (12L) -#define PINMUX_PB22M_GCLK_IO0 ((PIN_PB22M_GCLK_IO0 << 16) | MUX_PB22M_GCLK_IO0) -#define PORT_PB22M_GCLK_IO0 ((1UL) << 22) - -#define PIN_PB15M_GCLK_IO1 (47L) -#define MUX_PB15M_GCLK_IO1 (12L) -#define PINMUX_PB15M_GCLK_IO1 ((PIN_PB15M_GCLK_IO1 << 16) | MUX_PB15M_GCLK_IO1) -#define PORT_PB15M_GCLK_IO1 ((1UL) << 15) - -#define PIN_PA15M_GCLK_IO1 (15L) -#define MUX_PA15M_GCLK_IO1 (12L) -#define PINMUX_PA15M_GCLK_IO1 ((PIN_PA15M_GCLK_IO1 << 16) | MUX_PA15M_GCLK_IO1) -#define PORT_PA15M_GCLK_IO1 ((1UL) << 15) - -#define PIN_PB23M_GCLK_IO1 (55L) -#define MUX_PB23M_GCLK_IO1 (12L) -#define PINMUX_PB23M_GCLK_IO1 ((PIN_PB23M_GCLK_IO1 << 16) | MUX_PB23M_GCLK_IO1) -#define PORT_PB23M_GCLK_IO1 ((1UL) << 23) - -#define PIN_PA27M_GCLK_IO1 (27L) -#define MUX_PA27M_GCLK_IO1 (12L) -#define PINMUX_PA27M_GCLK_IO1 ((PIN_PA27M_GCLK_IO1 << 16) | MUX_PA27M_GCLK_IO1) -#define PORT_PA27M_GCLK_IO1 ((1UL) << 27) - -#define PIN_PA16M_GCLK_IO2 (16L) -#define MUX_PA16M_GCLK_IO2 (12L) -#define PINMUX_PA16M_GCLK_IO2 ((PIN_PA16M_GCLK_IO2 << 16) | MUX_PA16M_GCLK_IO2) -#define PORT_PA16M_GCLK_IO2 ((1UL) << 16) - -#define PIN_PB16M_GCLK_IO2 (48L) -#define MUX_PB16M_GCLK_IO2 (12L) -#define PINMUX_PB16M_GCLK_IO2 ((PIN_PB16M_GCLK_IO2 << 16) | MUX_PB16M_GCLK_IO2) -#define PORT_PB16M_GCLK_IO2 ((1UL) << 16) - -#define PIN_PA17M_GCLK_IO3 (17L) -#define MUX_PA17M_GCLK_IO3 (12L) -#define PINMUX_PA17M_GCLK_IO3 ((PIN_PA17M_GCLK_IO3 << 16) | MUX_PA17M_GCLK_IO3) -#define PORT_PA17M_GCLK_IO3 ((1UL) << 17) - -#define PIN_PB17M_GCLK_IO3 (49L) -#define MUX_PB17M_GCLK_IO3 (12L) -#define PINMUX_PB17M_GCLK_IO3 ((PIN_PB17M_GCLK_IO3 << 16) | MUX_PB17M_GCLK_IO3) -#define PORT_PB17M_GCLK_IO3 ((1UL) << 17) - -#define PIN_PA10M_GCLK_IO4 (10L) -#define MUX_PA10M_GCLK_IO4 (12L) -#define PINMUX_PA10M_GCLK_IO4 ((PIN_PA10M_GCLK_IO4 << 16) | MUX_PA10M_GCLK_IO4) -#define PORT_PA10M_GCLK_IO4 ((1UL) << 10) - -#define PIN_PB10M_GCLK_IO4 (42L) -#define MUX_PB10M_GCLK_IO4 (12L) -#define PINMUX_PB10M_GCLK_IO4 ((PIN_PB10M_GCLK_IO4 << 16) | MUX_PB10M_GCLK_IO4) -#define PORT_PB10M_GCLK_IO4 ((1UL) << 10) - -#define PIN_PB18M_GCLK_IO4 (50L) -#define MUX_PB18M_GCLK_IO4 (12L) -#define PINMUX_PB18M_GCLK_IO4 ((PIN_PB18M_GCLK_IO4 << 16) | MUX_PB18M_GCLK_IO4) -#define PORT_PB18M_GCLK_IO4 ((1UL) << 18) - -#define PIN_PA11M_GCLK_IO5 (11L) -#define MUX_PA11M_GCLK_IO5 (12L) -#define PINMUX_PA11M_GCLK_IO5 ((PIN_PA11M_GCLK_IO5 << 16) | MUX_PA11M_GCLK_IO5) -#define PORT_PA11M_GCLK_IO5 ((1UL) << 11) - -#define PIN_PB11M_GCLK_IO5 (43L) -#define MUX_PB11M_GCLK_IO5 (12L) -#define PINMUX_PB11M_GCLK_IO5 ((PIN_PB11M_GCLK_IO5 << 16) | MUX_PB11M_GCLK_IO5) -#define PORT_PB11M_GCLK_IO5 ((1UL) << 11) - -#define PIN_PB19M_GCLK_IO5 (51L) -#define MUX_PB19M_GCLK_IO5 (12L) -#define PINMUX_PB19M_GCLK_IO5 ((PIN_PB19M_GCLK_IO5 << 16) | MUX_PB19M_GCLK_IO5) -#define PORT_PB19M_GCLK_IO5 ((1UL) << 19) - -#define PIN_PB12M_GCLK_IO6 (44L) -#define MUX_PB12M_GCLK_IO6 (12L) -#define PINMUX_PB12M_GCLK_IO6 ((PIN_PB12M_GCLK_IO6 << 16) | MUX_PB12M_GCLK_IO6) -#define PORT_PB12M_GCLK_IO6 ((1UL) << 12) - -#define PIN_PB20M_GCLK_IO6 (52L) -#define MUX_PB20M_GCLK_IO6 (12L) -#define PINMUX_PB20M_GCLK_IO6 ((PIN_PB20M_GCLK_IO6 << 16) | MUX_PB20M_GCLK_IO6) -#define PORT_PB20M_GCLK_IO6 ((1UL) << 20) - -#define PIN_PB13M_GCLK_IO7 (45L) -#define MUX_PB13M_GCLK_IO7 (12L) -#define PINMUX_PB13M_GCLK_IO7 ((PIN_PB13M_GCLK_IO7 << 16) | MUX_PB13M_GCLK_IO7) -#define PORT_PB13M_GCLK_IO7 ((1UL) << 13) - -#define PIN_PB21M_GCLK_IO7 (53L) -#define MUX_PB21M_GCLK_IO7 (12L) -#define PINMUX_PB21M_GCLK_IO7 ((PIN_PB21M_GCLK_IO7 << 16) | MUX_PB21M_GCLK_IO7) -#define PORT_PB21M_GCLK_IO7 ((1UL) << 21) - -/* ========== PORT definition for GMAC peripheral ========== */ -#define PIN_PC21L_GMAC_GCOL (85L) -#define MUX_PC21L_GMAC_GCOL (11L) -#define PINMUX_PC21L_GMAC_GCOL ((PIN_PC21L_GMAC_GCOL << 16) | MUX_PC21L_GMAC_GCOL) -#define PORT_PC21L_GMAC_GCOL ((1UL) << 21) - -#define PIN_PA16L_GMAC_GCRS (16L) -#define MUX_PA16L_GMAC_GCRS (11L) -#define PINMUX_PA16L_GMAC_GCRS ((PIN_PA16L_GMAC_GCRS << 16) | MUX_PA16L_GMAC_GCRS) -#define PORT_PA16L_GMAC_GCRS ((1UL) << 16) - -#define PIN_PA20L_GMAC_GMDC (20L) -#define MUX_PA20L_GMAC_GMDC (11L) -#define PINMUX_PA20L_GMAC_GMDC ((PIN_PA20L_GMAC_GMDC << 16) | MUX_PA20L_GMAC_GMDC) -#define PORT_PA20L_GMAC_GMDC ((1UL) << 20) - -#define PIN_PB14L_GMAC_GMDC (46L) -#define MUX_PB14L_GMAC_GMDC (11L) -#define PINMUX_PB14L_GMAC_GMDC ((PIN_PB14L_GMAC_GMDC << 16) | MUX_PB14L_GMAC_GMDC) -#define PORT_PB14L_GMAC_GMDC ((1UL) << 14) - -#define PIN_PC11L_GMAC_GMDC (75L) -#define MUX_PC11L_GMAC_GMDC (11L) -#define PINMUX_PC11L_GMAC_GMDC ((PIN_PC11L_GMAC_GMDC << 16) | MUX_PC11L_GMAC_GMDC) -#define PORT_PC11L_GMAC_GMDC ((1UL) << 11) - -#define PIN_PC22L_GMAC_GMDC (86L) -#define MUX_PC22L_GMAC_GMDC (11L) -#define PINMUX_PC22L_GMAC_GMDC ((PIN_PC22L_GMAC_GMDC << 16) | MUX_PC22L_GMAC_GMDC) -#define PORT_PC22L_GMAC_GMDC ((1UL) << 22) - -#define PIN_PA21L_GMAC_GMDIO (21L) -#define MUX_PA21L_GMAC_GMDIO (11L) -#define PINMUX_PA21L_GMAC_GMDIO ((PIN_PA21L_GMAC_GMDIO << 16) | MUX_PA21L_GMAC_GMDIO) -#define PORT_PA21L_GMAC_GMDIO ((1UL) << 21) - -#define PIN_PB15L_GMAC_GMDIO (47L) -#define MUX_PB15L_GMAC_GMDIO (11L) -#define PINMUX_PB15L_GMAC_GMDIO ((PIN_PB15L_GMAC_GMDIO << 16) | MUX_PB15L_GMAC_GMDIO) -#define PORT_PB15L_GMAC_GMDIO ((1UL) << 15) - -#define PIN_PC12L_GMAC_GMDIO (76L) -#define MUX_PC12L_GMAC_GMDIO (11L) -#define PINMUX_PC12L_GMAC_GMDIO ((PIN_PC12L_GMAC_GMDIO << 16) | MUX_PC12L_GMAC_GMDIO) -#define PORT_PC12L_GMAC_GMDIO ((1UL) << 12) - -#define PIN_PC23L_GMAC_GMDIO (87L) -#define MUX_PC23L_GMAC_GMDIO (11L) -#define PINMUX_PC23L_GMAC_GMDIO ((PIN_PC23L_GMAC_GMDIO << 16) | MUX_PC23L_GMAC_GMDIO) -#define PORT_PC23L_GMAC_GMDIO ((1UL) << 23) - -#define PIN_PA13L_GMAC_GRX0 (13L) -#define MUX_PA13L_GMAC_GRX0 (11L) -#define PINMUX_PA13L_GMAC_GRX0 ((PIN_PA13L_GMAC_GRX0 << 16) | MUX_PA13L_GMAC_GRX0) -#define PORT_PA13L_GMAC_GRX0 ((1UL) << 13) - -#define PIN_PA12L_GMAC_GRX1 (12L) -#define MUX_PA12L_GMAC_GRX1 (11L) -#define PINMUX_PA12L_GMAC_GRX1 ((PIN_PA12L_GMAC_GRX1 << 16) | MUX_PA12L_GMAC_GRX1) -#define PORT_PA12L_GMAC_GRX1 ((1UL) << 12) - -#define PIN_PC15L_GMAC_GRX2 (79L) -#define MUX_PC15L_GMAC_GRX2 (11L) -#define PINMUX_PC15L_GMAC_GRX2 ((PIN_PC15L_GMAC_GRX2 << 16) | MUX_PC15L_GMAC_GRX2) -#define PORT_PC15L_GMAC_GRX2 ((1UL) << 15) - -#define PIN_PC14L_GMAC_GRX3 (78L) -#define MUX_PC14L_GMAC_GRX3 (11L) -#define PINMUX_PC14L_GMAC_GRX3 ((PIN_PC14L_GMAC_GRX3 << 16) | MUX_PC14L_GMAC_GRX3) -#define PORT_PC14L_GMAC_GRX3 ((1UL) << 14) - -#define PIN_PC18L_GMAC_GRXCK (82L) -#define MUX_PC18L_GMAC_GRXCK (11L) -#define PINMUX_PC18L_GMAC_GRXCK ((PIN_PC18L_GMAC_GRXCK << 16) | MUX_PC18L_GMAC_GRXCK) -#define PORT_PC18L_GMAC_GRXCK ((1UL) << 18) - -#define PIN_PC20L_GMAC_GRXDV (84L) -#define MUX_PC20L_GMAC_GRXDV (11L) -#define PINMUX_PC20L_GMAC_GRXDV ((PIN_PC20L_GMAC_GRXDV << 16) | MUX_PC20L_GMAC_GRXDV) -#define PORT_PC20L_GMAC_GRXDV ((1UL) << 20) - -#define PIN_PA15L_GMAC_GRXER (15L) -#define MUX_PA15L_GMAC_GRXER (11L) -#define PINMUX_PA15L_GMAC_GRXER ((PIN_PA15L_GMAC_GRXER << 16) | MUX_PA15L_GMAC_GRXER) -#define PORT_PA15L_GMAC_GRXER ((1UL) << 15) - -#define PIN_PA18L_GMAC_GTX0 (18L) -#define MUX_PA18L_GMAC_GTX0 (11L) -#define PINMUX_PA18L_GMAC_GTX0 ((PIN_PA18L_GMAC_GTX0 << 16) | MUX_PA18L_GMAC_GTX0) -#define PORT_PA18L_GMAC_GTX0 ((1UL) << 18) - -#define PIN_PA19L_GMAC_GTX1 (19L) -#define MUX_PA19L_GMAC_GTX1 (11L) -#define PINMUX_PA19L_GMAC_GTX1 ((PIN_PA19L_GMAC_GTX1 << 16) | MUX_PA19L_GMAC_GTX1) -#define PORT_PA19L_GMAC_GTX1 ((1UL) << 19) - -#define PIN_PC16L_GMAC_GTX2 (80L) -#define MUX_PC16L_GMAC_GTX2 (11L) -#define PINMUX_PC16L_GMAC_GTX2 ((PIN_PC16L_GMAC_GTX2 << 16) | MUX_PC16L_GMAC_GTX2) -#define PORT_PC16L_GMAC_GTX2 ((1UL) << 16) - -#define PIN_PC17L_GMAC_GTX3 (81L) -#define MUX_PC17L_GMAC_GTX3 (11L) -#define PINMUX_PC17L_GMAC_GTX3 ((PIN_PC17L_GMAC_GTX3 << 16) | MUX_PC17L_GMAC_GTX3) -#define PORT_PC17L_GMAC_GTX3 ((1UL) << 17) - -#define PIN_PA14L_GMAC_GTXCK (14L) -#define MUX_PA14L_GMAC_GTXCK (11L) -#define PINMUX_PA14L_GMAC_GTXCK ((PIN_PA14L_GMAC_GTXCK << 16) | MUX_PA14L_GMAC_GTXCK) -#define PORT_PA14L_GMAC_GTXCK ((1UL) << 14) - -#define PIN_PA17L_GMAC_GTXEN (17L) -#define MUX_PA17L_GMAC_GTXEN (11L) -#define PINMUX_PA17L_GMAC_GTXEN ((PIN_PA17L_GMAC_GTXEN << 16) | MUX_PA17L_GMAC_GTXEN) -#define PORT_PA17L_GMAC_GTXEN ((1UL) << 17) - -#define PIN_PC19L_GMAC_GTXER (83L) -#define MUX_PC19L_GMAC_GTXER (11L) -#define PINMUX_PC19L_GMAC_GTXER ((PIN_PC19L_GMAC_GTXER << 16) | MUX_PC19L_GMAC_GTXER) -#define PORT_PC19L_GMAC_GTXER ((1UL) << 19) - -/* ========== PORT definition for I2S peripheral ========== */ -#define PIN_PA09J_I2S_FS0 (9L) -#define MUX_PA09J_I2S_FS0 (9L) -#define PINMUX_PA09J_I2S_FS0 ((PIN_PA09J_I2S_FS0 << 16) | MUX_PA09J_I2S_FS0) -#define PORT_PA09J_I2S_FS0 ((1UL) << 9) - -#define PIN_PA20J_I2S_FS0 (20L) -#define MUX_PA20J_I2S_FS0 (9L) -#define PINMUX_PA20J_I2S_FS0 ((PIN_PA20J_I2S_FS0 << 16) | MUX_PA20J_I2S_FS0) -#define PORT_PA20J_I2S_FS0 ((1UL) << 20) - -#define PIN_PA23J_I2S_FS1 (23L) -#define MUX_PA23J_I2S_FS1 (9L) -#define PINMUX_PA23J_I2S_FS1 ((PIN_PA23J_I2S_FS1 << 16) | MUX_PA23J_I2S_FS1) -#define PORT_PA23J_I2S_FS1 ((1UL) << 23) - -#define PIN_PB11J_I2S_FS1 (43L) -#define MUX_PB11J_I2S_FS1 (9L) -#define PINMUX_PB11J_I2S_FS1 ((PIN_PB11J_I2S_FS1 << 16) | MUX_PB11J_I2S_FS1) -#define PORT_PB11J_I2S_FS1 ((1UL) << 11) - -#define PIN_PA08J_I2S_MCK0 (8L) -#define MUX_PA08J_I2S_MCK0 (9L) -#define PINMUX_PA08J_I2S_MCK0 ((PIN_PA08J_I2S_MCK0 << 16) | MUX_PA08J_I2S_MCK0) -#define PORT_PA08J_I2S_MCK0 ((1UL) << 8) - -#define PIN_PB17J_I2S_MCK0 (49L) -#define MUX_PB17J_I2S_MCK0 (9L) -#define PINMUX_PB17J_I2S_MCK0 ((PIN_PB17J_I2S_MCK0 << 16) | MUX_PB17J_I2S_MCK0) -#define PORT_PB17J_I2S_MCK0 ((1UL) << 17) - -#define PIN_PB29J_I2S_MCK1 (61L) -#define MUX_PB29J_I2S_MCK1 (9L) -#define PINMUX_PB29J_I2S_MCK1 ((PIN_PB29J_I2S_MCK1 << 16) | MUX_PB29J_I2S_MCK1) -#define PORT_PB29J_I2S_MCK1 ((1UL) << 29) - -#define PIN_PB13J_I2S_MCK1 (45L) -#define MUX_PB13J_I2S_MCK1 (9L) -#define PINMUX_PB13J_I2S_MCK1 ((PIN_PB13J_I2S_MCK1 << 16) | MUX_PB13J_I2S_MCK1) -#define PORT_PB13J_I2S_MCK1 ((1UL) << 13) - -#define PIN_PA10J_I2S_SCK0 (10L) -#define MUX_PA10J_I2S_SCK0 (9L) -#define PINMUX_PA10J_I2S_SCK0 ((PIN_PA10J_I2S_SCK0 << 16) | MUX_PA10J_I2S_SCK0) -#define PORT_PA10J_I2S_SCK0 ((1UL) << 10) - -#define PIN_PB16J_I2S_SCK0 (48L) -#define MUX_PB16J_I2S_SCK0 (9L) -#define PINMUX_PB16J_I2S_SCK0 ((PIN_PB16J_I2S_SCK0 << 16) | MUX_PB16J_I2S_SCK0) -#define PORT_PB16J_I2S_SCK0 ((1UL) << 16) - -#define PIN_PB28J_I2S_SCK1 (60L) -#define MUX_PB28J_I2S_SCK1 (9L) -#define PINMUX_PB28J_I2S_SCK1 ((PIN_PB28J_I2S_SCK1 << 16) | MUX_PB28J_I2S_SCK1) -#define PORT_PB28J_I2S_SCK1 ((1UL) << 28) - -#define PIN_PB12J_I2S_SCK1 (44L) -#define MUX_PB12J_I2S_SCK1 (9L) -#define PINMUX_PB12J_I2S_SCK1 ((PIN_PB12J_I2S_SCK1 << 16) | MUX_PB12J_I2S_SCK1) -#define PORT_PB12J_I2S_SCK1 ((1UL) << 12) - -#define PIN_PA22J_I2S_SDI (22L) -#define MUX_PA22J_I2S_SDI (9L) -#define PINMUX_PA22J_I2S_SDI ((PIN_PA22J_I2S_SDI << 16) | MUX_PA22J_I2S_SDI) -#define PORT_PA22J_I2S_SDI ((1UL) << 22) - -#define PIN_PB10J_I2S_SDI (42L) -#define MUX_PB10J_I2S_SDI (9L) -#define PINMUX_PB10J_I2S_SDI ((PIN_PB10J_I2S_SDI << 16) | MUX_PB10J_I2S_SDI) -#define PORT_PB10J_I2S_SDI ((1UL) << 10) - -#define PIN_PA11J_I2S_SDO (11L) -#define MUX_PA11J_I2S_SDO (9L) -#define PINMUX_PA11J_I2S_SDO ((PIN_PA11J_I2S_SDO << 16) | MUX_PA11J_I2S_SDO) -#define PORT_PA11J_I2S_SDO ((1UL) << 11) - -#define PIN_PA21J_I2S_SDO (21L) -#define MUX_PA21J_I2S_SDO (9L) -#define PINMUX_PA21J_I2S_SDO ((PIN_PA21J_I2S_SDO << 16) | MUX_PA21J_I2S_SDO) -#define PORT_PA21J_I2S_SDO ((1UL) << 21) - -/* ========== PORT definition for PCC peripheral ========== */ -#define PIN_PA14K_PCC_CLK (14L) -#define MUX_PA14K_PCC_CLK (10L) -#define PINMUX_PA14K_PCC_CLK ((PIN_PA14K_PCC_CLK << 16) | MUX_PA14K_PCC_CLK) -#define PORT_PA14K_PCC_CLK ((1UL) << 14) - -#define PIN_PA16K_PCC_DATA0 (16L) -#define MUX_PA16K_PCC_DATA0 (10L) -#define PINMUX_PA16K_PCC_DATA0 ((PIN_PA16K_PCC_DATA0 << 16) | MUX_PA16K_PCC_DATA0) -#define PORT_PA16K_PCC_DATA0 ((1UL) << 16) - -#define PIN_PA17K_PCC_DATA1 (17L) -#define MUX_PA17K_PCC_DATA1 (10L) -#define PINMUX_PA17K_PCC_DATA1 ((PIN_PA17K_PCC_DATA1 << 16) | MUX_PA17K_PCC_DATA1) -#define PORT_PA17K_PCC_DATA1 ((1UL) << 17) - -#define PIN_PA18K_PCC_DATA2 (18L) -#define MUX_PA18K_PCC_DATA2 (10L) -#define PINMUX_PA18K_PCC_DATA2 ((PIN_PA18K_PCC_DATA2 << 16) | MUX_PA18K_PCC_DATA2) -#define PORT_PA18K_PCC_DATA2 ((1UL) << 18) - -#define PIN_PA19K_PCC_DATA3 (19L) -#define MUX_PA19K_PCC_DATA3 (10L) -#define PINMUX_PA19K_PCC_DATA3 ((PIN_PA19K_PCC_DATA3 << 16) | MUX_PA19K_PCC_DATA3) -#define PORT_PA19K_PCC_DATA3 ((1UL) << 19) - -#define PIN_PA20K_PCC_DATA4 (20L) -#define MUX_PA20K_PCC_DATA4 (10L) -#define PINMUX_PA20K_PCC_DATA4 ((PIN_PA20K_PCC_DATA4 << 16) | MUX_PA20K_PCC_DATA4) -#define PORT_PA20K_PCC_DATA4 ((1UL) << 20) - -#define PIN_PA21K_PCC_DATA5 (21L) -#define MUX_PA21K_PCC_DATA5 (10L) -#define PINMUX_PA21K_PCC_DATA5 ((PIN_PA21K_PCC_DATA5 << 16) | MUX_PA21K_PCC_DATA5) -#define PORT_PA21K_PCC_DATA5 ((1UL) << 21) - -#define PIN_PA22K_PCC_DATA6 (22L) -#define MUX_PA22K_PCC_DATA6 (10L) -#define PINMUX_PA22K_PCC_DATA6 ((PIN_PA22K_PCC_DATA6 << 16) | MUX_PA22K_PCC_DATA6) -#define PORT_PA22K_PCC_DATA6 ((1UL) << 22) - -#define PIN_PA23K_PCC_DATA7 (23L) -#define MUX_PA23K_PCC_DATA7 (10L) -#define PINMUX_PA23K_PCC_DATA7 ((PIN_PA23K_PCC_DATA7 << 16) | MUX_PA23K_PCC_DATA7) -#define PORT_PA23K_PCC_DATA7 ((1UL) << 23) - -#define PIN_PB14K_PCC_DATA8 (46L) -#define MUX_PB14K_PCC_DATA8 (10L) -#define PINMUX_PB14K_PCC_DATA8 ((PIN_PB14K_PCC_DATA8 << 16) | MUX_PB14K_PCC_DATA8) -#define PORT_PB14K_PCC_DATA8 ((1UL) << 14) - -#define PIN_PB15K_PCC_DATA9 (47L) -#define MUX_PB15K_PCC_DATA9 (10L) -#define PINMUX_PB15K_PCC_DATA9 ((PIN_PB15K_PCC_DATA9 << 16) | MUX_PB15K_PCC_DATA9) -#define PORT_PB15K_PCC_DATA9 ((1UL) << 15) - -#define PIN_PC12K_PCC_DATA10 (76L) -#define MUX_PC12K_PCC_DATA10 (10L) -#define PINMUX_PC12K_PCC_DATA10 ((PIN_PC12K_PCC_DATA10 << 16) | MUX_PC12K_PCC_DATA10) -#define PORT_PC12K_PCC_DATA10 ((1UL) << 12) - -#define PIN_PC13K_PCC_DATA11 (77L) -#define MUX_PC13K_PCC_DATA11 (10L) -#define PINMUX_PC13K_PCC_DATA11 ((PIN_PC13K_PCC_DATA11 << 16) | MUX_PC13K_PCC_DATA11) -#define PORT_PC13K_PCC_DATA11 ((1UL) << 13) - -#define PIN_PC14K_PCC_DATA12 (78L) -#define MUX_PC14K_PCC_DATA12 (10L) -#define PINMUX_PC14K_PCC_DATA12 ((PIN_PC14K_PCC_DATA12 << 16) | MUX_PC14K_PCC_DATA12) -#define PORT_PC14K_PCC_DATA12 ((1UL) << 14) - -#define PIN_PC15K_PCC_DATA13 (79L) -#define MUX_PC15K_PCC_DATA13 (10L) -#define PINMUX_PC15K_PCC_DATA13 ((PIN_PC15K_PCC_DATA13 << 16) | MUX_PC15K_PCC_DATA13) -#define PORT_PC15K_PCC_DATA13 ((1UL) << 15) - -#define PIN_PA12K_PCC_DEN1 (12L) -#define MUX_PA12K_PCC_DEN1 (10L) -#define PINMUX_PA12K_PCC_DEN1 ((PIN_PA12K_PCC_DEN1 << 16) | MUX_PA12K_PCC_DEN1) -#define PORT_PA12K_PCC_DEN1 ((1UL) << 12) - -#define PIN_PA13K_PCC_DEN2 (13L) -#define MUX_PA13K_PCC_DEN2 (10L) -#define PINMUX_PA13K_PCC_DEN2 ((PIN_PA13K_PCC_DEN2 << 16) | MUX_PA13K_PCC_DEN2) -#define PORT_PA13K_PCC_DEN2 ((1UL) << 13) - -/* ========== PORT definition for PDEC peripheral ========== */ -#define PIN_PB18G_PDEC_QDI0 (50L) -#define MUX_PB18G_PDEC_QDI0 (6L) -#define PINMUX_PB18G_PDEC_QDI0 ((PIN_PB18G_PDEC_QDI0 << 16) | MUX_PB18G_PDEC_QDI0) -#define PORT_PB18G_PDEC_QDI0 ((1UL) << 18) - -#define PIN_PB23G_PDEC_QDI0 (55L) -#define MUX_PB23G_PDEC_QDI0 (6L) -#define PINMUX_PB23G_PDEC_QDI0 ((PIN_PB23G_PDEC_QDI0 << 16) | MUX_PB23G_PDEC_QDI0) -#define PORT_PB23G_PDEC_QDI0 ((1UL) << 23) - -#define PIN_PC16G_PDEC_QDI0 (80L) -#define MUX_PC16G_PDEC_QDI0 (6L) -#define PINMUX_PC16G_PDEC_QDI0 ((PIN_PC16G_PDEC_QDI0 << 16) | MUX_PC16G_PDEC_QDI0) -#define PORT_PC16G_PDEC_QDI0 ((1UL) << 16) - -#define PIN_PA24G_PDEC_QDI0 (24L) -#define MUX_PA24G_PDEC_QDI0 (6L) -#define PINMUX_PA24G_PDEC_QDI0 ((PIN_PA24G_PDEC_QDI0 << 16) | MUX_PA24G_PDEC_QDI0) -#define PORT_PA24G_PDEC_QDI0 ((1UL) << 24) - -#define PIN_PB19G_PDEC_QDI1 (51L) -#define MUX_PB19G_PDEC_QDI1 (6L) -#define PINMUX_PB19G_PDEC_QDI1 ((PIN_PB19G_PDEC_QDI1 << 16) | MUX_PB19G_PDEC_QDI1) -#define PORT_PB19G_PDEC_QDI1 ((1UL) << 19) - -#define PIN_PB24G_PDEC_QDI1 (56L) -#define MUX_PB24G_PDEC_QDI1 (6L) -#define PINMUX_PB24G_PDEC_QDI1 ((PIN_PB24G_PDEC_QDI1 << 16) | MUX_PB24G_PDEC_QDI1) -#define PORT_PB24G_PDEC_QDI1 ((1UL) << 24) - -#define PIN_PC17G_PDEC_QDI1 (81L) -#define MUX_PC17G_PDEC_QDI1 (6L) -#define PINMUX_PC17G_PDEC_QDI1 ((PIN_PC17G_PDEC_QDI1 << 16) | MUX_PC17G_PDEC_QDI1) -#define PORT_PC17G_PDEC_QDI1 ((1UL) << 17) - -#define PIN_PA25G_PDEC_QDI1 (25L) -#define MUX_PA25G_PDEC_QDI1 (6L) -#define PINMUX_PA25G_PDEC_QDI1 ((PIN_PA25G_PDEC_QDI1 << 16) | MUX_PA25G_PDEC_QDI1) -#define PORT_PA25G_PDEC_QDI1 ((1UL) << 25) - -#define PIN_PB20G_PDEC_QDI2 (52L) -#define MUX_PB20G_PDEC_QDI2 (6L) -#define PINMUX_PB20G_PDEC_QDI2 ((PIN_PB20G_PDEC_QDI2 << 16) | MUX_PB20G_PDEC_QDI2) -#define PORT_PB20G_PDEC_QDI2 ((1UL) << 20) - -#define PIN_PB25G_PDEC_QDI2 (57L) -#define MUX_PB25G_PDEC_QDI2 (6L) -#define PINMUX_PB25G_PDEC_QDI2 ((PIN_PB25G_PDEC_QDI2 << 16) | MUX_PB25G_PDEC_QDI2) -#define PORT_PB25G_PDEC_QDI2 ((1UL) << 25) - -#define PIN_PC18G_PDEC_QDI2 (82L) -#define MUX_PC18G_PDEC_QDI2 (6L) -#define PINMUX_PC18G_PDEC_QDI2 ((PIN_PC18G_PDEC_QDI2 << 16) | MUX_PC18G_PDEC_QDI2) -#define PORT_PC18G_PDEC_QDI2 ((1UL) << 18) - -#define PIN_PB22G_PDEC_QDI2 (54L) -#define MUX_PB22G_PDEC_QDI2 (6L) -#define PINMUX_PB22G_PDEC_QDI2 ((PIN_PB22G_PDEC_QDI2 << 16) | MUX_PB22G_PDEC_QDI2) -#define PORT_PB22G_PDEC_QDI2 ((1UL) << 22) - -/* ========== PORT definition for QSPI peripheral ========== */ -#define PIN_PB11H_QSPI_CS (43L) -#define MUX_PB11H_QSPI_CS (7L) -#define PINMUX_PB11H_QSPI_CS ((PIN_PB11H_QSPI_CS << 16) | MUX_PB11H_QSPI_CS) -#define PORT_PB11H_QSPI_CS ((1UL) << 11) - -#define PIN_PA08H_QSPI_DATA0 (8L) -#define MUX_PA08H_QSPI_DATA0 (7L) -#define PINMUX_PA08H_QSPI_DATA0 ((PIN_PA08H_QSPI_DATA0 << 16) | MUX_PA08H_QSPI_DATA0) -#define PORT_PA08H_QSPI_DATA0 ((1UL) << 8) - -#define PIN_PA09H_QSPI_DATA1 (9L) -#define MUX_PA09H_QSPI_DATA1 (7L) -#define PINMUX_PA09H_QSPI_DATA1 ((PIN_PA09H_QSPI_DATA1 << 16) | MUX_PA09H_QSPI_DATA1) -#define PORT_PA09H_QSPI_DATA1 ((1UL) << 9) - -#define PIN_PA10H_QSPI_DATA2 (10L) -#define MUX_PA10H_QSPI_DATA2 (7L) -#define PINMUX_PA10H_QSPI_DATA2 ((PIN_PA10H_QSPI_DATA2 << 16) | MUX_PA10H_QSPI_DATA2) -#define PORT_PA10H_QSPI_DATA2 ((1UL) << 10) - -#define PIN_PA11H_QSPI_DATA3 (11L) -#define MUX_PA11H_QSPI_DATA3 (7L) -#define PINMUX_PA11H_QSPI_DATA3 ((PIN_PA11H_QSPI_DATA3 << 16) | MUX_PA11H_QSPI_DATA3) -#define PORT_PA11H_QSPI_DATA3 ((1UL) << 11) - -#define PIN_PB10H_QSPI_SCK (42L) -#define MUX_PB10H_QSPI_SCK (7L) -#define PINMUX_PB10H_QSPI_SCK ((PIN_PB10H_QSPI_SCK << 16) | MUX_PB10H_QSPI_SCK) -#define PORT_PB10H_QSPI_SCK ((1UL) << 10) - -/* ========== PORT definition for SDHC0 peripheral ========== */ -#define PIN_PA06I_SDHC0_SDCD (6L) -#define MUX_PA06I_SDHC0_SDCD (8L) -#define PINMUX_PA06I_SDHC0_SDCD ((PIN_PA06I_SDHC0_SDCD << 16) | MUX_PA06I_SDHC0_SDCD) -#define PORT_PA06I_SDHC0_SDCD ((1UL) << 6) - -#define PIN_PA12I_SDHC0_SDCD (12L) -#define MUX_PA12I_SDHC0_SDCD (8L) -#define PINMUX_PA12I_SDHC0_SDCD ((PIN_PA12I_SDHC0_SDCD << 16) | MUX_PA12I_SDHC0_SDCD) -#define PORT_PA12I_SDHC0_SDCD ((1UL) << 12) - -#define PIN_PB12I_SDHC0_SDCD (44L) -#define MUX_PB12I_SDHC0_SDCD (8L) -#define PINMUX_PB12I_SDHC0_SDCD ((PIN_PB12I_SDHC0_SDCD << 16) | MUX_PB12I_SDHC0_SDCD) -#define PORT_PB12I_SDHC0_SDCD ((1UL) << 12) - -#define PIN_PC06I_SDHC0_SDCD (70L) -#define MUX_PC06I_SDHC0_SDCD (8L) -#define PINMUX_PC06I_SDHC0_SDCD ((PIN_PC06I_SDHC0_SDCD << 16) | MUX_PC06I_SDHC0_SDCD) -#define PORT_PC06I_SDHC0_SDCD ((1UL) << 6) - -#define PIN_PB11I_SDHC0_SDCK (43L) -#define MUX_PB11I_SDHC0_SDCK (8L) -#define PINMUX_PB11I_SDHC0_SDCK ((PIN_PB11I_SDHC0_SDCK << 16) | MUX_PB11I_SDHC0_SDCK) -#define PORT_PB11I_SDHC0_SDCK ((1UL) << 11) - -#define PIN_PA08I_SDHC0_SDCMD (8L) -#define MUX_PA08I_SDHC0_SDCMD (8L) -#define PINMUX_PA08I_SDHC0_SDCMD ((PIN_PA08I_SDHC0_SDCMD << 16) | MUX_PA08I_SDHC0_SDCMD) -#define PORT_PA08I_SDHC0_SDCMD ((1UL) << 8) - -#define PIN_PA09I_SDHC0_SDDAT0 (9L) -#define MUX_PA09I_SDHC0_SDDAT0 (8L) -#define PINMUX_PA09I_SDHC0_SDDAT0 ((PIN_PA09I_SDHC0_SDDAT0 << 16) | MUX_PA09I_SDHC0_SDDAT0) -#define PORT_PA09I_SDHC0_SDDAT0 ((1UL) << 9) - -#define PIN_PA10I_SDHC0_SDDAT1 (10L) -#define MUX_PA10I_SDHC0_SDDAT1 (8L) -#define PINMUX_PA10I_SDHC0_SDDAT1 ((PIN_PA10I_SDHC0_SDDAT1 << 16) | MUX_PA10I_SDHC0_SDDAT1) -#define PORT_PA10I_SDHC0_SDDAT1 ((1UL) << 10) - -#define PIN_PA11I_SDHC0_SDDAT2 (11L) -#define MUX_PA11I_SDHC0_SDDAT2 (8L) -#define PINMUX_PA11I_SDHC0_SDDAT2 ((PIN_PA11I_SDHC0_SDDAT2 << 16) | MUX_PA11I_SDHC0_SDDAT2) -#define PORT_PA11I_SDHC0_SDDAT2 ((1UL) << 11) - -#define PIN_PB10I_SDHC0_SDDAT3 (42L) -#define MUX_PB10I_SDHC0_SDDAT3 (8L) -#define PINMUX_PB10I_SDHC0_SDDAT3 ((PIN_PB10I_SDHC0_SDDAT3 << 16) | MUX_PB10I_SDHC0_SDDAT3) -#define PORT_PB10I_SDHC0_SDDAT3 ((1UL) << 10) - -#define PIN_PA07I_SDHC0_SDWP (7L) -#define MUX_PA07I_SDHC0_SDWP (8L) -#define PINMUX_PA07I_SDHC0_SDWP ((PIN_PA07I_SDHC0_SDWP << 16) | MUX_PA07I_SDHC0_SDWP) -#define PORT_PA07I_SDHC0_SDWP ((1UL) << 7) - -#define PIN_PA13I_SDHC0_SDWP (13L) -#define MUX_PA13I_SDHC0_SDWP (8L) -#define PINMUX_PA13I_SDHC0_SDWP ((PIN_PA13I_SDHC0_SDWP << 16) | MUX_PA13I_SDHC0_SDWP) -#define PORT_PA13I_SDHC0_SDWP ((1UL) << 13) - -#define PIN_PB13I_SDHC0_SDWP (45L) -#define MUX_PB13I_SDHC0_SDWP (8L) -#define PINMUX_PB13I_SDHC0_SDWP ((PIN_PB13I_SDHC0_SDWP << 16) | MUX_PB13I_SDHC0_SDWP) -#define PORT_PB13I_SDHC0_SDWP ((1UL) << 13) - -#define PIN_PC07I_SDHC0_SDWP (71L) -#define MUX_PC07I_SDHC0_SDWP (8L) -#define PINMUX_PC07I_SDHC0_SDWP ((PIN_PC07I_SDHC0_SDWP << 16) | MUX_PC07I_SDHC0_SDWP) -#define PORT_PC07I_SDHC0_SDWP ((1UL) << 7) - -/* ========== PORT definition for SDHC1 peripheral ========== */ -#define PIN_PB16I_SDHC1_SDCD (48L) -#define MUX_PB16I_SDHC1_SDCD (8L) -#define PINMUX_PB16I_SDHC1_SDCD ((PIN_PB16I_SDHC1_SDCD << 16) | MUX_PB16I_SDHC1_SDCD) -#define PORT_PB16I_SDHC1_SDCD ((1UL) << 16) - -#define PIN_PC20I_SDHC1_SDCD (84L) -#define MUX_PC20I_SDHC1_SDCD (8L) -#define PINMUX_PC20I_SDHC1_SDCD ((PIN_PC20I_SDHC1_SDCD << 16) | MUX_PC20I_SDHC1_SDCD) -#define PORT_PC20I_SDHC1_SDCD ((1UL) << 20) - -#define PIN_PD20I_SDHC1_SDCD (116L) -#define MUX_PD20I_SDHC1_SDCD (8L) -#define PINMUX_PD20I_SDHC1_SDCD ((PIN_PD20I_SDHC1_SDCD << 16) | MUX_PD20I_SDHC1_SDCD) -#define PORT_PD20I_SDHC1_SDCD ((1UL) << 20) - -#define PIN_PA21I_SDHC1_SDCK (21L) -#define MUX_PA21I_SDHC1_SDCK (8L) -#define PINMUX_PA21I_SDHC1_SDCK ((PIN_PA21I_SDHC1_SDCK << 16) | MUX_PA21I_SDHC1_SDCK) -#define PORT_PA21I_SDHC1_SDCK ((1UL) << 21) - -#define PIN_PA20I_SDHC1_SDCMD (20L) -#define MUX_PA20I_SDHC1_SDCMD (8L) -#define PINMUX_PA20I_SDHC1_SDCMD ((PIN_PA20I_SDHC1_SDCMD << 16) | MUX_PA20I_SDHC1_SDCMD) -#define PORT_PA20I_SDHC1_SDCMD ((1UL) << 20) - -#define PIN_PB18I_SDHC1_SDDAT0 (50L) -#define MUX_PB18I_SDHC1_SDDAT0 (8L) -#define PINMUX_PB18I_SDHC1_SDDAT0 ((PIN_PB18I_SDHC1_SDDAT0 << 16) | MUX_PB18I_SDHC1_SDDAT0) -#define PORT_PB18I_SDHC1_SDDAT0 ((1UL) << 18) - -#define PIN_PB19I_SDHC1_SDDAT1 (51L) -#define MUX_PB19I_SDHC1_SDDAT1 (8L) -#define PINMUX_PB19I_SDHC1_SDDAT1 ((PIN_PB19I_SDHC1_SDDAT1 << 16) | MUX_PB19I_SDHC1_SDDAT1) -#define PORT_PB19I_SDHC1_SDDAT1 ((1UL) << 19) - -#define PIN_PB20I_SDHC1_SDDAT2 (52L) -#define MUX_PB20I_SDHC1_SDDAT2 (8L) -#define PINMUX_PB20I_SDHC1_SDDAT2 ((PIN_PB20I_SDHC1_SDDAT2 << 16) | MUX_PB20I_SDHC1_SDDAT2) -#define PORT_PB20I_SDHC1_SDDAT2 ((1UL) << 20) - -#define PIN_PB21I_SDHC1_SDDAT3 (53L) -#define MUX_PB21I_SDHC1_SDDAT3 (8L) -#define PINMUX_PB21I_SDHC1_SDDAT3 ((PIN_PB21I_SDHC1_SDDAT3 << 16) | MUX_PB21I_SDHC1_SDDAT3) -#define PORT_PB21I_SDHC1_SDDAT3 ((1UL) << 21) - -#define PIN_PB17I_SDHC1_SDWP (49L) -#define MUX_PB17I_SDHC1_SDWP (8L) -#define PINMUX_PB17I_SDHC1_SDWP ((PIN_PB17I_SDHC1_SDWP << 16) | MUX_PB17I_SDHC1_SDWP) -#define PORT_PB17I_SDHC1_SDWP ((1UL) << 17) - -#define PIN_PC21I_SDHC1_SDWP (85L) -#define MUX_PC21I_SDHC1_SDWP (8L) -#define PINMUX_PC21I_SDHC1_SDWP ((PIN_PC21I_SDHC1_SDWP << 16) | MUX_PC21I_SDHC1_SDWP) -#define PORT_PC21I_SDHC1_SDWP ((1UL) << 21) - -#define PIN_PD21I_SDHC1_SDWP (117L) -#define MUX_PD21I_SDHC1_SDWP (8L) -#define PINMUX_PD21I_SDHC1_SDWP ((PIN_PD21I_SDHC1_SDWP << 16) | MUX_PD21I_SDHC1_SDWP) -#define PORT_PD21I_SDHC1_SDWP ((1UL) << 21) - -/* ========== PORT definition for SERCOM0 peripheral ========== */ -#define PIN_PA04D_SERCOM0_PAD0 (4L) -#define MUX_PA04D_SERCOM0_PAD0 (3L) -#define PINMUX_PA04D_SERCOM0_PAD0 ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0) -#define PORT_PA04D_SERCOM0_PAD0 ((1UL) << 4) - -#define PIN_PC17D_SERCOM0_PAD0 (81L) -#define MUX_PC17D_SERCOM0_PAD0 (3L) -#define PINMUX_PC17D_SERCOM0_PAD0 ((PIN_PC17D_SERCOM0_PAD0 << 16) | MUX_PC17D_SERCOM0_PAD0) -#define PORT_PC17D_SERCOM0_PAD0 ((1UL) << 17) - -#define PIN_PA08C_SERCOM0_PAD0 (8L) -#define MUX_PA08C_SERCOM0_PAD0 (2L) -#define PINMUX_PA08C_SERCOM0_PAD0 ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0) -#define PORT_PA08C_SERCOM0_PAD0 ((1UL) << 8) - -#define PIN_PB24C_SERCOM0_PAD0 (56L) -#define MUX_PB24C_SERCOM0_PAD0 (2L) -#define PINMUX_PB24C_SERCOM0_PAD0 ((PIN_PB24C_SERCOM0_PAD0 << 16) | MUX_PB24C_SERCOM0_PAD0) -#define PORT_PB24C_SERCOM0_PAD0 ((1UL) << 24) - -#define PIN_PA05D_SERCOM0_PAD1 (5L) -#define MUX_PA05D_SERCOM0_PAD1 (3L) -#define PINMUX_PA05D_SERCOM0_PAD1 ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1) -#define PORT_PA05D_SERCOM0_PAD1 ((1UL) << 5) - -#define PIN_PC16D_SERCOM0_PAD1 (80L) -#define MUX_PC16D_SERCOM0_PAD1 (3L) -#define PINMUX_PC16D_SERCOM0_PAD1 ((PIN_PC16D_SERCOM0_PAD1 << 16) | MUX_PC16D_SERCOM0_PAD1) -#define PORT_PC16D_SERCOM0_PAD1 ((1UL) << 16) - -#define PIN_PA09C_SERCOM0_PAD1 (9L) -#define MUX_PA09C_SERCOM0_PAD1 (2L) -#define PINMUX_PA09C_SERCOM0_PAD1 ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1) -#define PORT_PA09C_SERCOM0_PAD1 ((1UL) << 9) - -#define PIN_PB25C_SERCOM0_PAD1 (57L) -#define MUX_PB25C_SERCOM0_PAD1 (2L) -#define PINMUX_PB25C_SERCOM0_PAD1 ((PIN_PB25C_SERCOM0_PAD1 << 16) | MUX_PB25C_SERCOM0_PAD1) -#define PORT_PB25C_SERCOM0_PAD1 ((1UL) << 25) - -#define PIN_PA06D_SERCOM0_PAD2 (6L) -#define MUX_PA06D_SERCOM0_PAD2 (3L) -#define PINMUX_PA06D_SERCOM0_PAD2 ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2) -#define PORT_PA06D_SERCOM0_PAD2 ((1UL) << 6) - -#define PIN_PC18D_SERCOM0_PAD2 (82L) -#define MUX_PC18D_SERCOM0_PAD2 (3L) -#define PINMUX_PC18D_SERCOM0_PAD2 ((PIN_PC18D_SERCOM0_PAD2 << 16) | MUX_PC18D_SERCOM0_PAD2) -#define PORT_PC18D_SERCOM0_PAD2 ((1UL) << 18) - -#define PIN_PA10C_SERCOM0_PAD2 (10L) -#define MUX_PA10C_SERCOM0_PAD2 (2L) -#define PINMUX_PA10C_SERCOM0_PAD2 ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2) -#define PORT_PA10C_SERCOM0_PAD2 ((1UL) << 10) - -#define PIN_PC24C_SERCOM0_PAD2 (88L) -#define MUX_PC24C_SERCOM0_PAD2 (2L) -#define PINMUX_PC24C_SERCOM0_PAD2 ((PIN_PC24C_SERCOM0_PAD2 << 16) | MUX_PC24C_SERCOM0_PAD2) -#define PORT_PC24C_SERCOM0_PAD2 ((1UL) << 24) - -#define PIN_PA07D_SERCOM0_PAD3 (7L) -#define MUX_PA07D_SERCOM0_PAD3 (3L) -#define PINMUX_PA07D_SERCOM0_PAD3 ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3) -#define PORT_PA07D_SERCOM0_PAD3 ((1UL) << 7) - -#define PIN_PC19D_SERCOM0_PAD3 (83L) -#define MUX_PC19D_SERCOM0_PAD3 (3L) -#define PINMUX_PC19D_SERCOM0_PAD3 ((PIN_PC19D_SERCOM0_PAD3 << 16) | MUX_PC19D_SERCOM0_PAD3) -#define PORT_PC19D_SERCOM0_PAD3 ((1UL) << 19) - -#define PIN_PA11C_SERCOM0_PAD3 (11L) -#define MUX_PA11C_SERCOM0_PAD3 (2L) -#define PINMUX_PA11C_SERCOM0_PAD3 ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3) -#define PORT_PA11C_SERCOM0_PAD3 ((1UL) << 11) - -#define PIN_PC25C_SERCOM0_PAD3 (89L) -#define MUX_PC25C_SERCOM0_PAD3 (2L) -#define PINMUX_PC25C_SERCOM0_PAD3 ((PIN_PC25C_SERCOM0_PAD3 << 16) | MUX_PC25C_SERCOM0_PAD3) -#define PORT_PC25C_SERCOM0_PAD3 ((1UL) << 25) - -/* ========== PORT definition for SERCOM1 peripheral ========== */ -#define PIN_PA00D_SERCOM1_PAD0 (0L) -#define MUX_PA00D_SERCOM1_PAD0 (3L) -#define PINMUX_PA00D_SERCOM1_PAD0 ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0) -#define PORT_PA00D_SERCOM1_PAD0 ((1UL) << 0) - -#define PIN_PA16C_SERCOM1_PAD0 (16L) -#define MUX_PA16C_SERCOM1_PAD0 (2L) -#define PINMUX_PA16C_SERCOM1_PAD0 ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0) -#define PORT_PA16C_SERCOM1_PAD0 ((1UL) << 16) - -#define PIN_PC22C_SERCOM1_PAD0 (86L) -#define MUX_PC22C_SERCOM1_PAD0 (2L) -#define PINMUX_PC22C_SERCOM1_PAD0 ((PIN_PC22C_SERCOM1_PAD0 << 16) | MUX_PC22C_SERCOM1_PAD0) -#define PORT_PC22C_SERCOM1_PAD0 ((1UL) << 22) - -#define PIN_PC27C_SERCOM1_PAD0 (91L) -#define MUX_PC27C_SERCOM1_PAD0 (2L) -#define PINMUX_PC27C_SERCOM1_PAD0 ((PIN_PC27C_SERCOM1_PAD0 << 16) | MUX_PC27C_SERCOM1_PAD0) -#define PORT_PC27C_SERCOM1_PAD0 ((1UL) << 27) - -#define PIN_PA01D_SERCOM1_PAD1 (1L) -#define MUX_PA01D_SERCOM1_PAD1 (3L) -#define PINMUX_PA01D_SERCOM1_PAD1 ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1) -#define PORT_PA01D_SERCOM1_PAD1 ((1UL) << 1) - -#define PIN_PA17C_SERCOM1_PAD1 (17L) -#define MUX_PA17C_SERCOM1_PAD1 (2L) -#define PINMUX_PA17C_SERCOM1_PAD1 ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1) -#define PORT_PA17C_SERCOM1_PAD1 ((1UL) << 17) - -#define PIN_PC23C_SERCOM1_PAD1 (87L) -#define MUX_PC23C_SERCOM1_PAD1 (2L) -#define PINMUX_PC23C_SERCOM1_PAD1 ((PIN_PC23C_SERCOM1_PAD1 << 16) | MUX_PC23C_SERCOM1_PAD1) -#define PORT_PC23C_SERCOM1_PAD1 ((1UL) << 23) - -#define PIN_PC28C_SERCOM1_PAD1 (92L) -#define MUX_PC28C_SERCOM1_PAD1 (2L) -#define PINMUX_PC28C_SERCOM1_PAD1 ((PIN_PC28C_SERCOM1_PAD1 << 16) | MUX_PC28C_SERCOM1_PAD1) -#define PORT_PC28C_SERCOM1_PAD1 ((1UL) << 28) - -#define PIN_PA30D_SERCOM1_PAD2 (30L) -#define MUX_PA30D_SERCOM1_PAD2 (3L) -#define PINMUX_PA30D_SERCOM1_PAD2 ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2) -#define PORT_PA30D_SERCOM1_PAD2 ((1UL) << 30) - -#define PIN_PA18C_SERCOM1_PAD2 (18L) -#define MUX_PA18C_SERCOM1_PAD2 (2L) -#define PINMUX_PA18C_SERCOM1_PAD2 ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2) -#define PORT_PA18C_SERCOM1_PAD2 ((1UL) << 18) - -#define PIN_PB22C_SERCOM1_PAD2 (54L) -#define MUX_PB22C_SERCOM1_PAD2 (2L) -#define PINMUX_PB22C_SERCOM1_PAD2 ((PIN_PB22C_SERCOM1_PAD2 << 16) | MUX_PB22C_SERCOM1_PAD2) -#define PORT_PB22C_SERCOM1_PAD2 ((1UL) << 22) - -#define PIN_PD20C_SERCOM1_PAD2 (116L) -#define MUX_PD20C_SERCOM1_PAD2 (2L) -#define PINMUX_PD20C_SERCOM1_PAD2 ((PIN_PD20C_SERCOM1_PAD2 << 16) | MUX_PD20C_SERCOM1_PAD2) -#define PORT_PD20C_SERCOM1_PAD2 ((1UL) << 20) - -#define PIN_PA31D_SERCOM1_PAD3 (31L) -#define MUX_PA31D_SERCOM1_PAD3 (3L) -#define PINMUX_PA31D_SERCOM1_PAD3 ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3) -#define PORT_PA31D_SERCOM1_PAD3 ((1UL) << 31) - -#define PIN_PA19C_SERCOM1_PAD3 (19L) -#define MUX_PA19C_SERCOM1_PAD3 (2L) -#define PINMUX_PA19C_SERCOM1_PAD3 ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3) -#define PORT_PA19C_SERCOM1_PAD3 ((1UL) << 19) - -#define PIN_PB23C_SERCOM1_PAD3 (55L) -#define MUX_PB23C_SERCOM1_PAD3 (2L) -#define PINMUX_PB23C_SERCOM1_PAD3 ((PIN_PB23C_SERCOM1_PAD3 << 16) | MUX_PB23C_SERCOM1_PAD3) -#define PORT_PB23C_SERCOM1_PAD3 ((1UL) << 23) - -#define PIN_PD21C_SERCOM1_PAD3 (117L) -#define MUX_PD21C_SERCOM1_PAD3 (2L) -#define PINMUX_PD21C_SERCOM1_PAD3 ((PIN_PD21C_SERCOM1_PAD3 << 16) | MUX_PD21C_SERCOM1_PAD3) -#define PORT_PD21C_SERCOM1_PAD3 ((1UL) << 21) - -/* ========== PORT definition for SERCOM2 peripheral ========== */ -#define PIN_PA09D_SERCOM2_PAD0 (9L) -#define MUX_PA09D_SERCOM2_PAD0 (3L) -#define PINMUX_PA09D_SERCOM2_PAD0 ((PIN_PA09D_SERCOM2_PAD0 << 16) | MUX_PA09D_SERCOM2_PAD0) -#define PORT_PA09D_SERCOM2_PAD0 ((1UL) << 9) - -#define PIN_PB25D_SERCOM2_PAD0 (57L) -#define MUX_PB25D_SERCOM2_PAD0 (3L) -#define PINMUX_PB25D_SERCOM2_PAD0 ((PIN_PB25D_SERCOM2_PAD0 << 16) | MUX_PB25D_SERCOM2_PAD0) -#define PORT_PB25D_SERCOM2_PAD0 ((1UL) << 25) - -#define PIN_PA12C_SERCOM2_PAD0 (12L) -#define MUX_PA12C_SERCOM2_PAD0 (2L) -#define PINMUX_PA12C_SERCOM2_PAD0 ((PIN_PA12C_SERCOM2_PAD0 << 16) | MUX_PA12C_SERCOM2_PAD0) -#define PORT_PA12C_SERCOM2_PAD0 ((1UL) << 12) - -#define PIN_PB26C_SERCOM2_PAD0 (58L) -#define MUX_PB26C_SERCOM2_PAD0 (2L) -#define PINMUX_PB26C_SERCOM2_PAD0 ((PIN_PB26C_SERCOM2_PAD0 << 16) | MUX_PB26C_SERCOM2_PAD0) -#define PORT_PB26C_SERCOM2_PAD0 ((1UL) << 26) - -#define PIN_PA08D_SERCOM2_PAD1 (8L) -#define MUX_PA08D_SERCOM2_PAD1 (3L) -#define PINMUX_PA08D_SERCOM2_PAD1 ((PIN_PA08D_SERCOM2_PAD1 << 16) | MUX_PA08D_SERCOM2_PAD1) -#define PORT_PA08D_SERCOM2_PAD1 ((1UL) << 8) - -#define PIN_PB24D_SERCOM2_PAD1 (56L) -#define MUX_PB24D_SERCOM2_PAD1 (3L) -#define PINMUX_PB24D_SERCOM2_PAD1 ((PIN_PB24D_SERCOM2_PAD1 << 16) | MUX_PB24D_SERCOM2_PAD1) -#define PORT_PB24D_SERCOM2_PAD1 ((1UL) << 24) - -#define PIN_PA13C_SERCOM2_PAD1 (13L) -#define MUX_PA13C_SERCOM2_PAD1 (2L) -#define PINMUX_PA13C_SERCOM2_PAD1 ((PIN_PA13C_SERCOM2_PAD1 << 16) | MUX_PA13C_SERCOM2_PAD1) -#define PORT_PA13C_SERCOM2_PAD1 ((1UL) << 13) - -#define PIN_PB27C_SERCOM2_PAD1 (59L) -#define MUX_PB27C_SERCOM2_PAD1 (2L) -#define PINMUX_PB27C_SERCOM2_PAD1 ((PIN_PB27C_SERCOM2_PAD1 << 16) | MUX_PB27C_SERCOM2_PAD1) -#define PORT_PB27C_SERCOM2_PAD1 ((1UL) << 27) - -#define PIN_PA10D_SERCOM2_PAD2 (10L) -#define MUX_PA10D_SERCOM2_PAD2 (3L) -#define PINMUX_PA10D_SERCOM2_PAD2 ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2) -#define PORT_PA10D_SERCOM2_PAD2 ((1UL) << 10) - -#define PIN_PC24D_SERCOM2_PAD2 (88L) -#define MUX_PC24D_SERCOM2_PAD2 (3L) -#define PINMUX_PC24D_SERCOM2_PAD2 ((PIN_PC24D_SERCOM2_PAD2 << 16) | MUX_PC24D_SERCOM2_PAD2) -#define PORT_PC24D_SERCOM2_PAD2 ((1UL) << 24) - -#define PIN_PB28C_SERCOM2_PAD2 (60L) -#define MUX_PB28C_SERCOM2_PAD2 (2L) -#define PINMUX_PB28C_SERCOM2_PAD2 ((PIN_PB28C_SERCOM2_PAD2 << 16) | MUX_PB28C_SERCOM2_PAD2) -#define PORT_PB28C_SERCOM2_PAD2 ((1UL) << 28) - -#define PIN_PA14C_SERCOM2_PAD2 (14L) -#define MUX_PA14C_SERCOM2_PAD2 (2L) -#define PINMUX_PA14C_SERCOM2_PAD2 ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2) -#define PORT_PA14C_SERCOM2_PAD2 ((1UL) << 14) - -#define PIN_PA11D_SERCOM2_PAD3 (11L) -#define MUX_PA11D_SERCOM2_PAD3 (3L) -#define PINMUX_PA11D_SERCOM2_PAD3 ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3) -#define PORT_PA11D_SERCOM2_PAD3 ((1UL) << 11) - -#define PIN_PC25D_SERCOM2_PAD3 (89L) -#define MUX_PC25D_SERCOM2_PAD3 (3L) -#define PINMUX_PC25D_SERCOM2_PAD3 ((PIN_PC25D_SERCOM2_PAD3 << 16) | MUX_PC25D_SERCOM2_PAD3) -#define PORT_PC25D_SERCOM2_PAD3 ((1UL) << 25) - -#define PIN_PB29C_SERCOM2_PAD3 (61L) -#define MUX_PB29C_SERCOM2_PAD3 (2L) -#define PINMUX_PB29C_SERCOM2_PAD3 ((PIN_PB29C_SERCOM2_PAD3 << 16) | MUX_PB29C_SERCOM2_PAD3) -#define PORT_PB29C_SERCOM2_PAD3 ((1UL) << 29) - -#define PIN_PA15C_SERCOM2_PAD3 (15L) -#define MUX_PA15C_SERCOM2_PAD3 (2L) -#define PINMUX_PA15C_SERCOM2_PAD3 ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3) -#define PORT_PA15C_SERCOM2_PAD3 ((1UL) << 15) - -/* ========== PORT definition for SERCOM3 peripheral ========== */ -#define PIN_PA17D_SERCOM3_PAD0 (17L) -#define MUX_PA17D_SERCOM3_PAD0 (3L) -#define PINMUX_PA17D_SERCOM3_PAD0 ((PIN_PA17D_SERCOM3_PAD0 << 16) | MUX_PA17D_SERCOM3_PAD0) -#define PORT_PA17D_SERCOM3_PAD0 ((1UL) << 17) - -#define PIN_PC23D_SERCOM3_PAD0 (87L) -#define MUX_PC23D_SERCOM3_PAD0 (3L) -#define PINMUX_PC23D_SERCOM3_PAD0 ((PIN_PC23D_SERCOM3_PAD0 << 16) | MUX_PC23D_SERCOM3_PAD0) -#define PORT_PC23D_SERCOM3_PAD0 ((1UL) << 23) - -#define PIN_PA22C_SERCOM3_PAD0 (22L) -#define MUX_PA22C_SERCOM3_PAD0 (2L) -#define PINMUX_PA22C_SERCOM3_PAD0 ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0) -#define PORT_PA22C_SERCOM3_PAD0 ((1UL) << 22) - -#define PIN_PB20C_SERCOM3_PAD0 (52L) -#define MUX_PB20C_SERCOM3_PAD0 (2L) -#define PINMUX_PB20C_SERCOM3_PAD0 ((PIN_PB20C_SERCOM3_PAD0 << 16) | MUX_PB20C_SERCOM3_PAD0) -#define PORT_PB20C_SERCOM3_PAD0 ((1UL) << 20) - -#define PIN_PA16D_SERCOM3_PAD1 (16L) -#define MUX_PA16D_SERCOM3_PAD1 (3L) -#define PINMUX_PA16D_SERCOM3_PAD1 ((PIN_PA16D_SERCOM3_PAD1 << 16) | MUX_PA16D_SERCOM3_PAD1) -#define PORT_PA16D_SERCOM3_PAD1 ((1UL) << 16) - -#define PIN_PC22D_SERCOM3_PAD1 (86L) -#define MUX_PC22D_SERCOM3_PAD1 (3L) -#define PINMUX_PC22D_SERCOM3_PAD1 ((PIN_PC22D_SERCOM3_PAD1 << 16) | MUX_PC22D_SERCOM3_PAD1) -#define PORT_PC22D_SERCOM3_PAD1 ((1UL) << 22) - -#define PIN_PA23C_SERCOM3_PAD1 (23L) -#define MUX_PA23C_SERCOM3_PAD1 (2L) -#define PINMUX_PA23C_SERCOM3_PAD1 ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1) -#define PORT_PA23C_SERCOM3_PAD1 ((1UL) << 23) - -#define PIN_PB21C_SERCOM3_PAD1 (53L) -#define MUX_PB21C_SERCOM3_PAD1 (2L) -#define PINMUX_PB21C_SERCOM3_PAD1 ((PIN_PB21C_SERCOM3_PAD1 << 16) | MUX_PB21C_SERCOM3_PAD1) -#define PORT_PB21C_SERCOM3_PAD1 ((1UL) << 21) - -#define PIN_PA18D_SERCOM3_PAD2 (18L) -#define MUX_PA18D_SERCOM3_PAD2 (3L) -#define PINMUX_PA18D_SERCOM3_PAD2 ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2) -#define PORT_PA18D_SERCOM3_PAD2 ((1UL) << 18) - -#define PIN_PA20D_SERCOM3_PAD2 (20L) -#define MUX_PA20D_SERCOM3_PAD2 (3L) -#define PINMUX_PA20D_SERCOM3_PAD2 ((PIN_PA20D_SERCOM3_PAD2 << 16) | MUX_PA20D_SERCOM3_PAD2) -#define PORT_PA20D_SERCOM3_PAD2 ((1UL) << 20) - -#define PIN_PD20D_SERCOM3_PAD2 (116L) -#define MUX_PD20D_SERCOM3_PAD2 (3L) -#define PINMUX_PD20D_SERCOM3_PAD2 ((PIN_PD20D_SERCOM3_PAD2 << 16) | MUX_PD20D_SERCOM3_PAD2) -#define PORT_PD20D_SERCOM3_PAD2 ((1UL) << 20) - -#define PIN_PA24C_SERCOM3_PAD2 (24L) -#define MUX_PA24C_SERCOM3_PAD2 (2L) -#define PINMUX_PA24C_SERCOM3_PAD2 ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2) -#define PORT_PA24C_SERCOM3_PAD2 ((1UL) << 24) - -#define PIN_PA19D_SERCOM3_PAD3 (19L) -#define MUX_PA19D_SERCOM3_PAD3 (3L) -#define PINMUX_PA19D_SERCOM3_PAD3 ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3) -#define PORT_PA19D_SERCOM3_PAD3 ((1UL) << 19) - -#define PIN_PA21D_SERCOM3_PAD3 (21L) -#define MUX_PA21D_SERCOM3_PAD3 (3L) -#define PINMUX_PA21D_SERCOM3_PAD3 ((PIN_PA21D_SERCOM3_PAD3 << 16) | MUX_PA21D_SERCOM3_PAD3) -#define PORT_PA21D_SERCOM3_PAD3 ((1UL) << 21) - -#define PIN_PD21D_SERCOM3_PAD3 (117L) -#define MUX_PD21D_SERCOM3_PAD3 (3L) -#define PINMUX_PD21D_SERCOM3_PAD3 ((PIN_PD21D_SERCOM3_PAD3 << 16) | MUX_PD21D_SERCOM3_PAD3) -#define PORT_PD21D_SERCOM3_PAD3 ((1UL) << 21) - -#define PIN_PA25C_SERCOM3_PAD3 (25L) -#define MUX_PA25C_SERCOM3_PAD3 (2L) -#define PINMUX_PA25C_SERCOM3_PAD3 ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3) -#define PORT_PA25C_SERCOM3_PAD3 ((1UL) << 25) - -/* ========== PORT definition for SERCOM4 peripheral ========== */ -#define PIN_PA13D_SERCOM4_PAD0 (13L) -#define MUX_PA13D_SERCOM4_PAD0 (3L) -#define PINMUX_PA13D_SERCOM4_PAD0 ((PIN_PA13D_SERCOM4_PAD0 << 16) | MUX_PA13D_SERCOM4_PAD0) -#define PORT_PA13D_SERCOM4_PAD0 ((1UL) << 13) - -#define PIN_PB08D_SERCOM4_PAD0 (40L) -#define MUX_PB08D_SERCOM4_PAD0 (3L) -#define PINMUX_PB08D_SERCOM4_PAD0 ((PIN_PB08D_SERCOM4_PAD0 << 16) | MUX_PB08D_SERCOM4_PAD0) -#define PORT_PB08D_SERCOM4_PAD0 ((1UL) << 8) - -#define PIN_PB27D_SERCOM4_PAD0 (59L) -#define MUX_PB27D_SERCOM4_PAD0 (3L) -#define PINMUX_PB27D_SERCOM4_PAD0 ((PIN_PB27D_SERCOM4_PAD0 << 16) | MUX_PB27D_SERCOM4_PAD0) -#define PORT_PB27D_SERCOM4_PAD0 ((1UL) << 27) - -#define PIN_PB12C_SERCOM4_PAD0 (44L) -#define MUX_PB12C_SERCOM4_PAD0 (2L) -#define PINMUX_PB12C_SERCOM4_PAD0 ((PIN_PB12C_SERCOM4_PAD0 << 16) | MUX_PB12C_SERCOM4_PAD0) -#define PORT_PB12C_SERCOM4_PAD0 ((1UL) << 12) - -#define PIN_PA12D_SERCOM4_PAD1 (12L) -#define MUX_PA12D_SERCOM4_PAD1 (3L) -#define PINMUX_PA12D_SERCOM4_PAD1 ((PIN_PA12D_SERCOM4_PAD1 << 16) | MUX_PA12D_SERCOM4_PAD1) -#define PORT_PA12D_SERCOM4_PAD1 ((1UL) << 12) - -#define PIN_PB09D_SERCOM4_PAD1 (41L) -#define MUX_PB09D_SERCOM4_PAD1 (3L) -#define PINMUX_PB09D_SERCOM4_PAD1 ((PIN_PB09D_SERCOM4_PAD1 << 16) | MUX_PB09D_SERCOM4_PAD1) -#define PORT_PB09D_SERCOM4_PAD1 ((1UL) << 9) - -#define PIN_PB26D_SERCOM4_PAD1 (58L) -#define MUX_PB26D_SERCOM4_PAD1 (3L) -#define PINMUX_PB26D_SERCOM4_PAD1 ((PIN_PB26D_SERCOM4_PAD1 << 16) | MUX_PB26D_SERCOM4_PAD1) -#define PORT_PB26D_SERCOM4_PAD1 ((1UL) << 26) - -#define PIN_PB13C_SERCOM4_PAD1 (45L) -#define MUX_PB13C_SERCOM4_PAD1 (2L) -#define PINMUX_PB13C_SERCOM4_PAD1 ((PIN_PB13C_SERCOM4_PAD1 << 16) | MUX_PB13C_SERCOM4_PAD1) -#define PORT_PB13C_SERCOM4_PAD1 ((1UL) << 13) - -#define PIN_PA14D_SERCOM4_PAD2 (14L) -#define MUX_PA14D_SERCOM4_PAD2 (3L) -#define PINMUX_PA14D_SERCOM4_PAD2 ((PIN_PA14D_SERCOM4_PAD2 << 16) | MUX_PA14D_SERCOM4_PAD2) -#define PORT_PA14D_SERCOM4_PAD2 ((1UL) << 14) - -#define PIN_PB10D_SERCOM4_PAD2 (42L) -#define MUX_PB10D_SERCOM4_PAD2 (3L) -#define PINMUX_PB10D_SERCOM4_PAD2 ((PIN_PB10D_SERCOM4_PAD2 << 16) | MUX_PB10D_SERCOM4_PAD2) -#define PORT_PB10D_SERCOM4_PAD2 ((1UL) << 10) - -#define PIN_PB28D_SERCOM4_PAD2 (60L) -#define MUX_PB28D_SERCOM4_PAD2 (3L) -#define PINMUX_PB28D_SERCOM4_PAD2 ((PIN_PB28D_SERCOM4_PAD2 << 16) | MUX_PB28D_SERCOM4_PAD2) -#define PORT_PB28D_SERCOM4_PAD2 ((1UL) << 28) - -#define PIN_PB14C_SERCOM4_PAD2 (46L) -#define MUX_PB14C_SERCOM4_PAD2 (2L) -#define PINMUX_PB14C_SERCOM4_PAD2 ((PIN_PB14C_SERCOM4_PAD2 << 16) | MUX_PB14C_SERCOM4_PAD2) -#define PORT_PB14C_SERCOM4_PAD2 ((1UL) << 14) - -#define PIN_PB11D_SERCOM4_PAD3 (43L) -#define MUX_PB11D_SERCOM4_PAD3 (3L) -#define PINMUX_PB11D_SERCOM4_PAD3 ((PIN_PB11D_SERCOM4_PAD3 << 16) | MUX_PB11D_SERCOM4_PAD3) -#define PORT_PB11D_SERCOM4_PAD3 ((1UL) << 11) - -#define PIN_PB29D_SERCOM4_PAD3 (61L) -#define MUX_PB29D_SERCOM4_PAD3 (3L) -#define PINMUX_PB29D_SERCOM4_PAD3 ((PIN_PB29D_SERCOM4_PAD3 << 16) | MUX_PB29D_SERCOM4_PAD3) -#define PORT_PB29D_SERCOM4_PAD3 ((1UL) << 29) - -#define PIN_PA15D_SERCOM4_PAD3 (15L) -#define MUX_PA15D_SERCOM4_PAD3 (3L) -#define PINMUX_PA15D_SERCOM4_PAD3 ((PIN_PA15D_SERCOM4_PAD3 << 16) | MUX_PA15D_SERCOM4_PAD3) -#define PORT_PA15D_SERCOM4_PAD3 ((1UL) << 15) - -#define PIN_PB15C_SERCOM4_PAD3 (47L) -#define MUX_PB15C_SERCOM4_PAD3 (2L) -#define PINMUX_PB15C_SERCOM4_PAD3 ((PIN_PB15C_SERCOM4_PAD3 << 16) | MUX_PB15C_SERCOM4_PAD3) -#define PORT_PB15C_SERCOM4_PAD3 ((1UL) << 15) - -/* ========== PORT definition for SERCOM5 peripheral ========== */ -#define PIN_PA23D_SERCOM5_PAD0 (23L) -#define MUX_PA23D_SERCOM5_PAD0 (3L) -#define PINMUX_PA23D_SERCOM5_PAD0 ((PIN_PA23D_SERCOM5_PAD0 << 16) | MUX_PA23D_SERCOM5_PAD0) -#define PORT_PA23D_SERCOM5_PAD0 ((1UL) << 23) - -#define PIN_PB02D_SERCOM5_PAD0 (34L) -#define MUX_PB02D_SERCOM5_PAD0 (3L) -#define PINMUX_PB02D_SERCOM5_PAD0 ((PIN_PB02D_SERCOM5_PAD0 << 16) | MUX_PB02D_SERCOM5_PAD0) -#define PORT_PB02D_SERCOM5_PAD0 ((1UL) << 2) - -#define PIN_PB31D_SERCOM5_PAD0 (63L) -#define MUX_PB31D_SERCOM5_PAD0 (3L) -#define PINMUX_PB31D_SERCOM5_PAD0 ((PIN_PB31D_SERCOM5_PAD0 << 16) | MUX_PB31D_SERCOM5_PAD0) -#define PORT_PB31D_SERCOM5_PAD0 ((1UL) << 31) - -#define PIN_PB16C_SERCOM5_PAD0 (48L) -#define MUX_PB16C_SERCOM5_PAD0 (2L) -#define PINMUX_PB16C_SERCOM5_PAD0 ((PIN_PB16C_SERCOM5_PAD0 << 16) | MUX_PB16C_SERCOM5_PAD0) -#define PORT_PB16C_SERCOM5_PAD0 ((1UL) << 16) - -#define PIN_PA22D_SERCOM5_PAD1 (22L) -#define MUX_PA22D_SERCOM5_PAD1 (3L) -#define PINMUX_PA22D_SERCOM5_PAD1 ((PIN_PA22D_SERCOM5_PAD1 << 16) | MUX_PA22D_SERCOM5_PAD1) -#define PORT_PA22D_SERCOM5_PAD1 ((1UL) << 22) - -#define PIN_PB03D_SERCOM5_PAD1 (35L) -#define MUX_PB03D_SERCOM5_PAD1 (3L) -#define PINMUX_PB03D_SERCOM5_PAD1 ((PIN_PB03D_SERCOM5_PAD1 << 16) | MUX_PB03D_SERCOM5_PAD1) -#define PORT_PB03D_SERCOM5_PAD1 ((1UL) << 3) - -#define PIN_PB30D_SERCOM5_PAD1 (62L) -#define MUX_PB30D_SERCOM5_PAD1 (3L) -#define PINMUX_PB30D_SERCOM5_PAD1 ((PIN_PB30D_SERCOM5_PAD1 << 16) | MUX_PB30D_SERCOM5_PAD1) -#define PORT_PB30D_SERCOM5_PAD1 ((1UL) << 30) - -#define PIN_PB17C_SERCOM5_PAD1 (49L) -#define MUX_PB17C_SERCOM5_PAD1 (2L) -#define PINMUX_PB17C_SERCOM5_PAD1 ((PIN_PB17C_SERCOM5_PAD1 << 16) | MUX_PB17C_SERCOM5_PAD1) -#define PORT_PB17C_SERCOM5_PAD1 ((1UL) << 17) - -#define PIN_PA24D_SERCOM5_PAD2 (24L) -#define MUX_PA24D_SERCOM5_PAD2 (3L) -#define PINMUX_PA24D_SERCOM5_PAD2 ((PIN_PA24D_SERCOM5_PAD2 << 16) | MUX_PA24D_SERCOM5_PAD2) -#define PORT_PA24D_SERCOM5_PAD2 ((1UL) << 24) - -#define PIN_PB00D_SERCOM5_PAD2 (32L) -#define MUX_PB00D_SERCOM5_PAD2 (3L) -#define PINMUX_PB00D_SERCOM5_PAD2 ((PIN_PB00D_SERCOM5_PAD2 << 16) | MUX_PB00D_SERCOM5_PAD2) -#define PORT_PB00D_SERCOM5_PAD2 ((1UL) << 0) - -#define PIN_PB22D_SERCOM5_PAD2 (54L) -#define MUX_PB22D_SERCOM5_PAD2 (3L) -#define PINMUX_PB22D_SERCOM5_PAD2 ((PIN_PB22D_SERCOM5_PAD2 << 16) | MUX_PB22D_SERCOM5_PAD2) -#define PORT_PB22D_SERCOM5_PAD2 ((1UL) << 22) - -#define PIN_PA20C_SERCOM5_PAD2 (20L) -#define MUX_PA20C_SERCOM5_PAD2 (2L) -#define PINMUX_PA20C_SERCOM5_PAD2 ((PIN_PA20C_SERCOM5_PAD2 << 16) | MUX_PA20C_SERCOM5_PAD2) -#define PORT_PA20C_SERCOM5_PAD2 ((1UL) << 20) - -#define PIN_PB18C_SERCOM5_PAD2 (50L) -#define MUX_PB18C_SERCOM5_PAD2 (2L) -#define PINMUX_PB18C_SERCOM5_PAD2 ((PIN_PB18C_SERCOM5_PAD2 << 16) | MUX_PB18C_SERCOM5_PAD2) -#define PORT_PB18C_SERCOM5_PAD2 ((1UL) << 18) - -#define PIN_PA25D_SERCOM5_PAD3 (25L) -#define MUX_PA25D_SERCOM5_PAD3 (3L) -#define PINMUX_PA25D_SERCOM5_PAD3 ((PIN_PA25D_SERCOM5_PAD3 << 16) | MUX_PA25D_SERCOM5_PAD3) -#define PORT_PA25D_SERCOM5_PAD3 ((1UL) << 25) - -#define PIN_PB01D_SERCOM5_PAD3 (33L) -#define MUX_PB01D_SERCOM5_PAD3 (3L) -#define PINMUX_PB01D_SERCOM5_PAD3 ((PIN_PB01D_SERCOM5_PAD3 << 16) | MUX_PB01D_SERCOM5_PAD3) -#define PORT_PB01D_SERCOM5_PAD3 ((1UL) << 1) - -#define PIN_PB23D_SERCOM5_PAD3 (55L) -#define MUX_PB23D_SERCOM5_PAD3 (3L) -#define PINMUX_PB23D_SERCOM5_PAD3 ((PIN_PB23D_SERCOM5_PAD3 << 16) | MUX_PB23D_SERCOM5_PAD3) -#define PORT_PB23D_SERCOM5_PAD3 ((1UL) << 23) - -#define PIN_PA21C_SERCOM5_PAD3 (21L) -#define MUX_PA21C_SERCOM5_PAD3 (2L) -#define PINMUX_PA21C_SERCOM5_PAD3 ((PIN_PA21C_SERCOM5_PAD3 << 16) | MUX_PA21C_SERCOM5_PAD3) -#define PORT_PA21C_SERCOM5_PAD3 ((1UL) << 21) - -#define PIN_PB19C_SERCOM5_PAD3 (51L) -#define MUX_PB19C_SERCOM5_PAD3 (2L) -#define PINMUX_PB19C_SERCOM5_PAD3 ((PIN_PB19C_SERCOM5_PAD3 << 16) | MUX_PB19C_SERCOM5_PAD3) -#define PORT_PB19C_SERCOM5_PAD3 ((1UL) << 19) - -/* ========== PORT definition for SERCOM6 peripheral ========== */ -#define PIN_PD09D_SERCOM6_PAD0 (105L) -#define MUX_PD09D_SERCOM6_PAD0 (3L) -#define PINMUX_PD09D_SERCOM6_PAD0 ((PIN_PD09D_SERCOM6_PAD0 << 16) | MUX_PD09D_SERCOM6_PAD0) -#define PORT_PD09D_SERCOM6_PAD0 ((1UL) << 9) - -#define PIN_PC13D_SERCOM6_PAD0 (77L) -#define MUX_PC13D_SERCOM6_PAD0 (3L) -#define PINMUX_PC13D_SERCOM6_PAD0 ((PIN_PC13D_SERCOM6_PAD0 << 16) | MUX_PC13D_SERCOM6_PAD0) -#define PORT_PC13D_SERCOM6_PAD0 ((1UL) << 13) - -#define PIN_PC04C_SERCOM6_PAD0 (68L) -#define MUX_PC04C_SERCOM6_PAD0 (2L) -#define PINMUX_PC04C_SERCOM6_PAD0 ((PIN_PC04C_SERCOM6_PAD0 << 16) | MUX_PC04C_SERCOM6_PAD0) -#define PORT_PC04C_SERCOM6_PAD0 ((1UL) << 4) - -#define PIN_PC16C_SERCOM6_PAD0 (80L) -#define MUX_PC16C_SERCOM6_PAD0 (2L) -#define PINMUX_PC16C_SERCOM6_PAD0 ((PIN_PC16C_SERCOM6_PAD0 << 16) | MUX_PC16C_SERCOM6_PAD0) -#define PORT_PC16C_SERCOM6_PAD0 ((1UL) << 16) - -#define PIN_PD08D_SERCOM6_PAD1 (104L) -#define MUX_PD08D_SERCOM6_PAD1 (3L) -#define PINMUX_PD08D_SERCOM6_PAD1 ((PIN_PD08D_SERCOM6_PAD1 << 16) | MUX_PD08D_SERCOM6_PAD1) -#define PORT_PD08D_SERCOM6_PAD1 ((1UL) << 8) - -#define PIN_PC12D_SERCOM6_PAD1 (76L) -#define MUX_PC12D_SERCOM6_PAD1 (3L) -#define PINMUX_PC12D_SERCOM6_PAD1 ((PIN_PC12D_SERCOM6_PAD1 << 16) | MUX_PC12D_SERCOM6_PAD1) -#define PORT_PC12D_SERCOM6_PAD1 ((1UL) << 12) - -#define PIN_PC05C_SERCOM6_PAD1 (69L) -#define MUX_PC05C_SERCOM6_PAD1 (2L) -#define PINMUX_PC05C_SERCOM6_PAD1 ((PIN_PC05C_SERCOM6_PAD1 << 16) | MUX_PC05C_SERCOM6_PAD1) -#define PORT_PC05C_SERCOM6_PAD1 ((1UL) << 5) - -#define PIN_PC17C_SERCOM6_PAD1 (81L) -#define MUX_PC17C_SERCOM6_PAD1 (2L) -#define PINMUX_PC17C_SERCOM6_PAD1 ((PIN_PC17C_SERCOM6_PAD1 << 16) | MUX_PC17C_SERCOM6_PAD1) -#define PORT_PC17C_SERCOM6_PAD1 ((1UL) << 17) - -#define PIN_PC14D_SERCOM6_PAD2 (78L) -#define MUX_PC14D_SERCOM6_PAD2 (3L) -#define PINMUX_PC14D_SERCOM6_PAD2 ((PIN_PC14D_SERCOM6_PAD2 << 16) | MUX_PC14D_SERCOM6_PAD2) -#define PORT_PC14D_SERCOM6_PAD2 ((1UL) << 14) - -#define PIN_PD10D_SERCOM6_PAD2 (106L) -#define MUX_PD10D_SERCOM6_PAD2 (3L) -#define PINMUX_PD10D_SERCOM6_PAD2 ((PIN_PD10D_SERCOM6_PAD2 << 16) | MUX_PD10D_SERCOM6_PAD2) -#define PORT_PD10D_SERCOM6_PAD2 ((1UL) << 10) - -#define PIN_PC06C_SERCOM6_PAD2 (70L) -#define MUX_PC06C_SERCOM6_PAD2 (2L) -#define PINMUX_PC06C_SERCOM6_PAD2 ((PIN_PC06C_SERCOM6_PAD2 << 16) | MUX_PC06C_SERCOM6_PAD2) -#define PORT_PC06C_SERCOM6_PAD2 ((1UL) << 6) - -#define PIN_PC10C_SERCOM6_PAD2 (74L) -#define MUX_PC10C_SERCOM6_PAD2 (2L) -#define PINMUX_PC10C_SERCOM6_PAD2 ((PIN_PC10C_SERCOM6_PAD2 << 16) | MUX_PC10C_SERCOM6_PAD2) -#define PORT_PC10C_SERCOM6_PAD2 ((1UL) << 10) - -#define PIN_PC18C_SERCOM6_PAD2 (82L) -#define MUX_PC18C_SERCOM6_PAD2 (2L) -#define PINMUX_PC18C_SERCOM6_PAD2 ((PIN_PC18C_SERCOM6_PAD2 << 16) | MUX_PC18C_SERCOM6_PAD2) -#define PORT_PC18C_SERCOM6_PAD2 ((1UL) << 18) - -#define PIN_PC15D_SERCOM6_PAD3 (79L) -#define MUX_PC15D_SERCOM6_PAD3 (3L) -#define PINMUX_PC15D_SERCOM6_PAD3 ((PIN_PC15D_SERCOM6_PAD3 << 16) | MUX_PC15D_SERCOM6_PAD3) -#define PORT_PC15D_SERCOM6_PAD3 ((1UL) << 15) - -#define PIN_PD11D_SERCOM6_PAD3 (107L) -#define MUX_PD11D_SERCOM6_PAD3 (3L) -#define PINMUX_PD11D_SERCOM6_PAD3 ((PIN_PD11D_SERCOM6_PAD3 << 16) | MUX_PD11D_SERCOM6_PAD3) -#define PORT_PD11D_SERCOM6_PAD3 ((1UL) << 11) - -#define PIN_PC07C_SERCOM6_PAD3 (71L) -#define MUX_PC07C_SERCOM6_PAD3 (2L) -#define PINMUX_PC07C_SERCOM6_PAD3 ((PIN_PC07C_SERCOM6_PAD3 << 16) | MUX_PC07C_SERCOM6_PAD3) -#define PORT_PC07C_SERCOM6_PAD3 ((1UL) << 7) - -#define PIN_PC11C_SERCOM6_PAD3 (75L) -#define MUX_PC11C_SERCOM6_PAD3 (2L) -#define PINMUX_PC11C_SERCOM6_PAD3 ((PIN_PC11C_SERCOM6_PAD3 << 16) | MUX_PC11C_SERCOM6_PAD3) -#define PORT_PC11C_SERCOM6_PAD3 ((1UL) << 11) - -#define PIN_PC19C_SERCOM6_PAD3 (83L) -#define MUX_PC19C_SERCOM6_PAD3 (2L) -#define PINMUX_PC19C_SERCOM6_PAD3 ((PIN_PC19C_SERCOM6_PAD3 << 16) | MUX_PC19C_SERCOM6_PAD3) -#define PORT_PC19C_SERCOM6_PAD3 ((1UL) << 19) - -/* ========== PORT definition for SERCOM7 peripheral ========== */ -#define PIN_PB21D_SERCOM7_PAD0 (53L) -#define MUX_PB21D_SERCOM7_PAD0 (3L) -#define PINMUX_PB21D_SERCOM7_PAD0 ((PIN_PB21D_SERCOM7_PAD0 << 16) | MUX_PB21D_SERCOM7_PAD0) -#define PORT_PB21D_SERCOM7_PAD0 ((1UL) << 21) - -#define PIN_PD08C_SERCOM7_PAD0 (104L) -#define MUX_PD08C_SERCOM7_PAD0 (2L) -#define PINMUX_PD08C_SERCOM7_PAD0 ((PIN_PD08C_SERCOM7_PAD0 << 16) | MUX_PD08C_SERCOM7_PAD0) -#define PORT_PD08C_SERCOM7_PAD0 ((1UL) << 8) - -#define PIN_PB30C_SERCOM7_PAD0 (62L) -#define MUX_PB30C_SERCOM7_PAD0 (2L) -#define PINMUX_PB30C_SERCOM7_PAD0 ((PIN_PB30C_SERCOM7_PAD0 << 16) | MUX_PB30C_SERCOM7_PAD0) -#define PORT_PB30C_SERCOM7_PAD0 ((1UL) << 30) - -#define PIN_PC12C_SERCOM7_PAD0 (76L) -#define MUX_PC12C_SERCOM7_PAD0 (2L) -#define PINMUX_PC12C_SERCOM7_PAD0 ((PIN_PC12C_SERCOM7_PAD0 << 16) | MUX_PC12C_SERCOM7_PAD0) -#define PORT_PC12C_SERCOM7_PAD0 ((1UL) << 12) - -#define PIN_PB20D_SERCOM7_PAD1 (52L) -#define MUX_PB20D_SERCOM7_PAD1 (3L) -#define PINMUX_PB20D_SERCOM7_PAD1 ((PIN_PB20D_SERCOM7_PAD1 << 16) | MUX_PB20D_SERCOM7_PAD1) -#define PORT_PB20D_SERCOM7_PAD1 ((1UL) << 20) - -#define PIN_PD09C_SERCOM7_PAD1 (105L) -#define MUX_PD09C_SERCOM7_PAD1 (2L) -#define PINMUX_PD09C_SERCOM7_PAD1 ((PIN_PD09C_SERCOM7_PAD1 << 16) | MUX_PD09C_SERCOM7_PAD1) -#define PORT_PD09C_SERCOM7_PAD1 ((1UL) << 9) - -#define PIN_PB31C_SERCOM7_PAD1 (63L) -#define MUX_PB31C_SERCOM7_PAD1 (2L) -#define PINMUX_PB31C_SERCOM7_PAD1 ((PIN_PB31C_SERCOM7_PAD1 << 16) | MUX_PB31C_SERCOM7_PAD1) -#define PORT_PB31C_SERCOM7_PAD1 ((1UL) << 31) - -#define PIN_PC13C_SERCOM7_PAD1 (77L) -#define MUX_PC13C_SERCOM7_PAD1 (2L) -#define PINMUX_PC13C_SERCOM7_PAD1 ((PIN_PC13C_SERCOM7_PAD1 << 16) | MUX_PC13C_SERCOM7_PAD1) -#define PORT_PC13C_SERCOM7_PAD1 ((1UL) << 13) - -#define PIN_PB18D_SERCOM7_PAD2 (50L) -#define MUX_PB18D_SERCOM7_PAD2 (3L) -#define PINMUX_PB18D_SERCOM7_PAD2 ((PIN_PB18D_SERCOM7_PAD2 << 16) | MUX_PB18D_SERCOM7_PAD2) -#define PORT_PB18D_SERCOM7_PAD2 ((1UL) << 18) - -#define PIN_PC10D_SERCOM7_PAD2 (74L) -#define MUX_PC10D_SERCOM7_PAD2 (3L) -#define PINMUX_PC10D_SERCOM7_PAD2 ((PIN_PC10D_SERCOM7_PAD2 << 16) | MUX_PC10D_SERCOM7_PAD2) -#define PORT_PC10D_SERCOM7_PAD2 ((1UL) << 10) - -#define PIN_PC14C_SERCOM7_PAD2 (78L) -#define MUX_PC14C_SERCOM7_PAD2 (2L) -#define PINMUX_PC14C_SERCOM7_PAD2 ((PIN_PC14C_SERCOM7_PAD2 << 16) | MUX_PC14C_SERCOM7_PAD2) -#define PORT_PC14C_SERCOM7_PAD2 ((1UL) << 14) - -#define PIN_PD10C_SERCOM7_PAD2 (106L) -#define MUX_PD10C_SERCOM7_PAD2 (2L) -#define PINMUX_PD10C_SERCOM7_PAD2 ((PIN_PD10C_SERCOM7_PAD2 << 16) | MUX_PD10C_SERCOM7_PAD2) -#define PORT_PD10C_SERCOM7_PAD2 ((1UL) << 10) - -#define PIN_PA30C_SERCOM7_PAD2 (30L) -#define MUX_PA30C_SERCOM7_PAD2 (2L) -#define PINMUX_PA30C_SERCOM7_PAD2 ((PIN_PA30C_SERCOM7_PAD2 << 16) | MUX_PA30C_SERCOM7_PAD2) -#define PORT_PA30C_SERCOM7_PAD2 ((1UL) << 30) - -#define PIN_PB19D_SERCOM7_PAD3 (51L) -#define MUX_PB19D_SERCOM7_PAD3 (3L) -#define PINMUX_PB19D_SERCOM7_PAD3 ((PIN_PB19D_SERCOM7_PAD3 << 16) | MUX_PB19D_SERCOM7_PAD3) -#define PORT_PB19D_SERCOM7_PAD3 ((1UL) << 19) - -#define PIN_PC11D_SERCOM7_PAD3 (75L) -#define MUX_PC11D_SERCOM7_PAD3 (3L) -#define PINMUX_PC11D_SERCOM7_PAD3 ((PIN_PC11D_SERCOM7_PAD3 << 16) | MUX_PC11D_SERCOM7_PAD3) -#define PORT_PC11D_SERCOM7_PAD3 ((1UL) << 11) - -#define PIN_PC15C_SERCOM7_PAD3 (79L) -#define MUX_PC15C_SERCOM7_PAD3 (2L) -#define PINMUX_PC15C_SERCOM7_PAD3 ((PIN_PC15C_SERCOM7_PAD3 << 16) | MUX_PC15C_SERCOM7_PAD3) -#define PORT_PC15C_SERCOM7_PAD3 ((1UL) << 15) - -#define PIN_PD11C_SERCOM7_PAD3 (107L) -#define MUX_PD11C_SERCOM7_PAD3 (2L) -#define PINMUX_PD11C_SERCOM7_PAD3 ((PIN_PD11C_SERCOM7_PAD3 << 16) | MUX_PD11C_SERCOM7_PAD3) -#define PORT_PD11C_SERCOM7_PAD3 ((1UL) << 11) - -#define PIN_PA31C_SERCOM7_PAD3 (31L) -#define MUX_PA31C_SERCOM7_PAD3 (2L) -#define PINMUX_PA31C_SERCOM7_PAD3 ((PIN_PA31C_SERCOM7_PAD3 << 16) | MUX_PA31C_SERCOM7_PAD3) -#define PORT_PA31C_SERCOM7_PAD3 ((1UL) << 31) - -/* ========== PORT definition for TC0 peripheral ========== */ -#define PIN_PA04E_TC0_WO0 (4L) -#define MUX_PA04E_TC0_WO0 (4L) -#define PINMUX_PA04E_TC0_WO0 ((PIN_PA04E_TC0_WO0 << 16) | MUX_PA04E_TC0_WO0) -#define PORT_PA04E_TC0_WO0 ((1UL) << 4) - -#define PIN_PA08E_TC0_WO0 (8L) -#define MUX_PA08E_TC0_WO0 (4L) -#define PINMUX_PA08E_TC0_WO0 ((PIN_PA08E_TC0_WO0 << 16) | MUX_PA08E_TC0_WO0) -#define PORT_PA08E_TC0_WO0 ((1UL) << 8) - -#define PIN_PB30E_TC0_WO0 (62L) -#define MUX_PB30E_TC0_WO0 (4L) -#define PINMUX_PB30E_TC0_WO0 ((PIN_PB30E_TC0_WO0 << 16) | MUX_PB30E_TC0_WO0) -#define PORT_PB30E_TC0_WO0 ((1UL) << 30) - -#define PIN_PA05E_TC0_WO1 (5L) -#define MUX_PA05E_TC0_WO1 (4L) -#define PINMUX_PA05E_TC0_WO1 ((PIN_PA05E_TC0_WO1 << 16) | MUX_PA05E_TC0_WO1) -#define PORT_PA05E_TC0_WO1 ((1UL) << 5) - -#define PIN_PA09E_TC0_WO1 (9L) -#define MUX_PA09E_TC0_WO1 (4L) -#define PINMUX_PA09E_TC0_WO1 ((PIN_PA09E_TC0_WO1 << 16) | MUX_PA09E_TC0_WO1) -#define PORT_PA09E_TC0_WO1 ((1UL) << 9) - -#define PIN_PB31E_TC0_WO1 (63L) -#define MUX_PB31E_TC0_WO1 (4L) -#define PINMUX_PB31E_TC0_WO1 ((PIN_PB31E_TC0_WO1 << 16) | MUX_PB31E_TC0_WO1) -#define PORT_PB31E_TC0_WO1 ((1UL) << 31) - -/* ========== PORT definition for TC1 peripheral ========== */ -#define PIN_PA06E_TC1_WO0 (6L) -#define MUX_PA06E_TC1_WO0 (4L) -#define PINMUX_PA06E_TC1_WO0 ((PIN_PA06E_TC1_WO0 << 16) | MUX_PA06E_TC1_WO0) -#define PORT_PA06E_TC1_WO0 ((1UL) << 6) - -#define PIN_PA10E_TC1_WO0 (10L) -#define MUX_PA10E_TC1_WO0 (4L) -#define PINMUX_PA10E_TC1_WO0 ((PIN_PA10E_TC1_WO0 << 16) | MUX_PA10E_TC1_WO0) -#define PORT_PA10E_TC1_WO0 ((1UL) << 10) - -#define PIN_PA07E_TC1_WO1 (7L) -#define MUX_PA07E_TC1_WO1 (4L) -#define PINMUX_PA07E_TC1_WO1 ((PIN_PA07E_TC1_WO1 << 16) | MUX_PA07E_TC1_WO1) -#define PORT_PA07E_TC1_WO1 ((1UL) << 7) - -#define PIN_PA11E_TC1_WO1 (11L) -#define MUX_PA11E_TC1_WO1 (4L) -#define PINMUX_PA11E_TC1_WO1 ((PIN_PA11E_TC1_WO1 << 16) | MUX_PA11E_TC1_WO1) -#define PORT_PA11E_TC1_WO1 ((1UL) << 11) - -/* ========== PORT definition for TC2 peripheral ========== */ -#define PIN_PA12E_TC2_WO0 (12L) -#define MUX_PA12E_TC2_WO0 (4L) -#define PINMUX_PA12E_TC2_WO0 ((PIN_PA12E_TC2_WO0 << 16) | MUX_PA12E_TC2_WO0) -#define PORT_PA12E_TC2_WO0 ((1UL) << 12) - -#define PIN_PA16E_TC2_WO0 (16L) -#define MUX_PA16E_TC2_WO0 (4L) -#define PINMUX_PA16E_TC2_WO0 ((PIN_PA16E_TC2_WO0 << 16) | MUX_PA16E_TC2_WO0) -#define PORT_PA16E_TC2_WO0 ((1UL) << 16) - -#define PIN_PA00E_TC2_WO0 (0L) -#define MUX_PA00E_TC2_WO0 (4L) -#define PINMUX_PA00E_TC2_WO0 ((PIN_PA00E_TC2_WO0 << 16) | MUX_PA00E_TC2_WO0) -#define PORT_PA00E_TC2_WO0 ((1UL) << 0) - -#define PIN_PA01E_TC2_WO1 (1L) -#define MUX_PA01E_TC2_WO1 (4L) -#define PINMUX_PA01E_TC2_WO1 ((PIN_PA01E_TC2_WO1 << 16) | MUX_PA01E_TC2_WO1) -#define PORT_PA01E_TC2_WO1 ((1UL) << 1) - -#define PIN_PA13E_TC2_WO1 (13L) -#define MUX_PA13E_TC2_WO1 (4L) -#define PINMUX_PA13E_TC2_WO1 ((PIN_PA13E_TC2_WO1 << 16) | MUX_PA13E_TC2_WO1) -#define PORT_PA13E_TC2_WO1 ((1UL) << 13) - -#define PIN_PA17E_TC2_WO1 (17L) -#define MUX_PA17E_TC2_WO1 (4L) -#define PINMUX_PA17E_TC2_WO1 ((PIN_PA17E_TC2_WO1 << 16) | MUX_PA17E_TC2_WO1) -#define PORT_PA17E_TC2_WO1 ((1UL) << 17) - -/* ========== PORT definition for TC3 peripheral ========== */ -#define PIN_PA18E_TC3_WO0 (18L) -#define MUX_PA18E_TC3_WO0 (4L) -#define PINMUX_PA18E_TC3_WO0 ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0) -#define PORT_PA18E_TC3_WO0 ((1UL) << 18) - -#define PIN_PA14E_TC3_WO0 (14L) -#define MUX_PA14E_TC3_WO0 (4L) -#define PINMUX_PA14E_TC3_WO0 ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0) -#define PORT_PA14E_TC3_WO0 ((1UL) << 14) - -#define PIN_PA15E_TC3_WO1 (15L) -#define MUX_PA15E_TC3_WO1 (4L) -#define PINMUX_PA15E_TC3_WO1 ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1) -#define PORT_PA15E_TC3_WO1 ((1UL) << 15) - -#define PIN_PA19E_TC3_WO1 (19L) -#define MUX_PA19E_TC3_WO1 (4L) -#define PINMUX_PA19E_TC3_WO1 ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1) -#define PORT_PA19E_TC3_WO1 ((1UL) << 19) - -/* ========== PORT definition for TC4 peripheral ========== */ -#define PIN_PA22E_TC4_WO0 (22L) -#define MUX_PA22E_TC4_WO0 (4L) -#define PINMUX_PA22E_TC4_WO0 ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0) -#define PORT_PA22E_TC4_WO0 ((1UL) << 22) - -#define PIN_PB08E_TC4_WO0 (40L) -#define MUX_PB08E_TC4_WO0 (4L) -#define PINMUX_PB08E_TC4_WO0 ((PIN_PB08E_TC4_WO0 << 16) | MUX_PB08E_TC4_WO0) -#define PORT_PB08E_TC4_WO0 ((1UL) << 8) - -#define PIN_PB12E_TC4_WO0 (44L) -#define MUX_PB12E_TC4_WO0 (4L) -#define PINMUX_PB12E_TC4_WO0 ((PIN_PB12E_TC4_WO0 << 16) | MUX_PB12E_TC4_WO0) -#define PORT_PB12E_TC4_WO0 ((1UL) << 12) - -#define PIN_PA23E_TC4_WO1 (23L) -#define MUX_PA23E_TC4_WO1 (4L) -#define PINMUX_PA23E_TC4_WO1 ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1) -#define PORT_PA23E_TC4_WO1 ((1UL) << 23) - -#define PIN_PB09E_TC4_WO1 (41L) -#define MUX_PB09E_TC4_WO1 (4L) -#define PINMUX_PB09E_TC4_WO1 ((PIN_PB09E_TC4_WO1 << 16) | MUX_PB09E_TC4_WO1) -#define PORT_PB09E_TC4_WO1 ((1UL) << 9) - -#define PIN_PB13E_TC4_WO1 (45L) -#define MUX_PB13E_TC4_WO1 (4L) -#define PINMUX_PB13E_TC4_WO1 ((PIN_PB13E_TC4_WO1 << 16) | MUX_PB13E_TC4_WO1) -#define PORT_PB13E_TC4_WO1 ((1UL) << 13) - -/* ========== PORT definition for TC5 peripheral ========== */ -#define PIN_PA24E_TC5_WO0 (24L) -#define MUX_PA24E_TC5_WO0 (4L) -#define PINMUX_PA24E_TC5_WO0 ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0) -#define PORT_PA24E_TC5_WO0 ((1UL) << 24) - -#define PIN_PB10E_TC5_WO0 (42L) -#define MUX_PB10E_TC5_WO0 (4L) -#define PINMUX_PB10E_TC5_WO0 ((PIN_PB10E_TC5_WO0 << 16) | MUX_PB10E_TC5_WO0) -#define PORT_PB10E_TC5_WO0 ((1UL) << 10) - -#define PIN_PB14E_TC5_WO0 (46L) -#define MUX_PB14E_TC5_WO0 (4L) -#define PINMUX_PB14E_TC5_WO0 ((PIN_PB14E_TC5_WO0 << 16) | MUX_PB14E_TC5_WO0) -#define PORT_PB14E_TC5_WO0 ((1UL) << 14) - -#define PIN_PA25E_TC5_WO1 (25L) -#define MUX_PA25E_TC5_WO1 (4L) -#define PINMUX_PA25E_TC5_WO1 ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1) -#define PORT_PA25E_TC5_WO1 ((1UL) << 25) - -#define PIN_PB11E_TC5_WO1 (43L) -#define MUX_PB11E_TC5_WO1 (4L) -#define PINMUX_PB11E_TC5_WO1 ((PIN_PB11E_TC5_WO1 << 16) | MUX_PB11E_TC5_WO1) -#define PORT_PB11E_TC5_WO1 ((1UL) << 11) - -#define PIN_PB15E_TC5_WO1 (47L) -#define MUX_PB15E_TC5_WO1 (4L) -#define PINMUX_PB15E_TC5_WO1 ((PIN_PB15E_TC5_WO1 << 16) | MUX_PB15E_TC5_WO1) -#define PORT_PB15E_TC5_WO1 ((1UL) << 15) - -/* ========== PORT definition for TC6 peripheral ========== */ -#define PIN_PA30E_TC6_WO0 (30L) -#define MUX_PA30E_TC6_WO0 (4L) -#define PINMUX_PA30E_TC6_WO0 ((PIN_PA30E_TC6_WO0 << 16) | MUX_PA30E_TC6_WO0) -#define PORT_PA30E_TC6_WO0 ((1UL) << 30) - -#define PIN_PB02E_TC6_WO0 (34L) -#define MUX_PB02E_TC6_WO0 (4L) -#define PINMUX_PB02E_TC6_WO0 ((PIN_PB02E_TC6_WO0 << 16) | MUX_PB02E_TC6_WO0) -#define PORT_PB02E_TC6_WO0 ((1UL) << 2) - -#define PIN_PB16E_TC6_WO0 (48L) -#define MUX_PB16E_TC6_WO0 (4L) -#define PINMUX_PB16E_TC6_WO0 ((PIN_PB16E_TC6_WO0 << 16) | MUX_PB16E_TC6_WO0) -#define PORT_PB16E_TC6_WO0 ((1UL) << 16) - -#define PIN_PA31E_TC6_WO1 (31L) -#define MUX_PA31E_TC6_WO1 (4L) -#define PINMUX_PA31E_TC6_WO1 ((PIN_PA31E_TC6_WO1 << 16) | MUX_PA31E_TC6_WO1) -#define PORT_PA31E_TC6_WO1 ((1UL) << 31) - -#define PIN_PB03E_TC6_WO1 (35L) -#define MUX_PB03E_TC6_WO1 (4L) -#define PINMUX_PB03E_TC6_WO1 ((PIN_PB03E_TC6_WO1 << 16) | MUX_PB03E_TC6_WO1) -#define PORT_PB03E_TC6_WO1 ((1UL) << 3) - -#define PIN_PB17E_TC6_WO1 (49L) -#define MUX_PB17E_TC6_WO1 (4L) -#define PINMUX_PB17E_TC6_WO1 ((PIN_PB17E_TC6_WO1 << 16) | MUX_PB17E_TC6_WO1) -#define PORT_PB17E_TC6_WO1 ((1UL) << 17) - -/* ========== PORT definition for TC7 peripheral ========== */ -#define PIN_PA20E_TC7_WO0 (20L) -#define MUX_PA20E_TC7_WO0 (4L) -#define PINMUX_PA20E_TC7_WO0 ((PIN_PA20E_TC7_WO0 << 16) | MUX_PA20E_TC7_WO0) -#define PORT_PA20E_TC7_WO0 ((1UL) << 20) - -#define PIN_PB00E_TC7_WO0 (32L) -#define MUX_PB00E_TC7_WO0 (4L) -#define PINMUX_PB00E_TC7_WO0 ((PIN_PB00E_TC7_WO0 << 16) | MUX_PB00E_TC7_WO0) -#define PORT_PB00E_TC7_WO0 ((1UL) << 0) - -#define PIN_PB22E_TC7_WO0 (54L) -#define MUX_PB22E_TC7_WO0 (4L) -#define PINMUX_PB22E_TC7_WO0 ((PIN_PB22E_TC7_WO0 << 16) | MUX_PB22E_TC7_WO0) -#define PORT_PB22E_TC7_WO0 ((1UL) << 22) - -#define PIN_PA21E_TC7_WO1 (21L) -#define MUX_PA21E_TC7_WO1 (4L) -#define PINMUX_PA21E_TC7_WO1 ((PIN_PA21E_TC7_WO1 << 16) | MUX_PA21E_TC7_WO1) -#define PORT_PA21E_TC7_WO1 ((1UL) << 21) - -#define PIN_PB01E_TC7_WO1 (33L) -#define MUX_PB01E_TC7_WO1 (4L) -#define PINMUX_PB01E_TC7_WO1 ((PIN_PB01E_TC7_WO1 << 16) | MUX_PB01E_TC7_WO1) -#define PORT_PB01E_TC7_WO1 ((1UL) << 1) - -#define PIN_PB23E_TC7_WO1 (55L) -#define MUX_PB23E_TC7_WO1 (4L) -#define PINMUX_PB23E_TC7_WO1 ((PIN_PB23E_TC7_WO1 << 16) | MUX_PB23E_TC7_WO1) -#define PORT_PB23E_TC7_WO1 ((1UL) << 23) - -/* ========== PORT definition for TCC0 peripheral ========== */ -#define PIN_PA20G_TCC0_WO0 (20L) -#define MUX_PA20G_TCC0_WO0 (6L) -#define PINMUX_PA20G_TCC0_WO0 ((PIN_PA20G_TCC0_WO0 << 16) | MUX_PA20G_TCC0_WO0) -#define PORT_PA20G_TCC0_WO0 ((1UL) << 20) - -#define PIN_PB12G_TCC0_WO0 (44L) -#define MUX_PB12G_TCC0_WO0 (6L) -#define PINMUX_PB12G_TCC0_WO0 ((PIN_PB12G_TCC0_WO0 << 16) | MUX_PB12G_TCC0_WO0) -#define PORT_PB12G_TCC0_WO0 ((1UL) << 12) - -#define PIN_PA08F_TCC0_WO0 (8L) -#define MUX_PA08F_TCC0_WO0 (5L) -#define PINMUX_PA08F_TCC0_WO0 ((PIN_PA08F_TCC0_WO0 << 16) | MUX_PA08F_TCC0_WO0) -#define PORT_PA08F_TCC0_WO0 ((1UL) << 8) - -#define PIN_PC04F_TCC0_WO0 (68L) -#define MUX_PC04F_TCC0_WO0 (5L) -#define PINMUX_PC04F_TCC0_WO0 ((PIN_PC04F_TCC0_WO0 << 16) | MUX_PC04F_TCC0_WO0) -#define PORT_PC04F_TCC0_WO0 ((1UL) << 4) - -#define PIN_PC10F_TCC0_WO0 (74L) -#define MUX_PC10F_TCC0_WO0 (5L) -#define PINMUX_PC10F_TCC0_WO0 ((PIN_PC10F_TCC0_WO0 << 16) | MUX_PC10F_TCC0_WO0) -#define PORT_PC10F_TCC0_WO0 ((1UL) << 10) - -#define PIN_PC16F_TCC0_WO0 (80L) -#define MUX_PC16F_TCC0_WO0 (5L) -#define PINMUX_PC16F_TCC0_WO0 ((PIN_PC16F_TCC0_WO0 << 16) | MUX_PC16F_TCC0_WO0) -#define PORT_PC16F_TCC0_WO0 ((1UL) << 16) - -#define PIN_PA21G_TCC0_WO1 (21L) -#define MUX_PA21G_TCC0_WO1 (6L) -#define PINMUX_PA21G_TCC0_WO1 ((PIN_PA21G_TCC0_WO1 << 16) | MUX_PA21G_TCC0_WO1) -#define PORT_PA21G_TCC0_WO1 ((1UL) << 21) - -#define PIN_PB13G_TCC0_WO1 (45L) -#define MUX_PB13G_TCC0_WO1 (6L) -#define PINMUX_PB13G_TCC0_WO1 ((PIN_PB13G_TCC0_WO1 << 16) | MUX_PB13G_TCC0_WO1) -#define PORT_PB13G_TCC0_WO1 ((1UL) << 13) - -#define PIN_PA09F_TCC0_WO1 (9L) -#define MUX_PA09F_TCC0_WO1 (5L) -#define PINMUX_PA09F_TCC0_WO1 ((PIN_PA09F_TCC0_WO1 << 16) | MUX_PA09F_TCC0_WO1) -#define PORT_PA09F_TCC0_WO1 ((1UL) << 9) - -#define PIN_PC11F_TCC0_WO1 (75L) -#define MUX_PC11F_TCC0_WO1 (5L) -#define PINMUX_PC11F_TCC0_WO1 ((PIN_PC11F_TCC0_WO1 << 16) | MUX_PC11F_TCC0_WO1) -#define PORT_PC11F_TCC0_WO1 ((1UL) << 11) - -#define PIN_PC17F_TCC0_WO1 (81L) -#define MUX_PC17F_TCC0_WO1 (5L) -#define PINMUX_PC17F_TCC0_WO1 ((PIN_PC17F_TCC0_WO1 << 16) | MUX_PC17F_TCC0_WO1) -#define PORT_PC17F_TCC0_WO1 ((1UL) << 17) - -#define PIN_PD08F_TCC0_WO1 (104L) -#define MUX_PD08F_TCC0_WO1 (5L) -#define PINMUX_PD08F_TCC0_WO1 ((PIN_PD08F_TCC0_WO1 << 16) | MUX_PD08F_TCC0_WO1) -#define PORT_PD08F_TCC0_WO1 ((1UL) << 8) - -#define PIN_PA22G_TCC0_WO2 (22L) -#define MUX_PA22G_TCC0_WO2 (6L) -#define PINMUX_PA22G_TCC0_WO2 ((PIN_PA22G_TCC0_WO2 << 16) | MUX_PA22G_TCC0_WO2) -#define PORT_PA22G_TCC0_WO2 ((1UL) << 22) - -#define PIN_PB14G_TCC0_WO2 (46L) -#define MUX_PB14G_TCC0_WO2 (6L) -#define PINMUX_PB14G_TCC0_WO2 ((PIN_PB14G_TCC0_WO2 << 16) | MUX_PB14G_TCC0_WO2) -#define PORT_PB14G_TCC0_WO2 ((1UL) << 14) - -#define PIN_PA10F_TCC0_WO2 (10L) -#define MUX_PA10F_TCC0_WO2 (5L) -#define PINMUX_PA10F_TCC0_WO2 ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2) -#define PORT_PA10F_TCC0_WO2 ((1UL) << 10) - -#define PIN_PC12F_TCC0_WO2 (76L) -#define MUX_PC12F_TCC0_WO2 (5L) -#define PINMUX_PC12F_TCC0_WO2 ((PIN_PC12F_TCC0_WO2 << 16) | MUX_PC12F_TCC0_WO2) -#define PORT_PC12F_TCC0_WO2 ((1UL) << 12) - -#define PIN_PC18F_TCC0_WO2 (82L) -#define MUX_PC18F_TCC0_WO2 (5L) -#define PINMUX_PC18F_TCC0_WO2 ((PIN_PC18F_TCC0_WO2 << 16) | MUX_PC18F_TCC0_WO2) -#define PORT_PC18F_TCC0_WO2 ((1UL) << 18) - -#define PIN_PD09F_TCC0_WO2 (105L) -#define MUX_PD09F_TCC0_WO2 (5L) -#define PINMUX_PD09F_TCC0_WO2 ((PIN_PD09F_TCC0_WO2 << 16) | MUX_PD09F_TCC0_WO2) -#define PORT_PD09F_TCC0_WO2 ((1UL) << 9) - -#define PIN_PA23G_TCC0_WO3 (23L) -#define MUX_PA23G_TCC0_WO3 (6L) -#define PINMUX_PA23G_TCC0_WO3 ((PIN_PA23G_TCC0_WO3 << 16) | MUX_PA23G_TCC0_WO3) -#define PORT_PA23G_TCC0_WO3 ((1UL) << 23) - -#define PIN_PB15G_TCC0_WO3 (47L) -#define MUX_PB15G_TCC0_WO3 (6L) -#define PINMUX_PB15G_TCC0_WO3 ((PIN_PB15G_TCC0_WO3 << 16) | MUX_PB15G_TCC0_WO3) -#define PORT_PB15G_TCC0_WO3 ((1UL) << 15) - -#define PIN_PA11F_TCC0_WO3 (11L) -#define MUX_PA11F_TCC0_WO3 (5L) -#define PINMUX_PA11F_TCC0_WO3 ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3) -#define PORT_PA11F_TCC0_WO3 ((1UL) << 11) - -#define PIN_PC13F_TCC0_WO3 (77L) -#define MUX_PC13F_TCC0_WO3 (5L) -#define PINMUX_PC13F_TCC0_WO3 ((PIN_PC13F_TCC0_WO3 << 16) | MUX_PC13F_TCC0_WO3) -#define PORT_PC13F_TCC0_WO3 ((1UL) << 13) - -#define PIN_PC19F_TCC0_WO3 (83L) -#define MUX_PC19F_TCC0_WO3 (5L) -#define PINMUX_PC19F_TCC0_WO3 ((PIN_PC19F_TCC0_WO3 << 16) | MUX_PC19F_TCC0_WO3) -#define PORT_PC19F_TCC0_WO3 ((1UL) << 19) - -#define PIN_PD10F_TCC0_WO3 (106L) -#define MUX_PD10F_TCC0_WO3 (5L) -#define PINMUX_PD10F_TCC0_WO3 ((PIN_PD10F_TCC0_WO3 << 16) | MUX_PD10F_TCC0_WO3) -#define PORT_PD10F_TCC0_WO3 ((1UL) << 10) - -#define PIN_PA16G_TCC0_WO4 (16L) -#define MUX_PA16G_TCC0_WO4 (6L) -#define PINMUX_PA16G_TCC0_WO4 ((PIN_PA16G_TCC0_WO4 << 16) | MUX_PA16G_TCC0_WO4) -#define PORT_PA16G_TCC0_WO4 ((1UL) << 16) - -#define PIN_PB16G_TCC0_WO4 (48L) -#define MUX_PB16G_TCC0_WO4 (6L) -#define PINMUX_PB16G_TCC0_WO4 ((PIN_PB16G_TCC0_WO4 << 16) | MUX_PB16G_TCC0_WO4) -#define PORT_PB16G_TCC0_WO4 ((1UL) << 16) - -#define PIN_PB10F_TCC0_WO4 (42L) -#define MUX_PB10F_TCC0_WO4 (5L) -#define PINMUX_PB10F_TCC0_WO4 ((PIN_PB10F_TCC0_WO4 << 16) | MUX_PB10F_TCC0_WO4) -#define PORT_PB10F_TCC0_WO4 ((1UL) << 10) - -#define PIN_PC14F_TCC0_WO4 (78L) -#define MUX_PC14F_TCC0_WO4 (5L) -#define PINMUX_PC14F_TCC0_WO4 ((PIN_PC14F_TCC0_WO4 << 16) | MUX_PC14F_TCC0_WO4) -#define PORT_PC14F_TCC0_WO4 ((1UL) << 14) - -#define PIN_PC20F_TCC0_WO4 (84L) -#define MUX_PC20F_TCC0_WO4 (5L) -#define PINMUX_PC20F_TCC0_WO4 ((PIN_PC20F_TCC0_WO4 << 16) | MUX_PC20F_TCC0_WO4) -#define PORT_PC20F_TCC0_WO4 ((1UL) << 20) - -#define PIN_PD11F_TCC0_WO4 (107L) -#define MUX_PD11F_TCC0_WO4 (5L) -#define PINMUX_PD11F_TCC0_WO4 ((PIN_PD11F_TCC0_WO4 << 16) | MUX_PD11F_TCC0_WO4) -#define PORT_PD11F_TCC0_WO4 ((1UL) << 11) - -#define PIN_PA17G_TCC0_WO5 (17L) -#define MUX_PA17G_TCC0_WO5 (6L) -#define PINMUX_PA17G_TCC0_WO5 ((PIN_PA17G_TCC0_WO5 << 16) | MUX_PA17G_TCC0_WO5) -#define PORT_PA17G_TCC0_WO5 ((1UL) << 17) - -#define PIN_PB17G_TCC0_WO5 (49L) -#define MUX_PB17G_TCC0_WO5 (6L) -#define PINMUX_PB17G_TCC0_WO5 ((PIN_PB17G_TCC0_WO5 << 16) | MUX_PB17G_TCC0_WO5) -#define PORT_PB17G_TCC0_WO5 ((1UL) << 17) - -#define PIN_PB11F_TCC0_WO5 (43L) -#define MUX_PB11F_TCC0_WO5 (5L) -#define PINMUX_PB11F_TCC0_WO5 ((PIN_PB11F_TCC0_WO5 << 16) | MUX_PB11F_TCC0_WO5) -#define PORT_PB11F_TCC0_WO5 ((1UL) << 11) - -#define PIN_PC15F_TCC0_WO5 (79L) -#define MUX_PC15F_TCC0_WO5 (5L) -#define PINMUX_PC15F_TCC0_WO5 ((PIN_PC15F_TCC0_WO5 << 16) | MUX_PC15F_TCC0_WO5) -#define PORT_PC15F_TCC0_WO5 ((1UL) << 15) - -#define PIN_PC21F_TCC0_WO5 (85L) -#define MUX_PC21F_TCC0_WO5 (5L) -#define PINMUX_PC21F_TCC0_WO5 ((PIN_PC21F_TCC0_WO5 << 16) | MUX_PC21F_TCC0_WO5) -#define PORT_PC21F_TCC0_WO5 ((1UL) << 21) - -#define PIN_PD12F_TCC0_WO5 (108L) -#define MUX_PD12F_TCC0_WO5 (5L) -#define PINMUX_PD12F_TCC0_WO5 ((PIN_PD12F_TCC0_WO5 << 16) | MUX_PD12F_TCC0_WO5) -#define PORT_PD12F_TCC0_WO5 ((1UL) << 12) - -#define PIN_PA18G_TCC0_WO6 (18L) -#define MUX_PA18G_TCC0_WO6 (6L) -#define PINMUX_PA18G_TCC0_WO6 ((PIN_PA18G_TCC0_WO6 << 16) | MUX_PA18G_TCC0_WO6) -#define PORT_PA18G_TCC0_WO6 ((1UL) << 18) - -#define PIN_PB30G_TCC0_WO6 (62L) -#define MUX_PB30G_TCC0_WO6 (6L) -#define PINMUX_PB30G_TCC0_WO6 ((PIN_PB30G_TCC0_WO6 << 16) | MUX_PB30G_TCC0_WO6) -#define PORT_PB30G_TCC0_WO6 ((1UL) << 30) - -#define PIN_PA12F_TCC0_WO6 (12L) -#define MUX_PA12F_TCC0_WO6 (5L) -#define PINMUX_PA12F_TCC0_WO6 ((PIN_PA12F_TCC0_WO6 << 16) | MUX_PA12F_TCC0_WO6) -#define PORT_PA12F_TCC0_WO6 ((1UL) << 12) - -#define PIN_PC22F_TCC0_WO6 (86L) -#define MUX_PC22F_TCC0_WO6 (5L) -#define PINMUX_PC22F_TCC0_WO6 ((PIN_PC22F_TCC0_WO6 << 16) | MUX_PC22F_TCC0_WO6) -#define PORT_PC22F_TCC0_WO6 ((1UL) << 22) - -#define PIN_PA19G_TCC0_WO7 (19L) -#define MUX_PA19G_TCC0_WO7 (6L) -#define PINMUX_PA19G_TCC0_WO7 ((PIN_PA19G_TCC0_WO7 << 16) | MUX_PA19G_TCC0_WO7) -#define PORT_PA19G_TCC0_WO7 ((1UL) << 19) - -#define PIN_PB31G_TCC0_WO7 (63L) -#define MUX_PB31G_TCC0_WO7 (6L) -#define PINMUX_PB31G_TCC0_WO7 ((PIN_PB31G_TCC0_WO7 << 16) | MUX_PB31G_TCC0_WO7) -#define PORT_PB31G_TCC0_WO7 ((1UL) << 31) - -#define PIN_PA13F_TCC0_WO7 (13L) -#define MUX_PA13F_TCC0_WO7 (5L) -#define PINMUX_PA13F_TCC0_WO7 ((PIN_PA13F_TCC0_WO7 << 16) | MUX_PA13F_TCC0_WO7) -#define PORT_PA13F_TCC0_WO7 ((1UL) << 13) - -#define PIN_PC23F_TCC0_WO7 (87L) -#define MUX_PC23F_TCC0_WO7 (5L) -#define PINMUX_PC23F_TCC0_WO7 ((PIN_PC23F_TCC0_WO7 << 16) | MUX_PC23F_TCC0_WO7) -#define PORT_PC23F_TCC0_WO7 ((1UL) << 23) - -/* ========== PORT definition for TCC1 peripheral ========== */ -#define PIN_PB10G_TCC1_WO0 (42L) -#define MUX_PB10G_TCC1_WO0 (6L) -#define PINMUX_PB10G_TCC1_WO0 ((PIN_PB10G_TCC1_WO0 << 16) | MUX_PB10G_TCC1_WO0) -#define PORT_PB10G_TCC1_WO0 ((1UL) << 10) - -#define PIN_PC14G_TCC1_WO0 (78L) -#define MUX_PC14G_TCC1_WO0 (6L) -#define PINMUX_PC14G_TCC1_WO0 ((PIN_PC14G_TCC1_WO0 << 16) | MUX_PC14G_TCC1_WO0) -#define PORT_PC14G_TCC1_WO0 ((1UL) << 14) - -#define PIN_PA16F_TCC1_WO0 (16L) -#define MUX_PA16F_TCC1_WO0 (5L) -#define PINMUX_PA16F_TCC1_WO0 ((PIN_PA16F_TCC1_WO0 << 16) | MUX_PA16F_TCC1_WO0) -#define PORT_PA16F_TCC1_WO0 ((1UL) << 16) - -#define PIN_PB18F_TCC1_WO0 (50L) -#define MUX_PB18F_TCC1_WO0 (5L) -#define PINMUX_PB18F_TCC1_WO0 ((PIN_PB18F_TCC1_WO0 << 16) | MUX_PB18F_TCC1_WO0) -#define PORT_PB18F_TCC1_WO0 ((1UL) << 18) - -#define PIN_PD20F_TCC1_WO0 (116L) -#define MUX_PD20F_TCC1_WO0 (5L) -#define PINMUX_PD20F_TCC1_WO0 ((PIN_PD20F_TCC1_WO0 << 16) | MUX_PD20F_TCC1_WO0) -#define PORT_PD20F_TCC1_WO0 ((1UL) << 20) - -#define PIN_PB11G_TCC1_WO1 (43L) -#define MUX_PB11G_TCC1_WO1 (6L) -#define PINMUX_PB11G_TCC1_WO1 ((PIN_PB11G_TCC1_WO1 << 16) | MUX_PB11G_TCC1_WO1) -#define PORT_PB11G_TCC1_WO1 ((1UL) << 11) - -#define PIN_PC15G_TCC1_WO1 (79L) -#define MUX_PC15G_TCC1_WO1 (6L) -#define PINMUX_PC15G_TCC1_WO1 ((PIN_PC15G_TCC1_WO1 << 16) | MUX_PC15G_TCC1_WO1) -#define PORT_PC15G_TCC1_WO1 ((1UL) << 15) - -#define PIN_PA17F_TCC1_WO1 (17L) -#define MUX_PA17F_TCC1_WO1 (5L) -#define PINMUX_PA17F_TCC1_WO1 ((PIN_PA17F_TCC1_WO1 << 16) | MUX_PA17F_TCC1_WO1) -#define PORT_PA17F_TCC1_WO1 ((1UL) << 17) - -#define PIN_PB19F_TCC1_WO1 (51L) -#define MUX_PB19F_TCC1_WO1 (5L) -#define PINMUX_PB19F_TCC1_WO1 ((PIN_PB19F_TCC1_WO1 << 16) | MUX_PB19F_TCC1_WO1) -#define PORT_PB19F_TCC1_WO1 ((1UL) << 19) - -#define PIN_PD21F_TCC1_WO1 (117L) -#define MUX_PD21F_TCC1_WO1 (5L) -#define PINMUX_PD21F_TCC1_WO1 ((PIN_PD21F_TCC1_WO1 << 16) | MUX_PD21F_TCC1_WO1) -#define PORT_PD21F_TCC1_WO1 ((1UL) << 21) - -#define PIN_PA12G_TCC1_WO2 (12L) -#define MUX_PA12G_TCC1_WO2 (6L) -#define PINMUX_PA12G_TCC1_WO2 ((PIN_PA12G_TCC1_WO2 << 16) | MUX_PA12G_TCC1_WO2) -#define PORT_PA12G_TCC1_WO2 ((1UL) << 12) - -#define PIN_PA14G_TCC1_WO2 (14L) -#define MUX_PA14G_TCC1_WO2 (6L) -#define PINMUX_PA14G_TCC1_WO2 ((PIN_PA14G_TCC1_WO2 << 16) | MUX_PA14G_TCC1_WO2) -#define PORT_PA14G_TCC1_WO2 ((1UL) << 14) - -#define PIN_PA18F_TCC1_WO2 (18L) -#define MUX_PA18F_TCC1_WO2 (5L) -#define PINMUX_PA18F_TCC1_WO2 ((PIN_PA18F_TCC1_WO2 << 16) | MUX_PA18F_TCC1_WO2) -#define PORT_PA18F_TCC1_WO2 ((1UL) << 18) - -#define PIN_PB20F_TCC1_WO2 (52L) -#define MUX_PB20F_TCC1_WO2 (5L) -#define PINMUX_PB20F_TCC1_WO2 ((PIN_PB20F_TCC1_WO2 << 16) | MUX_PB20F_TCC1_WO2) -#define PORT_PB20F_TCC1_WO2 ((1UL) << 20) - -#define PIN_PB26F_TCC1_WO2 (58L) -#define MUX_PB26F_TCC1_WO2 (5L) -#define PINMUX_PB26F_TCC1_WO2 ((PIN_PB26F_TCC1_WO2 << 16) | MUX_PB26F_TCC1_WO2) -#define PORT_PB26F_TCC1_WO2 ((1UL) << 26) - -#define PIN_PA13G_TCC1_WO3 (13L) -#define MUX_PA13G_TCC1_WO3 (6L) -#define PINMUX_PA13G_TCC1_WO3 ((PIN_PA13G_TCC1_WO3 << 16) | MUX_PA13G_TCC1_WO3) -#define PORT_PA13G_TCC1_WO3 ((1UL) << 13) - -#define PIN_PA15G_TCC1_WO3 (15L) -#define MUX_PA15G_TCC1_WO3 (6L) -#define PINMUX_PA15G_TCC1_WO3 ((PIN_PA15G_TCC1_WO3 << 16) | MUX_PA15G_TCC1_WO3) -#define PORT_PA15G_TCC1_WO3 ((1UL) << 15) - -#define PIN_PA19F_TCC1_WO3 (19L) -#define MUX_PA19F_TCC1_WO3 (5L) -#define PINMUX_PA19F_TCC1_WO3 ((PIN_PA19F_TCC1_WO3 << 16) | MUX_PA19F_TCC1_WO3) -#define PORT_PA19F_TCC1_WO3 ((1UL) << 19) - -#define PIN_PB21F_TCC1_WO3 (53L) -#define MUX_PB21F_TCC1_WO3 (5L) -#define PINMUX_PB21F_TCC1_WO3 ((PIN_PB21F_TCC1_WO3 << 16) | MUX_PB21F_TCC1_WO3) -#define PORT_PB21F_TCC1_WO3 ((1UL) << 21) - -#define PIN_PB27F_TCC1_WO3 (59L) -#define MUX_PB27F_TCC1_WO3 (5L) -#define PINMUX_PB27F_TCC1_WO3 ((PIN_PB27F_TCC1_WO3 << 16) | MUX_PB27F_TCC1_WO3) -#define PORT_PB27F_TCC1_WO3 ((1UL) << 27) - -#define PIN_PA08G_TCC1_WO4 (8L) -#define MUX_PA08G_TCC1_WO4 (6L) -#define PINMUX_PA08G_TCC1_WO4 ((PIN_PA08G_TCC1_WO4 << 16) | MUX_PA08G_TCC1_WO4) -#define PORT_PA08G_TCC1_WO4 ((1UL) << 8) - -#define PIN_PC10G_TCC1_WO4 (74L) -#define MUX_PC10G_TCC1_WO4 (6L) -#define PINMUX_PC10G_TCC1_WO4 ((PIN_PC10G_TCC1_WO4 << 16) | MUX_PC10G_TCC1_WO4) -#define PORT_PC10G_TCC1_WO4 ((1UL) << 10) - -#define PIN_PA20F_TCC1_WO4 (20L) -#define MUX_PA20F_TCC1_WO4 (5L) -#define PINMUX_PA20F_TCC1_WO4 ((PIN_PA20F_TCC1_WO4 << 16) | MUX_PA20F_TCC1_WO4) -#define PORT_PA20F_TCC1_WO4 ((1UL) << 20) - -#define PIN_PB28F_TCC1_WO4 (60L) -#define MUX_PB28F_TCC1_WO4 (5L) -#define PINMUX_PB28F_TCC1_WO4 ((PIN_PB28F_TCC1_WO4 << 16) | MUX_PB28F_TCC1_WO4) -#define PORT_PB28F_TCC1_WO4 ((1UL) << 28) - -#define PIN_PA09G_TCC1_WO5 (9L) -#define MUX_PA09G_TCC1_WO5 (6L) -#define PINMUX_PA09G_TCC1_WO5 ((PIN_PA09G_TCC1_WO5 << 16) | MUX_PA09G_TCC1_WO5) -#define PORT_PA09G_TCC1_WO5 ((1UL) << 9) - -#define PIN_PC11G_TCC1_WO5 (75L) -#define MUX_PC11G_TCC1_WO5 (6L) -#define PINMUX_PC11G_TCC1_WO5 ((PIN_PC11G_TCC1_WO5 << 16) | MUX_PC11G_TCC1_WO5) -#define PORT_PC11G_TCC1_WO5 ((1UL) << 11) - -#define PIN_PA21F_TCC1_WO5 (21L) -#define MUX_PA21F_TCC1_WO5 (5L) -#define PINMUX_PA21F_TCC1_WO5 ((PIN_PA21F_TCC1_WO5 << 16) | MUX_PA21F_TCC1_WO5) -#define PORT_PA21F_TCC1_WO5 ((1UL) << 21) - -#define PIN_PB29F_TCC1_WO5 (61L) -#define MUX_PB29F_TCC1_WO5 (5L) -#define PINMUX_PB29F_TCC1_WO5 ((PIN_PB29F_TCC1_WO5 << 16) | MUX_PB29F_TCC1_WO5) -#define PORT_PB29F_TCC1_WO5 ((1UL) << 29) - -#define PIN_PA10G_TCC1_WO6 (10L) -#define MUX_PA10G_TCC1_WO6 (6L) -#define PINMUX_PA10G_TCC1_WO6 ((PIN_PA10G_TCC1_WO6 << 16) | MUX_PA10G_TCC1_WO6) -#define PORT_PA10G_TCC1_WO6 ((1UL) << 10) - -#define PIN_PC12G_TCC1_WO6 (76L) -#define MUX_PC12G_TCC1_WO6 (6L) -#define PINMUX_PC12G_TCC1_WO6 ((PIN_PC12G_TCC1_WO6 << 16) | MUX_PC12G_TCC1_WO6) -#define PORT_PC12G_TCC1_WO6 ((1UL) << 12) - -#define PIN_PA22F_TCC1_WO6 (22L) -#define MUX_PA22F_TCC1_WO6 (5L) -#define PINMUX_PA22F_TCC1_WO6 ((PIN_PA22F_TCC1_WO6 << 16) | MUX_PA22F_TCC1_WO6) -#define PORT_PA22F_TCC1_WO6 ((1UL) << 22) - -#define PIN_PA11G_TCC1_WO7 (11L) -#define MUX_PA11G_TCC1_WO7 (6L) -#define PINMUX_PA11G_TCC1_WO7 ((PIN_PA11G_TCC1_WO7 << 16) | MUX_PA11G_TCC1_WO7) -#define PORT_PA11G_TCC1_WO7 ((1UL) << 11) - -#define PIN_PC13G_TCC1_WO7 (77L) -#define MUX_PC13G_TCC1_WO7 (6L) -#define PINMUX_PC13G_TCC1_WO7 ((PIN_PC13G_TCC1_WO7 << 16) | MUX_PC13G_TCC1_WO7) -#define PORT_PC13G_TCC1_WO7 ((1UL) << 13) - -#define PIN_PA23F_TCC1_WO7 (23L) -#define MUX_PA23F_TCC1_WO7 (5L) -#define PINMUX_PA23F_TCC1_WO7 ((PIN_PA23F_TCC1_WO7 << 16) | MUX_PA23F_TCC1_WO7) -#define PORT_PA23F_TCC1_WO7 ((1UL) << 23) - -/* ========== PORT definition for TCC2 peripheral ========== */ -#define PIN_PA14F_TCC2_WO0 (14L) -#define MUX_PA14F_TCC2_WO0 (5L) -#define PINMUX_PA14F_TCC2_WO0 ((PIN_PA14F_TCC2_WO0 << 16) | MUX_PA14F_TCC2_WO0) -#define PORT_PA14F_TCC2_WO0 ((1UL) << 14) - -#define PIN_PA30F_TCC2_WO0 (30L) -#define MUX_PA30F_TCC2_WO0 (5L) -#define PINMUX_PA30F_TCC2_WO0 ((PIN_PA30F_TCC2_WO0 << 16) | MUX_PA30F_TCC2_WO0) -#define PORT_PA30F_TCC2_WO0 ((1UL) << 30) - -#define PIN_PA15F_TCC2_WO1 (15L) -#define MUX_PA15F_TCC2_WO1 (5L) -#define PINMUX_PA15F_TCC2_WO1 ((PIN_PA15F_TCC2_WO1 << 16) | MUX_PA15F_TCC2_WO1) -#define PORT_PA15F_TCC2_WO1 ((1UL) << 15) - -#define PIN_PA31F_TCC2_WO1 (31L) -#define MUX_PA31F_TCC2_WO1 (5L) -#define PINMUX_PA31F_TCC2_WO1 ((PIN_PA31F_TCC2_WO1 << 16) | MUX_PA31F_TCC2_WO1) -#define PORT_PA31F_TCC2_WO1 ((1UL) << 31) - -#define PIN_PA24F_TCC2_WO2 (24L) -#define MUX_PA24F_TCC2_WO2 (5L) -#define PINMUX_PA24F_TCC2_WO2 ((PIN_PA24F_TCC2_WO2 << 16) | MUX_PA24F_TCC2_WO2) -#define PORT_PA24F_TCC2_WO2 ((1UL) << 24) - -#define PIN_PB02F_TCC2_WO2 (34L) -#define MUX_PB02F_TCC2_WO2 (5L) -#define PINMUX_PB02F_TCC2_WO2 ((PIN_PB02F_TCC2_WO2 << 16) | MUX_PB02F_TCC2_WO2) -#define PORT_PB02F_TCC2_WO2 ((1UL) << 2) - -/* ========== PORT definition for TCC3 peripheral ========== */ -#define PIN_PB12F_TCC3_WO0 (44L) -#define MUX_PB12F_TCC3_WO0 (5L) -#define PINMUX_PB12F_TCC3_WO0 ((PIN_PB12F_TCC3_WO0 << 16) | MUX_PB12F_TCC3_WO0) -#define PORT_PB12F_TCC3_WO0 ((1UL) << 12) - -#define PIN_PB16F_TCC3_WO0 (48L) -#define MUX_PB16F_TCC3_WO0 (5L) -#define PINMUX_PB16F_TCC3_WO0 ((PIN_PB16F_TCC3_WO0 << 16) | MUX_PB16F_TCC3_WO0) -#define PORT_PB16F_TCC3_WO0 ((1UL) << 16) - -#define PIN_PB13F_TCC3_WO1 (45L) -#define MUX_PB13F_TCC3_WO1 (5L) -#define PINMUX_PB13F_TCC3_WO1 ((PIN_PB13F_TCC3_WO1 << 16) | MUX_PB13F_TCC3_WO1) -#define PORT_PB13F_TCC3_WO1 ((1UL) << 13) - -#define PIN_PB17F_TCC3_WO1 (49L) -#define MUX_PB17F_TCC3_WO1 (5L) -#define PINMUX_PB17F_TCC3_WO1 ((PIN_PB17F_TCC3_WO1 << 16) | MUX_PB17F_TCC3_WO1) -#define PORT_PB17F_TCC3_WO1 ((1UL) << 17) - -/* ========== PORT definition for TCC4 peripheral ========== */ -#define PIN_PB14F_TCC4_WO0 (46L) -#define MUX_PB14F_TCC4_WO0 (5L) -#define PINMUX_PB14F_TCC4_WO0 ((PIN_PB14F_TCC4_WO0 << 16) | MUX_PB14F_TCC4_WO0) -#define PORT_PB14F_TCC4_WO0 ((1UL) << 14) - -#define PIN_PB30F_TCC4_WO0 (62L) -#define MUX_PB30F_TCC4_WO0 (5L) -#define PINMUX_PB30F_TCC4_WO0 ((PIN_PB30F_TCC4_WO0 << 16) | MUX_PB30F_TCC4_WO0) -#define PORT_PB30F_TCC4_WO0 ((1UL) << 30) - -#define PIN_PB15F_TCC4_WO1 (47L) -#define MUX_PB15F_TCC4_WO1 (5L) -#define PINMUX_PB15F_TCC4_WO1 ((PIN_PB15F_TCC4_WO1 << 16) | MUX_PB15F_TCC4_WO1) -#define PORT_PB15F_TCC4_WO1 ((1UL) << 15) - -#define PIN_PB31F_TCC4_WO1 (63L) -#define MUX_PB31F_TCC4_WO1 (5L) -#define PINMUX_PB31F_TCC4_WO1 ((PIN_PB31F_TCC4_WO1 << 16) | MUX_PB31F_TCC4_WO1) -#define PORT_PB31F_TCC4_WO1 ((1UL) << 31) - -/* ========== PORT definition for USB peripheral ========== */ -#define PIN_PA24H_USB_DM (24L) -#define MUX_PA24H_USB_DM (7L) -#define PINMUX_PA24H_USB_DM ((PIN_PA24H_USB_DM << 16) | MUX_PA24H_USB_DM) -#define PORT_PA24H_USB_DM ((1UL) << 24) - -#define PIN_PA25H_USB_DP (25L) -#define MUX_PA25H_USB_DP (7L) -#define PINMUX_PA25H_USB_DP ((PIN_PA25H_USB_DP << 16) | MUX_PA25H_USB_DP) -#define PORT_PA25H_USB_DP ((1UL) << 25) - -#define PIN_PA23H_USB_SOF_1KHZ (23L) -#define MUX_PA23H_USB_SOF_1KHZ (7L) -#define PINMUX_PA23H_USB_SOF_1KHZ ((PIN_PA23H_USB_SOF_1KHZ << 16) | MUX_PA23H_USB_SOF_1KHZ) -#define PORT_PA23H_USB_SOF_1KHZ ((1UL) << 23) - -#define PIN_PB22H_USB_SOF_1KHZ (54L) -#define MUX_PB22H_USB_SOF_1KHZ (7L) -#define PINMUX_PB22H_USB_SOF_1KHZ ((PIN_PB22H_USB_SOF_1KHZ << 16) | MUX_PB22H_USB_SOF_1KHZ) -#define PORT_PB22H_USB_SOF_1KHZ ((1UL) << 22) - - - -#endif /* _SAME54P19A_GPIO_H_ */ - +/** + * \file + * + * \brief Peripheral I/O description for SAME54P19A + * + * Copyright (c) 2019 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAME54P19A_PIO_ +#define _SAME54P19A_PIO_ + +#define PIN_PA00 0 /**< \brief Pin Number for PA00 */ +#define PORT_PA00 (_UL_(1) << 0) /**< \brief PORT Mask for PA00 */ +#define PIN_PA01 1 /**< \brief Pin Number for PA01 */ +#define PORT_PA01 (_UL_(1) << 1) /**< \brief PORT Mask for PA01 */ +#define PIN_PA02 2 /**< \brief Pin Number for PA02 */ +#define PORT_PA02 (_UL_(1) << 2) /**< \brief PORT Mask for PA02 */ +#define PIN_PA03 3 /**< \brief Pin Number for PA03 */ +#define PORT_PA03 (_UL_(1) << 3) /**< \brief PORT Mask for PA03 */ +#define PIN_PA04 4 /**< \brief Pin Number for PA04 */ +#define PORT_PA04 (_UL_(1) << 4) /**< \brief PORT Mask for PA04 */ +#define PIN_PA05 5 /**< \brief Pin Number for PA05 */ +#define PORT_PA05 (_UL_(1) << 5) /**< \brief PORT Mask for PA05 */ +#define PIN_PA06 6 /**< \brief Pin Number for PA06 */ +#define PORT_PA06 (_UL_(1) << 6) /**< \brief PORT Mask for PA06 */ +#define PIN_PA07 7 /**< \brief Pin Number for PA07 */ +#define PORT_PA07 (_UL_(1) << 7) /**< \brief PORT Mask for PA07 */ +#define PIN_PA08 8 /**< \brief Pin Number for PA08 */ +#define PORT_PA08 (_UL_(1) << 8) /**< \brief PORT Mask for PA08 */ +#define PIN_PA09 9 /**< \brief Pin Number for PA09 */ +#define PORT_PA09 (_UL_(1) << 9) /**< \brief PORT Mask for PA09 */ +#define PIN_PA10 10 /**< \brief Pin Number for PA10 */ +#define PORT_PA10 (_UL_(1) << 10) /**< \brief PORT Mask for PA10 */ +#define PIN_PA11 11 /**< \brief Pin Number for PA11 */ +#define PORT_PA11 (_UL_(1) << 11) /**< \brief PORT Mask for PA11 */ +#define PIN_PA12 12 /**< \brief Pin Number for PA12 */ +#define PORT_PA12 (_UL_(1) << 12) /**< \brief PORT Mask for PA12 */ +#define PIN_PA13 13 /**< \brief Pin Number for PA13 */ +#define PORT_PA13 (_UL_(1) << 13) /**< \brief PORT Mask for PA13 */ +#define PIN_PA14 14 /**< \brief Pin Number for PA14 */ +#define PORT_PA14 (_UL_(1) << 14) /**< \brief PORT Mask for PA14 */ +#define PIN_PA15 15 /**< \brief Pin Number for PA15 */ +#define PORT_PA15 (_UL_(1) << 15) /**< \brief PORT Mask for PA15 */ +#define PIN_PA16 16 /**< \brief Pin Number for PA16 */ +#define PORT_PA16 (_UL_(1) << 16) /**< \brief PORT Mask for PA16 */ +#define PIN_PA17 17 /**< \brief Pin Number for PA17 */ +#define PORT_PA17 (_UL_(1) << 17) /**< \brief PORT Mask for PA17 */ +#define PIN_PA18 18 /**< \brief Pin Number for PA18 */ +#define PORT_PA18 (_UL_(1) << 18) /**< \brief PORT Mask for PA18 */ +#define PIN_PA19 19 /**< \brief Pin Number for PA19 */ +#define PORT_PA19 (_UL_(1) << 19) /**< \brief PORT Mask for PA19 */ +#define PIN_PA20 20 /**< \brief Pin Number for PA20 */ +#define PORT_PA20 (_UL_(1) << 20) /**< \brief PORT Mask for PA20 */ +#define PIN_PA21 21 /**< \brief Pin Number for PA21 */ +#define PORT_PA21 (_UL_(1) << 21) /**< \brief PORT Mask for PA21 */ +#define PIN_PA22 22 /**< \brief Pin Number for PA22 */ +#define PORT_PA22 (_UL_(1) << 22) /**< \brief PORT Mask for PA22 */ +#define PIN_PA23 23 /**< \brief Pin Number for PA23 */ +#define PORT_PA23 (_UL_(1) << 23) /**< \brief PORT Mask for PA23 */ +#define PIN_PA24 24 /**< \brief Pin Number for PA24 */ +#define PORT_PA24 (_UL_(1) << 24) /**< \brief PORT Mask for PA24 */ +#define PIN_PA25 25 /**< \brief Pin Number for PA25 */ +#define PORT_PA25 (_UL_(1) << 25) /**< \brief PORT Mask for PA25 */ +#define PIN_PA27 27 /**< \brief Pin Number for PA27 */ +#define PORT_PA27 (_UL_(1) << 27) /**< \brief PORT Mask for PA27 */ +#define PIN_PA30 30 /**< \brief Pin Number for PA30 */ +#define PORT_PA30 (_UL_(1) << 30) /**< \brief PORT Mask for PA30 */ +#define PIN_PA31 31 /**< \brief Pin Number for PA31 */ +#define PORT_PA31 (_UL_(1) << 31) /**< \brief PORT Mask for PA31 */ +#define PIN_PB00 32 /**< \brief Pin Number for PB00 */ +#define PORT_PB00 (_UL_(1) << 0) /**< \brief PORT Mask for PB00 */ +#define PIN_PB01 33 /**< \brief Pin Number for PB01 */ +#define PORT_PB01 (_UL_(1) << 1) /**< \brief PORT Mask for PB01 */ +#define PIN_PB02 34 /**< \brief Pin Number for PB02 */ +#define PORT_PB02 (_UL_(1) << 2) /**< \brief PORT Mask for PB02 */ +#define PIN_PB03 35 /**< \brief Pin Number for PB03 */ +#define PORT_PB03 (_UL_(1) << 3) /**< \brief PORT Mask for PB03 */ +#define PIN_PB04 36 /**< \brief Pin Number for PB04 */ +#define PORT_PB04 (_UL_(1) << 4) /**< \brief PORT Mask for PB04 */ +#define PIN_PB05 37 /**< \brief Pin Number for PB05 */ +#define PORT_PB05 (_UL_(1) << 5) /**< \brief PORT Mask for PB05 */ +#define PIN_PB06 38 /**< \brief Pin Number for PB06 */ +#define PORT_PB06 (_UL_(1) << 6) /**< \brief PORT Mask for PB06 */ +#define PIN_PB07 39 /**< \brief Pin Number for PB07 */ +#define PORT_PB07 (_UL_(1) << 7) /**< \brief PORT Mask for PB07 */ +#define PIN_PB08 40 /**< \brief Pin Number for PB08 */ +#define PORT_PB08 (_UL_(1) << 8) /**< \brief PORT Mask for PB08 */ +#define PIN_PB09 41 /**< \brief Pin Number for PB09 */ +#define PORT_PB09 (_UL_(1) << 9) /**< \brief PORT Mask for PB09 */ +#define PIN_PB10 42 /**< \brief Pin Number for PB10 */ +#define PORT_PB10 (_UL_(1) << 10) /**< \brief PORT Mask for PB10 */ +#define PIN_PB11 43 /**< \brief Pin Number for PB11 */ +#define PORT_PB11 (_UL_(1) << 11) /**< \brief PORT Mask for PB11 */ +#define PIN_PB12 44 /**< \brief Pin Number for PB12 */ +#define PORT_PB12 (_UL_(1) << 12) /**< \brief PORT Mask for PB12 */ +#define PIN_PB13 45 /**< \brief Pin Number for PB13 */ +#define PORT_PB13 (_UL_(1) << 13) /**< \brief PORT Mask for PB13 */ +#define PIN_PB14 46 /**< \brief Pin Number for PB14 */ +#define PORT_PB14 (_UL_(1) << 14) /**< \brief PORT Mask for PB14 */ +#define PIN_PB15 47 /**< \brief Pin Number for PB15 */ +#define PORT_PB15 (_UL_(1) << 15) /**< \brief PORT Mask for PB15 */ +#define PIN_PB16 48 /**< \brief Pin Number for PB16 */ +#define PORT_PB16 (_UL_(1) << 16) /**< \brief PORT Mask for PB16 */ +#define PIN_PB17 49 /**< \brief Pin Number for PB17 */ +#define PORT_PB17 (_UL_(1) << 17) /**< \brief PORT Mask for PB17 */ +#define PIN_PB18 50 /**< \brief Pin Number for PB18 */ +#define PORT_PB18 (_UL_(1) << 18) /**< \brief PORT Mask for PB18 */ +#define PIN_PB19 51 /**< \brief Pin Number for PB19 */ +#define PORT_PB19 (_UL_(1) << 19) /**< \brief PORT Mask for PB19 */ +#define PIN_PB20 52 /**< \brief Pin Number for PB20 */ +#define PORT_PB20 (_UL_(1) << 20) /**< \brief PORT Mask for PB20 */ +#define PIN_PB21 53 /**< \brief Pin Number for PB21 */ +#define PORT_PB21 (_UL_(1) << 21) /**< \brief PORT Mask for PB21 */ +#define PIN_PB22 54 /**< \brief Pin Number for PB22 */ +#define PORT_PB22 (_UL_(1) << 22) /**< \brief PORT Mask for PB22 */ +#define PIN_PB23 55 /**< \brief Pin Number for PB23 */ +#define PORT_PB23 (_UL_(1) << 23) /**< \brief PORT Mask for PB23 */ +#define PIN_PB24 56 /**< \brief Pin Number for PB24 */ +#define PORT_PB24 (_UL_(1) << 24) /**< \brief PORT Mask for PB24 */ +#define PIN_PB25 57 /**< \brief Pin Number for PB25 */ +#define PORT_PB25 (_UL_(1) << 25) /**< \brief PORT Mask for PB25 */ +#define PIN_PB26 58 /**< \brief Pin Number for PB26 */ +#define PORT_PB26 (_UL_(1) << 26) /**< \brief PORT Mask for PB26 */ +#define PIN_PB27 59 /**< \brief Pin Number for PB27 */ +#define PORT_PB27 (_UL_(1) << 27) /**< \brief PORT Mask for PB27 */ +#define PIN_PB28 60 /**< \brief Pin Number for PB28 */ +#define PORT_PB28 (_UL_(1) << 28) /**< \brief PORT Mask for PB28 */ +#define PIN_PB29 61 /**< \brief Pin Number for PB29 */ +#define PORT_PB29 (_UL_(1) << 29) /**< \brief PORT Mask for PB29 */ +#define PIN_PB30 62 /**< \brief Pin Number for PB30 */ +#define PORT_PB30 (_UL_(1) << 30) /**< \brief PORT Mask for PB30 */ +#define PIN_PB31 63 /**< \brief Pin Number for PB31 */ +#define PORT_PB31 (_UL_(1) << 31) /**< \brief PORT Mask for PB31 */ +#define PIN_PC00 64 /**< \brief Pin Number for PC00 */ +#define PORT_PC00 (_UL_(1) << 0) /**< \brief PORT Mask for PC00 */ +#define PIN_PC01 65 /**< \brief Pin Number for PC01 */ +#define PORT_PC01 (_UL_(1) << 1) /**< \brief PORT Mask for PC01 */ +#define PIN_PC02 66 /**< \brief Pin Number for PC02 */ +#define PORT_PC02 (_UL_(1) << 2) /**< \brief PORT Mask for PC02 */ +#define PIN_PC03 67 /**< \brief Pin Number for PC03 */ +#define PORT_PC03 (_UL_(1) << 3) /**< \brief PORT Mask for PC03 */ +#define PIN_PC04 68 /**< \brief Pin Number for PC04 */ +#define PORT_PC04 (_UL_(1) << 4) /**< \brief PORT Mask for PC04 */ +#define PIN_PC05 69 /**< \brief Pin Number for PC05 */ +#define PORT_PC05 (_UL_(1) << 5) /**< \brief PORT Mask for PC05 */ +#define PIN_PC06 70 /**< \brief Pin Number for PC06 */ +#define PORT_PC06 (_UL_(1) << 6) /**< \brief PORT Mask for PC06 */ +#define PIN_PC07 71 /**< \brief Pin Number for PC07 */ +#define PORT_PC07 (_UL_(1) << 7) /**< \brief PORT Mask for PC07 */ +#define PIN_PC10 74 /**< \brief Pin Number for PC10 */ +#define PORT_PC10 (_UL_(1) << 10) /**< \brief PORT Mask for PC10 */ +#define PIN_PC11 75 /**< \brief Pin Number for PC11 */ +#define PORT_PC11 (_UL_(1) << 11) /**< \brief PORT Mask for PC11 */ +#define PIN_PC12 76 /**< \brief Pin Number for PC12 */ +#define PORT_PC12 (_UL_(1) << 12) /**< \brief PORT Mask for PC12 */ +#define PIN_PC13 77 /**< \brief Pin Number for PC13 */ +#define PORT_PC13 (_UL_(1) << 13) /**< \brief PORT Mask for PC13 */ +#define PIN_PC14 78 /**< \brief Pin Number for PC14 */ +#define PORT_PC14 (_UL_(1) << 14) /**< \brief PORT Mask for PC14 */ +#define PIN_PC15 79 /**< \brief Pin Number for PC15 */ +#define PORT_PC15 (_UL_(1) << 15) /**< \brief PORT Mask for PC15 */ +#define PIN_PC16 80 /**< \brief Pin Number for PC16 */ +#define PORT_PC16 (_UL_(1) << 16) /**< \brief PORT Mask for PC16 */ +#define PIN_PC17 81 /**< \brief Pin Number for PC17 */ +#define PORT_PC17 (_UL_(1) << 17) /**< \brief PORT Mask for PC17 */ +#define PIN_PC18 82 /**< \brief Pin Number for PC18 */ +#define PORT_PC18 (_UL_(1) << 18) /**< \brief PORT Mask for PC18 */ +#define PIN_PC19 83 /**< \brief Pin Number for PC19 */ +#define PORT_PC19 (_UL_(1) << 19) /**< \brief PORT Mask for PC19 */ +#define PIN_PC20 84 /**< \brief Pin Number for PC20 */ +#define PORT_PC20 (_UL_(1) << 20) /**< \brief PORT Mask for PC20 */ +#define PIN_PC21 85 /**< \brief Pin Number for PC21 */ +#define PORT_PC21 (_UL_(1) << 21) /**< \brief PORT Mask for PC21 */ +#define PIN_PC22 86 /**< \brief Pin Number for PC22 */ +#define PORT_PC22 (_UL_(1) << 22) /**< \brief PORT Mask for PC22 */ +#define PIN_PC23 87 /**< \brief Pin Number for PC23 */ +#define PORT_PC23 (_UL_(1) << 23) /**< \brief PORT Mask for PC23 */ +#define PIN_PC24 88 /**< \brief Pin Number for PC24 */ +#define PORT_PC24 (_UL_(1) << 24) /**< \brief PORT Mask for PC24 */ +#define PIN_PC25 89 /**< \brief Pin Number for PC25 */ +#define PORT_PC25 (_UL_(1) << 25) /**< \brief PORT Mask for PC25 */ +#define PIN_PC26 90 /**< \brief Pin Number for PC26 */ +#define PORT_PC26 (_UL_(1) << 26) /**< \brief PORT Mask for PC26 */ +#define PIN_PC27 91 /**< \brief Pin Number for PC27 */ +#define PORT_PC27 (_UL_(1) << 27) /**< \brief PORT Mask for PC27 */ +#define PIN_PC28 92 /**< \brief Pin Number for PC28 */ +#define PORT_PC28 (_UL_(1) << 28) /**< \brief PORT Mask for PC28 */ +#define PIN_PC30 94 /**< \brief Pin Number for PC30 */ +#define PORT_PC30 (_UL_(1) << 30) /**< \brief PORT Mask for PC30 */ +#define PIN_PC31 95 /**< \brief Pin Number for PC31 */ +#define PORT_PC31 (_UL_(1) << 31) /**< \brief PORT Mask for PC31 */ +#define PIN_PD00 96 /**< \brief Pin Number for PD00 */ +#define PORT_PD00 (_UL_(1) << 0) /**< \brief PORT Mask for PD00 */ +#define PIN_PD01 97 /**< \brief Pin Number for PD01 */ +#define PORT_PD01 (_UL_(1) << 1) /**< \brief PORT Mask for PD01 */ +#define PIN_PD08 104 /**< \brief Pin Number for PD08 */ +#define PORT_PD08 (_UL_(1) << 8) /**< \brief PORT Mask for PD08 */ +#define PIN_PD09 105 /**< \brief Pin Number for PD09 */ +#define PORT_PD09 (_UL_(1) << 9) /**< \brief PORT Mask for PD09 */ +#define PIN_PD10 106 /**< \brief Pin Number for PD10 */ +#define PORT_PD10 (_UL_(1) << 10) /**< \brief PORT Mask for PD10 */ +#define PIN_PD11 107 /**< \brief Pin Number for PD11 */ +#define PORT_PD11 (_UL_(1) << 11) /**< \brief PORT Mask for PD11 */ +#define PIN_PD12 108 /**< \brief Pin Number for PD12 */ +#define PORT_PD12 (_UL_(1) << 12) /**< \brief PORT Mask for PD12 */ +#define PIN_PD20 116 /**< \brief Pin Number for PD20 */ +#define PORT_PD20 (_UL_(1) << 20) /**< \brief PORT Mask for PD20 */ +#define PIN_PD21 117 /**< \brief Pin Number for PD21 */ +#define PORT_PD21 (_UL_(1) << 21) /**< \brief PORT Mask for PD21 */ +/* ========== PORT definition for CM4 peripheral ========== */ +#define PIN_PA30H_CM4_SWCLK _L_(30) /**< \brief CM4 signal: SWCLK on PA30 mux H */ +#define MUX_PA30H_CM4_SWCLK _L_(7) +#define PINMUX_PA30H_CM4_SWCLK ((PIN_PA30H_CM4_SWCLK << 16) | MUX_PA30H_CM4_SWCLK) +#define PORT_PA30H_CM4_SWCLK (_UL_(1) << 30) +#define PIN_PC27M_CM4_SWO _L_(91) /**< \brief CM4 signal: SWO on PC27 mux M */ +#define MUX_PC27M_CM4_SWO _L_(12) +#define PINMUX_PC27M_CM4_SWO ((PIN_PC27M_CM4_SWO << 16) | MUX_PC27M_CM4_SWO) +#define PORT_PC27M_CM4_SWO (_UL_(1) << 27) +#define PIN_PB30H_CM4_SWO _L_(62) /**< \brief CM4 signal: SWO on PB30 mux H */ +#define MUX_PB30H_CM4_SWO _L_(7) +#define PINMUX_PB30H_CM4_SWO ((PIN_PB30H_CM4_SWO << 16) | MUX_PB30H_CM4_SWO) +#define PORT_PB30H_CM4_SWO (_UL_(1) << 30) +#define PIN_PC27H_CM4_TRACECLK _L_(91) /**< \brief CM4 signal: TRACECLK on PC27 mux H */ +#define MUX_PC27H_CM4_TRACECLK _L_(7) +#define PINMUX_PC27H_CM4_TRACECLK ((PIN_PC27H_CM4_TRACECLK << 16) | MUX_PC27H_CM4_TRACECLK) +#define PORT_PC27H_CM4_TRACECLK (_UL_(1) << 27) +#define PIN_PC28H_CM4_TRACEDATA0 _L_(92) /**< \brief CM4 signal: TRACEDATA0 on PC28 mux H */ +#define MUX_PC28H_CM4_TRACEDATA0 _L_(7) +#define PINMUX_PC28H_CM4_TRACEDATA0 ((PIN_PC28H_CM4_TRACEDATA0 << 16) | MUX_PC28H_CM4_TRACEDATA0) +#define PORT_PC28H_CM4_TRACEDATA0 (_UL_(1) << 28) +#define PIN_PC26H_CM4_TRACEDATA1 _L_(90) /**< \brief CM4 signal: TRACEDATA1 on PC26 mux H */ +#define MUX_PC26H_CM4_TRACEDATA1 _L_(7) +#define PINMUX_PC26H_CM4_TRACEDATA1 ((PIN_PC26H_CM4_TRACEDATA1 << 16) | MUX_PC26H_CM4_TRACEDATA1) +#define PORT_PC26H_CM4_TRACEDATA1 (_UL_(1) << 26) +#define PIN_PC25H_CM4_TRACEDATA2 _L_(89) /**< \brief CM4 signal: TRACEDATA2 on PC25 mux H */ +#define MUX_PC25H_CM4_TRACEDATA2 _L_(7) +#define PINMUX_PC25H_CM4_TRACEDATA2 ((PIN_PC25H_CM4_TRACEDATA2 << 16) | MUX_PC25H_CM4_TRACEDATA2) +#define PORT_PC25H_CM4_TRACEDATA2 (_UL_(1) << 25) +#define PIN_PC24H_CM4_TRACEDATA3 _L_(88) /**< \brief CM4 signal: TRACEDATA3 on PC24 mux H */ +#define MUX_PC24H_CM4_TRACEDATA3 _L_(7) +#define PINMUX_PC24H_CM4_TRACEDATA3 ((PIN_PC24H_CM4_TRACEDATA3 << 16) | MUX_PC24H_CM4_TRACEDATA3) +#define PORT_PC24H_CM4_TRACEDATA3 (_UL_(1) << 24) +/* ========== PORT definition for ANAREF peripheral ========== */ +#define PIN_PA03B_ANAREF_VREF0 _L_(3) /**< \brief ANAREF signal: VREF0 on PA03 mux B */ +#define MUX_PA03B_ANAREF_VREF0 _L_(1) +#define PINMUX_PA03B_ANAREF_VREF0 ((PIN_PA03B_ANAREF_VREF0 << 16) | MUX_PA03B_ANAREF_VREF0) +#define PORT_PA03B_ANAREF_VREF0 (_UL_(1) << 3) +#define PIN_PA04B_ANAREF_VREF1 _L_(4) /**< \brief ANAREF signal: VREF1 on PA04 mux B */ +#define MUX_PA04B_ANAREF_VREF1 _L_(1) +#define PINMUX_PA04B_ANAREF_VREF1 ((PIN_PA04B_ANAREF_VREF1 << 16) | MUX_PA04B_ANAREF_VREF1) +#define PORT_PA04B_ANAREF_VREF1 (_UL_(1) << 4) +#define PIN_PA06B_ANAREF_VREF2 _L_(6) /**< \brief ANAREF signal: VREF2 on PA06 mux B */ +#define MUX_PA06B_ANAREF_VREF2 _L_(1) +#define PINMUX_PA06B_ANAREF_VREF2 ((PIN_PA06B_ANAREF_VREF2 << 16) | MUX_PA06B_ANAREF_VREF2) +#define PORT_PA06B_ANAREF_VREF2 (_UL_(1) << 6) +/* ========== PORT definition for GCLK peripheral ========== */ +#define PIN_PA30M_GCLK_IO0 _L_(30) /**< \brief GCLK signal: IO0 on PA30 mux M */ +#define MUX_PA30M_GCLK_IO0 _L_(12) +#define PINMUX_PA30M_GCLK_IO0 ((PIN_PA30M_GCLK_IO0 << 16) | MUX_PA30M_GCLK_IO0) +#define PORT_PA30M_GCLK_IO0 (_UL_(1) << 30) +#define PIN_PB14M_GCLK_IO0 _L_(46) /**< \brief GCLK signal: IO0 on PB14 mux M */ +#define MUX_PB14M_GCLK_IO0 _L_(12) +#define PINMUX_PB14M_GCLK_IO0 ((PIN_PB14M_GCLK_IO0 << 16) | MUX_PB14M_GCLK_IO0) +#define PORT_PB14M_GCLK_IO0 (_UL_(1) << 14) +#define PIN_PA14M_GCLK_IO0 _L_(14) /**< \brief GCLK signal: IO0 on PA14 mux M */ +#define MUX_PA14M_GCLK_IO0 _L_(12) +#define PINMUX_PA14M_GCLK_IO0 ((PIN_PA14M_GCLK_IO0 << 16) | MUX_PA14M_GCLK_IO0) +#define PORT_PA14M_GCLK_IO0 (_UL_(1) << 14) +#define PIN_PB22M_GCLK_IO0 _L_(54) /**< \brief GCLK signal: IO0 on PB22 mux M */ +#define MUX_PB22M_GCLK_IO0 _L_(12) +#define PINMUX_PB22M_GCLK_IO0 ((PIN_PB22M_GCLK_IO0 << 16) | MUX_PB22M_GCLK_IO0) +#define PORT_PB22M_GCLK_IO0 (_UL_(1) << 22) +#define PIN_PB15M_GCLK_IO1 _L_(47) /**< \brief GCLK signal: IO1 on PB15 mux M */ +#define MUX_PB15M_GCLK_IO1 _L_(12) +#define PINMUX_PB15M_GCLK_IO1 ((PIN_PB15M_GCLK_IO1 << 16) | MUX_PB15M_GCLK_IO1) +#define PORT_PB15M_GCLK_IO1 (_UL_(1) << 15) +#define PIN_PA15M_GCLK_IO1 _L_(15) /**< \brief GCLK signal: IO1 on PA15 mux M */ +#define MUX_PA15M_GCLK_IO1 _L_(12) +#define PINMUX_PA15M_GCLK_IO1 ((PIN_PA15M_GCLK_IO1 << 16) | MUX_PA15M_GCLK_IO1) +#define PORT_PA15M_GCLK_IO1 (_UL_(1) << 15) +#define PIN_PB23M_GCLK_IO1 _L_(55) /**< \brief GCLK signal: IO1 on PB23 mux M */ +#define MUX_PB23M_GCLK_IO1 _L_(12) +#define PINMUX_PB23M_GCLK_IO1 ((PIN_PB23M_GCLK_IO1 << 16) | MUX_PB23M_GCLK_IO1) +#define PORT_PB23M_GCLK_IO1 (_UL_(1) << 23) +#define PIN_PA27M_GCLK_IO1 _L_(27) /**< \brief GCLK signal: IO1 on PA27 mux M */ +#define MUX_PA27M_GCLK_IO1 _L_(12) +#define PINMUX_PA27M_GCLK_IO1 ((PIN_PA27M_GCLK_IO1 << 16) | MUX_PA27M_GCLK_IO1) +#define PORT_PA27M_GCLK_IO1 (_UL_(1) << 27) +#define PIN_PA16M_GCLK_IO2 _L_(16) /**< \brief GCLK signal: IO2 on PA16 mux M */ +#define MUX_PA16M_GCLK_IO2 _L_(12) +#define PINMUX_PA16M_GCLK_IO2 ((PIN_PA16M_GCLK_IO2 << 16) | MUX_PA16M_GCLK_IO2) +#define PORT_PA16M_GCLK_IO2 (_UL_(1) << 16) +#define PIN_PB16M_GCLK_IO2 _L_(48) /**< \brief GCLK signal: IO2 on PB16 mux M */ +#define MUX_PB16M_GCLK_IO2 _L_(12) +#define PINMUX_PB16M_GCLK_IO2 ((PIN_PB16M_GCLK_IO2 << 16) | MUX_PB16M_GCLK_IO2) +#define PORT_PB16M_GCLK_IO2 (_UL_(1) << 16) +#define PIN_PA17M_GCLK_IO3 _L_(17) /**< \brief GCLK signal: IO3 on PA17 mux M */ +#define MUX_PA17M_GCLK_IO3 _L_(12) +#define PINMUX_PA17M_GCLK_IO3 ((PIN_PA17M_GCLK_IO3 << 16) | MUX_PA17M_GCLK_IO3) +#define PORT_PA17M_GCLK_IO3 (_UL_(1) << 17) +#define PIN_PB17M_GCLK_IO3 _L_(49) /**< \brief GCLK signal: IO3 on PB17 mux M */ +#define MUX_PB17M_GCLK_IO3 _L_(12) +#define PINMUX_PB17M_GCLK_IO3 ((PIN_PB17M_GCLK_IO3 << 16) | MUX_PB17M_GCLK_IO3) +#define PORT_PB17M_GCLK_IO3 (_UL_(1) << 17) +#define PIN_PA10M_GCLK_IO4 _L_(10) /**< \brief GCLK signal: IO4 on PA10 mux M */ +#define MUX_PA10M_GCLK_IO4 _L_(12) +#define PINMUX_PA10M_GCLK_IO4 ((PIN_PA10M_GCLK_IO4 << 16) | MUX_PA10M_GCLK_IO4) +#define PORT_PA10M_GCLK_IO4 (_UL_(1) << 10) +#define PIN_PB10M_GCLK_IO4 _L_(42) /**< \brief GCLK signal: IO4 on PB10 mux M */ +#define MUX_PB10M_GCLK_IO4 _L_(12) +#define PINMUX_PB10M_GCLK_IO4 ((PIN_PB10M_GCLK_IO4 << 16) | MUX_PB10M_GCLK_IO4) +#define PORT_PB10M_GCLK_IO4 (_UL_(1) << 10) +#define PIN_PB18M_GCLK_IO4 _L_(50) /**< \brief GCLK signal: IO4 on PB18 mux M */ +#define MUX_PB18M_GCLK_IO4 _L_(12) +#define PINMUX_PB18M_GCLK_IO4 ((PIN_PB18M_GCLK_IO4 << 16) | MUX_PB18M_GCLK_IO4) +#define PORT_PB18M_GCLK_IO4 (_UL_(1) << 18) +#define PIN_PA11M_GCLK_IO5 _L_(11) /**< \brief GCLK signal: IO5 on PA11 mux M */ +#define MUX_PA11M_GCLK_IO5 _L_(12) +#define PINMUX_PA11M_GCLK_IO5 ((PIN_PA11M_GCLK_IO5 << 16) | MUX_PA11M_GCLK_IO5) +#define PORT_PA11M_GCLK_IO5 (_UL_(1) << 11) +#define PIN_PB11M_GCLK_IO5 _L_(43) /**< \brief GCLK signal: IO5 on PB11 mux M */ +#define MUX_PB11M_GCLK_IO5 _L_(12) +#define PINMUX_PB11M_GCLK_IO5 ((PIN_PB11M_GCLK_IO5 << 16) | MUX_PB11M_GCLK_IO5) +#define PORT_PB11M_GCLK_IO5 (_UL_(1) << 11) +#define PIN_PB19M_GCLK_IO5 _L_(51) /**< \brief GCLK signal: IO5 on PB19 mux M */ +#define MUX_PB19M_GCLK_IO5 _L_(12) +#define PINMUX_PB19M_GCLK_IO5 ((PIN_PB19M_GCLK_IO5 << 16) | MUX_PB19M_GCLK_IO5) +#define PORT_PB19M_GCLK_IO5 (_UL_(1) << 19) +#define PIN_PB12M_GCLK_IO6 _L_(44) /**< \brief GCLK signal: IO6 on PB12 mux M */ +#define MUX_PB12M_GCLK_IO6 _L_(12) +#define PINMUX_PB12M_GCLK_IO6 ((PIN_PB12M_GCLK_IO6 << 16) | MUX_PB12M_GCLK_IO6) +#define PORT_PB12M_GCLK_IO6 (_UL_(1) << 12) +#define PIN_PB20M_GCLK_IO6 _L_(52) /**< \brief GCLK signal: IO6 on PB20 mux M */ +#define MUX_PB20M_GCLK_IO6 _L_(12) +#define PINMUX_PB20M_GCLK_IO6 ((PIN_PB20M_GCLK_IO6 << 16) | MUX_PB20M_GCLK_IO6) +#define PORT_PB20M_GCLK_IO6 (_UL_(1) << 20) +#define PIN_PB13M_GCLK_IO7 _L_(45) /**< \brief GCLK signal: IO7 on PB13 mux M */ +#define MUX_PB13M_GCLK_IO7 _L_(12) +#define PINMUX_PB13M_GCLK_IO7 ((PIN_PB13M_GCLK_IO7 << 16) | MUX_PB13M_GCLK_IO7) +#define PORT_PB13M_GCLK_IO7 (_UL_(1) << 13) +#define PIN_PB21M_GCLK_IO7 _L_(53) /**< \brief GCLK signal: IO7 on PB21 mux M */ +#define MUX_PB21M_GCLK_IO7 _L_(12) +#define PINMUX_PB21M_GCLK_IO7 ((PIN_PB21M_GCLK_IO7 << 16) | MUX_PB21M_GCLK_IO7) +#define PORT_PB21M_GCLK_IO7 (_UL_(1) << 21) +/* ========== PORT definition for EIC peripheral ========== */ +#define PIN_PA00A_EIC_EXTINT0 _L_(0) /**< \brief EIC signal: EXTINT0 on PA00 mux A */ +#define MUX_PA00A_EIC_EXTINT0 _L_(0) +#define PINMUX_PA00A_EIC_EXTINT0 ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0) +#define PORT_PA00A_EIC_EXTINT0 (_UL_(1) << 0) +#define PIN_PA00A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PA00 External Interrupt Line */ +#define PIN_PA16A_EIC_EXTINT0 _L_(16) /**< \brief EIC signal: EXTINT0 on PA16 mux A */ +#define MUX_PA16A_EIC_EXTINT0 _L_(0) +#define PINMUX_PA16A_EIC_EXTINT0 ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0) +#define PORT_PA16A_EIC_EXTINT0 (_UL_(1) << 16) +#define PIN_PA16A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PA16 External Interrupt Line */ +#define PIN_PB00A_EIC_EXTINT0 _L_(32) /**< \brief EIC signal: EXTINT0 on PB00 mux A */ +#define MUX_PB00A_EIC_EXTINT0 _L_(0) +#define PINMUX_PB00A_EIC_EXTINT0 ((PIN_PB00A_EIC_EXTINT0 << 16) | MUX_PB00A_EIC_EXTINT0) +#define PORT_PB00A_EIC_EXTINT0 (_UL_(1) << 0) +#define PIN_PB00A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PB00 External Interrupt Line */ +#define PIN_PB16A_EIC_EXTINT0 _L_(48) /**< \brief EIC signal: EXTINT0 on PB16 mux A */ +#define MUX_PB16A_EIC_EXTINT0 _L_(0) +#define PINMUX_PB16A_EIC_EXTINT0 ((PIN_PB16A_EIC_EXTINT0 << 16) | MUX_PB16A_EIC_EXTINT0) +#define PORT_PB16A_EIC_EXTINT0 (_UL_(1) << 16) +#define PIN_PB16A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PB16 External Interrupt Line */ +#define PIN_PC00A_EIC_EXTINT0 _L_(64) /**< \brief EIC signal: EXTINT0 on PC00 mux A */ +#define MUX_PC00A_EIC_EXTINT0 _L_(0) +#define PINMUX_PC00A_EIC_EXTINT0 ((PIN_PC00A_EIC_EXTINT0 << 16) | MUX_PC00A_EIC_EXTINT0) +#define PORT_PC00A_EIC_EXTINT0 (_UL_(1) << 0) +#define PIN_PC00A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PC00 External Interrupt Line */ +#define PIN_PC16A_EIC_EXTINT0 _L_(80) /**< \brief EIC signal: EXTINT0 on PC16 mux A */ +#define MUX_PC16A_EIC_EXTINT0 _L_(0) +#define PINMUX_PC16A_EIC_EXTINT0 ((PIN_PC16A_EIC_EXTINT0 << 16) | MUX_PC16A_EIC_EXTINT0) +#define PORT_PC16A_EIC_EXTINT0 (_UL_(1) << 16) +#define PIN_PC16A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PC16 External Interrupt Line */ +#define PIN_PD00A_EIC_EXTINT0 _L_(96) /**< \brief EIC signal: EXTINT0 on PD00 mux A */ +#define MUX_PD00A_EIC_EXTINT0 _L_(0) +#define PINMUX_PD00A_EIC_EXTINT0 ((PIN_PD00A_EIC_EXTINT0 << 16) | MUX_PD00A_EIC_EXTINT0) +#define PORT_PD00A_EIC_EXTINT0 (_UL_(1) << 0) +#define PIN_PD00A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PD00 External Interrupt Line */ +#define PIN_PA01A_EIC_EXTINT1 _L_(1) /**< \brief EIC signal: EXTINT1 on PA01 mux A */ +#define MUX_PA01A_EIC_EXTINT1 _L_(0) +#define PINMUX_PA01A_EIC_EXTINT1 ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1) +#define PORT_PA01A_EIC_EXTINT1 (_UL_(1) << 1) +#define PIN_PA01A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PA01 External Interrupt Line */ +#define PIN_PA17A_EIC_EXTINT1 _L_(17) /**< \brief EIC signal: EXTINT1 on PA17 mux A */ +#define MUX_PA17A_EIC_EXTINT1 _L_(0) +#define PINMUX_PA17A_EIC_EXTINT1 ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1) +#define PORT_PA17A_EIC_EXTINT1 (_UL_(1) << 17) +#define PIN_PA17A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PA17 External Interrupt Line */ +#define PIN_PB01A_EIC_EXTINT1 _L_(33) /**< \brief EIC signal: EXTINT1 on PB01 mux A */ +#define MUX_PB01A_EIC_EXTINT1 _L_(0) +#define PINMUX_PB01A_EIC_EXTINT1 ((PIN_PB01A_EIC_EXTINT1 << 16) | MUX_PB01A_EIC_EXTINT1) +#define PORT_PB01A_EIC_EXTINT1 (_UL_(1) << 1) +#define PIN_PB01A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PB01 External Interrupt Line */ +#define PIN_PB17A_EIC_EXTINT1 _L_(49) /**< \brief EIC signal: EXTINT1 on PB17 mux A */ +#define MUX_PB17A_EIC_EXTINT1 _L_(0) +#define PINMUX_PB17A_EIC_EXTINT1 ((PIN_PB17A_EIC_EXTINT1 << 16) | MUX_PB17A_EIC_EXTINT1) +#define PORT_PB17A_EIC_EXTINT1 (_UL_(1) << 17) +#define PIN_PB17A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PB17 External Interrupt Line */ +#define PIN_PC01A_EIC_EXTINT1 _L_(65) /**< \brief EIC signal: EXTINT1 on PC01 mux A */ +#define MUX_PC01A_EIC_EXTINT1 _L_(0) +#define PINMUX_PC01A_EIC_EXTINT1 ((PIN_PC01A_EIC_EXTINT1 << 16) | MUX_PC01A_EIC_EXTINT1) +#define PORT_PC01A_EIC_EXTINT1 (_UL_(1) << 1) +#define PIN_PC01A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PC01 External Interrupt Line */ +#define PIN_PC17A_EIC_EXTINT1 _L_(81) /**< \brief EIC signal: EXTINT1 on PC17 mux A */ +#define MUX_PC17A_EIC_EXTINT1 _L_(0) +#define PINMUX_PC17A_EIC_EXTINT1 ((PIN_PC17A_EIC_EXTINT1 << 16) | MUX_PC17A_EIC_EXTINT1) +#define PORT_PC17A_EIC_EXTINT1 (_UL_(1) << 17) +#define PIN_PC17A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PC17 External Interrupt Line */ +#define PIN_PD01A_EIC_EXTINT1 _L_(97) /**< \brief EIC signal: EXTINT1 on PD01 mux A */ +#define MUX_PD01A_EIC_EXTINT1 _L_(0) +#define PINMUX_PD01A_EIC_EXTINT1 ((PIN_PD01A_EIC_EXTINT1 << 16) | MUX_PD01A_EIC_EXTINT1) +#define PORT_PD01A_EIC_EXTINT1 (_UL_(1) << 1) +#define PIN_PD01A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PD01 External Interrupt Line */ +#define PIN_PA02A_EIC_EXTINT2 _L_(2) /**< \brief EIC signal: EXTINT2 on PA02 mux A */ +#define MUX_PA02A_EIC_EXTINT2 _L_(0) +#define PINMUX_PA02A_EIC_EXTINT2 ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2) +#define PORT_PA02A_EIC_EXTINT2 (_UL_(1) << 2) +#define PIN_PA02A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PA02 External Interrupt Line */ +#define PIN_PA18A_EIC_EXTINT2 _L_(18) /**< \brief EIC signal: EXTINT2 on PA18 mux A */ +#define MUX_PA18A_EIC_EXTINT2 _L_(0) +#define PINMUX_PA18A_EIC_EXTINT2 ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2) +#define PORT_PA18A_EIC_EXTINT2 (_UL_(1) << 18) +#define PIN_PA18A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PA18 External Interrupt Line */ +#define PIN_PB02A_EIC_EXTINT2 _L_(34) /**< \brief EIC signal: EXTINT2 on PB02 mux A */ +#define MUX_PB02A_EIC_EXTINT2 _L_(0) +#define PINMUX_PB02A_EIC_EXTINT2 ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2) +#define PORT_PB02A_EIC_EXTINT2 (_UL_(1) << 2) +#define PIN_PB02A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PB02 External Interrupt Line */ +#define PIN_PB18A_EIC_EXTINT2 _L_(50) /**< \brief EIC signal: EXTINT2 on PB18 mux A */ +#define MUX_PB18A_EIC_EXTINT2 _L_(0) +#define PINMUX_PB18A_EIC_EXTINT2 ((PIN_PB18A_EIC_EXTINT2 << 16) | MUX_PB18A_EIC_EXTINT2) +#define PORT_PB18A_EIC_EXTINT2 (_UL_(1) << 18) +#define PIN_PB18A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PB18 External Interrupt Line */ +#define PIN_PC02A_EIC_EXTINT2 _L_(66) /**< \brief EIC signal: EXTINT2 on PC02 mux A */ +#define MUX_PC02A_EIC_EXTINT2 _L_(0) +#define PINMUX_PC02A_EIC_EXTINT2 ((PIN_PC02A_EIC_EXTINT2 << 16) | MUX_PC02A_EIC_EXTINT2) +#define PORT_PC02A_EIC_EXTINT2 (_UL_(1) << 2) +#define PIN_PC02A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PC02 External Interrupt Line */ +#define PIN_PC18A_EIC_EXTINT2 _L_(82) /**< \brief EIC signal: EXTINT2 on PC18 mux A */ +#define MUX_PC18A_EIC_EXTINT2 _L_(0) +#define PINMUX_PC18A_EIC_EXTINT2 ((PIN_PC18A_EIC_EXTINT2 << 16) | MUX_PC18A_EIC_EXTINT2) +#define PORT_PC18A_EIC_EXTINT2 (_UL_(1) << 18) +#define PIN_PC18A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PC18 External Interrupt Line */ +#define PIN_PA03A_EIC_EXTINT3 _L_(3) /**< \brief EIC signal: EXTINT3 on PA03 mux A */ +#define MUX_PA03A_EIC_EXTINT3 _L_(0) +#define PINMUX_PA03A_EIC_EXTINT3 ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3) +#define PORT_PA03A_EIC_EXTINT3 (_UL_(1) << 3) +#define PIN_PA03A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PA03 External Interrupt Line */ +#define PIN_PA19A_EIC_EXTINT3 _L_(19) /**< \brief EIC signal: EXTINT3 on PA19 mux A */ +#define MUX_PA19A_EIC_EXTINT3 _L_(0) +#define PINMUX_PA19A_EIC_EXTINT3 ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3) +#define PORT_PA19A_EIC_EXTINT3 (_UL_(1) << 19) +#define PIN_PA19A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PA19 External Interrupt Line */ +#define PIN_PB03A_EIC_EXTINT3 _L_(35) /**< \brief EIC signal: EXTINT3 on PB03 mux A */ +#define MUX_PB03A_EIC_EXTINT3 _L_(0) +#define PINMUX_PB03A_EIC_EXTINT3 ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3) +#define PORT_PB03A_EIC_EXTINT3 (_UL_(1) << 3) +#define PIN_PB03A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PB03 External Interrupt Line */ +#define PIN_PB19A_EIC_EXTINT3 _L_(51) /**< \brief EIC signal: EXTINT3 on PB19 mux A */ +#define MUX_PB19A_EIC_EXTINT3 _L_(0) +#define PINMUX_PB19A_EIC_EXTINT3 ((PIN_PB19A_EIC_EXTINT3 << 16) | MUX_PB19A_EIC_EXTINT3) +#define PORT_PB19A_EIC_EXTINT3 (_UL_(1) << 19) +#define PIN_PB19A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PB19 External Interrupt Line */ +#define PIN_PC03A_EIC_EXTINT3 _L_(67) /**< \brief EIC signal: EXTINT3 on PC03 mux A */ +#define MUX_PC03A_EIC_EXTINT3 _L_(0) +#define PINMUX_PC03A_EIC_EXTINT3 ((PIN_PC03A_EIC_EXTINT3 << 16) | MUX_PC03A_EIC_EXTINT3) +#define PORT_PC03A_EIC_EXTINT3 (_UL_(1) << 3) +#define PIN_PC03A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PC03 External Interrupt Line */ +#define PIN_PC19A_EIC_EXTINT3 _L_(83) /**< \brief EIC signal: EXTINT3 on PC19 mux A */ +#define MUX_PC19A_EIC_EXTINT3 _L_(0) +#define PINMUX_PC19A_EIC_EXTINT3 ((PIN_PC19A_EIC_EXTINT3 << 16) | MUX_PC19A_EIC_EXTINT3) +#define PORT_PC19A_EIC_EXTINT3 (_UL_(1) << 19) +#define PIN_PC19A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PC19 External Interrupt Line */ +#define PIN_PD08A_EIC_EXTINT3 _L_(104) /**< \brief EIC signal: EXTINT3 on PD08 mux A */ +#define MUX_PD08A_EIC_EXTINT3 _L_(0) +#define PINMUX_PD08A_EIC_EXTINT3 ((PIN_PD08A_EIC_EXTINT3 << 16) | MUX_PD08A_EIC_EXTINT3) +#define PORT_PD08A_EIC_EXTINT3 (_UL_(1) << 8) +#define PIN_PD08A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PD08 External Interrupt Line */ +#define PIN_PA04A_EIC_EXTINT4 _L_(4) /**< \brief EIC signal: EXTINT4 on PA04 mux A */ +#define MUX_PA04A_EIC_EXTINT4 _L_(0) +#define PINMUX_PA04A_EIC_EXTINT4 ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4) +#define PORT_PA04A_EIC_EXTINT4 (_UL_(1) << 4) +#define PIN_PA04A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PA04 External Interrupt Line */ +#define PIN_PA20A_EIC_EXTINT4 _L_(20) /**< \brief EIC signal: EXTINT4 on PA20 mux A */ +#define MUX_PA20A_EIC_EXTINT4 _L_(0) +#define PINMUX_PA20A_EIC_EXTINT4 ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4) +#define PORT_PA20A_EIC_EXTINT4 (_UL_(1) << 20) +#define PIN_PA20A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PA20 External Interrupt Line */ +#define PIN_PB04A_EIC_EXTINT4 _L_(36) /**< \brief EIC signal: EXTINT4 on PB04 mux A */ +#define MUX_PB04A_EIC_EXTINT4 _L_(0) +#define PINMUX_PB04A_EIC_EXTINT4 ((PIN_PB04A_EIC_EXTINT4 << 16) | MUX_PB04A_EIC_EXTINT4) +#define PORT_PB04A_EIC_EXTINT4 (_UL_(1) << 4) +#define PIN_PB04A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PB04 External Interrupt Line */ +#define PIN_PB20A_EIC_EXTINT4 _L_(52) /**< \brief EIC signal: EXTINT4 on PB20 mux A */ +#define MUX_PB20A_EIC_EXTINT4 _L_(0) +#define PINMUX_PB20A_EIC_EXTINT4 ((PIN_PB20A_EIC_EXTINT4 << 16) | MUX_PB20A_EIC_EXTINT4) +#define PORT_PB20A_EIC_EXTINT4 (_UL_(1) << 20) +#define PIN_PB20A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PB20 External Interrupt Line */ +#define PIN_PC04A_EIC_EXTINT4 _L_(68) /**< \brief EIC signal: EXTINT4 on PC04 mux A */ +#define MUX_PC04A_EIC_EXTINT4 _L_(0) +#define PINMUX_PC04A_EIC_EXTINT4 ((PIN_PC04A_EIC_EXTINT4 << 16) | MUX_PC04A_EIC_EXTINT4) +#define PORT_PC04A_EIC_EXTINT4 (_UL_(1) << 4) +#define PIN_PC04A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PC04 External Interrupt Line */ +#define PIN_PC20A_EIC_EXTINT4 _L_(84) /**< \brief EIC signal: EXTINT4 on PC20 mux A */ +#define MUX_PC20A_EIC_EXTINT4 _L_(0) +#define PINMUX_PC20A_EIC_EXTINT4 ((PIN_PC20A_EIC_EXTINT4 << 16) | MUX_PC20A_EIC_EXTINT4) +#define PORT_PC20A_EIC_EXTINT4 (_UL_(1) << 20) +#define PIN_PC20A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PC20 External Interrupt Line */ +#define PIN_PD09A_EIC_EXTINT4 _L_(105) /**< \brief EIC signal: EXTINT4 on PD09 mux A */ +#define MUX_PD09A_EIC_EXTINT4 _L_(0) +#define PINMUX_PD09A_EIC_EXTINT4 ((PIN_PD09A_EIC_EXTINT4 << 16) | MUX_PD09A_EIC_EXTINT4) +#define PORT_PD09A_EIC_EXTINT4 (_UL_(1) << 9) +#define PIN_PD09A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PD09 External Interrupt Line */ +#define PIN_PA05A_EIC_EXTINT5 _L_(5) /**< \brief EIC signal: EXTINT5 on PA05 mux A */ +#define MUX_PA05A_EIC_EXTINT5 _L_(0) +#define PINMUX_PA05A_EIC_EXTINT5 ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5) +#define PORT_PA05A_EIC_EXTINT5 (_UL_(1) << 5) +#define PIN_PA05A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PA05 External Interrupt Line */ +#define PIN_PA21A_EIC_EXTINT5 _L_(21) /**< \brief EIC signal: EXTINT5 on PA21 mux A */ +#define MUX_PA21A_EIC_EXTINT5 _L_(0) +#define PINMUX_PA21A_EIC_EXTINT5 ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5) +#define PORT_PA21A_EIC_EXTINT5 (_UL_(1) << 21) +#define PIN_PA21A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PA21 External Interrupt Line */ +#define PIN_PB05A_EIC_EXTINT5 _L_(37) /**< \brief EIC signal: EXTINT5 on PB05 mux A */ +#define MUX_PB05A_EIC_EXTINT5 _L_(0) +#define PINMUX_PB05A_EIC_EXTINT5 ((PIN_PB05A_EIC_EXTINT5 << 16) | MUX_PB05A_EIC_EXTINT5) +#define PORT_PB05A_EIC_EXTINT5 (_UL_(1) << 5) +#define PIN_PB05A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PB05 External Interrupt Line */ +#define PIN_PB21A_EIC_EXTINT5 _L_(53) /**< \brief EIC signal: EXTINT5 on PB21 mux A */ +#define MUX_PB21A_EIC_EXTINT5 _L_(0) +#define PINMUX_PB21A_EIC_EXTINT5 ((PIN_PB21A_EIC_EXTINT5 << 16) | MUX_PB21A_EIC_EXTINT5) +#define PORT_PB21A_EIC_EXTINT5 (_UL_(1) << 21) +#define PIN_PB21A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PB21 External Interrupt Line */ +#define PIN_PC05A_EIC_EXTINT5 _L_(69) /**< \brief EIC signal: EXTINT5 on PC05 mux A */ +#define MUX_PC05A_EIC_EXTINT5 _L_(0) +#define PINMUX_PC05A_EIC_EXTINT5 ((PIN_PC05A_EIC_EXTINT5 << 16) | MUX_PC05A_EIC_EXTINT5) +#define PORT_PC05A_EIC_EXTINT5 (_UL_(1) << 5) +#define PIN_PC05A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PC05 External Interrupt Line */ +#define PIN_PC21A_EIC_EXTINT5 _L_(85) /**< \brief EIC signal: EXTINT5 on PC21 mux A */ +#define MUX_PC21A_EIC_EXTINT5 _L_(0) +#define PINMUX_PC21A_EIC_EXTINT5 ((PIN_PC21A_EIC_EXTINT5 << 16) | MUX_PC21A_EIC_EXTINT5) +#define PORT_PC21A_EIC_EXTINT5 (_UL_(1) << 21) +#define PIN_PC21A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PC21 External Interrupt Line */ +#define PIN_PD10A_EIC_EXTINT5 _L_(106) /**< \brief EIC signal: EXTINT5 on PD10 mux A */ +#define MUX_PD10A_EIC_EXTINT5 _L_(0) +#define PINMUX_PD10A_EIC_EXTINT5 ((PIN_PD10A_EIC_EXTINT5 << 16) | MUX_PD10A_EIC_EXTINT5) +#define PORT_PD10A_EIC_EXTINT5 (_UL_(1) << 10) +#define PIN_PD10A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PD10 External Interrupt Line */ +#define PIN_PA06A_EIC_EXTINT6 _L_(6) /**< \brief EIC signal: EXTINT6 on PA06 mux A */ +#define MUX_PA06A_EIC_EXTINT6 _L_(0) +#define PINMUX_PA06A_EIC_EXTINT6 ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6) +#define PORT_PA06A_EIC_EXTINT6 (_UL_(1) << 6) +#define PIN_PA06A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PA06 External Interrupt Line */ +#define PIN_PA22A_EIC_EXTINT6 _L_(22) /**< \brief EIC signal: EXTINT6 on PA22 mux A */ +#define MUX_PA22A_EIC_EXTINT6 _L_(0) +#define PINMUX_PA22A_EIC_EXTINT6 ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6) +#define PORT_PA22A_EIC_EXTINT6 (_UL_(1) << 22) +#define PIN_PA22A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PA22 External Interrupt Line */ +#define PIN_PB06A_EIC_EXTINT6 _L_(38) /**< \brief EIC signal: EXTINT6 on PB06 mux A */ +#define MUX_PB06A_EIC_EXTINT6 _L_(0) +#define PINMUX_PB06A_EIC_EXTINT6 ((PIN_PB06A_EIC_EXTINT6 << 16) | MUX_PB06A_EIC_EXTINT6) +#define PORT_PB06A_EIC_EXTINT6 (_UL_(1) << 6) +#define PIN_PB06A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PB06 External Interrupt Line */ +#define PIN_PB22A_EIC_EXTINT6 _L_(54) /**< \brief EIC signal: EXTINT6 on PB22 mux A */ +#define MUX_PB22A_EIC_EXTINT6 _L_(0) +#define PINMUX_PB22A_EIC_EXTINT6 ((PIN_PB22A_EIC_EXTINT6 << 16) | MUX_PB22A_EIC_EXTINT6) +#define PORT_PB22A_EIC_EXTINT6 (_UL_(1) << 22) +#define PIN_PB22A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PB22 External Interrupt Line */ +#define PIN_PC06A_EIC_EXTINT6 _L_(70) /**< \brief EIC signal: EXTINT6 on PC06 mux A */ +#define MUX_PC06A_EIC_EXTINT6 _L_(0) +#define PINMUX_PC06A_EIC_EXTINT6 ((PIN_PC06A_EIC_EXTINT6 << 16) | MUX_PC06A_EIC_EXTINT6) +#define PORT_PC06A_EIC_EXTINT6 (_UL_(1) << 6) +#define PIN_PC06A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PC06 External Interrupt Line */ +#define PIN_PC22A_EIC_EXTINT6 _L_(86) /**< \brief EIC signal: EXTINT6 on PC22 mux A */ +#define MUX_PC22A_EIC_EXTINT6 _L_(0) +#define PINMUX_PC22A_EIC_EXTINT6 ((PIN_PC22A_EIC_EXTINT6 << 16) | MUX_PC22A_EIC_EXTINT6) +#define PORT_PC22A_EIC_EXTINT6 (_UL_(1) << 22) +#define PIN_PC22A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PC22 External Interrupt Line */ +#define PIN_PD11A_EIC_EXTINT6 _L_(107) /**< \brief EIC signal: EXTINT6 on PD11 mux A */ +#define MUX_PD11A_EIC_EXTINT6 _L_(0) +#define PINMUX_PD11A_EIC_EXTINT6 ((PIN_PD11A_EIC_EXTINT6 << 16) | MUX_PD11A_EIC_EXTINT6) +#define PORT_PD11A_EIC_EXTINT6 (_UL_(1) << 11) +#define PIN_PD11A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PD11 External Interrupt Line */ +#define PIN_PA07A_EIC_EXTINT7 _L_(7) /**< \brief EIC signal: EXTINT7 on PA07 mux A */ +#define MUX_PA07A_EIC_EXTINT7 _L_(0) +#define PINMUX_PA07A_EIC_EXTINT7 ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7) +#define PORT_PA07A_EIC_EXTINT7 (_UL_(1) << 7) +#define PIN_PA07A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PA07 External Interrupt Line */ +#define PIN_PA23A_EIC_EXTINT7 _L_(23) /**< \brief EIC signal: EXTINT7 on PA23 mux A */ +#define MUX_PA23A_EIC_EXTINT7 _L_(0) +#define PINMUX_PA23A_EIC_EXTINT7 ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7) +#define PORT_PA23A_EIC_EXTINT7 (_UL_(1) << 23) +#define PIN_PA23A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PA23 External Interrupt Line */ +#define PIN_PB07A_EIC_EXTINT7 _L_(39) /**< \brief EIC signal: EXTINT7 on PB07 mux A */ +#define MUX_PB07A_EIC_EXTINT7 _L_(0) +#define PINMUX_PB07A_EIC_EXTINT7 ((PIN_PB07A_EIC_EXTINT7 << 16) | MUX_PB07A_EIC_EXTINT7) +#define PORT_PB07A_EIC_EXTINT7 (_UL_(1) << 7) +#define PIN_PB07A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PB07 External Interrupt Line */ +#define PIN_PB23A_EIC_EXTINT7 _L_(55) /**< \brief EIC signal: EXTINT7 on PB23 mux A */ +#define MUX_PB23A_EIC_EXTINT7 _L_(0) +#define PINMUX_PB23A_EIC_EXTINT7 ((PIN_PB23A_EIC_EXTINT7 << 16) | MUX_PB23A_EIC_EXTINT7) +#define PORT_PB23A_EIC_EXTINT7 (_UL_(1) << 23) +#define PIN_PB23A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PB23 External Interrupt Line */ +#define PIN_PC23A_EIC_EXTINT7 _L_(87) /**< \brief EIC signal: EXTINT7 on PC23 mux A */ +#define MUX_PC23A_EIC_EXTINT7 _L_(0) +#define PINMUX_PC23A_EIC_EXTINT7 ((PIN_PC23A_EIC_EXTINT7 << 16) | MUX_PC23A_EIC_EXTINT7) +#define PORT_PC23A_EIC_EXTINT7 (_UL_(1) << 23) +#define PIN_PC23A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PC23 External Interrupt Line */ +#define PIN_PD12A_EIC_EXTINT7 _L_(108) /**< \brief EIC signal: EXTINT7 on PD12 mux A */ +#define MUX_PD12A_EIC_EXTINT7 _L_(0) +#define PINMUX_PD12A_EIC_EXTINT7 ((PIN_PD12A_EIC_EXTINT7 << 16) | MUX_PD12A_EIC_EXTINT7) +#define PORT_PD12A_EIC_EXTINT7 (_UL_(1) << 12) +#define PIN_PD12A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PD12 External Interrupt Line */ +#define PIN_PA24A_EIC_EXTINT8 _L_(24) /**< \brief EIC signal: EXTINT8 on PA24 mux A */ +#define MUX_PA24A_EIC_EXTINT8 _L_(0) +#define PINMUX_PA24A_EIC_EXTINT8 ((PIN_PA24A_EIC_EXTINT8 << 16) | MUX_PA24A_EIC_EXTINT8) +#define PORT_PA24A_EIC_EXTINT8 (_UL_(1) << 24) +#define PIN_PA24A_EIC_EXTINT_NUM _L_(8) /**< \brief EIC signal: PIN_PA24 External Interrupt Line */ +#define PIN_PB08A_EIC_EXTINT8 _L_(40) /**< \brief EIC signal: EXTINT8 on PB08 mux A */ +#define MUX_PB08A_EIC_EXTINT8 _L_(0) +#define PINMUX_PB08A_EIC_EXTINT8 ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8) +#define PORT_PB08A_EIC_EXTINT8 (_UL_(1) << 8) +#define PIN_PB08A_EIC_EXTINT_NUM _L_(8) /**< \brief EIC signal: PIN_PB08 External Interrupt Line */ +#define PIN_PB24A_EIC_EXTINT8 _L_(56) /**< \brief EIC signal: EXTINT8 on PB24 mux A */ +#define MUX_PB24A_EIC_EXTINT8 _L_(0) +#define PINMUX_PB24A_EIC_EXTINT8 ((PIN_PB24A_EIC_EXTINT8 << 16) | MUX_PB24A_EIC_EXTINT8) +#define PORT_PB24A_EIC_EXTINT8 (_UL_(1) << 24) +#define PIN_PB24A_EIC_EXTINT_NUM _L_(8) /**< \brief EIC signal: PIN_PB24 External Interrupt Line */ +#define PIN_PC24A_EIC_EXTINT8 _L_(88) /**< \brief EIC signal: EXTINT8 on PC24 mux A */ +#define MUX_PC24A_EIC_EXTINT8 _L_(0) +#define PINMUX_PC24A_EIC_EXTINT8 ((PIN_PC24A_EIC_EXTINT8 << 16) | MUX_PC24A_EIC_EXTINT8) +#define PORT_PC24A_EIC_EXTINT8 (_UL_(1) << 24) +#define PIN_PC24A_EIC_EXTINT_NUM _L_(8) /**< \brief EIC signal: PIN_PC24 External Interrupt Line */ +#define PIN_PA09A_EIC_EXTINT9 _L_(9) /**< \brief EIC signal: EXTINT9 on PA09 mux A */ +#define MUX_PA09A_EIC_EXTINT9 _L_(0) +#define PINMUX_PA09A_EIC_EXTINT9 ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9) +#define PORT_PA09A_EIC_EXTINT9 (_UL_(1) << 9) +#define PIN_PA09A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PA09 External Interrupt Line */ +#define PIN_PA25A_EIC_EXTINT9 _L_(25) /**< \brief EIC signal: EXTINT9 on PA25 mux A */ +#define MUX_PA25A_EIC_EXTINT9 _L_(0) +#define PINMUX_PA25A_EIC_EXTINT9 ((PIN_PA25A_EIC_EXTINT9 << 16) | MUX_PA25A_EIC_EXTINT9) +#define PORT_PA25A_EIC_EXTINT9 (_UL_(1) << 25) +#define PIN_PA25A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PA25 External Interrupt Line */ +#define PIN_PB09A_EIC_EXTINT9 _L_(41) /**< \brief EIC signal: EXTINT9 on PB09 mux A */ +#define MUX_PB09A_EIC_EXTINT9 _L_(0) +#define PINMUX_PB09A_EIC_EXTINT9 ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9) +#define PORT_PB09A_EIC_EXTINT9 (_UL_(1) << 9) +#define PIN_PB09A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PB09 External Interrupt Line */ +#define PIN_PB25A_EIC_EXTINT9 _L_(57) /**< \brief EIC signal: EXTINT9 on PB25 mux A */ +#define MUX_PB25A_EIC_EXTINT9 _L_(0) +#define PINMUX_PB25A_EIC_EXTINT9 ((PIN_PB25A_EIC_EXTINT9 << 16) | MUX_PB25A_EIC_EXTINT9) +#define PORT_PB25A_EIC_EXTINT9 (_UL_(1) << 25) +#define PIN_PB25A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PB25 External Interrupt Line */ +#define PIN_PC07A_EIC_EXTINT9 _L_(71) /**< \brief EIC signal: EXTINT9 on PC07 mux A */ +#define MUX_PC07A_EIC_EXTINT9 _L_(0) +#define PINMUX_PC07A_EIC_EXTINT9 ((PIN_PC07A_EIC_EXTINT9 << 16) | MUX_PC07A_EIC_EXTINT9) +#define PORT_PC07A_EIC_EXTINT9 (_UL_(1) << 7) +#define PIN_PC07A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PC07 External Interrupt Line */ +#define PIN_PC25A_EIC_EXTINT9 _L_(89) /**< \brief EIC signal: EXTINT9 on PC25 mux A */ +#define MUX_PC25A_EIC_EXTINT9 _L_(0) +#define PINMUX_PC25A_EIC_EXTINT9 ((PIN_PC25A_EIC_EXTINT9 << 16) | MUX_PC25A_EIC_EXTINT9) +#define PORT_PC25A_EIC_EXTINT9 (_UL_(1) << 25) +#define PIN_PC25A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PC25 External Interrupt Line */ +#define PIN_PA10A_EIC_EXTINT10 _L_(10) /**< \brief EIC signal: EXTINT10 on PA10 mux A */ +#define MUX_PA10A_EIC_EXTINT10 _L_(0) +#define PINMUX_PA10A_EIC_EXTINT10 ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10) +#define PORT_PA10A_EIC_EXTINT10 (_UL_(1) << 10) +#define PIN_PA10A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PA10 External Interrupt Line */ +#define PIN_PB10A_EIC_EXTINT10 _L_(42) /**< \brief EIC signal: EXTINT10 on PB10 mux A */ +#define MUX_PB10A_EIC_EXTINT10 _L_(0) +#define PINMUX_PB10A_EIC_EXTINT10 ((PIN_PB10A_EIC_EXTINT10 << 16) | MUX_PB10A_EIC_EXTINT10) +#define PORT_PB10A_EIC_EXTINT10 (_UL_(1) << 10) +#define PIN_PB10A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PB10 External Interrupt Line */ +#define PIN_PC10A_EIC_EXTINT10 _L_(74) /**< \brief EIC signal: EXTINT10 on PC10 mux A */ +#define MUX_PC10A_EIC_EXTINT10 _L_(0) +#define PINMUX_PC10A_EIC_EXTINT10 ((PIN_PC10A_EIC_EXTINT10 << 16) | MUX_PC10A_EIC_EXTINT10) +#define PORT_PC10A_EIC_EXTINT10 (_UL_(1) << 10) +#define PIN_PC10A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PC10 External Interrupt Line */ +#define PIN_PC26A_EIC_EXTINT10 _L_(90) /**< \brief EIC signal: EXTINT10 on PC26 mux A */ +#define MUX_PC26A_EIC_EXTINT10 _L_(0) +#define PINMUX_PC26A_EIC_EXTINT10 ((PIN_PC26A_EIC_EXTINT10 << 16) | MUX_PC26A_EIC_EXTINT10) +#define PORT_PC26A_EIC_EXTINT10 (_UL_(1) << 26) +#define PIN_PC26A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PC26 External Interrupt Line */ +#define PIN_PD20A_EIC_EXTINT10 _L_(116) /**< \brief EIC signal: EXTINT10 on PD20 mux A */ +#define MUX_PD20A_EIC_EXTINT10 _L_(0) +#define PINMUX_PD20A_EIC_EXTINT10 ((PIN_PD20A_EIC_EXTINT10 << 16) | MUX_PD20A_EIC_EXTINT10) +#define PORT_PD20A_EIC_EXTINT10 (_UL_(1) << 20) +#define PIN_PD20A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PD20 External Interrupt Line */ +#define PIN_PA11A_EIC_EXTINT11 _L_(11) /**< \brief EIC signal: EXTINT11 on PA11 mux A */ +#define MUX_PA11A_EIC_EXTINT11 _L_(0) +#define PINMUX_PA11A_EIC_EXTINT11 ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11) +#define PORT_PA11A_EIC_EXTINT11 (_UL_(1) << 11) +#define PIN_PA11A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PA11 External Interrupt Line */ +#define PIN_PA27A_EIC_EXTINT11 _L_(27) /**< \brief EIC signal: EXTINT11 on PA27 mux A */ +#define MUX_PA27A_EIC_EXTINT11 _L_(0) +#define PINMUX_PA27A_EIC_EXTINT11 ((PIN_PA27A_EIC_EXTINT11 << 16) | MUX_PA27A_EIC_EXTINT11) +#define PORT_PA27A_EIC_EXTINT11 (_UL_(1) << 27) +#define PIN_PA27A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PA27 External Interrupt Line */ +#define PIN_PB11A_EIC_EXTINT11 _L_(43) /**< \brief EIC signal: EXTINT11 on PB11 mux A */ +#define MUX_PB11A_EIC_EXTINT11 _L_(0) +#define PINMUX_PB11A_EIC_EXTINT11 ((PIN_PB11A_EIC_EXTINT11 << 16) | MUX_PB11A_EIC_EXTINT11) +#define PORT_PB11A_EIC_EXTINT11 (_UL_(1) << 11) +#define PIN_PB11A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PB11 External Interrupt Line */ +#define PIN_PC11A_EIC_EXTINT11 _L_(75) /**< \brief EIC signal: EXTINT11 on PC11 mux A */ +#define MUX_PC11A_EIC_EXTINT11 _L_(0) +#define PINMUX_PC11A_EIC_EXTINT11 ((PIN_PC11A_EIC_EXTINT11 << 16) | MUX_PC11A_EIC_EXTINT11) +#define PORT_PC11A_EIC_EXTINT11 (_UL_(1) << 11) +#define PIN_PC11A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PC11 External Interrupt Line */ +#define PIN_PC27A_EIC_EXTINT11 _L_(91) /**< \brief EIC signal: EXTINT11 on PC27 mux A */ +#define MUX_PC27A_EIC_EXTINT11 _L_(0) +#define PINMUX_PC27A_EIC_EXTINT11 ((PIN_PC27A_EIC_EXTINT11 << 16) | MUX_PC27A_EIC_EXTINT11) +#define PORT_PC27A_EIC_EXTINT11 (_UL_(1) << 27) +#define PIN_PC27A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PC27 External Interrupt Line */ +#define PIN_PD21A_EIC_EXTINT11 _L_(117) /**< \brief EIC signal: EXTINT11 on PD21 mux A */ +#define MUX_PD21A_EIC_EXTINT11 _L_(0) +#define PINMUX_PD21A_EIC_EXTINT11 ((PIN_PD21A_EIC_EXTINT11 << 16) | MUX_PD21A_EIC_EXTINT11) +#define PORT_PD21A_EIC_EXTINT11 (_UL_(1) << 21) +#define PIN_PD21A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PD21 External Interrupt Line */ +#define PIN_PA12A_EIC_EXTINT12 _L_(12) /**< \brief EIC signal: EXTINT12 on PA12 mux A */ +#define MUX_PA12A_EIC_EXTINT12 _L_(0) +#define PINMUX_PA12A_EIC_EXTINT12 ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12) +#define PORT_PA12A_EIC_EXTINT12 (_UL_(1) << 12) +#define PIN_PA12A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PA12 External Interrupt Line */ +#define PIN_PB12A_EIC_EXTINT12 _L_(44) /**< \brief EIC signal: EXTINT12 on PB12 mux A */ +#define MUX_PB12A_EIC_EXTINT12 _L_(0) +#define PINMUX_PB12A_EIC_EXTINT12 ((PIN_PB12A_EIC_EXTINT12 << 16) | MUX_PB12A_EIC_EXTINT12) +#define PORT_PB12A_EIC_EXTINT12 (_UL_(1) << 12) +#define PIN_PB12A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PB12 External Interrupt Line */ +#define PIN_PB26A_EIC_EXTINT12 _L_(58) /**< \brief EIC signal: EXTINT12 on PB26 mux A */ +#define MUX_PB26A_EIC_EXTINT12 _L_(0) +#define PINMUX_PB26A_EIC_EXTINT12 ((PIN_PB26A_EIC_EXTINT12 << 16) | MUX_PB26A_EIC_EXTINT12) +#define PORT_PB26A_EIC_EXTINT12 (_UL_(1) << 26) +#define PIN_PB26A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PB26 External Interrupt Line */ +#define PIN_PC12A_EIC_EXTINT12 _L_(76) /**< \brief EIC signal: EXTINT12 on PC12 mux A */ +#define MUX_PC12A_EIC_EXTINT12 _L_(0) +#define PINMUX_PC12A_EIC_EXTINT12 ((PIN_PC12A_EIC_EXTINT12 << 16) | MUX_PC12A_EIC_EXTINT12) +#define PORT_PC12A_EIC_EXTINT12 (_UL_(1) << 12) +#define PIN_PC12A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PC12 External Interrupt Line */ +#define PIN_PC28A_EIC_EXTINT12 _L_(92) /**< \brief EIC signal: EXTINT12 on PC28 mux A */ +#define MUX_PC28A_EIC_EXTINT12 _L_(0) +#define PINMUX_PC28A_EIC_EXTINT12 ((PIN_PC28A_EIC_EXTINT12 << 16) | MUX_PC28A_EIC_EXTINT12) +#define PORT_PC28A_EIC_EXTINT12 (_UL_(1) << 28) +#define PIN_PC28A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PC28 External Interrupt Line */ +#define PIN_PA13A_EIC_EXTINT13 _L_(13) /**< \brief EIC signal: EXTINT13 on PA13 mux A */ +#define MUX_PA13A_EIC_EXTINT13 _L_(0) +#define PINMUX_PA13A_EIC_EXTINT13 ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13) +#define PORT_PA13A_EIC_EXTINT13 (_UL_(1) << 13) +#define PIN_PA13A_EIC_EXTINT_NUM _L_(13) /**< \brief EIC signal: PIN_PA13 External Interrupt Line */ +#define PIN_PB13A_EIC_EXTINT13 _L_(45) /**< \brief EIC signal: EXTINT13 on PB13 mux A */ +#define MUX_PB13A_EIC_EXTINT13 _L_(0) +#define PINMUX_PB13A_EIC_EXTINT13 ((PIN_PB13A_EIC_EXTINT13 << 16) | MUX_PB13A_EIC_EXTINT13) +#define PORT_PB13A_EIC_EXTINT13 (_UL_(1) << 13) +#define PIN_PB13A_EIC_EXTINT_NUM _L_(13) /**< \brief EIC signal: PIN_PB13 External Interrupt Line */ +#define PIN_PB27A_EIC_EXTINT13 _L_(59) /**< \brief EIC signal: EXTINT13 on PB27 mux A */ +#define MUX_PB27A_EIC_EXTINT13 _L_(0) +#define PINMUX_PB27A_EIC_EXTINT13 ((PIN_PB27A_EIC_EXTINT13 << 16) | MUX_PB27A_EIC_EXTINT13) +#define PORT_PB27A_EIC_EXTINT13 (_UL_(1) << 27) +#define PIN_PB27A_EIC_EXTINT_NUM _L_(13) /**< \brief EIC signal: PIN_PB27 External Interrupt Line */ +#define PIN_PC13A_EIC_EXTINT13 _L_(77) /**< \brief EIC signal: EXTINT13 on PC13 mux A */ +#define MUX_PC13A_EIC_EXTINT13 _L_(0) +#define PINMUX_PC13A_EIC_EXTINT13 ((PIN_PC13A_EIC_EXTINT13 << 16) | MUX_PC13A_EIC_EXTINT13) +#define PORT_PC13A_EIC_EXTINT13 (_UL_(1) << 13) +#define PIN_PC13A_EIC_EXTINT_NUM _L_(13) /**< \brief EIC signal: PIN_PC13 External Interrupt Line */ +#define PIN_PA30A_EIC_EXTINT14 _L_(30) /**< \brief EIC signal: EXTINT14 on PA30 mux A */ +#define MUX_PA30A_EIC_EXTINT14 _L_(0) +#define PINMUX_PA30A_EIC_EXTINT14 ((PIN_PA30A_EIC_EXTINT14 << 16) | MUX_PA30A_EIC_EXTINT14) +#define PORT_PA30A_EIC_EXTINT14 (_UL_(1) << 30) +#define PIN_PA30A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PA30 External Interrupt Line */ +#define PIN_PB14A_EIC_EXTINT14 _L_(46) /**< \brief EIC signal: EXTINT14 on PB14 mux A */ +#define MUX_PB14A_EIC_EXTINT14 _L_(0) +#define PINMUX_PB14A_EIC_EXTINT14 ((PIN_PB14A_EIC_EXTINT14 << 16) | MUX_PB14A_EIC_EXTINT14) +#define PORT_PB14A_EIC_EXTINT14 (_UL_(1) << 14) +#define PIN_PB14A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PB14 External Interrupt Line */ +#define PIN_PB28A_EIC_EXTINT14 _L_(60) /**< \brief EIC signal: EXTINT14 on PB28 mux A */ +#define MUX_PB28A_EIC_EXTINT14 _L_(0) +#define PINMUX_PB28A_EIC_EXTINT14 ((PIN_PB28A_EIC_EXTINT14 << 16) | MUX_PB28A_EIC_EXTINT14) +#define PORT_PB28A_EIC_EXTINT14 (_UL_(1) << 28) +#define PIN_PB28A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PB28 External Interrupt Line */ +#define PIN_PB30A_EIC_EXTINT14 _L_(62) /**< \brief EIC signal: EXTINT14 on PB30 mux A */ +#define MUX_PB30A_EIC_EXTINT14 _L_(0) +#define PINMUX_PB30A_EIC_EXTINT14 ((PIN_PB30A_EIC_EXTINT14 << 16) | MUX_PB30A_EIC_EXTINT14) +#define PORT_PB30A_EIC_EXTINT14 (_UL_(1) << 30) +#define PIN_PB30A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PB30 External Interrupt Line */ +#define PIN_PC14A_EIC_EXTINT14 _L_(78) /**< \brief EIC signal: EXTINT14 on PC14 mux A */ +#define MUX_PC14A_EIC_EXTINT14 _L_(0) +#define PINMUX_PC14A_EIC_EXTINT14 ((PIN_PC14A_EIC_EXTINT14 << 16) | MUX_PC14A_EIC_EXTINT14) +#define PORT_PC14A_EIC_EXTINT14 (_UL_(1) << 14) +#define PIN_PC14A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PC14 External Interrupt Line */ +#define PIN_PC30A_EIC_EXTINT14 _L_(94) /**< \brief EIC signal: EXTINT14 on PC30 mux A */ +#define MUX_PC30A_EIC_EXTINT14 _L_(0) +#define PINMUX_PC30A_EIC_EXTINT14 ((PIN_PC30A_EIC_EXTINT14 << 16) | MUX_PC30A_EIC_EXTINT14) +#define PORT_PC30A_EIC_EXTINT14 (_UL_(1) << 30) +#define PIN_PC30A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PC30 External Interrupt Line */ +#define PIN_PA14A_EIC_EXTINT14 _L_(14) /**< \brief EIC signal: EXTINT14 on PA14 mux A */ +#define MUX_PA14A_EIC_EXTINT14 _L_(0) +#define PINMUX_PA14A_EIC_EXTINT14 ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14) +#define PORT_PA14A_EIC_EXTINT14 (_UL_(1) << 14) +#define PIN_PA14A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PA14 External Interrupt Line */ +#define PIN_PA15A_EIC_EXTINT15 _L_(15) /**< \brief EIC signal: EXTINT15 on PA15 mux A */ +#define MUX_PA15A_EIC_EXTINT15 _L_(0) +#define PINMUX_PA15A_EIC_EXTINT15 ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15) +#define PORT_PA15A_EIC_EXTINT15 (_UL_(1) << 15) +#define PIN_PA15A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PA15 External Interrupt Line */ +#define PIN_PA31A_EIC_EXTINT15 _L_(31) /**< \brief EIC signal: EXTINT15 on PA31 mux A */ +#define MUX_PA31A_EIC_EXTINT15 _L_(0) +#define PINMUX_PA31A_EIC_EXTINT15 ((PIN_PA31A_EIC_EXTINT15 << 16) | MUX_PA31A_EIC_EXTINT15) +#define PORT_PA31A_EIC_EXTINT15 (_UL_(1) << 31) +#define PIN_PA31A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PA31 External Interrupt Line */ +#define PIN_PB15A_EIC_EXTINT15 _L_(47) /**< \brief EIC signal: EXTINT15 on PB15 mux A */ +#define MUX_PB15A_EIC_EXTINT15 _L_(0) +#define PINMUX_PB15A_EIC_EXTINT15 ((PIN_PB15A_EIC_EXTINT15 << 16) | MUX_PB15A_EIC_EXTINT15) +#define PORT_PB15A_EIC_EXTINT15 (_UL_(1) << 15) +#define PIN_PB15A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PB15 External Interrupt Line */ +#define PIN_PB29A_EIC_EXTINT15 _L_(61) /**< \brief EIC signal: EXTINT15 on PB29 mux A */ +#define MUX_PB29A_EIC_EXTINT15 _L_(0) +#define PINMUX_PB29A_EIC_EXTINT15 ((PIN_PB29A_EIC_EXTINT15 << 16) | MUX_PB29A_EIC_EXTINT15) +#define PORT_PB29A_EIC_EXTINT15 (_UL_(1) << 29) +#define PIN_PB29A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PB29 External Interrupt Line */ +#define PIN_PB31A_EIC_EXTINT15 _L_(63) /**< \brief EIC signal: EXTINT15 on PB31 mux A */ +#define MUX_PB31A_EIC_EXTINT15 _L_(0) +#define PINMUX_PB31A_EIC_EXTINT15 ((PIN_PB31A_EIC_EXTINT15 << 16) | MUX_PB31A_EIC_EXTINT15) +#define PORT_PB31A_EIC_EXTINT15 (_UL_(1) << 31) +#define PIN_PB31A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PB31 External Interrupt Line */ +#define PIN_PC15A_EIC_EXTINT15 _L_(79) /**< \brief EIC signal: EXTINT15 on PC15 mux A */ +#define MUX_PC15A_EIC_EXTINT15 _L_(0) +#define PINMUX_PC15A_EIC_EXTINT15 ((PIN_PC15A_EIC_EXTINT15 << 16) | MUX_PC15A_EIC_EXTINT15) +#define PORT_PC15A_EIC_EXTINT15 (_UL_(1) << 15) +#define PIN_PC15A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PC15 External Interrupt Line */ +#define PIN_PC31A_EIC_EXTINT15 _L_(95) /**< \brief EIC signal: EXTINT15 on PC31 mux A */ +#define MUX_PC31A_EIC_EXTINT15 _L_(0) +#define PINMUX_PC31A_EIC_EXTINT15 ((PIN_PC31A_EIC_EXTINT15 << 16) | MUX_PC31A_EIC_EXTINT15) +#define PORT_PC31A_EIC_EXTINT15 (_UL_(1) << 31) +#define PIN_PC31A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PC31 External Interrupt Line */ +#define PIN_PA08A_EIC_NMI _L_(8) /**< \brief EIC signal: NMI on PA08 mux A */ +#define MUX_PA08A_EIC_NMI _L_(0) +#define PINMUX_PA08A_EIC_NMI ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI) +#define PORT_PA08A_EIC_NMI (_UL_(1) << 8) +/* ========== PORT definition for SERCOM0 peripheral ========== */ +#define PIN_PA04D_SERCOM0_PAD0 _L_(4) /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */ +#define MUX_PA04D_SERCOM0_PAD0 _L_(3) +#define PINMUX_PA04D_SERCOM0_PAD0 ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0) +#define PORT_PA04D_SERCOM0_PAD0 (_UL_(1) << 4) +#define PIN_PC17D_SERCOM0_PAD0 _L_(81) /**< \brief SERCOM0 signal: PAD0 on PC17 mux D */ +#define MUX_PC17D_SERCOM0_PAD0 _L_(3) +#define PINMUX_PC17D_SERCOM0_PAD0 ((PIN_PC17D_SERCOM0_PAD0 << 16) | MUX_PC17D_SERCOM0_PAD0) +#define PORT_PC17D_SERCOM0_PAD0 (_UL_(1) << 17) +#define PIN_PA08C_SERCOM0_PAD0 _L_(8) /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */ +#define MUX_PA08C_SERCOM0_PAD0 _L_(2) +#define PINMUX_PA08C_SERCOM0_PAD0 ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0) +#define PORT_PA08C_SERCOM0_PAD0 (_UL_(1) << 8) +#define PIN_PB24C_SERCOM0_PAD0 _L_(56) /**< \brief SERCOM0 signal: PAD0 on PB24 mux C */ +#define MUX_PB24C_SERCOM0_PAD0 _L_(2) +#define PINMUX_PB24C_SERCOM0_PAD0 ((PIN_PB24C_SERCOM0_PAD0 << 16) | MUX_PB24C_SERCOM0_PAD0) +#define PORT_PB24C_SERCOM0_PAD0 (_UL_(1) << 24) +#define PIN_PA05D_SERCOM0_PAD1 _L_(5) /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */ +#define MUX_PA05D_SERCOM0_PAD1 _L_(3) +#define PINMUX_PA05D_SERCOM0_PAD1 ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1) +#define PORT_PA05D_SERCOM0_PAD1 (_UL_(1) << 5) +#define PIN_PC16D_SERCOM0_PAD1 _L_(80) /**< \brief SERCOM0 signal: PAD1 on PC16 mux D */ +#define MUX_PC16D_SERCOM0_PAD1 _L_(3) +#define PINMUX_PC16D_SERCOM0_PAD1 ((PIN_PC16D_SERCOM0_PAD1 << 16) | MUX_PC16D_SERCOM0_PAD1) +#define PORT_PC16D_SERCOM0_PAD1 (_UL_(1) << 16) +#define PIN_PA09C_SERCOM0_PAD1 _L_(9) /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */ +#define MUX_PA09C_SERCOM0_PAD1 _L_(2) +#define PINMUX_PA09C_SERCOM0_PAD1 ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1) +#define PORT_PA09C_SERCOM0_PAD1 (_UL_(1) << 9) +#define PIN_PB25C_SERCOM0_PAD1 _L_(57) /**< \brief SERCOM0 signal: PAD1 on PB25 mux C */ +#define MUX_PB25C_SERCOM0_PAD1 _L_(2) +#define PINMUX_PB25C_SERCOM0_PAD1 ((PIN_PB25C_SERCOM0_PAD1 << 16) | MUX_PB25C_SERCOM0_PAD1) +#define PORT_PB25C_SERCOM0_PAD1 (_UL_(1) << 25) +#define PIN_PA06D_SERCOM0_PAD2 _L_(6) /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */ +#define MUX_PA06D_SERCOM0_PAD2 _L_(3) +#define PINMUX_PA06D_SERCOM0_PAD2 ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2) +#define PORT_PA06D_SERCOM0_PAD2 (_UL_(1) << 6) +#define PIN_PC18D_SERCOM0_PAD2 _L_(82) /**< \brief SERCOM0 signal: PAD2 on PC18 mux D */ +#define MUX_PC18D_SERCOM0_PAD2 _L_(3) +#define PINMUX_PC18D_SERCOM0_PAD2 ((PIN_PC18D_SERCOM0_PAD2 << 16) | MUX_PC18D_SERCOM0_PAD2) +#define PORT_PC18D_SERCOM0_PAD2 (_UL_(1) << 18) +#define PIN_PA10C_SERCOM0_PAD2 _L_(10) /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */ +#define MUX_PA10C_SERCOM0_PAD2 _L_(2) +#define PINMUX_PA10C_SERCOM0_PAD2 ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2) +#define PORT_PA10C_SERCOM0_PAD2 (_UL_(1) << 10) +#define PIN_PC24C_SERCOM0_PAD2 _L_(88) /**< \brief SERCOM0 signal: PAD2 on PC24 mux C */ +#define MUX_PC24C_SERCOM0_PAD2 _L_(2) +#define PINMUX_PC24C_SERCOM0_PAD2 ((PIN_PC24C_SERCOM0_PAD2 << 16) | MUX_PC24C_SERCOM0_PAD2) +#define PORT_PC24C_SERCOM0_PAD2 (_UL_(1) << 24) +#define PIN_PA07D_SERCOM0_PAD3 _L_(7) /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */ +#define MUX_PA07D_SERCOM0_PAD3 _L_(3) +#define PINMUX_PA07D_SERCOM0_PAD3 ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3) +#define PORT_PA07D_SERCOM0_PAD3 (_UL_(1) << 7) +#define PIN_PC19D_SERCOM0_PAD3 _L_(83) /**< \brief SERCOM0 signal: PAD3 on PC19 mux D */ +#define MUX_PC19D_SERCOM0_PAD3 _L_(3) +#define PINMUX_PC19D_SERCOM0_PAD3 ((PIN_PC19D_SERCOM0_PAD3 << 16) | MUX_PC19D_SERCOM0_PAD3) +#define PORT_PC19D_SERCOM0_PAD3 (_UL_(1) << 19) +#define PIN_PA11C_SERCOM0_PAD3 _L_(11) /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */ +#define MUX_PA11C_SERCOM0_PAD3 _L_(2) +#define PINMUX_PA11C_SERCOM0_PAD3 ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3) +#define PORT_PA11C_SERCOM0_PAD3 (_UL_(1) << 11) +#define PIN_PC25C_SERCOM0_PAD3 _L_(89) /**< \brief SERCOM0 signal: PAD3 on PC25 mux C */ +#define MUX_PC25C_SERCOM0_PAD3 _L_(2) +#define PINMUX_PC25C_SERCOM0_PAD3 ((PIN_PC25C_SERCOM0_PAD3 << 16) | MUX_PC25C_SERCOM0_PAD3) +#define PORT_PC25C_SERCOM0_PAD3 (_UL_(1) << 25) +/* ========== PORT definition for SERCOM1 peripheral ========== */ +#define PIN_PA00D_SERCOM1_PAD0 _L_(0) /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */ +#define MUX_PA00D_SERCOM1_PAD0 _L_(3) +#define PINMUX_PA00D_SERCOM1_PAD0 ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0) +#define PORT_PA00D_SERCOM1_PAD0 (_UL_(1) << 0) +#define PIN_PA16C_SERCOM1_PAD0 _L_(16) /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */ +#define MUX_PA16C_SERCOM1_PAD0 _L_(2) +#define PINMUX_PA16C_SERCOM1_PAD0 ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0) +#define PORT_PA16C_SERCOM1_PAD0 (_UL_(1) << 16) +#define PIN_PC22C_SERCOM1_PAD0 _L_(86) /**< \brief SERCOM1 signal: PAD0 on PC22 mux C */ +#define MUX_PC22C_SERCOM1_PAD0 _L_(2) +#define PINMUX_PC22C_SERCOM1_PAD0 ((PIN_PC22C_SERCOM1_PAD0 << 16) | MUX_PC22C_SERCOM1_PAD0) +#define PORT_PC22C_SERCOM1_PAD0 (_UL_(1) << 22) +#define PIN_PC27C_SERCOM1_PAD0 _L_(91) /**< \brief SERCOM1 signal: PAD0 on PC27 mux C */ +#define MUX_PC27C_SERCOM1_PAD0 _L_(2) +#define PINMUX_PC27C_SERCOM1_PAD0 ((PIN_PC27C_SERCOM1_PAD0 << 16) | MUX_PC27C_SERCOM1_PAD0) +#define PORT_PC27C_SERCOM1_PAD0 (_UL_(1) << 27) +#define PIN_PA01D_SERCOM1_PAD1 _L_(1) /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */ +#define MUX_PA01D_SERCOM1_PAD1 _L_(3) +#define PINMUX_PA01D_SERCOM1_PAD1 ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1) +#define PORT_PA01D_SERCOM1_PAD1 (_UL_(1) << 1) +#define PIN_PA17C_SERCOM1_PAD1 _L_(17) /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */ +#define MUX_PA17C_SERCOM1_PAD1 _L_(2) +#define PINMUX_PA17C_SERCOM1_PAD1 ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1) +#define PORT_PA17C_SERCOM1_PAD1 (_UL_(1) << 17) +#define PIN_PC23C_SERCOM1_PAD1 _L_(87) /**< \brief SERCOM1 signal: PAD1 on PC23 mux C */ +#define MUX_PC23C_SERCOM1_PAD1 _L_(2) +#define PINMUX_PC23C_SERCOM1_PAD1 ((PIN_PC23C_SERCOM1_PAD1 << 16) | MUX_PC23C_SERCOM1_PAD1) +#define PORT_PC23C_SERCOM1_PAD1 (_UL_(1) << 23) +#define PIN_PC28C_SERCOM1_PAD1 _L_(92) /**< \brief SERCOM1 signal: PAD1 on PC28 mux C */ +#define MUX_PC28C_SERCOM1_PAD1 _L_(2) +#define PINMUX_PC28C_SERCOM1_PAD1 ((PIN_PC28C_SERCOM1_PAD1 << 16) | MUX_PC28C_SERCOM1_PAD1) +#define PORT_PC28C_SERCOM1_PAD1 (_UL_(1) << 28) +#define PIN_PA30D_SERCOM1_PAD2 _L_(30) /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */ +#define MUX_PA30D_SERCOM1_PAD2 _L_(3) +#define PINMUX_PA30D_SERCOM1_PAD2 ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2) +#define PORT_PA30D_SERCOM1_PAD2 (_UL_(1) << 30) +#define PIN_PA18C_SERCOM1_PAD2 _L_(18) /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */ +#define MUX_PA18C_SERCOM1_PAD2 _L_(2) +#define PINMUX_PA18C_SERCOM1_PAD2 ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2) +#define PORT_PA18C_SERCOM1_PAD2 (_UL_(1) << 18) +#define PIN_PB22C_SERCOM1_PAD2 _L_(54) /**< \brief SERCOM1 signal: PAD2 on PB22 mux C */ +#define MUX_PB22C_SERCOM1_PAD2 _L_(2) +#define PINMUX_PB22C_SERCOM1_PAD2 ((PIN_PB22C_SERCOM1_PAD2 << 16) | MUX_PB22C_SERCOM1_PAD2) +#define PORT_PB22C_SERCOM1_PAD2 (_UL_(1) << 22) +#define PIN_PD20C_SERCOM1_PAD2 _L_(116) /**< \brief SERCOM1 signal: PAD2 on PD20 mux C */ +#define MUX_PD20C_SERCOM1_PAD2 _L_(2) +#define PINMUX_PD20C_SERCOM1_PAD2 ((PIN_PD20C_SERCOM1_PAD2 << 16) | MUX_PD20C_SERCOM1_PAD2) +#define PORT_PD20C_SERCOM1_PAD2 (_UL_(1) << 20) +#define PIN_PA31D_SERCOM1_PAD3 _L_(31) /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */ +#define MUX_PA31D_SERCOM1_PAD3 _L_(3) +#define PINMUX_PA31D_SERCOM1_PAD3 ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3) +#define PORT_PA31D_SERCOM1_PAD3 (_UL_(1) << 31) +#define PIN_PA19C_SERCOM1_PAD3 _L_(19) /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */ +#define MUX_PA19C_SERCOM1_PAD3 _L_(2) +#define PINMUX_PA19C_SERCOM1_PAD3 ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3) +#define PORT_PA19C_SERCOM1_PAD3 (_UL_(1) << 19) +#define PIN_PB23C_SERCOM1_PAD3 _L_(55) /**< \brief SERCOM1 signal: PAD3 on PB23 mux C */ +#define MUX_PB23C_SERCOM1_PAD3 _L_(2) +#define PINMUX_PB23C_SERCOM1_PAD3 ((PIN_PB23C_SERCOM1_PAD3 << 16) | MUX_PB23C_SERCOM1_PAD3) +#define PORT_PB23C_SERCOM1_PAD3 (_UL_(1) << 23) +#define PIN_PD21C_SERCOM1_PAD3 _L_(117) /**< \brief SERCOM1 signal: PAD3 on PD21 mux C */ +#define MUX_PD21C_SERCOM1_PAD3 _L_(2) +#define PINMUX_PD21C_SERCOM1_PAD3 ((PIN_PD21C_SERCOM1_PAD3 << 16) | MUX_PD21C_SERCOM1_PAD3) +#define PORT_PD21C_SERCOM1_PAD3 (_UL_(1) << 21) +/* ========== PORT definition for TC0 peripheral ========== */ +#define PIN_PA04E_TC0_WO0 _L_(4) /**< \brief TC0 signal: WO0 on PA04 mux E */ +#define MUX_PA04E_TC0_WO0 _L_(4) +#define PINMUX_PA04E_TC0_WO0 ((PIN_PA04E_TC0_WO0 << 16) | MUX_PA04E_TC0_WO0) +#define PORT_PA04E_TC0_WO0 (_UL_(1) << 4) +#define PIN_PA08E_TC0_WO0 _L_(8) /**< \brief TC0 signal: WO0 on PA08 mux E */ +#define MUX_PA08E_TC0_WO0 _L_(4) +#define PINMUX_PA08E_TC0_WO0 ((PIN_PA08E_TC0_WO0 << 16) | MUX_PA08E_TC0_WO0) +#define PORT_PA08E_TC0_WO0 (_UL_(1) << 8) +#define PIN_PB30E_TC0_WO0 _L_(62) /**< \brief TC0 signal: WO0 on PB30 mux E */ +#define MUX_PB30E_TC0_WO0 _L_(4) +#define PINMUX_PB30E_TC0_WO0 ((PIN_PB30E_TC0_WO0 << 16) | MUX_PB30E_TC0_WO0) +#define PORT_PB30E_TC0_WO0 (_UL_(1) << 30) +#define PIN_PA05E_TC0_WO1 _L_(5) /**< \brief TC0 signal: WO1 on PA05 mux E */ +#define MUX_PA05E_TC0_WO1 _L_(4) +#define PINMUX_PA05E_TC0_WO1 ((PIN_PA05E_TC0_WO1 << 16) | MUX_PA05E_TC0_WO1) +#define PORT_PA05E_TC0_WO1 (_UL_(1) << 5) +#define PIN_PA09E_TC0_WO1 _L_(9) /**< \brief TC0 signal: WO1 on PA09 mux E */ +#define MUX_PA09E_TC0_WO1 _L_(4) +#define PINMUX_PA09E_TC0_WO1 ((PIN_PA09E_TC0_WO1 << 16) | MUX_PA09E_TC0_WO1) +#define PORT_PA09E_TC0_WO1 (_UL_(1) << 9) +#define PIN_PB31E_TC0_WO1 _L_(63) /**< \brief TC0 signal: WO1 on PB31 mux E */ +#define MUX_PB31E_TC0_WO1 _L_(4) +#define PINMUX_PB31E_TC0_WO1 ((PIN_PB31E_TC0_WO1 << 16) | MUX_PB31E_TC0_WO1) +#define PORT_PB31E_TC0_WO1 (_UL_(1) << 31) +/* ========== PORT definition for TC1 peripheral ========== */ +#define PIN_PA06E_TC1_WO0 _L_(6) /**< \brief TC1 signal: WO0 on PA06 mux E */ +#define MUX_PA06E_TC1_WO0 _L_(4) +#define PINMUX_PA06E_TC1_WO0 ((PIN_PA06E_TC1_WO0 << 16) | MUX_PA06E_TC1_WO0) +#define PORT_PA06E_TC1_WO0 (_UL_(1) << 6) +#define PIN_PA10E_TC1_WO0 _L_(10) /**< \brief TC1 signal: WO0 on PA10 mux E */ +#define MUX_PA10E_TC1_WO0 _L_(4) +#define PINMUX_PA10E_TC1_WO0 ((PIN_PA10E_TC1_WO0 << 16) | MUX_PA10E_TC1_WO0) +#define PORT_PA10E_TC1_WO0 (_UL_(1) << 10) +#define PIN_PA07E_TC1_WO1 _L_(7) /**< \brief TC1 signal: WO1 on PA07 mux E */ +#define MUX_PA07E_TC1_WO1 _L_(4) +#define PINMUX_PA07E_TC1_WO1 ((PIN_PA07E_TC1_WO1 << 16) | MUX_PA07E_TC1_WO1) +#define PORT_PA07E_TC1_WO1 (_UL_(1) << 7) +#define PIN_PA11E_TC1_WO1 _L_(11) /**< \brief TC1 signal: WO1 on PA11 mux E */ +#define MUX_PA11E_TC1_WO1 _L_(4) +#define PINMUX_PA11E_TC1_WO1 ((PIN_PA11E_TC1_WO1 << 16) | MUX_PA11E_TC1_WO1) +#define PORT_PA11E_TC1_WO1 (_UL_(1) << 11) +/* ========== PORT definition for USB peripheral ========== */ +#define PIN_PA24H_USB_DM _L_(24) /**< \brief USB signal: DM on PA24 mux H */ +#define MUX_PA24H_USB_DM _L_(7) +#define PINMUX_PA24H_USB_DM ((PIN_PA24H_USB_DM << 16) | MUX_PA24H_USB_DM) +#define PORT_PA24H_USB_DM (_UL_(1) << 24) +#define PIN_PA25H_USB_DP _L_(25) /**< \brief USB signal: DP on PA25 mux H */ +#define MUX_PA25H_USB_DP _L_(7) +#define PINMUX_PA25H_USB_DP ((PIN_PA25H_USB_DP << 16) | MUX_PA25H_USB_DP) +#define PORT_PA25H_USB_DP (_UL_(1) << 25) +#define PIN_PA23H_USB_SOF_1KHZ _L_(23) /**< \brief USB signal: SOF_1KHZ on PA23 mux H */ +#define MUX_PA23H_USB_SOF_1KHZ _L_(7) +#define PINMUX_PA23H_USB_SOF_1KHZ ((PIN_PA23H_USB_SOF_1KHZ << 16) | MUX_PA23H_USB_SOF_1KHZ) +#define PORT_PA23H_USB_SOF_1KHZ (_UL_(1) << 23) +#define PIN_PB22H_USB_SOF_1KHZ _L_(54) /**< \brief USB signal: SOF_1KHZ on PB22 mux H */ +#define MUX_PB22H_USB_SOF_1KHZ _L_(7) +#define PINMUX_PB22H_USB_SOF_1KHZ ((PIN_PB22H_USB_SOF_1KHZ << 16) | MUX_PB22H_USB_SOF_1KHZ) +#define PORT_PB22H_USB_SOF_1KHZ (_UL_(1) << 22) +/* ========== PORT definition for SERCOM2 peripheral ========== */ +#define PIN_PA09D_SERCOM2_PAD0 _L_(9) /**< \brief SERCOM2 signal: PAD0 on PA09 mux D */ +#define MUX_PA09D_SERCOM2_PAD0 _L_(3) +#define PINMUX_PA09D_SERCOM2_PAD0 ((PIN_PA09D_SERCOM2_PAD0 << 16) | MUX_PA09D_SERCOM2_PAD0) +#define PORT_PA09D_SERCOM2_PAD0 (_UL_(1) << 9) +#define PIN_PB25D_SERCOM2_PAD0 _L_(57) /**< \brief SERCOM2 signal: PAD0 on PB25 mux D */ +#define MUX_PB25D_SERCOM2_PAD0 _L_(3) +#define PINMUX_PB25D_SERCOM2_PAD0 ((PIN_PB25D_SERCOM2_PAD0 << 16) | MUX_PB25D_SERCOM2_PAD0) +#define PORT_PB25D_SERCOM2_PAD0 (_UL_(1) << 25) +#define PIN_PA12C_SERCOM2_PAD0 _L_(12) /**< \brief SERCOM2 signal: PAD0 on PA12 mux C */ +#define MUX_PA12C_SERCOM2_PAD0 _L_(2) +#define PINMUX_PA12C_SERCOM2_PAD0 ((PIN_PA12C_SERCOM2_PAD0 << 16) | MUX_PA12C_SERCOM2_PAD0) +#define PORT_PA12C_SERCOM2_PAD0 (_UL_(1) << 12) +#define PIN_PB26C_SERCOM2_PAD0 _L_(58) /**< \brief SERCOM2 signal: PAD0 on PB26 mux C */ +#define MUX_PB26C_SERCOM2_PAD0 _L_(2) +#define PINMUX_PB26C_SERCOM2_PAD0 ((PIN_PB26C_SERCOM2_PAD0 << 16) | MUX_PB26C_SERCOM2_PAD0) +#define PORT_PB26C_SERCOM2_PAD0 (_UL_(1) << 26) +#define PIN_PA08D_SERCOM2_PAD1 _L_(8) /**< \brief SERCOM2 signal: PAD1 on PA08 mux D */ +#define MUX_PA08D_SERCOM2_PAD1 _L_(3) +#define PINMUX_PA08D_SERCOM2_PAD1 ((PIN_PA08D_SERCOM2_PAD1 << 16) | MUX_PA08D_SERCOM2_PAD1) +#define PORT_PA08D_SERCOM2_PAD1 (_UL_(1) << 8) +#define PIN_PB24D_SERCOM2_PAD1 _L_(56) /**< \brief SERCOM2 signal: PAD1 on PB24 mux D */ +#define MUX_PB24D_SERCOM2_PAD1 _L_(3) +#define PINMUX_PB24D_SERCOM2_PAD1 ((PIN_PB24D_SERCOM2_PAD1 << 16) | MUX_PB24D_SERCOM2_PAD1) +#define PORT_PB24D_SERCOM2_PAD1 (_UL_(1) << 24) +#define PIN_PA13C_SERCOM2_PAD1 _L_(13) /**< \brief SERCOM2 signal: PAD1 on PA13 mux C */ +#define MUX_PA13C_SERCOM2_PAD1 _L_(2) +#define PINMUX_PA13C_SERCOM2_PAD1 ((PIN_PA13C_SERCOM2_PAD1 << 16) | MUX_PA13C_SERCOM2_PAD1) +#define PORT_PA13C_SERCOM2_PAD1 (_UL_(1) << 13) +#define PIN_PB27C_SERCOM2_PAD1 _L_(59) /**< \brief SERCOM2 signal: PAD1 on PB27 mux C */ +#define MUX_PB27C_SERCOM2_PAD1 _L_(2) +#define PINMUX_PB27C_SERCOM2_PAD1 ((PIN_PB27C_SERCOM2_PAD1 << 16) | MUX_PB27C_SERCOM2_PAD1) +#define PORT_PB27C_SERCOM2_PAD1 (_UL_(1) << 27) +#define PIN_PA10D_SERCOM2_PAD2 _L_(10) /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */ +#define MUX_PA10D_SERCOM2_PAD2 _L_(3) +#define PINMUX_PA10D_SERCOM2_PAD2 ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2) +#define PORT_PA10D_SERCOM2_PAD2 (_UL_(1) << 10) +#define PIN_PC24D_SERCOM2_PAD2 _L_(88) /**< \brief SERCOM2 signal: PAD2 on PC24 mux D */ +#define MUX_PC24D_SERCOM2_PAD2 _L_(3) +#define PINMUX_PC24D_SERCOM2_PAD2 ((PIN_PC24D_SERCOM2_PAD2 << 16) | MUX_PC24D_SERCOM2_PAD2) +#define PORT_PC24D_SERCOM2_PAD2 (_UL_(1) << 24) +#define PIN_PB28C_SERCOM2_PAD2 _L_(60) /**< \brief SERCOM2 signal: PAD2 on PB28 mux C */ +#define MUX_PB28C_SERCOM2_PAD2 _L_(2) +#define PINMUX_PB28C_SERCOM2_PAD2 ((PIN_PB28C_SERCOM2_PAD2 << 16) | MUX_PB28C_SERCOM2_PAD2) +#define PORT_PB28C_SERCOM2_PAD2 (_UL_(1) << 28) +#define PIN_PA14C_SERCOM2_PAD2 _L_(14) /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */ +#define MUX_PA14C_SERCOM2_PAD2 _L_(2) +#define PINMUX_PA14C_SERCOM2_PAD2 ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2) +#define PORT_PA14C_SERCOM2_PAD2 (_UL_(1) << 14) +#define PIN_PA11D_SERCOM2_PAD3 _L_(11) /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */ +#define MUX_PA11D_SERCOM2_PAD3 _L_(3) +#define PINMUX_PA11D_SERCOM2_PAD3 ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3) +#define PORT_PA11D_SERCOM2_PAD3 (_UL_(1) << 11) +#define PIN_PC25D_SERCOM2_PAD3 _L_(89) /**< \brief SERCOM2 signal: PAD3 on PC25 mux D */ +#define MUX_PC25D_SERCOM2_PAD3 _L_(3) +#define PINMUX_PC25D_SERCOM2_PAD3 ((PIN_PC25D_SERCOM2_PAD3 << 16) | MUX_PC25D_SERCOM2_PAD3) +#define PORT_PC25D_SERCOM2_PAD3 (_UL_(1) << 25) +#define PIN_PB29C_SERCOM2_PAD3 _L_(61) /**< \brief SERCOM2 signal: PAD3 on PB29 mux C */ +#define MUX_PB29C_SERCOM2_PAD3 _L_(2) +#define PINMUX_PB29C_SERCOM2_PAD3 ((PIN_PB29C_SERCOM2_PAD3 << 16) | MUX_PB29C_SERCOM2_PAD3) +#define PORT_PB29C_SERCOM2_PAD3 (_UL_(1) << 29) +#define PIN_PA15C_SERCOM2_PAD3 _L_(15) /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */ +#define MUX_PA15C_SERCOM2_PAD3 _L_(2) +#define PINMUX_PA15C_SERCOM2_PAD3 ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3) +#define PORT_PA15C_SERCOM2_PAD3 (_UL_(1) << 15) +/* ========== PORT definition for SERCOM3 peripheral ========== */ +#define PIN_PA17D_SERCOM3_PAD0 _L_(17) /**< \brief SERCOM3 signal: PAD0 on PA17 mux D */ +#define MUX_PA17D_SERCOM3_PAD0 _L_(3) +#define PINMUX_PA17D_SERCOM3_PAD0 ((PIN_PA17D_SERCOM3_PAD0 << 16) | MUX_PA17D_SERCOM3_PAD0) +#define PORT_PA17D_SERCOM3_PAD0 (_UL_(1) << 17) +#define PIN_PC23D_SERCOM3_PAD0 _L_(87) /**< \brief SERCOM3 signal: PAD0 on PC23 mux D */ +#define MUX_PC23D_SERCOM3_PAD0 _L_(3) +#define PINMUX_PC23D_SERCOM3_PAD0 ((PIN_PC23D_SERCOM3_PAD0 << 16) | MUX_PC23D_SERCOM3_PAD0) +#define PORT_PC23D_SERCOM3_PAD0 (_UL_(1) << 23) +#define PIN_PA22C_SERCOM3_PAD0 _L_(22) /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */ +#define MUX_PA22C_SERCOM3_PAD0 _L_(2) +#define PINMUX_PA22C_SERCOM3_PAD0 ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0) +#define PORT_PA22C_SERCOM3_PAD0 (_UL_(1) << 22) +#define PIN_PB20C_SERCOM3_PAD0 _L_(52) /**< \brief SERCOM3 signal: PAD0 on PB20 mux C */ +#define MUX_PB20C_SERCOM3_PAD0 _L_(2) +#define PINMUX_PB20C_SERCOM3_PAD0 ((PIN_PB20C_SERCOM3_PAD0 << 16) | MUX_PB20C_SERCOM3_PAD0) +#define PORT_PB20C_SERCOM3_PAD0 (_UL_(1) << 20) +#define PIN_PA16D_SERCOM3_PAD1 _L_(16) /**< \brief SERCOM3 signal: PAD1 on PA16 mux D */ +#define MUX_PA16D_SERCOM3_PAD1 _L_(3) +#define PINMUX_PA16D_SERCOM3_PAD1 ((PIN_PA16D_SERCOM3_PAD1 << 16) | MUX_PA16D_SERCOM3_PAD1) +#define PORT_PA16D_SERCOM3_PAD1 (_UL_(1) << 16) +#define PIN_PC22D_SERCOM3_PAD1 _L_(86) /**< \brief SERCOM3 signal: PAD1 on PC22 mux D */ +#define MUX_PC22D_SERCOM3_PAD1 _L_(3) +#define PINMUX_PC22D_SERCOM3_PAD1 ((PIN_PC22D_SERCOM3_PAD1 << 16) | MUX_PC22D_SERCOM3_PAD1) +#define PORT_PC22D_SERCOM3_PAD1 (_UL_(1) << 22) +#define PIN_PA23C_SERCOM3_PAD1 _L_(23) /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */ +#define MUX_PA23C_SERCOM3_PAD1 _L_(2) +#define PINMUX_PA23C_SERCOM3_PAD1 ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1) +#define PORT_PA23C_SERCOM3_PAD1 (_UL_(1) << 23) +#define PIN_PB21C_SERCOM3_PAD1 _L_(53) /**< \brief SERCOM3 signal: PAD1 on PB21 mux C */ +#define MUX_PB21C_SERCOM3_PAD1 _L_(2) +#define PINMUX_PB21C_SERCOM3_PAD1 ((PIN_PB21C_SERCOM3_PAD1 << 16) | MUX_PB21C_SERCOM3_PAD1) +#define PORT_PB21C_SERCOM3_PAD1 (_UL_(1) << 21) +#define PIN_PA18D_SERCOM3_PAD2 _L_(18) /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */ +#define MUX_PA18D_SERCOM3_PAD2 _L_(3) +#define PINMUX_PA18D_SERCOM3_PAD2 ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2) +#define PORT_PA18D_SERCOM3_PAD2 (_UL_(1) << 18) +#define PIN_PA20D_SERCOM3_PAD2 _L_(20) /**< \brief SERCOM3 signal: PAD2 on PA20 mux D */ +#define MUX_PA20D_SERCOM3_PAD2 _L_(3) +#define PINMUX_PA20D_SERCOM3_PAD2 ((PIN_PA20D_SERCOM3_PAD2 << 16) | MUX_PA20D_SERCOM3_PAD2) +#define PORT_PA20D_SERCOM3_PAD2 (_UL_(1) << 20) +#define PIN_PD20D_SERCOM3_PAD2 _L_(116) /**< \brief SERCOM3 signal: PAD2 on PD20 mux D */ +#define MUX_PD20D_SERCOM3_PAD2 _L_(3) +#define PINMUX_PD20D_SERCOM3_PAD2 ((PIN_PD20D_SERCOM3_PAD2 << 16) | MUX_PD20D_SERCOM3_PAD2) +#define PORT_PD20D_SERCOM3_PAD2 (_UL_(1) << 20) +#define PIN_PA24C_SERCOM3_PAD2 _L_(24) /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */ +#define MUX_PA24C_SERCOM3_PAD2 _L_(2) +#define PINMUX_PA24C_SERCOM3_PAD2 ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2) +#define PORT_PA24C_SERCOM3_PAD2 (_UL_(1) << 24) +#define PIN_PA19D_SERCOM3_PAD3 _L_(19) /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */ +#define MUX_PA19D_SERCOM3_PAD3 _L_(3) +#define PINMUX_PA19D_SERCOM3_PAD3 ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3) +#define PORT_PA19D_SERCOM3_PAD3 (_UL_(1) << 19) +#define PIN_PA21D_SERCOM3_PAD3 _L_(21) /**< \brief SERCOM3 signal: PAD3 on PA21 mux D */ +#define MUX_PA21D_SERCOM3_PAD3 _L_(3) +#define PINMUX_PA21D_SERCOM3_PAD3 ((PIN_PA21D_SERCOM3_PAD3 << 16) | MUX_PA21D_SERCOM3_PAD3) +#define PORT_PA21D_SERCOM3_PAD3 (_UL_(1) << 21) +#define PIN_PD21D_SERCOM3_PAD3 _L_(117) /**< \brief SERCOM3 signal: PAD3 on PD21 mux D */ +#define MUX_PD21D_SERCOM3_PAD3 _L_(3) +#define PINMUX_PD21D_SERCOM3_PAD3 ((PIN_PD21D_SERCOM3_PAD3 << 16) | MUX_PD21D_SERCOM3_PAD3) +#define PORT_PD21D_SERCOM3_PAD3 (_UL_(1) << 21) +#define PIN_PA25C_SERCOM3_PAD3 _L_(25) /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */ +#define MUX_PA25C_SERCOM3_PAD3 _L_(2) +#define PINMUX_PA25C_SERCOM3_PAD3 ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3) +#define PORT_PA25C_SERCOM3_PAD3 (_UL_(1) << 25) +/* ========== PORT definition for TCC0 peripheral ========== */ +#define PIN_PA20G_TCC0_WO0 _L_(20) /**< \brief TCC0 signal: WO0 on PA20 mux G */ +#define MUX_PA20G_TCC0_WO0 _L_(6) +#define PINMUX_PA20G_TCC0_WO0 ((PIN_PA20G_TCC0_WO0 << 16) | MUX_PA20G_TCC0_WO0) +#define PORT_PA20G_TCC0_WO0 (_UL_(1) << 20) +#define PIN_PB12G_TCC0_WO0 _L_(44) /**< \brief TCC0 signal: WO0 on PB12 mux G */ +#define MUX_PB12G_TCC0_WO0 _L_(6) +#define PINMUX_PB12G_TCC0_WO0 ((PIN_PB12G_TCC0_WO0 << 16) | MUX_PB12G_TCC0_WO0) +#define PORT_PB12G_TCC0_WO0 (_UL_(1) << 12) +#define PIN_PA08F_TCC0_WO0 _L_(8) /**< \brief TCC0 signal: WO0 on PA08 mux F */ +#define MUX_PA08F_TCC0_WO0 _L_(5) +#define PINMUX_PA08F_TCC0_WO0 ((PIN_PA08F_TCC0_WO0 << 16) | MUX_PA08F_TCC0_WO0) +#define PORT_PA08F_TCC0_WO0 (_UL_(1) << 8) +#define PIN_PC04F_TCC0_WO0 _L_(68) /**< \brief TCC0 signal: WO0 on PC04 mux F */ +#define MUX_PC04F_TCC0_WO0 _L_(5) +#define PINMUX_PC04F_TCC0_WO0 ((PIN_PC04F_TCC0_WO0 << 16) | MUX_PC04F_TCC0_WO0) +#define PORT_PC04F_TCC0_WO0 (_UL_(1) << 4) +#define PIN_PC10F_TCC0_WO0 _L_(74) /**< \brief TCC0 signal: WO0 on PC10 mux F */ +#define MUX_PC10F_TCC0_WO0 _L_(5) +#define PINMUX_PC10F_TCC0_WO0 ((PIN_PC10F_TCC0_WO0 << 16) | MUX_PC10F_TCC0_WO0) +#define PORT_PC10F_TCC0_WO0 (_UL_(1) << 10) +#define PIN_PC16F_TCC0_WO0 _L_(80) /**< \brief TCC0 signal: WO0 on PC16 mux F */ +#define MUX_PC16F_TCC0_WO0 _L_(5) +#define PINMUX_PC16F_TCC0_WO0 ((PIN_PC16F_TCC0_WO0 << 16) | MUX_PC16F_TCC0_WO0) +#define PORT_PC16F_TCC0_WO0 (_UL_(1) << 16) +#define PIN_PA21G_TCC0_WO1 _L_(21) /**< \brief TCC0 signal: WO1 on PA21 mux G */ +#define MUX_PA21G_TCC0_WO1 _L_(6) +#define PINMUX_PA21G_TCC0_WO1 ((PIN_PA21G_TCC0_WO1 << 16) | MUX_PA21G_TCC0_WO1) +#define PORT_PA21G_TCC0_WO1 (_UL_(1) << 21) +#define PIN_PB13G_TCC0_WO1 _L_(45) /**< \brief TCC0 signal: WO1 on PB13 mux G */ +#define MUX_PB13G_TCC0_WO1 _L_(6) +#define PINMUX_PB13G_TCC0_WO1 ((PIN_PB13G_TCC0_WO1 << 16) | MUX_PB13G_TCC0_WO1) +#define PORT_PB13G_TCC0_WO1 (_UL_(1) << 13) +#define PIN_PA09F_TCC0_WO1 _L_(9) /**< \brief TCC0 signal: WO1 on PA09 mux F */ +#define MUX_PA09F_TCC0_WO1 _L_(5) +#define PINMUX_PA09F_TCC0_WO1 ((PIN_PA09F_TCC0_WO1 << 16) | MUX_PA09F_TCC0_WO1) +#define PORT_PA09F_TCC0_WO1 (_UL_(1) << 9) +#define PIN_PC11F_TCC0_WO1 _L_(75) /**< \brief TCC0 signal: WO1 on PC11 mux F */ +#define MUX_PC11F_TCC0_WO1 _L_(5) +#define PINMUX_PC11F_TCC0_WO1 ((PIN_PC11F_TCC0_WO1 << 16) | MUX_PC11F_TCC0_WO1) +#define PORT_PC11F_TCC0_WO1 (_UL_(1) << 11) +#define PIN_PC17F_TCC0_WO1 _L_(81) /**< \brief TCC0 signal: WO1 on PC17 mux F */ +#define MUX_PC17F_TCC0_WO1 _L_(5) +#define PINMUX_PC17F_TCC0_WO1 ((PIN_PC17F_TCC0_WO1 << 16) | MUX_PC17F_TCC0_WO1) +#define PORT_PC17F_TCC0_WO1 (_UL_(1) << 17) +#define PIN_PD08F_TCC0_WO1 _L_(104) /**< \brief TCC0 signal: WO1 on PD08 mux F */ +#define MUX_PD08F_TCC0_WO1 _L_(5) +#define PINMUX_PD08F_TCC0_WO1 ((PIN_PD08F_TCC0_WO1 << 16) | MUX_PD08F_TCC0_WO1) +#define PORT_PD08F_TCC0_WO1 (_UL_(1) << 8) +#define PIN_PA22G_TCC0_WO2 _L_(22) /**< \brief TCC0 signal: WO2 on PA22 mux G */ +#define MUX_PA22G_TCC0_WO2 _L_(6) +#define PINMUX_PA22G_TCC0_WO2 ((PIN_PA22G_TCC0_WO2 << 16) | MUX_PA22G_TCC0_WO2) +#define PORT_PA22G_TCC0_WO2 (_UL_(1) << 22) +#define PIN_PB14G_TCC0_WO2 _L_(46) /**< \brief TCC0 signal: WO2 on PB14 mux G */ +#define MUX_PB14G_TCC0_WO2 _L_(6) +#define PINMUX_PB14G_TCC0_WO2 ((PIN_PB14G_TCC0_WO2 << 16) | MUX_PB14G_TCC0_WO2) +#define PORT_PB14G_TCC0_WO2 (_UL_(1) << 14) +#define PIN_PA10F_TCC0_WO2 _L_(10) /**< \brief TCC0 signal: WO2 on PA10 mux F */ +#define MUX_PA10F_TCC0_WO2 _L_(5) +#define PINMUX_PA10F_TCC0_WO2 ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2) +#define PORT_PA10F_TCC0_WO2 (_UL_(1) << 10) +#define PIN_PC12F_TCC0_WO2 _L_(76) /**< \brief TCC0 signal: WO2 on PC12 mux F */ +#define MUX_PC12F_TCC0_WO2 _L_(5) +#define PINMUX_PC12F_TCC0_WO2 ((PIN_PC12F_TCC0_WO2 << 16) | MUX_PC12F_TCC0_WO2) +#define PORT_PC12F_TCC0_WO2 (_UL_(1) << 12) +#define PIN_PC18F_TCC0_WO2 _L_(82) /**< \brief TCC0 signal: WO2 on PC18 mux F */ +#define MUX_PC18F_TCC0_WO2 _L_(5) +#define PINMUX_PC18F_TCC0_WO2 ((PIN_PC18F_TCC0_WO2 << 16) | MUX_PC18F_TCC0_WO2) +#define PORT_PC18F_TCC0_WO2 (_UL_(1) << 18) +#define PIN_PD09F_TCC0_WO2 _L_(105) /**< \brief TCC0 signal: WO2 on PD09 mux F */ +#define MUX_PD09F_TCC0_WO2 _L_(5) +#define PINMUX_PD09F_TCC0_WO2 ((PIN_PD09F_TCC0_WO2 << 16) | MUX_PD09F_TCC0_WO2) +#define PORT_PD09F_TCC0_WO2 (_UL_(1) << 9) +#define PIN_PA23G_TCC0_WO3 _L_(23) /**< \brief TCC0 signal: WO3 on PA23 mux G */ +#define MUX_PA23G_TCC0_WO3 _L_(6) +#define PINMUX_PA23G_TCC0_WO3 ((PIN_PA23G_TCC0_WO3 << 16) | MUX_PA23G_TCC0_WO3) +#define PORT_PA23G_TCC0_WO3 (_UL_(1) << 23) +#define PIN_PB15G_TCC0_WO3 _L_(47) /**< \brief TCC0 signal: WO3 on PB15 mux G */ +#define MUX_PB15G_TCC0_WO3 _L_(6) +#define PINMUX_PB15G_TCC0_WO3 ((PIN_PB15G_TCC0_WO3 << 16) | MUX_PB15G_TCC0_WO3) +#define PORT_PB15G_TCC0_WO3 (_UL_(1) << 15) +#define PIN_PA11F_TCC0_WO3 _L_(11) /**< \brief TCC0 signal: WO3 on PA11 mux F */ +#define MUX_PA11F_TCC0_WO3 _L_(5) +#define PINMUX_PA11F_TCC0_WO3 ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3) +#define PORT_PA11F_TCC0_WO3 (_UL_(1) << 11) +#define PIN_PC13F_TCC0_WO3 _L_(77) /**< \brief TCC0 signal: WO3 on PC13 mux F */ +#define MUX_PC13F_TCC0_WO3 _L_(5) +#define PINMUX_PC13F_TCC0_WO3 ((PIN_PC13F_TCC0_WO3 << 16) | MUX_PC13F_TCC0_WO3) +#define PORT_PC13F_TCC0_WO3 (_UL_(1) << 13) +#define PIN_PC19F_TCC0_WO3 _L_(83) /**< \brief TCC0 signal: WO3 on PC19 mux F */ +#define MUX_PC19F_TCC0_WO3 _L_(5) +#define PINMUX_PC19F_TCC0_WO3 ((PIN_PC19F_TCC0_WO3 << 16) | MUX_PC19F_TCC0_WO3) +#define PORT_PC19F_TCC0_WO3 (_UL_(1) << 19) +#define PIN_PD10F_TCC0_WO3 _L_(106) /**< \brief TCC0 signal: WO3 on PD10 mux F */ +#define MUX_PD10F_TCC0_WO3 _L_(5) +#define PINMUX_PD10F_TCC0_WO3 ((PIN_PD10F_TCC0_WO3 << 16) | MUX_PD10F_TCC0_WO3) +#define PORT_PD10F_TCC0_WO3 (_UL_(1) << 10) +#define PIN_PA16G_TCC0_WO4 _L_(16) /**< \brief TCC0 signal: WO4 on PA16 mux G */ +#define MUX_PA16G_TCC0_WO4 _L_(6) +#define PINMUX_PA16G_TCC0_WO4 ((PIN_PA16G_TCC0_WO4 << 16) | MUX_PA16G_TCC0_WO4) +#define PORT_PA16G_TCC0_WO4 (_UL_(1) << 16) +#define PIN_PB16G_TCC0_WO4 _L_(48) /**< \brief TCC0 signal: WO4 on PB16 mux G */ +#define MUX_PB16G_TCC0_WO4 _L_(6) +#define PINMUX_PB16G_TCC0_WO4 ((PIN_PB16G_TCC0_WO4 << 16) | MUX_PB16G_TCC0_WO4) +#define PORT_PB16G_TCC0_WO4 (_UL_(1) << 16) +#define PIN_PB10F_TCC0_WO4 _L_(42) /**< \brief TCC0 signal: WO4 on PB10 mux F */ +#define MUX_PB10F_TCC0_WO4 _L_(5) +#define PINMUX_PB10F_TCC0_WO4 ((PIN_PB10F_TCC0_WO4 << 16) | MUX_PB10F_TCC0_WO4) +#define PORT_PB10F_TCC0_WO4 (_UL_(1) << 10) +#define PIN_PC14F_TCC0_WO4 _L_(78) /**< \brief TCC0 signal: WO4 on PC14 mux F */ +#define MUX_PC14F_TCC0_WO4 _L_(5) +#define PINMUX_PC14F_TCC0_WO4 ((PIN_PC14F_TCC0_WO4 << 16) | MUX_PC14F_TCC0_WO4) +#define PORT_PC14F_TCC0_WO4 (_UL_(1) << 14) +#define PIN_PC20F_TCC0_WO4 _L_(84) /**< \brief TCC0 signal: WO4 on PC20 mux F */ +#define MUX_PC20F_TCC0_WO4 _L_(5) +#define PINMUX_PC20F_TCC0_WO4 ((PIN_PC20F_TCC0_WO4 << 16) | MUX_PC20F_TCC0_WO4) +#define PORT_PC20F_TCC0_WO4 (_UL_(1) << 20) +#define PIN_PD11F_TCC0_WO4 _L_(107) /**< \brief TCC0 signal: WO4 on PD11 mux F */ +#define MUX_PD11F_TCC0_WO4 _L_(5) +#define PINMUX_PD11F_TCC0_WO4 ((PIN_PD11F_TCC0_WO4 << 16) | MUX_PD11F_TCC0_WO4) +#define PORT_PD11F_TCC0_WO4 (_UL_(1) << 11) +#define PIN_PA17G_TCC0_WO5 _L_(17) /**< \brief TCC0 signal: WO5 on PA17 mux G */ +#define MUX_PA17G_TCC0_WO5 _L_(6) +#define PINMUX_PA17G_TCC0_WO5 ((PIN_PA17G_TCC0_WO5 << 16) | MUX_PA17G_TCC0_WO5) +#define PORT_PA17G_TCC0_WO5 (_UL_(1) << 17) +#define PIN_PB17G_TCC0_WO5 _L_(49) /**< \brief TCC0 signal: WO5 on PB17 mux G */ +#define MUX_PB17G_TCC0_WO5 _L_(6) +#define PINMUX_PB17G_TCC0_WO5 ((PIN_PB17G_TCC0_WO5 << 16) | MUX_PB17G_TCC0_WO5) +#define PORT_PB17G_TCC0_WO5 (_UL_(1) << 17) +#define PIN_PB11F_TCC0_WO5 _L_(43) /**< \brief TCC0 signal: WO5 on PB11 mux F */ +#define MUX_PB11F_TCC0_WO5 _L_(5) +#define PINMUX_PB11F_TCC0_WO5 ((PIN_PB11F_TCC0_WO5 << 16) | MUX_PB11F_TCC0_WO5) +#define PORT_PB11F_TCC0_WO5 (_UL_(1) << 11) +#define PIN_PC15F_TCC0_WO5 _L_(79) /**< \brief TCC0 signal: WO5 on PC15 mux F */ +#define MUX_PC15F_TCC0_WO5 _L_(5) +#define PINMUX_PC15F_TCC0_WO5 ((PIN_PC15F_TCC0_WO5 << 16) | MUX_PC15F_TCC0_WO5) +#define PORT_PC15F_TCC0_WO5 (_UL_(1) << 15) +#define PIN_PC21F_TCC0_WO5 _L_(85) /**< \brief TCC0 signal: WO5 on PC21 mux F */ +#define MUX_PC21F_TCC0_WO5 _L_(5) +#define PINMUX_PC21F_TCC0_WO5 ((PIN_PC21F_TCC0_WO5 << 16) | MUX_PC21F_TCC0_WO5) +#define PORT_PC21F_TCC0_WO5 (_UL_(1) << 21) +#define PIN_PD12F_TCC0_WO5 _L_(108) /**< \brief TCC0 signal: WO5 on PD12 mux F */ +#define MUX_PD12F_TCC0_WO5 _L_(5) +#define PINMUX_PD12F_TCC0_WO5 ((PIN_PD12F_TCC0_WO5 << 16) | MUX_PD12F_TCC0_WO5) +#define PORT_PD12F_TCC0_WO5 (_UL_(1) << 12) +#define PIN_PA18G_TCC0_WO6 _L_(18) /**< \brief TCC0 signal: WO6 on PA18 mux G */ +#define MUX_PA18G_TCC0_WO6 _L_(6) +#define PINMUX_PA18G_TCC0_WO6 ((PIN_PA18G_TCC0_WO6 << 16) | MUX_PA18G_TCC0_WO6) +#define PORT_PA18G_TCC0_WO6 (_UL_(1) << 18) +#define PIN_PB30G_TCC0_WO6 _L_(62) /**< \brief TCC0 signal: WO6 on PB30 mux G */ +#define MUX_PB30G_TCC0_WO6 _L_(6) +#define PINMUX_PB30G_TCC0_WO6 ((PIN_PB30G_TCC0_WO6 << 16) | MUX_PB30G_TCC0_WO6) +#define PORT_PB30G_TCC0_WO6 (_UL_(1) << 30) +#define PIN_PA12F_TCC0_WO6 _L_(12) /**< \brief TCC0 signal: WO6 on PA12 mux F */ +#define MUX_PA12F_TCC0_WO6 _L_(5) +#define PINMUX_PA12F_TCC0_WO6 ((PIN_PA12F_TCC0_WO6 << 16) | MUX_PA12F_TCC0_WO6) +#define PORT_PA12F_TCC0_WO6 (_UL_(1) << 12) +#define PIN_PC22F_TCC0_WO6 _L_(86) /**< \brief TCC0 signal: WO6 on PC22 mux F */ +#define MUX_PC22F_TCC0_WO6 _L_(5) +#define PINMUX_PC22F_TCC0_WO6 ((PIN_PC22F_TCC0_WO6 << 16) | MUX_PC22F_TCC0_WO6) +#define PORT_PC22F_TCC0_WO6 (_UL_(1) << 22) +#define PIN_PA19G_TCC0_WO7 _L_(19) /**< \brief TCC0 signal: WO7 on PA19 mux G */ +#define MUX_PA19G_TCC0_WO7 _L_(6) +#define PINMUX_PA19G_TCC0_WO7 ((PIN_PA19G_TCC0_WO7 << 16) | MUX_PA19G_TCC0_WO7) +#define PORT_PA19G_TCC0_WO7 (_UL_(1) << 19) +#define PIN_PB31G_TCC0_WO7 _L_(63) /**< \brief TCC0 signal: WO7 on PB31 mux G */ +#define MUX_PB31G_TCC0_WO7 _L_(6) +#define PINMUX_PB31G_TCC0_WO7 ((PIN_PB31G_TCC0_WO7 << 16) | MUX_PB31G_TCC0_WO7) +#define PORT_PB31G_TCC0_WO7 (_UL_(1) << 31) +#define PIN_PA13F_TCC0_WO7 _L_(13) /**< \brief TCC0 signal: WO7 on PA13 mux F */ +#define MUX_PA13F_TCC0_WO7 _L_(5) +#define PINMUX_PA13F_TCC0_WO7 ((PIN_PA13F_TCC0_WO7 << 16) | MUX_PA13F_TCC0_WO7) +#define PORT_PA13F_TCC0_WO7 (_UL_(1) << 13) +#define PIN_PC23F_TCC0_WO7 _L_(87) /**< \brief TCC0 signal: WO7 on PC23 mux F */ +#define MUX_PC23F_TCC0_WO7 _L_(5) +#define PINMUX_PC23F_TCC0_WO7 ((PIN_PC23F_TCC0_WO7 << 16) | MUX_PC23F_TCC0_WO7) +#define PORT_PC23F_TCC0_WO7 (_UL_(1) << 23) +/* ========== PORT definition for TCC1 peripheral ========== */ +#define PIN_PB10G_TCC1_WO0 _L_(42) /**< \brief TCC1 signal: WO0 on PB10 mux G */ +#define MUX_PB10G_TCC1_WO0 _L_(6) +#define PINMUX_PB10G_TCC1_WO0 ((PIN_PB10G_TCC1_WO0 << 16) | MUX_PB10G_TCC1_WO0) +#define PORT_PB10G_TCC1_WO0 (_UL_(1) << 10) +#define PIN_PC14G_TCC1_WO0 _L_(78) /**< \brief TCC1 signal: WO0 on PC14 mux G */ +#define MUX_PC14G_TCC1_WO0 _L_(6) +#define PINMUX_PC14G_TCC1_WO0 ((PIN_PC14G_TCC1_WO0 << 16) | MUX_PC14G_TCC1_WO0) +#define PORT_PC14G_TCC1_WO0 (_UL_(1) << 14) +#define PIN_PA16F_TCC1_WO0 _L_(16) /**< \brief TCC1 signal: WO0 on PA16 mux F */ +#define MUX_PA16F_TCC1_WO0 _L_(5) +#define PINMUX_PA16F_TCC1_WO0 ((PIN_PA16F_TCC1_WO0 << 16) | MUX_PA16F_TCC1_WO0) +#define PORT_PA16F_TCC1_WO0 (_UL_(1) << 16) +#define PIN_PB18F_TCC1_WO0 _L_(50) /**< \brief TCC1 signal: WO0 on PB18 mux F */ +#define MUX_PB18F_TCC1_WO0 _L_(5) +#define PINMUX_PB18F_TCC1_WO0 ((PIN_PB18F_TCC1_WO0 << 16) | MUX_PB18F_TCC1_WO0) +#define PORT_PB18F_TCC1_WO0 (_UL_(1) << 18) +#define PIN_PD20F_TCC1_WO0 _L_(116) /**< \brief TCC1 signal: WO0 on PD20 mux F */ +#define MUX_PD20F_TCC1_WO0 _L_(5) +#define PINMUX_PD20F_TCC1_WO0 ((PIN_PD20F_TCC1_WO0 << 16) | MUX_PD20F_TCC1_WO0) +#define PORT_PD20F_TCC1_WO0 (_UL_(1) << 20) +#define PIN_PB11G_TCC1_WO1 _L_(43) /**< \brief TCC1 signal: WO1 on PB11 mux G */ +#define MUX_PB11G_TCC1_WO1 _L_(6) +#define PINMUX_PB11G_TCC1_WO1 ((PIN_PB11G_TCC1_WO1 << 16) | MUX_PB11G_TCC1_WO1) +#define PORT_PB11G_TCC1_WO1 (_UL_(1) << 11) +#define PIN_PC15G_TCC1_WO1 _L_(79) /**< \brief TCC1 signal: WO1 on PC15 mux G */ +#define MUX_PC15G_TCC1_WO1 _L_(6) +#define PINMUX_PC15G_TCC1_WO1 ((PIN_PC15G_TCC1_WO1 << 16) | MUX_PC15G_TCC1_WO1) +#define PORT_PC15G_TCC1_WO1 (_UL_(1) << 15) +#define PIN_PA17F_TCC1_WO1 _L_(17) /**< \brief TCC1 signal: WO1 on PA17 mux F */ +#define MUX_PA17F_TCC1_WO1 _L_(5) +#define PINMUX_PA17F_TCC1_WO1 ((PIN_PA17F_TCC1_WO1 << 16) | MUX_PA17F_TCC1_WO1) +#define PORT_PA17F_TCC1_WO1 (_UL_(1) << 17) +#define PIN_PB19F_TCC1_WO1 _L_(51) /**< \brief TCC1 signal: WO1 on PB19 mux F */ +#define MUX_PB19F_TCC1_WO1 _L_(5) +#define PINMUX_PB19F_TCC1_WO1 ((PIN_PB19F_TCC1_WO1 << 16) | MUX_PB19F_TCC1_WO1) +#define PORT_PB19F_TCC1_WO1 (_UL_(1) << 19) +#define PIN_PD21F_TCC1_WO1 _L_(117) /**< \brief TCC1 signal: WO1 on PD21 mux F */ +#define MUX_PD21F_TCC1_WO1 _L_(5) +#define PINMUX_PD21F_TCC1_WO1 ((PIN_PD21F_TCC1_WO1 << 16) | MUX_PD21F_TCC1_WO1) +#define PORT_PD21F_TCC1_WO1 (_UL_(1) << 21) +#define PIN_PA12G_TCC1_WO2 _L_(12) /**< \brief TCC1 signal: WO2 on PA12 mux G */ +#define MUX_PA12G_TCC1_WO2 _L_(6) +#define PINMUX_PA12G_TCC1_WO2 ((PIN_PA12G_TCC1_WO2 << 16) | MUX_PA12G_TCC1_WO2) +#define PORT_PA12G_TCC1_WO2 (_UL_(1) << 12) +#define PIN_PA14G_TCC1_WO2 _L_(14) /**< \brief TCC1 signal: WO2 on PA14 mux G */ +#define MUX_PA14G_TCC1_WO2 _L_(6) +#define PINMUX_PA14G_TCC1_WO2 ((PIN_PA14G_TCC1_WO2 << 16) | MUX_PA14G_TCC1_WO2) +#define PORT_PA14G_TCC1_WO2 (_UL_(1) << 14) +#define PIN_PA18F_TCC1_WO2 _L_(18) /**< \brief TCC1 signal: WO2 on PA18 mux F */ +#define MUX_PA18F_TCC1_WO2 _L_(5) +#define PINMUX_PA18F_TCC1_WO2 ((PIN_PA18F_TCC1_WO2 << 16) | MUX_PA18F_TCC1_WO2) +#define PORT_PA18F_TCC1_WO2 (_UL_(1) << 18) +#define PIN_PB20F_TCC1_WO2 _L_(52) /**< \brief TCC1 signal: WO2 on PB20 mux F */ +#define MUX_PB20F_TCC1_WO2 _L_(5) +#define PINMUX_PB20F_TCC1_WO2 ((PIN_PB20F_TCC1_WO2 << 16) | MUX_PB20F_TCC1_WO2) +#define PORT_PB20F_TCC1_WO2 (_UL_(1) << 20) +#define PIN_PB26F_TCC1_WO2 _L_(58) /**< \brief TCC1 signal: WO2 on PB26 mux F */ +#define MUX_PB26F_TCC1_WO2 _L_(5) +#define PINMUX_PB26F_TCC1_WO2 ((PIN_PB26F_TCC1_WO2 << 16) | MUX_PB26F_TCC1_WO2) +#define PORT_PB26F_TCC1_WO2 (_UL_(1) << 26) +#define PIN_PA13G_TCC1_WO3 _L_(13) /**< \brief TCC1 signal: WO3 on PA13 mux G */ +#define MUX_PA13G_TCC1_WO3 _L_(6) +#define PINMUX_PA13G_TCC1_WO3 ((PIN_PA13G_TCC1_WO3 << 16) | MUX_PA13G_TCC1_WO3) +#define PORT_PA13G_TCC1_WO3 (_UL_(1) << 13) +#define PIN_PA15G_TCC1_WO3 _L_(15) /**< \brief TCC1 signal: WO3 on PA15 mux G */ +#define MUX_PA15G_TCC1_WO3 _L_(6) +#define PINMUX_PA15G_TCC1_WO3 ((PIN_PA15G_TCC1_WO3 << 16) | MUX_PA15G_TCC1_WO3) +#define PORT_PA15G_TCC1_WO3 (_UL_(1) << 15) +#define PIN_PA19F_TCC1_WO3 _L_(19) /**< \brief TCC1 signal: WO3 on PA19 mux F */ +#define MUX_PA19F_TCC1_WO3 _L_(5) +#define PINMUX_PA19F_TCC1_WO3 ((PIN_PA19F_TCC1_WO3 << 16) | MUX_PA19F_TCC1_WO3) +#define PORT_PA19F_TCC1_WO3 (_UL_(1) << 19) +#define PIN_PB21F_TCC1_WO3 _L_(53) /**< \brief TCC1 signal: WO3 on PB21 mux F */ +#define MUX_PB21F_TCC1_WO3 _L_(5) +#define PINMUX_PB21F_TCC1_WO3 ((PIN_PB21F_TCC1_WO3 << 16) | MUX_PB21F_TCC1_WO3) +#define PORT_PB21F_TCC1_WO3 (_UL_(1) << 21) +#define PIN_PB27F_TCC1_WO3 _L_(59) /**< \brief TCC1 signal: WO3 on PB27 mux F */ +#define MUX_PB27F_TCC1_WO3 _L_(5) +#define PINMUX_PB27F_TCC1_WO3 ((PIN_PB27F_TCC1_WO3 << 16) | MUX_PB27F_TCC1_WO3) +#define PORT_PB27F_TCC1_WO3 (_UL_(1) << 27) +#define PIN_PA08G_TCC1_WO4 _L_(8) /**< \brief TCC1 signal: WO4 on PA08 mux G */ +#define MUX_PA08G_TCC1_WO4 _L_(6) +#define PINMUX_PA08G_TCC1_WO4 ((PIN_PA08G_TCC1_WO4 << 16) | MUX_PA08G_TCC1_WO4) +#define PORT_PA08G_TCC1_WO4 (_UL_(1) << 8) +#define PIN_PC10G_TCC1_WO4 _L_(74) /**< \brief TCC1 signal: WO4 on PC10 mux G */ +#define MUX_PC10G_TCC1_WO4 _L_(6) +#define PINMUX_PC10G_TCC1_WO4 ((PIN_PC10G_TCC1_WO4 << 16) | MUX_PC10G_TCC1_WO4) +#define PORT_PC10G_TCC1_WO4 (_UL_(1) << 10) +#define PIN_PA20F_TCC1_WO4 _L_(20) /**< \brief TCC1 signal: WO4 on PA20 mux F */ +#define MUX_PA20F_TCC1_WO4 _L_(5) +#define PINMUX_PA20F_TCC1_WO4 ((PIN_PA20F_TCC1_WO4 << 16) | MUX_PA20F_TCC1_WO4) +#define PORT_PA20F_TCC1_WO4 (_UL_(1) << 20) +#define PIN_PB28F_TCC1_WO4 _L_(60) /**< \brief TCC1 signal: WO4 on PB28 mux F */ +#define MUX_PB28F_TCC1_WO4 _L_(5) +#define PINMUX_PB28F_TCC1_WO4 ((PIN_PB28F_TCC1_WO4 << 16) | MUX_PB28F_TCC1_WO4) +#define PORT_PB28F_TCC1_WO4 (_UL_(1) << 28) +#define PIN_PA09G_TCC1_WO5 _L_(9) /**< \brief TCC1 signal: WO5 on PA09 mux G */ +#define MUX_PA09G_TCC1_WO5 _L_(6) +#define PINMUX_PA09G_TCC1_WO5 ((PIN_PA09G_TCC1_WO5 << 16) | MUX_PA09G_TCC1_WO5) +#define PORT_PA09G_TCC1_WO5 (_UL_(1) << 9) +#define PIN_PC11G_TCC1_WO5 _L_(75) /**< \brief TCC1 signal: WO5 on PC11 mux G */ +#define MUX_PC11G_TCC1_WO5 _L_(6) +#define PINMUX_PC11G_TCC1_WO5 ((PIN_PC11G_TCC1_WO5 << 16) | MUX_PC11G_TCC1_WO5) +#define PORT_PC11G_TCC1_WO5 (_UL_(1) << 11) +#define PIN_PA21F_TCC1_WO5 _L_(21) /**< \brief TCC1 signal: WO5 on PA21 mux F */ +#define MUX_PA21F_TCC1_WO5 _L_(5) +#define PINMUX_PA21F_TCC1_WO5 ((PIN_PA21F_TCC1_WO5 << 16) | MUX_PA21F_TCC1_WO5) +#define PORT_PA21F_TCC1_WO5 (_UL_(1) << 21) +#define PIN_PB29F_TCC1_WO5 _L_(61) /**< \brief TCC1 signal: WO5 on PB29 mux F */ +#define MUX_PB29F_TCC1_WO5 _L_(5) +#define PINMUX_PB29F_TCC1_WO5 ((PIN_PB29F_TCC1_WO5 << 16) | MUX_PB29F_TCC1_WO5) +#define PORT_PB29F_TCC1_WO5 (_UL_(1) << 29) +#define PIN_PA10G_TCC1_WO6 _L_(10) /**< \brief TCC1 signal: WO6 on PA10 mux G */ +#define MUX_PA10G_TCC1_WO6 _L_(6) +#define PINMUX_PA10G_TCC1_WO6 ((PIN_PA10G_TCC1_WO6 << 16) | MUX_PA10G_TCC1_WO6) +#define PORT_PA10G_TCC1_WO6 (_UL_(1) << 10) +#define PIN_PC12G_TCC1_WO6 _L_(76) /**< \brief TCC1 signal: WO6 on PC12 mux G */ +#define MUX_PC12G_TCC1_WO6 _L_(6) +#define PINMUX_PC12G_TCC1_WO6 ((PIN_PC12G_TCC1_WO6 << 16) | MUX_PC12G_TCC1_WO6) +#define PORT_PC12G_TCC1_WO6 (_UL_(1) << 12) +#define PIN_PA22F_TCC1_WO6 _L_(22) /**< \brief TCC1 signal: WO6 on PA22 mux F */ +#define MUX_PA22F_TCC1_WO6 _L_(5) +#define PINMUX_PA22F_TCC1_WO6 ((PIN_PA22F_TCC1_WO6 << 16) | MUX_PA22F_TCC1_WO6) +#define PORT_PA22F_TCC1_WO6 (_UL_(1) << 22) +#define PIN_PA11G_TCC1_WO7 _L_(11) /**< \brief TCC1 signal: WO7 on PA11 mux G */ +#define MUX_PA11G_TCC1_WO7 _L_(6) +#define PINMUX_PA11G_TCC1_WO7 ((PIN_PA11G_TCC1_WO7 << 16) | MUX_PA11G_TCC1_WO7) +#define PORT_PA11G_TCC1_WO7 (_UL_(1) << 11) +#define PIN_PC13G_TCC1_WO7 _L_(77) /**< \brief TCC1 signal: WO7 on PC13 mux G */ +#define MUX_PC13G_TCC1_WO7 _L_(6) +#define PINMUX_PC13G_TCC1_WO7 ((PIN_PC13G_TCC1_WO7 << 16) | MUX_PC13G_TCC1_WO7) +#define PORT_PC13G_TCC1_WO7 (_UL_(1) << 13) +#define PIN_PA23F_TCC1_WO7 _L_(23) /**< \brief TCC1 signal: WO7 on PA23 mux F */ +#define MUX_PA23F_TCC1_WO7 _L_(5) +#define PINMUX_PA23F_TCC1_WO7 ((PIN_PA23F_TCC1_WO7 << 16) | MUX_PA23F_TCC1_WO7) +#define PORT_PA23F_TCC1_WO7 (_UL_(1) << 23) +/* ========== PORT definition for TC2 peripheral ========== */ +#define PIN_PA12E_TC2_WO0 _L_(12) /**< \brief TC2 signal: WO0 on PA12 mux E */ +#define MUX_PA12E_TC2_WO0 _L_(4) +#define PINMUX_PA12E_TC2_WO0 ((PIN_PA12E_TC2_WO0 << 16) | MUX_PA12E_TC2_WO0) +#define PORT_PA12E_TC2_WO0 (_UL_(1) << 12) +#define PIN_PA16E_TC2_WO0 _L_(16) /**< \brief TC2 signal: WO0 on PA16 mux E */ +#define MUX_PA16E_TC2_WO0 _L_(4) +#define PINMUX_PA16E_TC2_WO0 ((PIN_PA16E_TC2_WO0 << 16) | MUX_PA16E_TC2_WO0) +#define PORT_PA16E_TC2_WO0 (_UL_(1) << 16) +#define PIN_PA00E_TC2_WO0 _L_(0) /**< \brief TC2 signal: WO0 on PA00 mux E */ +#define MUX_PA00E_TC2_WO0 _L_(4) +#define PINMUX_PA00E_TC2_WO0 ((PIN_PA00E_TC2_WO0 << 16) | MUX_PA00E_TC2_WO0) +#define PORT_PA00E_TC2_WO0 (_UL_(1) << 0) +#define PIN_PA01E_TC2_WO1 _L_(1) /**< \brief TC2 signal: WO1 on PA01 mux E */ +#define MUX_PA01E_TC2_WO1 _L_(4) +#define PINMUX_PA01E_TC2_WO1 ((PIN_PA01E_TC2_WO1 << 16) | MUX_PA01E_TC2_WO1) +#define PORT_PA01E_TC2_WO1 (_UL_(1) << 1) +#define PIN_PA13E_TC2_WO1 _L_(13) /**< \brief TC2 signal: WO1 on PA13 mux E */ +#define MUX_PA13E_TC2_WO1 _L_(4) +#define PINMUX_PA13E_TC2_WO1 ((PIN_PA13E_TC2_WO1 << 16) | MUX_PA13E_TC2_WO1) +#define PORT_PA13E_TC2_WO1 (_UL_(1) << 13) +#define PIN_PA17E_TC2_WO1 _L_(17) /**< \brief TC2 signal: WO1 on PA17 mux E */ +#define MUX_PA17E_TC2_WO1 _L_(4) +#define PINMUX_PA17E_TC2_WO1 ((PIN_PA17E_TC2_WO1 << 16) | MUX_PA17E_TC2_WO1) +#define PORT_PA17E_TC2_WO1 (_UL_(1) << 17) +/* ========== PORT definition for TC3 peripheral ========== */ +#define PIN_PA18E_TC3_WO0 _L_(18) /**< \brief TC3 signal: WO0 on PA18 mux E */ +#define MUX_PA18E_TC3_WO0 _L_(4) +#define PINMUX_PA18E_TC3_WO0 ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0) +#define PORT_PA18E_TC3_WO0 (_UL_(1) << 18) +#define PIN_PA14E_TC3_WO0 _L_(14) /**< \brief TC3 signal: WO0 on PA14 mux E */ +#define MUX_PA14E_TC3_WO0 _L_(4) +#define PINMUX_PA14E_TC3_WO0 ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0) +#define PORT_PA14E_TC3_WO0 (_UL_(1) << 14) +#define PIN_PA15E_TC3_WO1 _L_(15) /**< \brief TC3 signal: WO1 on PA15 mux E */ +#define MUX_PA15E_TC3_WO1 _L_(4) +#define PINMUX_PA15E_TC3_WO1 ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1) +#define PORT_PA15E_TC3_WO1 (_UL_(1) << 15) +#define PIN_PA19E_TC3_WO1 _L_(19) /**< \brief TC3 signal: WO1 on PA19 mux E */ +#define MUX_PA19E_TC3_WO1 _L_(4) +#define PINMUX_PA19E_TC3_WO1 ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1) +#define PORT_PA19E_TC3_WO1 (_UL_(1) << 19) +/* ========== PORT definition for CAN0 peripheral ========== */ +#define PIN_PA23I_CAN0_RX _L_(23) /**< \brief CAN0 signal: RX on PA23 mux I */ +#define MUX_PA23I_CAN0_RX _L_(8) +#define PINMUX_PA23I_CAN0_RX ((PIN_PA23I_CAN0_RX << 16) | MUX_PA23I_CAN0_RX) +#define PORT_PA23I_CAN0_RX (_UL_(1) << 23) +#define PIN_PA25I_CAN0_RX _L_(25) /**< \brief CAN0 signal: RX on PA25 mux I */ +#define MUX_PA25I_CAN0_RX _L_(8) +#define PINMUX_PA25I_CAN0_RX ((PIN_PA25I_CAN0_RX << 16) | MUX_PA25I_CAN0_RX) +#define PORT_PA25I_CAN0_RX (_UL_(1) << 25) +#define PIN_PA22I_CAN0_TX _L_(22) /**< \brief CAN0 signal: TX on PA22 mux I */ +#define MUX_PA22I_CAN0_TX _L_(8) +#define PINMUX_PA22I_CAN0_TX ((PIN_PA22I_CAN0_TX << 16) | MUX_PA22I_CAN0_TX) +#define PORT_PA22I_CAN0_TX (_UL_(1) << 22) +#define PIN_PA24I_CAN0_TX _L_(24) /**< \brief CAN0 signal: TX on PA24 mux I */ +#define MUX_PA24I_CAN0_TX _L_(8) +#define PINMUX_PA24I_CAN0_TX ((PIN_PA24I_CAN0_TX << 16) | MUX_PA24I_CAN0_TX) +#define PORT_PA24I_CAN0_TX (_UL_(1) << 24) +/* ========== PORT definition for CAN1 peripheral ========== */ +#define PIN_PB13H_CAN1_RX _L_(45) /**< \brief CAN1 signal: RX on PB13 mux H */ +#define MUX_PB13H_CAN1_RX _L_(7) +#define PINMUX_PB13H_CAN1_RX ((PIN_PB13H_CAN1_RX << 16) | MUX_PB13H_CAN1_RX) +#define PORT_PB13H_CAN1_RX (_UL_(1) << 13) +#define PIN_PB15H_CAN1_RX _L_(47) /**< \brief CAN1 signal: RX on PB15 mux H */ +#define MUX_PB15H_CAN1_RX _L_(7) +#define PINMUX_PB15H_CAN1_RX ((PIN_PB15H_CAN1_RX << 16) | MUX_PB15H_CAN1_RX) +#define PORT_PB15H_CAN1_RX (_UL_(1) << 15) +#define PIN_PB12H_CAN1_TX _L_(44) /**< \brief CAN1 signal: TX on PB12 mux H */ +#define MUX_PB12H_CAN1_TX _L_(7) +#define PINMUX_PB12H_CAN1_TX ((PIN_PB12H_CAN1_TX << 16) | MUX_PB12H_CAN1_TX) +#define PORT_PB12H_CAN1_TX (_UL_(1) << 12) +#define PIN_PB14H_CAN1_TX _L_(46) /**< \brief CAN1 signal: TX on PB14 mux H */ +#define MUX_PB14H_CAN1_TX _L_(7) +#define PINMUX_PB14H_CAN1_TX ((PIN_PB14H_CAN1_TX << 16) | MUX_PB14H_CAN1_TX) +#define PORT_PB14H_CAN1_TX (_UL_(1) << 14) +/* ========== PORT definition for GMAC peripheral ========== */ +#define PIN_PC21L_GMAC_GCOL _L_(85) /**< \brief GMAC signal: GCOL on PC21 mux L */ +#define MUX_PC21L_GMAC_GCOL _L_(11) +#define PINMUX_PC21L_GMAC_GCOL ((PIN_PC21L_GMAC_GCOL << 16) | MUX_PC21L_GMAC_GCOL) +#define PORT_PC21L_GMAC_GCOL (_UL_(1) << 21) +#define PIN_PA16L_GMAC_GCRS _L_(16) /**< \brief GMAC signal: GCRS on PA16 mux L */ +#define MUX_PA16L_GMAC_GCRS _L_(11) +#define PINMUX_PA16L_GMAC_GCRS ((PIN_PA16L_GMAC_GCRS << 16) | MUX_PA16L_GMAC_GCRS) +#define PORT_PA16L_GMAC_GCRS (_UL_(1) << 16) +#define PIN_PA20L_GMAC_GMDC _L_(20) /**< \brief GMAC signal: GMDC on PA20 mux L */ +#define MUX_PA20L_GMAC_GMDC _L_(11) +#define PINMUX_PA20L_GMAC_GMDC ((PIN_PA20L_GMAC_GMDC << 16) | MUX_PA20L_GMAC_GMDC) +#define PORT_PA20L_GMAC_GMDC (_UL_(1) << 20) +#define PIN_PB14L_GMAC_GMDC _L_(46) /**< \brief GMAC signal: GMDC on PB14 mux L */ +#define MUX_PB14L_GMAC_GMDC _L_(11) +#define PINMUX_PB14L_GMAC_GMDC ((PIN_PB14L_GMAC_GMDC << 16) | MUX_PB14L_GMAC_GMDC) +#define PORT_PB14L_GMAC_GMDC (_UL_(1) << 14) +#define PIN_PC11L_GMAC_GMDC _L_(75) /**< \brief GMAC signal: GMDC on PC11 mux L */ +#define MUX_PC11L_GMAC_GMDC _L_(11) +#define PINMUX_PC11L_GMAC_GMDC ((PIN_PC11L_GMAC_GMDC << 16) | MUX_PC11L_GMAC_GMDC) +#define PORT_PC11L_GMAC_GMDC (_UL_(1) << 11) +#define PIN_PC22L_GMAC_GMDC _L_(86) /**< \brief GMAC signal: GMDC on PC22 mux L */ +#define MUX_PC22L_GMAC_GMDC _L_(11) +#define PINMUX_PC22L_GMAC_GMDC ((PIN_PC22L_GMAC_GMDC << 16) | MUX_PC22L_GMAC_GMDC) +#define PORT_PC22L_GMAC_GMDC (_UL_(1) << 22) +#define PIN_PA21L_GMAC_GMDIO _L_(21) /**< \brief GMAC signal: GMDIO on PA21 mux L */ +#define MUX_PA21L_GMAC_GMDIO _L_(11) +#define PINMUX_PA21L_GMAC_GMDIO ((PIN_PA21L_GMAC_GMDIO << 16) | MUX_PA21L_GMAC_GMDIO) +#define PORT_PA21L_GMAC_GMDIO (_UL_(1) << 21) +#define PIN_PB15L_GMAC_GMDIO _L_(47) /**< \brief GMAC signal: GMDIO on PB15 mux L */ +#define MUX_PB15L_GMAC_GMDIO _L_(11) +#define PINMUX_PB15L_GMAC_GMDIO ((PIN_PB15L_GMAC_GMDIO << 16) | MUX_PB15L_GMAC_GMDIO) +#define PORT_PB15L_GMAC_GMDIO (_UL_(1) << 15) +#define PIN_PC12L_GMAC_GMDIO _L_(76) /**< \brief GMAC signal: GMDIO on PC12 mux L */ +#define MUX_PC12L_GMAC_GMDIO _L_(11) +#define PINMUX_PC12L_GMAC_GMDIO ((PIN_PC12L_GMAC_GMDIO << 16) | MUX_PC12L_GMAC_GMDIO) +#define PORT_PC12L_GMAC_GMDIO (_UL_(1) << 12) +#define PIN_PC23L_GMAC_GMDIO _L_(87) /**< \brief GMAC signal: GMDIO on PC23 mux L */ +#define MUX_PC23L_GMAC_GMDIO _L_(11) +#define PINMUX_PC23L_GMAC_GMDIO ((PIN_PC23L_GMAC_GMDIO << 16) | MUX_PC23L_GMAC_GMDIO) +#define PORT_PC23L_GMAC_GMDIO (_UL_(1) << 23) +#define PIN_PA13L_GMAC_GRX0 _L_(13) /**< \brief GMAC signal: GRX0 on PA13 mux L */ +#define MUX_PA13L_GMAC_GRX0 _L_(11) +#define PINMUX_PA13L_GMAC_GRX0 ((PIN_PA13L_GMAC_GRX0 << 16) | MUX_PA13L_GMAC_GRX0) +#define PORT_PA13L_GMAC_GRX0 (_UL_(1) << 13) +#define PIN_PA12L_GMAC_GRX1 _L_(12) /**< \brief GMAC signal: GRX1 on PA12 mux L */ +#define MUX_PA12L_GMAC_GRX1 _L_(11) +#define PINMUX_PA12L_GMAC_GRX1 ((PIN_PA12L_GMAC_GRX1 << 16) | MUX_PA12L_GMAC_GRX1) +#define PORT_PA12L_GMAC_GRX1 (_UL_(1) << 12) +#define PIN_PC15L_GMAC_GRX2 _L_(79) /**< \brief GMAC signal: GRX2 on PC15 mux L */ +#define MUX_PC15L_GMAC_GRX2 _L_(11) +#define PINMUX_PC15L_GMAC_GRX2 ((PIN_PC15L_GMAC_GRX2 << 16) | MUX_PC15L_GMAC_GRX2) +#define PORT_PC15L_GMAC_GRX2 (_UL_(1) << 15) +#define PIN_PC14L_GMAC_GRX3 _L_(78) /**< \brief GMAC signal: GRX3 on PC14 mux L */ +#define MUX_PC14L_GMAC_GRX3 _L_(11) +#define PINMUX_PC14L_GMAC_GRX3 ((PIN_PC14L_GMAC_GRX3 << 16) | MUX_PC14L_GMAC_GRX3) +#define PORT_PC14L_GMAC_GRX3 (_UL_(1) << 14) +#define PIN_PC18L_GMAC_GRXCK _L_(82) /**< \brief GMAC signal: GRXCK on PC18 mux L */ +#define MUX_PC18L_GMAC_GRXCK _L_(11) +#define PINMUX_PC18L_GMAC_GRXCK ((PIN_PC18L_GMAC_GRXCK << 16) | MUX_PC18L_GMAC_GRXCK) +#define PORT_PC18L_GMAC_GRXCK (_UL_(1) << 18) +#define PIN_PC20L_GMAC_GRXDV _L_(84) /**< \brief GMAC signal: GRXDV on PC20 mux L */ +#define MUX_PC20L_GMAC_GRXDV _L_(11) +#define PINMUX_PC20L_GMAC_GRXDV ((PIN_PC20L_GMAC_GRXDV << 16) | MUX_PC20L_GMAC_GRXDV) +#define PORT_PC20L_GMAC_GRXDV (_UL_(1) << 20) +#define PIN_PA15L_GMAC_GRXER _L_(15) /**< \brief GMAC signal: GRXER on PA15 mux L */ +#define MUX_PA15L_GMAC_GRXER _L_(11) +#define PINMUX_PA15L_GMAC_GRXER ((PIN_PA15L_GMAC_GRXER << 16) | MUX_PA15L_GMAC_GRXER) +#define PORT_PA15L_GMAC_GRXER (_UL_(1) << 15) +#define PIN_PA18L_GMAC_GTX0 _L_(18) /**< \brief GMAC signal: GTX0 on PA18 mux L */ +#define MUX_PA18L_GMAC_GTX0 _L_(11) +#define PINMUX_PA18L_GMAC_GTX0 ((PIN_PA18L_GMAC_GTX0 << 16) | MUX_PA18L_GMAC_GTX0) +#define PORT_PA18L_GMAC_GTX0 (_UL_(1) << 18) +#define PIN_PA19L_GMAC_GTX1 _L_(19) /**< \brief GMAC signal: GTX1 on PA19 mux L */ +#define MUX_PA19L_GMAC_GTX1 _L_(11) +#define PINMUX_PA19L_GMAC_GTX1 ((PIN_PA19L_GMAC_GTX1 << 16) | MUX_PA19L_GMAC_GTX1) +#define PORT_PA19L_GMAC_GTX1 (_UL_(1) << 19) +#define PIN_PC16L_GMAC_GTX2 _L_(80) /**< \brief GMAC signal: GTX2 on PC16 mux L */ +#define MUX_PC16L_GMAC_GTX2 _L_(11) +#define PINMUX_PC16L_GMAC_GTX2 ((PIN_PC16L_GMAC_GTX2 << 16) | MUX_PC16L_GMAC_GTX2) +#define PORT_PC16L_GMAC_GTX2 (_UL_(1) << 16) +#define PIN_PC17L_GMAC_GTX3 _L_(81) /**< \brief GMAC signal: GTX3 on PC17 mux L */ +#define MUX_PC17L_GMAC_GTX3 _L_(11) +#define PINMUX_PC17L_GMAC_GTX3 ((PIN_PC17L_GMAC_GTX3 << 16) | MUX_PC17L_GMAC_GTX3) +#define PORT_PC17L_GMAC_GTX3 (_UL_(1) << 17) +#define PIN_PA14L_GMAC_GTXCK _L_(14) /**< \brief GMAC signal: GTXCK on PA14 mux L */ +#define MUX_PA14L_GMAC_GTXCK _L_(11) +#define PINMUX_PA14L_GMAC_GTXCK ((PIN_PA14L_GMAC_GTXCK << 16) | MUX_PA14L_GMAC_GTXCK) +#define PORT_PA14L_GMAC_GTXCK (_UL_(1) << 14) +#define PIN_PA17L_GMAC_GTXEN _L_(17) /**< \brief GMAC signal: GTXEN on PA17 mux L */ +#define MUX_PA17L_GMAC_GTXEN _L_(11) +#define PINMUX_PA17L_GMAC_GTXEN ((PIN_PA17L_GMAC_GTXEN << 16) | MUX_PA17L_GMAC_GTXEN) +#define PORT_PA17L_GMAC_GTXEN (_UL_(1) << 17) +#define PIN_PC19L_GMAC_GTXER _L_(83) /**< \brief GMAC signal: GTXER on PC19 mux L */ +#define MUX_PC19L_GMAC_GTXER _L_(11) +#define PINMUX_PC19L_GMAC_GTXER ((PIN_PC19L_GMAC_GTXER << 16) | MUX_PC19L_GMAC_GTXER) +#define PORT_PC19L_GMAC_GTXER (_UL_(1) << 19) +/* ========== PORT definition for TCC2 peripheral ========== */ +#define PIN_PA14F_TCC2_WO0 _L_(14) /**< \brief TCC2 signal: WO0 on PA14 mux F */ +#define MUX_PA14F_TCC2_WO0 _L_(5) +#define PINMUX_PA14F_TCC2_WO0 ((PIN_PA14F_TCC2_WO0 << 16) | MUX_PA14F_TCC2_WO0) +#define PORT_PA14F_TCC2_WO0 (_UL_(1) << 14) +#define PIN_PA30F_TCC2_WO0 _L_(30) /**< \brief TCC2 signal: WO0 on PA30 mux F */ +#define MUX_PA30F_TCC2_WO0 _L_(5) +#define PINMUX_PA30F_TCC2_WO0 ((PIN_PA30F_TCC2_WO0 << 16) | MUX_PA30F_TCC2_WO0) +#define PORT_PA30F_TCC2_WO0 (_UL_(1) << 30) +#define PIN_PA15F_TCC2_WO1 _L_(15) /**< \brief TCC2 signal: WO1 on PA15 mux F */ +#define MUX_PA15F_TCC2_WO1 _L_(5) +#define PINMUX_PA15F_TCC2_WO1 ((PIN_PA15F_TCC2_WO1 << 16) | MUX_PA15F_TCC2_WO1) +#define PORT_PA15F_TCC2_WO1 (_UL_(1) << 15) +#define PIN_PA31F_TCC2_WO1 _L_(31) /**< \brief TCC2 signal: WO1 on PA31 mux F */ +#define MUX_PA31F_TCC2_WO1 _L_(5) +#define PINMUX_PA31F_TCC2_WO1 ((PIN_PA31F_TCC2_WO1 << 16) | MUX_PA31F_TCC2_WO1) +#define PORT_PA31F_TCC2_WO1 (_UL_(1) << 31) +#define PIN_PA24F_TCC2_WO2 _L_(24) /**< \brief TCC2 signal: WO2 on PA24 mux F */ +#define MUX_PA24F_TCC2_WO2 _L_(5) +#define PINMUX_PA24F_TCC2_WO2 ((PIN_PA24F_TCC2_WO2 << 16) | MUX_PA24F_TCC2_WO2) +#define PORT_PA24F_TCC2_WO2 (_UL_(1) << 24) +#define PIN_PB02F_TCC2_WO2 _L_(34) /**< \brief TCC2 signal: WO2 on PB02 mux F */ +#define MUX_PB02F_TCC2_WO2 _L_(5) +#define PINMUX_PB02F_TCC2_WO2 ((PIN_PB02F_TCC2_WO2 << 16) | MUX_PB02F_TCC2_WO2) +#define PORT_PB02F_TCC2_WO2 (_UL_(1) << 2) +/* ========== PORT definition for TCC3 peripheral ========== */ +#define PIN_PB12F_TCC3_WO0 _L_(44) /**< \brief TCC3 signal: WO0 on PB12 mux F */ +#define MUX_PB12F_TCC3_WO0 _L_(5) +#define PINMUX_PB12F_TCC3_WO0 ((PIN_PB12F_TCC3_WO0 << 16) | MUX_PB12F_TCC3_WO0) +#define PORT_PB12F_TCC3_WO0 (_UL_(1) << 12) +#define PIN_PB16F_TCC3_WO0 _L_(48) /**< \brief TCC3 signal: WO0 on PB16 mux F */ +#define MUX_PB16F_TCC3_WO0 _L_(5) +#define PINMUX_PB16F_TCC3_WO0 ((PIN_PB16F_TCC3_WO0 << 16) | MUX_PB16F_TCC3_WO0) +#define PORT_PB16F_TCC3_WO0 (_UL_(1) << 16) +#define PIN_PB13F_TCC3_WO1 _L_(45) /**< \brief TCC3 signal: WO1 on PB13 mux F */ +#define MUX_PB13F_TCC3_WO1 _L_(5) +#define PINMUX_PB13F_TCC3_WO1 ((PIN_PB13F_TCC3_WO1 << 16) | MUX_PB13F_TCC3_WO1) +#define PORT_PB13F_TCC3_WO1 (_UL_(1) << 13) +#define PIN_PB17F_TCC3_WO1 _L_(49) /**< \brief TCC3 signal: WO1 on PB17 mux F */ +#define MUX_PB17F_TCC3_WO1 _L_(5) +#define PINMUX_PB17F_TCC3_WO1 ((PIN_PB17F_TCC3_WO1 << 16) | MUX_PB17F_TCC3_WO1) +#define PORT_PB17F_TCC3_WO1 (_UL_(1) << 17) +/* ========== PORT definition for TC4 peripheral ========== */ +#define PIN_PA22E_TC4_WO0 _L_(22) /**< \brief TC4 signal: WO0 on PA22 mux E */ +#define MUX_PA22E_TC4_WO0 _L_(4) +#define PINMUX_PA22E_TC4_WO0 ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0) +#define PORT_PA22E_TC4_WO0 (_UL_(1) << 22) +#define PIN_PB08E_TC4_WO0 _L_(40) /**< \brief TC4 signal: WO0 on PB08 mux E */ +#define MUX_PB08E_TC4_WO0 _L_(4) +#define PINMUX_PB08E_TC4_WO0 ((PIN_PB08E_TC4_WO0 << 16) | MUX_PB08E_TC4_WO0) +#define PORT_PB08E_TC4_WO0 (_UL_(1) << 8) +#define PIN_PB12E_TC4_WO0 _L_(44) /**< \brief TC4 signal: WO0 on PB12 mux E */ +#define MUX_PB12E_TC4_WO0 _L_(4) +#define PINMUX_PB12E_TC4_WO0 ((PIN_PB12E_TC4_WO0 << 16) | MUX_PB12E_TC4_WO0) +#define PORT_PB12E_TC4_WO0 (_UL_(1) << 12) +#define PIN_PA23E_TC4_WO1 _L_(23) /**< \brief TC4 signal: WO1 on PA23 mux E */ +#define MUX_PA23E_TC4_WO1 _L_(4) +#define PINMUX_PA23E_TC4_WO1 ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1) +#define PORT_PA23E_TC4_WO1 (_UL_(1) << 23) +#define PIN_PB09E_TC4_WO1 _L_(41) /**< \brief TC4 signal: WO1 on PB09 mux E */ +#define MUX_PB09E_TC4_WO1 _L_(4) +#define PINMUX_PB09E_TC4_WO1 ((PIN_PB09E_TC4_WO1 << 16) | MUX_PB09E_TC4_WO1) +#define PORT_PB09E_TC4_WO1 (_UL_(1) << 9) +#define PIN_PB13E_TC4_WO1 _L_(45) /**< \brief TC4 signal: WO1 on PB13 mux E */ +#define MUX_PB13E_TC4_WO1 _L_(4) +#define PINMUX_PB13E_TC4_WO1 ((PIN_PB13E_TC4_WO1 << 16) | MUX_PB13E_TC4_WO1) +#define PORT_PB13E_TC4_WO1 (_UL_(1) << 13) +/* ========== PORT definition for TC5 peripheral ========== */ +#define PIN_PA24E_TC5_WO0 _L_(24) /**< \brief TC5 signal: WO0 on PA24 mux E */ +#define MUX_PA24E_TC5_WO0 _L_(4) +#define PINMUX_PA24E_TC5_WO0 ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0) +#define PORT_PA24E_TC5_WO0 (_UL_(1) << 24) +#define PIN_PB10E_TC5_WO0 _L_(42) /**< \brief TC5 signal: WO0 on PB10 mux E */ +#define MUX_PB10E_TC5_WO0 _L_(4) +#define PINMUX_PB10E_TC5_WO0 ((PIN_PB10E_TC5_WO0 << 16) | MUX_PB10E_TC5_WO0) +#define PORT_PB10E_TC5_WO0 (_UL_(1) << 10) +#define PIN_PB14E_TC5_WO0 _L_(46) /**< \brief TC5 signal: WO0 on PB14 mux E */ +#define MUX_PB14E_TC5_WO0 _L_(4) +#define PINMUX_PB14E_TC5_WO0 ((PIN_PB14E_TC5_WO0 << 16) | MUX_PB14E_TC5_WO0) +#define PORT_PB14E_TC5_WO0 (_UL_(1) << 14) +#define PIN_PA25E_TC5_WO1 _L_(25) /**< \brief TC5 signal: WO1 on PA25 mux E */ +#define MUX_PA25E_TC5_WO1 _L_(4) +#define PINMUX_PA25E_TC5_WO1 ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1) +#define PORT_PA25E_TC5_WO1 (_UL_(1) << 25) +#define PIN_PB11E_TC5_WO1 _L_(43) /**< \brief TC5 signal: WO1 on PB11 mux E */ +#define MUX_PB11E_TC5_WO1 _L_(4) +#define PINMUX_PB11E_TC5_WO1 ((PIN_PB11E_TC5_WO1 << 16) | MUX_PB11E_TC5_WO1) +#define PORT_PB11E_TC5_WO1 (_UL_(1) << 11) +#define PIN_PB15E_TC5_WO1 _L_(47) /**< \brief TC5 signal: WO1 on PB15 mux E */ +#define MUX_PB15E_TC5_WO1 _L_(4) +#define PINMUX_PB15E_TC5_WO1 ((PIN_PB15E_TC5_WO1 << 16) | MUX_PB15E_TC5_WO1) +#define PORT_PB15E_TC5_WO1 (_UL_(1) << 15) +/* ========== PORT definition for PDEC peripheral ========== */ +#define PIN_PB18G_PDEC_QDI0 _L_(50) /**< \brief PDEC signal: QDI0 on PB18 mux G */ +#define MUX_PB18G_PDEC_QDI0 _L_(6) +#define PINMUX_PB18G_PDEC_QDI0 ((PIN_PB18G_PDEC_QDI0 << 16) | MUX_PB18G_PDEC_QDI0) +#define PORT_PB18G_PDEC_QDI0 (_UL_(1) << 18) +#define PIN_PB23G_PDEC_QDI0 _L_(55) /**< \brief PDEC signal: QDI0 on PB23 mux G */ +#define MUX_PB23G_PDEC_QDI0 _L_(6) +#define PINMUX_PB23G_PDEC_QDI0 ((PIN_PB23G_PDEC_QDI0 << 16) | MUX_PB23G_PDEC_QDI0) +#define PORT_PB23G_PDEC_QDI0 (_UL_(1) << 23) +#define PIN_PC16G_PDEC_QDI0 _L_(80) /**< \brief PDEC signal: QDI0 on PC16 mux G */ +#define MUX_PC16G_PDEC_QDI0 _L_(6) +#define PINMUX_PC16G_PDEC_QDI0 ((PIN_PC16G_PDEC_QDI0 << 16) | MUX_PC16G_PDEC_QDI0) +#define PORT_PC16G_PDEC_QDI0 (_UL_(1) << 16) +#define PIN_PA24G_PDEC_QDI0 _L_(24) /**< \brief PDEC signal: QDI0 on PA24 mux G */ +#define MUX_PA24G_PDEC_QDI0 _L_(6) +#define PINMUX_PA24G_PDEC_QDI0 ((PIN_PA24G_PDEC_QDI0 << 16) | MUX_PA24G_PDEC_QDI0) +#define PORT_PA24G_PDEC_QDI0 (_UL_(1) << 24) +#define PIN_PB19G_PDEC_QDI1 _L_(51) /**< \brief PDEC signal: QDI1 on PB19 mux G */ +#define MUX_PB19G_PDEC_QDI1 _L_(6) +#define PINMUX_PB19G_PDEC_QDI1 ((PIN_PB19G_PDEC_QDI1 << 16) | MUX_PB19G_PDEC_QDI1) +#define PORT_PB19G_PDEC_QDI1 (_UL_(1) << 19) +#define PIN_PB24G_PDEC_QDI1 _L_(56) /**< \brief PDEC signal: QDI1 on PB24 mux G */ +#define MUX_PB24G_PDEC_QDI1 _L_(6) +#define PINMUX_PB24G_PDEC_QDI1 ((PIN_PB24G_PDEC_QDI1 << 16) | MUX_PB24G_PDEC_QDI1) +#define PORT_PB24G_PDEC_QDI1 (_UL_(1) << 24) +#define PIN_PC17G_PDEC_QDI1 _L_(81) /**< \brief PDEC signal: QDI1 on PC17 mux G */ +#define MUX_PC17G_PDEC_QDI1 _L_(6) +#define PINMUX_PC17G_PDEC_QDI1 ((PIN_PC17G_PDEC_QDI1 << 16) | MUX_PC17G_PDEC_QDI1) +#define PORT_PC17G_PDEC_QDI1 (_UL_(1) << 17) +#define PIN_PA25G_PDEC_QDI1 _L_(25) /**< \brief PDEC signal: QDI1 on PA25 mux G */ +#define MUX_PA25G_PDEC_QDI1 _L_(6) +#define PINMUX_PA25G_PDEC_QDI1 ((PIN_PA25G_PDEC_QDI1 << 16) | MUX_PA25G_PDEC_QDI1) +#define PORT_PA25G_PDEC_QDI1 (_UL_(1) << 25) +#define PIN_PB20G_PDEC_QDI2 _L_(52) /**< \brief PDEC signal: QDI2 on PB20 mux G */ +#define MUX_PB20G_PDEC_QDI2 _L_(6) +#define PINMUX_PB20G_PDEC_QDI2 ((PIN_PB20G_PDEC_QDI2 << 16) | MUX_PB20G_PDEC_QDI2) +#define PORT_PB20G_PDEC_QDI2 (_UL_(1) << 20) +#define PIN_PB25G_PDEC_QDI2 _L_(57) /**< \brief PDEC signal: QDI2 on PB25 mux G */ +#define MUX_PB25G_PDEC_QDI2 _L_(6) +#define PINMUX_PB25G_PDEC_QDI2 ((PIN_PB25G_PDEC_QDI2 << 16) | MUX_PB25G_PDEC_QDI2) +#define PORT_PB25G_PDEC_QDI2 (_UL_(1) << 25) +#define PIN_PC18G_PDEC_QDI2 _L_(82) /**< \brief PDEC signal: QDI2 on PC18 mux G */ +#define MUX_PC18G_PDEC_QDI2 _L_(6) +#define PINMUX_PC18G_PDEC_QDI2 ((PIN_PC18G_PDEC_QDI2 << 16) | MUX_PC18G_PDEC_QDI2) +#define PORT_PC18G_PDEC_QDI2 (_UL_(1) << 18) +#define PIN_PB22G_PDEC_QDI2 _L_(54) /**< \brief PDEC signal: QDI2 on PB22 mux G */ +#define MUX_PB22G_PDEC_QDI2 _L_(6) +#define PINMUX_PB22G_PDEC_QDI2 ((PIN_PB22G_PDEC_QDI2 << 16) | MUX_PB22G_PDEC_QDI2) +#define PORT_PB22G_PDEC_QDI2 (_UL_(1) << 22) +/* ========== PORT definition for AC peripheral ========== */ +#define PIN_PA04B_AC_AIN0 _L_(4) /**< \brief AC signal: AIN0 on PA04 mux B */ +#define MUX_PA04B_AC_AIN0 _L_(1) +#define PINMUX_PA04B_AC_AIN0 ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0) +#define PORT_PA04B_AC_AIN0 (_UL_(1) << 4) +#define PIN_PA05B_AC_AIN1 _L_(5) /**< \brief AC signal: AIN1 on PA05 mux B */ +#define MUX_PA05B_AC_AIN1 _L_(1) +#define PINMUX_PA05B_AC_AIN1 ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1) +#define PORT_PA05B_AC_AIN1 (_UL_(1) << 5) +#define PIN_PA06B_AC_AIN2 _L_(6) /**< \brief AC signal: AIN2 on PA06 mux B */ +#define MUX_PA06B_AC_AIN2 _L_(1) +#define PINMUX_PA06B_AC_AIN2 ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2) +#define PORT_PA06B_AC_AIN2 (_UL_(1) << 6) +#define PIN_PA07B_AC_AIN3 _L_(7) /**< \brief AC signal: AIN3 on PA07 mux B */ +#define MUX_PA07B_AC_AIN3 _L_(1) +#define PINMUX_PA07B_AC_AIN3 ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3) +#define PORT_PA07B_AC_AIN3 (_UL_(1) << 7) +#define PIN_PA12M_AC_CMP0 _L_(12) /**< \brief AC signal: CMP0 on PA12 mux M */ +#define MUX_PA12M_AC_CMP0 _L_(12) +#define PINMUX_PA12M_AC_CMP0 ((PIN_PA12M_AC_CMP0 << 16) | MUX_PA12M_AC_CMP0) +#define PORT_PA12M_AC_CMP0 (_UL_(1) << 12) +#define PIN_PA18M_AC_CMP0 _L_(18) /**< \brief AC signal: CMP0 on PA18 mux M */ +#define MUX_PA18M_AC_CMP0 _L_(12) +#define PINMUX_PA18M_AC_CMP0 ((PIN_PA18M_AC_CMP0 << 16) | MUX_PA18M_AC_CMP0) +#define PORT_PA18M_AC_CMP0 (_UL_(1) << 18) +#define PIN_PB24M_AC_CMP0 _L_(56) /**< \brief AC signal: CMP0 on PB24 mux M */ +#define MUX_PB24M_AC_CMP0 _L_(12) +#define PINMUX_PB24M_AC_CMP0 ((PIN_PB24M_AC_CMP0 << 16) | MUX_PB24M_AC_CMP0) +#define PORT_PB24M_AC_CMP0 (_UL_(1) << 24) +#define PIN_PA13M_AC_CMP1 _L_(13) /**< \brief AC signal: CMP1 on PA13 mux M */ +#define MUX_PA13M_AC_CMP1 _L_(12) +#define PINMUX_PA13M_AC_CMP1 ((PIN_PA13M_AC_CMP1 << 16) | MUX_PA13M_AC_CMP1) +#define PORT_PA13M_AC_CMP1 (_UL_(1) << 13) +#define PIN_PA19M_AC_CMP1 _L_(19) /**< \brief AC signal: CMP1 on PA19 mux M */ +#define MUX_PA19M_AC_CMP1 _L_(12) +#define PINMUX_PA19M_AC_CMP1 ((PIN_PA19M_AC_CMP1 << 16) | MUX_PA19M_AC_CMP1) +#define PORT_PA19M_AC_CMP1 (_UL_(1) << 19) +#define PIN_PB25M_AC_CMP1 _L_(57) /**< \brief AC signal: CMP1 on PB25 mux M */ +#define MUX_PB25M_AC_CMP1 _L_(12) +#define PINMUX_PB25M_AC_CMP1 ((PIN_PB25M_AC_CMP1 << 16) | MUX_PB25M_AC_CMP1) +#define PORT_PB25M_AC_CMP1 (_UL_(1) << 25) +/* ========== PORT definition for QSPI peripheral ========== */ +#define PIN_PB11H_QSPI_CS _L_(43) /**< \brief QSPI signal: CS on PB11 mux H */ +#define MUX_PB11H_QSPI_CS _L_(7) +#define PINMUX_PB11H_QSPI_CS ((PIN_PB11H_QSPI_CS << 16) | MUX_PB11H_QSPI_CS) +#define PORT_PB11H_QSPI_CS (_UL_(1) << 11) +#define PIN_PA08H_QSPI_DATA0 _L_(8) /**< \brief QSPI signal: DATA0 on PA08 mux H */ +#define MUX_PA08H_QSPI_DATA0 _L_(7) +#define PINMUX_PA08H_QSPI_DATA0 ((PIN_PA08H_QSPI_DATA0 << 16) | MUX_PA08H_QSPI_DATA0) +#define PORT_PA08H_QSPI_DATA0 (_UL_(1) << 8) +#define PIN_PA09H_QSPI_DATA1 _L_(9) /**< \brief QSPI signal: DATA1 on PA09 mux H */ +#define MUX_PA09H_QSPI_DATA1 _L_(7) +#define PINMUX_PA09H_QSPI_DATA1 ((PIN_PA09H_QSPI_DATA1 << 16) | MUX_PA09H_QSPI_DATA1) +#define PORT_PA09H_QSPI_DATA1 (_UL_(1) << 9) +#define PIN_PA10H_QSPI_DATA2 _L_(10) /**< \brief QSPI signal: DATA2 on PA10 mux H */ +#define MUX_PA10H_QSPI_DATA2 _L_(7) +#define PINMUX_PA10H_QSPI_DATA2 ((PIN_PA10H_QSPI_DATA2 << 16) | MUX_PA10H_QSPI_DATA2) +#define PORT_PA10H_QSPI_DATA2 (_UL_(1) << 10) +#define PIN_PA11H_QSPI_DATA3 _L_(11) /**< \brief QSPI signal: DATA3 on PA11 mux H */ +#define MUX_PA11H_QSPI_DATA3 _L_(7) +#define PINMUX_PA11H_QSPI_DATA3 ((PIN_PA11H_QSPI_DATA3 << 16) | MUX_PA11H_QSPI_DATA3) +#define PORT_PA11H_QSPI_DATA3 (_UL_(1) << 11) +#define PIN_PB10H_QSPI_SCK _L_(42) /**< \brief QSPI signal: SCK on PB10 mux H */ +#define MUX_PB10H_QSPI_SCK _L_(7) +#define PINMUX_PB10H_QSPI_SCK ((PIN_PB10H_QSPI_SCK << 16) | MUX_PB10H_QSPI_SCK) +#define PORT_PB10H_QSPI_SCK (_UL_(1) << 10) +/* ========== PORT definition for CCL peripheral ========== */ +#define PIN_PA04N_CCL_IN0 _L_(4) /**< \brief CCL signal: IN0 on PA04 mux N */ +#define MUX_PA04N_CCL_IN0 _L_(13) +#define PINMUX_PA04N_CCL_IN0 ((PIN_PA04N_CCL_IN0 << 16) | MUX_PA04N_CCL_IN0) +#define PORT_PA04N_CCL_IN0 (_UL_(1) << 4) +#define PIN_PA16N_CCL_IN0 _L_(16) /**< \brief CCL signal: IN0 on PA16 mux N */ +#define MUX_PA16N_CCL_IN0 _L_(13) +#define PINMUX_PA16N_CCL_IN0 ((PIN_PA16N_CCL_IN0 << 16) | MUX_PA16N_CCL_IN0) +#define PORT_PA16N_CCL_IN0 (_UL_(1) << 16) +#define PIN_PB22N_CCL_IN0 _L_(54) /**< \brief CCL signal: IN0 on PB22 mux N */ +#define MUX_PB22N_CCL_IN0 _L_(13) +#define PINMUX_PB22N_CCL_IN0 ((PIN_PB22N_CCL_IN0 << 16) | MUX_PB22N_CCL_IN0) +#define PORT_PB22N_CCL_IN0 (_UL_(1) << 22) +#define PIN_PA05N_CCL_IN1 _L_(5) /**< \brief CCL signal: IN1 on PA05 mux N */ +#define MUX_PA05N_CCL_IN1 _L_(13) +#define PINMUX_PA05N_CCL_IN1 ((PIN_PA05N_CCL_IN1 << 16) | MUX_PA05N_CCL_IN1) +#define PORT_PA05N_CCL_IN1 (_UL_(1) << 5) +#define PIN_PA17N_CCL_IN1 _L_(17) /**< \brief CCL signal: IN1 on PA17 mux N */ +#define MUX_PA17N_CCL_IN1 _L_(13) +#define PINMUX_PA17N_CCL_IN1 ((PIN_PA17N_CCL_IN1 << 16) | MUX_PA17N_CCL_IN1) +#define PORT_PA17N_CCL_IN1 (_UL_(1) << 17) +#define PIN_PB00N_CCL_IN1 _L_(32) /**< \brief CCL signal: IN1 on PB00 mux N */ +#define MUX_PB00N_CCL_IN1 _L_(13) +#define PINMUX_PB00N_CCL_IN1 ((PIN_PB00N_CCL_IN1 << 16) | MUX_PB00N_CCL_IN1) +#define PORT_PB00N_CCL_IN1 (_UL_(1) << 0) +#define PIN_PA06N_CCL_IN2 _L_(6) /**< \brief CCL signal: IN2 on PA06 mux N */ +#define MUX_PA06N_CCL_IN2 _L_(13) +#define PINMUX_PA06N_CCL_IN2 ((PIN_PA06N_CCL_IN2 << 16) | MUX_PA06N_CCL_IN2) +#define PORT_PA06N_CCL_IN2 (_UL_(1) << 6) +#define PIN_PA18N_CCL_IN2 _L_(18) /**< \brief CCL signal: IN2 on PA18 mux N */ +#define MUX_PA18N_CCL_IN2 _L_(13) +#define PINMUX_PA18N_CCL_IN2 ((PIN_PA18N_CCL_IN2 << 16) | MUX_PA18N_CCL_IN2) +#define PORT_PA18N_CCL_IN2 (_UL_(1) << 18) +#define PIN_PB01N_CCL_IN2 _L_(33) /**< \brief CCL signal: IN2 on PB01 mux N */ +#define MUX_PB01N_CCL_IN2 _L_(13) +#define PINMUX_PB01N_CCL_IN2 ((PIN_PB01N_CCL_IN2 << 16) | MUX_PB01N_CCL_IN2) +#define PORT_PB01N_CCL_IN2 (_UL_(1) << 1) +#define PIN_PA08N_CCL_IN3 _L_(8) /**< \brief CCL signal: IN3 on PA08 mux N */ +#define MUX_PA08N_CCL_IN3 _L_(13) +#define PINMUX_PA08N_CCL_IN3 ((PIN_PA08N_CCL_IN3 << 16) | MUX_PA08N_CCL_IN3) +#define PORT_PA08N_CCL_IN3 (_UL_(1) << 8) +#define PIN_PA30N_CCL_IN3 _L_(30) /**< \brief CCL signal: IN3 on PA30 mux N */ +#define MUX_PA30N_CCL_IN3 _L_(13) +#define PINMUX_PA30N_CCL_IN3 ((PIN_PA30N_CCL_IN3 << 16) | MUX_PA30N_CCL_IN3) +#define PORT_PA30N_CCL_IN3 (_UL_(1) << 30) +#define PIN_PA09N_CCL_IN4 _L_(9) /**< \brief CCL signal: IN4 on PA09 mux N */ +#define MUX_PA09N_CCL_IN4 _L_(13) +#define PINMUX_PA09N_CCL_IN4 ((PIN_PA09N_CCL_IN4 << 16) | MUX_PA09N_CCL_IN4) +#define PORT_PA09N_CCL_IN4 (_UL_(1) << 9) +#define PIN_PC27N_CCL_IN4 _L_(91) /**< \brief CCL signal: IN4 on PC27 mux N */ +#define MUX_PC27N_CCL_IN4 _L_(13) +#define PINMUX_PC27N_CCL_IN4 ((PIN_PC27N_CCL_IN4 << 16) | MUX_PC27N_CCL_IN4) +#define PORT_PC27N_CCL_IN4 (_UL_(1) << 27) +#define PIN_PA10N_CCL_IN5 _L_(10) /**< \brief CCL signal: IN5 on PA10 mux N */ +#define MUX_PA10N_CCL_IN5 _L_(13) +#define PINMUX_PA10N_CCL_IN5 ((PIN_PA10N_CCL_IN5 << 16) | MUX_PA10N_CCL_IN5) +#define PORT_PA10N_CCL_IN5 (_UL_(1) << 10) +#define PIN_PC28N_CCL_IN5 _L_(92) /**< \brief CCL signal: IN5 on PC28 mux N */ +#define MUX_PC28N_CCL_IN5 _L_(13) +#define PINMUX_PC28N_CCL_IN5 ((PIN_PC28N_CCL_IN5 << 16) | MUX_PC28N_CCL_IN5) +#define PORT_PC28N_CCL_IN5 (_UL_(1) << 28) +#define PIN_PA22N_CCL_IN6 _L_(22) /**< \brief CCL signal: IN6 on PA22 mux N */ +#define MUX_PA22N_CCL_IN6 _L_(13) +#define PINMUX_PA22N_CCL_IN6 ((PIN_PA22N_CCL_IN6 << 16) | MUX_PA22N_CCL_IN6) +#define PORT_PA22N_CCL_IN6 (_UL_(1) << 22) +#define PIN_PB06N_CCL_IN6 _L_(38) /**< \brief CCL signal: IN6 on PB06 mux N */ +#define MUX_PB06N_CCL_IN6 _L_(13) +#define PINMUX_PB06N_CCL_IN6 ((PIN_PB06N_CCL_IN6 << 16) | MUX_PB06N_CCL_IN6) +#define PORT_PB06N_CCL_IN6 (_UL_(1) << 6) +#define PIN_PA23N_CCL_IN7 _L_(23) /**< \brief CCL signal: IN7 on PA23 mux N */ +#define MUX_PA23N_CCL_IN7 _L_(13) +#define PINMUX_PA23N_CCL_IN7 ((PIN_PA23N_CCL_IN7 << 16) | MUX_PA23N_CCL_IN7) +#define PORT_PA23N_CCL_IN7 (_UL_(1) << 23) +#define PIN_PB07N_CCL_IN7 _L_(39) /**< \brief CCL signal: IN7 on PB07 mux N */ +#define MUX_PB07N_CCL_IN7 _L_(13) +#define PINMUX_PB07N_CCL_IN7 ((PIN_PB07N_CCL_IN7 << 16) | MUX_PB07N_CCL_IN7) +#define PORT_PB07N_CCL_IN7 (_UL_(1) << 7) +#define PIN_PA24N_CCL_IN8 _L_(24) /**< \brief CCL signal: IN8 on PA24 mux N */ +#define MUX_PA24N_CCL_IN8 _L_(13) +#define PINMUX_PA24N_CCL_IN8 ((PIN_PA24N_CCL_IN8 << 16) | MUX_PA24N_CCL_IN8) +#define PORT_PA24N_CCL_IN8 (_UL_(1) << 24) +#define PIN_PB08N_CCL_IN8 _L_(40) /**< \brief CCL signal: IN8 on PB08 mux N */ +#define MUX_PB08N_CCL_IN8 _L_(13) +#define PINMUX_PB08N_CCL_IN8 ((PIN_PB08N_CCL_IN8 << 16) | MUX_PB08N_CCL_IN8) +#define PORT_PB08N_CCL_IN8 (_UL_(1) << 8) +#define PIN_PB14N_CCL_IN9 _L_(46) /**< \brief CCL signal: IN9 on PB14 mux N */ +#define MUX_PB14N_CCL_IN9 _L_(13) +#define PINMUX_PB14N_CCL_IN9 ((PIN_PB14N_CCL_IN9 << 16) | MUX_PB14N_CCL_IN9) +#define PORT_PB14N_CCL_IN9 (_UL_(1) << 14) +#define PIN_PC20N_CCL_IN9 _L_(84) /**< \brief CCL signal: IN9 on PC20 mux N */ +#define MUX_PC20N_CCL_IN9 _L_(13) +#define PINMUX_PC20N_CCL_IN9 ((PIN_PC20N_CCL_IN9 << 16) | MUX_PC20N_CCL_IN9) +#define PORT_PC20N_CCL_IN9 (_UL_(1) << 20) +#define PIN_PB15N_CCL_IN10 _L_(47) /**< \brief CCL signal: IN10 on PB15 mux N */ +#define MUX_PB15N_CCL_IN10 _L_(13) +#define PINMUX_PB15N_CCL_IN10 ((PIN_PB15N_CCL_IN10 << 16) | MUX_PB15N_CCL_IN10) +#define PORT_PB15N_CCL_IN10 (_UL_(1) << 15) +#define PIN_PC21N_CCL_IN10 _L_(85) /**< \brief CCL signal: IN10 on PC21 mux N */ +#define MUX_PC21N_CCL_IN10 _L_(13) +#define PINMUX_PC21N_CCL_IN10 ((PIN_PC21N_CCL_IN10 << 16) | MUX_PC21N_CCL_IN10) +#define PORT_PC21N_CCL_IN10 (_UL_(1) << 21) +#define PIN_PB10N_CCL_IN11 _L_(42) /**< \brief CCL signal: IN11 on PB10 mux N */ +#define MUX_PB10N_CCL_IN11 _L_(13) +#define PINMUX_PB10N_CCL_IN11 ((PIN_PB10N_CCL_IN11 << 16) | MUX_PB10N_CCL_IN11) +#define PORT_PB10N_CCL_IN11 (_UL_(1) << 10) +#define PIN_PB16N_CCL_IN11 _L_(48) /**< \brief CCL signal: IN11 on PB16 mux N */ +#define MUX_PB16N_CCL_IN11 _L_(13) +#define PINMUX_PB16N_CCL_IN11 ((PIN_PB16N_CCL_IN11 << 16) | MUX_PB16N_CCL_IN11) +#define PORT_PB16N_CCL_IN11 (_UL_(1) << 16) +#define PIN_PA07N_CCL_OUT0 _L_(7) /**< \brief CCL signal: OUT0 on PA07 mux N */ +#define MUX_PA07N_CCL_OUT0 _L_(13) +#define PINMUX_PA07N_CCL_OUT0 ((PIN_PA07N_CCL_OUT0 << 16) | MUX_PA07N_CCL_OUT0) +#define PORT_PA07N_CCL_OUT0 (_UL_(1) << 7) +#define PIN_PA19N_CCL_OUT0 _L_(19) /**< \brief CCL signal: OUT0 on PA19 mux N */ +#define MUX_PA19N_CCL_OUT0 _L_(13) +#define PINMUX_PA19N_CCL_OUT0 ((PIN_PA19N_CCL_OUT0 << 16) | MUX_PA19N_CCL_OUT0) +#define PORT_PA19N_CCL_OUT0 (_UL_(1) << 19) +#define PIN_PB02N_CCL_OUT0 _L_(34) /**< \brief CCL signal: OUT0 on PB02 mux N */ +#define MUX_PB02N_CCL_OUT0 _L_(13) +#define PINMUX_PB02N_CCL_OUT0 ((PIN_PB02N_CCL_OUT0 << 16) | MUX_PB02N_CCL_OUT0) +#define PORT_PB02N_CCL_OUT0 (_UL_(1) << 2) +#define PIN_PB23N_CCL_OUT0 _L_(55) /**< \brief CCL signal: OUT0 on PB23 mux N */ +#define MUX_PB23N_CCL_OUT0 _L_(13) +#define PINMUX_PB23N_CCL_OUT0 ((PIN_PB23N_CCL_OUT0 << 16) | MUX_PB23N_CCL_OUT0) +#define PORT_PB23N_CCL_OUT0 (_UL_(1) << 23) +#define PIN_PA11N_CCL_OUT1 _L_(11) /**< \brief CCL signal: OUT1 on PA11 mux N */ +#define MUX_PA11N_CCL_OUT1 _L_(13) +#define PINMUX_PA11N_CCL_OUT1 ((PIN_PA11N_CCL_OUT1 << 16) | MUX_PA11N_CCL_OUT1) +#define PORT_PA11N_CCL_OUT1 (_UL_(1) << 11) +#define PIN_PA31N_CCL_OUT1 _L_(31) /**< \brief CCL signal: OUT1 on PA31 mux N */ +#define MUX_PA31N_CCL_OUT1 _L_(13) +#define PINMUX_PA31N_CCL_OUT1 ((PIN_PA31N_CCL_OUT1 << 16) | MUX_PA31N_CCL_OUT1) +#define PORT_PA31N_CCL_OUT1 (_UL_(1) << 31) +#define PIN_PB11N_CCL_OUT1 _L_(43) /**< \brief CCL signal: OUT1 on PB11 mux N */ +#define MUX_PB11N_CCL_OUT1 _L_(13) +#define PINMUX_PB11N_CCL_OUT1 ((PIN_PB11N_CCL_OUT1 << 16) | MUX_PB11N_CCL_OUT1) +#define PORT_PB11N_CCL_OUT1 (_UL_(1) << 11) +#define PIN_PA25N_CCL_OUT2 _L_(25) /**< \brief CCL signal: OUT2 on PA25 mux N */ +#define MUX_PA25N_CCL_OUT2 _L_(13) +#define PINMUX_PA25N_CCL_OUT2 ((PIN_PA25N_CCL_OUT2 << 16) | MUX_PA25N_CCL_OUT2) +#define PORT_PA25N_CCL_OUT2 (_UL_(1) << 25) +#define PIN_PB09N_CCL_OUT2 _L_(41) /**< \brief CCL signal: OUT2 on PB09 mux N */ +#define MUX_PB09N_CCL_OUT2 _L_(13) +#define PINMUX_PB09N_CCL_OUT2 ((PIN_PB09N_CCL_OUT2 << 16) | MUX_PB09N_CCL_OUT2) +#define PORT_PB09N_CCL_OUT2 (_UL_(1) << 9) +#define PIN_PB17N_CCL_OUT3 _L_(49) /**< \brief CCL signal: OUT3 on PB17 mux N */ +#define MUX_PB17N_CCL_OUT3 _L_(13) +#define PINMUX_PB17N_CCL_OUT3 ((PIN_PB17N_CCL_OUT3 << 16) | MUX_PB17N_CCL_OUT3) +#define PORT_PB17N_CCL_OUT3 (_UL_(1) << 17) +/* ========== PORT definition for SERCOM4 peripheral ========== */ +#define PIN_PA13D_SERCOM4_PAD0 _L_(13) /**< \brief SERCOM4 signal: PAD0 on PA13 mux D */ +#define MUX_PA13D_SERCOM4_PAD0 _L_(3) +#define PINMUX_PA13D_SERCOM4_PAD0 ((PIN_PA13D_SERCOM4_PAD0 << 16) | MUX_PA13D_SERCOM4_PAD0) +#define PORT_PA13D_SERCOM4_PAD0 (_UL_(1) << 13) +#define PIN_PB08D_SERCOM4_PAD0 _L_(40) /**< \brief SERCOM4 signal: PAD0 on PB08 mux D */ +#define MUX_PB08D_SERCOM4_PAD0 _L_(3) +#define PINMUX_PB08D_SERCOM4_PAD0 ((PIN_PB08D_SERCOM4_PAD0 << 16) | MUX_PB08D_SERCOM4_PAD0) +#define PORT_PB08D_SERCOM4_PAD0 (_UL_(1) << 8) +#define PIN_PB27D_SERCOM4_PAD0 _L_(59) /**< \brief SERCOM4 signal: PAD0 on PB27 mux D */ +#define MUX_PB27D_SERCOM4_PAD0 _L_(3) +#define PINMUX_PB27D_SERCOM4_PAD0 ((PIN_PB27D_SERCOM4_PAD0 << 16) | MUX_PB27D_SERCOM4_PAD0) +#define PORT_PB27D_SERCOM4_PAD0 (_UL_(1) << 27) +#define PIN_PB12C_SERCOM4_PAD0 _L_(44) /**< \brief SERCOM4 signal: PAD0 on PB12 mux C */ +#define MUX_PB12C_SERCOM4_PAD0 _L_(2) +#define PINMUX_PB12C_SERCOM4_PAD0 ((PIN_PB12C_SERCOM4_PAD0 << 16) | MUX_PB12C_SERCOM4_PAD0) +#define PORT_PB12C_SERCOM4_PAD0 (_UL_(1) << 12) +#define PIN_PA12D_SERCOM4_PAD1 _L_(12) /**< \brief SERCOM4 signal: PAD1 on PA12 mux D */ +#define MUX_PA12D_SERCOM4_PAD1 _L_(3) +#define PINMUX_PA12D_SERCOM4_PAD1 ((PIN_PA12D_SERCOM4_PAD1 << 16) | MUX_PA12D_SERCOM4_PAD1) +#define PORT_PA12D_SERCOM4_PAD1 (_UL_(1) << 12) +#define PIN_PB09D_SERCOM4_PAD1 _L_(41) /**< \brief SERCOM4 signal: PAD1 on PB09 mux D */ +#define MUX_PB09D_SERCOM4_PAD1 _L_(3) +#define PINMUX_PB09D_SERCOM4_PAD1 ((PIN_PB09D_SERCOM4_PAD1 << 16) | MUX_PB09D_SERCOM4_PAD1) +#define PORT_PB09D_SERCOM4_PAD1 (_UL_(1) << 9) +#define PIN_PB26D_SERCOM4_PAD1 _L_(58) /**< \brief SERCOM4 signal: PAD1 on PB26 mux D */ +#define MUX_PB26D_SERCOM4_PAD1 _L_(3) +#define PINMUX_PB26D_SERCOM4_PAD1 ((PIN_PB26D_SERCOM4_PAD1 << 16) | MUX_PB26D_SERCOM4_PAD1) +#define PORT_PB26D_SERCOM4_PAD1 (_UL_(1) << 26) +#define PIN_PB13C_SERCOM4_PAD1 _L_(45) /**< \brief SERCOM4 signal: PAD1 on PB13 mux C */ +#define MUX_PB13C_SERCOM4_PAD1 _L_(2) +#define PINMUX_PB13C_SERCOM4_PAD1 ((PIN_PB13C_SERCOM4_PAD1 << 16) | MUX_PB13C_SERCOM4_PAD1) +#define PORT_PB13C_SERCOM4_PAD1 (_UL_(1) << 13) +#define PIN_PA14D_SERCOM4_PAD2 _L_(14) /**< \brief SERCOM4 signal: PAD2 on PA14 mux D */ +#define MUX_PA14D_SERCOM4_PAD2 _L_(3) +#define PINMUX_PA14D_SERCOM4_PAD2 ((PIN_PA14D_SERCOM4_PAD2 << 16) | MUX_PA14D_SERCOM4_PAD2) +#define PORT_PA14D_SERCOM4_PAD2 (_UL_(1) << 14) +#define PIN_PB10D_SERCOM4_PAD2 _L_(42) /**< \brief SERCOM4 signal: PAD2 on PB10 mux D */ +#define MUX_PB10D_SERCOM4_PAD2 _L_(3) +#define PINMUX_PB10D_SERCOM4_PAD2 ((PIN_PB10D_SERCOM4_PAD2 << 16) | MUX_PB10D_SERCOM4_PAD2) +#define PORT_PB10D_SERCOM4_PAD2 (_UL_(1) << 10) +#define PIN_PB28D_SERCOM4_PAD2 _L_(60) /**< \brief SERCOM4 signal: PAD2 on PB28 mux D */ +#define MUX_PB28D_SERCOM4_PAD2 _L_(3) +#define PINMUX_PB28D_SERCOM4_PAD2 ((PIN_PB28D_SERCOM4_PAD2 << 16) | MUX_PB28D_SERCOM4_PAD2) +#define PORT_PB28D_SERCOM4_PAD2 (_UL_(1) << 28) +#define PIN_PB14C_SERCOM4_PAD2 _L_(46) /**< \brief SERCOM4 signal: PAD2 on PB14 mux C */ +#define MUX_PB14C_SERCOM4_PAD2 _L_(2) +#define PINMUX_PB14C_SERCOM4_PAD2 ((PIN_PB14C_SERCOM4_PAD2 << 16) | MUX_PB14C_SERCOM4_PAD2) +#define PORT_PB14C_SERCOM4_PAD2 (_UL_(1) << 14) +#define PIN_PB11D_SERCOM4_PAD3 _L_(43) /**< \brief SERCOM4 signal: PAD3 on PB11 mux D */ +#define MUX_PB11D_SERCOM4_PAD3 _L_(3) +#define PINMUX_PB11D_SERCOM4_PAD3 ((PIN_PB11D_SERCOM4_PAD3 << 16) | MUX_PB11D_SERCOM4_PAD3) +#define PORT_PB11D_SERCOM4_PAD3 (_UL_(1) << 11) +#define PIN_PB29D_SERCOM4_PAD3 _L_(61) /**< \brief SERCOM4 signal: PAD3 on PB29 mux D */ +#define MUX_PB29D_SERCOM4_PAD3 _L_(3) +#define PINMUX_PB29D_SERCOM4_PAD3 ((PIN_PB29D_SERCOM4_PAD3 << 16) | MUX_PB29D_SERCOM4_PAD3) +#define PORT_PB29D_SERCOM4_PAD3 (_UL_(1) << 29) +#define PIN_PA15D_SERCOM4_PAD3 _L_(15) /**< \brief SERCOM4 signal: PAD3 on PA15 mux D */ +#define MUX_PA15D_SERCOM4_PAD3 _L_(3) +#define PINMUX_PA15D_SERCOM4_PAD3 ((PIN_PA15D_SERCOM4_PAD3 << 16) | MUX_PA15D_SERCOM4_PAD3) +#define PORT_PA15D_SERCOM4_PAD3 (_UL_(1) << 15) +#define PIN_PB15C_SERCOM4_PAD3 _L_(47) /**< \brief SERCOM4 signal: PAD3 on PB15 mux C */ +#define MUX_PB15C_SERCOM4_PAD3 _L_(2) +#define PINMUX_PB15C_SERCOM4_PAD3 ((PIN_PB15C_SERCOM4_PAD3 << 16) | MUX_PB15C_SERCOM4_PAD3) +#define PORT_PB15C_SERCOM4_PAD3 (_UL_(1) << 15) +/* ========== PORT definition for SERCOM5 peripheral ========== */ +#define PIN_PA23D_SERCOM5_PAD0 _L_(23) /**< \brief SERCOM5 signal: PAD0 on PA23 mux D */ +#define MUX_PA23D_SERCOM5_PAD0 _L_(3) +#define PINMUX_PA23D_SERCOM5_PAD0 ((PIN_PA23D_SERCOM5_PAD0 << 16) | MUX_PA23D_SERCOM5_PAD0) +#define PORT_PA23D_SERCOM5_PAD0 (_UL_(1) << 23) +#define PIN_PB02D_SERCOM5_PAD0 _L_(34) /**< \brief SERCOM5 signal: PAD0 on PB02 mux D */ +#define MUX_PB02D_SERCOM5_PAD0 _L_(3) +#define PINMUX_PB02D_SERCOM5_PAD0 ((PIN_PB02D_SERCOM5_PAD0 << 16) | MUX_PB02D_SERCOM5_PAD0) +#define PORT_PB02D_SERCOM5_PAD0 (_UL_(1) << 2) +#define PIN_PB31D_SERCOM5_PAD0 _L_(63) /**< \brief SERCOM5 signal: PAD0 on PB31 mux D */ +#define MUX_PB31D_SERCOM5_PAD0 _L_(3) +#define PINMUX_PB31D_SERCOM5_PAD0 ((PIN_PB31D_SERCOM5_PAD0 << 16) | MUX_PB31D_SERCOM5_PAD0) +#define PORT_PB31D_SERCOM5_PAD0 (_UL_(1) << 31) +#define PIN_PB16C_SERCOM5_PAD0 _L_(48) /**< \brief SERCOM5 signal: PAD0 on PB16 mux C */ +#define MUX_PB16C_SERCOM5_PAD0 _L_(2) +#define PINMUX_PB16C_SERCOM5_PAD0 ((PIN_PB16C_SERCOM5_PAD0 << 16) | MUX_PB16C_SERCOM5_PAD0) +#define PORT_PB16C_SERCOM5_PAD0 (_UL_(1) << 16) +#define PIN_PA22D_SERCOM5_PAD1 _L_(22) /**< \brief SERCOM5 signal: PAD1 on PA22 mux D */ +#define MUX_PA22D_SERCOM5_PAD1 _L_(3) +#define PINMUX_PA22D_SERCOM5_PAD1 ((PIN_PA22D_SERCOM5_PAD1 << 16) | MUX_PA22D_SERCOM5_PAD1) +#define PORT_PA22D_SERCOM5_PAD1 (_UL_(1) << 22) +#define PIN_PB03D_SERCOM5_PAD1 _L_(35) /**< \brief SERCOM5 signal: PAD1 on PB03 mux D */ +#define MUX_PB03D_SERCOM5_PAD1 _L_(3) +#define PINMUX_PB03D_SERCOM5_PAD1 ((PIN_PB03D_SERCOM5_PAD1 << 16) | MUX_PB03D_SERCOM5_PAD1) +#define PORT_PB03D_SERCOM5_PAD1 (_UL_(1) << 3) +#define PIN_PB30D_SERCOM5_PAD1 _L_(62) /**< \brief SERCOM5 signal: PAD1 on PB30 mux D */ +#define MUX_PB30D_SERCOM5_PAD1 _L_(3) +#define PINMUX_PB30D_SERCOM5_PAD1 ((PIN_PB30D_SERCOM5_PAD1 << 16) | MUX_PB30D_SERCOM5_PAD1) +#define PORT_PB30D_SERCOM5_PAD1 (_UL_(1) << 30) +#define PIN_PB17C_SERCOM5_PAD1 _L_(49) /**< \brief SERCOM5 signal: PAD1 on PB17 mux C */ +#define MUX_PB17C_SERCOM5_PAD1 _L_(2) +#define PINMUX_PB17C_SERCOM5_PAD1 ((PIN_PB17C_SERCOM5_PAD1 << 16) | MUX_PB17C_SERCOM5_PAD1) +#define PORT_PB17C_SERCOM5_PAD1 (_UL_(1) << 17) +#define PIN_PA24D_SERCOM5_PAD2 _L_(24) /**< \brief SERCOM5 signal: PAD2 on PA24 mux D */ +#define MUX_PA24D_SERCOM5_PAD2 _L_(3) +#define PINMUX_PA24D_SERCOM5_PAD2 ((PIN_PA24D_SERCOM5_PAD2 << 16) | MUX_PA24D_SERCOM5_PAD2) +#define PORT_PA24D_SERCOM5_PAD2 (_UL_(1) << 24) +#define PIN_PB00D_SERCOM5_PAD2 _L_(32) /**< \brief SERCOM5 signal: PAD2 on PB00 mux D */ +#define MUX_PB00D_SERCOM5_PAD2 _L_(3) +#define PINMUX_PB00D_SERCOM5_PAD2 ((PIN_PB00D_SERCOM5_PAD2 << 16) | MUX_PB00D_SERCOM5_PAD2) +#define PORT_PB00D_SERCOM5_PAD2 (_UL_(1) << 0) +#define PIN_PB22D_SERCOM5_PAD2 _L_(54) /**< \brief SERCOM5 signal: PAD2 on PB22 mux D */ +#define MUX_PB22D_SERCOM5_PAD2 _L_(3) +#define PINMUX_PB22D_SERCOM5_PAD2 ((PIN_PB22D_SERCOM5_PAD2 << 16) | MUX_PB22D_SERCOM5_PAD2) +#define PORT_PB22D_SERCOM5_PAD2 (_UL_(1) << 22) +#define PIN_PA20C_SERCOM5_PAD2 _L_(20) /**< \brief SERCOM5 signal: PAD2 on PA20 mux C */ +#define MUX_PA20C_SERCOM5_PAD2 _L_(2) +#define PINMUX_PA20C_SERCOM5_PAD2 ((PIN_PA20C_SERCOM5_PAD2 << 16) | MUX_PA20C_SERCOM5_PAD2) +#define PORT_PA20C_SERCOM5_PAD2 (_UL_(1) << 20) +#define PIN_PB18C_SERCOM5_PAD2 _L_(50) /**< \brief SERCOM5 signal: PAD2 on PB18 mux C */ +#define MUX_PB18C_SERCOM5_PAD2 _L_(2) +#define PINMUX_PB18C_SERCOM5_PAD2 ((PIN_PB18C_SERCOM5_PAD2 << 16) | MUX_PB18C_SERCOM5_PAD2) +#define PORT_PB18C_SERCOM5_PAD2 (_UL_(1) << 18) +#define PIN_PA25D_SERCOM5_PAD3 _L_(25) /**< \brief SERCOM5 signal: PAD3 on PA25 mux D */ +#define MUX_PA25D_SERCOM5_PAD3 _L_(3) +#define PINMUX_PA25D_SERCOM5_PAD3 ((PIN_PA25D_SERCOM5_PAD3 << 16) | MUX_PA25D_SERCOM5_PAD3) +#define PORT_PA25D_SERCOM5_PAD3 (_UL_(1) << 25) +#define PIN_PB01D_SERCOM5_PAD3 _L_(33) /**< \brief SERCOM5 signal: PAD3 on PB01 mux D */ +#define MUX_PB01D_SERCOM5_PAD3 _L_(3) +#define PINMUX_PB01D_SERCOM5_PAD3 ((PIN_PB01D_SERCOM5_PAD3 << 16) | MUX_PB01D_SERCOM5_PAD3) +#define PORT_PB01D_SERCOM5_PAD3 (_UL_(1) << 1) +#define PIN_PB23D_SERCOM5_PAD3 _L_(55) /**< \brief SERCOM5 signal: PAD3 on PB23 mux D */ +#define MUX_PB23D_SERCOM5_PAD3 _L_(3) +#define PINMUX_PB23D_SERCOM5_PAD3 ((PIN_PB23D_SERCOM5_PAD3 << 16) | MUX_PB23D_SERCOM5_PAD3) +#define PORT_PB23D_SERCOM5_PAD3 (_UL_(1) << 23) +#define PIN_PA21C_SERCOM5_PAD3 _L_(21) /**< \brief SERCOM5 signal: PAD3 on PA21 mux C */ +#define MUX_PA21C_SERCOM5_PAD3 _L_(2) +#define PINMUX_PA21C_SERCOM5_PAD3 ((PIN_PA21C_SERCOM5_PAD3 << 16) | MUX_PA21C_SERCOM5_PAD3) +#define PORT_PA21C_SERCOM5_PAD3 (_UL_(1) << 21) +#define PIN_PB19C_SERCOM5_PAD3 _L_(51) /**< \brief SERCOM5 signal: PAD3 on PB19 mux C */ +#define MUX_PB19C_SERCOM5_PAD3 _L_(2) +#define PINMUX_PB19C_SERCOM5_PAD3 ((PIN_PB19C_SERCOM5_PAD3 << 16) | MUX_PB19C_SERCOM5_PAD3) +#define PORT_PB19C_SERCOM5_PAD3 (_UL_(1) << 19) +/* ========== PORT definition for SERCOM6 peripheral ========== */ +#define PIN_PD09D_SERCOM6_PAD0 _L_(105) /**< \brief SERCOM6 signal: PAD0 on PD09 mux D */ +#define MUX_PD09D_SERCOM6_PAD0 _L_(3) +#define PINMUX_PD09D_SERCOM6_PAD0 ((PIN_PD09D_SERCOM6_PAD0 << 16) | MUX_PD09D_SERCOM6_PAD0) +#define PORT_PD09D_SERCOM6_PAD0 (_UL_(1) << 9) +#define PIN_PC13D_SERCOM6_PAD0 _L_(77) /**< \brief SERCOM6 signal: PAD0 on PC13 mux D */ +#define MUX_PC13D_SERCOM6_PAD0 _L_(3) +#define PINMUX_PC13D_SERCOM6_PAD0 ((PIN_PC13D_SERCOM6_PAD0 << 16) | MUX_PC13D_SERCOM6_PAD0) +#define PORT_PC13D_SERCOM6_PAD0 (_UL_(1) << 13) +#define PIN_PC04C_SERCOM6_PAD0 _L_(68) /**< \brief SERCOM6 signal: PAD0 on PC04 mux C */ +#define MUX_PC04C_SERCOM6_PAD0 _L_(2) +#define PINMUX_PC04C_SERCOM6_PAD0 ((PIN_PC04C_SERCOM6_PAD0 << 16) | MUX_PC04C_SERCOM6_PAD0) +#define PORT_PC04C_SERCOM6_PAD0 (_UL_(1) << 4) +#define PIN_PC16C_SERCOM6_PAD0 _L_(80) /**< \brief SERCOM6 signal: PAD0 on PC16 mux C */ +#define MUX_PC16C_SERCOM6_PAD0 _L_(2) +#define PINMUX_PC16C_SERCOM6_PAD0 ((PIN_PC16C_SERCOM6_PAD0 << 16) | MUX_PC16C_SERCOM6_PAD0) +#define PORT_PC16C_SERCOM6_PAD0 (_UL_(1) << 16) +#define PIN_PD08D_SERCOM6_PAD1 _L_(104) /**< \brief SERCOM6 signal: PAD1 on PD08 mux D */ +#define MUX_PD08D_SERCOM6_PAD1 _L_(3) +#define PINMUX_PD08D_SERCOM6_PAD1 ((PIN_PD08D_SERCOM6_PAD1 << 16) | MUX_PD08D_SERCOM6_PAD1) +#define PORT_PD08D_SERCOM6_PAD1 (_UL_(1) << 8) +#define PIN_PC12D_SERCOM6_PAD1 _L_(76) /**< \brief SERCOM6 signal: PAD1 on PC12 mux D */ +#define MUX_PC12D_SERCOM6_PAD1 _L_(3) +#define PINMUX_PC12D_SERCOM6_PAD1 ((PIN_PC12D_SERCOM6_PAD1 << 16) | MUX_PC12D_SERCOM6_PAD1) +#define PORT_PC12D_SERCOM6_PAD1 (_UL_(1) << 12) +#define PIN_PC05C_SERCOM6_PAD1 _L_(69) /**< \brief SERCOM6 signal: PAD1 on PC05 mux C */ +#define MUX_PC05C_SERCOM6_PAD1 _L_(2) +#define PINMUX_PC05C_SERCOM6_PAD1 ((PIN_PC05C_SERCOM6_PAD1 << 16) | MUX_PC05C_SERCOM6_PAD1) +#define PORT_PC05C_SERCOM6_PAD1 (_UL_(1) << 5) +#define PIN_PC17C_SERCOM6_PAD1 _L_(81) /**< \brief SERCOM6 signal: PAD1 on PC17 mux C */ +#define MUX_PC17C_SERCOM6_PAD1 _L_(2) +#define PINMUX_PC17C_SERCOM6_PAD1 ((PIN_PC17C_SERCOM6_PAD1 << 16) | MUX_PC17C_SERCOM6_PAD1) +#define PORT_PC17C_SERCOM6_PAD1 (_UL_(1) << 17) +#define PIN_PC14D_SERCOM6_PAD2 _L_(78) /**< \brief SERCOM6 signal: PAD2 on PC14 mux D */ +#define MUX_PC14D_SERCOM6_PAD2 _L_(3) +#define PINMUX_PC14D_SERCOM6_PAD2 ((PIN_PC14D_SERCOM6_PAD2 << 16) | MUX_PC14D_SERCOM6_PAD2) +#define PORT_PC14D_SERCOM6_PAD2 (_UL_(1) << 14) +#define PIN_PD10D_SERCOM6_PAD2 _L_(106) /**< \brief SERCOM6 signal: PAD2 on PD10 mux D */ +#define MUX_PD10D_SERCOM6_PAD2 _L_(3) +#define PINMUX_PD10D_SERCOM6_PAD2 ((PIN_PD10D_SERCOM6_PAD2 << 16) | MUX_PD10D_SERCOM6_PAD2) +#define PORT_PD10D_SERCOM6_PAD2 (_UL_(1) << 10) +#define PIN_PC06C_SERCOM6_PAD2 _L_(70) /**< \brief SERCOM6 signal: PAD2 on PC06 mux C */ +#define MUX_PC06C_SERCOM6_PAD2 _L_(2) +#define PINMUX_PC06C_SERCOM6_PAD2 ((PIN_PC06C_SERCOM6_PAD2 << 16) | MUX_PC06C_SERCOM6_PAD2) +#define PORT_PC06C_SERCOM6_PAD2 (_UL_(1) << 6) +#define PIN_PC10C_SERCOM6_PAD2 _L_(74) /**< \brief SERCOM6 signal: PAD2 on PC10 mux C */ +#define MUX_PC10C_SERCOM6_PAD2 _L_(2) +#define PINMUX_PC10C_SERCOM6_PAD2 ((PIN_PC10C_SERCOM6_PAD2 << 16) | MUX_PC10C_SERCOM6_PAD2) +#define PORT_PC10C_SERCOM6_PAD2 (_UL_(1) << 10) +#define PIN_PC18C_SERCOM6_PAD2 _L_(82) /**< \brief SERCOM6 signal: PAD2 on PC18 mux C */ +#define MUX_PC18C_SERCOM6_PAD2 _L_(2) +#define PINMUX_PC18C_SERCOM6_PAD2 ((PIN_PC18C_SERCOM6_PAD2 << 16) | MUX_PC18C_SERCOM6_PAD2) +#define PORT_PC18C_SERCOM6_PAD2 (_UL_(1) << 18) +#define PIN_PC15D_SERCOM6_PAD3 _L_(79) /**< \brief SERCOM6 signal: PAD3 on PC15 mux D */ +#define MUX_PC15D_SERCOM6_PAD3 _L_(3) +#define PINMUX_PC15D_SERCOM6_PAD3 ((PIN_PC15D_SERCOM6_PAD3 << 16) | MUX_PC15D_SERCOM6_PAD3) +#define PORT_PC15D_SERCOM6_PAD3 (_UL_(1) << 15) +#define PIN_PD11D_SERCOM6_PAD3 _L_(107) /**< \brief SERCOM6 signal: PAD3 on PD11 mux D */ +#define MUX_PD11D_SERCOM6_PAD3 _L_(3) +#define PINMUX_PD11D_SERCOM6_PAD3 ((PIN_PD11D_SERCOM6_PAD3 << 16) | MUX_PD11D_SERCOM6_PAD3) +#define PORT_PD11D_SERCOM6_PAD3 (_UL_(1) << 11) +#define PIN_PC07C_SERCOM6_PAD3 _L_(71) /**< \brief SERCOM6 signal: PAD3 on PC07 mux C */ +#define MUX_PC07C_SERCOM6_PAD3 _L_(2) +#define PINMUX_PC07C_SERCOM6_PAD3 ((PIN_PC07C_SERCOM6_PAD3 << 16) | MUX_PC07C_SERCOM6_PAD3) +#define PORT_PC07C_SERCOM6_PAD3 (_UL_(1) << 7) +#define PIN_PC11C_SERCOM6_PAD3 _L_(75) /**< \brief SERCOM6 signal: PAD3 on PC11 mux C */ +#define MUX_PC11C_SERCOM6_PAD3 _L_(2) +#define PINMUX_PC11C_SERCOM6_PAD3 ((PIN_PC11C_SERCOM6_PAD3 << 16) | MUX_PC11C_SERCOM6_PAD3) +#define PORT_PC11C_SERCOM6_PAD3 (_UL_(1) << 11) +#define PIN_PC19C_SERCOM6_PAD3 _L_(83) /**< \brief SERCOM6 signal: PAD3 on PC19 mux C */ +#define MUX_PC19C_SERCOM6_PAD3 _L_(2) +#define PINMUX_PC19C_SERCOM6_PAD3 ((PIN_PC19C_SERCOM6_PAD3 << 16) | MUX_PC19C_SERCOM6_PAD3) +#define PORT_PC19C_SERCOM6_PAD3 (_UL_(1) << 19) +/* ========== PORT definition for SERCOM7 peripheral ========== */ +#define PIN_PB21D_SERCOM7_PAD0 _L_(53) /**< \brief SERCOM7 signal: PAD0 on PB21 mux D */ +#define MUX_PB21D_SERCOM7_PAD0 _L_(3) +#define PINMUX_PB21D_SERCOM7_PAD0 ((PIN_PB21D_SERCOM7_PAD0 << 16) | MUX_PB21D_SERCOM7_PAD0) +#define PORT_PB21D_SERCOM7_PAD0 (_UL_(1) << 21) +#define PIN_PD08C_SERCOM7_PAD0 _L_(104) /**< \brief SERCOM7 signal: PAD0 on PD08 mux C */ +#define MUX_PD08C_SERCOM7_PAD0 _L_(2) +#define PINMUX_PD08C_SERCOM7_PAD0 ((PIN_PD08C_SERCOM7_PAD0 << 16) | MUX_PD08C_SERCOM7_PAD0) +#define PORT_PD08C_SERCOM7_PAD0 (_UL_(1) << 8) +#define PIN_PB30C_SERCOM7_PAD0 _L_(62) /**< \brief SERCOM7 signal: PAD0 on PB30 mux C */ +#define MUX_PB30C_SERCOM7_PAD0 _L_(2) +#define PINMUX_PB30C_SERCOM7_PAD0 ((PIN_PB30C_SERCOM7_PAD0 << 16) | MUX_PB30C_SERCOM7_PAD0) +#define PORT_PB30C_SERCOM7_PAD0 (_UL_(1) << 30) +#define PIN_PC12C_SERCOM7_PAD0 _L_(76) /**< \brief SERCOM7 signal: PAD0 on PC12 mux C */ +#define MUX_PC12C_SERCOM7_PAD0 _L_(2) +#define PINMUX_PC12C_SERCOM7_PAD0 ((PIN_PC12C_SERCOM7_PAD0 << 16) | MUX_PC12C_SERCOM7_PAD0) +#define PORT_PC12C_SERCOM7_PAD0 (_UL_(1) << 12) +#define PIN_PB20D_SERCOM7_PAD1 _L_(52) /**< \brief SERCOM7 signal: PAD1 on PB20 mux D */ +#define MUX_PB20D_SERCOM7_PAD1 _L_(3) +#define PINMUX_PB20D_SERCOM7_PAD1 ((PIN_PB20D_SERCOM7_PAD1 << 16) | MUX_PB20D_SERCOM7_PAD1) +#define PORT_PB20D_SERCOM7_PAD1 (_UL_(1) << 20) +#define PIN_PD09C_SERCOM7_PAD1 _L_(105) /**< \brief SERCOM7 signal: PAD1 on PD09 mux C */ +#define MUX_PD09C_SERCOM7_PAD1 _L_(2) +#define PINMUX_PD09C_SERCOM7_PAD1 ((PIN_PD09C_SERCOM7_PAD1 << 16) | MUX_PD09C_SERCOM7_PAD1) +#define PORT_PD09C_SERCOM7_PAD1 (_UL_(1) << 9) +#define PIN_PB31C_SERCOM7_PAD1 _L_(63) /**< \brief SERCOM7 signal: PAD1 on PB31 mux C */ +#define MUX_PB31C_SERCOM7_PAD1 _L_(2) +#define PINMUX_PB31C_SERCOM7_PAD1 ((PIN_PB31C_SERCOM7_PAD1 << 16) | MUX_PB31C_SERCOM7_PAD1) +#define PORT_PB31C_SERCOM7_PAD1 (_UL_(1) << 31) +#define PIN_PC13C_SERCOM7_PAD1 _L_(77) /**< \brief SERCOM7 signal: PAD1 on PC13 mux C */ +#define MUX_PC13C_SERCOM7_PAD1 _L_(2) +#define PINMUX_PC13C_SERCOM7_PAD1 ((PIN_PC13C_SERCOM7_PAD1 << 16) | MUX_PC13C_SERCOM7_PAD1) +#define PORT_PC13C_SERCOM7_PAD1 (_UL_(1) << 13) +#define PIN_PB18D_SERCOM7_PAD2 _L_(50) /**< \brief SERCOM7 signal: PAD2 on PB18 mux D */ +#define MUX_PB18D_SERCOM7_PAD2 _L_(3) +#define PINMUX_PB18D_SERCOM7_PAD2 ((PIN_PB18D_SERCOM7_PAD2 << 16) | MUX_PB18D_SERCOM7_PAD2) +#define PORT_PB18D_SERCOM7_PAD2 (_UL_(1) << 18) +#define PIN_PC10D_SERCOM7_PAD2 _L_(74) /**< \brief SERCOM7 signal: PAD2 on PC10 mux D */ +#define MUX_PC10D_SERCOM7_PAD2 _L_(3) +#define PINMUX_PC10D_SERCOM7_PAD2 ((PIN_PC10D_SERCOM7_PAD2 << 16) | MUX_PC10D_SERCOM7_PAD2) +#define PORT_PC10D_SERCOM7_PAD2 (_UL_(1) << 10) +#define PIN_PC14C_SERCOM7_PAD2 _L_(78) /**< \brief SERCOM7 signal: PAD2 on PC14 mux C */ +#define MUX_PC14C_SERCOM7_PAD2 _L_(2) +#define PINMUX_PC14C_SERCOM7_PAD2 ((PIN_PC14C_SERCOM7_PAD2 << 16) | MUX_PC14C_SERCOM7_PAD2) +#define PORT_PC14C_SERCOM7_PAD2 (_UL_(1) << 14) +#define PIN_PD10C_SERCOM7_PAD2 _L_(106) /**< \brief SERCOM7 signal: PAD2 on PD10 mux C */ +#define MUX_PD10C_SERCOM7_PAD2 _L_(2) +#define PINMUX_PD10C_SERCOM7_PAD2 ((PIN_PD10C_SERCOM7_PAD2 << 16) | MUX_PD10C_SERCOM7_PAD2) +#define PORT_PD10C_SERCOM7_PAD2 (_UL_(1) << 10) +#define PIN_PA30C_SERCOM7_PAD2 _L_(30) /**< \brief SERCOM7 signal: PAD2 on PA30 mux C */ +#define MUX_PA30C_SERCOM7_PAD2 _L_(2) +#define PINMUX_PA30C_SERCOM7_PAD2 ((PIN_PA30C_SERCOM7_PAD2 << 16) | MUX_PA30C_SERCOM7_PAD2) +#define PORT_PA30C_SERCOM7_PAD2 (_UL_(1) << 30) +#define PIN_PB19D_SERCOM7_PAD3 _L_(51) /**< \brief SERCOM7 signal: PAD3 on PB19 mux D */ +#define MUX_PB19D_SERCOM7_PAD3 _L_(3) +#define PINMUX_PB19D_SERCOM7_PAD3 ((PIN_PB19D_SERCOM7_PAD3 << 16) | MUX_PB19D_SERCOM7_PAD3) +#define PORT_PB19D_SERCOM7_PAD3 (_UL_(1) << 19) +#define PIN_PC11D_SERCOM7_PAD3 _L_(75) /**< \brief SERCOM7 signal: PAD3 on PC11 mux D */ +#define MUX_PC11D_SERCOM7_PAD3 _L_(3) +#define PINMUX_PC11D_SERCOM7_PAD3 ((PIN_PC11D_SERCOM7_PAD3 << 16) | MUX_PC11D_SERCOM7_PAD3) +#define PORT_PC11D_SERCOM7_PAD3 (_UL_(1) << 11) +#define PIN_PC15C_SERCOM7_PAD3 _L_(79) /**< \brief SERCOM7 signal: PAD3 on PC15 mux C */ +#define MUX_PC15C_SERCOM7_PAD3 _L_(2) +#define PINMUX_PC15C_SERCOM7_PAD3 ((PIN_PC15C_SERCOM7_PAD3 << 16) | MUX_PC15C_SERCOM7_PAD3) +#define PORT_PC15C_SERCOM7_PAD3 (_UL_(1) << 15) +#define PIN_PD11C_SERCOM7_PAD3 _L_(107) /**< \brief SERCOM7 signal: PAD3 on PD11 mux C */ +#define MUX_PD11C_SERCOM7_PAD3 _L_(2) +#define PINMUX_PD11C_SERCOM7_PAD3 ((PIN_PD11C_SERCOM7_PAD3 << 16) | MUX_PD11C_SERCOM7_PAD3) +#define PORT_PD11C_SERCOM7_PAD3 (_UL_(1) << 11) +#define PIN_PA31C_SERCOM7_PAD3 _L_(31) /**< \brief SERCOM7 signal: PAD3 on PA31 mux C */ +#define MUX_PA31C_SERCOM7_PAD3 _L_(2) +#define PINMUX_PA31C_SERCOM7_PAD3 ((PIN_PA31C_SERCOM7_PAD3 << 16) | MUX_PA31C_SERCOM7_PAD3) +#define PORT_PA31C_SERCOM7_PAD3 (_UL_(1) << 31) +/* ========== PORT definition for TCC4 peripheral ========== */ +#define PIN_PB14F_TCC4_WO0 _L_(46) /**< \brief TCC4 signal: WO0 on PB14 mux F */ +#define MUX_PB14F_TCC4_WO0 _L_(5) +#define PINMUX_PB14F_TCC4_WO0 ((PIN_PB14F_TCC4_WO0 << 16) | MUX_PB14F_TCC4_WO0) +#define PORT_PB14F_TCC4_WO0 (_UL_(1) << 14) +#define PIN_PB30F_TCC4_WO0 _L_(62) /**< \brief TCC4 signal: WO0 on PB30 mux F */ +#define MUX_PB30F_TCC4_WO0 _L_(5) +#define PINMUX_PB30F_TCC4_WO0 ((PIN_PB30F_TCC4_WO0 << 16) | MUX_PB30F_TCC4_WO0) +#define PORT_PB30F_TCC4_WO0 (_UL_(1) << 30) +#define PIN_PB15F_TCC4_WO1 _L_(47) /**< \brief TCC4 signal: WO1 on PB15 mux F */ +#define MUX_PB15F_TCC4_WO1 _L_(5) +#define PINMUX_PB15F_TCC4_WO1 ((PIN_PB15F_TCC4_WO1 << 16) | MUX_PB15F_TCC4_WO1) +#define PORT_PB15F_TCC4_WO1 (_UL_(1) << 15) +#define PIN_PB31F_TCC4_WO1 _L_(63) /**< \brief TCC4 signal: WO1 on PB31 mux F */ +#define MUX_PB31F_TCC4_WO1 _L_(5) +#define PINMUX_PB31F_TCC4_WO1 ((PIN_PB31F_TCC4_WO1 << 16) | MUX_PB31F_TCC4_WO1) +#define PORT_PB31F_TCC4_WO1 (_UL_(1) << 31) +/* ========== PORT definition for TC6 peripheral ========== */ +#define PIN_PA30E_TC6_WO0 _L_(30) /**< \brief TC6 signal: WO0 on PA30 mux E */ +#define MUX_PA30E_TC6_WO0 _L_(4) +#define PINMUX_PA30E_TC6_WO0 ((PIN_PA30E_TC6_WO0 << 16) | MUX_PA30E_TC6_WO0) +#define PORT_PA30E_TC6_WO0 (_UL_(1) << 30) +#define PIN_PB02E_TC6_WO0 _L_(34) /**< \brief TC6 signal: WO0 on PB02 mux E */ +#define MUX_PB02E_TC6_WO0 _L_(4) +#define PINMUX_PB02E_TC6_WO0 ((PIN_PB02E_TC6_WO0 << 16) | MUX_PB02E_TC6_WO0) +#define PORT_PB02E_TC6_WO0 (_UL_(1) << 2) +#define PIN_PB16E_TC6_WO0 _L_(48) /**< \brief TC6 signal: WO0 on PB16 mux E */ +#define MUX_PB16E_TC6_WO0 _L_(4) +#define PINMUX_PB16E_TC6_WO0 ((PIN_PB16E_TC6_WO0 << 16) | MUX_PB16E_TC6_WO0) +#define PORT_PB16E_TC6_WO0 (_UL_(1) << 16) +#define PIN_PA31E_TC6_WO1 _L_(31) /**< \brief TC6 signal: WO1 on PA31 mux E */ +#define MUX_PA31E_TC6_WO1 _L_(4) +#define PINMUX_PA31E_TC6_WO1 ((PIN_PA31E_TC6_WO1 << 16) | MUX_PA31E_TC6_WO1) +#define PORT_PA31E_TC6_WO1 (_UL_(1) << 31) +#define PIN_PB03E_TC6_WO1 _L_(35) /**< \brief TC6 signal: WO1 on PB03 mux E */ +#define MUX_PB03E_TC6_WO1 _L_(4) +#define PINMUX_PB03E_TC6_WO1 ((PIN_PB03E_TC6_WO1 << 16) | MUX_PB03E_TC6_WO1) +#define PORT_PB03E_TC6_WO1 (_UL_(1) << 3) +#define PIN_PB17E_TC6_WO1 _L_(49) /**< \brief TC6 signal: WO1 on PB17 mux E */ +#define MUX_PB17E_TC6_WO1 _L_(4) +#define PINMUX_PB17E_TC6_WO1 ((PIN_PB17E_TC6_WO1 << 16) | MUX_PB17E_TC6_WO1) +#define PORT_PB17E_TC6_WO1 (_UL_(1) << 17) +/* ========== PORT definition for TC7 peripheral ========== */ +#define PIN_PA20E_TC7_WO0 _L_(20) /**< \brief TC7 signal: WO0 on PA20 mux E */ +#define MUX_PA20E_TC7_WO0 _L_(4) +#define PINMUX_PA20E_TC7_WO0 ((PIN_PA20E_TC7_WO0 << 16) | MUX_PA20E_TC7_WO0) +#define PORT_PA20E_TC7_WO0 (_UL_(1) << 20) +#define PIN_PB00E_TC7_WO0 _L_(32) /**< \brief TC7 signal: WO0 on PB00 mux E */ +#define MUX_PB00E_TC7_WO0 _L_(4) +#define PINMUX_PB00E_TC7_WO0 ((PIN_PB00E_TC7_WO0 << 16) | MUX_PB00E_TC7_WO0) +#define PORT_PB00E_TC7_WO0 (_UL_(1) << 0) +#define PIN_PB22E_TC7_WO0 _L_(54) /**< \brief TC7 signal: WO0 on PB22 mux E */ +#define MUX_PB22E_TC7_WO0 _L_(4) +#define PINMUX_PB22E_TC7_WO0 ((PIN_PB22E_TC7_WO0 << 16) | MUX_PB22E_TC7_WO0) +#define PORT_PB22E_TC7_WO0 (_UL_(1) << 22) +#define PIN_PA21E_TC7_WO1 _L_(21) /**< \brief TC7 signal: WO1 on PA21 mux E */ +#define MUX_PA21E_TC7_WO1 _L_(4) +#define PINMUX_PA21E_TC7_WO1 ((PIN_PA21E_TC7_WO1 << 16) | MUX_PA21E_TC7_WO1) +#define PORT_PA21E_TC7_WO1 (_UL_(1) << 21) +#define PIN_PB01E_TC7_WO1 _L_(33) /**< \brief TC7 signal: WO1 on PB01 mux E */ +#define MUX_PB01E_TC7_WO1 _L_(4) +#define PINMUX_PB01E_TC7_WO1 ((PIN_PB01E_TC7_WO1 << 16) | MUX_PB01E_TC7_WO1) +#define PORT_PB01E_TC7_WO1 (_UL_(1) << 1) +#define PIN_PB23E_TC7_WO1 _L_(55) /**< \brief TC7 signal: WO1 on PB23 mux E */ +#define MUX_PB23E_TC7_WO1 _L_(4) +#define PINMUX_PB23E_TC7_WO1 ((PIN_PB23E_TC7_WO1 << 16) | MUX_PB23E_TC7_WO1) +#define PORT_PB23E_TC7_WO1 (_UL_(1) << 23) +/* ========== PORT definition for ADC0 peripheral ========== */ +#define PIN_PA02B_ADC0_AIN0 _L_(2) /**< \brief ADC0 signal: AIN0 on PA02 mux B */ +#define MUX_PA02B_ADC0_AIN0 _L_(1) +#define PINMUX_PA02B_ADC0_AIN0 ((PIN_PA02B_ADC0_AIN0 << 16) | MUX_PA02B_ADC0_AIN0) +#define PORT_PA02B_ADC0_AIN0 (_UL_(1) << 2) +#define PIN_PA03B_ADC0_AIN1 _L_(3) /**< \brief ADC0 signal: AIN1 on PA03 mux B */ +#define MUX_PA03B_ADC0_AIN1 _L_(1) +#define PINMUX_PA03B_ADC0_AIN1 ((PIN_PA03B_ADC0_AIN1 << 16) | MUX_PA03B_ADC0_AIN1) +#define PORT_PA03B_ADC0_AIN1 (_UL_(1) << 3) +#define PIN_PB08B_ADC0_AIN2 _L_(40) /**< \brief ADC0 signal: AIN2 on PB08 mux B */ +#define MUX_PB08B_ADC0_AIN2 _L_(1) +#define PINMUX_PB08B_ADC0_AIN2 ((PIN_PB08B_ADC0_AIN2 << 16) | MUX_PB08B_ADC0_AIN2) +#define PORT_PB08B_ADC0_AIN2 (_UL_(1) << 8) +#define PIN_PB09B_ADC0_AIN3 _L_(41) /**< \brief ADC0 signal: AIN3 on PB09 mux B */ +#define MUX_PB09B_ADC0_AIN3 _L_(1) +#define PINMUX_PB09B_ADC0_AIN3 ((PIN_PB09B_ADC0_AIN3 << 16) | MUX_PB09B_ADC0_AIN3) +#define PORT_PB09B_ADC0_AIN3 (_UL_(1) << 9) +#define PIN_PA04B_ADC0_AIN4 _L_(4) /**< \brief ADC0 signal: AIN4 on PA04 mux B */ +#define MUX_PA04B_ADC0_AIN4 _L_(1) +#define PINMUX_PA04B_ADC0_AIN4 ((PIN_PA04B_ADC0_AIN4 << 16) | MUX_PA04B_ADC0_AIN4) +#define PORT_PA04B_ADC0_AIN4 (_UL_(1) << 4) +#define PIN_PA05B_ADC0_AIN5 _L_(5) /**< \brief ADC0 signal: AIN5 on PA05 mux B */ +#define MUX_PA05B_ADC0_AIN5 _L_(1) +#define PINMUX_PA05B_ADC0_AIN5 ((PIN_PA05B_ADC0_AIN5 << 16) | MUX_PA05B_ADC0_AIN5) +#define PORT_PA05B_ADC0_AIN5 (_UL_(1) << 5) +#define PIN_PA06B_ADC0_AIN6 _L_(6) /**< \brief ADC0 signal: AIN6 on PA06 mux B */ +#define MUX_PA06B_ADC0_AIN6 _L_(1) +#define PINMUX_PA06B_ADC0_AIN6 ((PIN_PA06B_ADC0_AIN6 << 16) | MUX_PA06B_ADC0_AIN6) +#define PORT_PA06B_ADC0_AIN6 (_UL_(1) << 6) +#define PIN_PA07B_ADC0_AIN7 _L_(7) /**< \brief ADC0 signal: AIN7 on PA07 mux B */ +#define MUX_PA07B_ADC0_AIN7 _L_(1) +#define PINMUX_PA07B_ADC0_AIN7 ((PIN_PA07B_ADC0_AIN7 << 16) | MUX_PA07B_ADC0_AIN7) +#define PORT_PA07B_ADC0_AIN7 (_UL_(1) << 7) +#define PIN_PA08B_ADC0_AIN8 _L_(8) /**< \brief ADC0 signal: AIN8 on PA08 mux B */ +#define MUX_PA08B_ADC0_AIN8 _L_(1) +#define PINMUX_PA08B_ADC0_AIN8 ((PIN_PA08B_ADC0_AIN8 << 16) | MUX_PA08B_ADC0_AIN8) +#define PORT_PA08B_ADC0_AIN8 (_UL_(1) << 8) +#define PIN_PA09B_ADC0_AIN9 _L_(9) /**< \brief ADC0 signal: AIN9 on PA09 mux B */ +#define MUX_PA09B_ADC0_AIN9 _L_(1) +#define PINMUX_PA09B_ADC0_AIN9 ((PIN_PA09B_ADC0_AIN9 << 16) | MUX_PA09B_ADC0_AIN9) +#define PORT_PA09B_ADC0_AIN9 (_UL_(1) << 9) +#define PIN_PA10B_ADC0_AIN10 _L_(10) /**< \brief ADC0 signal: AIN10 on PA10 mux B */ +#define MUX_PA10B_ADC0_AIN10 _L_(1) +#define PINMUX_PA10B_ADC0_AIN10 ((PIN_PA10B_ADC0_AIN10 << 16) | MUX_PA10B_ADC0_AIN10) +#define PORT_PA10B_ADC0_AIN10 (_UL_(1) << 10) +#define PIN_PA11B_ADC0_AIN11 _L_(11) /**< \brief ADC0 signal: AIN11 on PA11 mux B */ +#define MUX_PA11B_ADC0_AIN11 _L_(1) +#define PINMUX_PA11B_ADC0_AIN11 ((PIN_PA11B_ADC0_AIN11 << 16) | MUX_PA11B_ADC0_AIN11) +#define PORT_PA11B_ADC0_AIN11 (_UL_(1) << 11) +#define PIN_PB00B_ADC0_AIN12 _L_(32) /**< \brief ADC0 signal: AIN12 on PB00 mux B */ +#define MUX_PB00B_ADC0_AIN12 _L_(1) +#define PINMUX_PB00B_ADC0_AIN12 ((PIN_PB00B_ADC0_AIN12 << 16) | MUX_PB00B_ADC0_AIN12) +#define PORT_PB00B_ADC0_AIN12 (_UL_(1) << 0) +#define PIN_PB01B_ADC0_AIN13 _L_(33) /**< \brief ADC0 signal: AIN13 on PB01 mux B */ +#define MUX_PB01B_ADC0_AIN13 _L_(1) +#define PINMUX_PB01B_ADC0_AIN13 ((PIN_PB01B_ADC0_AIN13 << 16) | MUX_PB01B_ADC0_AIN13) +#define PORT_PB01B_ADC0_AIN13 (_UL_(1) << 1) +#define PIN_PB02B_ADC0_AIN14 _L_(34) /**< \brief ADC0 signal: AIN14 on PB02 mux B */ +#define MUX_PB02B_ADC0_AIN14 _L_(1) +#define PINMUX_PB02B_ADC0_AIN14 ((PIN_PB02B_ADC0_AIN14 << 16) | MUX_PB02B_ADC0_AIN14) +#define PORT_PB02B_ADC0_AIN14 (_UL_(1) << 2) +#define PIN_PB03B_ADC0_AIN15 _L_(35) /**< \brief ADC0 signal: AIN15 on PB03 mux B */ +#define MUX_PB03B_ADC0_AIN15 _L_(1) +#define PINMUX_PB03B_ADC0_AIN15 ((PIN_PB03B_ADC0_AIN15 << 16) | MUX_PB03B_ADC0_AIN15) +#define PORT_PB03B_ADC0_AIN15 (_UL_(1) << 3) +#define PIN_PA03O_ADC0_DRV0 _L_(3) /**< \brief ADC0 signal: DRV0 on PA03 mux O */ +#define MUX_PA03O_ADC0_DRV0 _L_(14) +#define PINMUX_PA03O_ADC0_DRV0 ((PIN_PA03O_ADC0_DRV0 << 16) | MUX_PA03O_ADC0_DRV0) +#define PORT_PA03O_ADC0_DRV0 (_UL_(1) << 3) +#define PIN_PB08O_ADC0_DRV1 _L_(40) /**< \brief ADC0 signal: DRV1 on PB08 mux O */ +#define MUX_PB08O_ADC0_DRV1 _L_(14) +#define PINMUX_PB08O_ADC0_DRV1 ((PIN_PB08O_ADC0_DRV1 << 16) | MUX_PB08O_ADC0_DRV1) +#define PORT_PB08O_ADC0_DRV1 (_UL_(1) << 8) +#define PIN_PB09O_ADC0_DRV2 _L_(41) /**< \brief ADC0 signal: DRV2 on PB09 mux O */ +#define MUX_PB09O_ADC0_DRV2 _L_(14) +#define PINMUX_PB09O_ADC0_DRV2 ((PIN_PB09O_ADC0_DRV2 << 16) | MUX_PB09O_ADC0_DRV2) +#define PORT_PB09O_ADC0_DRV2 (_UL_(1) << 9) +#define PIN_PA04O_ADC0_DRV3 _L_(4) /**< \brief ADC0 signal: DRV3 on PA04 mux O */ +#define MUX_PA04O_ADC0_DRV3 _L_(14) +#define PINMUX_PA04O_ADC0_DRV3 ((PIN_PA04O_ADC0_DRV3 << 16) | MUX_PA04O_ADC0_DRV3) +#define PORT_PA04O_ADC0_DRV3 (_UL_(1) << 4) +#define PIN_PA06O_ADC0_DRV4 _L_(6) /**< \brief ADC0 signal: DRV4 on PA06 mux O */ +#define MUX_PA06O_ADC0_DRV4 _L_(14) +#define PINMUX_PA06O_ADC0_DRV4 ((PIN_PA06O_ADC0_DRV4 << 16) | MUX_PA06O_ADC0_DRV4) +#define PORT_PA06O_ADC0_DRV4 (_UL_(1) << 6) +#define PIN_PA07O_ADC0_DRV5 _L_(7) /**< \brief ADC0 signal: DRV5 on PA07 mux O */ +#define MUX_PA07O_ADC0_DRV5 _L_(14) +#define PINMUX_PA07O_ADC0_DRV5 ((PIN_PA07O_ADC0_DRV5 << 16) | MUX_PA07O_ADC0_DRV5) +#define PORT_PA07O_ADC0_DRV5 (_UL_(1) << 7) +#define PIN_PA08O_ADC0_DRV6 _L_(8) /**< \brief ADC0 signal: DRV6 on PA08 mux O */ +#define MUX_PA08O_ADC0_DRV6 _L_(14) +#define PINMUX_PA08O_ADC0_DRV6 ((PIN_PA08O_ADC0_DRV6 << 16) | MUX_PA08O_ADC0_DRV6) +#define PORT_PA08O_ADC0_DRV6 (_UL_(1) << 8) +#define PIN_PA09O_ADC0_DRV7 _L_(9) /**< \brief ADC0 signal: DRV7 on PA09 mux O */ +#define MUX_PA09O_ADC0_DRV7 _L_(14) +#define PINMUX_PA09O_ADC0_DRV7 ((PIN_PA09O_ADC0_DRV7 << 16) | MUX_PA09O_ADC0_DRV7) +#define PORT_PA09O_ADC0_DRV7 (_UL_(1) << 9) +#define PIN_PA10O_ADC0_DRV8 _L_(10) /**< \brief ADC0 signal: DRV8 on PA10 mux O */ +#define MUX_PA10O_ADC0_DRV8 _L_(14) +#define PINMUX_PA10O_ADC0_DRV8 ((PIN_PA10O_ADC0_DRV8 << 16) | MUX_PA10O_ADC0_DRV8) +#define PORT_PA10O_ADC0_DRV8 (_UL_(1) << 10) +#define PIN_PA11O_ADC0_DRV9 _L_(11) /**< \brief ADC0 signal: DRV9 on PA11 mux O */ +#define MUX_PA11O_ADC0_DRV9 _L_(14) +#define PINMUX_PA11O_ADC0_DRV9 ((PIN_PA11O_ADC0_DRV9 << 16) | MUX_PA11O_ADC0_DRV9) +#define PORT_PA11O_ADC0_DRV9 (_UL_(1) << 11) +#define PIN_PA16O_ADC0_DRV10 _L_(16) /**< \brief ADC0 signal: DRV10 on PA16 mux O */ +#define MUX_PA16O_ADC0_DRV10 _L_(14) +#define PINMUX_PA16O_ADC0_DRV10 ((PIN_PA16O_ADC0_DRV10 << 16) | MUX_PA16O_ADC0_DRV10) +#define PORT_PA16O_ADC0_DRV10 (_UL_(1) << 16) +#define PIN_PA17O_ADC0_DRV11 _L_(17) /**< \brief ADC0 signal: DRV11 on PA17 mux O */ +#define MUX_PA17O_ADC0_DRV11 _L_(14) +#define PINMUX_PA17O_ADC0_DRV11 ((PIN_PA17O_ADC0_DRV11 << 16) | MUX_PA17O_ADC0_DRV11) +#define PORT_PA17O_ADC0_DRV11 (_UL_(1) << 17) +#define PIN_PA18O_ADC0_DRV12 _L_(18) /**< \brief ADC0 signal: DRV12 on PA18 mux O */ +#define MUX_PA18O_ADC0_DRV12 _L_(14) +#define PINMUX_PA18O_ADC0_DRV12 ((PIN_PA18O_ADC0_DRV12 << 16) | MUX_PA18O_ADC0_DRV12) +#define PORT_PA18O_ADC0_DRV12 (_UL_(1) << 18) +#define PIN_PA19O_ADC0_DRV13 _L_(19) /**< \brief ADC0 signal: DRV13 on PA19 mux O */ +#define MUX_PA19O_ADC0_DRV13 _L_(14) +#define PINMUX_PA19O_ADC0_DRV13 ((PIN_PA19O_ADC0_DRV13 << 16) | MUX_PA19O_ADC0_DRV13) +#define PORT_PA19O_ADC0_DRV13 (_UL_(1) << 19) +#define PIN_PA20O_ADC0_DRV14 _L_(20) /**< \brief ADC0 signal: DRV14 on PA20 mux O */ +#define MUX_PA20O_ADC0_DRV14 _L_(14) +#define PINMUX_PA20O_ADC0_DRV14 ((PIN_PA20O_ADC0_DRV14 << 16) | MUX_PA20O_ADC0_DRV14) +#define PORT_PA20O_ADC0_DRV14 (_UL_(1) << 20) +#define PIN_PA21O_ADC0_DRV15 _L_(21) /**< \brief ADC0 signal: DRV15 on PA21 mux O */ +#define MUX_PA21O_ADC0_DRV15 _L_(14) +#define PINMUX_PA21O_ADC0_DRV15 ((PIN_PA21O_ADC0_DRV15 << 16) | MUX_PA21O_ADC0_DRV15) +#define PORT_PA21O_ADC0_DRV15 (_UL_(1) << 21) +#define PIN_PA22O_ADC0_DRV16 _L_(22) /**< \brief ADC0 signal: DRV16 on PA22 mux O */ +#define MUX_PA22O_ADC0_DRV16 _L_(14) +#define PINMUX_PA22O_ADC0_DRV16 ((PIN_PA22O_ADC0_DRV16 << 16) | MUX_PA22O_ADC0_DRV16) +#define PORT_PA22O_ADC0_DRV16 (_UL_(1) << 22) +#define PIN_PA23O_ADC0_DRV17 _L_(23) /**< \brief ADC0 signal: DRV17 on PA23 mux O */ +#define MUX_PA23O_ADC0_DRV17 _L_(14) +#define PINMUX_PA23O_ADC0_DRV17 ((PIN_PA23O_ADC0_DRV17 << 16) | MUX_PA23O_ADC0_DRV17) +#define PORT_PA23O_ADC0_DRV17 (_UL_(1) << 23) +#define PIN_PA27O_ADC0_DRV18 _L_(27) /**< \brief ADC0 signal: DRV18 on PA27 mux O */ +#define MUX_PA27O_ADC0_DRV18 _L_(14) +#define PINMUX_PA27O_ADC0_DRV18 ((PIN_PA27O_ADC0_DRV18 << 16) | MUX_PA27O_ADC0_DRV18) +#define PORT_PA27O_ADC0_DRV18 (_UL_(1) << 27) +#define PIN_PA30O_ADC0_DRV19 _L_(30) /**< \brief ADC0 signal: DRV19 on PA30 mux O */ +#define MUX_PA30O_ADC0_DRV19 _L_(14) +#define PINMUX_PA30O_ADC0_DRV19 ((PIN_PA30O_ADC0_DRV19 << 16) | MUX_PA30O_ADC0_DRV19) +#define PORT_PA30O_ADC0_DRV19 (_UL_(1) << 30) +#define PIN_PB02O_ADC0_DRV20 _L_(34) /**< \brief ADC0 signal: DRV20 on PB02 mux O */ +#define MUX_PB02O_ADC0_DRV20 _L_(14) +#define PINMUX_PB02O_ADC0_DRV20 ((PIN_PB02O_ADC0_DRV20 << 16) | MUX_PB02O_ADC0_DRV20) +#define PORT_PB02O_ADC0_DRV20 (_UL_(1) << 2) +#define PIN_PB03O_ADC0_DRV21 _L_(35) /**< \brief ADC0 signal: DRV21 on PB03 mux O */ +#define MUX_PB03O_ADC0_DRV21 _L_(14) +#define PINMUX_PB03O_ADC0_DRV21 ((PIN_PB03O_ADC0_DRV21 << 16) | MUX_PB03O_ADC0_DRV21) +#define PORT_PB03O_ADC0_DRV21 (_UL_(1) << 3) +#define PIN_PB04O_ADC0_DRV22 _L_(36) /**< \brief ADC0 signal: DRV22 on PB04 mux O */ +#define MUX_PB04O_ADC0_DRV22 _L_(14) +#define PINMUX_PB04O_ADC0_DRV22 ((PIN_PB04O_ADC0_DRV22 << 16) | MUX_PB04O_ADC0_DRV22) +#define PORT_PB04O_ADC0_DRV22 (_UL_(1) << 4) +#define PIN_PB05O_ADC0_DRV23 _L_(37) /**< \brief ADC0 signal: DRV23 on PB05 mux O */ +#define MUX_PB05O_ADC0_DRV23 _L_(14) +#define PINMUX_PB05O_ADC0_DRV23 ((PIN_PB05O_ADC0_DRV23 << 16) | MUX_PB05O_ADC0_DRV23) +#define PORT_PB05O_ADC0_DRV23 (_UL_(1) << 5) +#define PIN_PB06O_ADC0_DRV24 _L_(38) /**< \brief ADC0 signal: DRV24 on PB06 mux O */ +#define MUX_PB06O_ADC0_DRV24 _L_(14) +#define PINMUX_PB06O_ADC0_DRV24 ((PIN_PB06O_ADC0_DRV24 << 16) | MUX_PB06O_ADC0_DRV24) +#define PORT_PB06O_ADC0_DRV24 (_UL_(1) << 6) +#define PIN_PB07O_ADC0_DRV25 _L_(39) /**< \brief ADC0 signal: DRV25 on PB07 mux O */ +#define MUX_PB07O_ADC0_DRV25 _L_(14) +#define PINMUX_PB07O_ADC0_DRV25 ((PIN_PB07O_ADC0_DRV25 << 16) | MUX_PB07O_ADC0_DRV25) +#define PORT_PB07O_ADC0_DRV25 (_UL_(1) << 7) +#define PIN_PB12O_ADC0_DRV26 _L_(44) /**< \brief ADC0 signal: DRV26 on PB12 mux O */ +#define MUX_PB12O_ADC0_DRV26 _L_(14) +#define PINMUX_PB12O_ADC0_DRV26 ((PIN_PB12O_ADC0_DRV26 << 16) | MUX_PB12O_ADC0_DRV26) +#define PORT_PB12O_ADC0_DRV26 (_UL_(1) << 12) +#define PIN_PB13O_ADC0_DRV27 _L_(45) /**< \brief ADC0 signal: DRV27 on PB13 mux O */ +#define MUX_PB13O_ADC0_DRV27 _L_(14) +#define PINMUX_PB13O_ADC0_DRV27 ((PIN_PB13O_ADC0_DRV27 << 16) | MUX_PB13O_ADC0_DRV27) +#define PORT_PB13O_ADC0_DRV27 (_UL_(1) << 13) +#define PIN_PB14O_ADC0_DRV28 _L_(46) /**< \brief ADC0 signal: DRV28 on PB14 mux O */ +#define MUX_PB14O_ADC0_DRV28 _L_(14) +#define PINMUX_PB14O_ADC0_DRV28 ((PIN_PB14O_ADC0_DRV28 << 16) | MUX_PB14O_ADC0_DRV28) +#define PORT_PB14O_ADC0_DRV28 (_UL_(1) << 14) +#define PIN_PB15O_ADC0_DRV29 _L_(47) /**< \brief ADC0 signal: DRV29 on PB15 mux O */ +#define MUX_PB15O_ADC0_DRV29 _L_(14) +#define PINMUX_PB15O_ADC0_DRV29 ((PIN_PB15O_ADC0_DRV29 << 16) | MUX_PB15O_ADC0_DRV29) +#define PORT_PB15O_ADC0_DRV29 (_UL_(1) << 15) +#define PIN_PB00O_ADC0_DRV30 _L_(32) /**< \brief ADC0 signal: DRV30 on PB00 mux O */ +#define MUX_PB00O_ADC0_DRV30 _L_(14) +#define PINMUX_PB00O_ADC0_DRV30 ((PIN_PB00O_ADC0_DRV30 << 16) | MUX_PB00O_ADC0_DRV30) +#define PORT_PB00O_ADC0_DRV30 (_UL_(1) << 0) +#define PIN_PB01O_ADC0_DRV31 _L_(33) /**< \brief ADC0 signal: DRV31 on PB01 mux O */ +#define MUX_PB01O_ADC0_DRV31 _L_(14) +#define PINMUX_PB01O_ADC0_DRV31 ((PIN_PB01O_ADC0_DRV31 << 16) | MUX_PB01O_ADC0_DRV31) +#define PORT_PB01O_ADC0_DRV31 (_UL_(1) << 1) +#define PIN_PA03B_ADC0_PTCXY0 _L_(3) /**< \brief ADC0 signal: PTCXY0 on PA03 mux B */ +#define MUX_PA03B_ADC0_PTCXY0 _L_(1) +#define PINMUX_PA03B_ADC0_PTCXY0 ((PIN_PA03B_ADC0_PTCXY0 << 16) | MUX_PA03B_ADC0_PTCXY0) +#define PORT_PA03B_ADC0_PTCXY0 (_UL_(1) << 3) +#define PIN_PB08B_ADC0_PTCXY1 _L_(40) /**< \brief ADC0 signal: PTCXY1 on PB08 mux B */ +#define MUX_PB08B_ADC0_PTCXY1 _L_(1) +#define PINMUX_PB08B_ADC0_PTCXY1 ((PIN_PB08B_ADC0_PTCXY1 << 16) | MUX_PB08B_ADC0_PTCXY1) +#define PORT_PB08B_ADC0_PTCXY1 (_UL_(1) << 8) +#define PIN_PB09B_ADC0_PTCXY2 _L_(41) /**< \brief ADC0 signal: PTCXY2 on PB09 mux B */ +#define MUX_PB09B_ADC0_PTCXY2 _L_(1) +#define PINMUX_PB09B_ADC0_PTCXY2 ((PIN_PB09B_ADC0_PTCXY2 << 16) | MUX_PB09B_ADC0_PTCXY2) +#define PORT_PB09B_ADC0_PTCXY2 (_UL_(1) << 9) +#define PIN_PA04B_ADC0_PTCXY3 _L_(4) /**< \brief ADC0 signal: PTCXY3 on PA04 mux B */ +#define MUX_PA04B_ADC0_PTCXY3 _L_(1) +#define PINMUX_PA04B_ADC0_PTCXY3 ((PIN_PA04B_ADC0_PTCXY3 << 16) | MUX_PA04B_ADC0_PTCXY3) +#define PORT_PA04B_ADC0_PTCXY3 (_UL_(1) << 4) +#define PIN_PA06B_ADC0_PTCXY4 _L_(6) /**< \brief ADC0 signal: PTCXY4 on PA06 mux B */ +#define MUX_PA06B_ADC0_PTCXY4 _L_(1) +#define PINMUX_PA06B_ADC0_PTCXY4 ((PIN_PA06B_ADC0_PTCXY4 << 16) | MUX_PA06B_ADC0_PTCXY4) +#define PORT_PA06B_ADC0_PTCXY4 (_UL_(1) << 6) +#define PIN_PA07B_ADC0_PTCXY5 _L_(7) /**< \brief ADC0 signal: PTCXY5 on PA07 mux B */ +#define MUX_PA07B_ADC0_PTCXY5 _L_(1) +#define PINMUX_PA07B_ADC0_PTCXY5 ((PIN_PA07B_ADC0_PTCXY5 << 16) | MUX_PA07B_ADC0_PTCXY5) +#define PORT_PA07B_ADC0_PTCXY5 (_UL_(1) << 7) +#define PIN_PA08B_ADC0_PTCXY6 _L_(8) /**< \brief ADC0 signal: PTCXY6 on PA08 mux B */ +#define MUX_PA08B_ADC0_PTCXY6 _L_(1) +#define PINMUX_PA08B_ADC0_PTCXY6 ((PIN_PA08B_ADC0_PTCXY6 << 16) | MUX_PA08B_ADC0_PTCXY6) +#define PORT_PA08B_ADC0_PTCXY6 (_UL_(1) << 8) +#define PIN_PA09B_ADC0_PTCXY7 _L_(9) /**< \brief ADC0 signal: PTCXY7 on PA09 mux B */ +#define MUX_PA09B_ADC0_PTCXY7 _L_(1) +#define PINMUX_PA09B_ADC0_PTCXY7 ((PIN_PA09B_ADC0_PTCXY7 << 16) | MUX_PA09B_ADC0_PTCXY7) +#define PORT_PA09B_ADC0_PTCXY7 (_UL_(1) << 9) +#define PIN_PA10B_ADC0_PTCXY8 _L_(10) /**< \brief ADC0 signal: PTCXY8 on PA10 mux B */ +#define MUX_PA10B_ADC0_PTCXY8 _L_(1) +#define PINMUX_PA10B_ADC0_PTCXY8 ((PIN_PA10B_ADC0_PTCXY8 << 16) | MUX_PA10B_ADC0_PTCXY8) +#define PORT_PA10B_ADC0_PTCXY8 (_UL_(1) << 10) +#define PIN_PA11B_ADC0_PTCXY9 _L_(11) /**< \brief ADC0 signal: PTCXY9 on PA11 mux B */ +#define MUX_PA11B_ADC0_PTCXY9 _L_(1) +#define PINMUX_PA11B_ADC0_PTCXY9 ((PIN_PA11B_ADC0_PTCXY9 << 16) | MUX_PA11B_ADC0_PTCXY9) +#define PORT_PA11B_ADC0_PTCXY9 (_UL_(1) << 11) +#define PIN_PA16B_ADC0_PTCXY10 _L_(16) /**< \brief ADC0 signal: PTCXY10 on PA16 mux B */ +#define MUX_PA16B_ADC0_PTCXY10 _L_(1) +#define PINMUX_PA16B_ADC0_PTCXY10 ((PIN_PA16B_ADC0_PTCXY10 << 16) | MUX_PA16B_ADC0_PTCXY10) +#define PORT_PA16B_ADC0_PTCXY10 (_UL_(1) << 16) +#define PIN_PA17B_ADC0_PTCXY11 _L_(17) /**< \brief ADC0 signal: PTCXY11 on PA17 mux B */ +#define MUX_PA17B_ADC0_PTCXY11 _L_(1) +#define PINMUX_PA17B_ADC0_PTCXY11 ((PIN_PA17B_ADC0_PTCXY11 << 16) | MUX_PA17B_ADC0_PTCXY11) +#define PORT_PA17B_ADC0_PTCXY11 (_UL_(1) << 17) +#define PIN_PA18B_ADC0_PTCXY12 _L_(18) /**< \brief ADC0 signal: PTCXY12 on PA18 mux B */ +#define MUX_PA18B_ADC0_PTCXY12 _L_(1) +#define PINMUX_PA18B_ADC0_PTCXY12 ((PIN_PA18B_ADC0_PTCXY12 << 16) | MUX_PA18B_ADC0_PTCXY12) +#define PORT_PA18B_ADC0_PTCXY12 (_UL_(1) << 18) +#define PIN_PA19B_ADC0_PTCXY13 _L_(19) /**< \brief ADC0 signal: PTCXY13 on PA19 mux B */ +#define MUX_PA19B_ADC0_PTCXY13 _L_(1) +#define PINMUX_PA19B_ADC0_PTCXY13 ((PIN_PA19B_ADC0_PTCXY13 << 16) | MUX_PA19B_ADC0_PTCXY13) +#define PORT_PA19B_ADC0_PTCXY13 (_UL_(1) << 19) +#define PIN_PA20B_ADC0_PTCXY14 _L_(20) /**< \brief ADC0 signal: PTCXY14 on PA20 mux B */ +#define MUX_PA20B_ADC0_PTCXY14 _L_(1) +#define PINMUX_PA20B_ADC0_PTCXY14 ((PIN_PA20B_ADC0_PTCXY14 << 16) | MUX_PA20B_ADC0_PTCXY14) +#define PORT_PA20B_ADC0_PTCXY14 (_UL_(1) << 20) +#define PIN_PA21B_ADC0_PTCXY15 _L_(21) /**< \brief ADC0 signal: PTCXY15 on PA21 mux B */ +#define MUX_PA21B_ADC0_PTCXY15 _L_(1) +#define PINMUX_PA21B_ADC0_PTCXY15 ((PIN_PA21B_ADC0_PTCXY15 << 16) | MUX_PA21B_ADC0_PTCXY15) +#define PORT_PA21B_ADC0_PTCXY15 (_UL_(1) << 21) +#define PIN_PA22B_ADC0_PTCXY16 _L_(22) /**< \brief ADC0 signal: PTCXY16 on PA22 mux B */ +#define MUX_PA22B_ADC0_PTCXY16 _L_(1) +#define PINMUX_PA22B_ADC0_PTCXY16 ((PIN_PA22B_ADC0_PTCXY16 << 16) | MUX_PA22B_ADC0_PTCXY16) +#define PORT_PA22B_ADC0_PTCXY16 (_UL_(1) << 22) +#define PIN_PA23B_ADC0_PTCXY17 _L_(23) /**< \brief ADC0 signal: PTCXY17 on PA23 mux B */ +#define MUX_PA23B_ADC0_PTCXY17 _L_(1) +#define PINMUX_PA23B_ADC0_PTCXY17 ((PIN_PA23B_ADC0_PTCXY17 << 16) | MUX_PA23B_ADC0_PTCXY17) +#define PORT_PA23B_ADC0_PTCXY17 (_UL_(1) << 23) +#define PIN_PA27B_ADC0_PTCXY18 _L_(27) /**< \brief ADC0 signal: PTCXY18 on PA27 mux B */ +#define MUX_PA27B_ADC0_PTCXY18 _L_(1) +#define PINMUX_PA27B_ADC0_PTCXY18 ((PIN_PA27B_ADC0_PTCXY18 << 16) | MUX_PA27B_ADC0_PTCXY18) +#define PORT_PA27B_ADC0_PTCXY18 (_UL_(1) << 27) +#define PIN_PA30B_ADC0_PTCXY19 _L_(30) /**< \brief ADC0 signal: PTCXY19 on PA30 mux B */ +#define MUX_PA30B_ADC0_PTCXY19 _L_(1) +#define PINMUX_PA30B_ADC0_PTCXY19 ((PIN_PA30B_ADC0_PTCXY19 << 16) | MUX_PA30B_ADC0_PTCXY19) +#define PORT_PA30B_ADC0_PTCXY19 (_UL_(1) << 30) +#define PIN_PB02B_ADC0_PTCXY20 _L_(34) /**< \brief ADC0 signal: PTCXY20 on PB02 mux B */ +#define MUX_PB02B_ADC0_PTCXY20 _L_(1) +#define PINMUX_PB02B_ADC0_PTCXY20 ((PIN_PB02B_ADC0_PTCXY20 << 16) | MUX_PB02B_ADC0_PTCXY20) +#define PORT_PB02B_ADC0_PTCXY20 (_UL_(1) << 2) +#define PIN_PB03B_ADC0_PTCXY21 _L_(35) /**< \brief ADC0 signal: PTCXY21 on PB03 mux B */ +#define MUX_PB03B_ADC0_PTCXY21 _L_(1) +#define PINMUX_PB03B_ADC0_PTCXY21 ((PIN_PB03B_ADC0_PTCXY21 << 16) | MUX_PB03B_ADC0_PTCXY21) +#define PORT_PB03B_ADC0_PTCXY21 (_UL_(1) << 3) +#define PIN_PB04B_ADC0_PTCXY22 _L_(36) /**< \brief ADC0 signal: PTCXY22 on PB04 mux B */ +#define MUX_PB04B_ADC0_PTCXY22 _L_(1) +#define PINMUX_PB04B_ADC0_PTCXY22 ((PIN_PB04B_ADC0_PTCXY22 << 16) | MUX_PB04B_ADC0_PTCXY22) +#define PORT_PB04B_ADC0_PTCXY22 (_UL_(1) << 4) +#define PIN_PB05B_ADC0_PTCXY23 _L_(37) /**< \brief ADC0 signal: PTCXY23 on PB05 mux B */ +#define MUX_PB05B_ADC0_PTCXY23 _L_(1) +#define PINMUX_PB05B_ADC0_PTCXY23 ((PIN_PB05B_ADC0_PTCXY23 << 16) | MUX_PB05B_ADC0_PTCXY23) +#define PORT_PB05B_ADC0_PTCXY23 (_UL_(1) << 5) +#define PIN_PB06B_ADC0_PTCXY24 _L_(38) /**< \brief ADC0 signal: PTCXY24 on PB06 mux B */ +#define MUX_PB06B_ADC0_PTCXY24 _L_(1) +#define PINMUX_PB06B_ADC0_PTCXY24 ((PIN_PB06B_ADC0_PTCXY24 << 16) | MUX_PB06B_ADC0_PTCXY24) +#define PORT_PB06B_ADC0_PTCXY24 (_UL_(1) << 6) +#define PIN_PB07B_ADC0_PTCXY25 _L_(39) /**< \brief ADC0 signal: PTCXY25 on PB07 mux B */ +#define MUX_PB07B_ADC0_PTCXY25 _L_(1) +#define PINMUX_PB07B_ADC0_PTCXY25 ((PIN_PB07B_ADC0_PTCXY25 << 16) | MUX_PB07B_ADC0_PTCXY25) +#define PORT_PB07B_ADC0_PTCXY25 (_UL_(1) << 7) +#define PIN_PB12B_ADC0_PTCXY26 _L_(44) /**< \brief ADC0 signal: PTCXY26 on PB12 mux B */ +#define MUX_PB12B_ADC0_PTCXY26 _L_(1) +#define PINMUX_PB12B_ADC0_PTCXY26 ((PIN_PB12B_ADC0_PTCXY26 << 16) | MUX_PB12B_ADC0_PTCXY26) +#define PORT_PB12B_ADC0_PTCXY26 (_UL_(1) << 12) +#define PIN_PB13B_ADC0_PTCXY27 _L_(45) /**< \brief ADC0 signal: PTCXY27 on PB13 mux B */ +#define MUX_PB13B_ADC0_PTCXY27 _L_(1) +#define PINMUX_PB13B_ADC0_PTCXY27 ((PIN_PB13B_ADC0_PTCXY27 << 16) | MUX_PB13B_ADC0_PTCXY27) +#define PORT_PB13B_ADC0_PTCXY27 (_UL_(1) << 13) +#define PIN_PB14B_ADC0_PTCXY28 _L_(46) /**< \brief ADC0 signal: PTCXY28 on PB14 mux B */ +#define MUX_PB14B_ADC0_PTCXY28 _L_(1) +#define PINMUX_PB14B_ADC0_PTCXY28 ((PIN_PB14B_ADC0_PTCXY28 << 16) | MUX_PB14B_ADC0_PTCXY28) +#define PORT_PB14B_ADC0_PTCXY28 (_UL_(1) << 14) +#define PIN_PB15B_ADC0_PTCXY29 _L_(47) /**< \brief ADC0 signal: PTCXY29 on PB15 mux B */ +#define MUX_PB15B_ADC0_PTCXY29 _L_(1) +#define PINMUX_PB15B_ADC0_PTCXY29 ((PIN_PB15B_ADC0_PTCXY29 << 16) | MUX_PB15B_ADC0_PTCXY29) +#define PORT_PB15B_ADC0_PTCXY29 (_UL_(1) << 15) +#define PIN_PB00B_ADC0_PTCXY30 _L_(32) /**< \brief ADC0 signal: PTCXY30 on PB00 mux B */ +#define MUX_PB00B_ADC0_PTCXY30 _L_(1) +#define PINMUX_PB00B_ADC0_PTCXY30 ((PIN_PB00B_ADC0_PTCXY30 << 16) | MUX_PB00B_ADC0_PTCXY30) +#define PORT_PB00B_ADC0_PTCXY30 (_UL_(1) << 0) +#define PIN_PB01B_ADC0_PTCXY31 _L_(33) /**< \brief ADC0 signal: PTCXY31 on PB01 mux B */ +#define MUX_PB01B_ADC0_PTCXY31 _L_(1) +#define PINMUX_PB01B_ADC0_PTCXY31 ((PIN_PB01B_ADC0_PTCXY31 << 16) | MUX_PB01B_ADC0_PTCXY31) +#define PORT_PB01B_ADC0_PTCXY31 (_UL_(1) << 1) +/* ========== PORT definition for ADC1 peripheral ========== */ +#define PIN_PB08B_ADC1_AIN0 _L_(40) /**< \brief ADC1 signal: AIN0 on PB08 mux B */ +#define MUX_PB08B_ADC1_AIN0 _L_(1) +#define PINMUX_PB08B_ADC1_AIN0 ((PIN_PB08B_ADC1_AIN0 << 16) | MUX_PB08B_ADC1_AIN0) +#define PORT_PB08B_ADC1_AIN0 (_UL_(1) << 8) +#define PIN_PB09B_ADC1_AIN1 _L_(41) /**< \brief ADC1 signal: AIN1 on PB09 mux B */ +#define MUX_PB09B_ADC1_AIN1 _L_(1) +#define PINMUX_PB09B_ADC1_AIN1 ((PIN_PB09B_ADC1_AIN1 << 16) | MUX_PB09B_ADC1_AIN1) +#define PORT_PB09B_ADC1_AIN1 (_UL_(1) << 9) +#define PIN_PA08B_ADC1_AIN2 _L_(8) /**< \brief ADC1 signal: AIN2 on PA08 mux B */ +#define MUX_PA08B_ADC1_AIN2 _L_(1) +#define PINMUX_PA08B_ADC1_AIN2 ((PIN_PA08B_ADC1_AIN2 << 16) | MUX_PA08B_ADC1_AIN2) +#define PORT_PA08B_ADC1_AIN2 (_UL_(1) << 8) +#define PIN_PA09B_ADC1_AIN3 _L_(9) /**< \brief ADC1 signal: AIN3 on PA09 mux B */ +#define MUX_PA09B_ADC1_AIN3 _L_(1) +#define PINMUX_PA09B_ADC1_AIN3 ((PIN_PA09B_ADC1_AIN3 << 16) | MUX_PA09B_ADC1_AIN3) +#define PORT_PA09B_ADC1_AIN3 (_UL_(1) << 9) +#define PIN_PC02B_ADC1_AIN4 _L_(66) /**< \brief ADC1 signal: AIN4 on PC02 mux B */ +#define MUX_PC02B_ADC1_AIN4 _L_(1) +#define PINMUX_PC02B_ADC1_AIN4 ((PIN_PC02B_ADC1_AIN4 << 16) | MUX_PC02B_ADC1_AIN4) +#define PORT_PC02B_ADC1_AIN4 (_UL_(1) << 2) +#define PIN_PC03B_ADC1_AIN5 _L_(67) /**< \brief ADC1 signal: AIN5 on PC03 mux B */ +#define MUX_PC03B_ADC1_AIN5 _L_(1) +#define PINMUX_PC03B_ADC1_AIN5 ((PIN_PC03B_ADC1_AIN5 << 16) | MUX_PC03B_ADC1_AIN5) +#define PORT_PC03B_ADC1_AIN5 (_UL_(1) << 3) +#define PIN_PB04B_ADC1_AIN6 _L_(36) /**< \brief ADC1 signal: AIN6 on PB04 mux B */ +#define MUX_PB04B_ADC1_AIN6 _L_(1) +#define PINMUX_PB04B_ADC1_AIN6 ((PIN_PB04B_ADC1_AIN6 << 16) | MUX_PB04B_ADC1_AIN6) +#define PORT_PB04B_ADC1_AIN6 (_UL_(1) << 4) +#define PIN_PB05B_ADC1_AIN7 _L_(37) /**< \brief ADC1 signal: AIN7 on PB05 mux B */ +#define MUX_PB05B_ADC1_AIN7 _L_(1) +#define PINMUX_PB05B_ADC1_AIN7 ((PIN_PB05B_ADC1_AIN7 << 16) | MUX_PB05B_ADC1_AIN7) +#define PORT_PB05B_ADC1_AIN7 (_UL_(1) << 5) +#define PIN_PB06B_ADC1_AIN8 _L_(38) /**< \brief ADC1 signal: AIN8 on PB06 mux B */ +#define MUX_PB06B_ADC1_AIN8 _L_(1) +#define PINMUX_PB06B_ADC1_AIN8 ((PIN_PB06B_ADC1_AIN8 << 16) | MUX_PB06B_ADC1_AIN8) +#define PORT_PB06B_ADC1_AIN8 (_UL_(1) << 6) +#define PIN_PB07B_ADC1_AIN9 _L_(39) /**< \brief ADC1 signal: AIN9 on PB07 mux B */ +#define MUX_PB07B_ADC1_AIN9 _L_(1) +#define PINMUX_PB07B_ADC1_AIN9 ((PIN_PB07B_ADC1_AIN9 << 16) | MUX_PB07B_ADC1_AIN9) +#define PORT_PB07B_ADC1_AIN9 (_UL_(1) << 7) +#define PIN_PC00B_ADC1_AIN10 _L_(64) /**< \brief ADC1 signal: AIN10 on PC00 mux B */ +#define MUX_PC00B_ADC1_AIN10 _L_(1) +#define PINMUX_PC00B_ADC1_AIN10 ((PIN_PC00B_ADC1_AIN10 << 16) | MUX_PC00B_ADC1_AIN10) +#define PORT_PC00B_ADC1_AIN10 (_UL_(1) << 0) +#define PIN_PC01B_ADC1_AIN11 _L_(65) /**< \brief ADC1 signal: AIN11 on PC01 mux B */ +#define MUX_PC01B_ADC1_AIN11 _L_(1) +#define PINMUX_PC01B_ADC1_AIN11 ((PIN_PC01B_ADC1_AIN11 << 16) | MUX_PC01B_ADC1_AIN11) +#define PORT_PC01B_ADC1_AIN11 (_UL_(1) << 1) +#define PIN_PC30B_ADC1_AIN12 _L_(94) /**< \brief ADC1 signal: AIN12 on PC30 mux B */ +#define MUX_PC30B_ADC1_AIN12 _L_(1) +#define PINMUX_PC30B_ADC1_AIN12 ((PIN_PC30B_ADC1_AIN12 << 16) | MUX_PC30B_ADC1_AIN12) +#define PORT_PC30B_ADC1_AIN12 (_UL_(1) << 30) +#define PIN_PC31B_ADC1_AIN13 _L_(95) /**< \brief ADC1 signal: AIN13 on PC31 mux B */ +#define MUX_PC31B_ADC1_AIN13 _L_(1) +#define PINMUX_PC31B_ADC1_AIN13 ((PIN_PC31B_ADC1_AIN13 << 16) | MUX_PC31B_ADC1_AIN13) +#define PORT_PC31B_ADC1_AIN13 (_UL_(1) << 31) +#define PIN_PD00B_ADC1_AIN14 _L_(96) /**< \brief ADC1 signal: AIN14 on PD00 mux B */ +#define MUX_PD00B_ADC1_AIN14 _L_(1) +#define PINMUX_PD00B_ADC1_AIN14 ((PIN_PD00B_ADC1_AIN14 << 16) | MUX_PD00B_ADC1_AIN14) +#define PORT_PD00B_ADC1_AIN14 (_UL_(1) << 0) +#define PIN_PD01B_ADC1_AIN15 _L_(97) /**< \brief ADC1 signal: AIN15 on PD01 mux B */ +#define MUX_PD01B_ADC1_AIN15 _L_(1) +#define PINMUX_PD01B_ADC1_AIN15 ((PIN_PD01B_ADC1_AIN15 << 16) | MUX_PD01B_ADC1_AIN15) +#define PORT_PD01B_ADC1_AIN15 (_UL_(1) << 1) +/* ========== PORT definition for DAC peripheral ========== */ +#define PIN_PA02B_DAC_VOUT0 _L_(2) /**< \brief DAC signal: VOUT0 on PA02 mux B */ +#define MUX_PA02B_DAC_VOUT0 _L_(1) +#define PINMUX_PA02B_DAC_VOUT0 ((PIN_PA02B_DAC_VOUT0 << 16) | MUX_PA02B_DAC_VOUT0) +#define PORT_PA02B_DAC_VOUT0 (_UL_(1) << 2) +#define PIN_PA05B_DAC_VOUT1 _L_(5) /**< \brief DAC signal: VOUT1 on PA05 mux B */ +#define MUX_PA05B_DAC_VOUT1 _L_(1) +#define PINMUX_PA05B_DAC_VOUT1 ((PIN_PA05B_DAC_VOUT1 << 16) | MUX_PA05B_DAC_VOUT1) +#define PORT_PA05B_DAC_VOUT1 (_UL_(1) << 5) +/* ========== PORT definition for I2S peripheral ========== */ +#define PIN_PA09J_I2S_FS0 _L_(9) /**< \brief I2S signal: FS0 on PA09 mux J */ +#define MUX_PA09J_I2S_FS0 _L_(9) +#define PINMUX_PA09J_I2S_FS0 ((PIN_PA09J_I2S_FS0 << 16) | MUX_PA09J_I2S_FS0) +#define PORT_PA09J_I2S_FS0 (_UL_(1) << 9) +#define PIN_PA20J_I2S_FS0 _L_(20) /**< \brief I2S signal: FS0 on PA20 mux J */ +#define MUX_PA20J_I2S_FS0 _L_(9) +#define PINMUX_PA20J_I2S_FS0 ((PIN_PA20J_I2S_FS0 << 16) | MUX_PA20J_I2S_FS0) +#define PORT_PA20J_I2S_FS0 (_UL_(1) << 20) +#define PIN_PA23J_I2S_FS1 _L_(23) /**< \brief I2S signal: FS1 on PA23 mux J */ +#define MUX_PA23J_I2S_FS1 _L_(9) +#define PINMUX_PA23J_I2S_FS1 ((PIN_PA23J_I2S_FS1 << 16) | MUX_PA23J_I2S_FS1) +#define PORT_PA23J_I2S_FS1 (_UL_(1) << 23) +#define PIN_PB11J_I2S_FS1 _L_(43) /**< \brief I2S signal: FS1 on PB11 mux J */ +#define MUX_PB11J_I2S_FS1 _L_(9) +#define PINMUX_PB11J_I2S_FS1 ((PIN_PB11J_I2S_FS1 << 16) | MUX_PB11J_I2S_FS1) +#define PORT_PB11J_I2S_FS1 (_UL_(1) << 11) +#define PIN_PA08J_I2S_MCK0 _L_(8) /**< \brief I2S signal: MCK0 on PA08 mux J */ +#define MUX_PA08J_I2S_MCK0 _L_(9) +#define PINMUX_PA08J_I2S_MCK0 ((PIN_PA08J_I2S_MCK0 << 16) | MUX_PA08J_I2S_MCK0) +#define PORT_PA08J_I2S_MCK0 (_UL_(1) << 8) +#define PIN_PB17J_I2S_MCK0 _L_(49) /**< \brief I2S signal: MCK0 on PB17 mux J */ +#define MUX_PB17J_I2S_MCK0 _L_(9) +#define PINMUX_PB17J_I2S_MCK0 ((PIN_PB17J_I2S_MCK0 << 16) | MUX_PB17J_I2S_MCK0) +#define PORT_PB17J_I2S_MCK0 (_UL_(1) << 17) +#define PIN_PB29J_I2S_MCK1 _L_(61) /**< \brief I2S signal: MCK1 on PB29 mux J */ +#define MUX_PB29J_I2S_MCK1 _L_(9) +#define PINMUX_PB29J_I2S_MCK1 ((PIN_PB29J_I2S_MCK1 << 16) | MUX_PB29J_I2S_MCK1) +#define PORT_PB29J_I2S_MCK1 (_UL_(1) << 29) +#define PIN_PB13J_I2S_MCK1 _L_(45) /**< \brief I2S signal: MCK1 on PB13 mux J */ +#define MUX_PB13J_I2S_MCK1 _L_(9) +#define PINMUX_PB13J_I2S_MCK1 ((PIN_PB13J_I2S_MCK1 << 16) | MUX_PB13J_I2S_MCK1) +#define PORT_PB13J_I2S_MCK1 (_UL_(1) << 13) +#define PIN_PA10J_I2S_SCK0 _L_(10) /**< \brief I2S signal: SCK0 on PA10 mux J */ +#define MUX_PA10J_I2S_SCK0 _L_(9) +#define PINMUX_PA10J_I2S_SCK0 ((PIN_PA10J_I2S_SCK0 << 16) | MUX_PA10J_I2S_SCK0) +#define PORT_PA10J_I2S_SCK0 (_UL_(1) << 10) +#define PIN_PB16J_I2S_SCK0 _L_(48) /**< \brief I2S signal: SCK0 on PB16 mux J */ +#define MUX_PB16J_I2S_SCK0 _L_(9) +#define PINMUX_PB16J_I2S_SCK0 ((PIN_PB16J_I2S_SCK0 << 16) | MUX_PB16J_I2S_SCK0) +#define PORT_PB16J_I2S_SCK0 (_UL_(1) << 16) +#define PIN_PB28J_I2S_SCK1 _L_(60) /**< \brief I2S signal: SCK1 on PB28 mux J */ +#define MUX_PB28J_I2S_SCK1 _L_(9) +#define PINMUX_PB28J_I2S_SCK1 ((PIN_PB28J_I2S_SCK1 << 16) | MUX_PB28J_I2S_SCK1) +#define PORT_PB28J_I2S_SCK1 (_UL_(1) << 28) +#define PIN_PB12J_I2S_SCK1 _L_(44) /**< \brief I2S signal: SCK1 on PB12 mux J */ +#define MUX_PB12J_I2S_SCK1 _L_(9) +#define PINMUX_PB12J_I2S_SCK1 ((PIN_PB12J_I2S_SCK1 << 16) | MUX_PB12J_I2S_SCK1) +#define PORT_PB12J_I2S_SCK1 (_UL_(1) << 12) +#define PIN_PA22J_I2S_SDI _L_(22) /**< \brief I2S signal: SDI on PA22 mux J */ +#define MUX_PA22J_I2S_SDI _L_(9) +#define PINMUX_PA22J_I2S_SDI ((PIN_PA22J_I2S_SDI << 16) | MUX_PA22J_I2S_SDI) +#define PORT_PA22J_I2S_SDI (_UL_(1) << 22) +#define PIN_PB10J_I2S_SDI _L_(42) /**< \brief I2S signal: SDI on PB10 mux J */ +#define MUX_PB10J_I2S_SDI _L_(9) +#define PINMUX_PB10J_I2S_SDI ((PIN_PB10J_I2S_SDI << 16) | MUX_PB10J_I2S_SDI) +#define PORT_PB10J_I2S_SDI (_UL_(1) << 10) +#define PIN_PA11J_I2S_SDO _L_(11) /**< \brief I2S signal: SDO on PA11 mux J */ +#define MUX_PA11J_I2S_SDO _L_(9) +#define PINMUX_PA11J_I2S_SDO ((PIN_PA11J_I2S_SDO << 16) | MUX_PA11J_I2S_SDO) +#define PORT_PA11J_I2S_SDO (_UL_(1) << 11) +#define PIN_PA21J_I2S_SDO _L_(21) /**< \brief I2S signal: SDO on PA21 mux J */ +#define MUX_PA21J_I2S_SDO _L_(9) +#define PINMUX_PA21J_I2S_SDO ((PIN_PA21J_I2S_SDO << 16) | MUX_PA21J_I2S_SDO) +#define PORT_PA21J_I2S_SDO (_UL_(1) << 21) +/* ========== PORT definition for PCC peripheral ========== */ +#define PIN_PA14K_PCC_CLK _L_(14) /**< \brief PCC signal: CLK on PA14 mux K */ +#define MUX_PA14K_PCC_CLK _L_(10) +#define PINMUX_PA14K_PCC_CLK ((PIN_PA14K_PCC_CLK << 16) | MUX_PA14K_PCC_CLK) +#define PORT_PA14K_PCC_CLK (_UL_(1) << 14) +#define PIN_PA16K_PCC_DATA0 _L_(16) /**< \brief PCC signal: DATA0 on PA16 mux K */ +#define MUX_PA16K_PCC_DATA0 _L_(10) +#define PINMUX_PA16K_PCC_DATA0 ((PIN_PA16K_PCC_DATA0 << 16) | MUX_PA16K_PCC_DATA0) +#define PORT_PA16K_PCC_DATA0 (_UL_(1) << 16) +#define PIN_PA17K_PCC_DATA1 _L_(17) /**< \brief PCC signal: DATA1 on PA17 mux K */ +#define MUX_PA17K_PCC_DATA1 _L_(10) +#define PINMUX_PA17K_PCC_DATA1 ((PIN_PA17K_PCC_DATA1 << 16) | MUX_PA17K_PCC_DATA1) +#define PORT_PA17K_PCC_DATA1 (_UL_(1) << 17) +#define PIN_PA18K_PCC_DATA2 _L_(18) /**< \brief PCC signal: DATA2 on PA18 mux K */ +#define MUX_PA18K_PCC_DATA2 _L_(10) +#define PINMUX_PA18K_PCC_DATA2 ((PIN_PA18K_PCC_DATA2 << 16) | MUX_PA18K_PCC_DATA2) +#define PORT_PA18K_PCC_DATA2 (_UL_(1) << 18) +#define PIN_PA19K_PCC_DATA3 _L_(19) /**< \brief PCC signal: DATA3 on PA19 mux K */ +#define MUX_PA19K_PCC_DATA3 _L_(10) +#define PINMUX_PA19K_PCC_DATA3 ((PIN_PA19K_PCC_DATA3 << 16) | MUX_PA19K_PCC_DATA3) +#define PORT_PA19K_PCC_DATA3 (_UL_(1) << 19) +#define PIN_PA20K_PCC_DATA4 _L_(20) /**< \brief PCC signal: DATA4 on PA20 mux K */ +#define MUX_PA20K_PCC_DATA4 _L_(10) +#define PINMUX_PA20K_PCC_DATA4 ((PIN_PA20K_PCC_DATA4 << 16) | MUX_PA20K_PCC_DATA4) +#define PORT_PA20K_PCC_DATA4 (_UL_(1) << 20) +#define PIN_PA21K_PCC_DATA5 _L_(21) /**< \brief PCC signal: DATA5 on PA21 mux K */ +#define MUX_PA21K_PCC_DATA5 _L_(10) +#define PINMUX_PA21K_PCC_DATA5 ((PIN_PA21K_PCC_DATA5 << 16) | MUX_PA21K_PCC_DATA5) +#define PORT_PA21K_PCC_DATA5 (_UL_(1) << 21) +#define PIN_PA22K_PCC_DATA6 _L_(22) /**< \brief PCC signal: DATA6 on PA22 mux K */ +#define MUX_PA22K_PCC_DATA6 _L_(10) +#define PINMUX_PA22K_PCC_DATA6 ((PIN_PA22K_PCC_DATA6 << 16) | MUX_PA22K_PCC_DATA6) +#define PORT_PA22K_PCC_DATA6 (_UL_(1) << 22) +#define PIN_PA23K_PCC_DATA7 _L_(23) /**< \brief PCC signal: DATA7 on PA23 mux K */ +#define MUX_PA23K_PCC_DATA7 _L_(10) +#define PINMUX_PA23K_PCC_DATA7 ((PIN_PA23K_PCC_DATA7 << 16) | MUX_PA23K_PCC_DATA7) +#define PORT_PA23K_PCC_DATA7 (_UL_(1) << 23) +#define PIN_PB14K_PCC_DATA8 _L_(46) /**< \brief PCC signal: DATA8 on PB14 mux K */ +#define MUX_PB14K_PCC_DATA8 _L_(10) +#define PINMUX_PB14K_PCC_DATA8 ((PIN_PB14K_PCC_DATA8 << 16) | MUX_PB14K_PCC_DATA8) +#define PORT_PB14K_PCC_DATA8 (_UL_(1) << 14) +#define PIN_PB15K_PCC_DATA9 _L_(47) /**< \brief PCC signal: DATA9 on PB15 mux K */ +#define MUX_PB15K_PCC_DATA9 _L_(10) +#define PINMUX_PB15K_PCC_DATA9 ((PIN_PB15K_PCC_DATA9 << 16) | MUX_PB15K_PCC_DATA9) +#define PORT_PB15K_PCC_DATA9 (_UL_(1) << 15) +#define PIN_PC12K_PCC_DATA10 _L_(76) /**< \brief PCC signal: DATA10 on PC12 mux K */ +#define MUX_PC12K_PCC_DATA10 _L_(10) +#define PINMUX_PC12K_PCC_DATA10 ((PIN_PC12K_PCC_DATA10 << 16) | MUX_PC12K_PCC_DATA10) +#define PORT_PC12K_PCC_DATA10 (_UL_(1) << 12) +#define PIN_PC13K_PCC_DATA11 _L_(77) /**< \brief PCC signal: DATA11 on PC13 mux K */ +#define MUX_PC13K_PCC_DATA11 _L_(10) +#define PINMUX_PC13K_PCC_DATA11 ((PIN_PC13K_PCC_DATA11 << 16) | MUX_PC13K_PCC_DATA11) +#define PORT_PC13K_PCC_DATA11 (_UL_(1) << 13) +#define PIN_PC14K_PCC_DATA12 _L_(78) /**< \brief PCC signal: DATA12 on PC14 mux K */ +#define MUX_PC14K_PCC_DATA12 _L_(10) +#define PINMUX_PC14K_PCC_DATA12 ((PIN_PC14K_PCC_DATA12 << 16) | MUX_PC14K_PCC_DATA12) +#define PORT_PC14K_PCC_DATA12 (_UL_(1) << 14) +#define PIN_PC15K_PCC_DATA13 _L_(79) /**< \brief PCC signal: DATA13 on PC15 mux K */ +#define MUX_PC15K_PCC_DATA13 _L_(10) +#define PINMUX_PC15K_PCC_DATA13 ((PIN_PC15K_PCC_DATA13 << 16) | MUX_PC15K_PCC_DATA13) +#define PORT_PC15K_PCC_DATA13 (_UL_(1) << 15) +#define PIN_PA12K_PCC_DEN1 _L_(12) /**< \brief PCC signal: DEN1 on PA12 mux K */ +#define MUX_PA12K_PCC_DEN1 _L_(10) +#define PINMUX_PA12K_PCC_DEN1 ((PIN_PA12K_PCC_DEN1 << 16) | MUX_PA12K_PCC_DEN1) +#define PORT_PA12K_PCC_DEN1 (_UL_(1) << 12) +#define PIN_PA13K_PCC_DEN2 _L_(13) /**< \brief PCC signal: DEN2 on PA13 mux K */ +#define MUX_PA13K_PCC_DEN2 _L_(10) +#define PINMUX_PA13K_PCC_DEN2 ((PIN_PA13K_PCC_DEN2 << 16) | MUX_PA13K_PCC_DEN2) +#define PORT_PA13K_PCC_DEN2 (_UL_(1) << 13) +/* ========== PORT definition for SDHC0 peripheral ========== */ +#define PIN_PA06I_SDHC0_SDCD _L_(6) /**< \brief SDHC0 signal: SDCD on PA06 mux I */ +#define MUX_PA06I_SDHC0_SDCD _L_(8) +#define PINMUX_PA06I_SDHC0_SDCD ((PIN_PA06I_SDHC0_SDCD << 16) | MUX_PA06I_SDHC0_SDCD) +#define PORT_PA06I_SDHC0_SDCD (_UL_(1) << 6) +#define PIN_PA12I_SDHC0_SDCD _L_(12) /**< \brief SDHC0 signal: SDCD on PA12 mux I */ +#define MUX_PA12I_SDHC0_SDCD _L_(8) +#define PINMUX_PA12I_SDHC0_SDCD ((PIN_PA12I_SDHC0_SDCD << 16) | MUX_PA12I_SDHC0_SDCD) +#define PORT_PA12I_SDHC0_SDCD (_UL_(1) << 12) +#define PIN_PB12I_SDHC0_SDCD _L_(44) /**< \brief SDHC0 signal: SDCD on PB12 mux I */ +#define MUX_PB12I_SDHC0_SDCD _L_(8) +#define PINMUX_PB12I_SDHC0_SDCD ((PIN_PB12I_SDHC0_SDCD << 16) | MUX_PB12I_SDHC0_SDCD) +#define PORT_PB12I_SDHC0_SDCD (_UL_(1) << 12) +#define PIN_PC06I_SDHC0_SDCD _L_(70) /**< \brief SDHC0 signal: SDCD on PC06 mux I */ +#define MUX_PC06I_SDHC0_SDCD _L_(8) +#define PINMUX_PC06I_SDHC0_SDCD ((PIN_PC06I_SDHC0_SDCD << 16) | MUX_PC06I_SDHC0_SDCD) +#define PORT_PC06I_SDHC0_SDCD (_UL_(1) << 6) +#define PIN_PB11I_SDHC0_SDCK _L_(43) /**< \brief SDHC0 signal: SDCK on PB11 mux I */ +#define MUX_PB11I_SDHC0_SDCK _L_(8) +#define PINMUX_PB11I_SDHC0_SDCK ((PIN_PB11I_SDHC0_SDCK << 16) | MUX_PB11I_SDHC0_SDCK) +#define PORT_PB11I_SDHC0_SDCK (_UL_(1) << 11) +#define PIN_PA08I_SDHC0_SDCMD _L_(8) /**< \brief SDHC0 signal: SDCMD on PA08 mux I */ +#define MUX_PA08I_SDHC0_SDCMD _L_(8) +#define PINMUX_PA08I_SDHC0_SDCMD ((PIN_PA08I_SDHC0_SDCMD << 16) | MUX_PA08I_SDHC0_SDCMD) +#define PORT_PA08I_SDHC0_SDCMD (_UL_(1) << 8) +#define PIN_PA09I_SDHC0_SDDAT0 _L_(9) /**< \brief SDHC0 signal: SDDAT0 on PA09 mux I */ +#define MUX_PA09I_SDHC0_SDDAT0 _L_(8) +#define PINMUX_PA09I_SDHC0_SDDAT0 ((PIN_PA09I_SDHC0_SDDAT0 << 16) | MUX_PA09I_SDHC0_SDDAT0) +#define PORT_PA09I_SDHC0_SDDAT0 (_UL_(1) << 9) +#define PIN_PA10I_SDHC0_SDDAT1 _L_(10) /**< \brief SDHC0 signal: SDDAT1 on PA10 mux I */ +#define MUX_PA10I_SDHC0_SDDAT1 _L_(8) +#define PINMUX_PA10I_SDHC0_SDDAT1 ((PIN_PA10I_SDHC0_SDDAT1 << 16) | MUX_PA10I_SDHC0_SDDAT1) +#define PORT_PA10I_SDHC0_SDDAT1 (_UL_(1) << 10) +#define PIN_PA11I_SDHC0_SDDAT2 _L_(11) /**< \brief SDHC0 signal: SDDAT2 on PA11 mux I */ +#define MUX_PA11I_SDHC0_SDDAT2 _L_(8) +#define PINMUX_PA11I_SDHC0_SDDAT2 ((PIN_PA11I_SDHC0_SDDAT2 << 16) | MUX_PA11I_SDHC0_SDDAT2) +#define PORT_PA11I_SDHC0_SDDAT2 (_UL_(1) << 11) +#define PIN_PB10I_SDHC0_SDDAT3 _L_(42) /**< \brief SDHC0 signal: SDDAT3 on PB10 mux I */ +#define MUX_PB10I_SDHC0_SDDAT3 _L_(8) +#define PINMUX_PB10I_SDHC0_SDDAT3 ((PIN_PB10I_SDHC0_SDDAT3 << 16) | MUX_PB10I_SDHC0_SDDAT3) +#define PORT_PB10I_SDHC0_SDDAT3 (_UL_(1) << 10) +#define PIN_PA07I_SDHC0_SDWP _L_(7) /**< \brief SDHC0 signal: SDWP on PA07 mux I */ +#define MUX_PA07I_SDHC0_SDWP _L_(8) +#define PINMUX_PA07I_SDHC0_SDWP ((PIN_PA07I_SDHC0_SDWP << 16) | MUX_PA07I_SDHC0_SDWP) +#define PORT_PA07I_SDHC0_SDWP (_UL_(1) << 7) +#define PIN_PA13I_SDHC0_SDWP _L_(13) /**< \brief SDHC0 signal: SDWP on PA13 mux I */ +#define MUX_PA13I_SDHC0_SDWP _L_(8) +#define PINMUX_PA13I_SDHC0_SDWP ((PIN_PA13I_SDHC0_SDWP << 16) | MUX_PA13I_SDHC0_SDWP) +#define PORT_PA13I_SDHC0_SDWP (_UL_(1) << 13) +#define PIN_PB13I_SDHC0_SDWP _L_(45) /**< \brief SDHC0 signal: SDWP on PB13 mux I */ +#define MUX_PB13I_SDHC0_SDWP _L_(8) +#define PINMUX_PB13I_SDHC0_SDWP ((PIN_PB13I_SDHC0_SDWP << 16) | MUX_PB13I_SDHC0_SDWP) +#define PORT_PB13I_SDHC0_SDWP (_UL_(1) << 13) +#define PIN_PC07I_SDHC0_SDWP _L_(71) /**< \brief SDHC0 signal: SDWP on PC07 mux I */ +#define MUX_PC07I_SDHC0_SDWP _L_(8) +#define PINMUX_PC07I_SDHC0_SDWP ((PIN_PC07I_SDHC0_SDWP << 16) | MUX_PC07I_SDHC0_SDWP) +#define PORT_PC07I_SDHC0_SDWP (_UL_(1) << 7) +/* ========== PORT definition for SDHC1 peripheral ========== */ +#define PIN_PB16I_SDHC1_SDCD _L_(48) /**< \brief SDHC1 signal: SDCD on PB16 mux I */ +#define MUX_PB16I_SDHC1_SDCD _L_(8) +#define PINMUX_PB16I_SDHC1_SDCD ((PIN_PB16I_SDHC1_SDCD << 16) | MUX_PB16I_SDHC1_SDCD) +#define PORT_PB16I_SDHC1_SDCD (_UL_(1) << 16) +#define PIN_PC20I_SDHC1_SDCD _L_(84) /**< \brief SDHC1 signal: SDCD on PC20 mux I */ +#define MUX_PC20I_SDHC1_SDCD _L_(8) +#define PINMUX_PC20I_SDHC1_SDCD ((PIN_PC20I_SDHC1_SDCD << 16) | MUX_PC20I_SDHC1_SDCD) +#define PORT_PC20I_SDHC1_SDCD (_UL_(1) << 20) +#define PIN_PD20I_SDHC1_SDCD _L_(116) /**< \brief SDHC1 signal: SDCD on PD20 mux I */ +#define MUX_PD20I_SDHC1_SDCD _L_(8) +#define PINMUX_PD20I_SDHC1_SDCD ((PIN_PD20I_SDHC1_SDCD << 16) | MUX_PD20I_SDHC1_SDCD) +#define PORT_PD20I_SDHC1_SDCD (_UL_(1) << 20) +#define PIN_PA21I_SDHC1_SDCK _L_(21) /**< \brief SDHC1 signal: SDCK on PA21 mux I */ +#define MUX_PA21I_SDHC1_SDCK _L_(8) +#define PINMUX_PA21I_SDHC1_SDCK ((PIN_PA21I_SDHC1_SDCK << 16) | MUX_PA21I_SDHC1_SDCK) +#define PORT_PA21I_SDHC1_SDCK (_UL_(1) << 21) +#define PIN_PA20I_SDHC1_SDCMD _L_(20) /**< \brief SDHC1 signal: SDCMD on PA20 mux I */ +#define MUX_PA20I_SDHC1_SDCMD _L_(8) +#define PINMUX_PA20I_SDHC1_SDCMD ((PIN_PA20I_SDHC1_SDCMD << 16) | MUX_PA20I_SDHC1_SDCMD) +#define PORT_PA20I_SDHC1_SDCMD (_UL_(1) << 20) +#define PIN_PB18I_SDHC1_SDDAT0 _L_(50) /**< \brief SDHC1 signal: SDDAT0 on PB18 mux I */ +#define MUX_PB18I_SDHC1_SDDAT0 _L_(8) +#define PINMUX_PB18I_SDHC1_SDDAT0 ((PIN_PB18I_SDHC1_SDDAT0 << 16) | MUX_PB18I_SDHC1_SDDAT0) +#define PORT_PB18I_SDHC1_SDDAT0 (_UL_(1) << 18) +#define PIN_PB19I_SDHC1_SDDAT1 _L_(51) /**< \brief SDHC1 signal: SDDAT1 on PB19 mux I */ +#define MUX_PB19I_SDHC1_SDDAT1 _L_(8) +#define PINMUX_PB19I_SDHC1_SDDAT1 ((PIN_PB19I_SDHC1_SDDAT1 << 16) | MUX_PB19I_SDHC1_SDDAT1) +#define PORT_PB19I_SDHC1_SDDAT1 (_UL_(1) << 19) +#define PIN_PB20I_SDHC1_SDDAT2 _L_(52) /**< \brief SDHC1 signal: SDDAT2 on PB20 mux I */ +#define MUX_PB20I_SDHC1_SDDAT2 _L_(8) +#define PINMUX_PB20I_SDHC1_SDDAT2 ((PIN_PB20I_SDHC1_SDDAT2 << 16) | MUX_PB20I_SDHC1_SDDAT2) +#define PORT_PB20I_SDHC1_SDDAT2 (_UL_(1) << 20) +#define PIN_PB21I_SDHC1_SDDAT3 _L_(53) /**< \brief SDHC1 signal: SDDAT3 on PB21 mux I */ +#define MUX_PB21I_SDHC1_SDDAT3 _L_(8) +#define PINMUX_PB21I_SDHC1_SDDAT3 ((PIN_PB21I_SDHC1_SDDAT3 << 16) | MUX_PB21I_SDHC1_SDDAT3) +#define PORT_PB21I_SDHC1_SDDAT3 (_UL_(1) << 21) +#define PIN_PB17I_SDHC1_SDWP _L_(49) /**< \brief SDHC1 signal: SDWP on PB17 mux I */ +#define MUX_PB17I_SDHC1_SDWP _L_(8) +#define PINMUX_PB17I_SDHC1_SDWP ((PIN_PB17I_SDHC1_SDWP << 16) | MUX_PB17I_SDHC1_SDWP) +#define PORT_PB17I_SDHC1_SDWP (_UL_(1) << 17) +#define PIN_PC21I_SDHC1_SDWP _L_(85) /**< \brief SDHC1 signal: SDWP on PC21 mux I */ +#define MUX_PC21I_SDHC1_SDWP _L_(8) +#define PINMUX_PC21I_SDHC1_SDWP ((PIN_PC21I_SDHC1_SDWP << 16) | MUX_PC21I_SDHC1_SDWP) +#define PORT_PC21I_SDHC1_SDWP (_UL_(1) << 21) +#define PIN_PD21I_SDHC1_SDWP _L_(117) /**< \brief SDHC1 signal: SDWP on PD21 mux I */ +#define MUX_PD21I_SDHC1_SDWP _L_(8) +#define PINMUX_PD21I_SDHC1_SDWP ((PIN_PD21I_SDHC1_SDWP << 16) | MUX_PD21I_SDHC1_SDWP) +#define PORT_PD21I_SDHC1_SDWP (_UL_(1) << 21) + +#endif /* _SAME54P19A_PIO_ */ diff --git a/arch/arm/SAME54/SAME54A/mcu/inc/pio/same54p20a.h b/arch/arm/SAME54/SAME54A/mcu/inc/pio/same54p20a.h index 7b9c4fe7..cc046809 100644 --- a/arch/arm/SAME54/SAME54A/mcu/inc/pio/same54p20a.h +++ b/arch/arm/SAME54/SAME54A/mcu/inc/pio/same54p20a.h @@ -1,3628 +1,3010 @@ -/** - * \brief Peripheral I/O description for SAME54P20A - * - * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries. - * - * Subject to your compliance with these terms, you may use Microchip software and any derivatives - * exclusively with Microchip products. It is your responsibility to comply with third party license - * terms applicable to your use of third party software (including open source software) that may - * accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, - * APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND - * FITNESS FOR A PARTICULAR PURPOSE. - * - * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF - * MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT - * EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - */ - -/* file generated from device description version 2020-03-12T17:27:04Z */ -#ifndef _SAME54P20A_GPIO_H_ -#define _SAME54P20A_GPIO_H_ - -/* ========== Peripheral I/O pin numbers ========== */ -#define PIN_PA00 ( 0 ) /**< Pin Number for PA00 */ -#define PIN_PA01 ( 1 ) /**< Pin Number for PA01 */ -#define PIN_PA02 ( 2 ) /**< Pin Number for PA02 */ -#define PIN_PA03 ( 3 ) /**< Pin Number for PA03 */ -#define PIN_PA04 ( 4 ) /**< Pin Number for PA04 */ -#define PIN_PA05 ( 5 ) /**< Pin Number for PA05 */ -#define PIN_PA06 ( 6 ) /**< Pin Number for PA06 */ -#define PIN_PA07 ( 7 ) /**< Pin Number for PA07 */ -#define PIN_PA08 ( 8 ) /**< Pin Number for PA08 */ -#define PIN_PA09 ( 9 ) /**< Pin Number for PA09 */ -#define PIN_PA10 ( 10 ) /**< Pin Number for PA10 */ -#define PIN_PA11 ( 11 ) /**< Pin Number for PA11 */ -#define PIN_PA12 ( 12 ) /**< Pin Number for PA12 */ -#define PIN_PA13 ( 13 ) /**< Pin Number for PA13 */ -#define PIN_PA14 ( 14 ) /**< Pin Number for PA14 */ -#define PIN_PA15 ( 15 ) /**< Pin Number for PA15 */ -#define PIN_PA16 ( 16 ) /**< Pin Number for PA16 */ -#define PIN_PA17 ( 17 ) /**< Pin Number for PA17 */ -#define PIN_PA18 ( 18 ) /**< Pin Number for PA18 */ -#define PIN_PA19 ( 19 ) /**< Pin Number for PA19 */ -#define PIN_PA20 ( 20 ) /**< Pin Number for PA20 */ -#define PIN_PA21 ( 21 ) /**< Pin Number for PA21 */ -#define PIN_PA22 ( 22 ) /**< Pin Number for PA22 */ -#define PIN_PA23 ( 23 ) /**< Pin Number for PA23 */ -#define PIN_PA24 ( 24 ) /**< Pin Number for PA24 */ -#define PIN_PA25 ( 25 ) /**< Pin Number for PA25 */ -#define PIN_PA27 ( 27 ) /**< Pin Number for PA27 */ -#define PIN_PA30 ( 30 ) /**< Pin Number for PA30 */ -#define PIN_PA31 ( 31 ) /**< Pin Number for PA31 */ -#define PIN_PB00 ( 32 ) /**< Pin Number for PB00 */ -#define PIN_PB01 ( 33 ) /**< Pin Number for PB01 */ -#define PIN_PB02 ( 34 ) /**< Pin Number for PB02 */ -#define PIN_PB03 ( 35 ) /**< Pin Number for PB03 */ -#define PIN_PB04 ( 36 ) /**< Pin Number for PB04 */ -#define PIN_PB05 ( 37 ) /**< Pin Number for PB05 */ -#define PIN_PB06 ( 38 ) /**< Pin Number for PB06 */ -#define PIN_PB07 ( 39 ) /**< Pin Number for PB07 */ -#define PIN_PB08 ( 40 ) /**< Pin Number for PB08 */ -#define PIN_PB09 ( 41 ) /**< Pin Number for PB09 */ -#define PIN_PB10 ( 42 ) /**< Pin Number for PB10 */ -#define PIN_PB11 ( 43 ) /**< Pin Number for PB11 */ -#define PIN_PB12 ( 44 ) /**< Pin Number for PB12 */ -#define PIN_PB13 ( 45 ) /**< Pin Number for PB13 */ -#define PIN_PB14 ( 46 ) /**< Pin Number for PB14 */ -#define PIN_PB15 ( 47 ) /**< Pin Number for PB15 */ -#define PIN_PB16 ( 48 ) /**< Pin Number for PB16 */ -#define PIN_PB17 ( 49 ) /**< Pin Number for PB17 */ -#define PIN_PB18 ( 50 ) /**< Pin Number for PB18 */ -#define PIN_PB19 ( 51 ) /**< Pin Number for PB19 */ -#define PIN_PB20 ( 52 ) /**< Pin Number for PB20 */ -#define PIN_PB21 ( 53 ) /**< Pin Number for PB21 */ -#define PIN_PB22 ( 54 ) /**< Pin Number for PB22 */ -#define PIN_PB23 ( 55 ) /**< Pin Number for PB23 */ -#define PIN_PB24 ( 56 ) /**< Pin Number for PB24 */ -#define PIN_PB25 ( 57 ) /**< Pin Number for PB25 */ -#define PIN_PB26 ( 58 ) /**< Pin Number for PB26 */ -#define PIN_PB27 ( 59 ) /**< Pin Number for PB27 */ -#define PIN_PB28 ( 60 ) /**< Pin Number for PB28 */ -#define PIN_PB29 ( 61 ) /**< Pin Number for PB29 */ -#define PIN_PB30 ( 62 ) /**< Pin Number for PB30 */ -#define PIN_PB31 ( 63 ) /**< Pin Number for PB31 */ -#define PIN_PC00 ( 64 ) /**< Pin Number for PC00 */ -#define PIN_PC01 ( 65 ) /**< Pin Number for PC01 */ -#define PIN_PC02 ( 66 ) /**< Pin Number for PC02 */ -#define PIN_PC03 ( 67 ) /**< Pin Number for PC03 */ -#define PIN_PC04 ( 68 ) /**< Pin Number for PC04 */ -#define PIN_PC05 ( 69 ) /**< Pin Number for PC05 */ -#define PIN_PC06 ( 70 ) /**< Pin Number for PC06 */ -#define PIN_PC07 ( 71 ) /**< Pin Number for PC07 */ -#define PIN_PC10 ( 74 ) /**< Pin Number for PC10 */ -#define PIN_PC11 ( 75 ) /**< Pin Number for PC11 */ -#define PIN_PC12 ( 76 ) /**< Pin Number for PC12 */ -#define PIN_PC13 ( 77 ) /**< Pin Number for PC13 */ -#define PIN_PC14 ( 78 ) /**< Pin Number for PC14 */ -#define PIN_PC15 ( 79 ) /**< Pin Number for PC15 */ -#define PIN_PC16 ( 80 ) /**< Pin Number for PC16 */ -#define PIN_PC17 ( 81 ) /**< Pin Number for PC17 */ -#define PIN_PC18 ( 82 ) /**< Pin Number for PC18 */ -#define PIN_PC19 ( 83 ) /**< Pin Number for PC19 */ -#define PIN_PC20 ( 84 ) /**< Pin Number for PC20 */ -#define PIN_PC21 ( 85 ) /**< Pin Number for PC21 */ -#define PIN_PC22 ( 86 ) /**< Pin Number for PC22 */ -#define PIN_PC23 ( 87 ) /**< Pin Number for PC23 */ -#define PIN_PC24 ( 88 ) /**< Pin Number for PC24 */ -#define PIN_PC25 ( 89 ) /**< Pin Number for PC25 */ -#define PIN_PC26 ( 90 ) /**< Pin Number for PC26 */ -#define PIN_PC27 ( 91 ) /**< Pin Number for PC27 */ -#define PIN_PC28 ( 92 ) /**< Pin Number for PC28 */ -#define PIN_PC30 ( 94 ) /**< Pin Number for PC30 */ -#define PIN_PC31 ( 95 ) /**< Pin Number for PC31 */ -#define PIN_PD00 ( 96 ) /**< Pin Number for PD00 */ -#define PIN_PD01 ( 97 ) /**< Pin Number for PD01 */ -#define PIN_PD08 (104 ) /**< Pin Number for PD08 */ -#define PIN_PD09 (105 ) /**< Pin Number for PD09 */ -#define PIN_PD10 (106 ) /**< Pin Number for PD10 */ -#define PIN_PD11 (107 ) /**< Pin Number for PD11 */ -#define PIN_PD12 (108 ) /**< Pin Number for PD12 */ -#define PIN_PD20 (116 ) /**< Pin Number for PD20 */ -#define PIN_PD21 (117 ) /**< Pin Number for PD21 */ - -/* ========== Peripheral I/O masks ========== */ -#define PORT_PA00 (_U_(1) << 0) /**< PORT mask for PA00 */ -#define PORT_PA01 (_U_(1) << 1) /**< PORT mask for PA01 */ -#define PORT_PA02 (_U_(1) << 2) /**< PORT mask for PA02 */ -#define PORT_PA03 (_U_(1) << 3) /**< PORT mask for PA03 */ -#define PORT_PA04 (_U_(1) << 4) /**< PORT mask for PA04 */ -#define PORT_PA05 (_U_(1) << 5) /**< PORT mask for PA05 */ -#define PORT_PA06 (_U_(1) << 6) /**< PORT mask for PA06 */ -#define PORT_PA07 (_U_(1) << 7) /**< PORT mask for PA07 */ -#define PORT_PA08 (_U_(1) << 8) /**< PORT mask for PA08 */ -#define PORT_PA09 (_U_(1) << 9) /**< PORT mask for PA09 */ -#define PORT_PA10 (_U_(1) << 10) /**< PORT mask for PA10 */ -#define PORT_PA11 (_U_(1) << 11) /**< PORT mask for PA11 */ -#define PORT_PA12 (_U_(1) << 12) /**< PORT mask for PA12 */ -#define PORT_PA13 (_U_(1) << 13) /**< PORT mask for PA13 */ -#define PORT_PA14 (_U_(1) << 14) /**< PORT mask for PA14 */ -#define PORT_PA15 (_U_(1) << 15) /**< PORT mask for PA15 */ -#define PORT_PA16 (_U_(1) << 16) /**< PORT mask for PA16 */ -#define PORT_PA17 (_U_(1) << 17) /**< PORT mask for PA17 */ -#define PORT_PA18 (_U_(1) << 18) /**< PORT mask for PA18 */ -#define PORT_PA19 (_U_(1) << 19) /**< PORT mask for PA19 */ -#define PORT_PA20 (_U_(1) << 20) /**< PORT mask for PA20 */ -#define PORT_PA21 (_U_(1) << 21) /**< PORT mask for PA21 */ -#define PORT_PA22 (_U_(1) << 22) /**< PORT mask for PA22 */ -#define PORT_PA23 (_U_(1) << 23) /**< PORT mask for PA23 */ -#define PORT_PA24 (_U_(1) << 24) /**< PORT mask for PA24 */ -#define PORT_PA25 (_U_(1) << 25) /**< PORT mask for PA25 */ -#define PORT_PA27 (_U_(1) << 27) /**< PORT mask for PA27 */ -#define PORT_PA30 (_U_(1) << 30) /**< PORT mask for PA30 */ -#define PORT_PA31 (_U_(1) << 31) /**< PORT mask for PA31 */ -#define PORT_PB00 (_U_(1) << 0) /**< PORT mask for PB00 */ -#define PORT_PB01 (_U_(1) << 1) /**< PORT mask for PB01 */ -#define PORT_PB02 (_U_(1) << 2) /**< PORT mask for PB02 */ -#define PORT_PB03 (_U_(1) << 3) /**< PORT mask for PB03 */ -#define PORT_PB04 (_U_(1) << 4) /**< PORT mask for PB04 */ -#define PORT_PB05 (_U_(1) << 5) /**< PORT mask for PB05 */ -#define PORT_PB06 (_U_(1) << 6) /**< PORT mask for PB06 */ -#define PORT_PB07 (_U_(1) << 7) /**< PORT mask for PB07 */ -#define PORT_PB08 (_U_(1) << 8) /**< PORT mask for PB08 */ -#define PORT_PB09 (_U_(1) << 9) /**< PORT mask for PB09 */ -#define PORT_PB10 (_U_(1) << 10) /**< PORT mask for PB10 */ -#define PORT_PB11 (_U_(1) << 11) /**< PORT mask for PB11 */ -#define PORT_PB12 (_U_(1) << 12) /**< PORT mask for PB12 */ -#define PORT_PB13 (_U_(1) << 13) /**< PORT mask for PB13 */ -#define PORT_PB14 (_U_(1) << 14) /**< PORT mask for PB14 */ -#define PORT_PB15 (_U_(1) << 15) /**< PORT mask for PB15 */ -#define PORT_PB16 (_U_(1) << 16) /**< PORT mask for PB16 */ -#define PORT_PB17 (_U_(1) << 17) /**< PORT mask for PB17 */ -#define PORT_PB18 (_U_(1) << 18) /**< PORT mask for PB18 */ -#define PORT_PB19 (_U_(1) << 19) /**< PORT mask for PB19 */ -#define PORT_PB20 (_U_(1) << 20) /**< PORT mask for PB20 */ -#define PORT_PB21 (_U_(1) << 21) /**< PORT mask for PB21 */ -#define PORT_PB22 (_U_(1) << 22) /**< PORT mask for PB22 */ -#define PORT_PB23 (_U_(1) << 23) /**< PORT mask for PB23 */ -#define PORT_PB24 (_U_(1) << 24) /**< PORT mask for PB24 */ -#define PORT_PB25 (_U_(1) << 25) /**< PORT mask for PB25 */ -#define PORT_PB26 (_U_(1) << 26) /**< PORT mask for PB26 */ -#define PORT_PB27 (_U_(1) << 27) /**< PORT mask for PB27 */ -#define PORT_PB28 (_U_(1) << 28) /**< PORT mask for PB28 */ -#define PORT_PB29 (_U_(1) << 29) /**< PORT mask for PB29 */ -#define PORT_PB30 (_U_(1) << 30) /**< PORT mask for PB30 */ -#define PORT_PB31 (_U_(1) << 31) /**< PORT mask for PB31 */ -#define PORT_PC00 (_U_(1) << 0) /**< PORT mask for PC00 */ -#define PORT_PC01 (_U_(1) << 1) /**< PORT mask for PC01 */ -#define PORT_PC02 (_U_(1) << 2) /**< PORT mask for PC02 */ -#define PORT_PC03 (_U_(1) << 3) /**< PORT mask for PC03 */ -#define PORT_PC04 (_U_(1) << 4) /**< PORT mask for PC04 */ -#define PORT_PC05 (_U_(1) << 5) /**< PORT mask for PC05 */ -#define PORT_PC06 (_U_(1) << 6) /**< PORT mask for PC06 */ -#define PORT_PC07 (_U_(1) << 7) /**< PORT mask for PC07 */ -#define PORT_PC10 (_U_(1) << 10) /**< PORT mask for PC10 */ -#define PORT_PC11 (_U_(1) << 11) /**< PORT mask for PC11 */ -#define PORT_PC12 (_U_(1) << 12) /**< PORT mask for PC12 */ -#define PORT_PC13 (_U_(1) << 13) /**< PORT mask for PC13 */ -#define PORT_PC14 (_U_(1) << 14) /**< PORT mask for PC14 */ -#define PORT_PC15 (_U_(1) << 15) /**< PORT mask for PC15 */ -#define PORT_PC16 (_U_(1) << 16) /**< PORT mask for PC16 */ -#define PORT_PC17 (_U_(1) << 17) /**< PORT mask for PC17 */ -#define PORT_PC18 (_U_(1) << 18) /**< PORT mask for PC18 */ -#define PORT_PC19 (_U_(1) << 19) /**< PORT mask for PC19 */ -#define PORT_PC20 (_U_(1) << 20) /**< PORT mask for PC20 */ -#define PORT_PC21 (_U_(1) << 21) /**< PORT mask for PC21 */ -#define PORT_PC22 (_U_(1) << 22) /**< PORT mask for PC22 */ -#define PORT_PC23 (_U_(1) << 23) /**< PORT mask for PC23 */ -#define PORT_PC24 (_U_(1) << 24) /**< PORT mask for PC24 */ -#define PORT_PC25 (_U_(1) << 25) /**< PORT mask for PC25 */ -#define PORT_PC26 (_U_(1) << 26) /**< PORT mask for PC26 */ -#define PORT_PC27 (_U_(1) << 27) /**< PORT mask for PC27 */ -#define PORT_PC28 (_U_(1) << 28) /**< PORT mask for PC28 */ -#define PORT_PC30 (_U_(1) << 30) /**< PORT mask for PC30 */ -#define PORT_PC31 (_U_(1) << 31) /**< PORT mask for PC31 */ -#define PORT_PD00 (_U_(1) << 0) /**< PORT mask for PD00 */ -#define PORT_PD01 (_U_(1) << 1) /**< PORT mask for PD01 */ -#define PORT_PD08 (_U_(1) << 8) /**< PORT mask for PD08 */ -#define PORT_PD09 (_U_(1) << 9) /**< PORT mask for PD09 */ -#define PORT_PD10 (_U_(1) << 10) /**< PORT mask for PD10 */ -#define PORT_PD11 (_U_(1) << 11) /**< PORT mask for PD11 */ -#define PORT_PD12 (_U_(1) << 12) /**< PORT mask for PD12 */ -#define PORT_PD20 (_U_(1) << 20) /**< PORT mask for PD20 */ -#define PORT_PD21 (_U_(1) << 21) /**< PORT mask for PD21 */ - -/* ========== PORT definition for AC peripheral ========== */ -#define PIN_PA04B_AC_AIN0 (4L) -#define MUX_PA04B_AC_AIN0 (1L) -#define PINMUX_PA04B_AC_AIN0 ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0) -#define PORT_PA04B_AC_AIN0 ((1UL) << 4) - -#define PIN_PA05B_AC_AIN1 (5L) -#define MUX_PA05B_AC_AIN1 (1L) -#define PINMUX_PA05B_AC_AIN1 ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1) -#define PORT_PA05B_AC_AIN1 ((1UL) << 5) - -#define PIN_PA06B_AC_AIN2 (6L) -#define MUX_PA06B_AC_AIN2 (1L) -#define PINMUX_PA06B_AC_AIN2 ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2) -#define PORT_PA06B_AC_AIN2 ((1UL) << 6) - -#define PIN_PA07B_AC_AIN3 (7L) -#define MUX_PA07B_AC_AIN3 (1L) -#define PINMUX_PA07B_AC_AIN3 ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3) -#define PORT_PA07B_AC_AIN3 ((1UL) << 7) - -#define PIN_PA12M_AC_CMP0 (12L) -#define MUX_PA12M_AC_CMP0 (12L) -#define PINMUX_PA12M_AC_CMP0 ((PIN_PA12M_AC_CMP0 << 16) | MUX_PA12M_AC_CMP0) -#define PORT_PA12M_AC_CMP0 ((1UL) << 12) - -#define PIN_PA18M_AC_CMP0 (18L) -#define MUX_PA18M_AC_CMP0 (12L) -#define PINMUX_PA18M_AC_CMP0 ((PIN_PA18M_AC_CMP0 << 16) | MUX_PA18M_AC_CMP0) -#define PORT_PA18M_AC_CMP0 ((1UL) << 18) - -#define PIN_PB24M_AC_CMP0 (56L) -#define MUX_PB24M_AC_CMP0 (12L) -#define PINMUX_PB24M_AC_CMP0 ((PIN_PB24M_AC_CMP0 << 16) | MUX_PB24M_AC_CMP0) -#define PORT_PB24M_AC_CMP0 ((1UL) << 24) - -#define PIN_PA13M_AC_CMP1 (13L) -#define MUX_PA13M_AC_CMP1 (12L) -#define PINMUX_PA13M_AC_CMP1 ((PIN_PA13M_AC_CMP1 << 16) | MUX_PA13M_AC_CMP1) -#define PORT_PA13M_AC_CMP1 ((1UL) << 13) - -#define PIN_PA19M_AC_CMP1 (19L) -#define MUX_PA19M_AC_CMP1 (12L) -#define PINMUX_PA19M_AC_CMP1 ((PIN_PA19M_AC_CMP1 << 16) | MUX_PA19M_AC_CMP1) -#define PORT_PA19M_AC_CMP1 ((1UL) << 19) - -#define PIN_PB25M_AC_CMP1 (57L) -#define MUX_PB25M_AC_CMP1 (12L) -#define PINMUX_PB25M_AC_CMP1 ((PIN_PB25M_AC_CMP1 << 16) | MUX_PB25M_AC_CMP1) -#define PORT_PB25M_AC_CMP1 ((1UL) << 25) - -/* ========== PORT definition for ADC0 peripheral ========== */ -#define PIN_PA02B_ADC0_AIN0 (2L) -#define MUX_PA02B_ADC0_AIN0 (1L) -#define PINMUX_PA02B_ADC0_AIN0 ((PIN_PA02B_ADC0_AIN0 << 16) | MUX_PA02B_ADC0_AIN0) -#define PORT_PA02B_ADC0_AIN0 ((1UL) << 2) - -#define PIN_PA03B_ADC0_AIN1 (3L) -#define MUX_PA03B_ADC0_AIN1 (1L) -#define PINMUX_PA03B_ADC0_AIN1 ((PIN_PA03B_ADC0_AIN1 << 16) | MUX_PA03B_ADC0_AIN1) -#define PORT_PA03B_ADC0_AIN1 ((1UL) << 3) - -#define PIN_PB08B_ADC0_AIN2 (40L) -#define MUX_PB08B_ADC0_AIN2 (1L) -#define PINMUX_PB08B_ADC0_AIN2 ((PIN_PB08B_ADC0_AIN2 << 16) | MUX_PB08B_ADC0_AIN2) -#define PORT_PB08B_ADC0_AIN2 ((1UL) << 8) - -#define PIN_PB09B_ADC0_AIN3 (41L) -#define MUX_PB09B_ADC0_AIN3 (1L) -#define PINMUX_PB09B_ADC0_AIN3 ((PIN_PB09B_ADC0_AIN3 << 16) | MUX_PB09B_ADC0_AIN3) -#define PORT_PB09B_ADC0_AIN3 ((1UL) << 9) - -#define PIN_PA04B_ADC0_AIN4 (4L) -#define MUX_PA04B_ADC0_AIN4 (1L) -#define PINMUX_PA04B_ADC0_AIN4 ((PIN_PA04B_ADC0_AIN4 << 16) | MUX_PA04B_ADC0_AIN4) -#define PORT_PA04B_ADC0_AIN4 ((1UL) << 4) - -#define PIN_PA05B_ADC0_AIN5 (5L) -#define MUX_PA05B_ADC0_AIN5 (1L) -#define PINMUX_PA05B_ADC0_AIN5 ((PIN_PA05B_ADC0_AIN5 << 16) | MUX_PA05B_ADC0_AIN5) -#define PORT_PA05B_ADC0_AIN5 ((1UL) << 5) - -#define PIN_PA06B_ADC0_AIN6 (6L) -#define MUX_PA06B_ADC0_AIN6 (1L) -#define PINMUX_PA06B_ADC0_AIN6 ((PIN_PA06B_ADC0_AIN6 << 16) | MUX_PA06B_ADC0_AIN6) -#define PORT_PA06B_ADC0_AIN6 ((1UL) << 6) - -#define PIN_PA07B_ADC0_AIN7 (7L) -#define MUX_PA07B_ADC0_AIN7 (1L) -#define PINMUX_PA07B_ADC0_AIN7 ((PIN_PA07B_ADC0_AIN7 << 16) | MUX_PA07B_ADC0_AIN7) -#define PORT_PA07B_ADC0_AIN7 ((1UL) << 7) - -#define PIN_PA08B_ADC0_AIN8 (8L) -#define MUX_PA08B_ADC0_AIN8 (1L) -#define PINMUX_PA08B_ADC0_AIN8 ((PIN_PA08B_ADC0_AIN8 << 16) | MUX_PA08B_ADC0_AIN8) -#define PORT_PA08B_ADC0_AIN8 ((1UL) << 8) - -#define PIN_PA09B_ADC0_AIN9 (9L) -#define MUX_PA09B_ADC0_AIN9 (1L) -#define PINMUX_PA09B_ADC0_AIN9 ((PIN_PA09B_ADC0_AIN9 << 16) | MUX_PA09B_ADC0_AIN9) -#define PORT_PA09B_ADC0_AIN9 ((1UL) << 9) - -#define PIN_PA10B_ADC0_AIN10 (10L) -#define MUX_PA10B_ADC0_AIN10 (1L) -#define PINMUX_PA10B_ADC0_AIN10 ((PIN_PA10B_ADC0_AIN10 << 16) | MUX_PA10B_ADC0_AIN10) -#define PORT_PA10B_ADC0_AIN10 ((1UL) << 10) - -#define PIN_PA11B_ADC0_AIN11 (11L) -#define MUX_PA11B_ADC0_AIN11 (1L) -#define PINMUX_PA11B_ADC0_AIN11 ((PIN_PA11B_ADC0_AIN11 << 16) | MUX_PA11B_ADC0_AIN11) -#define PORT_PA11B_ADC0_AIN11 ((1UL) << 11) - -#define PIN_PB00B_ADC0_AIN12 (32L) -#define MUX_PB00B_ADC0_AIN12 (1L) -#define PINMUX_PB00B_ADC0_AIN12 ((PIN_PB00B_ADC0_AIN12 << 16) | MUX_PB00B_ADC0_AIN12) -#define PORT_PB00B_ADC0_AIN12 ((1UL) << 0) - -#define PIN_PB01B_ADC0_AIN13 (33L) -#define MUX_PB01B_ADC0_AIN13 (1L) -#define PINMUX_PB01B_ADC0_AIN13 ((PIN_PB01B_ADC0_AIN13 << 16) | MUX_PB01B_ADC0_AIN13) -#define PORT_PB01B_ADC0_AIN13 ((1UL) << 1) - -#define PIN_PB02B_ADC0_AIN14 (34L) -#define MUX_PB02B_ADC0_AIN14 (1L) -#define PINMUX_PB02B_ADC0_AIN14 ((PIN_PB02B_ADC0_AIN14 << 16) | MUX_PB02B_ADC0_AIN14) -#define PORT_PB02B_ADC0_AIN14 ((1UL) << 2) - -#define PIN_PB03B_ADC0_AIN15 (35L) -#define MUX_PB03B_ADC0_AIN15 (1L) -#define PINMUX_PB03B_ADC0_AIN15 ((PIN_PB03B_ADC0_AIN15 << 16) | MUX_PB03B_ADC0_AIN15) -#define PORT_PB03B_ADC0_AIN15 ((1UL) << 3) - -#define PIN_PA03B_ADC0_VREFA (3L) -#define MUX_PA03B_ADC0_VREFA (1L) -#define PINMUX_PA03B_ADC0_VREFA ((PIN_PA03B_ADC0_VREFA << 16) | MUX_PA03B_ADC0_VREFA) -#define PORT_PA03B_ADC0_VREFA ((1UL) << 3) - -#define PIN_PA04B_ADC0_VREFB (4L) -#define MUX_PA04B_ADC0_VREFB (1L) -#define PINMUX_PA04B_ADC0_VREFB ((PIN_PA04B_ADC0_VREFB << 16) | MUX_PA04B_ADC0_VREFB) -#define PORT_PA04B_ADC0_VREFB ((1UL) << 4) - -#define PIN_PA06B_ADC0_VREFC (6L) -#define MUX_PA06B_ADC0_VREFC (1L) -#define PINMUX_PA06B_ADC0_VREFC ((PIN_PA06B_ADC0_VREFC << 16) | MUX_PA06B_ADC0_VREFC) -#define PORT_PA06B_ADC0_VREFC ((1UL) << 6) - -#define PIN_PA03B_ADC0_X0 (3L) -#define MUX_PA03B_ADC0_X0 (1L) -#define PINMUX_PA03B_ADC0_X0 ((PIN_PA03B_ADC0_X0 << 16) | MUX_PA03B_ADC0_X0) -#define PORT_PA03B_ADC0_X0 ((1UL) << 3) - -#define PIN_PB08B_ADC0_X1 (40L) -#define MUX_PB08B_ADC0_X1 (1L) -#define PINMUX_PB08B_ADC0_X1 ((PIN_PB08B_ADC0_X1 << 16) | MUX_PB08B_ADC0_X1) -#define PORT_PB08B_ADC0_X1 ((1UL) << 8) - -#define PIN_PB09B_ADC0_X2 (41L) -#define MUX_PB09B_ADC0_X2 (1L) -#define PINMUX_PB09B_ADC0_X2 ((PIN_PB09B_ADC0_X2 << 16) | MUX_PB09B_ADC0_X2) -#define PORT_PB09B_ADC0_X2 ((1UL) << 9) - -#define PIN_PA04B_ADC0_X3 (4L) -#define MUX_PA04B_ADC0_X3 (1L) -#define PINMUX_PA04B_ADC0_X3 ((PIN_PA04B_ADC0_X3 << 16) | MUX_PA04B_ADC0_X3) -#define PORT_PA04B_ADC0_X3 ((1UL) << 4) - -#define PIN_PA06B_ADC0_X4 (6L) -#define MUX_PA06B_ADC0_X4 (1L) -#define PINMUX_PA06B_ADC0_X4 ((PIN_PA06B_ADC0_X4 << 16) | MUX_PA06B_ADC0_X4) -#define PORT_PA06B_ADC0_X4 ((1UL) << 6) - -#define PIN_PA07B_ADC0_X5 (7L) -#define MUX_PA07B_ADC0_X5 (1L) -#define PINMUX_PA07B_ADC0_X5 ((PIN_PA07B_ADC0_X5 << 16) | MUX_PA07B_ADC0_X5) -#define PORT_PA07B_ADC0_X5 ((1UL) << 7) - -#define PIN_PA08B_ADC0_X6 (8L) -#define MUX_PA08B_ADC0_X6 (1L) -#define PINMUX_PA08B_ADC0_X6 ((PIN_PA08B_ADC0_X6 << 16) | MUX_PA08B_ADC0_X6) -#define PORT_PA08B_ADC0_X6 ((1UL) << 8) - -#define PIN_PA09B_ADC0_X7 (9L) -#define MUX_PA09B_ADC0_X7 (1L) -#define PINMUX_PA09B_ADC0_X7 ((PIN_PA09B_ADC0_X7 << 16) | MUX_PA09B_ADC0_X7) -#define PORT_PA09B_ADC0_X7 ((1UL) << 9) - -#define PIN_PA10B_ADC0_X8 (10L) -#define MUX_PA10B_ADC0_X8 (1L) -#define PINMUX_PA10B_ADC0_X8 ((PIN_PA10B_ADC0_X8 << 16) | MUX_PA10B_ADC0_X8) -#define PORT_PA10B_ADC0_X8 ((1UL) << 10) - -#define PIN_PA11B_ADC0_X9 (11L) -#define MUX_PA11B_ADC0_X9 (1L) -#define PINMUX_PA11B_ADC0_X9 ((PIN_PA11B_ADC0_X9 << 16) | MUX_PA11B_ADC0_X9) -#define PORT_PA11B_ADC0_X9 ((1UL) << 11) - -#define PIN_PA16B_ADC0_X10 (16L) -#define MUX_PA16B_ADC0_X10 (1L) -#define PINMUX_PA16B_ADC0_X10 ((PIN_PA16B_ADC0_X10 << 16) | MUX_PA16B_ADC0_X10) -#define PORT_PA16B_ADC0_X10 ((1UL) << 16) - -#define PIN_PA17B_ADC0_X11 (17L) -#define MUX_PA17B_ADC0_X11 (1L) -#define PINMUX_PA17B_ADC0_X11 ((PIN_PA17B_ADC0_X11 << 16) | MUX_PA17B_ADC0_X11) -#define PORT_PA17B_ADC0_X11 ((1UL) << 17) - -#define PIN_PA18B_ADC0_X12 (18L) -#define MUX_PA18B_ADC0_X12 (1L) -#define PINMUX_PA18B_ADC0_X12 ((PIN_PA18B_ADC0_X12 << 16) | MUX_PA18B_ADC0_X12) -#define PORT_PA18B_ADC0_X12 ((1UL) << 18) - -#define PIN_PA19B_ADC0_X13 (19L) -#define MUX_PA19B_ADC0_X13 (1L) -#define PINMUX_PA19B_ADC0_X13 ((PIN_PA19B_ADC0_X13 << 16) | MUX_PA19B_ADC0_X13) -#define PORT_PA19B_ADC0_X13 ((1UL) << 19) - -#define PIN_PA20B_ADC0_X14 (20L) -#define MUX_PA20B_ADC0_X14 (1L) -#define PINMUX_PA20B_ADC0_X14 ((PIN_PA20B_ADC0_X14 << 16) | MUX_PA20B_ADC0_X14) -#define PORT_PA20B_ADC0_X14 ((1UL) << 20) - -#define PIN_PA21B_ADC0_X15 (21L) -#define MUX_PA21B_ADC0_X15 (1L) -#define PINMUX_PA21B_ADC0_X15 ((PIN_PA21B_ADC0_X15 << 16) | MUX_PA21B_ADC0_X15) -#define PORT_PA21B_ADC0_X15 ((1UL) << 21) - -#define PIN_PA22B_ADC0_X16 (22L) -#define MUX_PA22B_ADC0_X16 (1L) -#define PINMUX_PA22B_ADC0_X16 ((PIN_PA22B_ADC0_X16 << 16) | MUX_PA22B_ADC0_X16) -#define PORT_PA22B_ADC0_X16 ((1UL) << 22) - -#define PIN_PA23B_ADC0_X17 (23L) -#define MUX_PA23B_ADC0_X17 (1L) -#define PINMUX_PA23B_ADC0_X17 ((PIN_PA23B_ADC0_X17 << 16) | MUX_PA23B_ADC0_X17) -#define PORT_PA23B_ADC0_X17 ((1UL) << 23) - -#define PIN_PA27B_ADC0_X18 (27L) -#define MUX_PA27B_ADC0_X18 (1L) -#define PINMUX_PA27B_ADC0_X18 ((PIN_PA27B_ADC0_X18 << 16) | MUX_PA27B_ADC0_X18) -#define PORT_PA27B_ADC0_X18 ((1UL) << 27) - -#define PIN_PA30B_ADC0_X19 (30L) -#define MUX_PA30B_ADC0_X19 (1L) -#define PINMUX_PA30B_ADC0_X19 ((PIN_PA30B_ADC0_X19 << 16) | MUX_PA30B_ADC0_X19) -#define PORT_PA30B_ADC0_X19 ((1UL) << 30) - -#define PIN_PB02B_ADC0_X20 (34L) -#define MUX_PB02B_ADC0_X20 (1L) -#define PINMUX_PB02B_ADC0_X20 ((PIN_PB02B_ADC0_X20 << 16) | MUX_PB02B_ADC0_X20) -#define PORT_PB02B_ADC0_X20 ((1UL) << 2) - -#define PIN_PB03B_ADC0_X21 (35L) -#define MUX_PB03B_ADC0_X21 (1L) -#define PINMUX_PB03B_ADC0_X21 ((PIN_PB03B_ADC0_X21 << 16) | MUX_PB03B_ADC0_X21) -#define PORT_PB03B_ADC0_X21 ((1UL) << 3) - -#define PIN_PB04B_ADC0_X22 (36L) -#define MUX_PB04B_ADC0_X22 (1L) -#define PINMUX_PB04B_ADC0_X22 ((PIN_PB04B_ADC0_X22 << 16) | MUX_PB04B_ADC0_X22) -#define PORT_PB04B_ADC0_X22 ((1UL) << 4) - -#define PIN_PB05B_ADC0_X23 (37L) -#define MUX_PB05B_ADC0_X23 (1L) -#define PINMUX_PB05B_ADC0_X23 ((PIN_PB05B_ADC0_X23 << 16) | MUX_PB05B_ADC0_X23) -#define PORT_PB05B_ADC0_X23 ((1UL) << 5) - -#define PIN_PB06B_ADC0_X24 (38L) -#define MUX_PB06B_ADC0_X24 (1L) -#define PINMUX_PB06B_ADC0_X24 ((PIN_PB06B_ADC0_X24 << 16) | MUX_PB06B_ADC0_X24) -#define PORT_PB06B_ADC0_X24 ((1UL) << 6) - -#define PIN_PB07B_ADC0_X25 (39L) -#define MUX_PB07B_ADC0_X25 (1L) -#define PINMUX_PB07B_ADC0_X25 ((PIN_PB07B_ADC0_X25 << 16) | MUX_PB07B_ADC0_X25) -#define PORT_PB07B_ADC0_X25 ((1UL) << 7) - -#define PIN_PB12B_ADC0_X26 (44L) -#define MUX_PB12B_ADC0_X26 (1L) -#define PINMUX_PB12B_ADC0_X26 ((PIN_PB12B_ADC0_X26 << 16) | MUX_PB12B_ADC0_X26) -#define PORT_PB12B_ADC0_X26 ((1UL) << 12) - -#define PIN_PB13B_ADC0_X27 (45L) -#define MUX_PB13B_ADC0_X27 (1L) -#define PINMUX_PB13B_ADC0_X27 ((PIN_PB13B_ADC0_X27 << 16) | MUX_PB13B_ADC0_X27) -#define PORT_PB13B_ADC0_X27 ((1UL) << 13) - -#define PIN_PB14B_ADC0_X28 (46L) -#define MUX_PB14B_ADC0_X28 (1L) -#define PINMUX_PB14B_ADC0_X28 ((PIN_PB14B_ADC0_X28 << 16) | MUX_PB14B_ADC0_X28) -#define PORT_PB14B_ADC0_X28 ((1UL) << 14) - -#define PIN_PB15B_ADC0_X29 (47L) -#define MUX_PB15B_ADC0_X29 (1L) -#define PINMUX_PB15B_ADC0_X29 ((PIN_PB15B_ADC0_X29 << 16) | MUX_PB15B_ADC0_X29) -#define PORT_PB15B_ADC0_X29 ((1UL) << 15) - -#define PIN_PB00B_ADC0_X30 (32L) -#define MUX_PB00B_ADC0_X30 (1L) -#define PINMUX_PB00B_ADC0_X30 ((PIN_PB00B_ADC0_X30 << 16) | MUX_PB00B_ADC0_X30) -#define PORT_PB00B_ADC0_X30 ((1UL) << 0) - -#define PIN_PB01B_ADC0_X31 (33L) -#define MUX_PB01B_ADC0_X31 (1L) -#define PINMUX_PB01B_ADC0_X31 ((PIN_PB01B_ADC0_X31 << 16) | MUX_PB01B_ADC0_X31) -#define PORT_PB01B_ADC0_X31 ((1UL) << 1) - -#define PIN_PA03B_ADC0_Y0 (3L) -#define MUX_PA03B_ADC0_Y0 (1L) -#define PINMUX_PA03B_ADC0_Y0 ((PIN_PA03B_ADC0_Y0 << 16) | MUX_PA03B_ADC0_Y0) -#define PORT_PA03B_ADC0_Y0 ((1UL) << 3) - -#define PIN_PB08B_ADC0_Y1 (40L) -#define MUX_PB08B_ADC0_Y1 (1L) -#define PINMUX_PB08B_ADC0_Y1 ((PIN_PB08B_ADC0_Y1 << 16) | MUX_PB08B_ADC0_Y1) -#define PORT_PB08B_ADC0_Y1 ((1UL) << 8) - -#define PIN_PB09B_ADC0_Y2 (41L) -#define MUX_PB09B_ADC0_Y2 (1L) -#define PINMUX_PB09B_ADC0_Y2 ((PIN_PB09B_ADC0_Y2 << 16) | MUX_PB09B_ADC0_Y2) -#define PORT_PB09B_ADC0_Y2 ((1UL) << 9) - -#define PIN_PA04B_ADC0_Y3 (4L) -#define MUX_PA04B_ADC0_Y3 (1L) -#define PINMUX_PA04B_ADC0_Y3 ((PIN_PA04B_ADC0_Y3 << 16) | MUX_PA04B_ADC0_Y3) -#define PORT_PA04B_ADC0_Y3 ((1UL) << 4) - -#define PIN_PA06B_ADC0_Y4 (6L) -#define MUX_PA06B_ADC0_Y4 (1L) -#define PINMUX_PA06B_ADC0_Y4 ((PIN_PA06B_ADC0_Y4 << 16) | MUX_PA06B_ADC0_Y4) -#define PORT_PA06B_ADC0_Y4 ((1UL) << 6) - -#define PIN_PA07B_ADC0_Y5 (7L) -#define MUX_PA07B_ADC0_Y5 (1L) -#define PINMUX_PA07B_ADC0_Y5 ((PIN_PA07B_ADC0_Y5 << 16) | MUX_PA07B_ADC0_Y5) -#define PORT_PA07B_ADC0_Y5 ((1UL) << 7) - -#define PIN_PA08B_ADC0_Y6 (8L) -#define MUX_PA08B_ADC0_Y6 (1L) -#define PINMUX_PA08B_ADC0_Y6 ((PIN_PA08B_ADC0_Y6 << 16) | MUX_PA08B_ADC0_Y6) -#define PORT_PA08B_ADC0_Y6 ((1UL) << 8) - -#define PIN_PA09B_ADC0_Y7 (9L) -#define MUX_PA09B_ADC0_Y7 (1L) -#define PINMUX_PA09B_ADC0_Y7 ((PIN_PA09B_ADC0_Y7 << 16) | MUX_PA09B_ADC0_Y7) -#define PORT_PA09B_ADC0_Y7 ((1UL) << 9) - -#define PIN_PA10B_ADC0_Y8 (10L) -#define MUX_PA10B_ADC0_Y8 (1L) -#define PINMUX_PA10B_ADC0_Y8 ((PIN_PA10B_ADC0_Y8 << 16) | MUX_PA10B_ADC0_Y8) -#define PORT_PA10B_ADC0_Y8 ((1UL) << 10) - -#define PIN_PA11B_ADC0_Y9 (11L) -#define MUX_PA11B_ADC0_Y9 (1L) -#define PINMUX_PA11B_ADC0_Y9 ((PIN_PA11B_ADC0_Y9 << 16) | MUX_PA11B_ADC0_Y9) -#define PORT_PA11B_ADC0_Y9 ((1UL) << 11) - -#define PIN_PA16B_ADC0_Y10 (16L) -#define MUX_PA16B_ADC0_Y10 (1L) -#define PINMUX_PA16B_ADC0_Y10 ((PIN_PA16B_ADC0_Y10 << 16) | MUX_PA16B_ADC0_Y10) -#define PORT_PA16B_ADC0_Y10 ((1UL) << 16) - -#define PIN_PA17B_ADC0_Y11 (17L) -#define MUX_PA17B_ADC0_Y11 (1L) -#define PINMUX_PA17B_ADC0_Y11 ((PIN_PA17B_ADC0_Y11 << 16) | MUX_PA17B_ADC0_Y11) -#define PORT_PA17B_ADC0_Y11 ((1UL) << 17) - -#define PIN_PA18B_ADC0_Y12 (18L) -#define MUX_PA18B_ADC0_Y12 (1L) -#define PINMUX_PA18B_ADC0_Y12 ((PIN_PA18B_ADC0_Y12 << 16) | MUX_PA18B_ADC0_Y12) -#define PORT_PA18B_ADC0_Y12 ((1UL) << 18) - -#define PIN_PA19B_ADC0_Y13 (19L) -#define MUX_PA19B_ADC0_Y13 (1L) -#define PINMUX_PA19B_ADC0_Y13 ((PIN_PA19B_ADC0_Y13 << 16) | MUX_PA19B_ADC0_Y13) -#define PORT_PA19B_ADC0_Y13 ((1UL) << 19) - -#define PIN_PA20B_ADC0_Y14 (20L) -#define MUX_PA20B_ADC0_Y14 (1L) -#define PINMUX_PA20B_ADC0_Y14 ((PIN_PA20B_ADC0_Y14 << 16) | MUX_PA20B_ADC0_Y14) -#define PORT_PA20B_ADC0_Y14 ((1UL) << 20) - -#define PIN_PA21B_ADC0_Y15 (21L) -#define MUX_PA21B_ADC0_Y15 (1L) -#define PINMUX_PA21B_ADC0_Y15 ((PIN_PA21B_ADC0_Y15 << 16) | MUX_PA21B_ADC0_Y15) -#define PORT_PA21B_ADC0_Y15 ((1UL) << 21) - -#define PIN_PA22B_ADC0_Y16 (22L) -#define MUX_PA22B_ADC0_Y16 (1L) -#define PINMUX_PA22B_ADC0_Y16 ((PIN_PA22B_ADC0_Y16 << 16) | MUX_PA22B_ADC0_Y16) -#define PORT_PA22B_ADC0_Y16 ((1UL) << 22) - -#define PIN_PA23B_ADC0_Y17 (23L) -#define MUX_PA23B_ADC0_Y17 (1L) -#define PINMUX_PA23B_ADC0_Y17 ((PIN_PA23B_ADC0_Y17 << 16) | MUX_PA23B_ADC0_Y17) -#define PORT_PA23B_ADC0_Y17 ((1UL) << 23) - -#define PIN_PA27B_ADC0_Y18 (27L) -#define MUX_PA27B_ADC0_Y18 (1L) -#define PINMUX_PA27B_ADC0_Y18 ((PIN_PA27B_ADC0_Y18 << 16) | MUX_PA27B_ADC0_Y18) -#define PORT_PA27B_ADC0_Y18 ((1UL) << 27) - -#define PIN_PA30B_ADC0_Y19 (30L) -#define MUX_PA30B_ADC0_Y19 (1L) -#define PINMUX_PA30B_ADC0_Y19 ((PIN_PA30B_ADC0_Y19 << 16) | MUX_PA30B_ADC0_Y19) -#define PORT_PA30B_ADC0_Y19 ((1UL) << 30) - -#define PIN_PB02B_ADC0_Y20 (34L) -#define MUX_PB02B_ADC0_Y20 (1L) -#define PINMUX_PB02B_ADC0_Y20 ((PIN_PB02B_ADC0_Y20 << 16) | MUX_PB02B_ADC0_Y20) -#define PORT_PB02B_ADC0_Y20 ((1UL) << 2) - -#define PIN_PB03B_ADC0_Y21 (35L) -#define MUX_PB03B_ADC0_Y21 (1L) -#define PINMUX_PB03B_ADC0_Y21 ((PIN_PB03B_ADC0_Y21 << 16) | MUX_PB03B_ADC0_Y21) -#define PORT_PB03B_ADC0_Y21 ((1UL) << 3) - -#define PIN_PB04B_ADC0_Y22 (36L) -#define MUX_PB04B_ADC0_Y22 (1L) -#define PINMUX_PB04B_ADC0_Y22 ((PIN_PB04B_ADC0_Y22 << 16) | MUX_PB04B_ADC0_Y22) -#define PORT_PB04B_ADC0_Y22 ((1UL) << 4) - -#define PIN_PB05B_ADC0_Y23 (37L) -#define MUX_PB05B_ADC0_Y23 (1L) -#define PINMUX_PB05B_ADC0_Y23 ((PIN_PB05B_ADC0_Y23 << 16) | MUX_PB05B_ADC0_Y23) -#define PORT_PB05B_ADC0_Y23 ((1UL) << 5) - -#define PIN_PB06B_ADC0_Y24 (38L) -#define MUX_PB06B_ADC0_Y24 (1L) -#define PINMUX_PB06B_ADC0_Y24 ((PIN_PB06B_ADC0_Y24 << 16) | MUX_PB06B_ADC0_Y24) -#define PORT_PB06B_ADC0_Y24 ((1UL) << 6) - -#define PIN_PB07B_ADC0_Y25 (39L) -#define MUX_PB07B_ADC0_Y25 (1L) -#define PINMUX_PB07B_ADC0_Y25 ((PIN_PB07B_ADC0_Y25 << 16) | MUX_PB07B_ADC0_Y25) -#define PORT_PB07B_ADC0_Y25 ((1UL) << 7) - -#define PIN_PB12B_ADC0_Y26 (44L) -#define MUX_PB12B_ADC0_Y26 (1L) -#define PINMUX_PB12B_ADC0_Y26 ((PIN_PB12B_ADC0_Y26 << 16) | MUX_PB12B_ADC0_Y26) -#define PORT_PB12B_ADC0_Y26 ((1UL) << 12) - -#define PIN_PB13B_ADC0_Y27 (45L) -#define MUX_PB13B_ADC0_Y27 (1L) -#define PINMUX_PB13B_ADC0_Y27 ((PIN_PB13B_ADC0_Y27 << 16) | MUX_PB13B_ADC0_Y27) -#define PORT_PB13B_ADC0_Y27 ((1UL) << 13) - -#define PIN_PB14B_ADC0_Y28 (46L) -#define MUX_PB14B_ADC0_Y28 (1L) -#define PINMUX_PB14B_ADC0_Y28 ((PIN_PB14B_ADC0_Y28 << 16) | MUX_PB14B_ADC0_Y28) -#define PORT_PB14B_ADC0_Y28 ((1UL) << 14) - -#define PIN_PB15B_ADC0_Y29 (47L) -#define MUX_PB15B_ADC0_Y29 (1L) -#define PINMUX_PB15B_ADC0_Y29 ((PIN_PB15B_ADC0_Y29 << 16) | MUX_PB15B_ADC0_Y29) -#define PORT_PB15B_ADC0_Y29 ((1UL) << 15) - -#define PIN_PB00B_ADC0_Y30 (32L) -#define MUX_PB00B_ADC0_Y30 (1L) -#define PINMUX_PB00B_ADC0_Y30 ((PIN_PB00B_ADC0_Y30 << 16) | MUX_PB00B_ADC0_Y30) -#define PORT_PB00B_ADC0_Y30 ((1UL) << 0) - -#define PIN_PB01B_ADC0_Y31 (33L) -#define MUX_PB01B_ADC0_Y31 (1L) -#define PINMUX_PB01B_ADC0_Y31 ((PIN_PB01B_ADC0_Y31 << 16) | MUX_PB01B_ADC0_Y31) -#define PORT_PB01B_ADC0_Y31 ((1UL) << 1) - -/* ========== PORT definition for ADC1 peripheral ========== */ -#define PIN_PB08B_ADC1_AIN0 (40L) -#define MUX_PB08B_ADC1_AIN0 (1L) -#define PINMUX_PB08B_ADC1_AIN0 ((PIN_PB08B_ADC1_AIN0 << 16) | MUX_PB08B_ADC1_AIN0) -#define PORT_PB08B_ADC1_AIN0 ((1UL) << 8) - -#define PIN_PB09B_ADC1_AIN1 (41L) -#define MUX_PB09B_ADC1_AIN1 (1L) -#define PINMUX_PB09B_ADC1_AIN1 ((PIN_PB09B_ADC1_AIN1 << 16) | MUX_PB09B_ADC1_AIN1) -#define PORT_PB09B_ADC1_AIN1 ((1UL) << 9) - -#define PIN_PA08B_ADC1_AIN2 (8L) -#define MUX_PA08B_ADC1_AIN2 (1L) -#define PINMUX_PA08B_ADC1_AIN2 ((PIN_PA08B_ADC1_AIN2 << 16) | MUX_PA08B_ADC1_AIN2) -#define PORT_PA08B_ADC1_AIN2 ((1UL) << 8) - -#define PIN_PA09B_ADC1_AIN3 (9L) -#define MUX_PA09B_ADC1_AIN3 (1L) -#define PINMUX_PA09B_ADC1_AIN3 ((PIN_PA09B_ADC1_AIN3 << 16) | MUX_PA09B_ADC1_AIN3) -#define PORT_PA09B_ADC1_AIN3 ((1UL) << 9) - -#define PIN_PC02B_ADC1_AIN4 (66L) -#define MUX_PC02B_ADC1_AIN4 (1L) -#define PINMUX_PC02B_ADC1_AIN4 ((PIN_PC02B_ADC1_AIN4 << 16) | MUX_PC02B_ADC1_AIN4) -#define PORT_PC02B_ADC1_AIN4 ((1UL) << 2) - -#define PIN_PC03B_ADC1_AIN5 (67L) -#define MUX_PC03B_ADC1_AIN5 (1L) -#define PINMUX_PC03B_ADC1_AIN5 ((PIN_PC03B_ADC1_AIN5 << 16) | MUX_PC03B_ADC1_AIN5) -#define PORT_PC03B_ADC1_AIN5 ((1UL) << 3) - -#define PIN_PB04B_ADC1_AIN6 (36L) -#define MUX_PB04B_ADC1_AIN6 (1L) -#define PINMUX_PB04B_ADC1_AIN6 ((PIN_PB04B_ADC1_AIN6 << 16) | MUX_PB04B_ADC1_AIN6) -#define PORT_PB04B_ADC1_AIN6 ((1UL) << 4) - -#define PIN_PB05B_ADC1_AIN7 (37L) -#define MUX_PB05B_ADC1_AIN7 (1L) -#define PINMUX_PB05B_ADC1_AIN7 ((PIN_PB05B_ADC1_AIN7 << 16) | MUX_PB05B_ADC1_AIN7) -#define PORT_PB05B_ADC1_AIN7 ((1UL) << 5) - -#define PIN_PB06B_ADC1_AIN8 (38L) -#define MUX_PB06B_ADC1_AIN8 (1L) -#define PINMUX_PB06B_ADC1_AIN8 ((PIN_PB06B_ADC1_AIN8 << 16) | MUX_PB06B_ADC1_AIN8) -#define PORT_PB06B_ADC1_AIN8 ((1UL) << 6) - -#define PIN_PB07B_ADC1_AIN9 (39L) -#define MUX_PB07B_ADC1_AIN9 (1L) -#define PINMUX_PB07B_ADC1_AIN9 ((PIN_PB07B_ADC1_AIN9 << 16) | MUX_PB07B_ADC1_AIN9) -#define PORT_PB07B_ADC1_AIN9 ((1UL) << 7) - -#define PIN_PC00B_ADC1_AIN10 (64L) -#define MUX_PC00B_ADC1_AIN10 (1L) -#define PINMUX_PC00B_ADC1_AIN10 ((PIN_PC00B_ADC1_AIN10 << 16) | MUX_PC00B_ADC1_AIN10) -#define PORT_PC00B_ADC1_AIN10 ((1UL) << 0) - -#define PIN_PC01B_ADC1_AIN11 (65L) -#define MUX_PC01B_ADC1_AIN11 (1L) -#define PINMUX_PC01B_ADC1_AIN11 ((PIN_PC01B_ADC1_AIN11 << 16) | MUX_PC01B_ADC1_AIN11) -#define PORT_PC01B_ADC1_AIN11 ((1UL) << 1) - -#define PIN_PC30B_ADC1_AIN12 (94L) -#define MUX_PC30B_ADC1_AIN12 (1L) -#define PINMUX_PC30B_ADC1_AIN12 ((PIN_PC30B_ADC1_AIN12 << 16) | MUX_PC30B_ADC1_AIN12) -#define PORT_PC30B_ADC1_AIN12 ((1UL) << 30) - -#define PIN_PC31B_ADC1_AIN13 (95L) -#define MUX_PC31B_ADC1_AIN13 (1L) -#define PINMUX_PC31B_ADC1_AIN13 ((PIN_PC31B_ADC1_AIN13 << 16) | MUX_PC31B_ADC1_AIN13) -#define PORT_PC31B_ADC1_AIN13 ((1UL) << 31) - -#define PIN_PD00B_ADC1_AIN14 (96L) -#define MUX_PD00B_ADC1_AIN14 (1L) -#define PINMUX_PD00B_ADC1_AIN14 ((PIN_PD00B_ADC1_AIN14 << 16) | MUX_PD00B_ADC1_AIN14) -#define PORT_PD00B_ADC1_AIN14 ((1UL) << 0) - -#define PIN_PD01B_ADC1_AIN15 (97L) -#define MUX_PD01B_ADC1_AIN15 (1L) -#define PINMUX_PD01B_ADC1_AIN15 ((PIN_PD01B_ADC1_AIN15 << 16) | MUX_PD01B_ADC1_AIN15) -#define PORT_PD01B_ADC1_AIN15 ((1UL) << 1) - -/* ========== PORT definition for CAN0 peripheral ========== */ -#define PIN_PA23I_CAN0_RX (23L) -#define MUX_PA23I_CAN0_RX (8L) -#define PINMUX_PA23I_CAN0_RX ((PIN_PA23I_CAN0_RX << 16) | MUX_PA23I_CAN0_RX) -#define PORT_PA23I_CAN0_RX ((1UL) << 23) - -#define PIN_PA25I_CAN0_RX (25L) -#define MUX_PA25I_CAN0_RX (8L) -#define PINMUX_PA25I_CAN0_RX ((PIN_PA25I_CAN0_RX << 16) | MUX_PA25I_CAN0_RX) -#define PORT_PA25I_CAN0_RX ((1UL) << 25) - -#define PIN_PA22I_CAN0_TX (22L) -#define MUX_PA22I_CAN0_TX (8L) -#define PINMUX_PA22I_CAN0_TX ((PIN_PA22I_CAN0_TX << 16) | MUX_PA22I_CAN0_TX) -#define PORT_PA22I_CAN0_TX ((1UL) << 22) - -#define PIN_PA24I_CAN0_TX (24L) -#define MUX_PA24I_CAN0_TX (8L) -#define PINMUX_PA24I_CAN0_TX ((PIN_PA24I_CAN0_TX << 16) | MUX_PA24I_CAN0_TX) -#define PORT_PA24I_CAN0_TX ((1UL) << 24) - -/* ========== PORT definition for CAN1 peripheral ========== */ -#define PIN_PB13H_CAN1_RX (45L) -#define MUX_PB13H_CAN1_RX (7L) -#define PINMUX_PB13H_CAN1_RX ((PIN_PB13H_CAN1_RX << 16) | MUX_PB13H_CAN1_RX) -#define PORT_PB13H_CAN1_RX ((1UL) << 13) - -#define PIN_PB15H_CAN1_RX (47L) -#define MUX_PB15H_CAN1_RX (7L) -#define PINMUX_PB15H_CAN1_RX ((PIN_PB15H_CAN1_RX << 16) | MUX_PB15H_CAN1_RX) -#define PORT_PB15H_CAN1_RX ((1UL) << 15) - -#define PIN_PB12H_CAN1_TX (44L) -#define MUX_PB12H_CAN1_TX (7L) -#define PINMUX_PB12H_CAN1_TX ((PIN_PB12H_CAN1_TX << 16) | MUX_PB12H_CAN1_TX) -#define PORT_PB12H_CAN1_TX ((1UL) << 12) - -#define PIN_PB14H_CAN1_TX (46L) -#define MUX_PB14H_CAN1_TX (7L) -#define PINMUX_PB14H_CAN1_TX ((PIN_PB14H_CAN1_TX << 16) | MUX_PB14H_CAN1_TX) -#define PORT_PB14H_CAN1_TX ((1UL) << 14) - -/* ========== PORT definition for CCL peripheral ========== */ -#define PIN_PA04N_CCL_IN0 (4L) -#define MUX_PA04N_CCL_IN0 (13L) -#define PINMUX_PA04N_CCL_IN0 ((PIN_PA04N_CCL_IN0 << 16) | MUX_PA04N_CCL_IN0) -#define PORT_PA04N_CCL_IN0 ((1UL) << 4) - -#define PIN_PA16N_CCL_IN0 (16L) -#define MUX_PA16N_CCL_IN0 (13L) -#define PINMUX_PA16N_CCL_IN0 ((PIN_PA16N_CCL_IN0 << 16) | MUX_PA16N_CCL_IN0) -#define PORT_PA16N_CCL_IN0 ((1UL) << 16) - -#define PIN_PB22N_CCL_IN0 (54L) -#define MUX_PB22N_CCL_IN0 (13L) -#define PINMUX_PB22N_CCL_IN0 ((PIN_PB22N_CCL_IN0 << 16) | MUX_PB22N_CCL_IN0) -#define PORT_PB22N_CCL_IN0 ((1UL) << 22) - -#define PIN_PA05N_CCL_IN1 (5L) -#define MUX_PA05N_CCL_IN1 (13L) -#define PINMUX_PA05N_CCL_IN1 ((PIN_PA05N_CCL_IN1 << 16) | MUX_PA05N_CCL_IN1) -#define PORT_PA05N_CCL_IN1 ((1UL) << 5) - -#define PIN_PA17N_CCL_IN1 (17L) -#define MUX_PA17N_CCL_IN1 (13L) -#define PINMUX_PA17N_CCL_IN1 ((PIN_PA17N_CCL_IN1 << 16) | MUX_PA17N_CCL_IN1) -#define PORT_PA17N_CCL_IN1 ((1UL) << 17) - -#define PIN_PB00N_CCL_IN1 (32L) -#define MUX_PB00N_CCL_IN1 (13L) -#define PINMUX_PB00N_CCL_IN1 ((PIN_PB00N_CCL_IN1 << 16) | MUX_PB00N_CCL_IN1) -#define PORT_PB00N_CCL_IN1 ((1UL) << 0) - -#define PIN_PA06N_CCL_IN2 (6L) -#define MUX_PA06N_CCL_IN2 (13L) -#define PINMUX_PA06N_CCL_IN2 ((PIN_PA06N_CCL_IN2 << 16) | MUX_PA06N_CCL_IN2) -#define PORT_PA06N_CCL_IN2 ((1UL) << 6) - -#define PIN_PA18N_CCL_IN2 (18L) -#define MUX_PA18N_CCL_IN2 (13L) -#define PINMUX_PA18N_CCL_IN2 ((PIN_PA18N_CCL_IN2 << 16) | MUX_PA18N_CCL_IN2) -#define PORT_PA18N_CCL_IN2 ((1UL) << 18) - -#define PIN_PB01N_CCL_IN2 (33L) -#define MUX_PB01N_CCL_IN2 (13L) -#define PINMUX_PB01N_CCL_IN2 ((PIN_PB01N_CCL_IN2 << 16) | MUX_PB01N_CCL_IN2) -#define PORT_PB01N_CCL_IN2 ((1UL) << 1) - -#define PIN_PA08N_CCL_IN3 (8L) -#define MUX_PA08N_CCL_IN3 (13L) -#define PINMUX_PA08N_CCL_IN3 ((PIN_PA08N_CCL_IN3 << 16) | MUX_PA08N_CCL_IN3) -#define PORT_PA08N_CCL_IN3 ((1UL) << 8) - -#define PIN_PA30N_CCL_IN3 (30L) -#define MUX_PA30N_CCL_IN3 (13L) -#define PINMUX_PA30N_CCL_IN3 ((PIN_PA30N_CCL_IN3 << 16) | MUX_PA30N_CCL_IN3) -#define PORT_PA30N_CCL_IN3 ((1UL) << 30) - -#define PIN_PA09N_CCL_IN4 (9L) -#define MUX_PA09N_CCL_IN4 (13L) -#define PINMUX_PA09N_CCL_IN4 ((PIN_PA09N_CCL_IN4 << 16) | MUX_PA09N_CCL_IN4) -#define PORT_PA09N_CCL_IN4 ((1UL) << 9) - -#define PIN_PC27N_CCL_IN4 (91L) -#define MUX_PC27N_CCL_IN4 (13L) -#define PINMUX_PC27N_CCL_IN4 ((PIN_PC27N_CCL_IN4 << 16) | MUX_PC27N_CCL_IN4) -#define PORT_PC27N_CCL_IN4 ((1UL) << 27) - -#define PIN_PA10N_CCL_IN5 (10L) -#define MUX_PA10N_CCL_IN5 (13L) -#define PINMUX_PA10N_CCL_IN5 ((PIN_PA10N_CCL_IN5 << 16) | MUX_PA10N_CCL_IN5) -#define PORT_PA10N_CCL_IN5 ((1UL) << 10) - -#define PIN_PC28N_CCL_IN5 (92L) -#define MUX_PC28N_CCL_IN5 (13L) -#define PINMUX_PC28N_CCL_IN5 ((PIN_PC28N_CCL_IN5 << 16) | MUX_PC28N_CCL_IN5) -#define PORT_PC28N_CCL_IN5 ((1UL) << 28) - -#define PIN_PA22N_CCL_IN6 (22L) -#define MUX_PA22N_CCL_IN6 (13L) -#define PINMUX_PA22N_CCL_IN6 ((PIN_PA22N_CCL_IN6 << 16) | MUX_PA22N_CCL_IN6) -#define PORT_PA22N_CCL_IN6 ((1UL) << 22) - -#define PIN_PB06N_CCL_IN6 (38L) -#define MUX_PB06N_CCL_IN6 (13L) -#define PINMUX_PB06N_CCL_IN6 ((PIN_PB06N_CCL_IN6 << 16) | MUX_PB06N_CCL_IN6) -#define PORT_PB06N_CCL_IN6 ((1UL) << 6) - -#define PIN_PA23N_CCL_IN7 (23L) -#define MUX_PA23N_CCL_IN7 (13L) -#define PINMUX_PA23N_CCL_IN7 ((PIN_PA23N_CCL_IN7 << 16) | MUX_PA23N_CCL_IN7) -#define PORT_PA23N_CCL_IN7 ((1UL) << 23) - -#define PIN_PB07N_CCL_IN7 (39L) -#define MUX_PB07N_CCL_IN7 (13L) -#define PINMUX_PB07N_CCL_IN7 ((PIN_PB07N_CCL_IN7 << 16) | MUX_PB07N_CCL_IN7) -#define PORT_PB07N_CCL_IN7 ((1UL) << 7) - -#define PIN_PA24N_CCL_IN8 (24L) -#define MUX_PA24N_CCL_IN8 (13L) -#define PINMUX_PA24N_CCL_IN8 ((PIN_PA24N_CCL_IN8 << 16) | MUX_PA24N_CCL_IN8) -#define PORT_PA24N_CCL_IN8 ((1UL) << 24) - -#define PIN_PB08N_CCL_IN8 (40L) -#define MUX_PB08N_CCL_IN8 (13L) -#define PINMUX_PB08N_CCL_IN8 ((PIN_PB08N_CCL_IN8 << 16) | MUX_PB08N_CCL_IN8) -#define PORT_PB08N_CCL_IN8 ((1UL) << 8) - -#define PIN_PB14N_CCL_IN9 (46L) -#define MUX_PB14N_CCL_IN9 (13L) -#define PINMUX_PB14N_CCL_IN9 ((PIN_PB14N_CCL_IN9 << 16) | MUX_PB14N_CCL_IN9) -#define PORT_PB14N_CCL_IN9 ((1UL) << 14) - -#define PIN_PC20N_CCL_IN9 (84L) -#define MUX_PC20N_CCL_IN9 (13L) -#define PINMUX_PC20N_CCL_IN9 ((PIN_PC20N_CCL_IN9 << 16) | MUX_PC20N_CCL_IN9) -#define PORT_PC20N_CCL_IN9 ((1UL) << 20) - -#define PIN_PB15N_CCL_IN10 (47L) -#define MUX_PB15N_CCL_IN10 (13L) -#define PINMUX_PB15N_CCL_IN10 ((PIN_PB15N_CCL_IN10 << 16) | MUX_PB15N_CCL_IN10) -#define PORT_PB15N_CCL_IN10 ((1UL) << 15) - -#define PIN_PC21N_CCL_IN10 (85L) -#define MUX_PC21N_CCL_IN10 (13L) -#define PINMUX_PC21N_CCL_IN10 ((PIN_PC21N_CCL_IN10 << 16) | MUX_PC21N_CCL_IN10) -#define PORT_PC21N_CCL_IN10 ((1UL) << 21) - -#define PIN_PB10N_CCL_IN11 (42L) -#define MUX_PB10N_CCL_IN11 (13L) -#define PINMUX_PB10N_CCL_IN11 ((PIN_PB10N_CCL_IN11 << 16) | MUX_PB10N_CCL_IN11) -#define PORT_PB10N_CCL_IN11 ((1UL) << 10) - -#define PIN_PB16N_CCL_IN11 (48L) -#define MUX_PB16N_CCL_IN11 (13L) -#define PINMUX_PB16N_CCL_IN11 ((PIN_PB16N_CCL_IN11 << 16) | MUX_PB16N_CCL_IN11) -#define PORT_PB16N_CCL_IN11 ((1UL) << 16) - -#define PIN_PA07N_CCL_OUT0 (7L) -#define MUX_PA07N_CCL_OUT0 (13L) -#define PINMUX_PA07N_CCL_OUT0 ((PIN_PA07N_CCL_OUT0 << 16) | MUX_PA07N_CCL_OUT0) -#define PORT_PA07N_CCL_OUT0 ((1UL) << 7) - -#define PIN_PA19N_CCL_OUT0 (19L) -#define MUX_PA19N_CCL_OUT0 (13L) -#define PINMUX_PA19N_CCL_OUT0 ((PIN_PA19N_CCL_OUT0 << 16) | MUX_PA19N_CCL_OUT0) -#define PORT_PA19N_CCL_OUT0 ((1UL) << 19) - -#define PIN_PB02N_CCL_OUT0 (34L) -#define MUX_PB02N_CCL_OUT0 (13L) -#define PINMUX_PB02N_CCL_OUT0 ((PIN_PB02N_CCL_OUT0 << 16) | MUX_PB02N_CCL_OUT0) -#define PORT_PB02N_CCL_OUT0 ((1UL) << 2) - -#define PIN_PB23N_CCL_OUT0 (55L) -#define MUX_PB23N_CCL_OUT0 (13L) -#define PINMUX_PB23N_CCL_OUT0 ((PIN_PB23N_CCL_OUT0 << 16) | MUX_PB23N_CCL_OUT0) -#define PORT_PB23N_CCL_OUT0 ((1UL) << 23) - -#define PIN_PA11N_CCL_OUT1 (11L) -#define MUX_PA11N_CCL_OUT1 (13L) -#define PINMUX_PA11N_CCL_OUT1 ((PIN_PA11N_CCL_OUT1 << 16) | MUX_PA11N_CCL_OUT1) -#define PORT_PA11N_CCL_OUT1 ((1UL) << 11) - -#define PIN_PA31N_CCL_OUT1 (31L) -#define MUX_PA31N_CCL_OUT1 (13L) -#define PINMUX_PA31N_CCL_OUT1 ((PIN_PA31N_CCL_OUT1 << 16) | MUX_PA31N_CCL_OUT1) -#define PORT_PA31N_CCL_OUT1 ((1UL) << 31) - -#define PIN_PB11N_CCL_OUT1 (43L) -#define MUX_PB11N_CCL_OUT1 (13L) -#define PINMUX_PB11N_CCL_OUT1 ((PIN_PB11N_CCL_OUT1 << 16) | MUX_PB11N_CCL_OUT1) -#define PORT_PB11N_CCL_OUT1 ((1UL) << 11) - -#define PIN_PA25N_CCL_OUT2 (25L) -#define MUX_PA25N_CCL_OUT2 (13L) -#define PINMUX_PA25N_CCL_OUT2 ((PIN_PA25N_CCL_OUT2 << 16) | MUX_PA25N_CCL_OUT2) -#define PORT_PA25N_CCL_OUT2 ((1UL) << 25) - -#define PIN_PB09N_CCL_OUT2 (41L) -#define MUX_PB09N_CCL_OUT2 (13L) -#define PINMUX_PB09N_CCL_OUT2 ((PIN_PB09N_CCL_OUT2 << 16) | MUX_PB09N_CCL_OUT2) -#define PORT_PB09N_CCL_OUT2 ((1UL) << 9) - -#define PIN_PB17N_CCL_OUT3 (49L) -#define MUX_PB17N_CCL_OUT3 (13L) -#define PINMUX_PB17N_CCL_OUT3 ((PIN_PB17N_CCL_OUT3 << 16) | MUX_PB17N_CCL_OUT3) -#define PORT_PB17N_CCL_OUT3 ((1UL) << 17) - -/* ========== PORT definition for DAC peripheral ========== */ -#define PIN_PA02B_DAC_VOUT0 (2L) -#define MUX_PA02B_DAC_VOUT0 (1L) -#define PINMUX_PA02B_DAC_VOUT0 ((PIN_PA02B_DAC_VOUT0 << 16) | MUX_PA02B_DAC_VOUT0) -#define PORT_PA02B_DAC_VOUT0 ((1UL) << 2) - -#define PIN_PA05B_DAC_VOUT1 (5L) -#define MUX_PA05B_DAC_VOUT1 (1L) -#define PINMUX_PA05B_DAC_VOUT1 ((PIN_PA05B_DAC_VOUT1 << 16) | MUX_PA05B_DAC_VOUT1) -#define PORT_PA05B_DAC_VOUT1 ((1UL) << 5) - -/* ========== PORT definition for EIC peripheral ========== */ -#define PIN_PA00A_EIC_EXTINT0 (0L) -#define MUX_PA00A_EIC_EXTINT0 (0L) -#define PINMUX_PA00A_EIC_EXTINT0 ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0) -#define PORT_PA00A_EIC_EXTINT0 ((1UL) << 0) -#define PIN_PA00A_EIC_EXTINT_NUM _L_(0) /**< EIC signal: PIN_PA00 External Interrupt Line */ - -#define PIN_PA16A_EIC_EXTINT0 (16L) -#define MUX_PA16A_EIC_EXTINT0 (0L) -#define PINMUX_PA16A_EIC_EXTINT0 ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0) -#define PORT_PA16A_EIC_EXTINT0 ((1UL) << 16) -#define PIN_PA16A_EIC_EXTINT_NUM _L_(0) /**< EIC signal: PIN_PA16 External Interrupt Line */ - -#define PIN_PB00A_EIC_EXTINT0 (32L) -#define MUX_PB00A_EIC_EXTINT0 (0L) -#define PINMUX_PB00A_EIC_EXTINT0 ((PIN_PB00A_EIC_EXTINT0 << 16) | MUX_PB00A_EIC_EXTINT0) -#define PORT_PB00A_EIC_EXTINT0 ((1UL) << 0) -#define PIN_PB00A_EIC_EXTINT_NUM _L_(0) /**< EIC signal: PIN_PB00 External Interrupt Line */ - -#define PIN_PB16A_EIC_EXTINT0 (48L) -#define MUX_PB16A_EIC_EXTINT0 (0L) -#define PINMUX_PB16A_EIC_EXTINT0 ((PIN_PB16A_EIC_EXTINT0 << 16) | MUX_PB16A_EIC_EXTINT0) -#define PORT_PB16A_EIC_EXTINT0 ((1UL) << 16) -#define PIN_PB16A_EIC_EXTINT_NUM _L_(0) /**< EIC signal: PIN_PB16 External Interrupt Line */ - -#define PIN_PC00A_EIC_EXTINT0 (64L) -#define MUX_PC00A_EIC_EXTINT0 (0L) -#define PINMUX_PC00A_EIC_EXTINT0 ((PIN_PC00A_EIC_EXTINT0 << 16) | MUX_PC00A_EIC_EXTINT0) -#define PORT_PC00A_EIC_EXTINT0 ((1UL) << 0) -#define PIN_PC00A_EIC_EXTINT_NUM _L_(0) /**< EIC signal: PIN_PC00 External Interrupt Line */ - -#define PIN_PC16A_EIC_EXTINT0 (80L) -#define MUX_PC16A_EIC_EXTINT0 (0L) -#define PINMUX_PC16A_EIC_EXTINT0 ((PIN_PC16A_EIC_EXTINT0 << 16) | MUX_PC16A_EIC_EXTINT0) -#define PORT_PC16A_EIC_EXTINT0 ((1UL) << 16) -#define PIN_PC16A_EIC_EXTINT_NUM _L_(0) /**< EIC signal: PIN_PC16 External Interrupt Line */ - -#define PIN_PD00A_EIC_EXTINT0 (96L) -#define MUX_PD00A_EIC_EXTINT0 (0L) -#define PINMUX_PD00A_EIC_EXTINT0 ((PIN_PD00A_EIC_EXTINT0 << 16) | MUX_PD00A_EIC_EXTINT0) -#define PORT_PD00A_EIC_EXTINT0 ((1UL) << 0) -#define PIN_PD00A_EIC_EXTINT_NUM _L_(0) /**< EIC signal: PIN_PD00 External Interrupt Line */ - -#define PIN_PA01A_EIC_EXTINT1 (1L) -#define MUX_PA01A_EIC_EXTINT1 (0L) -#define PINMUX_PA01A_EIC_EXTINT1 ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1) -#define PORT_PA01A_EIC_EXTINT1 ((1UL) << 1) -#define PIN_PA01A_EIC_EXTINT_NUM _L_(1) /**< EIC signal: PIN_PA01 External Interrupt Line */ - -#define PIN_PA17A_EIC_EXTINT1 (17L) -#define MUX_PA17A_EIC_EXTINT1 (0L) -#define PINMUX_PA17A_EIC_EXTINT1 ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1) -#define PORT_PA17A_EIC_EXTINT1 ((1UL) << 17) -#define PIN_PA17A_EIC_EXTINT_NUM _L_(1) /**< EIC signal: PIN_PA17 External Interrupt Line */ - -#define PIN_PB01A_EIC_EXTINT1 (33L) -#define MUX_PB01A_EIC_EXTINT1 (0L) -#define PINMUX_PB01A_EIC_EXTINT1 ((PIN_PB01A_EIC_EXTINT1 << 16) | MUX_PB01A_EIC_EXTINT1) -#define PORT_PB01A_EIC_EXTINT1 ((1UL) << 1) -#define PIN_PB01A_EIC_EXTINT_NUM _L_(1) /**< EIC signal: PIN_PB01 External Interrupt Line */ - -#define PIN_PB17A_EIC_EXTINT1 (49L) -#define MUX_PB17A_EIC_EXTINT1 (0L) -#define PINMUX_PB17A_EIC_EXTINT1 ((PIN_PB17A_EIC_EXTINT1 << 16) | MUX_PB17A_EIC_EXTINT1) -#define PORT_PB17A_EIC_EXTINT1 ((1UL) << 17) -#define PIN_PB17A_EIC_EXTINT_NUM _L_(1) /**< EIC signal: PIN_PB17 External Interrupt Line */ - -#define PIN_PC01A_EIC_EXTINT1 (65L) -#define MUX_PC01A_EIC_EXTINT1 (0L) -#define PINMUX_PC01A_EIC_EXTINT1 ((PIN_PC01A_EIC_EXTINT1 << 16) | MUX_PC01A_EIC_EXTINT1) -#define PORT_PC01A_EIC_EXTINT1 ((1UL) << 1) -#define PIN_PC01A_EIC_EXTINT_NUM _L_(1) /**< EIC signal: PIN_PC01 External Interrupt Line */ - -#define PIN_PC17A_EIC_EXTINT1 (81L) -#define MUX_PC17A_EIC_EXTINT1 (0L) -#define PINMUX_PC17A_EIC_EXTINT1 ((PIN_PC17A_EIC_EXTINT1 << 16) | MUX_PC17A_EIC_EXTINT1) -#define PORT_PC17A_EIC_EXTINT1 ((1UL) << 17) -#define PIN_PC17A_EIC_EXTINT_NUM _L_(1) /**< EIC signal: PIN_PC17 External Interrupt Line */ - -#define PIN_PD01A_EIC_EXTINT1 (97L) -#define MUX_PD01A_EIC_EXTINT1 (0L) -#define PINMUX_PD01A_EIC_EXTINT1 ((PIN_PD01A_EIC_EXTINT1 << 16) | MUX_PD01A_EIC_EXTINT1) -#define PORT_PD01A_EIC_EXTINT1 ((1UL) << 1) -#define PIN_PD01A_EIC_EXTINT_NUM _L_(1) /**< EIC signal: PIN_PD01 External Interrupt Line */ - -#define PIN_PA02A_EIC_EXTINT2 (2L) -#define MUX_PA02A_EIC_EXTINT2 (0L) -#define PINMUX_PA02A_EIC_EXTINT2 ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2) -#define PORT_PA02A_EIC_EXTINT2 ((1UL) << 2) -#define PIN_PA02A_EIC_EXTINT_NUM _L_(2) /**< EIC signal: PIN_PA02 External Interrupt Line */ - -#define PIN_PA18A_EIC_EXTINT2 (18L) -#define MUX_PA18A_EIC_EXTINT2 (0L) -#define PINMUX_PA18A_EIC_EXTINT2 ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2) -#define PORT_PA18A_EIC_EXTINT2 ((1UL) << 18) -#define PIN_PA18A_EIC_EXTINT_NUM _L_(2) /**< EIC signal: PIN_PA18 External Interrupt Line */ - -#define PIN_PB02A_EIC_EXTINT2 (34L) -#define MUX_PB02A_EIC_EXTINT2 (0L) -#define PINMUX_PB02A_EIC_EXTINT2 ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2) -#define PORT_PB02A_EIC_EXTINT2 ((1UL) << 2) -#define PIN_PB02A_EIC_EXTINT_NUM _L_(2) /**< EIC signal: PIN_PB02 External Interrupt Line */ - -#define PIN_PB18A_EIC_EXTINT2 (50L) -#define MUX_PB18A_EIC_EXTINT2 (0L) -#define PINMUX_PB18A_EIC_EXTINT2 ((PIN_PB18A_EIC_EXTINT2 << 16) | MUX_PB18A_EIC_EXTINT2) -#define PORT_PB18A_EIC_EXTINT2 ((1UL) << 18) -#define PIN_PB18A_EIC_EXTINT_NUM _L_(2) /**< EIC signal: PIN_PB18 External Interrupt Line */ - -#define PIN_PC02A_EIC_EXTINT2 (66L) -#define MUX_PC02A_EIC_EXTINT2 (0L) -#define PINMUX_PC02A_EIC_EXTINT2 ((PIN_PC02A_EIC_EXTINT2 << 16) | MUX_PC02A_EIC_EXTINT2) -#define PORT_PC02A_EIC_EXTINT2 ((1UL) << 2) -#define PIN_PC02A_EIC_EXTINT_NUM _L_(2) /**< EIC signal: PIN_PC02 External Interrupt Line */ - -#define PIN_PC18A_EIC_EXTINT2 (82L) -#define MUX_PC18A_EIC_EXTINT2 (0L) -#define PINMUX_PC18A_EIC_EXTINT2 ((PIN_PC18A_EIC_EXTINT2 << 16) | MUX_PC18A_EIC_EXTINT2) -#define PORT_PC18A_EIC_EXTINT2 ((1UL) << 18) -#define PIN_PC18A_EIC_EXTINT_NUM _L_(2) /**< EIC signal: PIN_PC18 External Interrupt Line */ - -#define PIN_PA03A_EIC_EXTINT3 (3L) -#define MUX_PA03A_EIC_EXTINT3 (0L) -#define PINMUX_PA03A_EIC_EXTINT3 ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3) -#define PORT_PA03A_EIC_EXTINT3 ((1UL) << 3) -#define PIN_PA03A_EIC_EXTINT_NUM _L_(3) /**< EIC signal: PIN_PA03 External Interrupt Line */ - -#define PIN_PA19A_EIC_EXTINT3 (19L) -#define MUX_PA19A_EIC_EXTINT3 (0L) -#define PINMUX_PA19A_EIC_EXTINT3 ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3) -#define PORT_PA19A_EIC_EXTINT3 ((1UL) << 19) -#define PIN_PA19A_EIC_EXTINT_NUM _L_(3) /**< EIC signal: PIN_PA19 External Interrupt Line */ - -#define PIN_PB03A_EIC_EXTINT3 (35L) -#define MUX_PB03A_EIC_EXTINT3 (0L) -#define PINMUX_PB03A_EIC_EXTINT3 ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3) -#define PORT_PB03A_EIC_EXTINT3 ((1UL) << 3) -#define PIN_PB03A_EIC_EXTINT_NUM _L_(3) /**< EIC signal: PIN_PB03 External Interrupt Line */ - -#define PIN_PB19A_EIC_EXTINT3 (51L) -#define MUX_PB19A_EIC_EXTINT3 (0L) -#define PINMUX_PB19A_EIC_EXTINT3 ((PIN_PB19A_EIC_EXTINT3 << 16) | MUX_PB19A_EIC_EXTINT3) -#define PORT_PB19A_EIC_EXTINT3 ((1UL) << 19) -#define PIN_PB19A_EIC_EXTINT_NUM _L_(3) /**< EIC signal: PIN_PB19 External Interrupt Line */ - -#define PIN_PC03A_EIC_EXTINT3 (67L) -#define MUX_PC03A_EIC_EXTINT3 (0L) -#define PINMUX_PC03A_EIC_EXTINT3 ((PIN_PC03A_EIC_EXTINT3 << 16) | MUX_PC03A_EIC_EXTINT3) -#define PORT_PC03A_EIC_EXTINT3 ((1UL) << 3) -#define PIN_PC03A_EIC_EXTINT_NUM _L_(3) /**< EIC signal: PIN_PC03 External Interrupt Line */ - -#define PIN_PC19A_EIC_EXTINT3 (83L) -#define MUX_PC19A_EIC_EXTINT3 (0L) -#define PINMUX_PC19A_EIC_EXTINT3 ((PIN_PC19A_EIC_EXTINT3 << 16) | MUX_PC19A_EIC_EXTINT3) -#define PORT_PC19A_EIC_EXTINT3 ((1UL) << 19) -#define PIN_PC19A_EIC_EXTINT_NUM _L_(3) /**< EIC signal: PIN_PC19 External Interrupt Line */ - -#define PIN_PD08A_EIC_EXTINT3 (104L) -#define MUX_PD08A_EIC_EXTINT3 (0L) -#define PINMUX_PD08A_EIC_EXTINT3 ((PIN_PD08A_EIC_EXTINT3 << 16) | MUX_PD08A_EIC_EXTINT3) -#define PORT_PD08A_EIC_EXTINT3 ((1UL) << 8) -#define PIN_PD08A_EIC_EXTINT_NUM _L_(3) /**< EIC signal: PIN_PD08 External Interrupt Line */ - -#define PIN_PA04A_EIC_EXTINT4 (4L) -#define MUX_PA04A_EIC_EXTINT4 (0L) -#define PINMUX_PA04A_EIC_EXTINT4 ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4) -#define PORT_PA04A_EIC_EXTINT4 ((1UL) << 4) -#define PIN_PA04A_EIC_EXTINT_NUM _L_(4) /**< EIC signal: PIN_PA04 External Interrupt Line */ - -#define PIN_PA20A_EIC_EXTINT4 (20L) -#define MUX_PA20A_EIC_EXTINT4 (0L) -#define PINMUX_PA20A_EIC_EXTINT4 ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4) -#define PORT_PA20A_EIC_EXTINT4 ((1UL) << 20) -#define PIN_PA20A_EIC_EXTINT_NUM _L_(4) /**< EIC signal: PIN_PA20 External Interrupt Line */ - -#define PIN_PB04A_EIC_EXTINT4 (36L) -#define MUX_PB04A_EIC_EXTINT4 (0L) -#define PINMUX_PB04A_EIC_EXTINT4 ((PIN_PB04A_EIC_EXTINT4 << 16) | MUX_PB04A_EIC_EXTINT4) -#define PORT_PB04A_EIC_EXTINT4 ((1UL) << 4) -#define PIN_PB04A_EIC_EXTINT_NUM _L_(4) /**< EIC signal: PIN_PB04 External Interrupt Line */ - -#define PIN_PB20A_EIC_EXTINT4 (52L) -#define MUX_PB20A_EIC_EXTINT4 (0L) -#define PINMUX_PB20A_EIC_EXTINT4 ((PIN_PB20A_EIC_EXTINT4 << 16) | MUX_PB20A_EIC_EXTINT4) -#define PORT_PB20A_EIC_EXTINT4 ((1UL) << 20) -#define PIN_PB20A_EIC_EXTINT_NUM _L_(4) /**< EIC signal: PIN_PB20 External Interrupt Line */ - -#define PIN_PC04A_EIC_EXTINT4 (68L) -#define MUX_PC04A_EIC_EXTINT4 (0L) -#define PINMUX_PC04A_EIC_EXTINT4 ((PIN_PC04A_EIC_EXTINT4 << 16) | MUX_PC04A_EIC_EXTINT4) -#define PORT_PC04A_EIC_EXTINT4 ((1UL) << 4) -#define PIN_PC04A_EIC_EXTINT_NUM _L_(4) /**< EIC signal: PIN_PC04 External Interrupt Line */ - -#define PIN_PC20A_EIC_EXTINT4 (84L) -#define MUX_PC20A_EIC_EXTINT4 (0L) -#define PINMUX_PC20A_EIC_EXTINT4 ((PIN_PC20A_EIC_EXTINT4 << 16) | MUX_PC20A_EIC_EXTINT4) -#define PORT_PC20A_EIC_EXTINT4 ((1UL) << 20) -#define PIN_PC20A_EIC_EXTINT_NUM _L_(4) /**< EIC signal: PIN_PC20 External Interrupt Line */ - -#define PIN_PD09A_EIC_EXTINT4 (105L) -#define MUX_PD09A_EIC_EXTINT4 (0L) -#define PINMUX_PD09A_EIC_EXTINT4 ((PIN_PD09A_EIC_EXTINT4 << 16) | MUX_PD09A_EIC_EXTINT4) -#define PORT_PD09A_EIC_EXTINT4 ((1UL) << 9) -#define PIN_PD09A_EIC_EXTINT_NUM _L_(4) /**< EIC signal: PIN_PD09 External Interrupt Line */ - -#define PIN_PA05A_EIC_EXTINT5 (5L) -#define MUX_PA05A_EIC_EXTINT5 (0L) -#define PINMUX_PA05A_EIC_EXTINT5 ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5) -#define PORT_PA05A_EIC_EXTINT5 ((1UL) << 5) -#define PIN_PA05A_EIC_EXTINT_NUM _L_(5) /**< EIC signal: PIN_PA05 External Interrupt Line */ - -#define PIN_PA21A_EIC_EXTINT5 (21L) -#define MUX_PA21A_EIC_EXTINT5 (0L) -#define PINMUX_PA21A_EIC_EXTINT5 ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5) -#define PORT_PA21A_EIC_EXTINT5 ((1UL) << 21) -#define PIN_PA21A_EIC_EXTINT_NUM _L_(5) /**< EIC signal: PIN_PA21 External Interrupt Line */ - -#define PIN_PB05A_EIC_EXTINT5 (37L) -#define MUX_PB05A_EIC_EXTINT5 (0L) -#define PINMUX_PB05A_EIC_EXTINT5 ((PIN_PB05A_EIC_EXTINT5 << 16) | MUX_PB05A_EIC_EXTINT5) -#define PORT_PB05A_EIC_EXTINT5 ((1UL) << 5) -#define PIN_PB05A_EIC_EXTINT_NUM _L_(5) /**< EIC signal: PIN_PB05 External Interrupt Line */ - -#define PIN_PB21A_EIC_EXTINT5 (53L) -#define MUX_PB21A_EIC_EXTINT5 (0L) -#define PINMUX_PB21A_EIC_EXTINT5 ((PIN_PB21A_EIC_EXTINT5 << 16) | MUX_PB21A_EIC_EXTINT5) -#define PORT_PB21A_EIC_EXTINT5 ((1UL) << 21) -#define PIN_PB21A_EIC_EXTINT_NUM _L_(5) /**< EIC signal: PIN_PB21 External Interrupt Line */ - -#define PIN_PC05A_EIC_EXTINT5 (69L) -#define MUX_PC05A_EIC_EXTINT5 (0L) -#define PINMUX_PC05A_EIC_EXTINT5 ((PIN_PC05A_EIC_EXTINT5 << 16) | MUX_PC05A_EIC_EXTINT5) -#define PORT_PC05A_EIC_EXTINT5 ((1UL) << 5) -#define PIN_PC05A_EIC_EXTINT_NUM _L_(5) /**< EIC signal: PIN_PC05 External Interrupt Line */ - -#define PIN_PC21A_EIC_EXTINT5 (85L) -#define MUX_PC21A_EIC_EXTINT5 (0L) -#define PINMUX_PC21A_EIC_EXTINT5 ((PIN_PC21A_EIC_EXTINT5 << 16) | MUX_PC21A_EIC_EXTINT5) -#define PORT_PC21A_EIC_EXTINT5 ((1UL) << 21) -#define PIN_PC21A_EIC_EXTINT_NUM _L_(5) /**< EIC signal: PIN_PC21 External Interrupt Line */ - -#define PIN_PD10A_EIC_EXTINT5 (106L) -#define MUX_PD10A_EIC_EXTINT5 (0L) -#define PINMUX_PD10A_EIC_EXTINT5 ((PIN_PD10A_EIC_EXTINT5 << 16) | MUX_PD10A_EIC_EXTINT5) -#define PORT_PD10A_EIC_EXTINT5 ((1UL) << 10) -#define PIN_PD10A_EIC_EXTINT_NUM _L_(5) /**< EIC signal: PIN_PD10 External Interrupt Line */ - -#define PIN_PA06A_EIC_EXTINT6 (6L) -#define MUX_PA06A_EIC_EXTINT6 (0L) -#define PINMUX_PA06A_EIC_EXTINT6 ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6) -#define PORT_PA06A_EIC_EXTINT6 ((1UL) << 6) -#define PIN_PA06A_EIC_EXTINT_NUM _L_(6) /**< EIC signal: PIN_PA06 External Interrupt Line */ - -#define PIN_PA22A_EIC_EXTINT6 (22L) -#define MUX_PA22A_EIC_EXTINT6 (0L) -#define PINMUX_PA22A_EIC_EXTINT6 ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6) -#define PORT_PA22A_EIC_EXTINT6 ((1UL) << 22) -#define PIN_PA22A_EIC_EXTINT_NUM _L_(6) /**< EIC signal: PIN_PA22 External Interrupt Line */ - -#define PIN_PB06A_EIC_EXTINT6 (38L) -#define MUX_PB06A_EIC_EXTINT6 (0L) -#define PINMUX_PB06A_EIC_EXTINT6 ((PIN_PB06A_EIC_EXTINT6 << 16) | MUX_PB06A_EIC_EXTINT6) -#define PORT_PB06A_EIC_EXTINT6 ((1UL) << 6) -#define PIN_PB06A_EIC_EXTINT_NUM _L_(6) /**< EIC signal: PIN_PB06 External Interrupt Line */ - -#define PIN_PB22A_EIC_EXTINT6 (54L) -#define MUX_PB22A_EIC_EXTINT6 (0L) -#define PINMUX_PB22A_EIC_EXTINT6 ((PIN_PB22A_EIC_EXTINT6 << 16) | MUX_PB22A_EIC_EXTINT6) -#define PORT_PB22A_EIC_EXTINT6 ((1UL) << 22) -#define PIN_PB22A_EIC_EXTINT_NUM _L_(6) /**< EIC signal: PIN_PB22 External Interrupt Line */ - -#define PIN_PC06A_EIC_EXTINT6 (70L) -#define MUX_PC06A_EIC_EXTINT6 (0L) -#define PINMUX_PC06A_EIC_EXTINT6 ((PIN_PC06A_EIC_EXTINT6 << 16) | MUX_PC06A_EIC_EXTINT6) -#define PORT_PC06A_EIC_EXTINT6 ((1UL) << 6) -#define PIN_PC06A_EIC_EXTINT_NUM _L_(6) /**< EIC signal: PIN_PC06 External Interrupt Line */ - -#define PIN_PC22A_EIC_EXTINT6 (86L) -#define MUX_PC22A_EIC_EXTINT6 (0L) -#define PINMUX_PC22A_EIC_EXTINT6 ((PIN_PC22A_EIC_EXTINT6 << 16) | MUX_PC22A_EIC_EXTINT6) -#define PORT_PC22A_EIC_EXTINT6 ((1UL) << 22) -#define PIN_PC22A_EIC_EXTINT_NUM _L_(6) /**< EIC signal: PIN_PC22 External Interrupt Line */ - -#define PIN_PD11A_EIC_EXTINT6 (107L) -#define MUX_PD11A_EIC_EXTINT6 (0L) -#define PINMUX_PD11A_EIC_EXTINT6 ((PIN_PD11A_EIC_EXTINT6 << 16) | MUX_PD11A_EIC_EXTINT6) -#define PORT_PD11A_EIC_EXTINT6 ((1UL) << 11) -#define PIN_PD11A_EIC_EXTINT_NUM _L_(6) /**< EIC signal: PIN_PD11 External Interrupt Line */ - -#define PIN_PA07A_EIC_EXTINT7 (7L) -#define MUX_PA07A_EIC_EXTINT7 (0L) -#define PINMUX_PA07A_EIC_EXTINT7 ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7) -#define PORT_PA07A_EIC_EXTINT7 ((1UL) << 7) -#define PIN_PA07A_EIC_EXTINT_NUM _L_(7) /**< EIC signal: PIN_PA07 External Interrupt Line */ - -#define PIN_PA23A_EIC_EXTINT7 (23L) -#define MUX_PA23A_EIC_EXTINT7 (0L) -#define PINMUX_PA23A_EIC_EXTINT7 ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7) -#define PORT_PA23A_EIC_EXTINT7 ((1UL) << 23) -#define PIN_PA23A_EIC_EXTINT_NUM _L_(7) /**< EIC signal: PIN_PA23 External Interrupt Line */ - -#define PIN_PB07A_EIC_EXTINT7 (39L) -#define MUX_PB07A_EIC_EXTINT7 (0L) -#define PINMUX_PB07A_EIC_EXTINT7 ((PIN_PB07A_EIC_EXTINT7 << 16) | MUX_PB07A_EIC_EXTINT7) -#define PORT_PB07A_EIC_EXTINT7 ((1UL) << 7) -#define PIN_PB07A_EIC_EXTINT_NUM _L_(7) /**< EIC signal: PIN_PB07 External Interrupt Line */ - -#define PIN_PB23A_EIC_EXTINT7 (55L) -#define MUX_PB23A_EIC_EXTINT7 (0L) -#define PINMUX_PB23A_EIC_EXTINT7 ((PIN_PB23A_EIC_EXTINT7 << 16) | MUX_PB23A_EIC_EXTINT7) -#define PORT_PB23A_EIC_EXTINT7 ((1UL) << 23) -#define PIN_PB23A_EIC_EXTINT_NUM _L_(7) /**< EIC signal: PIN_PB23 External Interrupt Line */ - -#define PIN_PC23A_EIC_EXTINT7 (87L) -#define MUX_PC23A_EIC_EXTINT7 (0L) -#define PINMUX_PC23A_EIC_EXTINT7 ((PIN_PC23A_EIC_EXTINT7 << 16) | MUX_PC23A_EIC_EXTINT7) -#define PORT_PC23A_EIC_EXTINT7 ((1UL) << 23) -#define PIN_PC23A_EIC_EXTINT_NUM _L_(7) /**< EIC signal: PIN_PC23 External Interrupt Line */ - -#define PIN_PD12A_EIC_EXTINT7 (108L) -#define MUX_PD12A_EIC_EXTINT7 (0L) -#define PINMUX_PD12A_EIC_EXTINT7 ((PIN_PD12A_EIC_EXTINT7 << 16) | MUX_PD12A_EIC_EXTINT7) -#define PORT_PD12A_EIC_EXTINT7 ((1UL) << 12) -#define PIN_PD12A_EIC_EXTINT_NUM _L_(7) /**< EIC signal: PIN_PD12 External Interrupt Line */ - -#define PIN_PA24A_EIC_EXTINT8 (24L) -#define MUX_PA24A_EIC_EXTINT8 (0L) -#define PINMUX_PA24A_EIC_EXTINT8 ((PIN_PA24A_EIC_EXTINT8 << 16) | MUX_PA24A_EIC_EXTINT8) -#define PORT_PA24A_EIC_EXTINT8 ((1UL) << 24) -#define PIN_PA24A_EIC_EXTINT_NUM _L_(8) /**< EIC signal: PIN_PA24 External Interrupt Line */ - -#define PIN_PB08A_EIC_EXTINT8 (40L) -#define MUX_PB08A_EIC_EXTINT8 (0L) -#define PINMUX_PB08A_EIC_EXTINT8 ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8) -#define PORT_PB08A_EIC_EXTINT8 ((1UL) << 8) -#define PIN_PB08A_EIC_EXTINT_NUM _L_(8) /**< EIC signal: PIN_PB08 External Interrupt Line */ - -#define PIN_PB24A_EIC_EXTINT8 (56L) -#define MUX_PB24A_EIC_EXTINT8 (0L) -#define PINMUX_PB24A_EIC_EXTINT8 ((PIN_PB24A_EIC_EXTINT8 << 16) | MUX_PB24A_EIC_EXTINT8) -#define PORT_PB24A_EIC_EXTINT8 ((1UL) << 24) -#define PIN_PB24A_EIC_EXTINT_NUM _L_(8) /**< EIC signal: PIN_PB24 External Interrupt Line */ - -#define PIN_PC24A_EIC_EXTINT8 (88L) -#define MUX_PC24A_EIC_EXTINT8 (0L) -#define PINMUX_PC24A_EIC_EXTINT8 ((PIN_PC24A_EIC_EXTINT8 << 16) | MUX_PC24A_EIC_EXTINT8) -#define PORT_PC24A_EIC_EXTINT8 ((1UL) << 24) -#define PIN_PC24A_EIC_EXTINT_NUM _L_(8) /**< EIC signal: PIN_PC24 External Interrupt Line */ - -#define PIN_PA09A_EIC_EXTINT9 (9L) -#define MUX_PA09A_EIC_EXTINT9 (0L) -#define PINMUX_PA09A_EIC_EXTINT9 ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9) -#define PORT_PA09A_EIC_EXTINT9 ((1UL) << 9) -#define PIN_PA09A_EIC_EXTINT_NUM _L_(9) /**< EIC signal: PIN_PA09 External Interrupt Line */ - -#define PIN_PA25A_EIC_EXTINT9 (25L) -#define MUX_PA25A_EIC_EXTINT9 (0L) -#define PINMUX_PA25A_EIC_EXTINT9 ((PIN_PA25A_EIC_EXTINT9 << 16) | MUX_PA25A_EIC_EXTINT9) -#define PORT_PA25A_EIC_EXTINT9 ((1UL) << 25) -#define PIN_PA25A_EIC_EXTINT_NUM _L_(9) /**< EIC signal: PIN_PA25 External Interrupt Line */ - -#define PIN_PB09A_EIC_EXTINT9 (41L) -#define MUX_PB09A_EIC_EXTINT9 (0L) -#define PINMUX_PB09A_EIC_EXTINT9 ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9) -#define PORT_PB09A_EIC_EXTINT9 ((1UL) << 9) -#define PIN_PB09A_EIC_EXTINT_NUM _L_(9) /**< EIC signal: PIN_PB09 External Interrupt Line */ - -#define PIN_PB25A_EIC_EXTINT9 (57L) -#define MUX_PB25A_EIC_EXTINT9 (0L) -#define PINMUX_PB25A_EIC_EXTINT9 ((PIN_PB25A_EIC_EXTINT9 << 16) | MUX_PB25A_EIC_EXTINT9) -#define PORT_PB25A_EIC_EXTINT9 ((1UL) << 25) -#define PIN_PB25A_EIC_EXTINT_NUM _L_(9) /**< EIC signal: PIN_PB25 External Interrupt Line */ - -#define PIN_PC07A_EIC_EXTINT9 (71L) -#define MUX_PC07A_EIC_EXTINT9 (0L) -#define PINMUX_PC07A_EIC_EXTINT9 ((PIN_PC07A_EIC_EXTINT9 << 16) | MUX_PC07A_EIC_EXTINT9) -#define PORT_PC07A_EIC_EXTINT9 ((1UL) << 7) -#define PIN_PC07A_EIC_EXTINT_NUM _L_(9) /**< EIC signal: PIN_PC07 External Interrupt Line */ - -#define PIN_PC25A_EIC_EXTINT9 (89L) -#define MUX_PC25A_EIC_EXTINT9 (0L) -#define PINMUX_PC25A_EIC_EXTINT9 ((PIN_PC25A_EIC_EXTINT9 << 16) | MUX_PC25A_EIC_EXTINT9) -#define PORT_PC25A_EIC_EXTINT9 ((1UL) << 25) -#define PIN_PC25A_EIC_EXTINT_NUM _L_(9) /**< EIC signal: PIN_PC25 External Interrupt Line */ - -#define PIN_PA10A_EIC_EXTINT10 (10L) -#define MUX_PA10A_EIC_EXTINT10 (0L) -#define PINMUX_PA10A_EIC_EXTINT10 ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10) -#define PORT_PA10A_EIC_EXTINT10 ((1UL) << 10) -#define PIN_PA10A_EIC_EXTINT_NUM _L_(10) /**< EIC signal: PIN_PA10 External Interrupt Line */ - -#define PIN_PB10A_EIC_EXTINT10 (42L) -#define MUX_PB10A_EIC_EXTINT10 (0L) -#define PINMUX_PB10A_EIC_EXTINT10 ((PIN_PB10A_EIC_EXTINT10 << 16) | MUX_PB10A_EIC_EXTINT10) -#define PORT_PB10A_EIC_EXTINT10 ((1UL) << 10) -#define PIN_PB10A_EIC_EXTINT_NUM _L_(10) /**< EIC signal: PIN_PB10 External Interrupt Line */ - -#define PIN_PC10A_EIC_EXTINT10 (74L) -#define MUX_PC10A_EIC_EXTINT10 (0L) -#define PINMUX_PC10A_EIC_EXTINT10 ((PIN_PC10A_EIC_EXTINT10 << 16) | MUX_PC10A_EIC_EXTINT10) -#define PORT_PC10A_EIC_EXTINT10 ((1UL) << 10) -#define PIN_PC10A_EIC_EXTINT_NUM _L_(10) /**< EIC signal: PIN_PC10 External Interrupt Line */ - -#define PIN_PC26A_EIC_EXTINT10 (90L) -#define MUX_PC26A_EIC_EXTINT10 (0L) -#define PINMUX_PC26A_EIC_EXTINT10 ((PIN_PC26A_EIC_EXTINT10 << 16) | MUX_PC26A_EIC_EXTINT10) -#define PORT_PC26A_EIC_EXTINT10 ((1UL) << 26) -#define PIN_PC26A_EIC_EXTINT_NUM _L_(10) /**< EIC signal: PIN_PC26 External Interrupt Line */ - -#define PIN_PD20A_EIC_EXTINT10 (116L) -#define MUX_PD20A_EIC_EXTINT10 (0L) -#define PINMUX_PD20A_EIC_EXTINT10 ((PIN_PD20A_EIC_EXTINT10 << 16) | MUX_PD20A_EIC_EXTINT10) -#define PORT_PD20A_EIC_EXTINT10 ((1UL) << 20) -#define PIN_PD20A_EIC_EXTINT_NUM _L_(10) /**< EIC signal: PIN_PD20 External Interrupt Line */ - -#define PIN_PA11A_EIC_EXTINT11 (11L) -#define MUX_PA11A_EIC_EXTINT11 (0L) -#define PINMUX_PA11A_EIC_EXTINT11 ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11) -#define PORT_PA11A_EIC_EXTINT11 ((1UL) << 11) -#define PIN_PA11A_EIC_EXTINT_NUM _L_(11) /**< EIC signal: PIN_PA11 External Interrupt Line */ - -#define PIN_PA27A_EIC_EXTINT11 (27L) -#define MUX_PA27A_EIC_EXTINT11 (0L) -#define PINMUX_PA27A_EIC_EXTINT11 ((PIN_PA27A_EIC_EXTINT11 << 16) | MUX_PA27A_EIC_EXTINT11) -#define PORT_PA27A_EIC_EXTINT11 ((1UL) << 27) -#define PIN_PA27A_EIC_EXTINT_NUM _L_(11) /**< EIC signal: PIN_PA27 External Interrupt Line */ - -#define PIN_PB11A_EIC_EXTINT11 (43L) -#define MUX_PB11A_EIC_EXTINT11 (0L) -#define PINMUX_PB11A_EIC_EXTINT11 ((PIN_PB11A_EIC_EXTINT11 << 16) | MUX_PB11A_EIC_EXTINT11) -#define PORT_PB11A_EIC_EXTINT11 ((1UL) << 11) -#define PIN_PB11A_EIC_EXTINT_NUM _L_(11) /**< EIC signal: PIN_PB11 External Interrupt Line */ - -#define PIN_PC11A_EIC_EXTINT11 (75L) -#define MUX_PC11A_EIC_EXTINT11 (0L) -#define PINMUX_PC11A_EIC_EXTINT11 ((PIN_PC11A_EIC_EXTINT11 << 16) | MUX_PC11A_EIC_EXTINT11) -#define PORT_PC11A_EIC_EXTINT11 ((1UL) << 11) -#define PIN_PC11A_EIC_EXTINT_NUM _L_(11) /**< EIC signal: PIN_PC11 External Interrupt Line */ - -#define PIN_PC27A_EIC_EXTINT11 (91L) -#define MUX_PC27A_EIC_EXTINT11 (0L) -#define PINMUX_PC27A_EIC_EXTINT11 ((PIN_PC27A_EIC_EXTINT11 << 16) | MUX_PC27A_EIC_EXTINT11) -#define PORT_PC27A_EIC_EXTINT11 ((1UL) << 27) -#define PIN_PC27A_EIC_EXTINT_NUM _L_(11) /**< EIC signal: PIN_PC27 External Interrupt Line */ - -#define PIN_PD21A_EIC_EXTINT11 (117L) -#define MUX_PD21A_EIC_EXTINT11 (0L) -#define PINMUX_PD21A_EIC_EXTINT11 ((PIN_PD21A_EIC_EXTINT11 << 16) | MUX_PD21A_EIC_EXTINT11) -#define PORT_PD21A_EIC_EXTINT11 ((1UL) << 21) -#define PIN_PD21A_EIC_EXTINT_NUM _L_(11) /**< EIC signal: PIN_PD21 External Interrupt Line */ - -#define PIN_PA12A_EIC_EXTINT12 (12L) -#define MUX_PA12A_EIC_EXTINT12 (0L) -#define PINMUX_PA12A_EIC_EXTINT12 ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12) -#define PORT_PA12A_EIC_EXTINT12 ((1UL) << 12) -#define PIN_PA12A_EIC_EXTINT_NUM _L_(12) /**< EIC signal: PIN_PA12 External Interrupt Line */ - -#define PIN_PB12A_EIC_EXTINT12 (44L) -#define MUX_PB12A_EIC_EXTINT12 (0L) -#define PINMUX_PB12A_EIC_EXTINT12 ((PIN_PB12A_EIC_EXTINT12 << 16) | MUX_PB12A_EIC_EXTINT12) -#define PORT_PB12A_EIC_EXTINT12 ((1UL) << 12) -#define PIN_PB12A_EIC_EXTINT_NUM _L_(12) /**< EIC signal: PIN_PB12 External Interrupt Line */ - -#define PIN_PB26A_EIC_EXTINT12 (58L) -#define MUX_PB26A_EIC_EXTINT12 (0L) -#define PINMUX_PB26A_EIC_EXTINT12 ((PIN_PB26A_EIC_EXTINT12 << 16) | MUX_PB26A_EIC_EXTINT12) -#define PORT_PB26A_EIC_EXTINT12 ((1UL) << 26) -#define PIN_PB26A_EIC_EXTINT_NUM _L_(12) /**< EIC signal: PIN_PB26 External Interrupt Line */ - -#define PIN_PC12A_EIC_EXTINT12 (76L) -#define MUX_PC12A_EIC_EXTINT12 (0L) -#define PINMUX_PC12A_EIC_EXTINT12 ((PIN_PC12A_EIC_EXTINT12 << 16) | MUX_PC12A_EIC_EXTINT12) -#define PORT_PC12A_EIC_EXTINT12 ((1UL) << 12) -#define PIN_PC12A_EIC_EXTINT_NUM _L_(12) /**< EIC signal: PIN_PC12 External Interrupt Line */ - -#define PIN_PC28A_EIC_EXTINT12 (92L) -#define MUX_PC28A_EIC_EXTINT12 (0L) -#define PINMUX_PC28A_EIC_EXTINT12 ((PIN_PC28A_EIC_EXTINT12 << 16) | MUX_PC28A_EIC_EXTINT12) -#define PORT_PC28A_EIC_EXTINT12 ((1UL) << 28) -#define PIN_PC28A_EIC_EXTINT_NUM _L_(12) /**< EIC signal: PIN_PC28 External Interrupt Line */ - -#define PIN_PA13A_EIC_EXTINT13 (13L) -#define MUX_PA13A_EIC_EXTINT13 (0L) -#define PINMUX_PA13A_EIC_EXTINT13 ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13) -#define PORT_PA13A_EIC_EXTINT13 ((1UL) << 13) -#define PIN_PA13A_EIC_EXTINT_NUM _L_(13) /**< EIC signal: PIN_PA13 External Interrupt Line */ - -#define PIN_PB13A_EIC_EXTINT13 (45L) -#define MUX_PB13A_EIC_EXTINT13 (0L) -#define PINMUX_PB13A_EIC_EXTINT13 ((PIN_PB13A_EIC_EXTINT13 << 16) | MUX_PB13A_EIC_EXTINT13) -#define PORT_PB13A_EIC_EXTINT13 ((1UL) << 13) -#define PIN_PB13A_EIC_EXTINT_NUM _L_(13) /**< EIC signal: PIN_PB13 External Interrupt Line */ - -#define PIN_PB27A_EIC_EXTINT13 (59L) -#define MUX_PB27A_EIC_EXTINT13 (0L) -#define PINMUX_PB27A_EIC_EXTINT13 ((PIN_PB27A_EIC_EXTINT13 << 16) | MUX_PB27A_EIC_EXTINT13) -#define PORT_PB27A_EIC_EXTINT13 ((1UL) << 27) -#define PIN_PB27A_EIC_EXTINT_NUM _L_(13) /**< EIC signal: PIN_PB27 External Interrupt Line */ - -#define PIN_PC13A_EIC_EXTINT13 (77L) -#define MUX_PC13A_EIC_EXTINT13 (0L) -#define PINMUX_PC13A_EIC_EXTINT13 ((PIN_PC13A_EIC_EXTINT13 << 16) | MUX_PC13A_EIC_EXTINT13) -#define PORT_PC13A_EIC_EXTINT13 ((1UL) << 13) -#define PIN_PC13A_EIC_EXTINT_NUM _L_(13) /**< EIC signal: PIN_PC13 External Interrupt Line */ - -#define PIN_PA30A_EIC_EXTINT14 (30L) -#define MUX_PA30A_EIC_EXTINT14 (0L) -#define PINMUX_PA30A_EIC_EXTINT14 ((PIN_PA30A_EIC_EXTINT14 << 16) | MUX_PA30A_EIC_EXTINT14) -#define PORT_PA30A_EIC_EXTINT14 ((1UL) << 30) -#define PIN_PA30A_EIC_EXTINT_NUM _L_(14) /**< EIC signal: PIN_PA30 External Interrupt Line */ - -#define PIN_PB14A_EIC_EXTINT14 (46L) -#define MUX_PB14A_EIC_EXTINT14 (0L) -#define PINMUX_PB14A_EIC_EXTINT14 ((PIN_PB14A_EIC_EXTINT14 << 16) | MUX_PB14A_EIC_EXTINT14) -#define PORT_PB14A_EIC_EXTINT14 ((1UL) << 14) -#define PIN_PB14A_EIC_EXTINT_NUM _L_(14) /**< EIC signal: PIN_PB14 External Interrupt Line */ - -#define PIN_PB28A_EIC_EXTINT14 (60L) -#define MUX_PB28A_EIC_EXTINT14 (0L) -#define PINMUX_PB28A_EIC_EXTINT14 ((PIN_PB28A_EIC_EXTINT14 << 16) | MUX_PB28A_EIC_EXTINT14) -#define PORT_PB28A_EIC_EXTINT14 ((1UL) << 28) -#define PIN_PB28A_EIC_EXTINT_NUM _L_(14) /**< EIC signal: PIN_PB28 External Interrupt Line */ - -#define PIN_PB30A_EIC_EXTINT14 (62L) -#define MUX_PB30A_EIC_EXTINT14 (0L) -#define PINMUX_PB30A_EIC_EXTINT14 ((PIN_PB30A_EIC_EXTINT14 << 16) | MUX_PB30A_EIC_EXTINT14) -#define PORT_PB30A_EIC_EXTINT14 ((1UL) << 30) -#define PIN_PB30A_EIC_EXTINT_NUM _L_(14) /**< EIC signal: PIN_PB30 External Interrupt Line */ - -#define PIN_PC14A_EIC_EXTINT14 (78L) -#define MUX_PC14A_EIC_EXTINT14 (0L) -#define PINMUX_PC14A_EIC_EXTINT14 ((PIN_PC14A_EIC_EXTINT14 << 16) | MUX_PC14A_EIC_EXTINT14) -#define PORT_PC14A_EIC_EXTINT14 ((1UL) << 14) -#define PIN_PC14A_EIC_EXTINT_NUM _L_(14) /**< EIC signal: PIN_PC14 External Interrupt Line */ - -#define PIN_PC30A_EIC_EXTINT14 (94L) -#define MUX_PC30A_EIC_EXTINT14 (0L) -#define PINMUX_PC30A_EIC_EXTINT14 ((PIN_PC30A_EIC_EXTINT14 << 16) | MUX_PC30A_EIC_EXTINT14) -#define PORT_PC30A_EIC_EXTINT14 ((1UL) << 30) -#define PIN_PC30A_EIC_EXTINT_NUM _L_(14) /**< EIC signal: PIN_PC30 External Interrupt Line */ - -#define PIN_PA14A_EIC_EXTINT14 (14L) -#define MUX_PA14A_EIC_EXTINT14 (0L) -#define PINMUX_PA14A_EIC_EXTINT14 ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14) -#define PORT_PA14A_EIC_EXTINT14 ((1UL) << 14) -#define PIN_PA14A_EIC_EXTINT_NUM _L_(14) /**< EIC signal: PIN_PA14 External Interrupt Line */ - -#define PIN_PA15A_EIC_EXTINT15 (15L) -#define MUX_PA15A_EIC_EXTINT15 (0L) -#define PINMUX_PA15A_EIC_EXTINT15 ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15) -#define PORT_PA15A_EIC_EXTINT15 ((1UL) << 15) -#define PIN_PA15A_EIC_EXTINT_NUM _L_(15) /**< EIC signal: PIN_PA15 External Interrupt Line */ - -#define PIN_PA31A_EIC_EXTINT15 (31L) -#define MUX_PA31A_EIC_EXTINT15 (0L) -#define PINMUX_PA31A_EIC_EXTINT15 ((PIN_PA31A_EIC_EXTINT15 << 16) | MUX_PA31A_EIC_EXTINT15) -#define PORT_PA31A_EIC_EXTINT15 ((1UL) << 31) -#define PIN_PA31A_EIC_EXTINT_NUM _L_(15) /**< EIC signal: PIN_PA31 External Interrupt Line */ - -#define PIN_PB15A_EIC_EXTINT15 (47L) -#define MUX_PB15A_EIC_EXTINT15 (0L) -#define PINMUX_PB15A_EIC_EXTINT15 ((PIN_PB15A_EIC_EXTINT15 << 16) | MUX_PB15A_EIC_EXTINT15) -#define PORT_PB15A_EIC_EXTINT15 ((1UL) << 15) -#define PIN_PB15A_EIC_EXTINT_NUM _L_(15) /**< EIC signal: PIN_PB15 External Interrupt Line */ - -#define PIN_PB29A_EIC_EXTINT15 (61L) -#define MUX_PB29A_EIC_EXTINT15 (0L) -#define PINMUX_PB29A_EIC_EXTINT15 ((PIN_PB29A_EIC_EXTINT15 << 16) | MUX_PB29A_EIC_EXTINT15) -#define PORT_PB29A_EIC_EXTINT15 ((1UL) << 29) -#define PIN_PB29A_EIC_EXTINT_NUM _L_(15) /**< EIC signal: PIN_PB29 External Interrupt Line */ - -#define PIN_PB31A_EIC_EXTINT15 (63L) -#define MUX_PB31A_EIC_EXTINT15 (0L) -#define PINMUX_PB31A_EIC_EXTINT15 ((PIN_PB31A_EIC_EXTINT15 << 16) | MUX_PB31A_EIC_EXTINT15) -#define PORT_PB31A_EIC_EXTINT15 ((1UL) << 31) -#define PIN_PB31A_EIC_EXTINT_NUM _L_(15) /**< EIC signal: PIN_PB31 External Interrupt Line */ - -#define PIN_PC15A_EIC_EXTINT15 (79L) -#define MUX_PC15A_EIC_EXTINT15 (0L) -#define PINMUX_PC15A_EIC_EXTINT15 ((PIN_PC15A_EIC_EXTINT15 << 16) | MUX_PC15A_EIC_EXTINT15) -#define PORT_PC15A_EIC_EXTINT15 ((1UL) << 15) -#define PIN_PC15A_EIC_EXTINT_NUM _L_(15) /**< EIC signal: PIN_PC15 External Interrupt Line */ - -#define PIN_PC31A_EIC_EXTINT15 (95L) -#define MUX_PC31A_EIC_EXTINT15 (0L) -#define PINMUX_PC31A_EIC_EXTINT15 ((PIN_PC31A_EIC_EXTINT15 << 16) | MUX_PC31A_EIC_EXTINT15) -#define PORT_PC31A_EIC_EXTINT15 ((1UL) << 31) -#define PIN_PC31A_EIC_EXTINT_NUM _L_(15) /**< EIC signal: PIN_PC31 External Interrupt Line */ - -#define PIN_PA08A_EIC_NMI (8L) -#define MUX_PA08A_EIC_NMI (0L) -#define PINMUX_PA08A_EIC_NMI ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI) -#define PORT_PA08A_EIC_NMI ((1UL) << 8) - -/* ========== PORT definition for GCLK peripheral ========== */ -#define PIN_PA30M_GCLK_IO0 (30L) -#define MUX_PA30M_GCLK_IO0 (12L) -#define PINMUX_PA30M_GCLK_IO0 ((PIN_PA30M_GCLK_IO0 << 16) | MUX_PA30M_GCLK_IO0) -#define PORT_PA30M_GCLK_IO0 ((1UL) << 30) - -#define PIN_PB14M_GCLK_IO0 (46L) -#define MUX_PB14M_GCLK_IO0 (12L) -#define PINMUX_PB14M_GCLK_IO0 ((PIN_PB14M_GCLK_IO0 << 16) | MUX_PB14M_GCLK_IO0) -#define PORT_PB14M_GCLK_IO0 ((1UL) << 14) - -#define PIN_PA14M_GCLK_IO0 (14L) -#define MUX_PA14M_GCLK_IO0 (12L) -#define PINMUX_PA14M_GCLK_IO0 ((PIN_PA14M_GCLK_IO0 << 16) | MUX_PA14M_GCLK_IO0) -#define PORT_PA14M_GCLK_IO0 ((1UL) << 14) - -#define PIN_PB22M_GCLK_IO0 (54L) -#define MUX_PB22M_GCLK_IO0 (12L) -#define PINMUX_PB22M_GCLK_IO0 ((PIN_PB22M_GCLK_IO0 << 16) | MUX_PB22M_GCLK_IO0) -#define PORT_PB22M_GCLK_IO0 ((1UL) << 22) - -#define PIN_PB15M_GCLK_IO1 (47L) -#define MUX_PB15M_GCLK_IO1 (12L) -#define PINMUX_PB15M_GCLK_IO1 ((PIN_PB15M_GCLK_IO1 << 16) | MUX_PB15M_GCLK_IO1) -#define PORT_PB15M_GCLK_IO1 ((1UL) << 15) - -#define PIN_PA15M_GCLK_IO1 (15L) -#define MUX_PA15M_GCLK_IO1 (12L) -#define PINMUX_PA15M_GCLK_IO1 ((PIN_PA15M_GCLK_IO1 << 16) | MUX_PA15M_GCLK_IO1) -#define PORT_PA15M_GCLK_IO1 ((1UL) << 15) - -#define PIN_PB23M_GCLK_IO1 (55L) -#define MUX_PB23M_GCLK_IO1 (12L) -#define PINMUX_PB23M_GCLK_IO1 ((PIN_PB23M_GCLK_IO1 << 16) | MUX_PB23M_GCLK_IO1) -#define PORT_PB23M_GCLK_IO1 ((1UL) << 23) - -#define PIN_PA27M_GCLK_IO1 (27L) -#define MUX_PA27M_GCLK_IO1 (12L) -#define PINMUX_PA27M_GCLK_IO1 ((PIN_PA27M_GCLK_IO1 << 16) | MUX_PA27M_GCLK_IO1) -#define PORT_PA27M_GCLK_IO1 ((1UL) << 27) - -#define PIN_PA16M_GCLK_IO2 (16L) -#define MUX_PA16M_GCLK_IO2 (12L) -#define PINMUX_PA16M_GCLK_IO2 ((PIN_PA16M_GCLK_IO2 << 16) | MUX_PA16M_GCLK_IO2) -#define PORT_PA16M_GCLK_IO2 ((1UL) << 16) - -#define PIN_PB16M_GCLK_IO2 (48L) -#define MUX_PB16M_GCLK_IO2 (12L) -#define PINMUX_PB16M_GCLK_IO2 ((PIN_PB16M_GCLK_IO2 << 16) | MUX_PB16M_GCLK_IO2) -#define PORT_PB16M_GCLK_IO2 ((1UL) << 16) - -#define PIN_PA17M_GCLK_IO3 (17L) -#define MUX_PA17M_GCLK_IO3 (12L) -#define PINMUX_PA17M_GCLK_IO3 ((PIN_PA17M_GCLK_IO3 << 16) | MUX_PA17M_GCLK_IO3) -#define PORT_PA17M_GCLK_IO3 ((1UL) << 17) - -#define PIN_PB17M_GCLK_IO3 (49L) -#define MUX_PB17M_GCLK_IO3 (12L) -#define PINMUX_PB17M_GCLK_IO3 ((PIN_PB17M_GCLK_IO3 << 16) | MUX_PB17M_GCLK_IO3) -#define PORT_PB17M_GCLK_IO3 ((1UL) << 17) - -#define PIN_PA10M_GCLK_IO4 (10L) -#define MUX_PA10M_GCLK_IO4 (12L) -#define PINMUX_PA10M_GCLK_IO4 ((PIN_PA10M_GCLK_IO4 << 16) | MUX_PA10M_GCLK_IO4) -#define PORT_PA10M_GCLK_IO4 ((1UL) << 10) - -#define PIN_PB10M_GCLK_IO4 (42L) -#define MUX_PB10M_GCLK_IO4 (12L) -#define PINMUX_PB10M_GCLK_IO4 ((PIN_PB10M_GCLK_IO4 << 16) | MUX_PB10M_GCLK_IO4) -#define PORT_PB10M_GCLK_IO4 ((1UL) << 10) - -#define PIN_PB18M_GCLK_IO4 (50L) -#define MUX_PB18M_GCLK_IO4 (12L) -#define PINMUX_PB18M_GCLK_IO4 ((PIN_PB18M_GCLK_IO4 << 16) | MUX_PB18M_GCLK_IO4) -#define PORT_PB18M_GCLK_IO4 ((1UL) << 18) - -#define PIN_PA11M_GCLK_IO5 (11L) -#define MUX_PA11M_GCLK_IO5 (12L) -#define PINMUX_PA11M_GCLK_IO5 ((PIN_PA11M_GCLK_IO5 << 16) | MUX_PA11M_GCLK_IO5) -#define PORT_PA11M_GCLK_IO5 ((1UL) << 11) - -#define PIN_PB11M_GCLK_IO5 (43L) -#define MUX_PB11M_GCLK_IO5 (12L) -#define PINMUX_PB11M_GCLK_IO5 ((PIN_PB11M_GCLK_IO5 << 16) | MUX_PB11M_GCLK_IO5) -#define PORT_PB11M_GCLK_IO5 ((1UL) << 11) - -#define PIN_PB19M_GCLK_IO5 (51L) -#define MUX_PB19M_GCLK_IO5 (12L) -#define PINMUX_PB19M_GCLK_IO5 ((PIN_PB19M_GCLK_IO5 << 16) | MUX_PB19M_GCLK_IO5) -#define PORT_PB19M_GCLK_IO5 ((1UL) << 19) - -#define PIN_PB12M_GCLK_IO6 (44L) -#define MUX_PB12M_GCLK_IO6 (12L) -#define PINMUX_PB12M_GCLK_IO6 ((PIN_PB12M_GCLK_IO6 << 16) | MUX_PB12M_GCLK_IO6) -#define PORT_PB12M_GCLK_IO6 ((1UL) << 12) - -#define PIN_PB20M_GCLK_IO6 (52L) -#define MUX_PB20M_GCLK_IO6 (12L) -#define PINMUX_PB20M_GCLK_IO6 ((PIN_PB20M_GCLK_IO6 << 16) | MUX_PB20M_GCLK_IO6) -#define PORT_PB20M_GCLK_IO6 ((1UL) << 20) - -#define PIN_PB13M_GCLK_IO7 (45L) -#define MUX_PB13M_GCLK_IO7 (12L) -#define PINMUX_PB13M_GCLK_IO7 ((PIN_PB13M_GCLK_IO7 << 16) | MUX_PB13M_GCLK_IO7) -#define PORT_PB13M_GCLK_IO7 ((1UL) << 13) - -#define PIN_PB21M_GCLK_IO7 (53L) -#define MUX_PB21M_GCLK_IO7 (12L) -#define PINMUX_PB21M_GCLK_IO7 ((PIN_PB21M_GCLK_IO7 << 16) | MUX_PB21M_GCLK_IO7) -#define PORT_PB21M_GCLK_IO7 ((1UL) << 21) - -/* ========== PORT definition for GMAC peripheral ========== */ -#define PIN_PC21L_GMAC_GCOL (85L) -#define MUX_PC21L_GMAC_GCOL (11L) -#define PINMUX_PC21L_GMAC_GCOL ((PIN_PC21L_GMAC_GCOL << 16) | MUX_PC21L_GMAC_GCOL) -#define PORT_PC21L_GMAC_GCOL ((1UL) << 21) - -#define PIN_PA16L_GMAC_GCRS (16L) -#define MUX_PA16L_GMAC_GCRS (11L) -#define PINMUX_PA16L_GMAC_GCRS ((PIN_PA16L_GMAC_GCRS << 16) | MUX_PA16L_GMAC_GCRS) -#define PORT_PA16L_GMAC_GCRS ((1UL) << 16) - -#define PIN_PA20L_GMAC_GMDC (20L) -#define MUX_PA20L_GMAC_GMDC (11L) -#define PINMUX_PA20L_GMAC_GMDC ((PIN_PA20L_GMAC_GMDC << 16) | MUX_PA20L_GMAC_GMDC) -#define PORT_PA20L_GMAC_GMDC ((1UL) << 20) - -#define PIN_PB14L_GMAC_GMDC (46L) -#define MUX_PB14L_GMAC_GMDC (11L) -#define PINMUX_PB14L_GMAC_GMDC ((PIN_PB14L_GMAC_GMDC << 16) | MUX_PB14L_GMAC_GMDC) -#define PORT_PB14L_GMAC_GMDC ((1UL) << 14) - -#define PIN_PC11L_GMAC_GMDC (75L) -#define MUX_PC11L_GMAC_GMDC (11L) -#define PINMUX_PC11L_GMAC_GMDC ((PIN_PC11L_GMAC_GMDC << 16) | MUX_PC11L_GMAC_GMDC) -#define PORT_PC11L_GMAC_GMDC ((1UL) << 11) - -#define PIN_PC22L_GMAC_GMDC (86L) -#define MUX_PC22L_GMAC_GMDC (11L) -#define PINMUX_PC22L_GMAC_GMDC ((PIN_PC22L_GMAC_GMDC << 16) | MUX_PC22L_GMAC_GMDC) -#define PORT_PC22L_GMAC_GMDC ((1UL) << 22) - -#define PIN_PA21L_GMAC_GMDIO (21L) -#define MUX_PA21L_GMAC_GMDIO (11L) -#define PINMUX_PA21L_GMAC_GMDIO ((PIN_PA21L_GMAC_GMDIO << 16) | MUX_PA21L_GMAC_GMDIO) -#define PORT_PA21L_GMAC_GMDIO ((1UL) << 21) - -#define PIN_PB15L_GMAC_GMDIO (47L) -#define MUX_PB15L_GMAC_GMDIO (11L) -#define PINMUX_PB15L_GMAC_GMDIO ((PIN_PB15L_GMAC_GMDIO << 16) | MUX_PB15L_GMAC_GMDIO) -#define PORT_PB15L_GMAC_GMDIO ((1UL) << 15) - -#define PIN_PC12L_GMAC_GMDIO (76L) -#define MUX_PC12L_GMAC_GMDIO (11L) -#define PINMUX_PC12L_GMAC_GMDIO ((PIN_PC12L_GMAC_GMDIO << 16) | MUX_PC12L_GMAC_GMDIO) -#define PORT_PC12L_GMAC_GMDIO ((1UL) << 12) - -#define PIN_PC23L_GMAC_GMDIO (87L) -#define MUX_PC23L_GMAC_GMDIO (11L) -#define PINMUX_PC23L_GMAC_GMDIO ((PIN_PC23L_GMAC_GMDIO << 16) | MUX_PC23L_GMAC_GMDIO) -#define PORT_PC23L_GMAC_GMDIO ((1UL) << 23) - -#define PIN_PA13L_GMAC_GRX0 (13L) -#define MUX_PA13L_GMAC_GRX0 (11L) -#define PINMUX_PA13L_GMAC_GRX0 ((PIN_PA13L_GMAC_GRX0 << 16) | MUX_PA13L_GMAC_GRX0) -#define PORT_PA13L_GMAC_GRX0 ((1UL) << 13) - -#define PIN_PA12L_GMAC_GRX1 (12L) -#define MUX_PA12L_GMAC_GRX1 (11L) -#define PINMUX_PA12L_GMAC_GRX1 ((PIN_PA12L_GMAC_GRX1 << 16) | MUX_PA12L_GMAC_GRX1) -#define PORT_PA12L_GMAC_GRX1 ((1UL) << 12) - -#define PIN_PC15L_GMAC_GRX2 (79L) -#define MUX_PC15L_GMAC_GRX2 (11L) -#define PINMUX_PC15L_GMAC_GRX2 ((PIN_PC15L_GMAC_GRX2 << 16) | MUX_PC15L_GMAC_GRX2) -#define PORT_PC15L_GMAC_GRX2 ((1UL) << 15) - -#define PIN_PC14L_GMAC_GRX3 (78L) -#define MUX_PC14L_GMAC_GRX3 (11L) -#define PINMUX_PC14L_GMAC_GRX3 ((PIN_PC14L_GMAC_GRX3 << 16) | MUX_PC14L_GMAC_GRX3) -#define PORT_PC14L_GMAC_GRX3 ((1UL) << 14) - -#define PIN_PC18L_GMAC_GRXCK (82L) -#define MUX_PC18L_GMAC_GRXCK (11L) -#define PINMUX_PC18L_GMAC_GRXCK ((PIN_PC18L_GMAC_GRXCK << 16) | MUX_PC18L_GMAC_GRXCK) -#define PORT_PC18L_GMAC_GRXCK ((1UL) << 18) - -#define PIN_PC20L_GMAC_GRXDV (84L) -#define MUX_PC20L_GMAC_GRXDV (11L) -#define PINMUX_PC20L_GMAC_GRXDV ((PIN_PC20L_GMAC_GRXDV << 16) | MUX_PC20L_GMAC_GRXDV) -#define PORT_PC20L_GMAC_GRXDV ((1UL) << 20) - -#define PIN_PA15L_GMAC_GRXER (15L) -#define MUX_PA15L_GMAC_GRXER (11L) -#define PINMUX_PA15L_GMAC_GRXER ((PIN_PA15L_GMAC_GRXER << 16) | MUX_PA15L_GMAC_GRXER) -#define PORT_PA15L_GMAC_GRXER ((1UL) << 15) - -#define PIN_PA18L_GMAC_GTX0 (18L) -#define MUX_PA18L_GMAC_GTX0 (11L) -#define PINMUX_PA18L_GMAC_GTX0 ((PIN_PA18L_GMAC_GTX0 << 16) | MUX_PA18L_GMAC_GTX0) -#define PORT_PA18L_GMAC_GTX0 ((1UL) << 18) - -#define PIN_PA19L_GMAC_GTX1 (19L) -#define MUX_PA19L_GMAC_GTX1 (11L) -#define PINMUX_PA19L_GMAC_GTX1 ((PIN_PA19L_GMAC_GTX1 << 16) | MUX_PA19L_GMAC_GTX1) -#define PORT_PA19L_GMAC_GTX1 ((1UL) << 19) - -#define PIN_PC16L_GMAC_GTX2 (80L) -#define MUX_PC16L_GMAC_GTX2 (11L) -#define PINMUX_PC16L_GMAC_GTX2 ((PIN_PC16L_GMAC_GTX2 << 16) | MUX_PC16L_GMAC_GTX2) -#define PORT_PC16L_GMAC_GTX2 ((1UL) << 16) - -#define PIN_PC17L_GMAC_GTX3 (81L) -#define MUX_PC17L_GMAC_GTX3 (11L) -#define PINMUX_PC17L_GMAC_GTX3 ((PIN_PC17L_GMAC_GTX3 << 16) | MUX_PC17L_GMAC_GTX3) -#define PORT_PC17L_GMAC_GTX3 ((1UL) << 17) - -#define PIN_PA14L_GMAC_GTXCK (14L) -#define MUX_PA14L_GMAC_GTXCK (11L) -#define PINMUX_PA14L_GMAC_GTXCK ((PIN_PA14L_GMAC_GTXCK << 16) | MUX_PA14L_GMAC_GTXCK) -#define PORT_PA14L_GMAC_GTXCK ((1UL) << 14) - -#define PIN_PA17L_GMAC_GTXEN (17L) -#define MUX_PA17L_GMAC_GTXEN (11L) -#define PINMUX_PA17L_GMAC_GTXEN ((PIN_PA17L_GMAC_GTXEN << 16) | MUX_PA17L_GMAC_GTXEN) -#define PORT_PA17L_GMAC_GTXEN ((1UL) << 17) - -#define PIN_PC19L_GMAC_GTXER (83L) -#define MUX_PC19L_GMAC_GTXER (11L) -#define PINMUX_PC19L_GMAC_GTXER ((PIN_PC19L_GMAC_GTXER << 16) | MUX_PC19L_GMAC_GTXER) -#define PORT_PC19L_GMAC_GTXER ((1UL) << 19) - -/* ========== PORT definition for I2S peripheral ========== */ -#define PIN_PA09J_I2S_FS0 (9L) -#define MUX_PA09J_I2S_FS0 (9L) -#define PINMUX_PA09J_I2S_FS0 ((PIN_PA09J_I2S_FS0 << 16) | MUX_PA09J_I2S_FS0) -#define PORT_PA09J_I2S_FS0 ((1UL) << 9) - -#define PIN_PA20J_I2S_FS0 (20L) -#define MUX_PA20J_I2S_FS0 (9L) -#define PINMUX_PA20J_I2S_FS0 ((PIN_PA20J_I2S_FS0 << 16) | MUX_PA20J_I2S_FS0) -#define PORT_PA20J_I2S_FS0 ((1UL) << 20) - -#define PIN_PA23J_I2S_FS1 (23L) -#define MUX_PA23J_I2S_FS1 (9L) -#define PINMUX_PA23J_I2S_FS1 ((PIN_PA23J_I2S_FS1 << 16) | MUX_PA23J_I2S_FS1) -#define PORT_PA23J_I2S_FS1 ((1UL) << 23) - -#define PIN_PB11J_I2S_FS1 (43L) -#define MUX_PB11J_I2S_FS1 (9L) -#define PINMUX_PB11J_I2S_FS1 ((PIN_PB11J_I2S_FS1 << 16) | MUX_PB11J_I2S_FS1) -#define PORT_PB11J_I2S_FS1 ((1UL) << 11) - -#define PIN_PA08J_I2S_MCK0 (8L) -#define MUX_PA08J_I2S_MCK0 (9L) -#define PINMUX_PA08J_I2S_MCK0 ((PIN_PA08J_I2S_MCK0 << 16) | MUX_PA08J_I2S_MCK0) -#define PORT_PA08J_I2S_MCK0 ((1UL) << 8) - -#define PIN_PB17J_I2S_MCK0 (49L) -#define MUX_PB17J_I2S_MCK0 (9L) -#define PINMUX_PB17J_I2S_MCK0 ((PIN_PB17J_I2S_MCK0 << 16) | MUX_PB17J_I2S_MCK0) -#define PORT_PB17J_I2S_MCK0 ((1UL) << 17) - -#define PIN_PB29J_I2S_MCK1 (61L) -#define MUX_PB29J_I2S_MCK1 (9L) -#define PINMUX_PB29J_I2S_MCK1 ((PIN_PB29J_I2S_MCK1 << 16) | MUX_PB29J_I2S_MCK1) -#define PORT_PB29J_I2S_MCK1 ((1UL) << 29) - -#define PIN_PB13J_I2S_MCK1 (45L) -#define MUX_PB13J_I2S_MCK1 (9L) -#define PINMUX_PB13J_I2S_MCK1 ((PIN_PB13J_I2S_MCK1 << 16) | MUX_PB13J_I2S_MCK1) -#define PORT_PB13J_I2S_MCK1 ((1UL) << 13) - -#define PIN_PA10J_I2S_SCK0 (10L) -#define MUX_PA10J_I2S_SCK0 (9L) -#define PINMUX_PA10J_I2S_SCK0 ((PIN_PA10J_I2S_SCK0 << 16) | MUX_PA10J_I2S_SCK0) -#define PORT_PA10J_I2S_SCK0 ((1UL) << 10) - -#define PIN_PB16J_I2S_SCK0 (48L) -#define MUX_PB16J_I2S_SCK0 (9L) -#define PINMUX_PB16J_I2S_SCK0 ((PIN_PB16J_I2S_SCK0 << 16) | MUX_PB16J_I2S_SCK0) -#define PORT_PB16J_I2S_SCK0 ((1UL) << 16) - -#define PIN_PB28J_I2S_SCK1 (60L) -#define MUX_PB28J_I2S_SCK1 (9L) -#define PINMUX_PB28J_I2S_SCK1 ((PIN_PB28J_I2S_SCK1 << 16) | MUX_PB28J_I2S_SCK1) -#define PORT_PB28J_I2S_SCK1 ((1UL) << 28) - -#define PIN_PB12J_I2S_SCK1 (44L) -#define MUX_PB12J_I2S_SCK1 (9L) -#define PINMUX_PB12J_I2S_SCK1 ((PIN_PB12J_I2S_SCK1 << 16) | MUX_PB12J_I2S_SCK1) -#define PORT_PB12J_I2S_SCK1 ((1UL) << 12) - -#define PIN_PA22J_I2S_SDI (22L) -#define MUX_PA22J_I2S_SDI (9L) -#define PINMUX_PA22J_I2S_SDI ((PIN_PA22J_I2S_SDI << 16) | MUX_PA22J_I2S_SDI) -#define PORT_PA22J_I2S_SDI ((1UL) << 22) - -#define PIN_PB10J_I2S_SDI (42L) -#define MUX_PB10J_I2S_SDI (9L) -#define PINMUX_PB10J_I2S_SDI ((PIN_PB10J_I2S_SDI << 16) | MUX_PB10J_I2S_SDI) -#define PORT_PB10J_I2S_SDI ((1UL) << 10) - -#define PIN_PA11J_I2S_SDO (11L) -#define MUX_PA11J_I2S_SDO (9L) -#define PINMUX_PA11J_I2S_SDO ((PIN_PA11J_I2S_SDO << 16) | MUX_PA11J_I2S_SDO) -#define PORT_PA11J_I2S_SDO ((1UL) << 11) - -#define PIN_PA21J_I2S_SDO (21L) -#define MUX_PA21J_I2S_SDO (9L) -#define PINMUX_PA21J_I2S_SDO ((PIN_PA21J_I2S_SDO << 16) | MUX_PA21J_I2S_SDO) -#define PORT_PA21J_I2S_SDO ((1UL) << 21) - -/* ========== PORT definition for PCC peripheral ========== */ -#define PIN_PA14K_PCC_CLK (14L) -#define MUX_PA14K_PCC_CLK (10L) -#define PINMUX_PA14K_PCC_CLK ((PIN_PA14K_PCC_CLK << 16) | MUX_PA14K_PCC_CLK) -#define PORT_PA14K_PCC_CLK ((1UL) << 14) - -#define PIN_PA16K_PCC_DATA0 (16L) -#define MUX_PA16K_PCC_DATA0 (10L) -#define PINMUX_PA16K_PCC_DATA0 ((PIN_PA16K_PCC_DATA0 << 16) | MUX_PA16K_PCC_DATA0) -#define PORT_PA16K_PCC_DATA0 ((1UL) << 16) - -#define PIN_PA17K_PCC_DATA1 (17L) -#define MUX_PA17K_PCC_DATA1 (10L) -#define PINMUX_PA17K_PCC_DATA1 ((PIN_PA17K_PCC_DATA1 << 16) | MUX_PA17K_PCC_DATA1) -#define PORT_PA17K_PCC_DATA1 ((1UL) << 17) - -#define PIN_PA18K_PCC_DATA2 (18L) -#define MUX_PA18K_PCC_DATA2 (10L) -#define PINMUX_PA18K_PCC_DATA2 ((PIN_PA18K_PCC_DATA2 << 16) | MUX_PA18K_PCC_DATA2) -#define PORT_PA18K_PCC_DATA2 ((1UL) << 18) - -#define PIN_PA19K_PCC_DATA3 (19L) -#define MUX_PA19K_PCC_DATA3 (10L) -#define PINMUX_PA19K_PCC_DATA3 ((PIN_PA19K_PCC_DATA3 << 16) | MUX_PA19K_PCC_DATA3) -#define PORT_PA19K_PCC_DATA3 ((1UL) << 19) - -#define PIN_PA20K_PCC_DATA4 (20L) -#define MUX_PA20K_PCC_DATA4 (10L) -#define PINMUX_PA20K_PCC_DATA4 ((PIN_PA20K_PCC_DATA4 << 16) | MUX_PA20K_PCC_DATA4) -#define PORT_PA20K_PCC_DATA4 ((1UL) << 20) - -#define PIN_PA21K_PCC_DATA5 (21L) -#define MUX_PA21K_PCC_DATA5 (10L) -#define PINMUX_PA21K_PCC_DATA5 ((PIN_PA21K_PCC_DATA5 << 16) | MUX_PA21K_PCC_DATA5) -#define PORT_PA21K_PCC_DATA5 ((1UL) << 21) - -#define PIN_PA22K_PCC_DATA6 (22L) -#define MUX_PA22K_PCC_DATA6 (10L) -#define PINMUX_PA22K_PCC_DATA6 ((PIN_PA22K_PCC_DATA6 << 16) | MUX_PA22K_PCC_DATA6) -#define PORT_PA22K_PCC_DATA6 ((1UL) << 22) - -#define PIN_PA23K_PCC_DATA7 (23L) -#define MUX_PA23K_PCC_DATA7 (10L) -#define PINMUX_PA23K_PCC_DATA7 ((PIN_PA23K_PCC_DATA7 << 16) | MUX_PA23K_PCC_DATA7) -#define PORT_PA23K_PCC_DATA7 ((1UL) << 23) - -#define PIN_PB14K_PCC_DATA8 (46L) -#define MUX_PB14K_PCC_DATA8 (10L) -#define PINMUX_PB14K_PCC_DATA8 ((PIN_PB14K_PCC_DATA8 << 16) | MUX_PB14K_PCC_DATA8) -#define PORT_PB14K_PCC_DATA8 ((1UL) << 14) - -#define PIN_PB15K_PCC_DATA9 (47L) -#define MUX_PB15K_PCC_DATA9 (10L) -#define PINMUX_PB15K_PCC_DATA9 ((PIN_PB15K_PCC_DATA9 << 16) | MUX_PB15K_PCC_DATA9) -#define PORT_PB15K_PCC_DATA9 ((1UL) << 15) - -#define PIN_PC12K_PCC_DATA10 (76L) -#define MUX_PC12K_PCC_DATA10 (10L) -#define PINMUX_PC12K_PCC_DATA10 ((PIN_PC12K_PCC_DATA10 << 16) | MUX_PC12K_PCC_DATA10) -#define PORT_PC12K_PCC_DATA10 ((1UL) << 12) - -#define PIN_PC13K_PCC_DATA11 (77L) -#define MUX_PC13K_PCC_DATA11 (10L) -#define PINMUX_PC13K_PCC_DATA11 ((PIN_PC13K_PCC_DATA11 << 16) | MUX_PC13K_PCC_DATA11) -#define PORT_PC13K_PCC_DATA11 ((1UL) << 13) - -#define PIN_PC14K_PCC_DATA12 (78L) -#define MUX_PC14K_PCC_DATA12 (10L) -#define PINMUX_PC14K_PCC_DATA12 ((PIN_PC14K_PCC_DATA12 << 16) | MUX_PC14K_PCC_DATA12) -#define PORT_PC14K_PCC_DATA12 ((1UL) << 14) - -#define PIN_PC15K_PCC_DATA13 (79L) -#define MUX_PC15K_PCC_DATA13 (10L) -#define PINMUX_PC15K_PCC_DATA13 ((PIN_PC15K_PCC_DATA13 << 16) | MUX_PC15K_PCC_DATA13) -#define PORT_PC15K_PCC_DATA13 ((1UL) << 15) - -#define PIN_PA12K_PCC_DEN1 (12L) -#define MUX_PA12K_PCC_DEN1 (10L) -#define PINMUX_PA12K_PCC_DEN1 ((PIN_PA12K_PCC_DEN1 << 16) | MUX_PA12K_PCC_DEN1) -#define PORT_PA12K_PCC_DEN1 ((1UL) << 12) - -#define PIN_PA13K_PCC_DEN2 (13L) -#define MUX_PA13K_PCC_DEN2 (10L) -#define PINMUX_PA13K_PCC_DEN2 ((PIN_PA13K_PCC_DEN2 << 16) | MUX_PA13K_PCC_DEN2) -#define PORT_PA13K_PCC_DEN2 ((1UL) << 13) - -/* ========== PORT definition for PDEC peripheral ========== */ -#define PIN_PB18G_PDEC_QDI0 (50L) -#define MUX_PB18G_PDEC_QDI0 (6L) -#define PINMUX_PB18G_PDEC_QDI0 ((PIN_PB18G_PDEC_QDI0 << 16) | MUX_PB18G_PDEC_QDI0) -#define PORT_PB18G_PDEC_QDI0 ((1UL) << 18) - -#define PIN_PB23G_PDEC_QDI0 (55L) -#define MUX_PB23G_PDEC_QDI0 (6L) -#define PINMUX_PB23G_PDEC_QDI0 ((PIN_PB23G_PDEC_QDI0 << 16) | MUX_PB23G_PDEC_QDI0) -#define PORT_PB23G_PDEC_QDI0 ((1UL) << 23) - -#define PIN_PC16G_PDEC_QDI0 (80L) -#define MUX_PC16G_PDEC_QDI0 (6L) -#define PINMUX_PC16G_PDEC_QDI0 ((PIN_PC16G_PDEC_QDI0 << 16) | MUX_PC16G_PDEC_QDI0) -#define PORT_PC16G_PDEC_QDI0 ((1UL) << 16) - -#define PIN_PA24G_PDEC_QDI0 (24L) -#define MUX_PA24G_PDEC_QDI0 (6L) -#define PINMUX_PA24G_PDEC_QDI0 ((PIN_PA24G_PDEC_QDI0 << 16) | MUX_PA24G_PDEC_QDI0) -#define PORT_PA24G_PDEC_QDI0 ((1UL) << 24) - -#define PIN_PB19G_PDEC_QDI1 (51L) -#define MUX_PB19G_PDEC_QDI1 (6L) -#define PINMUX_PB19G_PDEC_QDI1 ((PIN_PB19G_PDEC_QDI1 << 16) | MUX_PB19G_PDEC_QDI1) -#define PORT_PB19G_PDEC_QDI1 ((1UL) << 19) - -#define PIN_PB24G_PDEC_QDI1 (56L) -#define MUX_PB24G_PDEC_QDI1 (6L) -#define PINMUX_PB24G_PDEC_QDI1 ((PIN_PB24G_PDEC_QDI1 << 16) | MUX_PB24G_PDEC_QDI1) -#define PORT_PB24G_PDEC_QDI1 ((1UL) << 24) - -#define PIN_PC17G_PDEC_QDI1 (81L) -#define MUX_PC17G_PDEC_QDI1 (6L) -#define PINMUX_PC17G_PDEC_QDI1 ((PIN_PC17G_PDEC_QDI1 << 16) | MUX_PC17G_PDEC_QDI1) -#define PORT_PC17G_PDEC_QDI1 ((1UL) << 17) - -#define PIN_PA25G_PDEC_QDI1 (25L) -#define MUX_PA25G_PDEC_QDI1 (6L) -#define PINMUX_PA25G_PDEC_QDI1 ((PIN_PA25G_PDEC_QDI1 << 16) | MUX_PA25G_PDEC_QDI1) -#define PORT_PA25G_PDEC_QDI1 ((1UL) << 25) - -#define PIN_PB20G_PDEC_QDI2 (52L) -#define MUX_PB20G_PDEC_QDI2 (6L) -#define PINMUX_PB20G_PDEC_QDI2 ((PIN_PB20G_PDEC_QDI2 << 16) | MUX_PB20G_PDEC_QDI2) -#define PORT_PB20G_PDEC_QDI2 ((1UL) << 20) - -#define PIN_PB25G_PDEC_QDI2 (57L) -#define MUX_PB25G_PDEC_QDI2 (6L) -#define PINMUX_PB25G_PDEC_QDI2 ((PIN_PB25G_PDEC_QDI2 << 16) | MUX_PB25G_PDEC_QDI2) -#define PORT_PB25G_PDEC_QDI2 ((1UL) << 25) - -#define PIN_PC18G_PDEC_QDI2 (82L) -#define MUX_PC18G_PDEC_QDI2 (6L) -#define PINMUX_PC18G_PDEC_QDI2 ((PIN_PC18G_PDEC_QDI2 << 16) | MUX_PC18G_PDEC_QDI2) -#define PORT_PC18G_PDEC_QDI2 ((1UL) << 18) - -#define PIN_PB22G_PDEC_QDI2 (54L) -#define MUX_PB22G_PDEC_QDI2 (6L) -#define PINMUX_PB22G_PDEC_QDI2 ((PIN_PB22G_PDEC_QDI2 << 16) | MUX_PB22G_PDEC_QDI2) -#define PORT_PB22G_PDEC_QDI2 ((1UL) << 22) - -/* ========== PORT definition for QSPI peripheral ========== */ -#define PIN_PB11H_QSPI_CS (43L) -#define MUX_PB11H_QSPI_CS (7L) -#define PINMUX_PB11H_QSPI_CS ((PIN_PB11H_QSPI_CS << 16) | MUX_PB11H_QSPI_CS) -#define PORT_PB11H_QSPI_CS ((1UL) << 11) - -#define PIN_PA08H_QSPI_DATA0 (8L) -#define MUX_PA08H_QSPI_DATA0 (7L) -#define PINMUX_PA08H_QSPI_DATA0 ((PIN_PA08H_QSPI_DATA0 << 16) | MUX_PA08H_QSPI_DATA0) -#define PORT_PA08H_QSPI_DATA0 ((1UL) << 8) - -#define PIN_PA09H_QSPI_DATA1 (9L) -#define MUX_PA09H_QSPI_DATA1 (7L) -#define PINMUX_PA09H_QSPI_DATA1 ((PIN_PA09H_QSPI_DATA1 << 16) | MUX_PA09H_QSPI_DATA1) -#define PORT_PA09H_QSPI_DATA1 ((1UL) << 9) - -#define PIN_PA10H_QSPI_DATA2 (10L) -#define MUX_PA10H_QSPI_DATA2 (7L) -#define PINMUX_PA10H_QSPI_DATA2 ((PIN_PA10H_QSPI_DATA2 << 16) | MUX_PA10H_QSPI_DATA2) -#define PORT_PA10H_QSPI_DATA2 ((1UL) << 10) - -#define PIN_PA11H_QSPI_DATA3 (11L) -#define MUX_PA11H_QSPI_DATA3 (7L) -#define PINMUX_PA11H_QSPI_DATA3 ((PIN_PA11H_QSPI_DATA3 << 16) | MUX_PA11H_QSPI_DATA3) -#define PORT_PA11H_QSPI_DATA3 ((1UL) << 11) - -#define PIN_PB10H_QSPI_SCK (42L) -#define MUX_PB10H_QSPI_SCK (7L) -#define PINMUX_PB10H_QSPI_SCK ((PIN_PB10H_QSPI_SCK << 16) | MUX_PB10H_QSPI_SCK) -#define PORT_PB10H_QSPI_SCK ((1UL) << 10) - -/* ========== PORT definition for SDHC0 peripheral ========== */ -#define PIN_PA06I_SDHC0_SDCD (6L) -#define MUX_PA06I_SDHC0_SDCD (8L) -#define PINMUX_PA06I_SDHC0_SDCD ((PIN_PA06I_SDHC0_SDCD << 16) | MUX_PA06I_SDHC0_SDCD) -#define PORT_PA06I_SDHC0_SDCD ((1UL) << 6) - -#define PIN_PA12I_SDHC0_SDCD (12L) -#define MUX_PA12I_SDHC0_SDCD (8L) -#define PINMUX_PA12I_SDHC0_SDCD ((PIN_PA12I_SDHC0_SDCD << 16) | MUX_PA12I_SDHC0_SDCD) -#define PORT_PA12I_SDHC0_SDCD ((1UL) << 12) - -#define PIN_PB12I_SDHC0_SDCD (44L) -#define MUX_PB12I_SDHC0_SDCD (8L) -#define PINMUX_PB12I_SDHC0_SDCD ((PIN_PB12I_SDHC0_SDCD << 16) | MUX_PB12I_SDHC0_SDCD) -#define PORT_PB12I_SDHC0_SDCD ((1UL) << 12) - -#define PIN_PC06I_SDHC0_SDCD (70L) -#define MUX_PC06I_SDHC0_SDCD (8L) -#define PINMUX_PC06I_SDHC0_SDCD ((PIN_PC06I_SDHC0_SDCD << 16) | MUX_PC06I_SDHC0_SDCD) -#define PORT_PC06I_SDHC0_SDCD ((1UL) << 6) - -#define PIN_PB11I_SDHC0_SDCK (43L) -#define MUX_PB11I_SDHC0_SDCK (8L) -#define PINMUX_PB11I_SDHC0_SDCK ((PIN_PB11I_SDHC0_SDCK << 16) | MUX_PB11I_SDHC0_SDCK) -#define PORT_PB11I_SDHC0_SDCK ((1UL) << 11) - -#define PIN_PA08I_SDHC0_SDCMD (8L) -#define MUX_PA08I_SDHC0_SDCMD (8L) -#define PINMUX_PA08I_SDHC0_SDCMD ((PIN_PA08I_SDHC0_SDCMD << 16) | MUX_PA08I_SDHC0_SDCMD) -#define PORT_PA08I_SDHC0_SDCMD ((1UL) << 8) - -#define PIN_PA09I_SDHC0_SDDAT0 (9L) -#define MUX_PA09I_SDHC0_SDDAT0 (8L) -#define PINMUX_PA09I_SDHC0_SDDAT0 ((PIN_PA09I_SDHC0_SDDAT0 << 16) | MUX_PA09I_SDHC0_SDDAT0) -#define PORT_PA09I_SDHC0_SDDAT0 ((1UL) << 9) - -#define PIN_PA10I_SDHC0_SDDAT1 (10L) -#define MUX_PA10I_SDHC0_SDDAT1 (8L) -#define PINMUX_PA10I_SDHC0_SDDAT1 ((PIN_PA10I_SDHC0_SDDAT1 << 16) | MUX_PA10I_SDHC0_SDDAT1) -#define PORT_PA10I_SDHC0_SDDAT1 ((1UL) << 10) - -#define PIN_PA11I_SDHC0_SDDAT2 (11L) -#define MUX_PA11I_SDHC0_SDDAT2 (8L) -#define PINMUX_PA11I_SDHC0_SDDAT2 ((PIN_PA11I_SDHC0_SDDAT2 << 16) | MUX_PA11I_SDHC0_SDDAT2) -#define PORT_PA11I_SDHC0_SDDAT2 ((1UL) << 11) - -#define PIN_PB10I_SDHC0_SDDAT3 (42L) -#define MUX_PB10I_SDHC0_SDDAT3 (8L) -#define PINMUX_PB10I_SDHC0_SDDAT3 ((PIN_PB10I_SDHC0_SDDAT3 << 16) | MUX_PB10I_SDHC0_SDDAT3) -#define PORT_PB10I_SDHC0_SDDAT3 ((1UL) << 10) - -#define PIN_PA07I_SDHC0_SDWP (7L) -#define MUX_PA07I_SDHC0_SDWP (8L) -#define PINMUX_PA07I_SDHC0_SDWP ((PIN_PA07I_SDHC0_SDWP << 16) | MUX_PA07I_SDHC0_SDWP) -#define PORT_PA07I_SDHC0_SDWP ((1UL) << 7) - -#define PIN_PA13I_SDHC0_SDWP (13L) -#define MUX_PA13I_SDHC0_SDWP (8L) -#define PINMUX_PA13I_SDHC0_SDWP ((PIN_PA13I_SDHC0_SDWP << 16) | MUX_PA13I_SDHC0_SDWP) -#define PORT_PA13I_SDHC0_SDWP ((1UL) << 13) - -#define PIN_PB13I_SDHC0_SDWP (45L) -#define MUX_PB13I_SDHC0_SDWP (8L) -#define PINMUX_PB13I_SDHC0_SDWP ((PIN_PB13I_SDHC0_SDWP << 16) | MUX_PB13I_SDHC0_SDWP) -#define PORT_PB13I_SDHC0_SDWP ((1UL) << 13) - -#define PIN_PC07I_SDHC0_SDWP (71L) -#define MUX_PC07I_SDHC0_SDWP (8L) -#define PINMUX_PC07I_SDHC0_SDWP ((PIN_PC07I_SDHC0_SDWP << 16) | MUX_PC07I_SDHC0_SDWP) -#define PORT_PC07I_SDHC0_SDWP ((1UL) << 7) - -/* ========== PORT definition for SDHC1 peripheral ========== */ -#define PIN_PB16I_SDHC1_SDCD (48L) -#define MUX_PB16I_SDHC1_SDCD (8L) -#define PINMUX_PB16I_SDHC1_SDCD ((PIN_PB16I_SDHC1_SDCD << 16) | MUX_PB16I_SDHC1_SDCD) -#define PORT_PB16I_SDHC1_SDCD ((1UL) << 16) - -#define PIN_PC20I_SDHC1_SDCD (84L) -#define MUX_PC20I_SDHC1_SDCD (8L) -#define PINMUX_PC20I_SDHC1_SDCD ((PIN_PC20I_SDHC1_SDCD << 16) | MUX_PC20I_SDHC1_SDCD) -#define PORT_PC20I_SDHC1_SDCD ((1UL) << 20) - -#define PIN_PD20I_SDHC1_SDCD (116L) -#define MUX_PD20I_SDHC1_SDCD (8L) -#define PINMUX_PD20I_SDHC1_SDCD ((PIN_PD20I_SDHC1_SDCD << 16) | MUX_PD20I_SDHC1_SDCD) -#define PORT_PD20I_SDHC1_SDCD ((1UL) << 20) - -#define PIN_PA21I_SDHC1_SDCK (21L) -#define MUX_PA21I_SDHC1_SDCK (8L) -#define PINMUX_PA21I_SDHC1_SDCK ((PIN_PA21I_SDHC1_SDCK << 16) | MUX_PA21I_SDHC1_SDCK) -#define PORT_PA21I_SDHC1_SDCK ((1UL) << 21) - -#define PIN_PA20I_SDHC1_SDCMD (20L) -#define MUX_PA20I_SDHC1_SDCMD (8L) -#define PINMUX_PA20I_SDHC1_SDCMD ((PIN_PA20I_SDHC1_SDCMD << 16) | MUX_PA20I_SDHC1_SDCMD) -#define PORT_PA20I_SDHC1_SDCMD ((1UL) << 20) - -#define PIN_PB18I_SDHC1_SDDAT0 (50L) -#define MUX_PB18I_SDHC1_SDDAT0 (8L) -#define PINMUX_PB18I_SDHC1_SDDAT0 ((PIN_PB18I_SDHC1_SDDAT0 << 16) | MUX_PB18I_SDHC1_SDDAT0) -#define PORT_PB18I_SDHC1_SDDAT0 ((1UL) << 18) - -#define PIN_PB19I_SDHC1_SDDAT1 (51L) -#define MUX_PB19I_SDHC1_SDDAT1 (8L) -#define PINMUX_PB19I_SDHC1_SDDAT1 ((PIN_PB19I_SDHC1_SDDAT1 << 16) | MUX_PB19I_SDHC1_SDDAT1) -#define PORT_PB19I_SDHC1_SDDAT1 ((1UL) << 19) - -#define PIN_PB20I_SDHC1_SDDAT2 (52L) -#define MUX_PB20I_SDHC1_SDDAT2 (8L) -#define PINMUX_PB20I_SDHC1_SDDAT2 ((PIN_PB20I_SDHC1_SDDAT2 << 16) | MUX_PB20I_SDHC1_SDDAT2) -#define PORT_PB20I_SDHC1_SDDAT2 ((1UL) << 20) - -#define PIN_PB21I_SDHC1_SDDAT3 (53L) -#define MUX_PB21I_SDHC1_SDDAT3 (8L) -#define PINMUX_PB21I_SDHC1_SDDAT3 ((PIN_PB21I_SDHC1_SDDAT3 << 16) | MUX_PB21I_SDHC1_SDDAT3) -#define PORT_PB21I_SDHC1_SDDAT3 ((1UL) << 21) - -#define PIN_PB17I_SDHC1_SDWP (49L) -#define MUX_PB17I_SDHC1_SDWP (8L) -#define PINMUX_PB17I_SDHC1_SDWP ((PIN_PB17I_SDHC1_SDWP << 16) | MUX_PB17I_SDHC1_SDWP) -#define PORT_PB17I_SDHC1_SDWP ((1UL) << 17) - -#define PIN_PC21I_SDHC1_SDWP (85L) -#define MUX_PC21I_SDHC1_SDWP (8L) -#define PINMUX_PC21I_SDHC1_SDWP ((PIN_PC21I_SDHC1_SDWP << 16) | MUX_PC21I_SDHC1_SDWP) -#define PORT_PC21I_SDHC1_SDWP ((1UL) << 21) - -#define PIN_PD21I_SDHC1_SDWP (117L) -#define MUX_PD21I_SDHC1_SDWP (8L) -#define PINMUX_PD21I_SDHC1_SDWP ((PIN_PD21I_SDHC1_SDWP << 16) | MUX_PD21I_SDHC1_SDWP) -#define PORT_PD21I_SDHC1_SDWP ((1UL) << 21) - -/* ========== PORT definition for SERCOM0 peripheral ========== */ -#define PIN_PA04D_SERCOM0_PAD0 (4L) -#define MUX_PA04D_SERCOM0_PAD0 (3L) -#define PINMUX_PA04D_SERCOM0_PAD0 ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0) -#define PORT_PA04D_SERCOM0_PAD0 ((1UL) << 4) - -#define PIN_PC17D_SERCOM0_PAD0 (81L) -#define MUX_PC17D_SERCOM0_PAD0 (3L) -#define PINMUX_PC17D_SERCOM0_PAD0 ((PIN_PC17D_SERCOM0_PAD0 << 16) | MUX_PC17D_SERCOM0_PAD0) -#define PORT_PC17D_SERCOM0_PAD0 ((1UL) << 17) - -#define PIN_PA08C_SERCOM0_PAD0 (8L) -#define MUX_PA08C_SERCOM0_PAD0 (2L) -#define PINMUX_PA08C_SERCOM0_PAD0 ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0) -#define PORT_PA08C_SERCOM0_PAD0 ((1UL) << 8) - -#define PIN_PB24C_SERCOM0_PAD0 (56L) -#define MUX_PB24C_SERCOM0_PAD0 (2L) -#define PINMUX_PB24C_SERCOM0_PAD0 ((PIN_PB24C_SERCOM0_PAD0 << 16) | MUX_PB24C_SERCOM0_PAD0) -#define PORT_PB24C_SERCOM0_PAD0 ((1UL) << 24) - -#define PIN_PA05D_SERCOM0_PAD1 (5L) -#define MUX_PA05D_SERCOM0_PAD1 (3L) -#define PINMUX_PA05D_SERCOM0_PAD1 ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1) -#define PORT_PA05D_SERCOM0_PAD1 ((1UL) << 5) - -#define PIN_PC16D_SERCOM0_PAD1 (80L) -#define MUX_PC16D_SERCOM0_PAD1 (3L) -#define PINMUX_PC16D_SERCOM0_PAD1 ((PIN_PC16D_SERCOM0_PAD1 << 16) | MUX_PC16D_SERCOM0_PAD1) -#define PORT_PC16D_SERCOM0_PAD1 ((1UL) << 16) - -#define PIN_PA09C_SERCOM0_PAD1 (9L) -#define MUX_PA09C_SERCOM0_PAD1 (2L) -#define PINMUX_PA09C_SERCOM0_PAD1 ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1) -#define PORT_PA09C_SERCOM0_PAD1 ((1UL) << 9) - -#define PIN_PB25C_SERCOM0_PAD1 (57L) -#define MUX_PB25C_SERCOM0_PAD1 (2L) -#define PINMUX_PB25C_SERCOM0_PAD1 ((PIN_PB25C_SERCOM0_PAD1 << 16) | MUX_PB25C_SERCOM0_PAD1) -#define PORT_PB25C_SERCOM0_PAD1 ((1UL) << 25) - -#define PIN_PA06D_SERCOM0_PAD2 (6L) -#define MUX_PA06D_SERCOM0_PAD2 (3L) -#define PINMUX_PA06D_SERCOM0_PAD2 ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2) -#define PORT_PA06D_SERCOM0_PAD2 ((1UL) << 6) - -#define PIN_PC18D_SERCOM0_PAD2 (82L) -#define MUX_PC18D_SERCOM0_PAD2 (3L) -#define PINMUX_PC18D_SERCOM0_PAD2 ((PIN_PC18D_SERCOM0_PAD2 << 16) | MUX_PC18D_SERCOM0_PAD2) -#define PORT_PC18D_SERCOM0_PAD2 ((1UL) << 18) - -#define PIN_PA10C_SERCOM0_PAD2 (10L) -#define MUX_PA10C_SERCOM0_PAD2 (2L) -#define PINMUX_PA10C_SERCOM0_PAD2 ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2) -#define PORT_PA10C_SERCOM0_PAD2 ((1UL) << 10) - -#define PIN_PC24C_SERCOM0_PAD2 (88L) -#define MUX_PC24C_SERCOM0_PAD2 (2L) -#define PINMUX_PC24C_SERCOM0_PAD2 ((PIN_PC24C_SERCOM0_PAD2 << 16) | MUX_PC24C_SERCOM0_PAD2) -#define PORT_PC24C_SERCOM0_PAD2 ((1UL) << 24) - -#define PIN_PA07D_SERCOM0_PAD3 (7L) -#define MUX_PA07D_SERCOM0_PAD3 (3L) -#define PINMUX_PA07D_SERCOM0_PAD3 ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3) -#define PORT_PA07D_SERCOM0_PAD3 ((1UL) << 7) - -#define PIN_PC19D_SERCOM0_PAD3 (83L) -#define MUX_PC19D_SERCOM0_PAD3 (3L) -#define PINMUX_PC19D_SERCOM0_PAD3 ((PIN_PC19D_SERCOM0_PAD3 << 16) | MUX_PC19D_SERCOM0_PAD3) -#define PORT_PC19D_SERCOM0_PAD3 ((1UL) << 19) - -#define PIN_PA11C_SERCOM0_PAD3 (11L) -#define MUX_PA11C_SERCOM0_PAD3 (2L) -#define PINMUX_PA11C_SERCOM0_PAD3 ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3) -#define PORT_PA11C_SERCOM0_PAD3 ((1UL) << 11) - -#define PIN_PC25C_SERCOM0_PAD3 (89L) -#define MUX_PC25C_SERCOM0_PAD3 (2L) -#define PINMUX_PC25C_SERCOM0_PAD3 ((PIN_PC25C_SERCOM0_PAD3 << 16) | MUX_PC25C_SERCOM0_PAD3) -#define PORT_PC25C_SERCOM0_PAD3 ((1UL) << 25) - -/* ========== PORT definition for SERCOM1 peripheral ========== */ -#define PIN_PA00D_SERCOM1_PAD0 (0L) -#define MUX_PA00D_SERCOM1_PAD0 (3L) -#define PINMUX_PA00D_SERCOM1_PAD0 ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0) -#define PORT_PA00D_SERCOM1_PAD0 ((1UL) << 0) - -#define PIN_PA16C_SERCOM1_PAD0 (16L) -#define MUX_PA16C_SERCOM1_PAD0 (2L) -#define PINMUX_PA16C_SERCOM1_PAD0 ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0) -#define PORT_PA16C_SERCOM1_PAD0 ((1UL) << 16) - -#define PIN_PC22C_SERCOM1_PAD0 (86L) -#define MUX_PC22C_SERCOM1_PAD0 (2L) -#define PINMUX_PC22C_SERCOM1_PAD0 ((PIN_PC22C_SERCOM1_PAD0 << 16) | MUX_PC22C_SERCOM1_PAD0) -#define PORT_PC22C_SERCOM1_PAD0 ((1UL) << 22) - -#define PIN_PC27C_SERCOM1_PAD0 (91L) -#define MUX_PC27C_SERCOM1_PAD0 (2L) -#define PINMUX_PC27C_SERCOM1_PAD0 ((PIN_PC27C_SERCOM1_PAD0 << 16) | MUX_PC27C_SERCOM1_PAD0) -#define PORT_PC27C_SERCOM1_PAD0 ((1UL) << 27) - -#define PIN_PA01D_SERCOM1_PAD1 (1L) -#define MUX_PA01D_SERCOM1_PAD1 (3L) -#define PINMUX_PA01D_SERCOM1_PAD1 ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1) -#define PORT_PA01D_SERCOM1_PAD1 ((1UL) << 1) - -#define PIN_PA17C_SERCOM1_PAD1 (17L) -#define MUX_PA17C_SERCOM1_PAD1 (2L) -#define PINMUX_PA17C_SERCOM1_PAD1 ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1) -#define PORT_PA17C_SERCOM1_PAD1 ((1UL) << 17) - -#define PIN_PC23C_SERCOM1_PAD1 (87L) -#define MUX_PC23C_SERCOM1_PAD1 (2L) -#define PINMUX_PC23C_SERCOM1_PAD1 ((PIN_PC23C_SERCOM1_PAD1 << 16) | MUX_PC23C_SERCOM1_PAD1) -#define PORT_PC23C_SERCOM1_PAD1 ((1UL) << 23) - -#define PIN_PC28C_SERCOM1_PAD1 (92L) -#define MUX_PC28C_SERCOM1_PAD1 (2L) -#define PINMUX_PC28C_SERCOM1_PAD1 ((PIN_PC28C_SERCOM1_PAD1 << 16) | MUX_PC28C_SERCOM1_PAD1) -#define PORT_PC28C_SERCOM1_PAD1 ((1UL) << 28) - -#define PIN_PA30D_SERCOM1_PAD2 (30L) -#define MUX_PA30D_SERCOM1_PAD2 (3L) -#define PINMUX_PA30D_SERCOM1_PAD2 ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2) -#define PORT_PA30D_SERCOM1_PAD2 ((1UL) << 30) - -#define PIN_PA18C_SERCOM1_PAD2 (18L) -#define MUX_PA18C_SERCOM1_PAD2 (2L) -#define PINMUX_PA18C_SERCOM1_PAD2 ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2) -#define PORT_PA18C_SERCOM1_PAD2 ((1UL) << 18) - -#define PIN_PB22C_SERCOM1_PAD2 (54L) -#define MUX_PB22C_SERCOM1_PAD2 (2L) -#define PINMUX_PB22C_SERCOM1_PAD2 ((PIN_PB22C_SERCOM1_PAD2 << 16) | MUX_PB22C_SERCOM1_PAD2) -#define PORT_PB22C_SERCOM1_PAD2 ((1UL) << 22) - -#define PIN_PD20C_SERCOM1_PAD2 (116L) -#define MUX_PD20C_SERCOM1_PAD2 (2L) -#define PINMUX_PD20C_SERCOM1_PAD2 ((PIN_PD20C_SERCOM1_PAD2 << 16) | MUX_PD20C_SERCOM1_PAD2) -#define PORT_PD20C_SERCOM1_PAD2 ((1UL) << 20) - -#define PIN_PA31D_SERCOM1_PAD3 (31L) -#define MUX_PA31D_SERCOM1_PAD3 (3L) -#define PINMUX_PA31D_SERCOM1_PAD3 ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3) -#define PORT_PA31D_SERCOM1_PAD3 ((1UL) << 31) - -#define PIN_PA19C_SERCOM1_PAD3 (19L) -#define MUX_PA19C_SERCOM1_PAD3 (2L) -#define PINMUX_PA19C_SERCOM1_PAD3 ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3) -#define PORT_PA19C_SERCOM1_PAD3 ((1UL) << 19) - -#define PIN_PB23C_SERCOM1_PAD3 (55L) -#define MUX_PB23C_SERCOM1_PAD3 (2L) -#define PINMUX_PB23C_SERCOM1_PAD3 ((PIN_PB23C_SERCOM1_PAD3 << 16) | MUX_PB23C_SERCOM1_PAD3) -#define PORT_PB23C_SERCOM1_PAD3 ((1UL) << 23) - -#define PIN_PD21C_SERCOM1_PAD3 (117L) -#define MUX_PD21C_SERCOM1_PAD3 (2L) -#define PINMUX_PD21C_SERCOM1_PAD3 ((PIN_PD21C_SERCOM1_PAD3 << 16) | MUX_PD21C_SERCOM1_PAD3) -#define PORT_PD21C_SERCOM1_PAD3 ((1UL) << 21) - -/* ========== PORT definition for SERCOM2 peripheral ========== */ -#define PIN_PA09D_SERCOM2_PAD0 (9L) -#define MUX_PA09D_SERCOM2_PAD0 (3L) -#define PINMUX_PA09D_SERCOM2_PAD0 ((PIN_PA09D_SERCOM2_PAD0 << 16) | MUX_PA09D_SERCOM2_PAD0) -#define PORT_PA09D_SERCOM2_PAD0 ((1UL) << 9) - -#define PIN_PB25D_SERCOM2_PAD0 (57L) -#define MUX_PB25D_SERCOM2_PAD0 (3L) -#define PINMUX_PB25D_SERCOM2_PAD0 ((PIN_PB25D_SERCOM2_PAD0 << 16) | MUX_PB25D_SERCOM2_PAD0) -#define PORT_PB25D_SERCOM2_PAD0 ((1UL) << 25) - -#define PIN_PA12C_SERCOM2_PAD0 (12L) -#define MUX_PA12C_SERCOM2_PAD0 (2L) -#define PINMUX_PA12C_SERCOM2_PAD0 ((PIN_PA12C_SERCOM2_PAD0 << 16) | MUX_PA12C_SERCOM2_PAD0) -#define PORT_PA12C_SERCOM2_PAD0 ((1UL) << 12) - -#define PIN_PB26C_SERCOM2_PAD0 (58L) -#define MUX_PB26C_SERCOM2_PAD0 (2L) -#define PINMUX_PB26C_SERCOM2_PAD0 ((PIN_PB26C_SERCOM2_PAD0 << 16) | MUX_PB26C_SERCOM2_PAD0) -#define PORT_PB26C_SERCOM2_PAD0 ((1UL) << 26) - -#define PIN_PA08D_SERCOM2_PAD1 (8L) -#define MUX_PA08D_SERCOM2_PAD1 (3L) -#define PINMUX_PA08D_SERCOM2_PAD1 ((PIN_PA08D_SERCOM2_PAD1 << 16) | MUX_PA08D_SERCOM2_PAD1) -#define PORT_PA08D_SERCOM2_PAD1 ((1UL) << 8) - -#define PIN_PB24D_SERCOM2_PAD1 (56L) -#define MUX_PB24D_SERCOM2_PAD1 (3L) -#define PINMUX_PB24D_SERCOM2_PAD1 ((PIN_PB24D_SERCOM2_PAD1 << 16) | MUX_PB24D_SERCOM2_PAD1) -#define PORT_PB24D_SERCOM2_PAD1 ((1UL) << 24) - -#define PIN_PA13C_SERCOM2_PAD1 (13L) -#define MUX_PA13C_SERCOM2_PAD1 (2L) -#define PINMUX_PA13C_SERCOM2_PAD1 ((PIN_PA13C_SERCOM2_PAD1 << 16) | MUX_PA13C_SERCOM2_PAD1) -#define PORT_PA13C_SERCOM2_PAD1 ((1UL) << 13) - -#define PIN_PB27C_SERCOM2_PAD1 (59L) -#define MUX_PB27C_SERCOM2_PAD1 (2L) -#define PINMUX_PB27C_SERCOM2_PAD1 ((PIN_PB27C_SERCOM2_PAD1 << 16) | MUX_PB27C_SERCOM2_PAD1) -#define PORT_PB27C_SERCOM2_PAD1 ((1UL) << 27) - -#define PIN_PA10D_SERCOM2_PAD2 (10L) -#define MUX_PA10D_SERCOM2_PAD2 (3L) -#define PINMUX_PA10D_SERCOM2_PAD2 ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2) -#define PORT_PA10D_SERCOM2_PAD2 ((1UL) << 10) - -#define PIN_PC24D_SERCOM2_PAD2 (88L) -#define MUX_PC24D_SERCOM2_PAD2 (3L) -#define PINMUX_PC24D_SERCOM2_PAD2 ((PIN_PC24D_SERCOM2_PAD2 << 16) | MUX_PC24D_SERCOM2_PAD2) -#define PORT_PC24D_SERCOM2_PAD2 ((1UL) << 24) - -#define PIN_PB28C_SERCOM2_PAD2 (60L) -#define MUX_PB28C_SERCOM2_PAD2 (2L) -#define PINMUX_PB28C_SERCOM2_PAD2 ((PIN_PB28C_SERCOM2_PAD2 << 16) | MUX_PB28C_SERCOM2_PAD2) -#define PORT_PB28C_SERCOM2_PAD2 ((1UL) << 28) - -#define PIN_PA14C_SERCOM2_PAD2 (14L) -#define MUX_PA14C_SERCOM2_PAD2 (2L) -#define PINMUX_PA14C_SERCOM2_PAD2 ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2) -#define PORT_PA14C_SERCOM2_PAD2 ((1UL) << 14) - -#define PIN_PA11D_SERCOM2_PAD3 (11L) -#define MUX_PA11D_SERCOM2_PAD3 (3L) -#define PINMUX_PA11D_SERCOM2_PAD3 ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3) -#define PORT_PA11D_SERCOM2_PAD3 ((1UL) << 11) - -#define PIN_PC25D_SERCOM2_PAD3 (89L) -#define MUX_PC25D_SERCOM2_PAD3 (3L) -#define PINMUX_PC25D_SERCOM2_PAD3 ((PIN_PC25D_SERCOM2_PAD3 << 16) | MUX_PC25D_SERCOM2_PAD3) -#define PORT_PC25D_SERCOM2_PAD3 ((1UL) << 25) - -#define PIN_PB29C_SERCOM2_PAD3 (61L) -#define MUX_PB29C_SERCOM2_PAD3 (2L) -#define PINMUX_PB29C_SERCOM2_PAD3 ((PIN_PB29C_SERCOM2_PAD3 << 16) | MUX_PB29C_SERCOM2_PAD3) -#define PORT_PB29C_SERCOM2_PAD3 ((1UL) << 29) - -#define PIN_PA15C_SERCOM2_PAD3 (15L) -#define MUX_PA15C_SERCOM2_PAD3 (2L) -#define PINMUX_PA15C_SERCOM2_PAD3 ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3) -#define PORT_PA15C_SERCOM2_PAD3 ((1UL) << 15) - -/* ========== PORT definition for SERCOM3 peripheral ========== */ -#define PIN_PA17D_SERCOM3_PAD0 (17L) -#define MUX_PA17D_SERCOM3_PAD0 (3L) -#define PINMUX_PA17D_SERCOM3_PAD0 ((PIN_PA17D_SERCOM3_PAD0 << 16) | MUX_PA17D_SERCOM3_PAD0) -#define PORT_PA17D_SERCOM3_PAD0 ((1UL) << 17) - -#define PIN_PC23D_SERCOM3_PAD0 (87L) -#define MUX_PC23D_SERCOM3_PAD0 (3L) -#define PINMUX_PC23D_SERCOM3_PAD0 ((PIN_PC23D_SERCOM3_PAD0 << 16) | MUX_PC23D_SERCOM3_PAD0) -#define PORT_PC23D_SERCOM3_PAD0 ((1UL) << 23) - -#define PIN_PA22C_SERCOM3_PAD0 (22L) -#define MUX_PA22C_SERCOM3_PAD0 (2L) -#define PINMUX_PA22C_SERCOM3_PAD0 ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0) -#define PORT_PA22C_SERCOM3_PAD0 ((1UL) << 22) - -#define PIN_PB20C_SERCOM3_PAD0 (52L) -#define MUX_PB20C_SERCOM3_PAD0 (2L) -#define PINMUX_PB20C_SERCOM3_PAD0 ((PIN_PB20C_SERCOM3_PAD0 << 16) | MUX_PB20C_SERCOM3_PAD0) -#define PORT_PB20C_SERCOM3_PAD0 ((1UL) << 20) - -#define PIN_PA16D_SERCOM3_PAD1 (16L) -#define MUX_PA16D_SERCOM3_PAD1 (3L) -#define PINMUX_PA16D_SERCOM3_PAD1 ((PIN_PA16D_SERCOM3_PAD1 << 16) | MUX_PA16D_SERCOM3_PAD1) -#define PORT_PA16D_SERCOM3_PAD1 ((1UL) << 16) - -#define PIN_PC22D_SERCOM3_PAD1 (86L) -#define MUX_PC22D_SERCOM3_PAD1 (3L) -#define PINMUX_PC22D_SERCOM3_PAD1 ((PIN_PC22D_SERCOM3_PAD1 << 16) | MUX_PC22D_SERCOM3_PAD1) -#define PORT_PC22D_SERCOM3_PAD1 ((1UL) << 22) - -#define PIN_PA23C_SERCOM3_PAD1 (23L) -#define MUX_PA23C_SERCOM3_PAD1 (2L) -#define PINMUX_PA23C_SERCOM3_PAD1 ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1) -#define PORT_PA23C_SERCOM3_PAD1 ((1UL) << 23) - -#define PIN_PB21C_SERCOM3_PAD1 (53L) -#define MUX_PB21C_SERCOM3_PAD1 (2L) -#define PINMUX_PB21C_SERCOM3_PAD1 ((PIN_PB21C_SERCOM3_PAD1 << 16) | MUX_PB21C_SERCOM3_PAD1) -#define PORT_PB21C_SERCOM3_PAD1 ((1UL) << 21) - -#define PIN_PA18D_SERCOM3_PAD2 (18L) -#define MUX_PA18D_SERCOM3_PAD2 (3L) -#define PINMUX_PA18D_SERCOM3_PAD2 ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2) -#define PORT_PA18D_SERCOM3_PAD2 ((1UL) << 18) - -#define PIN_PA20D_SERCOM3_PAD2 (20L) -#define MUX_PA20D_SERCOM3_PAD2 (3L) -#define PINMUX_PA20D_SERCOM3_PAD2 ((PIN_PA20D_SERCOM3_PAD2 << 16) | MUX_PA20D_SERCOM3_PAD2) -#define PORT_PA20D_SERCOM3_PAD2 ((1UL) << 20) - -#define PIN_PD20D_SERCOM3_PAD2 (116L) -#define MUX_PD20D_SERCOM3_PAD2 (3L) -#define PINMUX_PD20D_SERCOM3_PAD2 ((PIN_PD20D_SERCOM3_PAD2 << 16) | MUX_PD20D_SERCOM3_PAD2) -#define PORT_PD20D_SERCOM3_PAD2 ((1UL) << 20) - -#define PIN_PA24C_SERCOM3_PAD2 (24L) -#define MUX_PA24C_SERCOM3_PAD2 (2L) -#define PINMUX_PA24C_SERCOM3_PAD2 ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2) -#define PORT_PA24C_SERCOM3_PAD2 ((1UL) << 24) - -#define PIN_PA19D_SERCOM3_PAD3 (19L) -#define MUX_PA19D_SERCOM3_PAD3 (3L) -#define PINMUX_PA19D_SERCOM3_PAD3 ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3) -#define PORT_PA19D_SERCOM3_PAD3 ((1UL) << 19) - -#define PIN_PA21D_SERCOM3_PAD3 (21L) -#define MUX_PA21D_SERCOM3_PAD3 (3L) -#define PINMUX_PA21D_SERCOM3_PAD3 ((PIN_PA21D_SERCOM3_PAD3 << 16) | MUX_PA21D_SERCOM3_PAD3) -#define PORT_PA21D_SERCOM3_PAD3 ((1UL) << 21) - -#define PIN_PD21D_SERCOM3_PAD3 (117L) -#define MUX_PD21D_SERCOM3_PAD3 (3L) -#define PINMUX_PD21D_SERCOM3_PAD3 ((PIN_PD21D_SERCOM3_PAD3 << 16) | MUX_PD21D_SERCOM3_PAD3) -#define PORT_PD21D_SERCOM3_PAD3 ((1UL) << 21) - -#define PIN_PA25C_SERCOM3_PAD3 (25L) -#define MUX_PA25C_SERCOM3_PAD3 (2L) -#define PINMUX_PA25C_SERCOM3_PAD3 ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3) -#define PORT_PA25C_SERCOM3_PAD3 ((1UL) << 25) - -/* ========== PORT definition for SERCOM4 peripheral ========== */ -#define PIN_PA13D_SERCOM4_PAD0 (13L) -#define MUX_PA13D_SERCOM4_PAD0 (3L) -#define PINMUX_PA13D_SERCOM4_PAD0 ((PIN_PA13D_SERCOM4_PAD0 << 16) | MUX_PA13D_SERCOM4_PAD0) -#define PORT_PA13D_SERCOM4_PAD0 ((1UL) << 13) - -#define PIN_PB08D_SERCOM4_PAD0 (40L) -#define MUX_PB08D_SERCOM4_PAD0 (3L) -#define PINMUX_PB08D_SERCOM4_PAD0 ((PIN_PB08D_SERCOM4_PAD0 << 16) | MUX_PB08D_SERCOM4_PAD0) -#define PORT_PB08D_SERCOM4_PAD0 ((1UL) << 8) - -#define PIN_PB27D_SERCOM4_PAD0 (59L) -#define MUX_PB27D_SERCOM4_PAD0 (3L) -#define PINMUX_PB27D_SERCOM4_PAD0 ((PIN_PB27D_SERCOM4_PAD0 << 16) | MUX_PB27D_SERCOM4_PAD0) -#define PORT_PB27D_SERCOM4_PAD0 ((1UL) << 27) - -#define PIN_PB12C_SERCOM4_PAD0 (44L) -#define MUX_PB12C_SERCOM4_PAD0 (2L) -#define PINMUX_PB12C_SERCOM4_PAD0 ((PIN_PB12C_SERCOM4_PAD0 << 16) | MUX_PB12C_SERCOM4_PAD0) -#define PORT_PB12C_SERCOM4_PAD0 ((1UL) << 12) - -#define PIN_PA12D_SERCOM4_PAD1 (12L) -#define MUX_PA12D_SERCOM4_PAD1 (3L) -#define PINMUX_PA12D_SERCOM4_PAD1 ((PIN_PA12D_SERCOM4_PAD1 << 16) | MUX_PA12D_SERCOM4_PAD1) -#define PORT_PA12D_SERCOM4_PAD1 ((1UL) << 12) - -#define PIN_PB09D_SERCOM4_PAD1 (41L) -#define MUX_PB09D_SERCOM4_PAD1 (3L) -#define PINMUX_PB09D_SERCOM4_PAD1 ((PIN_PB09D_SERCOM4_PAD1 << 16) | MUX_PB09D_SERCOM4_PAD1) -#define PORT_PB09D_SERCOM4_PAD1 ((1UL) << 9) - -#define PIN_PB26D_SERCOM4_PAD1 (58L) -#define MUX_PB26D_SERCOM4_PAD1 (3L) -#define PINMUX_PB26D_SERCOM4_PAD1 ((PIN_PB26D_SERCOM4_PAD1 << 16) | MUX_PB26D_SERCOM4_PAD1) -#define PORT_PB26D_SERCOM4_PAD1 ((1UL) << 26) - -#define PIN_PB13C_SERCOM4_PAD1 (45L) -#define MUX_PB13C_SERCOM4_PAD1 (2L) -#define PINMUX_PB13C_SERCOM4_PAD1 ((PIN_PB13C_SERCOM4_PAD1 << 16) | MUX_PB13C_SERCOM4_PAD1) -#define PORT_PB13C_SERCOM4_PAD1 ((1UL) << 13) - -#define PIN_PA14D_SERCOM4_PAD2 (14L) -#define MUX_PA14D_SERCOM4_PAD2 (3L) -#define PINMUX_PA14D_SERCOM4_PAD2 ((PIN_PA14D_SERCOM4_PAD2 << 16) | MUX_PA14D_SERCOM4_PAD2) -#define PORT_PA14D_SERCOM4_PAD2 ((1UL) << 14) - -#define PIN_PB10D_SERCOM4_PAD2 (42L) -#define MUX_PB10D_SERCOM4_PAD2 (3L) -#define PINMUX_PB10D_SERCOM4_PAD2 ((PIN_PB10D_SERCOM4_PAD2 << 16) | MUX_PB10D_SERCOM4_PAD2) -#define PORT_PB10D_SERCOM4_PAD2 ((1UL) << 10) - -#define PIN_PB28D_SERCOM4_PAD2 (60L) -#define MUX_PB28D_SERCOM4_PAD2 (3L) -#define PINMUX_PB28D_SERCOM4_PAD2 ((PIN_PB28D_SERCOM4_PAD2 << 16) | MUX_PB28D_SERCOM4_PAD2) -#define PORT_PB28D_SERCOM4_PAD2 ((1UL) << 28) - -#define PIN_PB14C_SERCOM4_PAD2 (46L) -#define MUX_PB14C_SERCOM4_PAD2 (2L) -#define PINMUX_PB14C_SERCOM4_PAD2 ((PIN_PB14C_SERCOM4_PAD2 << 16) | MUX_PB14C_SERCOM4_PAD2) -#define PORT_PB14C_SERCOM4_PAD2 ((1UL) << 14) - -#define PIN_PB11D_SERCOM4_PAD3 (43L) -#define MUX_PB11D_SERCOM4_PAD3 (3L) -#define PINMUX_PB11D_SERCOM4_PAD3 ((PIN_PB11D_SERCOM4_PAD3 << 16) | MUX_PB11D_SERCOM4_PAD3) -#define PORT_PB11D_SERCOM4_PAD3 ((1UL) << 11) - -#define PIN_PB29D_SERCOM4_PAD3 (61L) -#define MUX_PB29D_SERCOM4_PAD3 (3L) -#define PINMUX_PB29D_SERCOM4_PAD3 ((PIN_PB29D_SERCOM4_PAD3 << 16) | MUX_PB29D_SERCOM4_PAD3) -#define PORT_PB29D_SERCOM4_PAD3 ((1UL) << 29) - -#define PIN_PA15D_SERCOM4_PAD3 (15L) -#define MUX_PA15D_SERCOM4_PAD3 (3L) -#define PINMUX_PA15D_SERCOM4_PAD3 ((PIN_PA15D_SERCOM4_PAD3 << 16) | MUX_PA15D_SERCOM4_PAD3) -#define PORT_PA15D_SERCOM4_PAD3 ((1UL) << 15) - -#define PIN_PB15C_SERCOM4_PAD3 (47L) -#define MUX_PB15C_SERCOM4_PAD3 (2L) -#define PINMUX_PB15C_SERCOM4_PAD3 ((PIN_PB15C_SERCOM4_PAD3 << 16) | MUX_PB15C_SERCOM4_PAD3) -#define PORT_PB15C_SERCOM4_PAD3 ((1UL) << 15) - -/* ========== PORT definition for SERCOM5 peripheral ========== */ -#define PIN_PA23D_SERCOM5_PAD0 (23L) -#define MUX_PA23D_SERCOM5_PAD0 (3L) -#define PINMUX_PA23D_SERCOM5_PAD0 ((PIN_PA23D_SERCOM5_PAD0 << 16) | MUX_PA23D_SERCOM5_PAD0) -#define PORT_PA23D_SERCOM5_PAD0 ((1UL) << 23) - -#define PIN_PB02D_SERCOM5_PAD0 (34L) -#define MUX_PB02D_SERCOM5_PAD0 (3L) -#define PINMUX_PB02D_SERCOM5_PAD0 ((PIN_PB02D_SERCOM5_PAD0 << 16) | MUX_PB02D_SERCOM5_PAD0) -#define PORT_PB02D_SERCOM5_PAD0 ((1UL) << 2) - -#define PIN_PB31D_SERCOM5_PAD0 (63L) -#define MUX_PB31D_SERCOM5_PAD0 (3L) -#define PINMUX_PB31D_SERCOM5_PAD0 ((PIN_PB31D_SERCOM5_PAD0 << 16) | MUX_PB31D_SERCOM5_PAD0) -#define PORT_PB31D_SERCOM5_PAD0 ((1UL) << 31) - -#define PIN_PB16C_SERCOM5_PAD0 (48L) -#define MUX_PB16C_SERCOM5_PAD0 (2L) -#define PINMUX_PB16C_SERCOM5_PAD0 ((PIN_PB16C_SERCOM5_PAD0 << 16) | MUX_PB16C_SERCOM5_PAD0) -#define PORT_PB16C_SERCOM5_PAD0 ((1UL) << 16) - -#define PIN_PA22D_SERCOM5_PAD1 (22L) -#define MUX_PA22D_SERCOM5_PAD1 (3L) -#define PINMUX_PA22D_SERCOM5_PAD1 ((PIN_PA22D_SERCOM5_PAD1 << 16) | MUX_PA22D_SERCOM5_PAD1) -#define PORT_PA22D_SERCOM5_PAD1 ((1UL) << 22) - -#define PIN_PB03D_SERCOM5_PAD1 (35L) -#define MUX_PB03D_SERCOM5_PAD1 (3L) -#define PINMUX_PB03D_SERCOM5_PAD1 ((PIN_PB03D_SERCOM5_PAD1 << 16) | MUX_PB03D_SERCOM5_PAD1) -#define PORT_PB03D_SERCOM5_PAD1 ((1UL) << 3) - -#define PIN_PB30D_SERCOM5_PAD1 (62L) -#define MUX_PB30D_SERCOM5_PAD1 (3L) -#define PINMUX_PB30D_SERCOM5_PAD1 ((PIN_PB30D_SERCOM5_PAD1 << 16) | MUX_PB30D_SERCOM5_PAD1) -#define PORT_PB30D_SERCOM5_PAD1 ((1UL) << 30) - -#define PIN_PB17C_SERCOM5_PAD1 (49L) -#define MUX_PB17C_SERCOM5_PAD1 (2L) -#define PINMUX_PB17C_SERCOM5_PAD1 ((PIN_PB17C_SERCOM5_PAD1 << 16) | MUX_PB17C_SERCOM5_PAD1) -#define PORT_PB17C_SERCOM5_PAD1 ((1UL) << 17) - -#define PIN_PA24D_SERCOM5_PAD2 (24L) -#define MUX_PA24D_SERCOM5_PAD2 (3L) -#define PINMUX_PA24D_SERCOM5_PAD2 ((PIN_PA24D_SERCOM5_PAD2 << 16) | MUX_PA24D_SERCOM5_PAD2) -#define PORT_PA24D_SERCOM5_PAD2 ((1UL) << 24) - -#define PIN_PB00D_SERCOM5_PAD2 (32L) -#define MUX_PB00D_SERCOM5_PAD2 (3L) -#define PINMUX_PB00D_SERCOM5_PAD2 ((PIN_PB00D_SERCOM5_PAD2 << 16) | MUX_PB00D_SERCOM5_PAD2) -#define PORT_PB00D_SERCOM5_PAD2 ((1UL) << 0) - -#define PIN_PB22D_SERCOM5_PAD2 (54L) -#define MUX_PB22D_SERCOM5_PAD2 (3L) -#define PINMUX_PB22D_SERCOM5_PAD2 ((PIN_PB22D_SERCOM5_PAD2 << 16) | MUX_PB22D_SERCOM5_PAD2) -#define PORT_PB22D_SERCOM5_PAD2 ((1UL) << 22) - -#define PIN_PA20C_SERCOM5_PAD2 (20L) -#define MUX_PA20C_SERCOM5_PAD2 (2L) -#define PINMUX_PA20C_SERCOM5_PAD2 ((PIN_PA20C_SERCOM5_PAD2 << 16) | MUX_PA20C_SERCOM5_PAD2) -#define PORT_PA20C_SERCOM5_PAD2 ((1UL) << 20) - -#define PIN_PB18C_SERCOM5_PAD2 (50L) -#define MUX_PB18C_SERCOM5_PAD2 (2L) -#define PINMUX_PB18C_SERCOM5_PAD2 ((PIN_PB18C_SERCOM5_PAD2 << 16) | MUX_PB18C_SERCOM5_PAD2) -#define PORT_PB18C_SERCOM5_PAD2 ((1UL) << 18) - -#define PIN_PA25D_SERCOM5_PAD3 (25L) -#define MUX_PA25D_SERCOM5_PAD3 (3L) -#define PINMUX_PA25D_SERCOM5_PAD3 ((PIN_PA25D_SERCOM5_PAD3 << 16) | MUX_PA25D_SERCOM5_PAD3) -#define PORT_PA25D_SERCOM5_PAD3 ((1UL) << 25) - -#define PIN_PB01D_SERCOM5_PAD3 (33L) -#define MUX_PB01D_SERCOM5_PAD3 (3L) -#define PINMUX_PB01D_SERCOM5_PAD3 ((PIN_PB01D_SERCOM5_PAD3 << 16) | MUX_PB01D_SERCOM5_PAD3) -#define PORT_PB01D_SERCOM5_PAD3 ((1UL) << 1) - -#define PIN_PB23D_SERCOM5_PAD3 (55L) -#define MUX_PB23D_SERCOM5_PAD3 (3L) -#define PINMUX_PB23D_SERCOM5_PAD3 ((PIN_PB23D_SERCOM5_PAD3 << 16) | MUX_PB23D_SERCOM5_PAD3) -#define PORT_PB23D_SERCOM5_PAD3 ((1UL) << 23) - -#define PIN_PA21C_SERCOM5_PAD3 (21L) -#define MUX_PA21C_SERCOM5_PAD3 (2L) -#define PINMUX_PA21C_SERCOM5_PAD3 ((PIN_PA21C_SERCOM5_PAD3 << 16) | MUX_PA21C_SERCOM5_PAD3) -#define PORT_PA21C_SERCOM5_PAD3 ((1UL) << 21) - -#define PIN_PB19C_SERCOM5_PAD3 (51L) -#define MUX_PB19C_SERCOM5_PAD3 (2L) -#define PINMUX_PB19C_SERCOM5_PAD3 ((PIN_PB19C_SERCOM5_PAD3 << 16) | MUX_PB19C_SERCOM5_PAD3) -#define PORT_PB19C_SERCOM5_PAD3 ((1UL) << 19) - -/* ========== PORT definition for SERCOM6 peripheral ========== */ -#define PIN_PD09D_SERCOM6_PAD0 (105L) -#define MUX_PD09D_SERCOM6_PAD0 (3L) -#define PINMUX_PD09D_SERCOM6_PAD0 ((PIN_PD09D_SERCOM6_PAD0 << 16) | MUX_PD09D_SERCOM6_PAD0) -#define PORT_PD09D_SERCOM6_PAD0 ((1UL) << 9) - -#define PIN_PC13D_SERCOM6_PAD0 (77L) -#define MUX_PC13D_SERCOM6_PAD0 (3L) -#define PINMUX_PC13D_SERCOM6_PAD0 ((PIN_PC13D_SERCOM6_PAD0 << 16) | MUX_PC13D_SERCOM6_PAD0) -#define PORT_PC13D_SERCOM6_PAD0 ((1UL) << 13) - -#define PIN_PC04C_SERCOM6_PAD0 (68L) -#define MUX_PC04C_SERCOM6_PAD0 (2L) -#define PINMUX_PC04C_SERCOM6_PAD0 ((PIN_PC04C_SERCOM6_PAD0 << 16) | MUX_PC04C_SERCOM6_PAD0) -#define PORT_PC04C_SERCOM6_PAD0 ((1UL) << 4) - -#define PIN_PC16C_SERCOM6_PAD0 (80L) -#define MUX_PC16C_SERCOM6_PAD0 (2L) -#define PINMUX_PC16C_SERCOM6_PAD0 ((PIN_PC16C_SERCOM6_PAD0 << 16) | MUX_PC16C_SERCOM6_PAD0) -#define PORT_PC16C_SERCOM6_PAD0 ((1UL) << 16) - -#define PIN_PD08D_SERCOM6_PAD1 (104L) -#define MUX_PD08D_SERCOM6_PAD1 (3L) -#define PINMUX_PD08D_SERCOM6_PAD1 ((PIN_PD08D_SERCOM6_PAD1 << 16) | MUX_PD08D_SERCOM6_PAD1) -#define PORT_PD08D_SERCOM6_PAD1 ((1UL) << 8) - -#define PIN_PC12D_SERCOM6_PAD1 (76L) -#define MUX_PC12D_SERCOM6_PAD1 (3L) -#define PINMUX_PC12D_SERCOM6_PAD1 ((PIN_PC12D_SERCOM6_PAD1 << 16) | MUX_PC12D_SERCOM6_PAD1) -#define PORT_PC12D_SERCOM6_PAD1 ((1UL) << 12) - -#define PIN_PC05C_SERCOM6_PAD1 (69L) -#define MUX_PC05C_SERCOM6_PAD1 (2L) -#define PINMUX_PC05C_SERCOM6_PAD1 ((PIN_PC05C_SERCOM6_PAD1 << 16) | MUX_PC05C_SERCOM6_PAD1) -#define PORT_PC05C_SERCOM6_PAD1 ((1UL) << 5) - -#define PIN_PC17C_SERCOM6_PAD1 (81L) -#define MUX_PC17C_SERCOM6_PAD1 (2L) -#define PINMUX_PC17C_SERCOM6_PAD1 ((PIN_PC17C_SERCOM6_PAD1 << 16) | MUX_PC17C_SERCOM6_PAD1) -#define PORT_PC17C_SERCOM6_PAD1 ((1UL) << 17) - -#define PIN_PC14D_SERCOM6_PAD2 (78L) -#define MUX_PC14D_SERCOM6_PAD2 (3L) -#define PINMUX_PC14D_SERCOM6_PAD2 ((PIN_PC14D_SERCOM6_PAD2 << 16) | MUX_PC14D_SERCOM6_PAD2) -#define PORT_PC14D_SERCOM6_PAD2 ((1UL) << 14) - -#define PIN_PD10D_SERCOM6_PAD2 (106L) -#define MUX_PD10D_SERCOM6_PAD2 (3L) -#define PINMUX_PD10D_SERCOM6_PAD2 ((PIN_PD10D_SERCOM6_PAD2 << 16) | MUX_PD10D_SERCOM6_PAD2) -#define PORT_PD10D_SERCOM6_PAD2 ((1UL) << 10) - -#define PIN_PC06C_SERCOM6_PAD2 (70L) -#define MUX_PC06C_SERCOM6_PAD2 (2L) -#define PINMUX_PC06C_SERCOM6_PAD2 ((PIN_PC06C_SERCOM6_PAD2 << 16) | MUX_PC06C_SERCOM6_PAD2) -#define PORT_PC06C_SERCOM6_PAD2 ((1UL) << 6) - -#define PIN_PC10C_SERCOM6_PAD2 (74L) -#define MUX_PC10C_SERCOM6_PAD2 (2L) -#define PINMUX_PC10C_SERCOM6_PAD2 ((PIN_PC10C_SERCOM6_PAD2 << 16) | MUX_PC10C_SERCOM6_PAD2) -#define PORT_PC10C_SERCOM6_PAD2 ((1UL) << 10) - -#define PIN_PC18C_SERCOM6_PAD2 (82L) -#define MUX_PC18C_SERCOM6_PAD2 (2L) -#define PINMUX_PC18C_SERCOM6_PAD2 ((PIN_PC18C_SERCOM6_PAD2 << 16) | MUX_PC18C_SERCOM6_PAD2) -#define PORT_PC18C_SERCOM6_PAD2 ((1UL) << 18) - -#define PIN_PC15D_SERCOM6_PAD3 (79L) -#define MUX_PC15D_SERCOM6_PAD3 (3L) -#define PINMUX_PC15D_SERCOM6_PAD3 ((PIN_PC15D_SERCOM6_PAD3 << 16) | MUX_PC15D_SERCOM6_PAD3) -#define PORT_PC15D_SERCOM6_PAD3 ((1UL) << 15) - -#define PIN_PD11D_SERCOM6_PAD3 (107L) -#define MUX_PD11D_SERCOM6_PAD3 (3L) -#define PINMUX_PD11D_SERCOM6_PAD3 ((PIN_PD11D_SERCOM6_PAD3 << 16) | MUX_PD11D_SERCOM6_PAD3) -#define PORT_PD11D_SERCOM6_PAD3 ((1UL) << 11) - -#define PIN_PC07C_SERCOM6_PAD3 (71L) -#define MUX_PC07C_SERCOM6_PAD3 (2L) -#define PINMUX_PC07C_SERCOM6_PAD3 ((PIN_PC07C_SERCOM6_PAD3 << 16) | MUX_PC07C_SERCOM6_PAD3) -#define PORT_PC07C_SERCOM6_PAD3 ((1UL) << 7) - -#define PIN_PC11C_SERCOM6_PAD3 (75L) -#define MUX_PC11C_SERCOM6_PAD3 (2L) -#define PINMUX_PC11C_SERCOM6_PAD3 ((PIN_PC11C_SERCOM6_PAD3 << 16) | MUX_PC11C_SERCOM6_PAD3) -#define PORT_PC11C_SERCOM6_PAD3 ((1UL) << 11) - -#define PIN_PC19C_SERCOM6_PAD3 (83L) -#define MUX_PC19C_SERCOM6_PAD3 (2L) -#define PINMUX_PC19C_SERCOM6_PAD3 ((PIN_PC19C_SERCOM6_PAD3 << 16) | MUX_PC19C_SERCOM6_PAD3) -#define PORT_PC19C_SERCOM6_PAD3 ((1UL) << 19) - -/* ========== PORT definition for SERCOM7 peripheral ========== */ -#define PIN_PB21D_SERCOM7_PAD0 (53L) -#define MUX_PB21D_SERCOM7_PAD0 (3L) -#define PINMUX_PB21D_SERCOM7_PAD0 ((PIN_PB21D_SERCOM7_PAD0 << 16) | MUX_PB21D_SERCOM7_PAD0) -#define PORT_PB21D_SERCOM7_PAD0 ((1UL) << 21) - -#define PIN_PD08C_SERCOM7_PAD0 (104L) -#define MUX_PD08C_SERCOM7_PAD0 (2L) -#define PINMUX_PD08C_SERCOM7_PAD0 ((PIN_PD08C_SERCOM7_PAD0 << 16) | MUX_PD08C_SERCOM7_PAD0) -#define PORT_PD08C_SERCOM7_PAD0 ((1UL) << 8) - -#define PIN_PB30C_SERCOM7_PAD0 (62L) -#define MUX_PB30C_SERCOM7_PAD0 (2L) -#define PINMUX_PB30C_SERCOM7_PAD0 ((PIN_PB30C_SERCOM7_PAD0 << 16) | MUX_PB30C_SERCOM7_PAD0) -#define PORT_PB30C_SERCOM7_PAD0 ((1UL) << 30) - -#define PIN_PC12C_SERCOM7_PAD0 (76L) -#define MUX_PC12C_SERCOM7_PAD0 (2L) -#define PINMUX_PC12C_SERCOM7_PAD0 ((PIN_PC12C_SERCOM7_PAD0 << 16) | MUX_PC12C_SERCOM7_PAD0) -#define PORT_PC12C_SERCOM7_PAD0 ((1UL) << 12) - -#define PIN_PB20D_SERCOM7_PAD1 (52L) -#define MUX_PB20D_SERCOM7_PAD1 (3L) -#define PINMUX_PB20D_SERCOM7_PAD1 ((PIN_PB20D_SERCOM7_PAD1 << 16) | MUX_PB20D_SERCOM7_PAD1) -#define PORT_PB20D_SERCOM7_PAD1 ((1UL) << 20) - -#define PIN_PD09C_SERCOM7_PAD1 (105L) -#define MUX_PD09C_SERCOM7_PAD1 (2L) -#define PINMUX_PD09C_SERCOM7_PAD1 ((PIN_PD09C_SERCOM7_PAD1 << 16) | MUX_PD09C_SERCOM7_PAD1) -#define PORT_PD09C_SERCOM7_PAD1 ((1UL) << 9) - -#define PIN_PB31C_SERCOM7_PAD1 (63L) -#define MUX_PB31C_SERCOM7_PAD1 (2L) -#define PINMUX_PB31C_SERCOM7_PAD1 ((PIN_PB31C_SERCOM7_PAD1 << 16) | MUX_PB31C_SERCOM7_PAD1) -#define PORT_PB31C_SERCOM7_PAD1 ((1UL) << 31) - -#define PIN_PC13C_SERCOM7_PAD1 (77L) -#define MUX_PC13C_SERCOM7_PAD1 (2L) -#define PINMUX_PC13C_SERCOM7_PAD1 ((PIN_PC13C_SERCOM7_PAD1 << 16) | MUX_PC13C_SERCOM7_PAD1) -#define PORT_PC13C_SERCOM7_PAD1 ((1UL) << 13) - -#define PIN_PB18D_SERCOM7_PAD2 (50L) -#define MUX_PB18D_SERCOM7_PAD2 (3L) -#define PINMUX_PB18D_SERCOM7_PAD2 ((PIN_PB18D_SERCOM7_PAD2 << 16) | MUX_PB18D_SERCOM7_PAD2) -#define PORT_PB18D_SERCOM7_PAD2 ((1UL) << 18) - -#define PIN_PC10D_SERCOM7_PAD2 (74L) -#define MUX_PC10D_SERCOM7_PAD2 (3L) -#define PINMUX_PC10D_SERCOM7_PAD2 ((PIN_PC10D_SERCOM7_PAD2 << 16) | MUX_PC10D_SERCOM7_PAD2) -#define PORT_PC10D_SERCOM7_PAD2 ((1UL) << 10) - -#define PIN_PC14C_SERCOM7_PAD2 (78L) -#define MUX_PC14C_SERCOM7_PAD2 (2L) -#define PINMUX_PC14C_SERCOM7_PAD2 ((PIN_PC14C_SERCOM7_PAD2 << 16) | MUX_PC14C_SERCOM7_PAD2) -#define PORT_PC14C_SERCOM7_PAD2 ((1UL) << 14) - -#define PIN_PD10C_SERCOM7_PAD2 (106L) -#define MUX_PD10C_SERCOM7_PAD2 (2L) -#define PINMUX_PD10C_SERCOM7_PAD2 ((PIN_PD10C_SERCOM7_PAD2 << 16) | MUX_PD10C_SERCOM7_PAD2) -#define PORT_PD10C_SERCOM7_PAD2 ((1UL) << 10) - -#define PIN_PA30C_SERCOM7_PAD2 (30L) -#define MUX_PA30C_SERCOM7_PAD2 (2L) -#define PINMUX_PA30C_SERCOM7_PAD2 ((PIN_PA30C_SERCOM7_PAD2 << 16) | MUX_PA30C_SERCOM7_PAD2) -#define PORT_PA30C_SERCOM7_PAD2 ((1UL) << 30) - -#define PIN_PB19D_SERCOM7_PAD3 (51L) -#define MUX_PB19D_SERCOM7_PAD3 (3L) -#define PINMUX_PB19D_SERCOM7_PAD3 ((PIN_PB19D_SERCOM7_PAD3 << 16) | MUX_PB19D_SERCOM7_PAD3) -#define PORT_PB19D_SERCOM7_PAD3 ((1UL) << 19) - -#define PIN_PC11D_SERCOM7_PAD3 (75L) -#define MUX_PC11D_SERCOM7_PAD3 (3L) -#define PINMUX_PC11D_SERCOM7_PAD3 ((PIN_PC11D_SERCOM7_PAD3 << 16) | MUX_PC11D_SERCOM7_PAD3) -#define PORT_PC11D_SERCOM7_PAD3 ((1UL) << 11) - -#define PIN_PC15C_SERCOM7_PAD3 (79L) -#define MUX_PC15C_SERCOM7_PAD3 (2L) -#define PINMUX_PC15C_SERCOM7_PAD3 ((PIN_PC15C_SERCOM7_PAD3 << 16) | MUX_PC15C_SERCOM7_PAD3) -#define PORT_PC15C_SERCOM7_PAD3 ((1UL) << 15) - -#define PIN_PD11C_SERCOM7_PAD3 (107L) -#define MUX_PD11C_SERCOM7_PAD3 (2L) -#define PINMUX_PD11C_SERCOM7_PAD3 ((PIN_PD11C_SERCOM7_PAD3 << 16) | MUX_PD11C_SERCOM7_PAD3) -#define PORT_PD11C_SERCOM7_PAD3 ((1UL) << 11) - -#define PIN_PA31C_SERCOM7_PAD3 (31L) -#define MUX_PA31C_SERCOM7_PAD3 (2L) -#define PINMUX_PA31C_SERCOM7_PAD3 ((PIN_PA31C_SERCOM7_PAD3 << 16) | MUX_PA31C_SERCOM7_PAD3) -#define PORT_PA31C_SERCOM7_PAD3 ((1UL) << 31) - -/* ========== PORT definition for TC0 peripheral ========== */ -#define PIN_PA04E_TC0_WO0 (4L) -#define MUX_PA04E_TC0_WO0 (4L) -#define PINMUX_PA04E_TC0_WO0 ((PIN_PA04E_TC0_WO0 << 16) | MUX_PA04E_TC0_WO0) -#define PORT_PA04E_TC0_WO0 ((1UL) << 4) - -#define PIN_PA08E_TC0_WO0 (8L) -#define MUX_PA08E_TC0_WO0 (4L) -#define PINMUX_PA08E_TC0_WO0 ((PIN_PA08E_TC0_WO0 << 16) | MUX_PA08E_TC0_WO0) -#define PORT_PA08E_TC0_WO0 ((1UL) << 8) - -#define PIN_PB30E_TC0_WO0 (62L) -#define MUX_PB30E_TC0_WO0 (4L) -#define PINMUX_PB30E_TC0_WO0 ((PIN_PB30E_TC0_WO0 << 16) | MUX_PB30E_TC0_WO0) -#define PORT_PB30E_TC0_WO0 ((1UL) << 30) - -#define PIN_PA05E_TC0_WO1 (5L) -#define MUX_PA05E_TC0_WO1 (4L) -#define PINMUX_PA05E_TC0_WO1 ((PIN_PA05E_TC0_WO1 << 16) | MUX_PA05E_TC0_WO1) -#define PORT_PA05E_TC0_WO1 ((1UL) << 5) - -#define PIN_PA09E_TC0_WO1 (9L) -#define MUX_PA09E_TC0_WO1 (4L) -#define PINMUX_PA09E_TC0_WO1 ((PIN_PA09E_TC0_WO1 << 16) | MUX_PA09E_TC0_WO1) -#define PORT_PA09E_TC0_WO1 ((1UL) << 9) - -#define PIN_PB31E_TC0_WO1 (63L) -#define MUX_PB31E_TC0_WO1 (4L) -#define PINMUX_PB31E_TC0_WO1 ((PIN_PB31E_TC0_WO1 << 16) | MUX_PB31E_TC0_WO1) -#define PORT_PB31E_TC0_WO1 ((1UL) << 31) - -/* ========== PORT definition for TC1 peripheral ========== */ -#define PIN_PA06E_TC1_WO0 (6L) -#define MUX_PA06E_TC1_WO0 (4L) -#define PINMUX_PA06E_TC1_WO0 ((PIN_PA06E_TC1_WO0 << 16) | MUX_PA06E_TC1_WO0) -#define PORT_PA06E_TC1_WO0 ((1UL) << 6) - -#define PIN_PA10E_TC1_WO0 (10L) -#define MUX_PA10E_TC1_WO0 (4L) -#define PINMUX_PA10E_TC1_WO0 ((PIN_PA10E_TC1_WO0 << 16) | MUX_PA10E_TC1_WO0) -#define PORT_PA10E_TC1_WO0 ((1UL) << 10) - -#define PIN_PA07E_TC1_WO1 (7L) -#define MUX_PA07E_TC1_WO1 (4L) -#define PINMUX_PA07E_TC1_WO1 ((PIN_PA07E_TC1_WO1 << 16) | MUX_PA07E_TC1_WO1) -#define PORT_PA07E_TC1_WO1 ((1UL) << 7) - -#define PIN_PA11E_TC1_WO1 (11L) -#define MUX_PA11E_TC1_WO1 (4L) -#define PINMUX_PA11E_TC1_WO1 ((PIN_PA11E_TC1_WO1 << 16) | MUX_PA11E_TC1_WO1) -#define PORT_PA11E_TC1_WO1 ((1UL) << 11) - -/* ========== PORT definition for TC2 peripheral ========== */ -#define PIN_PA12E_TC2_WO0 (12L) -#define MUX_PA12E_TC2_WO0 (4L) -#define PINMUX_PA12E_TC2_WO0 ((PIN_PA12E_TC2_WO0 << 16) | MUX_PA12E_TC2_WO0) -#define PORT_PA12E_TC2_WO0 ((1UL) << 12) - -#define PIN_PA16E_TC2_WO0 (16L) -#define MUX_PA16E_TC2_WO0 (4L) -#define PINMUX_PA16E_TC2_WO0 ((PIN_PA16E_TC2_WO0 << 16) | MUX_PA16E_TC2_WO0) -#define PORT_PA16E_TC2_WO0 ((1UL) << 16) - -#define PIN_PA00E_TC2_WO0 (0L) -#define MUX_PA00E_TC2_WO0 (4L) -#define PINMUX_PA00E_TC2_WO0 ((PIN_PA00E_TC2_WO0 << 16) | MUX_PA00E_TC2_WO0) -#define PORT_PA00E_TC2_WO0 ((1UL) << 0) - -#define PIN_PA01E_TC2_WO1 (1L) -#define MUX_PA01E_TC2_WO1 (4L) -#define PINMUX_PA01E_TC2_WO1 ((PIN_PA01E_TC2_WO1 << 16) | MUX_PA01E_TC2_WO1) -#define PORT_PA01E_TC2_WO1 ((1UL) << 1) - -#define PIN_PA13E_TC2_WO1 (13L) -#define MUX_PA13E_TC2_WO1 (4L) -#define PINMUX_PA13E_TC2_WO1 ((PIN_PA13E_TC2_WO1 << 16) | MUX_PA13E_TC2_WO1) -#define PORT_PA13E_TC2_WO1 ((1UL) << 13) - -#define PIN_PA17E_TC2_WO1 (17L) -#define MUX_PA17E_TC2_WO1 (4L) -#define PINMUX_PA17E_TC2_WO1 ((PIN_PA17E_TC2_WO1 << 16) | MUX_PA17E_TC2_WO1) -#define PORT_PA17E_TC2_WO1 ((1UL) << 17) - -/* ========== PORT definition for TC3 peripheral ========== */ -#define PIN_PA18E_TC3_WO0 (18L) -#define MUX_PA18E_TC3_WO0 (4L) -#define PINMUX_PA18E_TC3_WO0 ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0) -#define PORT_PA18E_TC3_WO0 ((1UL) << 18) - -#define PIN_PA14E_TC3_WO0 (14L) -#define MUX_PA14E_TC3_WO0 (4L) -#define PINMUX_PA14E_TC3_WO0 ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0) -#define PORT_PA14E_TC3_WO0 ((1UL) << 14) - -#define PIN_PA15E_TC3_WO1 (15L) -#define MUX_PA15E_TC3_WO1 (4L) -#define PINMUX_PA15E_TC3_WO1 ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1) -#define PORT_PA15E_TC3_WO1 ((1UL) << 15) - -#define PIN_PA19E_TC3_WO1 (19L) -#define MUX_PA19E_TC3_WO1 (4L) -#define PINMUX_PA19E_TC3_WO1 ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1) -#define PORT_PA19E_TC3_WO1 ((1UL) << 19) - -/* ========== PORT definition for TC4 peripheral ========== */ -#define PIN_PA22E_TC4_WO0 (22L) -#define MUX_PA22E_TC4_WO0 (4L) -#define PINMUX_PA22E_TC4_WO0 ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0) -#define PORT_PA22E_TC4_WO0 ((1UL) << 22) - -#define PIN_PB08E_TC4_WO0 (40L) -#define MUX_PB08E_TC4_WO0 (4L) -#define PINMUX_PB08E_TC4_WO0 ((PIN_PB08E_TC4_WO0 << 16) | MUX_PB08E_TC4_WO0) -#define PORT_PB08E_TC4_WO0 ((1UL) << 8) - -#define PIN_PB12E_TC4_WO0 (44L) -#define MUX_PB12E_TC4_WO0 (4L) -#define PINMUX_PB12E_TC4_WO0 ((PIN_PB12E_TC4_WO0 << 16) | MUX_PB12E_TC4_WO0) -#define PORT_PB12E_TC4_WO0 ((1UL) << 12) - -#define PIN_PA23E_TC4_WO1 (23L) -#define MUX_PA23E_TC4_WO1 (4L) -#define PINMUX_PA23E_TC4_WO1 ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1) -#define PORT_PA23E_TC4_WO1 ((1UL) << 23) - -#define PIN_PB09E_TC4_WO1 (41L) -#define MUX_PB09E_TC4_WO1 (4L) -#define PINMUX_PB09E_TC4_WO1 ((PIN_PB09E_TC4_WO1 << 16) | MUX_PB09E_TC4_WO1) -#define PORT_PB09E_TC4_WO1 ((1UL) << 9) - -#define PIN_PB13E_TC4_WO1 (45L) -#define MUX_PB13E_TC4_WO1 (4L) -#define PINMUX_PB13E_TC4_WO1 ((PIN_PB13E_TC4_WO1 << 16) | MUX_PB13E_TC4_WO1) -#define PORT_PB13E_TC4_WO1 ((1UL) << 13) - -/* ========== PORT definition for TC5 peripheral ========== */ -#define PIN_PA24E_TC5_WO0 (24L) -#define MUX_PA24E_TC5_WO0 (4L) -#define PINMUX_PA24E_TC5_WO0 ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0) -#define PORT_PA24E_TC5_WO0 ((1UL) << 24) - -#define PIN_PB10E_TC5_WO0 (42L) -#define MUX_PB10E_TC5_WO0 (4L) -#define PINMUX_PB10E_TC5_WO0 ((PIN_PB10E_TC5_WO0 << 16) | MUX_PB10E_TC5_WO0) -#define PORT_PB10E_TC5_WO0 ((1UL) << 10) - -#define PIN_PB14E_TC5_WO0 (46L) -#define MUX_PB14E_TC5_WO0 (4L) -#define PINMUX_PB14E_TC5_WO0 ((PIN_PB14E_TC5_WO0 << 16) | MUX_PB14E_TC5_WO0) -#define PORT_PB14E_TC5_WO0 ((1UL) << 14) - -#define PIN_PA25E_TC5_WO1 (25L) -#define MUX_PA25E_TC5_WO1 (4L) -#define PINMUX_PA25E_TC5_WO1 ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1) -#define PORT_PA25E_TC5_WO1 ((1UL) << 25) - -#define PIN_PB11E_TC5_WO1 (43L) -#define MUX_PB11E_TC5_WO1 (4L) -#define PINMUX_PB11E_TC5_WO1 ((PIN_PB11E_TC5_WO1 << 16) | MUX_PB11E_TC5_WO1) -#define PORT_PB11E_TC5_WO1 ((1UL) << 11) - -#define PIN_PB15E_TC5_WO1 (47L) -#define MUX_PB15E_TC5_WO1 (4L) -#define PINMUX_PB15E_TC5_WO1 ((PIN_PB15E_TC5_WO1 << 16) | MUX_PB15E_TC5_WO1) -#define PORT_PB15E_TC5_WO1 ((1UL) << 15) - -/* ========== PORT definition for TC6 peripheral ========== */ -#define PIN_PA30E_TC6_WO0 (30L) -#define MUX_PA30E_TC6_WO0 (4L) -#define PINMUX_PA30E_TC6_WO0 ((PIN_PA30E_TC6_WO0 << 16) | MUX_PA30E_TC6_WO0) -#define PORT_PA30E_TC6_WO0 ((1UL) << 30) - -#define PIN_PB02E_TC6_WO0 (34L) -#define MUX_PB02E_TC6_WO0 (4L) -#define PINMUX_PB02E_TC6_WO0 ((PIN_PB02E_TC6_WO0 << 16) | MUX_PB02E_TC6_WO0) -#define PORT_PB02E_TC6_WO0 ((1UL) << 2) - -#define PIN_PB16E_TC6_WO0 (48L) -#define MUX_PB16E_TC6_WO0 (4L) -#define PINMUX_PB16E_TC6_WO0 ((PIN_PB16E_TC6_WO0 << 16) | MUX_PB16E_TC6_WO0) -#define PORT_PB16E_TC6_WO0 ((1UL) << 16) - -#define PIN_PA31E_TC6_WO1 (31L) -#define MUX_PA31E_TC6_WO1 (4L) -#define PINMUX_PA31E_TC6_WO1 ((PIN_PA31E_TC6_WO1 << 16) | MUX_PA31E_TC6_WO1) -#define PORT_PA31E_TC6_WO1 ((1UL) << 31) - -#define PIN_PB03E_TC6_WO1 (35L) -#define MUX_PB03E_TC6_WO1 (4L) -#define PINMUX_PB03E_TC6_WO1 ((PIN_PB03E_TC6_WO1 << 16) | MUX_PB03E_TC6_WO1) -#define PORT_PB03E_TC6_WO1 ((1UL) << 3) - -#define PIN_PB17E_TC6_WO1 (49L) -#define MUX_PB17E_TC6_WO1 (4L) -#define PINMUX_PB17E_TC6_WO1 ((PIN_PB17E_TC6_WO1 << 16) | MUX_PB17E_TC6_WO1) -#define PORT_PB17E_TC6_WO1 ((1UL) << 17) - -/* ========== PORT definition for TC7 peripheral ========== */ -#define PIN_PA20E_TC7_WO0 (20L) -#define MUX_PA20E_TC7_WO0 (4L) -#define PINMUX_PA20E_TC7_WO0 ((PIN_PA20E_TC7_WO0 << 16) | MUX_PA20E_TC7_WO0) -#define PORT_PA20E_TC7_WO0 ((1UL) << 20) - -#define PIN_PB00E_TC7_WO0 (32L) -#define MUX_PB00E_TC7_WO0 (4L) -#define PINMUX_PB00E_TC7_WO0 ((PIN_PB00E_TC7_WO0 << 16) | MUX_PB00E_TC7_WO0) -#define PORT_PB00E_TC7_WO0 ((1UL) << 0) - -#define PIN_PB22E_TC7_WO0 (54L) -#define MUX_PB22E_TC7_WO0 (4L) -#define PINMUX_PB22E_TC7_WO0 ((PIN_PB22E_TC7_WO0 << 16) | MUX_PB22E_TC7_WO0) -#define PORT_PB22E_TC7_WO0 ((1UL) << 22) - -#define PIN_PA21E_TC7_WO1 (21L) -#define MUX_PA21E_TC7_WO1 (4L) -#define PINMUX_PA21E_TC7_WO1 ((PIN_PA21E_TC7_WO1 << 16) | MUX_PA21E_TC7_WO1) -#define PORT_PA21E_TC7_WO1 ((1UL) << 21) - -#define PIN_PB01E_TC7_WO1 (33L) -#define MUX_PB01E_TC7_WO1 (4L) -#define PINMUX_PB01E_TC7_WO1 ((PIN_PB01E_TC7_WO1 << 16) | MUX_PB01E_TC7_WO1) -#define PORT_PB01E_TC7_WO1 ((1UL) << 1) - -#define PIN_PB23E_TC7_WO1 (55L) -#define MUX_PB23E_TC7_WO1 (4L) -#define PINMUX_PB23E_TC7_WO1 ((PIN_PB23E_TC7_WO1 << 16) | MUX_PB23E_TC7_WO1) -#define PORT_PB23E_TC7_WO1 ((1UL) << 23) - -/* ========== PORT definition for TCC0 peripheral ========== */ -#define PIN_PA20G_TCC0_WO0 (20L) -#define MUX_PA20G_TCC0_WO0 (6L) -#define PINMUX_PA20G_TCC0_WO0 ((PIN_PA20G_TCC0_WO0 << 16) | MUX_PA20G_TCC0_WO0) -#define PORT_PA20G_TCC0_WO0 ((1UL) << 20) - -#define PIN_PB12G_TCC0_WO0 (44L) -#define MUX_PB12G_TCC0_WO0 (6L) -#define PINMUX_PB12G_TCC0_WO0 ((PIN_PB12G_TCC0_WO0 << 16) | MUX_PB12G_TCC0_WO0) -#define PORT_PB12G_TCC0_WO0 ((1UL) << 12) - -#define PIN_PA08F_TCC0_WO0 (8L) -#define MUX_PA08F_TCC0_WO0 (5L) -#define PINMUX_PA08F_TCC0_WO0 ((PIN_PA08F_TCC0_WO0 << 16) | MUX_PA08F_TCC0_WO0) -#define PORT_PA08F_TCC0_WO0 ((1UL) << 8) - -#define PIN_PC04F_TCC0_WO0 (68L) -#define MUX_PC04F_TCC0_WO0 (5L) -#define PINMUX_PC04F_TCC0_WO0 ((PIN_PC04F_TCC0_WO0 << 16) | MUX_PC04F_TCC0_WO0) -#define PORT_PC04F_TCC0_WO0 ((1UL) << 4) - -#define PIN_PC10F_TCC0_WO0 (74L) -#define MUX_PC10F_TCC0_WO0 (5L) -#define PINMUX_PC10F_TCC0_WO0 ((PIN_PC10F_TCC0_WO0 << 16) | MUX_PC10F_TCC0_WO0) -#define PORT_PC10F_TCC0_WO0 ((1UL) << 10) - -#define PIN_PC16F_TCC0_WO0 (80L) -#define MUX_PC16F_TCC0_WO0 (5L) -#define PINMUX_PC16F_TCC0_WO0 ((PIN_PC16F_TCC0_WO0 << 16) | MUX_PC16F_TCC0_WO0) -#define PORT_PC16F_TCC0_WO0 ((1UL) << 16) - -#define PIN_PA21G_TCC0_WO1 (21L) -#define MUX_PA21G_TCC0_WO1 (6L) -#define PINMUX_PA21G_TCC0_WO1 ((PIN_PA21G_TCC0_WO1 << 16) | MUX_PA21G_TCC0_WO1) -#define PORT_PA21G_TCC0_WO1 ((1UL) << 21) - -#define PIN_PB13G_TCC0_WO1 (45L) -#define MUX_PB13G_TCC0_WO1 (6L) -#define PINMUX_PB13G_TCC0_WO1 ((PIN_PB13G_TCC0_WO1 << 16) | MUX_PB13G_TCC0_WO1) -#define PORT_PB13G_TCC0_WO1 ((1UL) << 13) - -#define PIN_PA09F_TCC0_WO1 (9L) -#define MUX_PA09F_TCC0_WO1 (5L) -#define PINMUX_PA09F_TCC0_WO1 ((PIN_PA09F_TCC0_WO1 << 16) | MUX_PA09F_TCC0_WO1) -#define PORT_PA09F_TCC0_WO1 ((1UL) << 9) - -#define PIN_PC11F_TCC0_WO1 (75L) -#define MUX_PC11F_TCC0_WO1 (5L) -#define PINMUX_PC11F_TCC0_WO1 ((PIN_PC11F_TCC0_WO1 << 16) | MUX_PC11F_TCC0_WO1) -#define PORT_PC11F_TCC0_WO1 ((1UL) << 11) - -#define PIN_PC17F_TCC0_WO1 (81L) -#define MUX_PC17F_TCC0_WO1 (5L) -#define PINMUX_PC17F_TCC0_WO1 ((PIN_PC17F_TCC0_WO1 << 16) | MUX_PC17F_TCC0_WO1) -#define PORT_PC17F_TCC0_WO1 ((1UL) << 17) - -#define PIN_PD08F_TCC0_WO1 (104L) -#define MUX_PD08F_TCC0_WO1 (5L) -#define PINMUX_PD08F_TCC0_WO1 ((PIN_PD08F_TCC0_WO1 << 16) | MUX_PD08F_TCC0_WO1) -#define PORT_PD08F_TCC0_WO1 ((1UL) << 8) - -#define PIN_PA22G_TCC0_WO2 (22L) -#define MUX_PA22G_TCC0_WO2 (6L) -#define PINMUX_PA22G_TCC0_WO2 ((PIN_PA22G_TCC0_WO2 << 16) | MUX_PA22G_TCC0_WO2) -#define PORT_PA22G_TCC0_WO2 ((1UL) << 22) - -#define PIN_PB14G_TCC0_WO2 (46L) -#define MUX_PB14G_TCC0_WO2 (6L) -#define PINMUX_PB14G_TCC0_WO2 ((PIN_PB14G_TCC0_WO2 << 16) | MUX_PB14G_TCC0_WO2) -#define PORT_PB14G_TCC0_WO2 ((1UL) << 14) - -#define PIN_PA10F_TCC0_WO2 (10L) -#define MUX_PA10F_TCC0_WO2 (5L) -#define PINMUX_PA10F_TCC0_WO2 ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2) -#define PORT_PA10F_TCC0_WO2 ((1UL) << 10) - -#define PIN_PC12F_TCC0_WO2 (76L) -#define MUX_PC12F_TCC0_WO2 (5L) -#define PINMUX_PC12F_TCC0_WO2 ((PIN_PC12F_TCC0_WO2 << 16) | MUX_PC12F_TCC0_WO2) -#define PORT_PC12F_TCC0_WO2 ((1UL) << 12) - -#define PIN_PC18F_TCC0_WO2 (82L) -#define MUX_PC18F_TCC0_WO2 (5L) -#define PINMUX_PC18F_TCC0_WO2 ((PIN_PC18F_TCC0_WO2 << 16) | MUX_PC18F_TCC0_WO2) -#define PORT_PC18F_TCC0_WO2 ((1UL) << 18) - -#define PIN_PD09F_TCC0_WO2 (105L) -#define MUX_PD09F_TCC0_WO2 (5L) -#define PINMUX_PD09F_TCC0_WO2 ((PIN_PD09F_TCC0_WO2 << 16) | MUX_PD09F_TCC0_WO2) -#define PORT_PD09F_TCC0_WO2 ((1UL) << 9) - -#define PIN_PA23G_TCC0_WO3 (23L) -#define MUX_PA23G_TCC0_WO3 (6L) -#define PINMUX_PA23G_TCC0_WO3 ((PIN_PA23G_TCC0_WO3 << 16) | MUX_PA23G_TCC0_WO3) -#define PORT_PA23G_TCC0_WO3 ((1UL) << 23) - -#define PIN_PB15G_TCC0_WO3 (47L) -#define MUX_PB15G_TCC0_WO3 (6L) -#define PINMUX_PB15G_TCC0_WO3 ((PIN_PB15G_TCC0_WO3 << 16) | MUX_PB15G_TCC0_WO3) -#define PORT_PB15G_TCC0_WO3 ((1UL) << 15) - -#define PIN_PA11F_TCC0_WO3 (11L) -#define MUX_PA11F_TCC0_WO3 (5L) -#define PINMUX_PA11F_TCC0_WO3 ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3) -#define PORT_PA11F_TCC0_WO3 ((1UL) << 11) - -#define PIN_PC13F_TCC0_WO3 (77L) -#define MUX_PC13F_TCC0_WO3 (5L) -#define PINMUX_PC13F_TCC0_WO3 ((PIN_PC13F_TCC0_WO3 << 16) | MUX_PC13F_TCC0_WO3) -#define PORT_PC13F_TCC0_WO3 ((1UL) << 13) - -#define PIN_PC19F_TCC0_WO3 (83L) -#define MUX_PC19F_TCC0_WO3 (5L) -#define PINMUX_PC19F_TCC0_WO3 ((PIN_PC19F_TCC0_WO3 << 16) | MUX_PC19F_TCC0_WO3) -#define PORT_PC19F_TCC0_WO3 ((1UL) << 19) - -#define PIN_PD10F_TCC0_WO3 (106L) -#define MUX_PD10F_TCC0_WO3 (5L) -#define PINMUX_PD10F_TCC0_WO3 ((PIN_PD10F_TCC0_WO3 << 16) | MUX_PD10F_TCC0_WO3) -#define PORT_PD10F_TCC0_WO3 ((1UL) << 10) - -#define PIN_PA16G_TCC0_WO4 (16L) -#define MUX_PA16G_TCC0_WO4 (6L) -#define PINMUX_PA16G_TCC0_WO4 ((PIN_PA16G_TCC0_WO4 << 16) | MUX_PA16G_TCC0_WO4) -#define PORT_PA16G_TCC0_WO4 ((1UL) << 16) - -#define PIN_PB16G_TCC0_WO4 (48L) -#define MUX_PB16G_TCC0_WO4 (6L) -#define PINMUX_PB16G_TCC0_WO4 ((PIN_PB16G_TCC0_WO4 << 16) | MUX_PB16G_TCC0_WO4) -#define PORT_PB16G_TCC0_WO4 ((1UL) << 16) - -#define PIN_PB10F_TCC0_WO4 (42L) -#define MUX_PB10F_TCC0_WO4 (5L) -#define PINMUX_PB10F_TCC0_WO4 ((PIN_PB10F_TCC0_WO4 << 16) | MUX_PB10F_TCC0_WO4) -#define PORT_PB10F_TCC0_WO4 ((1UL) << 10) - -#define PIN_PC14F_TCC0_WO4 (78L) -#define MUX_PC14F_TCC0_WO4 (5L) -#define PINMUX_PC14F_TCC0_WO4 ((PIN_PC14F_TCC0_WO4 << 16) | MUX_PC14F_TCC0_WO4) -#define PORT_PC14F_TCC0_WO4 ((1UL) << 14) - -#define PIN_PC20F_TCC0_WO4 (84L) -#define MUX_PC20F_TCC0_WO4 (5L) -#define PINMUX_PC20F_TCC0_WO4 ((PIN_PC20F_TCC0_WO4 << 16) | MUX_PC20F_TCC0_WO4) -#define PORT_PC20F_TCC0_WO4 ((1UL) << 20) - -#define PIN_PD11F_TCC0_WO4 (107L) -#define MUX_PD11F_TCC0_WO4 (5L) -#define PINMUX_PD11F_TCC0_WO4 ((PIN_PD11F_TCC0_WO4 << 16) | MUX_PD11F_TCC0_WO4) -#define PORT_PD11F_TCC0_WO4 ((1UL) << 11) - -#define PIN_PA17G_TCC0_WO5 (17L) -#define MUX_PA17G_TCC0_WO5 (6L) -#define PINMUX_PA17G_TCC0_WO5 ((PIN_PA17G_TCC0_WO5 << 16) | MUX_PA17G_TCC0_WO5) -#define PORT_PA17G_TCC0_WO5 ((1UL) << 17) - -#define PIN_PB17G_TCC0_WO5 (49L) -#define MUX_PB17G_TCC0_WO5 (6L) -#define PINMUX_PB17G_TCC0_WO5 ((PIN_PB17G_TCC0_WO5 << 16) | MUX_PB17G_TCC0_WO5) -#define PORT_PB17G_TCC0_WO5 ((1UL) << 17) - -#define PIN_PB11F_TCC0_WO5 (43L) -#define MUX_PB11F_TCC0_WO5 (5L) -#define PINMUX_PB11F_TCC0_WO5 ((PIN_PB11F_TCC0_WO5 << 16) | MUX_PB11F_TCC0_WO5) -#define PORT_PB11F_TCC0_WO5 ((1UL) << 11) - -#define PIN_PC15F_TCC0_WO5 (79L) -#define MUX_PC15F_TCC0_WO5 (5L) -#define PINMUX_PC15F_TCC0_WO5 ((PIN_PC15F_TCC0_WO5 << 16) | MUX_PC15F_TCC0_WO5) -#define PORT_PC15F_TCC0_WO5 ((1UL) << 15) - -#define PIN_PC21F_TCC0_WO5 (85L) -#define MUX_PC21F_TCC0_WO5 (5L) -#define PINMUX_PC21F_TCC0_WO5 ((PIN_PC21F_TCC0_WO5 << 16) | MUX_PC21F_TCC0_WO5) -#define PORT_PC21F_TCC0_WO5 ((1UL) << 21) - -#define PIN_PD12F_TCC0_WO5 (108L) -#define MUX_PD12F_TCC0_WO5 (5L) -#define PINMUX_PD12F_TCC0_WO5 ((PIN_PD12F_TCC0_WO5 << 16) | MUX_PD12F_TCC0_WO5) -#define PORT_PD12F_TCC0_WO5 ((1UL) << 12) - -#define PIN_PA18G_TCC0_WO6 (18L) -#define MUX_PA18G_TCC0_WO6 (6L) -#define PINMUX_PA18G_TCC0_WO6 ((PIN_PA18G_TCC0_WO6 << 16) | MUX_PA18G_TCC0_WO6) -#define PORT_PA18G_TCC0_WO6 ((1UL) << 18) - -#define PIN_PB30G_TCC0_WO6 (62L) -#define MUX_PB30G_TCC0_WO6 (6L) -#define PINMUX_PB30G_TCC0_WO6 ((PIN_PB30G_TCC0_WO6 << 16) | MUX_PB30G_TCC0_WO6) -#define PORT_PB30G_TCC0_WO6 ((1UL) << 30) - -#define PIN_PA12F_TCC0_WO6 (12L) -#define MUX_PA12F_TCC0_WO6 (5L) -#define PINMUX_PA12F_TCC0_WO6 ((PIN_PA12F_TCC0_WO6 << 16) | MUX_PA12F_TCC0_WO6) -#define PORT_PA12F_TCC0_WO6 ((1UL) << 12) - -#define PIN_PC22F_TCC0_WO6 (86L) -#define MUX_PC22F_TCC0_WO6 (5L) -#define PINMUX_PC22F_TCC0_WO6 ((PIN_PC22F_TCC0_WO6 << 16) | MUX_PC22F_TCC0_WO6) -#define PORT_PC22F_TCC0_WO6 ((1UL) << 22) - -#define PIN_PA19G_TCC0_WO7 (19L) -#define MUX_PA19G_TCC0_WO7 (6L) -#define PINMUX_PA19G_TCC0_WO7 ((PIN_PA19G_TCC0_WO7 << 16) | MUX_PA19G_TCC0_WO7) -#define PORT_PA19G_TCC0_WO7 ((1UL) << 19) - -#define PIN_PB31G_TCC0_WO7 (63L) -#define MUX_PB31G_TCC0_WO7 (6L) -#define PINMUX_PB31G_TCC0_WO7 ((PIN_PB31G_TCC0_WO7 << 16) | MUX_PB31G_TCC0_WO7) -#define PORT_PB31G_TCC0_WO7 ((1UL) << 31) - -#define PIN_PA13F_TCC0_WO7 (13L) -#define MUX_PA13F_TCC0_WO7 (5L) -#define PINMUX_PA13F_TCC0_WO7 ((PIN_PA13F_TCC0_WO7 << 16) | MUX_PA13F_TCC0_WO7) -#define PORT_PA13F_TCC0_WO7 ((1UL) << 13) - -#define PIN_PC23F_TCC0_WO7 (87L) -#define MUX_PC23F_TCC0_WO7 (5L) -#define PINMUX_PC23F_TCC0_WO7 ((PIN_PC23F_TCC0_WO7 << 16) | MUX_PC23F_TCC0_WO7) -#define PORT_PC23F_TCC0_WO7 ((1UL) << 23) - -/* ========== PORT definition for TCC1 peripheral ========== */ -#define PIN_PB10G_TCC1_WO0 (42L) -#define MUX_PB10G_TCC1_WO0 (6L) -#define PINMUX_PB10G_TCC1_WO0 ((PIN_PB10G_TCC1_WO0 << 16) | MUX_PB10G_TCC1_WO0) -#define PORT_PB10G_TCC1_WO0 ((1UL) << 10) - -#define PIN_PC14G_TCC1_WO0 (78L) -#define MUX_PC14G_TCC1_WO0 (6L) -#define PINMUX_PC14G_TCC1_WO0 ((PIN_PC14G_TCC1_WO0 << 16) | MUX_PC14G_TCC1_WO0) -#define PORT_PC14G_TCC1_WO0 ((1UL) << 14) - -#define PIN_PA16F_TCC1_WO0 (16L) -#define MUX_PA16F_TCC1_WO0 (5L) -#define PINMUX_PA16F_TCC1_WO0 ((PIN_PA16F_TCC1_WO0 << 16) | MUX_PA16F_TCC1_WO0) -#define PORT_PA16F_TCC1_WO0 ((1UL) << 16) - -#define PIN_PB18F_TCC1_WO0 (50L) -#define MUX_PB18F_TCC1_WO0 (5L) -#define PINMUX_PB18F_TCC1_WO0 ((PIN_PB18F_TCC1_WO0 << 16) | MUX_PB18F_TCC1_WO0) -#define PORT_PB18F_TCC1_WO0 ((1UL) << 18) - -#define PIN_PD20F_TCC1_WO0 (116L) -#define MUX_PD20F_TCC1_WO0 (5L) -#define PINMUX_PD20F_TCC1_WO0 ((PIN_PD20F_TCC1_WO0 << 16) | MUX_PD20F_TCC1_WO0) -#define PORT_PD20F_TCC1_WO0 ((1UL) << 20) - -#define PIN_PB11G_TCC1_WO1 (43L) -#define MUX_PB11G_TCC1_WO1 (6L) -#define PINMUX_PB11G_TCC1_WO1 ((PIN_PB11G_TCC1_WO1 << 16) | MUX_PB11G_TCC1_WO1) -#define PORT_PB11G_TCC1_WO1 ((1UL) << 11) - -#define PIN_PC15G_TCC1_WO1 (79L) -#define MUX_PC15G_TCC1_WO1 (6L) -#define PINMUX_PC15G_TCC1_WO1 ((PIN_PC15G_TCC1_WO1 << 16) | MUX_PC15G_TCC1_WO1) -#define PORT_PC15G_TCC1_WO1 ((1UL) << 15) - -#define PIN_PA17F_TCC1_WO1 (17L) -#define MUX_PA17F_TCC1_WO1 (5L) -#define PINMUX_PA17F_TCC1_WO1 ((PIN_PA17F_TCC1_WO1 << 16) | MUX_PA17F_TCC1_WO1) -#define PORT_PA17F_TCC1_WO1 ((1UL) << 17) - -#define PIN_PB19F_TCC1_WO1 (51L) -#define MUX_PB19F_TCC1_WO1 (5L) -#define PINMUX_PB19F_TCC1_WO1 ((PIN_PB19F_TCC1_WO1 << 16) | MUX_PB19F_TCC1_WO1) -#define PORT_PB19F_TCC1_WO1 ((1UL) << 19) - -#define PIN_PD21F_TCC1_WO1 (117L) -#define MUX_PD21F_TCC1_WO1 (5L) -#define PINMUX_PD21F_TCC1_WO1 ((PIN_PD21F_TCC1_WO1 << 16) | MUX_PD21F_TCC1_WO1) -#define PORT_PD21F_TCC1_WO1 ((1UL) << 21) - -#define PIN_PA12G_TCC1_WO2 (12L) -#define MUX_PA12G_TCC1_WO2 (6L) -#define PINMUX_PA12G_TCC1_WO2 ((PIN_PA12G_TCC1_WO2 << 16) | MUX_PA12G_TCC1_WO2) -#define PORT_PA12G_TCC1_WO2 ((1UL) << 12) - -#define PIN_PA14G_TCC1_WO2 (14L) -#define MUX_PA14G_TCC1_WO2 (6L) -#define PINMUX_PA14G_TCC1_WO2 ((PIN_PA14G_TCC1_WO2 << 16) | MUX_PA14G_TCC1_WO2) -#define PORT_PA14G_TCC1_WO2 ((1UL) << 14) - -#define PIN_PA18F_TCC1_WO2 (18L) -#define MUX_PA18F_TCC1_WO2 (5L) -#define PINMUX_PA18F_TCC1_WO2 ((PIN_PA18F_TCC1_WO2 << 16) | MUX_PA18F_TCC1_WO2) -#define PORT_PA18F_TCC1_WO2 ((1UL) << 18) - -#define PIN_PB20F_TCC1_WO2 (52L) -#define MUX_PB20F_TCC1_WO2 (5L) -#define PINMUX_PB20F_TCC1_WO2 ((PIN_PB20F_TCC1_WO2 << 16) | MUX_PB20F_TCC1_WO2) -#define PORT_PB20F_TCC1_WO2 ((1UL) << 20) - -#define PIN_PB26F_TCC1_WO2 (58L) -#define MUX_PB26F_TCC1_WO2 (5L) -#define PINMUX_PB26F_TCC1_WO2 ((PIN_PB26F_TCC1_WO2 << 16) | MUX_PB26F_TCC1_WO2) -#define PORT_PB26F_TCC1_WO2 ((1UL) << 26) - -#define PIN_PA13G_TCC1_WO3 (13L) -#define MUX_PA13G_TCC1_WO3 (6L) -#define PINMUX_PA13G_TCC1_WO3 ((PIN_PA13G_TCC1_WO3 << 16) | MUX_PA13G_TCC1_WO3) -#define PORT_PA13G_TCC1_WO3 ((1UL) << 13) - -#define PIN_PA15G_TCC1_WO3 (15L) -#define MUX_PA15G_TCC1_WO3 (6L) -#define PINMUX_PA15G_TCC1_WO3 ((PIN_PA15G_TCC1_WO3 << 16) | MUX_PA15G_TCC1_WO3) -#define PORT_PA15G_TCC1_WO3 ((1UL) << 15) - -#define PIN_PA19F_TCC1_WO3 (19L) -#define MUX_PA19F_TCC1_WO3 (5L) -#define PINMUX_PA19F_TCC1_WO3 ((PIN_PA19F_TCC1_WO3 << 16) | MUX_PA19F_TCC1_WO3) -#define PORT_PA19F_TCC1_WO3 ((1UL) << 19) - -#define PIN_PB21F_TCC1_WO3 (53L) -#define MUX_PB21F_TCC1_WO3 (5L) -#define PINMUX_PB21F_TCC1_WO3 ((PIN_PB21F_TCC1_WO3 << 16) | MUX_PB21F_TCC1_WO3) -#define PORT_PB21F_TCC1_WO3 ((1UL) << 21) - -#define PIN_PB27F_TCC1_WO3 (59L) -#define MUX_PB27F_TCC1_WO3 (5L) -#define PINMUX_PB27F_TCC1_WO3 ((PIN_PB27F_TCC1_WO3 << 16) | MUX_PB27F_TCC1_WO3) -#define PORT_PB27F_TCC1_WO3 ((1UL) << 27) - -#define PIN_PA08G_TCC1_WO4 (8L) -#define MUX_PA08G_TCC1_WO4 (6L) -#define PINMUX_PA08G_TCC1_WO4 ((PIN_PA08G_TCC1_WO4 << 16) | MUX_PA08G_TCC1_WO4) -#define PORT_PA08G_TCC1_WO4 ((1UL) << 8) - -#define PIN_PC10G_TCC1_WO4 (74L) -#define MUX_PC10G_TCC1_WO4 (6L) -#define PINMUX_PC10G_TCC1_WO4 ((PIN_PC10G_TCC1_WO4 << 16) | MUX_PC10G_TCC1_WO4) -#define PORT_PC10G_TCC1_WO4 ((1UL) << 10) - -#define PIN_PA20F_TCC1_WO4 (20L) -#define MUX_PA20F_TCC1_WO4 (5L) -#define PINMUX_PA20F_TCC1_WO4 ((PIN_PA20F_TCC1_WO4 << 16) | MUX_PA20F_TCC1_WO4) -#define PORT_PA20F_TCC1_WO4 ((1UL) << 20) - -#define PIN_PB28F_TCC1_WO4 (60L) -#define MUX_PB28F_TCC1_WO4 (5L) -#define PINMUX_PB28F_TCC1_WO4 ((PIN_PB28F_TCC1_WO4 << 16) | MUX_PB28F_TCC1_WO4) -#define PORT_PB28F_TCC1_WO4 ((1UL) << 28) - -#define PIN_PA09G_TCC1_WO5 (9L) -#define MUX_PA09G_TCC1_WO5 (6L) -#define PINMUX_PA09G_TCC1_WO5 ((PIN_PA09G_TCC1_WO5 << 16) | MUX_PA09G_TCC1_WO5) -#define PORT_PA09G_TCC1_WO5 ((1UL) << 9) - -#define PIN_PC11G_TCC1_WO5 (75L) -#define MUX_PC11G_TCC1_WO5 (6L) -#define PINMUX_PC11G_TCC1_WO5 ((PIN_PC11G_TCC1_WO5 << 16) | MUX_PC11G_TCC1_WO5) -#define PORT_PC11G_TCC1_WO5 ((1UL) << 11) - -#define PIN_PA21F_TCC1_WO5 (21L) -#define MUX_PA21F_TCC1_WO5 (5L) -#define PINMUX_PA21F_TCC1_WO5 ((PIN_PA21F_TCC1_WO5 << 16) | MUX_PA21F_TCC1_WO5) -#define PORT_PA21F_TCC1_WO5 ((1UL) << 21) - -#define PIN_PB29F_TCC1_WO5 (61L) -#define MUX_PB29F_TCC1_WO5 (5L) -#define PINMUX_PB29F_TCC1_WO5 ((PIN_PB29F_TCC1_WO5 << 16) | MUX_PB29F_TCC1_WO5) -#define PORT_PB29F_TCC1_WO5 ((1UL) << 29) - -#define PIN_PA10G_TCC1_WO6 (10L) -#define MUX_PA10G_TCC1_WO6 (6L) -#define PINMUX_PA10G_TCC1_WO6 ((PIN_PA10G_TCC1_WO6 << 16) | MUX_PA10G_TCC1_WO6) -#define PORT_PA10G_TCC1_WO6 ((1UL) << 10) - -#define PIN_PC12G_TCC1_WO6 (76L) -#define MUX_PC12G_TCC1_WO6 (6L) -#define PINMUX_PC12G_TCC1_WO6 ((PIN_PC12G_TCC1_WO6 << 16) | MUX_PC12G_TCC1_WO6) -#define PORT_PC12G_TCC1_WO6 ((1UL) << 12) - -#define PIN_PA22F_TCC1_WO6 (22L) -#define MUX_PA22F_TCC1_WO6 (5L) -#define PINMUX_PA22F_TCC1_WO6 ((PIN_PA22F_TCC1_WO6 << 16) | MUX_PA22F_TCC1_WO6) -#define PORT_PA22F_TCC1_WO6 ((1UL) << 22) - -#define PIN_PA11G_TCC1_WO7 (11L) -#define MUX_PA11G_TCC1_WO7 (6L) -#define PINMUX_PA11G_TCC1_WO7 ((PIN_PA11G_TCC1_WO7 << 16) | MUX_PA11G_TCC1_WO7) -#define PORT_PA11G_TCC1_WO7 ((1UL) << 11) - -#define PIN_PC13G_TCC1_WO7 (77L) -#define MUX_PC13G_TCC1_WO7 (6L) -#define PINMUX_PC13G_TCC1_WO7 ((PIN_PC13G_TCC1_WO7 << 16) | MUX_PC13G_TCC1_WO7) -#define PORT_PC13G_TCC1_WO7 ((1UL) << 13) - -#define PIN_PA23F_TCC1_WO7 (23L) -#define MUX_PA23F_TCC1_WO7 (5L) -#define PINMUX_PA23F_TCC1_WO7 ((PIN_PA23F_TCC1_WO7 << 16) | MUX_PA23F_TCC1_WO7) -#define PORT_PA23F_TCC1_WO7 ((1UL) << 23) - -/* ========== PORT definition for TCC2 peripheral ========== */ -#define PIN_PA14F_TCC2_WO0 (14L) -#define MUX_PA14F_TCC2_WO0 (5L) -#define PINMUX_PA14F_TCC2_WO0 ((PIN_PA14F_TCC2_WO0 << 16) | MUX_PA14F_TCC2_WO0) -#define PORT_PA14F_TCC2_WO0 ((1UL) << 14) - -#define PIN_PA30F_TCC2_WO0 (30L) -#define MUX_PA30F_TCC2_WO0 (5L) -#define PINMUX_PA30F_TCC2_WO0 ((PIN_PA30F_TCC2_WO0 << 16) | MUX_PA30F_TCC2_WO0) -#define PORT_PA30F_TCC2_WO0 ((1UL) << 30) - -#define PIN_PA15F_TCC2_WO1 (15L) -#define MUX_PA15F_TCC2_WO1 (5L) -#define PINMUX_PA15F_TCC2_WO1 ((PIN_PA15F_TCC2_WO1 << 16) | MUX_PA15F_TCC2_WO1) -#define PORT_PA15F_TCC2_WO1 ((1UL) << 15) - -#define PIN_PA31F_TCC2_WO1 (31L) -#define MUX_PA31F_TCC2_WO1 (5L) -#define PINMUX_PA31F_TCC2_WO1 ((PIN_PA31F_TCC2_WO1 << 16) | MUX_PA31F_TCC2_WO1) -#define PORT_PA31F_TCC2_WO1 ((1UL) << 31) - -#define PIN_PA24F_TCC2_WO2 (24L) -#define MUX_PA24F_TCC2_WO2 (5L) -#define PINMUX_PA24F_TCC2_WO2 ((PIN_PA24F_TCC2_WO2 << 16) | MUX_PA24F_TCC2_WO2) -#define PORT_PA24F_TCC2_WO2 ((1UL) << 24) - -#define PIN_PB02F_TCC2_WO2 (34L) -#define MUX_PB02F_TCC2_WO2 (5L) -#define PINMUX_PB02F_TCC2_WO2 ((PIN_PB02F_TCC2_WO2 << 16) | MUX_PB02F_TCC2_WO2) -#define PORT_PB02F_TCC2_WO2 ((1UL) << 2) - -/* ========== PORT definition for TCC3 peripheral ========== */ -#define PIN_PB12F_TCC3_WO0 (44L) -#define MUX_PB12F_TCC3_WO0 (5L) -#define PINMUX_PB12F_TCC3_WO0 ((PIN_PB12F_TCC3_WO0 << 16) | MUX_PB12F_TCC3_WO0) -#define PORT_PB12F_TCC3_WO0 ((1UL) << 12) - -#define PIN_PB16F_TCC3_WO0 (48L) -#define MUX_PB16F_TCC3_WO0 (5L) -#define PINMUX_PB16F_TCC3_WO0 ((PIN_PB16F_TCC3_WO0 << 16) | MUX_PB16F_TCC3_WO0) -#define PORT_PB16F_TCC3_WO0 ((1UL) << 16) - -#define PIN_PB13F_TCC3_WO1 (45L) -#define MUX_PB13F_TCC3_WO1 (5L) -#define PINMUX_PB13F_TCC3_WO1 ((PIN_PB13F_TCC3_WO1 << 16) | MUX_PB13F_TCC3_WO1) -#define PORT_PB13F_TCC3_WO1 ((1UL) << 13) - -#define PIN_PB17F_TCC3_WO1 (49L) -#define MUX_PB17F_TCC3_WO1 (5L) -#define PINMUX_PB17F_TCC3_WO1 ((PIN_PB17F_TCC3_WO1 << 16) | MUX_PB17F_TCC3_WO1) -#define PORT_PB17F_TCC3_WO1 ((1UL) << 17) - -/* ========== PORT definition for TCC4 peripheral ========== */ -#define PIN_PB14F_TCC4_WO0 (46L) -#define MUX_PB14F_TCC4_WO0 (5L) -#define PINMUX_PB14F_TCC4_WO0 ((PIN_PB14F_TCC4_WO0 << 16) | MUX_PB14F_TCC4_WO0) -#define PORT_PB14F_TCC4_WO0 ((1UL) << 14) - -#define PIN_PB30F_TCC4_WO0 (62L) -#define MUX_PB30F_TCC4_WO0 (5L) -#define PINMUX_PB30F_TCC4_WO0 ((PIN_PB30F_TCC4_WO0 << 16) | MUX_PB30F_TCC4_WO0) -#define PORT_PB30F_TCC4_WO0 ((1UL) << 30) - -#define PIN_PB15F_TCC4_WO1 (47L) -#define MUX_PB15F_TCC4_WO1 (5L) -#define PINMUX_PB15F_TCC4_WO1 ((PIN_PB15F_TCC4_WO1 << 16) | MUX_PB15F_TCC4_WO1) -#define PORT_PB15F_TCC4_WO1 ((1UL) << 15) - -#define PIN_PB31F_TCC4_WO1 (63L) -#define MUX_PB31F_TCC4_WO1 (5L) -#define PINMUX_PB31F_TCC4_WO1 ((PIN_PB31F_TCC4_WO1 << 16) | MUX_PB31F_TCC4_WO1) -#define PORT_PB31F_TCC4_WO1 ((1UL) << 31) - -/* ========== PORT definition for USB peripheral ========== */ -#define PIN_PA24H_USB_DM (24L) -#define MUX_PA24H_USB_DM (7L) -#define PINMUX_PA24H_USB_DM ((PIN_PA24H_USB_DM << 16) | MUX_PA24H_USB_DM) -#define PORT_PA24H_USB_DM ((1UL) << 24) - -#define PIN_PA25H_USB_DP (25L) -#define MUX_PA25H_USB_DP (7L) -#define PINMUX_PA25H_USB_DP ((PIN_PA25H_USB_DP << 16) | MUX_PA25H_USB_DP) -#define PORT_PA25H_USB_DP ((1UL) << 25) - -#define PIN_PA23H_USB_SOF_1KHZ (23L) -#define MUX_PA23H_USB_SOF_1KHZ (7L) -#define PINMUX_PA23H_USB_SOF_1KHZ ((PIN_PA23H_USB_SOF_1KHZ << 16) | MUX_PA23H_USB_SOF_1KHZ) -#define PORT_PA23H_USB_SOF_1KHZ ((1UL) << 23) - -#define PIN_PB22H_USB_SOF_1KHZ (54L) -#define MUX_PB22H_USB_SOF_1KHZ (7L) -#define PINMUX_PB22H_USB_SOF_1KHZ ((PIN_PB22H_USB_SOF_1KHZ << 16) | MUX_PB22H_USB_SOF_1KHZ) -#define PORT_PB22H_USB_SOF_1KHZ ((1UL) << 22) - - - -#endif /* _SAME54P20A_GPIO_H_ */ - +/** + * \file + * + * \brief Peripheral I/O description for SAME54P20A + * + * Copyright (c) 2019 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAME54P20A_PIO_ +#define _SAME54P20A_PIO_ + +#define PIN_PA00 0 /**< \brief Pin Number for PA00 */ +#define PORT_PA00 (_UL_(1) << 0) /**< \brief PORT Mask for PA00 */ +#define PIN_PA01 1 /**< \brief Pin Number for PA01 */ +#define PORT_PA01 (_UL_(1) << 1) /**< \brief PORT Mask for PA01 */ +#define PIN_PA02 2 /**< \brief Pin Number for PA02 */ +#define PORT_PA02 (_UL_(1) << 2) /**< \brief PORT Mask for PA02 */ +#define PIN_PA03 3 /**< \brief Pin Number for PA03 */ +#define PORT_PA03 (_UL_(1) << 3) /**< \brief PORT Mask for PA03 */ +#define PIN_PA04 4 /**< \brief Pin Number for PA04 */ +#define PORT_PA04 (_UL_(1) << 4) /**< \brief PORT Mask for PA04 */ +#define PIN_PA05 5 /**< \brief Pin Number for PA05 */ +#define PORT_PA05 (_UL_(1) << 5) /**< \brief PORT Mask for PA05 */ +#define PIN_PA06 6 /**< \brief Pin Number for PA06 */ +#define PORT_PA06 (_UL_(1) << 6) /**< \brief PORT Mask for PA06 */ +#define PIN_PA07 7 /**< \brief Pin Number for PA07 */ +#define PORT_PA07 (_UL_(1) << 7) /**< \brief PORT Mask for PA07 */ +#define PIN_PA08 8 /**< \brief Pin Number for PA08 */ +#define PORT_PA08 (_UL_(1) << 8) /**< \brief PORT Mask for PA08 */ +#define PIN_PA09 9 /**< \brief Pin Number for PA09 */ +#define PORT_PA09 (_UL_(1) << 9) /**< \brief PORT Mask for PA09 */ +#define PIN_PA10 10 /**< \brief Pin Number for PA10 */ +#define PORT_PA10 (_UL_(1) << 10) /**< \brief PORT Mask for PA10 */ +#define PIN_PA11 11 /**< \brief Pin Number for PA11 */ +#define PORT_PA11 (_UL_(1) << 11) /**< \brief PORT Mask for PA11 */ +#define PIN_PA12 12 /**< \brief Pin Number for PA12 */ +#define PORT_PA12 (_UL_(1) << 12) /**< \brief PORT Mask for PA12 */ +#define PIN_PA13 13 /**< \brief Pin Number for PA13 */ +#define PORT_PA13 (_UL_(1) << 13) /**< \brief PORT Mask for PA13 */ +#define PIN_PA14 14 /**< \brief Pin Number for PA14 */ +#define PORT_PA14 (_UL_(1) << 14) /**< \brief PORT Mask for PA14 */ +#define PIN_PA15 15 /**< \brief Pin Number for PA15 */ +#define PORT_PA15 (_UL_(1) << 15) /**< \brief PORT Mask for PA15 */ +#define PIN_PA16 16 /**< \brief Pin Number for PA16 */ +#define PORT_PA16 (_UL_(1) << 16) /**< \brief PORT Mask for PA16 */ +#define PIN_PA17 17 /**< \brief Pin Number for PA17 */ +#define PORT_PA17 (_UL_(1) << 17) /**< \brief PORT Mask for PA17 */ +#define PIN_PA18 18 /**< \brief Pin Number for PA18 */ +#define PORT_PA18 (_UL_(1) << 18) /**< \brief PORT Mask for PA18 */ +#define PIN_PA19 19 /**< \brief Pin Number for PA19 */ +#define PORT_PA19 (_UL_(1) << 19) /**< \brief PORT Mask for PA19 */ +#define PIN_PA20 20 /**< \brief Pin Number for PA20 */ +#define PORT_PA20 (_UL_(1) << 20) /**< \brief PORT Mask for PA20 */ +#define PIN_PA21 21 /**< \brief Pin Number for PA21 */ +#define PORT_PA21 (_UL_(1) << 21) /**< \brief PORT Mask for PA21 */ +#define PIN_PA22 22 /**< \brief Pin Number for PA22 */ +#define PORT_PA22 (_UL_(1) << 22) /**< \brief PORT Mask for PA22 */ +#define PIN_PA23 23 /**< \brief Pin Number for PA23 */ +#define PORT_PA23 (_UL_(1) << 23) /**< \brief PORT Mask for PA23 */ +#define PIN_PA24 24 /**< \brief Pin Number for PA24 */ +#define PORT_PA24 (_UL_(1) << 24) /**< \brief PORT Mask for PA24 */ +#define PIN_PA25 25 /**< \brief Pin Number for PA25 */ +#define PORT_PA25 (_UL_(1) << 25) /**< \brief PORT Mask for PA25 */ +#define PIN_PA27 27 /**< \brief Pin Number for PA27 */ +#define PORT_PA27 (_UL_(1) << 27) /**< \brief PORT Mask for PA27 */ +#define PIN_PA30 30 /**< \brief Pin Number for PA30 */ +#define PORT_PA30 (_UL_(1) << 30) /**< \brief PORT Mask for PA30 */ +#define PIN_PA31 31 /**< \brief Pin Number for PA31 */ +#define PORT_PA31 (_UL_(1) << 31) /**< \brief PORT Mask for PA31 */ +#define PIN_PB00 32 /**< \brief Pin Number for PB00 */ +#define PORT_PB00 (_UL_(1) << 0) /**< \brief PORT Mask for PB00 */ +#define PIN_PB01 33 /**< \brief Pin Number for PB01 */ +#define PORT_PB01 (_UL_(1) << 1) /**< \brief PORT Mask for PB01 */ +#define PIN_PB02 34 /**< \brief Pin Number for PB02 */ +#define PORT_PB02 (_UL_(1) << 2) /**< \brief PORT Mask for PB02 */ +#define PIN_PB03 35 /**< \brief Pin Number for PB03 */ +#define PORT_PB03 (_UL_(1) << 3) /**< \brief PORT Mask for PB03 */ +#define PIN_PB04 36 /**< \brief Pin Number for PB04 */ +#define PORT_PB04 (_UL_(1) << 4) /**< \brief PORT Mask for PB04 */ +#define PIN_PB05 37 /**< \brief Pin Number for PB05 */ +#define PORT_PB05 (_UL_(1) << 5) /**< \brief PORT Mask for PB05 */ +#define PIN_PB06 38 /**< \brief Pin Number for PB06 */ +#define PORT_PB06 (_UL_(1) << 6) /**< \brief PORT Mask for PB06 */ +#define PIN_PB07 39 /**< \brief Pin Number for PB07 */ +#define PORT_PB07 (_UL_(1) << 7) /**< \brief PORT Mask for PB07 */ +#define PIN_PB08 40 /**< \brief Pin Number for PB08 */ +#define PORT_PB08 (_UL_(1) << 8) /**< \brief PORT Mask for PB08 */ +#define PIN_PB09 41 /**< \brief Pin Number for PB09 */ +#define PORT_PB09 (_UL_(1) << 9) /**< \brief PORT Mask for PB09 */ +#define PIN_PB10 42 /**< \brief Pin Number for PB10 */ +#define PORT_PB10 (_UL_(1) << 10) /**< \brief PORT Mask for PB10 */ +#define PIN_PB11 43 /**< \brief Pin Number for PB11 */ +#define PORT_PB11 (_UL_(1) << 11) /**< \brief PORT Mask for PB11 */ +#define PIN_PB12 44 /**< \brief Pin Number for PB12 */ +#define PORT_PB12 (_UL_(1) << 12) /**< \brief PORT Mask for PB12 */ +#define PIN_PB13 45 /**< \brief Pin Number for PB13 */ +#define PORT_PB13 (_UL_(1) << 13) /**< \brief PORT Mask for PB13 */ +#define PIN_PB14 46 /**< \brief Pin Number for PB14 */ +#define PORT_PB14 (_UL_(1) << 14) /**< \brief PORT Mask for PB14 */ +#define PIN_PB15 47 /**< \brief Pin Number for PB15 */ +#define PORT_PB15 (_UL_(1) << 15) /**< \brief PORT Mask for PB15 */ +#define PIN_PB16 48 /**< \brief Pin Number for PB16 */ +#define PORT_PB16 (_UL_(1) << 16) /**< \brief PORT Mask for PB16 */ +#define PIN_PB17 49 /**< \brief Pin Number for PB17 */ +#define PORT_PB17 (_UL_(1) << 17) /**< \brief PORT Mask for PB17 */ +#define PIN_PB18 50 /**< \brief Pin Number for PB18 */ +#define PORT_PB18 (_UL_(1) << 18) /**< \brief PORT Mask for PB18 */ +#define PIN_PB19 51 /**< \brief Pin Number for PB19 */ +#define PORT_PB19 (_UL_(1) << 19) /**< \brief PORT Mask for PB19 */ +#define PIN_PB20 52 /**< \brief Pin Number for PB20 */ +#define PORT_PB20 (_UL_(1) << 20) /**< \brief PORT Mask for PB20 */ +#define PIN_PB21 53 /**< \brief Pin Number for PB21 */ +#define PORT_PB21 (_UL_(1) << 21) /**< \brief PORT Mask for PB21 */ +#define PIN_PB22 54 /**< \brief Pin Number for PB22 */ +#define PORT_PB22 (_UL_(1) << 22) /**< \brief PORT Mask for PB22 */ +#define PIN_PB23 55 /**< \brief Pin Number for PB23 */ +#define PORT_PB23 (_UL_(1) << 23) /**< \brief PORT Mask for PB23 */ +#define PIN_PB24 56 /**< \brief Pin Number for PB24 */ +#define PORT_PB24 (_UL_(1) << 24) /**< \brief PORT Mask for PB24 */ +#define PIN_PB25 57 /**< \brief Pin Number for PB25 */ +#define PORT_PB25 (_UL_(1) << 25) /**< \brief PORT Mask for PB25 */ +#define PIN_PB26 58 /**< \brief Pin Number for PB26 */ +#define PORT_PB26 (_UL_(1) << 26) /**< \brief PORT Mask for PB26 */ +#define PIN_PB27 59 /**< \brief Pin Number for PB27 */ +#define PORT_PB27 (_UL_(1) << 27) /**< \brief PORT Mask for PB27 */ +#define PIN_PB28 60 /**< \brief Pin Number for PB28 */ +#define PORT_PB28 (_UL_(1) << 28) /**< \brief PORT Mask for PB28 */ +#define PIN_PB29 61 /**< \brief Pin Number for PB29 */ +#define PORT_PB29 (_UL_(1) << 29) /**< \brief PORT Mask for PB29 */ +#define PIN_PB30 62 /**< \brief Pin Number for PB30 */ +#define PORT_PB30 (_UL_(1) << 30) /**< \brief PORT Mask for PB30 */ +#define PIN_PB31 63 /**< \brief Pin Number for PB31 */ +#define PORT_PB31 (_UL_(1) << 31) /**< \brief PORT Mask for PB31 */ +#define PIN_PC00 64 /**< \brief Pin Number for PC00 */ +#define PORT_PC00 (_UL_(1) << 0) /**< \brief PORT Mask for PC00 */ +#define PIN_PC01 65 /**< \brief Pin Number for PC01 */ +#define PORT_PC01 (_UL_(1) << 1) /**< \brief PORT Mask for PC01 */ +#define PIN_PC02 66 /**< \brief Pin Number for PC02 */ +#define PORT_PC02 (_UL_(1) << 2) /**< \brief PORT Mask for PC02 */ +#define PIN_PC03 67 /**< \brief Pin Number for PC03 */ +#define PORT_PC03 (_UL_(1) << 3) /**< \brief PORT Mask for PC03 */ +#define PIN_PC04 68 /**< \brief Pin Number for PC04 */ +#define PORT_PC04 (_UL_(1) << 4) /**< \brief PORT Mask for PC04 */ +#define PIN_PC05 69 /**< \brief Pin Number for PC05 */ +#define PORT_PC05 (_UL_(1) << 5) /**< \brief PORT Mask for PC05 */ +#define PIN_PC06 70 /**< \brief Pin Number for PC06 */ +#define PORT_PC06 (_UL_(1) << 6) /**< \brief PORT Mask for PC06 */ +#define PIN_PC07 71 /**< \brief Pin Number for PC07 */ +#define PORT_PC07 (_UL_(1) << 7) /**< \brief PORT Mask for PC07 */ +#define PIN_PC10 74 /**< \brief Pin Number for PC10 */ +#define PORT_PC10 (_UL_(1) << 10) /**< \brief PORT Mask for PC10 */ +#define PIN_PC11 75 /**< \brief Pin Number for PC11 */ +#define PORT_PC11 (_UL_(1) << 11) /**< \brief PORT Mask for PC11 */ +#define PIN_PC12 76 /**< \brief Pin Number for PC12 */ +#define PORT_PC12 (_UL_(1) << 12) /**< \brief PORT Mask for PC12 */ +#define PIN_PC13 77 /**< \brief Pin Number for PC13 */ +#define PORT_PC13 (_UL_(1) << 13) /**< \brief PORT Mask for PC13 */ +#define PIN_PC14 78 /**< \brief Pin Number for PC14 */ +#define PORT_PC14 (_UL_(1) << 14) /**< \brief PORT Mask for PC14 */ +#define PIN_PC15 79 /**< \brief Pin Number for PC15 */ +#define PORT_PC15 (_UL_(1) << 15) /**< \brief PORT Mask for PC15 */ +#define PIN_PC16 80 /**< \brief Pin Number for PC16 */ +#define PORT_PC16 (_UL_(1) << 16) /**< \brief PORT Mask for PC16 */ +#define PIN_PC17 81 /**< \brief Pin Number for PC17 */ +#define PORT_PC17 (_UL_(1) << 17) /**< \brief PORT Mask for PC17 */ +#define PIN_PC18 82 /**< \brief Pin Number for PC18 */ +#define PORT_PC18 (_UL_(1) << 18) /**< \brief PORT Mask for PC18 */ +#define PIN_PC19 83 /**< \brief Pin Number for PC19 */ +#define PORT_PC19 (_UL_(1) << 19) /**< \brief PORT Mask for PC19 */ +#define PIN_PC20 84 /**< \brief Pin Number for PC20 */ +#define PORT_PC20 (_UL_(1) << 20) /**< \brief PORT Mask for PC20 */ +#define PIN_PC21 85 /**< \brief Pin Number for PC21 */ +#define PORT_PC21 (_UL_(1) << 21) /**< \brief PORT Mask for PC21 */ +#define PIN_PC22 86 /**< \brief Pin Number for PC22 */ +#define PORT_PC22 (_UL_(1) << 22) /**< \brief PORT Mask for PC22 */ +#define PIN_PC23 87 /**< \brief Pin Number for PC23 */ +#define PORT_PC23 (_UL_(1) << 23) /**< \brief PORT Mask for PC23 */ +#define PIN_PC24 88 /**< \brief Pin Number for PC24 */ +#define PORT_PC24 (_UL_(1) << 24) /**< \brief PORT Mask for PC24 */ +#define PIN_PC25 89 /**< \brief Pin Number for PC25 */ +#define PORT_PC25 (_UL_(1) << 25) /**< \brief PORT Mask for PC25 */ +#define PIN_PC26 90 /**< \brief Pin Number for PC26 */ +#define PORT_PC26 (_UL_(1) << 26) /**< \brief PORT Mask for PC26 */ +#define PIN_PC27 91 /**< \brief Pin Number for PC27 */ +#define PORT_PC27 (_UL_(1) << 27) /**< \brief PORT Mask for PC27 */ +#define PIN_PC28 92 /**< \brief Pin Number for PC28 */ +#define PORT_PC28 (_UL_(1) << 28) /**< \brief PORT Mask for PC28 */ +#define PIN_PC30 94 /**< \brief Pin Number for PC30 */ +#define PORT_PC30 (_UL_(1) << 30) /**< \brief PORT Mask for PC30 */ +#define PIN_PC31 95 /**< \brief Pin Number for PC31 */ +#define PORT_PC31 (_UL_(1) << 31) /**< \brief PORT Mask for PC31 */ +#define PIN_PD00 96 /**< \brief Pin Number for PD00 */ +#define PORT_PD00 (_UL_(1) << 0) /**< \brief PORT Mask for PD00 */ +#define PIN_PD01 97 /**< \brief Pin Number for PD01 */ +#define PORT_PD01 (_UL_(1) << 1) /**< \brief PORT Mask for PD01 */ +#define PIN_PD08 104 /**< \brief Pin Number for PD08 */ +#define PORT_PD08 (_UL_(1) << 8) /**< \brief PORT Mask for PD08 */ +#define PIN_PD09 105 /**< \brief Pin Number for PD09 */ +#define PORT_PD09 (_UL_(1) << 9) /**< \brief PORT Mask for PD09 */ +#define PIN_PD10 106 /**< \brief Pin Number for PD10 */ +#define PORT_PD10 (_UL_(1) << 10) /**< \brief PORT Mask for PD10 */ +#define PIN_PD11 107 /**< \brief Pin Number for PD11 */ +#define PORT_PD11 (_UL_(1) << 11) /**< \brief PORT Mask for PD11 */ +#define PIN_PD12 108 /**< \brief Pin Number for PD12 */ +#define PORT_PD12 (_UL_(1) << 12) /**< \brief PORT Mask for PD12 */ +#define PIN_PD20 116 /**< \brief Pin Number for PD20 */ +#define PORT_PD20 (_UL_(1) << 20) /**< \brief PORT Mask for PD20 */ +#define PIN_PD21 117 /**< \brief Pin Number for PD21 */ +#define PORT_PD21 (_UL_(1) << 21) /**< \brief PORT Mask for PD21 */ +/* ========== PORT definition for CM4 peripheral ========== */ +#define PIN_PA30H_CM4_SWCLK _L_(30) /**< \brief CM4 signal: SWCLK on PA30 mux H */ +#define MUX_PA30H_CM4_SWCLK _L_(7) +#define PINMUX_PA30H_CM4_SWCLK ((PIN_PA30H_CM4_SWCLK << 16) | MUX_PA30H_CM4_SWCLK) +#define PORT_PA30H_CM4_SWCLK (_UL_(1) << 30) +#define PIN_PC27M_CM4_SWO _L_(91) /**< \brief CM4 signal: SWO on PC27 mux M */ +#define MUX_PC27M_CM4_SWO _L_(12) +#define PINMUX_PC27M_CM4_SWO ((PIN_PC27M_CM4_SWO << 16) | MUX_PC27M_CM4_SWO) +#define PORT_PC27M_CM4_SWO (_UL_(1) << 27) +#define PIN_PB30H_CM4_SWO _L_(62) /**< \brief CM4 signal: SWO on PB30 mux H */ +#define MUX_PB30H_CM4_SWO _L_(7) +#define PINMUX_PB30H_CM4_SWO ((PIN_PB30H_CM4_SWO << 16) | MUX_PB30H_CM4_SWO) +#define PORT_PB30H_CM4_SWO (_UL_(1) << 30) +#define PIN_PC27H_CM4_TRACECLK _L_(91) /**< \brief CM4 signal: TRACECLK on PC27 mux H */ +#define MUX_PC27H_CM4_TRACECLK _L_(7) +#define PINMUX_PC27H_CM4_TRACECLK ((PIN_PC27H_CM4_TRACECLK << 16) | MUX_PC27H_CM4_TRACECLK) +#define PORT_PC27H_CM4_TRACECLK (_UL_(1) << 27) +#define PIN_PC28H_CM4_TRACEDATA0 _L_(92) /**< \brief CM4 signal: TRACEDATA0 on PC28 mux H */ +#define MUX_PC28H_CM4_TRACEDATA0 _L_(7) +#define PINMUX_PC28H_CM4_TRACEDATA0 ((PIN_PC28H_CM4_TRACEDATA0 << 16) | MUX_PC28H_CM4_TRACEDATA0) +#define PORT_PC28H_CM4_TRACEDATA0 (_UL_(1) << 28) +#define PIN_PC26H_CM4_TRACEDATA1 _L_(90) /**< \brief CM4 signal: TRACEDATA1 on PC26 mux H */ +#define MUX_PC26H_CM4_TRACEDATA1 _L_(7) +#define PINMUX_PC26H_CM4_TRACEDATA1 ((PIN_PC26H_CM4_TRACEDATA1 << 16) | MUX_PC26H_CM4_TRACEDATA1) +#define PORT_PC26H_CM4_TRACEDATA1 (_UL_(1) << 26) +#define PIN_PC25H_CM4_TRACEDATA2 _L_(89) /**< \brief CM4 signal: TRACEDATA2 on PC25 mux H */ +#define MUX_PC25H_CM4_TRACEDATA2 _L_(7) +#define PINMUX_PC25H_CM4_TRACEDATA2 ((PIN_PC25H_CM4_TRACEDATA2 << 16) | MUX_PC25H_CM4_TRACEDATA2) +#define PORT_PC25H_CM4_TRACEDATA2 (_UL_(1) << 25) +#define PIN_PC24H_CM4_TRACEDATA3 _L_(88) /**< \brief CM4 signal: TRACEDATA3 on PC24 mux H */ +#define MUX_PC24H_CM4_TRACEDATA3 _L_(7) +#define PINMUX_PC24H_CM4_TRACEDATA3 ((PIN_PC24H_CM4_TRACEDATA3 << 16) | MUX_PC24H_CM4_TRACEDATA3) +#define PORT_PC24H_CM4_TRACEDATA3 (_UL_(1) << 24) +/* ========== PORT definition for ANAREF peripheral ========== */ +#define PIN_PA03B_ANAREF_VREF0 _L_(3) /**< \brief ANAREF signal: VREF0 on PA03 mux B */ +#define MUX_PA03B_ANAREF_VREF0 _L_(1) +#define PINMUX_PA03B_ANAREF_VREF0 ((PIN_PA03B_ANAREF_VREF0 << 16) | MUX_PA03B_ANAREF_VREF0) +#define PORT_PA03B_ANAREF_VREF0 (_UL_(1) << 3) +#define PIN_PA04B_ANAREF_VREF1 _L_(4) /**< \brief ANAREF signal: VREF1 on PA04 mux B */ +#define MUX_PA04B_ANAREF_VREF1 _L_(1) +#define PINMUX_PA04B_ANAREF_VREF1 ((PIN_PA04B_ANAREF_VREF1 << 16) | MUX_PA04B_ANAREF_VREF1) +#define PORT_PA04B_ANAREF_VREF1 (_UL_(1) << 4) +#define PIN_PA06B_ANAREF_VREF2 _L_(6) /**< \brief ANAREF signal: VREF2 on PA06 mux B */ +#define MUX_PA06B_ANAREF_VREF2 _L_(1) +#define PINMUX_PA06B_ANAREF_VREF2 ((PIN_PA06B_ANAREF_VREF2 << 16) | MUX_PA06B_ANAREF_VREF2) +#define PORT_PA06B_ANAREF_VREF2 (_UL_(1) << 6) +/* ========== PORT definition for GCLK peripheral ========== */ +#define PIN_PA30M_GCLK_IO0 _L_(30) /**< \brief GCLK signal: IO0 on PA30 mux M */ +#define MUX_PA30M_GCLK_IO0 _L_(12) +#define PINMUX_PA30M_GCLK_IO0 ((PIN_PA30M_GCLK_IO0 << 16) | MUX_PA30M_GCLK_IO0) +#define PORT_PA30M_GCLK_IO0 (_UL_(1) << 30) +#define PIN_PB14M_GCLK_IO0 _L_(46) /**< \brief GCLK signal: IO0 on PB14 mux M */ +#define MUX_PB14M_GCLK_IO0 _L_(12) +#define PINMUX_PB14M_GCLK_IO0 ((PIN_PB14M_GCLK_IO0 << 16) | MUX_PB14M_GCLK_IO0) +#define PORT_PB14M_GCLK_IO0 (_UL_(1) << 14) +#define PIN_PA14M_GCLK_IO0 _L_(14) /**< \brief GCLK signal: IO0 on PA14 mux M */ +#define MUX_PA14M_GCLK_IO0 _L_(12) +#define PINMUX_PA14M_GCLK_IO0 ((PIN_PA14M_GCLK_IO0 << 16) | MUX_PA14M_GCLK_IO0) +#define PORT_PA14M_GCLK_IO0 (_UL_(1) << 14) +#define PIN_PB22M_GCLK_IO0 _L_(54) /**< \brief GCLK signal: IO0 on PB22 mux M */ +#define MUX_PB22M_GCLK_IO0 _L_(12) +#define PINMUX_PB22M_GCLK_IO0 ((PIN_PB22M_GCLK_IO0 << 16) | MUX_PB22M_GCLK_IO0) +#define PORT_PB22M_GCLK_IO0 (_UL_(1) << 22) +#define PIN_PB15M_GCLK_IO1 _L_(47) /**< \brief GCLK signal: IO1 on PB15 mux M */ +#define MUX_PB15M_GCLK_IO1 _L_(12) +#define PINMUX_PB15M_GCLK_IO1 ((PIN_PB15M_GCLK_IO1 << 16) | MUX_PB15M_GCLK_IO1) +#define PORT_PB15M_GCLK_IO1 (_UL_(1) << 15) +#define PIN_PA15M_GCLK_IO1 _L_(15) /**< \brief GCLK signal: IO1 on PA15 mux M */ +#define MUX_PA15M_GCLK_IO1 _L_(12) +#define PINMUX_PA15M_GCLK_IO1 ((PIN_PA15M_GCLK_IO1 << 16) | MUX_PA15M_GCLK_IO1) +#define PORT_PA15M_GCLK_IO1 (_UL_(1) << 15) +#define PIN_PB23M_GCLK_IO1 _L_(55) /**< \brief GCLK signal: IO1 on PB23 mux M */ +#define MUX_PB23M_GCLK_IO1 _L_(12) +#define PINMUX_PB23M_GCLK_IO1 ((PIN_PB23M_GCLK_IO1 << 16) | MUX_PB23M_GCLK_IO1) +#define PORT_PB23M_GCLK_IO1 (_UL_(1) << 23) +#define PIN_PA27M_GCLK_IO1 _L_(27) /**< \brief GCLK signal: IO1 on PA27 mux M */ +#define MUX_PA27M_GCLK_IO1 _L_(12) +#define PINMUX_PA27M_GCLK_IO1 ((PIN_PA27M_GCLK_IO1 << 16) | MUX_PA27M_GCLK_IO1) +#define PORT_PA27M_GCLK_IO1 (_UL_(1) << 27) +#define PIN_PA16M_GCLK_IO2 _L_(16) /**< \brief GCLK signal: IO2 on PA16 mux M */ +#define MUX_PA16M_GCLK_IO2 _L_(12) +#define PINMUX_PA16M_GCLK_IO2 ((PIN_PA16M_GCLK_IO2 << 16) | MUX_PA16M_GCLK_IO2) +#define PORT_PA16M_GCLK_IO2 (_UL_(1) << 16) +#define PIN_PB16M_GCLK_IO2 _L_(48) /**< \brief GCLK signal: IO2 on PB16 mux M */ +#define MUX_PB16M_GCLK_IO2 _L_(12) +#define PINMUX_PB16M_GCLK_IO2 ((PIN_PB16M_GCLK_IO2 << 16) | MUX_PB16M_GCLK_IO2) +#define PORT_PB16M_GCLK_IO2 (_UL_(1) << 16) +#define PIN_PA17M_GCLK_IO3 _L_(17) /**< \brief GCLK signal: IO3 on PA17 mux M */ +#define MUX_PA17M_GCLK_IO3 _L_(12) +#define PINMUX_PA17M_GCLK_IO3 ((PIN_PA17M_GCLK_IO3 << 16) | MUX_PA17M_GCLK_IO3) +#define PORT_PA17M_GCLK_IO3 (_UL_(1) << 17) +#define PIN_PB17M_GCLK_IO3 _L_(49) /**< \brief GCLK signal: IO3 on PB17 mux M */ +#define MUX_PB17M_GCLK_IO3 _L_(12) +#define PINMUX_PB17M_GCLK_IO3 ((PIN_PB17M_GCLK_IO3 << 16) | MUX_PB17M_GCLK_IO3) +#define PORT_PB17M_GCLK_IO3 (_UL_(1) << 17) +#define PIN_PA10M_GCLK_IO4 _L_(10) /**< \brief GCLK signal: IO4 on PA10 mux M */ +#define MUX_PA10M_GCLK_IO4 _L_(12) +#define PINMUX_PA10M_GCLK_IO4 ((PIN_PA10M_GCLK_IO4 << 16) | MUX_PA10M_GCLK_IO4) +#define PORT_PA10M_GCLK_IO4 (_UL_(1) << 10) +#define PIN_PB10M_GCLK_IO4 _L_(42) /**< \brief GCLK signal: IO4 on PB10 mux M */ +#define MUX_PB10M_GCLK_IO4 _L_(12) +#define PINMUX_PB10M_GCLK_IO4 ((PIN_PB10M_GCLK_IO4 << 16) | MUX_PB10M_GCLK_IO4) +#define PORT_PB10M_GCLK_IO4 (_UL_(1) << 10) +#define PIN_PB18M_GCLK_IO4 _L_(50) /**< \brief GCLK signal: IO4 on PB18 mux M */ +#define MUX_PB18M_GCLK_IO4 _L_(12) +#define PINMUX_PB18M_GCLK_IO4 ((PIN_PB18M_GCLK_IO4 << 16) | MUX_PB18M_GCLK_IO4) +#define PORT_PB18M_GCLK_IO4 (_UL_(1) << 18) +#define PIN_PA11M_GCLK_IO5 _L_(11) /**< \brief GCLK signal: IO5 on PA11 mux M */ +#define MUX_PA11M_GCLK_IO5 _L_(12) +#define PINMUX_PA11M_GCLK_IO5 ((PIN_PA11M_GCLK_IO5 << 16) | MUX_PA11M_GCLK_IO5) +#define PORT_PA11M_GCLK_IO5 (_UL_(1) << 11) +#define PIN_PB11M_GCLK_IO5 _L_(43) /**< \brief GCLK signal: IO5 on PB11 mux M */ +#define MUX_PB11M_GCLK_IO5 _L_(12) +#define PINMUX_PB11M_GCLK_IO5 ((PIN_PB11M_GCLK_IO5 << 16) | MUX_PB11M_GCLK_IO5) +#define PORT_PB11M_GCLK_IO5 (_UL_(1) << 11) +#define PIN_PB19M_GCLK_IO5 _L_(51) /**< \brief GCLK signal: IO5 on PB19 mux M */ +#define MUX_PB19M_GCLK_IO5 _L_(12) +#define PINMUX_PB19M_GCLK_IO5 ((PIN_PB19M_GCLK_IO5 << 16) | MUX_PB19M_GCLK_IO5) +#define PORT_PB19M_GCLK_IO5 (_UL_(1) << 19) +#define PIN_PB12M_GCLK_IO6 _L_(44) /**< \brief GCLK signal: IO6 on PB12 mux M */ +#define MUX_PB12M_GCLK_IO6 _L_(12) +#define PINMUX_PB12M_GCLK_IO6 ((PIN_PB12M_GCLK_IO6 << 16) | MUX_PB12M_GCLK_IO6) +#define PORT_PB12M_GCLK_IO6 (_UL_(1) << 12) +#define PIN_PB20M_GCLK_IO6 _L_(52) /**< \brief GCLK signal: IO6 on PB20 mux M */ +#define MUX_PB20M_GCLK_IO6 _L_(12) +#define PINMUX_PB20M_GCLK_IO6 ((PIN_PB20M_GCLK_IO6 << 16) | MUX_PB20M_GCLK_IO6) +#define PORT_PB20M_GCLK_IO6 (_UL_(1) << 20) +#define PIN_PB13M_GCLK_IO7 _L_(45) /**< \brief GCLK signal: IO7 on PB13 mux M */ +#define MUX_PB13M_GCLK_IO7 _L_(12) +#define PINMUX_PB13M_GCLK_IO7 ((PIN_PB13M_GCLK_IO7 << 16) | MUX_PB13M_GCLK_IO7) +#define PORT_PB13M_GCLK_IO7 (_UL_(1) << 13) +#define PIN_PB21M_GCLK_IO7 _L_(53) /**< \brief GCLK signal: IO7 on PB21 mux M */ +#define MUX_PB21M_GCLK_IO7 _L_(12) +#define PINMUX_PB21M_GCLK_IO7 ((PIN_PB21M_GCLK_IO7 << 16) | MUX_PB21M_GCLK_IO7) +#define PORT_PB21M_GCLK_IO7 (_UL_(1) << 21) +/* ========== PORT definition for EIC peripheral ========== */ +#define PIN_PA00A_EIC_EXTINT0 _L_(0) /**< \brief EIC signal: EXTINT0 on PA00 mux A */ +#define MUX_PA00A_EIC_EXTINT0 _L_(0) +#define PINMUX_PA00A_EIC_EXTINT0 ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0) +#define PORT_PA00A_EIC_EXTINT0 (_UL_(1) << 0) +#define PIN_PA00A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PA00 External Interrupt Line */ +#define PIN_PA16A_EIC_EXTINT0 _L_(16) /**< \brief EIC signal: EXTINT0 on PA16 mux A */ +#define MUX_PA16A_EIC_EXTINT0 _L_(0) +#define PINMUX_PA16A_EIC_EXTINT0 ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0) +#define PORT_PA16A_EIC_EXTINT0 (_UL_(1) << 16) +#define PIN_PA16A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PA16 External Interrupt Line */ +#define PIN_PB00A_EIC_EXTINT0 _L_(32) /**< \brief EIC signal: EXTINT0 on PB00 mux A */ +#define MUX_PB00A_EIC_EXTINT0 _L_(0) +#define PINMUX_PB00A_EIC_EXTINT0 ((PIN_PB00A_EIC_EXTINT0 << 16) | MUX_PB00A_EIC_EXTINT0) +#define PORT_PB00A_EIC_EXTINT0 (_UL_(1) << 0) +#define PIN_PB00A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PB00 External Interrupt Line */ +#define PIN_PB16A_EIC_EXTINT0 _L_(48) /**< \brief EIC signal: EXTINT0 on PB16 mux A */ +#define MUX_PB16A_EIC_EXTINT0 _L_(0) +#define PINMUX_PB16A_EIC_EXTINT0 ((PIN_PB16A_EIC_EXTINT0 << 16) | MUX_PB16A_EIC_EXTINT0) +#define PORT_PB16A_EIC_EXTINT0 (_UL_(1) << 16) +#define PIN_PB16A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PB16 External Interrupt Line */ +#define PIN_PC00A_EIC_EXTINT0 _L_(64) /**< \brief EIC signal: EXTINT0 on PC00 mux A */ +#define MUX_PC00A_EIC_EXTINT0 _L_(0) +#define PINMUX_PC00A_EIC_EXTINT0 ((PIN_PC00A_EIC_EXTINT0 << 16) | MUX_PC00A_EIC_EXTINT0) +#define PORT_PC00A_EIC_EXTINT0 (_UL_(1) << 0) +#define PIN_PC00A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PC00 External Interrupt Line */ +#define PIN_PC16A_EIC_EXTINT0 _L_(80) /**< \brief EIC signal: EXTINT0 on PC16 mux A */ +#define MUX_PC16A_EIC_EXTINT0 _L_(0) +#define PINMUX_PC16A_EIC_EXTINT0 ((PIN_PC16A_EIC_EXTINT0 << 16) | MUX_PC16A_EIC_EXTINT0) +#define PORT_PC16A_EIC_EXTINT0 (_UL_(1) << 16) +#define PIN_PC16A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PC16 External Interrupt Line */ +#define PIN_PD00A_EIC_EXTINT0 _L_(96) /**< \brief EIC signal: EXTINT0 on PD00 mux A */ +#define MUX_PD00A_EIC_EXTINT0 _L_(0) +#define PINMUX_PD00A_EIC_EXTINT0 ((PIN_PD00A_EIC_EXTINT0 << 16) | MUX_PD00A_EIC_EXTINT0) +#define PORT_PD00A_EIC_EXTINT0 (_UL_(1) << 0) +#define PIN_PD00A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PD00 External Interrupt Line */ +#define PIN_PA01A_EIC_EXTINT1 _L_(1) /**< \brief EIC signal: EXTINT1 on PA01 mux A */ +#define MUX_PA01A_EIC_EXTINT1 _L_(0) +#define PINMUX_PA01A_EIC_EXTINT1 ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1) +#define PORT_PA01A_EIC_EXTINT1 (_UL_(1) << 1) +#define PIN_PA01A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PA01 External Interrupt Line */ +#define PIN_PA17A_EIC_EXTINT1 _L_(17) /**< \brief EIC signal: EXTINT1 on PA17 mux A */ +#define MUX_PA17A_EIC_EXTINT1 _L_(0) +#define PINMUX_PA17A_EIC_EXTINT1 ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1) +#define PORT_PA17A_EIC_EXTINT1 (_UL_(1) << 17) +#define PIN_PA17A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PA17 External Interrupt Line */ +#define PIN_PB01A_EIC_EXTINT1 _L_(33) /**< \brief EIC signal: EXTINT1 on PB01 mux A */ +#define MUX_PB01A_EIC_EXTINT1 _L_(0) +#define PINMUX_PB01A_EIC_EXTINT1 ((PIN_PB01A_EIC_EXTINT1 << 16) | MUX_PB01A_EIC_EXTINT1) +#define PORT_PB01A_EIC_EXTINT1 (_UL_(1) << 1) +#define PIN_PB01A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PB01 External Interrupt Line */ +#define PIN_PB17A_EIC_EXTINT1 _L_(49) /**< \brief EIC signal: EXTINT1 on PB17 mux A */ +#define MUX_PB17A_EIC_EXTINT1 _L_(0) +#define PINMUX_PB17A_EIC_EXTINT1 ((PIN_PB17A_EIC_EXTINT1 << 16) | MUX_PB17A_EIC_EXTINT1) +#define PORT_PB17A_EIC_EXTINT1 (_UL_(1) << 17) +#define PIN_PB17A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PB17 External Interrupt Line */ +#define PIN_PC01A_EIC_EXTINT1 _L_(65) /**< \brief EIC signal: EXTINT1 on PC01 mux A */ +#define MUX_PC01A_EIC_EXTINT1 _L_(0) +#define PINMUX_PC01A_EIC_EXTINT1 ((PIN_PC01A_EIC_EXTINT1 << 16) | MUX_PC01A_EIC_EXTINT1) +#define PORT_PC01A_EIC_EXTINT1 (_UL_(1) << 1) +#define PIN_PC01A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PC01 External Interrupt Line */ +#define PIN_PC17A_EIC_EXTINT1 _L_(81) /**< \brief EIC signal: EXTINT1 on PC17 mux A */ +#define MUX_PC17A_EIC_EXTINT1 _L_(0) +#define PINMUX_PC17A_EIC_EXTINT1 ((PIN_PC17A_EIC_EXTINT1 << 16) | MUX_PC17A_EIC_EXTINT1) +#define PORT_PC17A_EIC_EXTINT1 (_UL_(1) << 17) +#define PIN_PC17A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PC17 External Interrupt Line */ +#define PIN_PD01A_EIC_EXTINT1 _L_(97) /**< \brief EIC signal: EXTINT1 on PD01 mux A */ +#define MUX_PD01A_EIC_EXTINT1 _L_(0) +#define PINMUX_PD01A_EIC_EXTINT1 ((PIN_PD01A_EIC_EXTINT1 << 16) | MUX_PD01A_EIC_EXTINT1) +#define PORT_PD01A_EIC_EXTINT1 (_UL_(1) << 1) +#define PIN_PD01A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PD01 External Interrupt Line */ +#define PIN_PA02A_EIC_EXTINT2 _L_(2) /**< \brief EIC signal: EXTINT2 on PA02 mux A */ +#define MUX_PA02A_EIC_EXTINT2 _L_(0) +#define PINMUX_PA02A_EIC_EXTINT2 ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2) +#define PORT_PA02A_EIC_EXTINT2 (_UL_(1) << 2) +#define PIN_PA02A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PA02 External Interrupt Line */ +#define PIN_PA18A_EIC_EXTINT2 _L_(18) /**< \brief EIC signal: EXTINT2 on PA18 mux A */ +#define MUX_PA18A_EIC_EXTINT2 _L_(0) +#define PINMUX_PA18A_EIC_EXTINT2 ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2) +#define PORT_PA18A_EIC_EXTINT2 (_UL_(1) << 18) +#define PIN_PA18A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PA18 External Interrupt Line */ +#define PIN_PB02A_EIC_EXTINT2 _L_(34) /**< \brief EIC signal: EXTINT2 on PB02 mux A */ +#define MUX_PB02A_EIC_EXTINT2 _L_(0) +#define PINMUX_PB02A_EIC_EXTINT2 ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2) +#define PORT_PB02A_EIC_EXTINT2 (_UL_(1) << 2) +#define PIN_PB02A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PB02 External Interrupt Line */ +#define PIN_PB18A_EIC_EXTINT2 _L_(50) /**< \brief EIC signal: EXTINT2 on PB18 mux A */ +#define MUX_PB18A_EIC_EXTINT2 _L_(0) +#define PINMUX_PB18A_EIC_EXTINT2 ((PIN_PB18A_EIC_EXTINT2 << 16) | MUX_PB18A_EIC_EXTINT2) +#define PORT_PB18A_EIC_EXTINT2 (_UL_(1) << 18) +#define PIN_PB18A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PB18 External Interrupt Line */ +#define PIN_PC02A_EIC_EXTINT2 _L_(66) /**< \brief EIC signal: EXTINT2 on PC02 mux A */ +#define MUX_PC02A_EIC_EXTINT2 _L_(0) +#define PINMUX_PC02A_EIC_EXTINT2 ((PIN_PC02A_EIC_EXTINT2 << 16) | MUX_PC02A_EIC_EXTINT2) +#define PORT_PC02A_EIC_EXTINT2 (_UL_(1) << 2) +#define PIN_PC02A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PC02 External Interrupt Line */ +#define PIN_PC18A_EIC_EXTINT2 _L_(82) /**< \brief EIC signal: EXTINT2 on PC18 mux A */ +#define MUX_PC18A_EIC_EXTINT2 _L_(0) +#define PINMUX_PC18A_EIC_EXTINT2 ((PIN_PC18A_EIC_EXTINT2 << 16) | MUX_PC18A_EIC_EXTINT2) +#define PORT_PC18A_EIC_EXTINT2 (_UL_(1) << 18) +#define PIN_PC18A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PC18 External Interrupt Line */ +#define PIN_PA03A_EIC_EXTINT3 _L_(3) /**< \brief EIC signal: EXTINT3 on PA03 mux A */ +#define MUX_PA03A_EIC_EXTINT3 _L_(0) +#define PINMUX_PA03A_EIC_EXTINT3 ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3) +#define PORT_PA03A_EIC_EXTINT3 (_UL_(1) << 3) +#define PIN_PA03A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PA03 External Interrupt Line */ +#define PIN_PA19A_EIC_EXTINT3 _L_(19) /**< \brief EIC signal: EXTINT3 on PA19 mux A */ +#define MUX_PA19A_EIC_EXTINT3 _L_(0) +#define PINMUX_PA19A_EIC_EXTINT3 ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3) +#define PORT_PA19A_EIC_EXTINT3 (_UL_(1) << 19) +#define PIN_PA19A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PA19 External Interrupt Line */ +#define PIN_PB03A_EIC_EXTINT3 _L_(35) /**< \brief EIC signal: EXTINT3 on PB03 mux A */ +#define MUX_PB03A_EIC_EXTINT3 _L_(0) +#define PINMUX_PB03A_EIC_EXTINT3 ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3) +#define PORT_PB03A_EIC_EXTINT3 (_UL_(1) << 3) +#define PIN_PB03A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PB03 External Interrupt Line */ +#define PIN_PB19A_EIC_EXTINT3 _L_(51) /**< \brief EIC signal: EXTINT3 on PB19 mux A */ +#define MUX_PB19A_EIC_EXTINT3 _L_(0) +#define PINMUX_PB19A_EIC_EXTINT3 ((PIN_PB19A_EIC_EXTINT3 << 16) | MUX_PB19A_EIC_EXTINT3) +#define PORT_PB19A_EIC_EXTINT3 (_UL_(1) << 19) +#define PIN_PB19A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PB19 External Interrupt Line */ +#define PIN_PC03A_EIC_EXTINT3 _L_(67) /**< \brief EIC signal: EXTINT3 on PC03 mux A */ +#define MUX_PC03A_EIC_EXTINT3 _L_(0) +#define PINMUX_PC03A_EIC_EXTINT3 ((PIN_PC03A_EIC_EXTINT3 << 16) | MUX_PC03A_EIC_EXTINT3) +#define PORT_PC03A_EIC_EXTINT3 (_UL_(1) << 3) +#define PIN_PC03A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PC03 External Interrupt Line */ +#define PIN_PC19A_EIC_EXTINT3 _L_(83) /**< \brief EIC signal: EXTINT3 on PC19 mux A */ +#define MUX_PC19A_EIC_EXTINT3 _L_(0) +#define PINMUX_PC19A_EIC_EXTINT3 ((PIN_PC19A_EIC_EXTINT3 << 16) | MUX_PC19A_EIC_EXTINT3) +#define PORT_PC19A_EIC_EXTINT3 (_UL_(1) << 19) +#define PIN_PC19A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PC19 External Interrupt Line */ +#define PIN_PD08A_EIC_EXTINT3 _L_(104) /**< \brief EIC signal: EXTINT3 on PD08 mux A */ +#define MUX_PD08A_EIC_EXTINT3 _L_(0) +#define PINMUX_PD08A_EIC_EXTINT3 ((PIN_PD08A_EIC_EXTINT3 << 16) | MUX_PD08A_EIC_EXTINT3) +#define PORT_PD08A_EIC_EXTINT3 (_UL_(1) << 8) +#define PIN_PD08A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PD08 External Interrupt Line */ +#define PIN_PA04A_EIC_EXTINT4 _L_(4) /**< \brief EIC signal: EXTINT4 on PA04 mux A */ +#define MUX_PA04A_EIC_EXTINT4 _L_(0) +#define PINMUX_PA04A_EIC_EXTINT4 ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4) +#define PORT_PA04A_EIC_EXTINT4 (_UL_(1) << 4) +#define PIN_PA04A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PA04 External Interrupt Line */ +#define PIN_PA20A_EIC_EXTINT4 _L_(20) /**< \brief EIC signal: EXTINT4 on PA20 mux A */ +#define MUX_PA20A_EIC_EXTINT4 _L_(0) +#define PINMUX_PA20A_EIC_EXTINT4 ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4) +#define PORT_PA20A_EIC_EXTINT4 (_UL_(1) << 20) +#define PIN_PA20A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PA20 External Interrupt Line */ +#define PIN_PB04A_EIC_EXTINT4 _L_(36) /**< \brief EIC signal: EXTINT4 on PB04 mux A */ +#define MUX_PB04A_EIC_EXTINT4 _L_(0) +#define PINMUX_PB04A_EIC_EXTINT4 ((PIN_PB04A_EIC_EXTINT4 << 16) | MUX_PB04A_EIC_EXTINT4) +#define PORT_PB04A_EIC_EXTINT4 (_UL_(1) << 4) +#define PIN_PB04A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PB04 External Interrupt Line */ +#define PIN_PB20A_EIC_EXTINT4 _L_(52) /**< \brief EIC signal: EXTINT4 on PB20 mux A */ +#define MUX_PB20A_EIC_EXTINT4 _L_(0) +#define PINMUX_PB20A_EIC_EXTINT4 ((PIN_PB20A_EIC_EXTINT4 << 16) | MUX_PB20A_EIC_EXTINT4) +#define PORT_PB20A_EIC_EXTINT4 (_UL_(1) << 20) +#define PIN_PB20A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PB20 External Interrupt Line */ +#define PIN_PC04A_EIC_EXTINT4 _L_(68) /**< \brief EIC signal: EXTINT4 on PC04 mux A */ +#define MUX_PC04A_EIC_EXTINT4 _L_(0) +#define PINMUX_PC04A_EIC_EXTINT4 ((PIN_PC04A_EIC_EXTINT4 << 16) | MUX_PC04A_EIC_EXTINT4) +#define PORT_PC04A_EIC_EXTINT4 (_UL_(1) << 4) +#define PIN_PC04A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PC04 External Interrupt Line */ +#define PIN_PC20A_EIC_EXTINT4 _L_(84) /**< \brief EIC signal: EXTINT4 on PC20 mux A */ +#define MUX_PC20A_EIC_EXTINT4 _L_(0) +#define PINMUX_PC20A_EIC_EXTINT4 ((PIN_PC20A_EIC_EXTINT4 << 16) | MUX_PC20A_EIC_EXTINT4) +#define PORT_PC20A_EIC_EXTINT4 (_UL_(1) << 20) +#define PIN_PC20A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PC20 External Interrupt Line */ +#define PIN_PD09A_EIC_EXTINT4 _L_(105) /**< \brief EIC signal: EXTINT4 on PD09 mux A */ +#define MUX_PD09A_EIC_EXTINT4 _L_(0) +#define PINMUX_PD09A_EIC_EXTINT4 ((PIN_PD09A_EIC_EXTINT4 << 16) | MUX_PD09A_EIC_EXTINT4) +#define PORT_PD09A_EIC_EXTINT4 (_UL_(1) << 9) +#define PIN_PD09A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PD09 External Interrupt Line */ +#define PIN_PA05A_EIC_EXTINT5 _L_(5) /**< \brief EIC signal: EXTINT5 on PA05 mux A */ +#define MUX_PA05A_EIC_EXTINT5 _L_(0) +#define PINMUX_PA05A_EIC_EXTINT5 ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5) +#define PORT_PA05A_EIC_EXTINT5 (_UL_(1) << 5) +#define PIN_PA05A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PA05 External Interrupt Line */ +#define PIN_PA21A_EIC_EXTINT5 _L_(21) /**< \brief EIC signal: EXTINT5 on PA21 mux A */ +#define MUX_PA21A_EIC_EXTINT5 _L_(0) +#define PINMUX_PA21A_EIC_EXTINT5 ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5) +#define PORT_PA21A_EIC_EXTINT5 (_UL_(1) << 21) +#define PIN_PA21A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PA21 External Interrupt Line */ +#define PIN_PB05A_EIC_EXTINT5 _L_(37) /**< \brief EIC signal: EXTINT5 on PB05 mux A */ +#define MUX_PB05A_EIC_EXTINT5 _L_(0) +#define PINMUX_PB05A_EIC_EXTINT5 ((PIN_PB05A_EIC_EXTINT5 << 16) | MUX_PB05A_EIC_EXTINT5) +#define PORT_PB05A_EIC_EXTINT5 (_UL_(1) << 5) +#define PIN_PB05A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PB05 External Interrupt Line */ +#define PIN_PB21A_EIC_EXTINT5 _L_(53) /**< \brief EIC signal: EXTINT5 on PB21 mux A */ +#define MUX_PB21A_EIC_EXTINT5 _L_(0) +#define PINMUX_PB21A_EIC_EXTINT5 ((PIN_PB21A_EIC_EXTINT5 << 16) | MUX_PB21A_EIC_EXTINT5) +#define PORT_PB21A_EIC_EXTINT5 (_UL_(1) << 21) +#define PIN_PB21A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PB21 External Interrupt Line */ +#define PIN_PC05A_EIC_EXTINT5 _L_(69) /**< \brief EIC signal: EXTINT5 on PC05 mux A */ +#define MUX_PC05A_EIC_EXTINT5 _L_(0) +#define PINMUX_PC05A_EIC_EXTINT5 ((PIN_PC05A_EIC_EXTINT5 << 16) | MUX_PC05A_EIC_EXTINT5) +#define PORT_PC05A_EIC_EXTINT5 (_UL_(1) << 5) +#define PIN_PC05A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PC05 External Interrupt Line */ +#define PIN_PC21A_EIC_EXTINT5 _L_(85) /**< \brief EIC signal: EXTINT5 on PC21 mux A */ +#define MUX_PC21A_EIC_EXTINT5 _L_(0) +#define PINMUX_PC21A_EIC_EXTINT5 ((PIN_PC21A_EIC_EXTINT5 << 16) | MUX_PC21A_EIC_EXTINT5) +#define PORT_PC21A_EIC_EXTINT5 (_UL_(1) << 21) +#define PIN_PC21A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PC21 External Interrupt Line */ +#define PIN_PD10A_EIC_EXTINT5 _L_(106) /**< \brief EIC signal: EXTINT5 on PD10 mux A */ +#define MUX_PD10A_EIC_EXTINT5 _L_(0) +#define PINMUX_PD10A_EIC_EXTINT5 ((PIN_PD10A_EIC_EXTINT5 << 16) | MUX_PD10A_EIC_EXTINT5) +#define PORT_PD10A_EIC_EXTINT5 (_UL_(1) << 10) +#define PIN_PD10A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PD10 External Interrupt Line */ +#define PIN_PA06A_EIC_EXTINT6 _L_(6) /**< \brief EIC signal: EXTINT6 on PA06 mux A */ +#define MUX_PA06A_EIC_EXTINT6 _L_(0) +#define PINMUX_PA06A_EIC_EXTINT6 ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6) +#define PORT_PA06A_EIC_EXTINT6 (_UL_(1) << 6) +#define PIN_PA06A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PA06 External Interrupt Line */ +#define PIN_PA22A_EIC_EXTINT6 _L_(22) /**< \brief EIC signal: EXTINT6 on PA22 mux A */ +#define MUX_PA22A_EIC_EXTINT6 _L_(0) +#define PINMUX_PA22A_EIC_EXTINT6 ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6) +#define PORT_PA22A_EIC_EXTINT6 (_UL_(1) << 22) +#define PIN_PA22A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PA22 External Interrupt Line */ +#define PIN_PB06A_EIC_EXTINT6 _L_(38) /**< \brief EIC signal: EXTINT6 on PB06 mux A */ +#define MUX_PB06A_EIC_EXTINT6 _L_(0) +#define PINMUX_PB06A_EIC_EXTINT6 ((PIN_PB06A_EIC_EXTINT6 << 16) | MUX_PB06A_EIC_EXTINT6) +#define PORT_PB06A_EIC_EXTINT6 (_UL_(1) << 6) +#define PIN_PB06A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PB06 External Interrupt Line */ +#define PIN_PB22A_EIC_EXTINT6 _L_(54) /**< \brief EIC signal: EXTINT6 on PB22 mux A */ +#define MUX_PB22A_EIC_EXTINT6 _L_(0) +#define PINMUX_PB22A_EIC_EXTINT6 ((PIN_PB22A_EIC_EXTINT6 << 16) | MUX_PB22A_EIC_EXTINT6) +#define PORT_PB22A_EIC_EXTINT6 (_UL_(1) << 22) +#define PIN_PB22A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PB22 External Interrupt Line */ +#define PIN_PC06A_EIC_EXTINT6 _L_(70) /**< \brief EIC signal: EXTINT6 on PC06 mux A */ +#define MUX_PC06A_EIC_EXTINT6 _L_(0) +#define PINMUX_PC06A_EIC_EXTINT6 ((PIN_PC06A_EIC_EXTINT6 << 16) | MUX_PC06A_EIC_EXTINT6) +#define PORT_PC06A_EIC_EXTINT6 (_UL_(1) << 6) +#define PIN_PC06A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PC06 External Interrupt Line */ +#define PIN_PC22A_EIC_EXTINT6 _L_(86) /**< \brief EIC signal: EXTINT6 on PC22 mux A */ +#define MUX_PC22A_EIC_EXTINT6 _L_(0) +#define PINMUX_PC22A_EIC_EXTINT6 ((PIN_PC22A_EIC_EXTINT6 << 16) | MUX_PC22A_EIC_EXTINT6) +#define PORT_PC22A_EIC_EXTINT6 (_UL_(1) << 22) +#define PIN_PC22A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PC22 External Interrupt Line */ +#define PIN_PD11A_EIC_EXTINT6 _L_(107) /**< \brief EIC signal: EXTINT6 on PD11 mux A */ +#define MUX_PD11A_EIC_EXTINT6 _L_(0) +#define PINMUX_PD11A_EIC_EXTINT6 ((PIN_PD11A_EIC_EXTINT6 << 16) | MUX_PD11A_EIC_EXTINT6) +#define PORT_PD11A_EIC_EXTINT6 (_UL_(1) << 11) +#define PIN_PD11A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PD11 External Interrupt Line */ +#define PIN_PA07A_EIC_EXTINT7 _L_(7) /**< \brief EIC signal: EXTINT7 on PA07 mux A */ +#define MUX_PA07A_EIC_EXTINT7 _L_(0) +#define PINMUX_PA07A_EIC_EXTINT7 ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7) +#define PORT_PA07A_EIC_EXTINT7 (_UL_(1) << 7) +#define PIN_PA07A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PA07 External Interrupt Line */ +#define PIN_PA23A_EIC_EXTINT7 _L_(23) /**< \brief EIC signal: EXTINT7 on PA23 mux A */ +#define MUX_PA23A_EIC_EXTINT7 _L_(0) +#define PINMUX_PA23A_EIC_EXTINT7 ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7) +#define PORT_PA23A_EIC_EXTINT7 (_UL_(1) << 23) +#define PIN_PA23A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PA23 External Interrupt Line */ +#define PIN_PB07A_EIC_EXTINT7 _L_(39) /**< \brief EIC signal: EXTINT7 on PB07 mux A */ +#define MUX_PB07A_EIC_EXTINT7 _L_(0) +#define PINMUX_PB07A_EIC_EXTINT7 ((PIN_PB07A_EIC_EXTINT7 << 16) | MUX_PB07A_EIC_EXTINT7) +#define PORT_PB07A_EIC_EXTINT7 (_UL_(1) << 7) +#define PIN_PB07A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PB07 External Interrupt Line */ +#define PIN_PB23A_EIC_EXTINT7 _L_(55) /**< \brief EIC signal: EXTINT7 on PB23 mux A */ +#define MUX_PB23A_EIC_EXTINT7 _L_(0) +#define PINMUX_PB23A_EIC_EXTINT7 ((PIN_PB23A_EIC_EXTINT7 << 16) | MUX_PB23A_EIC_EXTINT7) +#define PORT_PB23A_EIC_EXTINT7 (_UL_(1) << 23) +#define PIN_PB23A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PB23 External Interrupt Line */ +#define PIN_PC23A_EIC_EXTINT7 _L_(87) /**< \brief EIC signal: EXTINT7 on PC23 mux A */ +#define MUX_PC23A_EIC_EXTINT7 _L_(0) +#define PINMUX_PC23A_EIC_EXTINT7 ((PIN_PC23A_EIC_EXTINT7 << 16) | MUX_PC23A_EIC_EXTINT7) +#define PORT_PC23A_EIC_EXTINT7 (_UL_(1) << 23) +#define PIN_PC23A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PC23 External Interrupt Line */ +#define PIN_PD12A_EIC_EXTINT7 _L_(108) /**< \brief EIC signal: EXTINT7 on PD12 mux A */ +#define MUX_PD12A_EIC_EXTINT7 _L_(0) +#define PINMUX_PD12A_EIC_EXTINT7 ((PIN_PD12A_EIC_EXTINT7 << 16) | MUX_PD12A_EIC_EXTINT7) +#define PORT_PD12A_EIC_EXTINT7 (_UL_(1) << 12) +#define PIN_PD12A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PD12 External Interrupt Line */ +#define PIN_PA24A_EIC_EXTINT8 _L_(24) /**< \brief EIC signal: EXTINT8 on PA24 mux A */ +#define MUX_PA24A_EIC_EXTINT8 _L_(0) +#define PINMUX_PA24A_EIC_EXTINT8 ((PIN_PA24A_EIC_EXTINT8 << 16) | MUX_PA24A_EIC_EXTINT8) +#define PORT_PA24A_EIC_EXTINT8 (_UL_(1) << 24) +#define PIN_PA24A_EIC_EXTINT_NUM _L_(8) /**< \brief EIC signal: PIN_PA24 External Interrupt Line */ +#define PIN_PB08A_EIC_EXTINT8 _L_(40) /**< \brief EIC signal: EXTINT8 on PB08 mux A */ +#define MUX_PB08A_EIC_EXTINT8 _L_(0) +#define PINMUX_PB08A_EIC_EXTINT8 ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8) +#define PORT_PB08A_EIC_EXTINT8 (_UL_(1) << 8) +#define PIN_PB08A_EIC_EXTINT_NUM _L_(8) /**< \brief EIC signal: PIN_PB08 External Interrupt Line */ +#define PIN_PB24A_EIC_EXTINT8 _L_(56) /**< \brief EIC signal: EXTINT8 on PB24 mux A */ +#define MUX_PB24A_EIC_EXTINT8 _L_(0) +#define PINMUX_PB24A_EIC_EXTINT8 ((PIN_PB24A_EIC_EXTINT8 << 16) | MUX_PB24A_EIC_EXTINT8) +#define PORT_PB24A_EIC_EXTINT8 (_UL_(1) << 24) +#define PIN_PB24A_EIC_EXTINT_NUM _L_(8) /**< \brief EIC signal: PIN_PB24 External Interrupt Line */ +#define PIN_PC24A_EIC_EXTINT8 _L_(88) /**< \brief EIC signal: EXTINT8 on PC24 mux A */ +#define MUX_PC24A_EIC_EXTINT8 _L_(0) +#define PINMUX_PC24A_EIC_EXTINT8 ((PIN_PC24A_EIC_EXTINT8 << 16) | MUX_PC24A_EIC_EXTINT8) +#define PORT_PC24A_EIC_EXTINT8 (_UL_(1) << 24) +#define PIN_PC24A_EIC_EXTINT_NUM _L_(8) /**< \brief EIC signal: PIN_PC24 External Interrupt Line */ +#define PIN_PA09A_EIC_EXTINT9 _L_(9) /**< \brief EIC signal: EXTINT9 on PA09 mux A */ +#define MUX_PA09A_EIC_EXTINT9 _L_(0) +#define PINMUX_PA09A_EIC_EXTINT9 ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9) +#define PORT_PA09A_EIC_EXTINT9 (_UL_(1) << 9) +#define PIN_PA09A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PA09 External Interrupt Line */ +#define PIN_PA25A_EIC_EXTINT9 _L_(25) /**< \brief EIC signal: EXTINT9 on PA25 mux A */ +#define MUX_PA25A_EIC_EXTINT9 _L_(0) +#define PINMUX_PA25A_EIC_EXTINT9 ((PIN_PA25A_EIC_EXTINT9 << 16) | MUX_PA25A_EIC_EXTINT9) +#define PORT_PA25A_EIC_EXTINT9 (_UL_(1) << 25) +#define PIN_PA25A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PA25 External Interrupt Line */ +#define PIN_PB09A_EIC_EXTINT9 _L_(41) /**< \brief EIC signal: EXTINT9 on PB09 mux A */ +#define MUX_PB09A_EIC_EXTINT9 _L_(0) +#define PINMUX_PB09A_EIC_EXTINT9 ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9) +#define PORT_PB09A_EIC_EXTINT9 (_UL_(1) << 9) +#define PIN_PB09A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PB09 External Interrupt Line */ +#define PIN_PB25A_EIC_EXTINT9 _L_(57) /**< \brief EIC signal: EXTINT9 on PB25 mux A */ +#define MUX_PB25A_EIC_EXTINT9 _L_(0) +#define PINMUX_PB25A_EIC_EXTINT9 ((PIN_PB25A_EIC_EXTINT9 << 16) | MUX_PB25A_EIC_EXTINT9) +#define PORT_PB25A_EIC_EXTINT9 (_UL_(1) << 25) +#define PIN_PB25A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PB25 External Interrupt Line */ +#define PIN_PC07A_EIC_EXTINT9 _L_(71) /**< \brief EIC signal: EXTINT9 on PC07 mux A */ +#define MUX_PC07A_EIC_EXTINT9 _L_(0) +#define PINMUX_PC07A_EIC_EXTINT9 ((PIN_PC07A_EIC_EXTINT9 << 16) | MUX_PC07A_EIC_EXTINT9) +#define PORT_PC07A_EIC_EXTINT9 (_UL_(1) << 7) +#define PIN_PC07A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PC07 External Interrupt Line */ +#define PIN_PC25A_EIC_EXTINT9 _L_(89) /**< \brief EIC signal: EXTINT9 on PC25 mux A */ +#define MUX_PC25A_EIC_EXTINT9 _L_(0) +#define PINMUX_PC25A_EIC_EXTINT9 ((PIN_PC25A_EIC_EXTINT9 << 16) | MUX_PC25A_EIC_EXTINT9) +#define PORT_PC25A_EIC_EXTINT9 (_UL_(1) << 25) +#define PIN_PC25A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PC25 External Interrupt Line */ +#define PIN_PA10A_EIC_EXTINT10 _L_(10) /**< \brief EIC signal: EXTINT10 on PA10 mux A */ +#define MUX_PA10A_EIC_EXTINT10 _L_(0) +#define PINMUX_PA10A_EIC_EXTINT10 ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10) +#define PORT_PA10A_EIC_EXTINT10 (_UL_(1) << 10) +#define PIN_PA10A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PA10 External Interrupt Line */ +#define PIN_PB10A_EIC_EXTINT10 _L_(42) /**< \brief EIC signal: EXTINT10 on PB10 mux A */ +#define MUX_PB10A_EIC_EXTINT10 _L_(0) +#define PINMUX_PB10A_EIC_EXTINT10 ((PIN_PB10A_EIC_EXTINT10 << 16) | MUX_PB10A_EIC_EXTINT10) +#define PORT_PB10A_EIC_EXTINT10 (_UL_(1) << 10) +#define PIN_PB10A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PB10 External Interrupt Line */ +#define PIN_PC10A_EIC_EXTINT10 _L_(74) /**< \brief EIC signal: EXTINT10 on PC10 mux A */ +#define MUX_PC10A_EIC_EXTINT10 _L_(0) +#define PINMUX_PC10A_EIC_EXTINT10 ((PIN_PC10A_EIC_EXTINT10 << 16) | MUX_PC10A_EIC_EXTINT10) +#define PORT_PC10A_EIC_EXTINT10 (_UL_(1) << 10) +#define PIN_PC10A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PC10 External Interrupt Line */ +#define PIN_PC26A_EIC_EXTINT10 _L_(90) /**< \brief EIC signal: EXTINT10 on PC26 mux A */ +#define MUX_PC26A_EIC_EXTINT10 _L_(0) +#define PINMUX_PC26A_EIC_EXTINT10 ((PIN_PC26A_EIC_EXTINT10 << 16) | MUX_PC26A_EIC_EXTINT10) +#define PORT_PC26A_EIC_EXTINT10 (_UL_(1) << 26) +#define PIN_PC26A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PC26 External Interrupt Line */ +#define PIN_PD20A_EIC_EXTINT10 _L_(116) /**< \brief EIC signal: EXTINT10 on PD20 mux A */ +#define MUX_PD20A_EIC_EXTINT10 _L_(0) +#define PINMUX_PD20A_EIC_EXTINT10 ((PIN_PD20A_EIC_EXTINT10 << 16) | MUX_PD20A_EIC_EXTINT10) +#define PORT_PD20A_EIC_EXTINT10 (_UL_(1) << 20) +#define PIN_PD20A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PD20 External Interrupt Line */ +#define PIN_PA11A_EIC_EXTINT11 _L_(11) /**< \brief EIC signal: EXTINT11 on PA11 mux A */ +#define MUX_PA11A_EIC_EXTINT11 _L_(0) +#define PINMUX_PA11A_EIC_EXTINT11 ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11) +#define PORT_PA11A_EIC_EXTINT11 (_UL_(1) << 11) +#define PIN_PA11A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PA11 External Interrupt Line */ +#define PIN_PA27A_EIC_EXTINT11 _L_(27) /**< \brief EIC signal: EXTINT11 on PA27 mux A */ +#define MUX_PA27A_EIC_EXTINT11 _L_(0) +#define PINMUX_PA27A_EIC_EXTINT11 ((PIN_PA27A_EIC_EXTINT11 << 16) | MUX_PA27A_EIC_EXTINT11) +#define PORT_PA27A_EIC_EXTINT11 (_UL_(1) << 27) +#define PIN_PA27A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PA27 External Interrupt Line */ +#define PIN_PB11A_EIC_EXTINT11 _L_(43) /**< \brief EIC signal: EXTINT11 on PB11 mux A */ +#define MUX_PB11A_EIC_EXTINT11 _L_(0) +#define PINMUX_PB11A_EIC_EXTINT11 ((PIN_PB11A_EIC_EXTINT11 << 16) | MUX_PB11A_EIC_EXTINT11) +#define PORT_PB11A_EIC_EXTINT11 (_UL_(1) << 11) +#define PIN_PB11A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PB11 External Interrupt Line */ +#define PIN_PC11A_EIC_EXTINT11 _L_(75) /**< \brief EIC signal: EXTINT11 on PC11 mux A */ +#define MUX_PC11A_EIC_EXTINT11 _L_(0) +#define PINMUX_PC11A_EIC_EXTINT11 ((PIN_PC11A_EIC_EXTINT11 << 16) | MUX_PC11A_EIC_EXTINT11) +#define PORT_PC11A_EIC_EXTINT11 (_UL_(1) << 11) +#define PIN_PC11A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PC11 External Interrupt Line */ +#define PIN_PC27A_EIC_EXTINT11 _L_(91) /**< \brief EIC signal: EXTINT11 on PC27 mux A */ +#define MUX_PC27A_EIC_EXTINT11 _L_(0) +#define PINMUX_PC27A_EIC_EXTINT11 ((PIN_PC27A_EIC_EXTINT11 << 16) | MUX_PC27A_EIC_EXTINT11) +#define PORT_PC27A_EIC_EXTINT11 (_UL_(1) << 27) +#define PIN_PC27A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PC27 External Interrupt Line */ +#define PIN_PD21A_EIC_EXTINT11 _L_(117) /**< \brief EIC signal: EXTINT11 on PD21 mux A */ +#define MUX_PD21A_EIC_EXTINT11 _L_(0) +#define PINMUX_PD21A_EIC_EXTINT11 ((PIN_PD21A_EIC_EXTINT11 << 16) | MUX_PD21A_EIC_EXTINT11) +#define PORT_PD21A_EIC_EXTINT11 (_UL_(1) << 21) +#define PIN_PD21A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PD21 External Interrupt Line */ +#define PIN_PA12A_EIC_EXTINT12 _L_(12) /**< \brief EIC signal: EXTINT12 on PA12 mux A */ +#define MUX_PA12A_EIC_EXTINT12 _L_(0) +#define PINMUX_PA12A_EIC_EXTINT12 ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12) +#define PORT_PA12A_EIC_EXTINT12 (_UL_(1) << 12) +#define PIN_PA12A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PA12 External Interrupt Line */ +#define PIN_PB12A_EIC_EXTINT12 _L_(44) /**< \brief EIC signal: EXTINT12 on PB12 mux A */ +#define MUX_PB12A_EIC_EXTINT12 _L_(0) +#define PINMUX_PB12A_EIC_EXTINT12 ((PIN_PB12A_EIC_EXTINT12 << 16) | MUX_PB12A_EIC_EXTINT12) +#define PORT_PB12A_EIC_EXTINT12 (_UL_(1) << 12) +#define PIN_PB12A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PB12 External Interrupt Line */ +#define PIN_PB26A_EIC_EXTINT12 _L_(58) /**< \brief EIC signal: EXTINT12 on PB26 mux A */ +#define MUX_PB26A_EIC_EXTINT12 _L_(0) +#define PINMUX_PB26A_EIC_EXTINT12 ((PIN_PB26A_EIC_EXTINT12 << 16) | MUX_PB26A_EIC_EXTINT12) +#define PORT_PB26A_EIC_EXTINT12 (_UL_(1) << 26) +#define PIN_PB26A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PB26 External Interrupt Line */ +#define PIN_PC12A_EIC_EXTINT12 _L_(76) /**< \brief EIC signal: EXTINT12 on PC12 mux A */ +#define MUX_PC12A_EIC_EXTINT12 _L_(0) +#define PINMUX_PC12A_EIC_EXTINT12 ((PIN_PC12A_EIC_EXTINT12 << 16) | MUX_PC12A_EIC_EXTINT12) +#define PORT_PC12A_EIC_EXTINT12 (_UL_(1) << 12) +#define PIN_PC12A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PC12 External Interrupt Line */ +#define PIN_PC28A_EIC_EXTINT12 _L_(92) /**< \brief EIC signal: EXTINT12 on PC28 mux A */ +#define MUX_PC28A_EIC_EXTINT12 _L_(0) +#define PINMUX_PC28A_EIC_EXTINT12 ((PIN_PC28A_EIC_EXTINT12 << 16) | MUX_PC28A_EIC_EXTINT12) +#define PORT_PC28A_EIC_EXTINT12 (_UL_(1) << 28) +#define PIN_PC28A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PC28 External Interrupt Line */ +#define PIN_PA13A_EIC_EXTINT13 _L_(13) /**< \brief EIC signal: EXTINT13 on PA13 mux A */ +#define MUX_PA13A_EIC_EXTINT13 _L_(0) +#define PINMUX_PA13A_EIC_EXTINT13 ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13) +#define PORT_PA13A_EIC_EXTINT13 (_UL_(1) << 13) +#define PIN_PA13A_EIC_EXTINT_NUM _L_(13) /**< \brief EIC signal: PIN_PA13 External Interrupt Line */ +#define PIN_PB13A_EIC_EXTINT13 _L_(45) /**< \brief EIC signal: EXTINT13 on PB13 mux A */ +#define MUX_PB13A_EIC_EXTINT13 _L_(0) +#define PINMUX_PB13A_EIC_EXTINT13 ((PIN_PB13A_EIC_EXTINT13 << 16) | MUX_PB13A_EIC_EXTINT13) +#define PORT_PB13A_EIC_EXTINT13 (_UL_(1) << 13) +#define PIN_PB13A_EIC_EXTINT_NUM _L_(13) /**< \brief EIC signal: PIN_PB13 External Interrupt Line */ +#define PIN_PB27A_EIC_EXTINT13 _L_(59) /**< \brief EIC signal: EXTINT13 on PB27 mux A */ +#define MUX_PB27A_EIC_EXTINT13 _L_(0) +#define PINMUX_PB27A_EIC_EXTINT13 ((PIN_PB27A_EIC_EXTINT13 << 16) | MUX_PB27A_EIC_EXTINT13) +#define PORT_PB27A_EIC_EXTINT13 (_UL_(1) << 27) +#define PIN_PB27A_EIC_EXTINT_NUM _L_(13) /**< \brief EIC signal: PIN_PB27 External Interrupt Line */ +#define PIN_PC13A_EIC_EXTINT13 _L_(77) /**< \brief EIC signal: EXTINT13 on PC13 mux A */ +#define MUX_PC13A_EIC_EXTINT13 _L_(0) +#define PINMUX_PC13A_EIC_EXTINT13 ((PIN_PC13A_EIC_EXTINT13 << 16) | MUX_PC13A_EIC_EXTINT13) +#define PORT_PC13A_EIC_EXTINT13 (_UL_(1) << 13) +#define PIN_PC13A_EIC_EXTINT_NUM _L_(13) /**< \brief EIC signal: PIN_PC13 External Interrupt Line */ +#define PIN_PA30A_EIC_EXTINT14 _L_(30) /**< \brief EIC signal: EXTINT14 on PA30 mux A */ +#define MUX_PA30A_EIC_EXTINT14 _L_(0) +#define PINMUX_PA30A_EIC_EXTINT14 ((PIN_PA30A_EIC_EXTINT14 << 16) | MUX_PA30A_EIC_EXTINT14) +#define PORT_PA30A_EIC_EXTINT14 (_UL_(1) << 30) +#define PIN_PA30A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PA30 External Interrupt Line */ +#define PIN_PB14A_EIC_EXTINT14 _L_(46) /**< \brief EIC signal: EXTINT14 on PB14 mux A */ +#define MUX_PB14A_EIC_EXTINT14 _L_(0) +#define PINMUX_PB14A_EIC_EXTINT14 ((PIN_PB14A_EIC_EXTINT14 << 16) | MUX_PB14A_EIC_EXTINT14) +#define PORT_PB14A_EIC_EXTINT14 (_UL_(1) << 14) +#define PIN_PB14A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PB14 External Interrupt Line */ +#define PIN_PB28A_EIC_EXTINT14 _L_(60) /**< \brief EIC signal: EXTINT14 on PB28 mux A */ +#define MUX_PB28A_EIC_EXTINT14 _L_(0) +#define PINMUX_PB28A_EIC_EXTINT14 ((PIN_PB28A_EIC_EXTINT14 << 16) | MUX_PB28A_EIC_EXTINT14) +#define PORT_PB28A_EIC_EXTINT14 (_UL_(1) << 28) +#define PIN_PB28A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PB28 External Interrupt Line */ +#define PIN_PB30A_EIC_EXTINT14 _L_(62) /**< \brief EIC signal: EXTINT14 on PB30 mux A */ +#define MUX_PB30A_EIC_EXTINT14 _L_(0) +#define PINMUX_PB30A_EIC_EXTINT14 ((PIN_PB30A_EIC_EXTINT14 << 16) | MUX_PB30A_EIC_EXTINT14) +#define PORT_PB30A_EIC_EXTINT14 (_UL_(1) << 30) +#define PIN_PB30A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PB30 External Interrupt Line */ +#define PIN_PC14A_EIC_EXTINT14 _L_(78) /**< \brief EIC signal: EXTINT14 on PC14 mux A */ +#define MUX_PC14A_EIC_EXTINT14 _L_(0) +#define PINMUX_PC14A_EIC_EXTINT14 ((PIN_PC14A_EIC_EXTINT14 << 16) | MUX_PC14A_EIC_EXTINT14) +#define PORT_PC14A_EIC_EXTINT14 (_UL_(1) << 14) +#define PIN_PC14A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PC14 External Interrupt Line */ +#define PIN_PC30A_EIC_EXTINT14 _L_(94) /**< \brief EIC signal: EXTINT14 on PC30 mux A */ +#define MUX_PC30A_EIC_EXTINT14 _L_(0) +#define PINMUX_PC30A_EIC_EXTINT14 ((PIN_PC30A_EIC_EXTINT14 << 16) | MUX_PC30A_EIC_EXTINT14) +#define PORT_PC30A_EIC_EXTINT14 (_UL_(1) << 30) +#define PIN_PC30A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PC30 External Interrupt Line */ +#define PIN_PA14A_EIC_EXTINT14 _L_(14) /**< \brief EIC signal: EXTINT14 on PA14 mux A */ +#define MUX_PA14A_EIC_EXTINT14 _L_(0) +#define PINMUX_PA14A_EIC_EXTINT14 ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14) +#define PORT_PA14A_EIC_EXTINT14 (_UL_(1) << 14) +#define PIN_PA14A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PA14 External Interrupt Line */ +#define PIN_PA15A_EIC_EXTINT15 _L_(15) /**< \brief EIC signal: EXTINT15 on PA15 mux A */ +#define MUX_PA15A_EIC_EXTINT15 _L_(0) +#define PINMUX_PA15A_EIC_EXTINT15 ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15) +#define PORT_PA15A_EIC_EXTINT15 (_UL_(1) << 15) +#define PIN_PA15A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PA15 External Interrupt Line */ +#define PIN_PA31A_EIC_EXTINT15 _L_(31) /**< \brief EIC signal: EXTINT15 on PA31 mux A */ +#define MUX_PA31A_EIC_EXTINT15 _L_(0) +#define PINMUX_PA31A_EIC_EXTINT15 ((PIN_PA31A_EIC_EXTINT15 << 16) | MUX_PA31A_EIC_EXTINT15) +#define PORT_PA31A_EIC_EXTINT15 (_UL_(1) << 31) +#define PIN_PA31A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PA31 External Interrupt Line */ +#define PIN_PB15A_EIC_EXTINT15 _L_(47) /**< \brief EIC signal: EXTINT15 on PB15 mux A */ +#define MUX_PB15A_EIC_EXTINT15 _L_(0) +#define PINMUX_PB15A_EIC_EXTINT15 ((PIN_PB15A_EIC_EXTINT15 << 16) | MUX_PB15A_EIC_EXTINT15) +#define PORT_PB15A_EIC_EXTINT15 (_UL_(1) << 15) +#define PIN_PB15A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PB15 External Interrupt Line */ +#define PIN_PB29A_EIC_EXTINT15 _L_(61) /**< \brief EIC signal: EXTINT15 on PB29 mux A */ +#define MUX_PB29A_EIC_EXTINT15 _L_(0) +#define PINMUX_PB29A_EIC_EXTINT15 ((PIN_PB29A_EIC_EXTINT15 << 16) | MUX_PB29A_EIC_EXTINT15) +#define PORT_PB29A_EIC_EXTINT15 (_UL_(1) << 29) +#define PIN_PB29A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PB29 External Interrupt Line */ +#define PIN_PB31A_EIC_EXTINT15 _L_(63) /**< \brief EIC signal: EXTINT15 on PB31 mux A */ +#define MUX_PB31A_EIC_EXTINT15 _L_(0) +#define PINMUX_PB31A_EIC_EXTINT15 ((PIN_PB31A_EIC_EXTINT15 << 16) | MUX_PB31A_EIC_EXTINT15) +#define PORT_PB31A_EIC_EXTINT15 (_UL_(1) << 31) +#define PIN_PB31A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PB31 External Interrupt Line */ +#define PIN_PC15A_EIC_EXTINT15 _L_(79) /**< \brief EIC signal: EXTINT15 on PC15 mux A */ +#define MUX_PC15A_EIC_EXTINT15 _L_(0) +#define PINMUX_PC15A_EIC_EXTINT15 ((PIN_PC15A_EIC_EXTINT15 << 16) | MUX_PC15A_EIC_EXTINT15) +#define PORT_PC15A_EIC_EXTINT15 (_UL_(1) << 15) +#define PIN_PC15A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PC15 External Interrupt Line */ +#define PIN_PC31A_EIC_EXTINT15 _L_(95) /**< \brief EIC signal: EXTINT15 on PC31 mux A */ +#define MUX_PC31A_EIC_EXTINT15 _L_(0) +#define PINMUX_PC31A_EIC_EXTINT15 ((PIN_PC31A_EIC_EXTINT15 << 16) | MUX_PC31A_EIC_EXTINT15) +#define PORT_PC31A_EIC_EXTINT15 (_UL_(1) << 31) +#define PIN_PC31A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PC31 External Interrupt Line */ +#define PIN_PA08A_EIC_NMI _L_(8) /**< \brief EIC signal: NMI on PA08 mux A */ +#define MUX_PA08A_EIC_NMI _L_(0) +#define PINMUX_PA08A_EIC_NMI ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI) +#define PORT_PA08A_EIC_NMI (_UL_(1) << 8) +/* ========== PORT definition for SERCOM0 peripheral ========== */ +#define PIN_PA04D_SERCOM0_PAD0 _L_(4) /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */ +#define MUX_PA04D_SERCOM0_PAD0 _L_(3) +#define PINMUX_PA04D_SERCOM0_PAD0 ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0) +#define PORT_PA04D_SERCOM0_PAD0 (_UL_(1) << 4) +#define PIN_PC17D_SERCOM0_PAD0 _L_(81) /**< \brief SERCOM0 signal: PAD0 on PC17 mux D */ +#define MUX_PC17D_SERCOM0_PAD0 _L_(3) +#define PINMUX_PC17D_SERCOM0_PAD0 ((PIN_PC17D_SERCOM0_PAD0 << 16) | MUX_PC17D_SERCOM0_PAD0) +#define PORT_PC17D_SERCOM0_PAD0 (_UL_(1) << 17) +#define PIN_PA08C_SERCOM0_PAD0 _L_(8) /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */ +#define MUX_PA08C_SERCOM0_PAD0 _L_(2) +#define PINMUX_PA08C_SERCOM0_PAD0 ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0) +#define PORT_PA08C_SERCOM0_PAD0 (_UL_(1) << 8) +#define PIN_PB24C_SERCOM0_PAD0 _L_(56) /**< \brief SERCOM0 signal: PAD0 on PB24 mux C */ +#define MUX_PB24C_SERCOM0_PAD0 _L_(2) +#define PINMUX_PB24C_SERCOM0_PAD0 ((PIN_PB24C_SERCOM0_PAD0 << 16) | MUX_PB24C_SERCOM0_PAD0) +#define PORT_PB24C_SERCOM0_PAD0 (_UL_(1) << 24) +#define PIN_PA05D_SERCOM0_PAD1 _L_(5) /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */ +#define MUX_PA05D_SERCOM0_PAD1 _L_(3) +#define PINMUX_PA05D_SERCOM0_PAD1 ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1) +#define PORT_PA05D_SERCOM0_PAD1 (_UL_(1) << 5) +#define PIN_PC16D_SERCOM0_PAD1 _L_(80) /**< \brief SERCOM0 signal: PAD1 on PC16 mux D */ +#define MUX_PC16D_SERCOM0_PAD1 _L_(3) +#define PINMUX_PC16D_SERCOM0_PAD1 ((PIN_PC16D_SERCOM0_PAD1 << 16) | MUX_PC16D_SERCOM0_PAD1) +#define PORT_PC16D_SERCOM0_PAD1 (_UL_(1) << 16) +#define PIN_PA09C_SERCOM0_PAD1 _L_(9) /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */ +#define MUX_PA09C_SERCOM0_PAD1 _L_(2) +#define PINMUX_PA09C_SERCOM0_PAD1 ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1) +#define PORT_PA09C_SERCOM0_PAD1 (_UL_(1) << 9) +#define PIN_PB25C_SERCOM0_PAD1 _L_(57) /**< \brief SERCOM0 signal: PAD1 on PB25 mux C */ +#define MUX_PB25C_SERCOM0_PAD1 _L_(2) +#define PINMUX_PB25C_SERCOM0_PAD1 ((PIN_PB25C_SERCOM0_PAD1 << 16) | MUX_PB25C_SERCOM0_PAD1) +#define PORT_PB25C_SERCOM0_PAD1 (_UL_(1) << 25) +#define PIN_PA06D_SERCOM0_PAD2 _L_(6) /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */ +#define MUX_PA06D_SERCOM0_PAD2 _L_(3) +#define PINMUX_PA06D_SERCOM0_PAD2 ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2) +#define PORT_PA06D_SERCOM0_PAD2 (_UL_(1) << 6) +#define PIN_PC18D_SERCOM0_PAD2 _L_(82) /**< \brief SERCOM0 signal: PAD2 on PC18 mux D */ +#define MUX_PC18D_SERCOM0_PAD2 _L_(3) +#define PINMUX_PC18D_SERCOM0_PAD2 ((PIN_PC18D_SERCOM0_PAD2 << 16) | MUX_PC18D_SERCOM0_PAD2) +#define PORT_PC18D_SERCOM0_PAD2 (_UL_(1) << 18) +#define PIN_PA10C_SERCOM0_PAD2 _L_(10) /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */ +#define MUX_PA10C_SERCOM0_PAD2 _L_(2) +#define PINMUX_PA10C_SERCOM0_PAD2 ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2) +#define PORT_PA10C_SERCOM0_PAD2 (_UL_(1) << 10) +#define PIN_PC24C_SERCOM0_PAD2 _L_(88) /**< \brief SERCOM0 signal: PAD2 on PC24 mux C */ +#define MUX_PC24C_SERCOM0_PAD2 _L_(2) +#define PINMUX_PC24C_SERCOM0_PAD2 ((PIN_PC24C_SERCOM0_PAD2 << 16) | MUX_PC24C_SERCOM0_PAD2) +#define PORT_PC24C_SERCOM0_PAD2 (_UL_(1) << 24) +#define PIN_PA07D_SERCOM0_PAD3 _L_(7) /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */ +#define MUX_PA07D_SERCOM0_PAD3 _L_(3) +#define PINMUX_PA07D_SERCOM0_PAD3 ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3) +#define PORT_PA07D_SERCOM0_PAD3 (_UL_(1) << 7) +#define PIN_PC19D_SERCOM0_PAD3 _L_(83) /**< \brief SERCOM0 signal: PAD3 on PC19 mux D */ +#define MUX_PC19D_SERCOM0_PAD3 _L_(3) +#define PINMUX_PC19D_SERCOM0_PAD3 ((PIN_PC19D_SERCOM0_PAD3 << 16) | MUX_PC19D_SERCOM0_PAD3) +#define PORT_PC19D_SERCOM0_PAD3 (_UL_(1) << 19) +#define PIN_PA11C_SERCOM0_PAD3 _L_(11) /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */ +#define MUX_PA11C_SERCOM0_PAD3 _L_(2) +#define PINMUX_PA11C_SERCOM0_PAD3 ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3) +#define PORT_PA11C_SERCOM0_PAD3 (_UL_(1) << 11) +#define PIN_PC25C_SERCOM0_PAD3 _L_(89) /**< \brief SERCOM0 signal: PAD3 on PC25 mux C */ +#define MUX_PC25C_SERCOM0_PAD3 _L_(2) +#define PINMUX_PC25C_SERCOM0_PAD3 ((PIN_PC25C_SERCOM0_PAD3 << 16) | MUX_PC25C_SERCOM0_PAD3) +#define PORT_PC25C_SERCOM0_PAD3 (_UL_(1) << 25) +/* ========== PORT definition for SERCOM1 peripheral ========== */ +#define PIN_PA00D_SERCOM1_PAD0 _L_(0) /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */ +#define MUX_PA00D_SERCOM1_PAD0 _L_(3) +#define PINMUX_PA00D_SERCOM1_PAD0 ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0) +#define PORT_PA00D_SERCOM1_PAD0 (_UL_(1) << 0) +#define PIN_PA16C_SERCOM1_PAD0 _L_(16) /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */ +#define MUX_PA16C_SERCOM1_PAD0 _L_(2) +#define PINMUX_PA16C_SERCOM1_PAD0 ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0) +#define PORT_PA16C_SERCOM1_PAD0 (_UL_(1) << 16) +#define PIN_PC22C_SERCOM1_PAD0 _L_(86) /**< \brief SERCOM1 signal: PAD0 on PC22 mux C */ +#define MUX_PC22C_SERCOM1_PAD0 _L_(2) +#define PINMUX_PC22C_SERCOM1_PAD0 ((PIN_PC22C_SERCOM1_PAD0 << 16) | MUX_PC22C_SERCOM1_PAD0) +#define PORT_PC22C_SERCOM1_PAD0 (_UL_(1) << 22) +#define PIN_PC27C_SERCOM1_PAD0 _L_(91) /**< \brief SERCOM1 signal: PAD0 on PC27 mux C */ +#define MUX_PC27C_SERCOM1_PAD0 _L_(2) +#define PINMUX_PC27C_SERCOM1_PAD0 ((PIN_PC27C_SERCOM1_PAD0 << 16) | MUX_PC27C_SERCOM1_PAD0) +#define PORT_PC27C_SERCOM1_PAD0 (_UL_(1) << 27) +#define PIN_PA01D_SERCOM1_PAD1 _L_(1) /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */ +#define MUX_PA01D_SERCOM1_PAD1 _L_(3) +#define PINMUX_PA01D_SERCOM1_PAD1 ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1) +#define PORT_PA01D_SERCOM1_PAD1 (_UL_(1) << 1) +#define PIN_PA17C_SERCOM1_PAD1 _L_(17) /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */ +#define MUX_PA17C_SERCOM1_PAD1 _L_(2) +#define PINMUX_PA17C_SERCOM1_PAD1 ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1) +#define PORT_PA17C_SERCOM1_PAD1 (_UL_(1) << 17) +#define PIN_PC23C_SERCOM1_PAD1 _L_(87) /**< \brief SERCOM1 signal: PAD1 on PC23 mux C */ +#define MUX_PC23C_SERCOM1_PAD1 _L_(2) +#define PINMUX_PC23C_SERCOM1_PAD1 ((PIN_PC23C_SERCOM1_PAD1 << 16) | MUX_PC23C_SERCOM1_PAD1) +#define PORT_PC23C_SERCOM1_PAD1 (_UL_(1) << 23) +#define PIN_PC28C_SERCOM1_PAD1 _L_(92) /**< \brief SERCOM1 signal: PAD1 on PC28 mux C */ +#define MUX_PC28C_SERCOM1_PAD1 _L_(2) +#define PINMUX_PC28C_SERCOM1_PAD1 ((PIN_PC28C_SERCOM1_PAD1 << 16) | MUX_PC28C_SERCOM1_PAD1) +#define PORT_PC28C_SERCOM1_PAD1 (_UL_(1) << 28) +#define PIN_PA30D_SERCOM1_PAD2 _L_(30) /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */ +#define MUX_PA30D_SERCOM1_PAD2 _L_(3) +#define PINMUX_PA30D_SERCOM1_PAD2 ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2) +#define PORT_PA30D_SERCOM1_PAD2 (_UL_(1) << 30) +#define PIN_PA18C_SERCOM1_PAD2 _L_(18) /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */ +#define MUX_PA18C_SERCOM1_PAD2 _L_(2) +#define PINMUX_PA18C_SERCOM1_PAD2 ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2) +#define PORT_PA18C_SERCOM1_PAD2 (_UL_(1) << 18) +#define PIN_PB22C_SERCOM1_PAD2 _L_(54) /**< \brief SERCOM1 signal: PAD2 on PB22 mux C */ +#define MUX_PB22C_SERCOM1_PAD2 _L_(2) +#define PINMUX_PB22C_SERCOM1_PAD2 ((PIN_PB22C_SERCOM1_PAD2 << 16) | MUX_PB22C_SERCOM1_PAD2) +#define PORT_PB22C_SERCOM1_PAD2 (_UL_(1) << 22) +#define PIN_PD20C_SERCOM1_PAD2 _L_(116) /**< \brief SERCOM1 signal: PAD2 on PD20 mux C */ +#define MUX_PD20C_SERCOM1_PAD2 _L_(2) +#define PINMUX_PD20C_SERCOM1_PAD2 ((PIN_PD20C_SERCOM1_PAD2 << 16) | MUX_PD20C_SERCOM1_PAD2) +#define PORT_PD20C_SERCOM1_PAD2 (_UL_(1) << 20) +#define PIN_PA31D_SERCOM1_PAD3 _L_(31) /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */ +#define MUX_PA31D_SERCOM1_PAD3 _L_(3) +#define PINMUX_PA31D_SERCOM1_PAD3 ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3) +#define PORT_PA31D_SERCOM1_PAD3 (_UL_(1) << 31) +#define PIN_PA19C_SERCOM1_PAD3 _L_(19) /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */ +#define MUX_PA19C_SERCOM1_PAD3 _L_(2) +#define PINMUX_PA19C_SERCOM1_PAD3 ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3) +#define PORT_PA19C_SERCOM1_PAD3 (_UL_(1) << 19) +#define PIN_PB23C_SERCOM1_PAD3 _L_(55) /**< \brief SERCOM1 signal: PAD3 on PB23 mux C */ +#define MUX_PB23C_SERCOM1_PAD3 _L_(2) +#define PINMUX_PB23C_SERCOM1_PAD3 ((PIN_PB23C_SERCOM1_PAD3 << 16) | MUX_PB23C_SERCOM1_PAD3) +#define PORT_PB23C_SERCOM1_PAD3 (_UL_(1) << 23) +#define PIN_PD21C_SERCOM1_PAD3 _L_(117) /**< \brief SERCOM1 signal: PAD3 on PD21 mux C */ +#define MUX_PD21C_SERCOM1_PAD3 _L_(2) +#define PINMUX_PD21C_SERCOM1_PAD3 ((PIN_PD21C_SERCOM1_PAD3 << 16) | MUX_PD21C_SERCOM1_PAD3) +#define PORT_PD21C_SERCOM1_PAD3 (_UL_(1) << 21) +/* ========== PORT definition for TC0 peripheral ========== */ +#define PIN_PA04E_TC0_WO0 _L_(4) /**< \brief TC0 signal: WO0 on PA04 mux E */ +#define MUX_PA04E_TC0_WO0 _L_(4) +#define PINMUX_PA04E_TC0_WO0 ((PIN_PA04E_TC0_WO0 << 16) | MUX_PA04E_TC0_WO0) +#define PORT_PA04E_TC0_WO0 (_UL_(1) << 4) +#define PIN_PA08E_TC0_WO0 _L_(8) /**< \brief TC0 signal: WO0 on PA08 mux E */ +#define MUX_PA08E_TC0_WO0 _L_(4) +#define PINMUX_PA08E_TC0_WO0 ((PIN_PA08E_TC0_WO0 << 16) | MUX_PA08E_TC0_WO0) +#define PORT_PA08E_TC0_WO0 (_UL_(1) << 8) +#define PIN_PB30E_TC0_WO0 _L_(62) /**< \brief TC0 signal: WO0 on PB30 mux E */ +#define MUX_PB30E_TC0_WO0 _L_(4) +#define PINMUX_PB30E_TC0_WO0 ((PIN_PB30E_TC0_WO0 << 16) | MUX_PB30E_TC0_WO0) +#define PORT_PB30E_TC0_WO0 (_UL_(1) << 30) +#define PIN_PA05E_TC0_WO1 _L_(5) /**< \brief TC0 signal: WO1 on PA05 mux E */ +#define MUX_PA05E_TC0_WO1 _L_(4) +#define PINMUX_PA05E_TC0_WO1 ((PIN_PA05E_TC0_WO1 << 16) | MUX_PA05E_TC0_WO1) +#define PORT_PA05E_TC0_WO1 (_UL_(1) << 5) +#define PIN_PA09E_TC0_WO1 _L_(9) /**< \brief TC0 signal: WO1 on PA09 mux E */ +#define MUX_PA09E_TC0_WO1 _L_(4) +#define PINMUX_PA09E_TC0_WO1 ((PIN_PA09E_TC0_WO1 << 16) | MUX_PA09E_TC0_WO1) +#define PORT_PA09E_TC0_WO1 (_UL_(1) << 9) +#define PIN_PB31E_TC0_WO1 _L_(63) /**< \brief TC0 signal: WO1 on PB31 mux E */ +#define MUX_PB31E_TC0_WO1 _L_(4) +#define PINMUX_PB31E_TC0_WO1 ((PIN_PB31E_TC0_WO1 << 16) | MUX_PB31E_TC0_WO1) +#define PORT_PB31E_TC0_WO1 (_UL_(1) << 31) +/* ========== PORT definition for TC1 peripheral ========== */ +#define PIN_PA06E_TC1_WO0 _L_(6) /**< \brief TC1 signal: WO0 on PA06 mux E */ +#define MUX_PA06E_TC1_WO0 _L_(4) +#define PINMUX_PA06E_TC1_WO0 ((PIN_PA06E_TC1_WO0 << 16) | MUX_PA06E_TC1_WO0) +#define PORT_PA06E_TC1_WO0 (_UL_(1) << 6) +#define PIN_PA10E_TC1_WO0 _L_(10) /**< \brief TC1 signal: WO0 on PA10 mux E */ +#define MUX_PA10E_TC1_WO0 _L_(4) +#define PINMUX_PA10E_TC1_WO0 ((PIN_PA10E_TC1_WO0 << 16) | MUX_PA10E_TC1_WO0) +#define PORT_PA10E_TC1_WO0 (_UL_(1) << 10) +#define PIN_PA07E_TC1_WO1 _L_(7) /**< \brief TC1 signal: WO1 on PA07 mux E */ +#define MUX_PA07E_TC1_WO1 _L_(4) +#define PINMUX_PA07E_TC1_WO1 ((PIN_PA07E_TC1_WO1 << 16) | MUX_PA07E_TC1_WO1) +#define PORT_PA07E_TC1_WO1 (_UL_(1) << 7) +#define PIN_PA11E_TC1_WO1 _L_(11) /**< \brief TC1 signal: WO1 on PA11 mux E */ +#define MUX_PA11E_TC1_WO1 _L_(4) +#define PINMUX_PA11E_TC1_WO1 ((PIN_PA11E_TC1_WO1 << 16) | MUX_PA11E_TC1_WO1) +#define PORT_PA11E_TC1_WO1 (_UL_(1) << 11) +/* ========== PORT definition for USB peripheral ========== */ +#define PIN_PA24H_USB_DM _L_(24) /**< \brief USB signal: DM on PA24 mux H */ +#define MUX_PA24H_USB_DM _L_(7) +#define PINMUX_PA24H_USB_DM ((PIN_PA24H_USB_DM << 16) | MUX_PA24H_USB_DM) +#define PORT_PA24H_USB_DM (_UL_(1) << 24) +#define PIN_PA25H_USB_DP _L_(25) /**< \brief USB signal: DP on PA25 mux H */ +#define MUX_PA25H_USB_DP _L_(7) +#define PINMUX_PA25H_USB_DP ((PIN_PA25H_USB_DP << 16) | MUX_PA25H_USB_DP) +#define PORT_PA25H_USB_DP (_UL_(1) << 25) +#define PIN_PA23H_USB_SOF_1KHZ _L_(23) /**< \brief USB signal: SOF_1KHZ on PA23 mux H */ +#define MUX_PA23H_USB_SOF_1KHZ _L_(7) +#define PINMUX_PA23H_USB_SOF_1KHZ ((PIN_PA23H_USB_SOF_1KHZ << 16) | MUX_PA23H_USB_SOF_1KHZ) +#define PORT_PA23H_USB_SOF_1KHZ (_UL_(1) << 23) +#define PIN_PB22H_USB_SOF_1KHZ _L_(54) /**< \brief USB signal: SOF_1KHZ on PB22 mux H */ +#define MUX_PB22H_USB_SOF_1KHZ _L_(7) +#define PINMUX_PB22H_USB_SOF_1KHZ ((PIN_PB22H_USB_SOF_1KHZ << 16) | MUX_PB22H_USB_SOF_1KHZ) +#define PORT_PB22H_USB_SOF_1KHZ (_UL_(1) << 22) +/* ========== PORT definition for SERCOM2 peripheral ========== */ +#define PIN_PA09D_SERCOM2_PAD0 _L_(9) /**< \brief SERCOM2 signal: PAD0 on PA09 mux D */ +#define MUX_PA09D_SERCOM2_PAD0 _L_(3) +#define PINMUX_PA09D_SERCOM2_PAD0 ((PIN_PA09D_SERCOM2_PAD0 << 16) | MUX_PA09D_SERCOM2_PAD0) +#define PORT_PA09D_SERCOM2_PAD0 (_UL_(1) << 9) +#define PIN_PB25D_SERCOM2_PAD0 _L_(57) /**< \brief SERCOM2 signal: PAD0 on PB25 mux D */ +#define MUX_PB25D_SERCOM2_PAD0 _L_(3) +#define PINMUX_PB25D_SERCOM2_PAD0 ((PIN_PB25D_SERCOM2_PAD0 << 16) | MUX_PB25D_SERCOM2_PAD0) +#define PORT_PB25D_SERCOM2_PAD0 (_UL_(1) << 25) +#define PIN_PA12C_SERCOM2_PAD0 _L_(12) /**< \brief SERCOM2 signal: PAD0 on PA12 mux C */ +#define MUX_PA12C_SERCOM2_PAD0 _L_(2) +#define PINMUX_PA12C_SERCOM2_PAD0 ((PIN_PA12C_SERCOM2_PAD0 << 16) | MUX_PA12C_SERCOM2_PAD0) +#define PORT_PA12C_SERCOM2_PAD0 (_UL_(1) << 12) +#define PIN_PB26C_SERCOM2_PAD0 _L_(58) /**< \brief SERCOM2 signal: PAD0 on PB26 mux C */ +#define MUX_PB26C_SERCOM2_PAD0 _L_(2) +#define PINMUX_PB26C_SERCOM2_PAD0 ((PIN_PB26C_SERCOM2_PAD0 << 16) | MUX_PB26C_SERCOM2_PAD0) +#define PORT_PB26C_SERCOM2_PAD0 (_UL_(1) << 26) +#define PIN_PA08D_SERCOM2_PAD1 _L_(8) /**< \brief SERCOM2 signal: PAD1 on PA08 mux D */ +#define MUX_PA08D_SERCOM2_PAD1 _L_(3) +#define PINMUX_PA08D_SERCOM2_PAD1 ((PIN_PA08D_SERCOM2_PAD1 << 16) | MUX_PA08D_SERCOM2_PAD1) +#define PORT_PA08D_SERCOM2_PAD1 (_UL_(1) << 8) +#define PIN_PB24D_SERCOM2_PAD1 _L_(56) /**< \brief SERCOM2 signal: PAD1 on PB24 mux D */ +#define MUX_PB24D_SERCOM2_PAD1 _L_(3) +#define PINMUX_PB24D_SERCOM2_PAD1 ((PIN_PB24D_SERCOM2_PAD1 << 16) | MUX_PB24D_SERCOM2_PAD1) +#define PORT_PB24D_SERCOM2_PAD1 (_UL_(1) << 24) +#define PIN_PA13C_SERCOM2_PAD1 _L_(13) /**< \brief SERCOM2 signal: PAD1 on PA13 mux C */ +#define MUX_PA13C_SERCOM2_PAD1 _L_(2) +#define PINMUX_PA13C_SERCOM2_PAD1 ((PIN_PA13C_SERCOM2_PAD1 << 16) | MUX_PA13C_SERCOM2_PAD1) +#define PORT_PA13C_SERCOM2_PAD1 (_UL_(1) << 13) +#define PIN_PB27C_SERCOM2_PAD1 _L_(59) /**< \brief SERCOM2 signal: PAD1 on PB27 mux C */ +#define MUX_PB27C_SERCOM2_PAD1 _L_(2) +#define PINMUX_PB27C_SERCOM2_PAD1 ((PIN_PB27C_SERCOM2_PAD1 << 16) | MUX_PB27C_SERCOM2_PAD1) +#define PORT_PB27C_SERCOM2_PAD1 (_UL_(1) << 27) +#define PIN_PA10D_SERCOM2_PAD2 _L_(10) /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */ +#define MUX_PA10D_SERCOM2_PAD2 _L_(3) +#define PINMUX_PA10D_SERCOM2_PAD2 ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2) +#define PORT_PA10D_SERCOM2_PAD2 (_UL_(1) << 10) +#define PIN_PC24D_SERCOM2_PAD2 _L_(88) /**< \brief SERCOM2 signal: PAD2 on PC24 mux D */ +#define MUX_PC24D_SERCOM2_PAD2 _L_(3) +#define PINMUX_PC24D_SERCOM2_PAD2 ((PIN_PC24D_SERCOM2_PAD2 << 16) | MUX_PC24D_SERCOM2_PAD2) +#define PORT_PC24D_SERCOM2_PAD2 (_UL_(1) << 24) +#define PIN_PB28C_SERCOM2_PAD2 _L_(60) /**< \brief SERCOM2 signal: PAD2 on PB28 mux C */ +#define MUX_PB28C_SERCOM2_PAD2 _L_(2) +#define PINMUX_PB28C_SERCOM2_PAD2 ((PIN_PB28C_SERCOM2_PAD2 << 16) | MUX_PB28C_SERCOM2_PAD2) +#define PORT_PB28C_SERCOM2_PAD2 (_UL_(1) << 28) +#define PIN_PA14C_SERCOM2_PAD2 _L_(14) /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */ +#define MUX_PA14C_SERCOM2_PAD2 _L_(2) +#define PINMUX_PA14C_SERCOM2_PAD2 ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2) +#define PORT_PA14C_SERCOM2_PAD2 (_UL_(1) << 14) +#define PIN_PA11D_SERCOM2_PAD3 _L_(11) /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */ +#define MUX_PA11D_SERCOM2_PAD3 _L_(3) +#define PINMUX_PA11D_SERCOM2_PAD3 ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3) +#define PORT_PA11D_SERCOM2_PAD3 (_UL_(1) << 11) +#define PIN_PC25D_SERCOM2_PAD3 _L_(89) /**< \brief SERCOM2 signal: PAD3 on PC25 mux D */ +#define MUX_PC25D_SERCOM2_PAD3 _L_(3) +#define PINMUX_PC25D_SERCOM2_PAD3 ((PIN_PC25D_SERCOM2_PAD3 << 16) | MUX_PC25D_SERCOM2_PAD3) +#define PORT_PC25D_SERCOM2_PAD3 (_UL_(1) << 25) +#define PIN_PB29C_SERCOM2_PAD3 _L_(61) /**< \brief SERCOM2 signal: PAD3 on PB29 mux C */ +#define MUX_PB29C_SERCOM2_PAD3 _L_(2) +#define PINMUX_PB29C_SERCOM2_PAD3 ((PIN_PB29C_SERCOM2_PAD3 << 16) | MUX_PB29C_SERCOM2_PAD3) +#define PORT_PB29C_SERCOM2_PAD3 (_UL_(1) << 29) +#define PIN_PA15C_SERCOM2_PAD3 _L_(15) /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */ +#define MUX_PA15C_SERCOM2_PAD3 _L_(2) +#define PINMUX_PA15C_SERCOM2_PAD3 ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3) +#define PORT_PA15C_SERCOM2_PAD3 (_UL_(1) << 15) +/* ========== PORT definition for SERCOM3 peripheral ========== */ +#define PIN_PA17D_SERCOM3_PAD0 _L_(17) /**< \brief SERCOM3 signal: PAD0 on PA17 mux D */ +#define MUX_PA17D_SERCOM3_PAD0 _L_(3) +#define PINMUX_PA17D_SERCOM3_PAD0 ((PIN_PA17D_SERCOM3_PAD0 << 16) | MUX_PA17D_SERCOM3_PAD0) +#define PORT_PA17D_SERCOM3_PAD0 (_UL_(1) << 17) +#define PIN_PC23D_SERCOM3_PAD0 _L_(87) /**< \brief SERCOM3 signal: PAD0 on PC23 mux D */ +#define MUX_PC23D_SERCOM3_PAD0 _L_(3) +#define PINMUX_PC23D_SERCOM3_PAD0 ((PIN_PC23D_SERCOM3_PAD0 << 16) | MUX_PC23D_SERCOM3_PAD0) +#define PORT_PC23D_SERCOM3_PAD0 (_UL_(1) << 23) +#define PIN_PA22C_SERCOM3_PAD0 _L_(22) /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */ +#define MUX_PA22C_SERCOM3_PAD0 _L_(2) +#define PINMUX_PA22C_SERCOM3_PAD0 ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0) +#define PORT_PA22C_SERCOM3_PAD0 (_UL_(1) << 22) +#define PIN_PB20C_SERCOM3_PAD0 _L_(52) /**< \brief SERCOM3 signal: PAD0 on PB20 mux C */ +#define MUX_PB20C_SERCOM3_PAD0 _L_(2) +#define PINMUX_PB20C_SERCOM3_PAD0 ((PIN_PB20C_SERCOM3_PAD0 << 16) | MUX_PB20C_SERCOM3_PAD0) +#define PORT_PB20C_SERCOM3_PAD0 (_UL_(1) << 20) +#define PIN_PA16D_SERCOM3_PAD1 _L_(16) /**< \brief SERCOM3 signal: PAD1 on PA16 mux D */ +#define MUX_PA16D_SERCOM3_PAD1 _L_(3) +#define PINMUX_PA16D_SERCOM3_PAD1 ((PIN_PA16D_SERCOM3_PAD1 << 16) | MUX_PA16D_SERCOM3_PAD1) +#define PORT_PA16D_SERCOM3_PAD1 (_UL_(1) << 16) +#define PIN_PC22D_SERCOM3_PAD1 _L_(86) /**< \brief SERCOM3 signal: PAD1 on PC22 mux D */ +#define MUX_PC22D_SERCOM3_PAD1 _L_(3) +#define PINMUX_PC22D_SERCOM3_PAD1 ((PIN_PC22D_SERCOM3_PAD1 << 16) | MUX_PC22D_SERCOM3_PAD1) +#define PORT_PC22D_SERCOM3_PAD1 (_UL_(1) << 22) +#define PIN_PA23C_SERCOM3_PAD1 _L_(23) /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */ +#define MUX_PA23C_SERCOM3_PAD1 _L_(2) +#define PINMUX_PA23C_SERCOM3_PAD1 ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1) +#define PORT_PA23C_SERCOM3_PAD1 (_UL_(1) << 23) +#define PIN_PB21C_SERCOM3_PAD1 _L_(53) /**< \brief SERCOM3 signal: PAD1 on PB21 mux C */ +#define MUX_PB21C_SERCOM3_PAD1 _L_(2) +#define PINMUX_PB21C_SERCOM3_PAD1 ((PIN_PB21C_SERCOM3_PAD1 << 16) | MUX_PB21C_SERCOM3_PAD1) +#define PORT_PB21C_SERCOM3_PAD1 (_UL_(1) << 21) +#define PIN_PA18D_SERCOM3_PAD2 _L_(18) /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */ +#define MUX_PA18D_SERCOM3_PAD2 _L_(3) +#define PINMUX_PA18D_SERCOM3_PAD2 ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2) +#define PORT_PA18D_SERCOM3_PAD2 (_UL_(1) << 18) +#define PIN_PA20D_SERCOM3_PAD2 _L_(20) /**< \brief SERCOM3 signal: PAD2 on PA20 mux D */ +#define MUX_PA20D_SERCOM3_PAD2 _L_(3) +#define PINMUX_PA20D_SERCOM3_PAD2 ((PIN_PA20D_SERCOM3_PAD2 << 16) | MUX_PA20D_SERCOM3_PAD2) +#define PORT_PA20D_SERCOM3_PAD2 (_UL_(1) << 20) +#define PIN_PD20D_SERCOM3_PAD2 _L_(116) /**< \brief SERCOM3 signal: PAD2 on PD20 mux D */ +#define MUX_PD20D_SERCOM3_PAD2 _L_(3) +#define PINMUX_PD20D_SERCOM3_PAD2 ((PIN_PD20D_SERCOM3_PAD2 << 16) | MUX_PD20D_SERCOM3_PAD2) +#define PORT_PD20D_SERCOM3_PAD2 (_UL_(1) << 20) +#define PIN_PA24C_SERCOM3_PAD2 _L_(24) /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */ +#define MUX_PA24C_SERCOM3_PAD2 _L_(2) +#define PINMUX_PA24C_SERCOM3_PAD2 ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2) +#define PORT_PA24C_SERCOM3_PAD2 (_UL_(1) << 24) +#define PIN_PA19D_SERCOM3_PAD3 _L_(19) /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */ +#define MUX_PA19D_SERCOM3_PAD3 _L_(3) +#define PINMUX_PA19D_SERCOM3_PAD3 ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3) +#define PORT_PA19D_SERCOM3_PAD3 (_UL_(1) << 19) +#define PIN_PA21D_SERCOM3_PAD3 _L_(21) /**< \brief SERCOM3 signal: PAD3 on PA21 mux D */ +#define MUX_PA21D_SERCOM3_PAD3 _L_(3) +#define PINMUX_PA21D_SERCOM3_PAD3 ((PIN_PA21D_SERCOM3_PAD3 << 16) | MUX_PA21D_SERCOM3_PAD3) +#define PORT_PA21D_SERCOM3_PAD3 (_UL_(1) << 21) +#define PIN_PD21D_SERCOM3_PAD3 _L_(117) /**< \brief SERCOM3 signal: PAD3 on PD21 mux D */ +#define MUX_PD21D_SERCOM3_PAD3 _L_(3) +#define PINMUX_PD21D_SERCOM3_PAD3 ((PIN_PD21D_SERCOM3_PAD3 << 16) | MUX_PD21D_SERCOM3_PAD3) +#define PORT_PD21D_SERCOM3_PAD3 (_UL_(1) << 21) +#define PIN_PA25C_SERCOM3_PAD3 _L_(25) /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */ +#define MUX_PA25C_SERCOM3_PAD3 _L_(2) +#define PINMUX_PA25C_SERCOM3_PAD3 ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3) +#define PORT_PA25C_SERCOM3_PAD3 (_UL_(1) << 25) +/* ========== PORT definition for TCC0 peripheral ========== */ +#define PIN_PA20G_TCC0_WO0 _L_(20) /**< \brief TCC0 signal: WO0 on PA20 mux G */ +#define MUX_PA20G_TCC0_WO0 _L_(6) +#define PINMUX_PA20G_TCC0_WO0 ((PIN_PA20G_TCC0_WO0 << 16) | MUX_PA20G_TCC0_WO0) +#define PORT_PA20G_TCC0_WO0 (_UL_(1) << 20) +#define PIN_PB12G_TCC0_WO0 _L_(44) /**< \brief TCC0 signal: WO0 on PB12 mux G */ +#define MUX_PB12G_TCC0_WO0 _L_(6) +#define PINMUX_PB12G_TCC0_WO0 ((PIN_PB12G_TCC0_WO0 << 16) | MUX_PB12G_TCC0_WO0) +#define PORT_PB12G_TCC0_WO0 (_UL_(1) << 12) +#define PIN_PA08F_TCC0_WO0 _L_(8) /**< \brief TCC0 signal: WO0 on PA08 mux F */ +#define MUX_PA08F_TCC0_WO0 _L_(5) +#define PINMUX_PA08F_TCC0_WO0 ((PIN_PA08F_TCC0_WO0 << 16) | MUX_PA08F_TCC0_WO0) +#define PORT_PA08F_TCC0_WO0 (_UL_(1) << 8) +#define PIN_PC04F_TCC0_WO0 _L_(68) /**< \brief TCC0 signal: WO0 on PC04 mux F */ +#define MUX_PC04F_TCC0_WO0 _L_(5) +#define PINMUX_PC04F_TCC0_WO0 ((PIN_PC04F_TCC0_WO0 << 16) | MUX_PC04F_TCC0_WO0) +#define PORT_PC04F_TCC0_WO0 (_UL_(1) << 4) +#define PIN_PC10F_TCC0_WO0 _L_(74) /**< \brief TCC0 signal: WO0 on PC10 mux F */ +#define MUX_PC10F_TCC0_WO0 _L_(5) +#define PINMUX_PC10F_TCC0_WO0 ((PIN_PC10F_TCC0_WO0 << 16) | MUX_PC10F_TCC0_WO0) +#define PORT_PC10F_TCC0_WO0 (_UL_(1) << 10) +#define PIN_PC16F_TCC0_WO0 _L_(80) /**< \brief TCC0 signal: WO0 on PC16 mux F */ +#define MUX_PC16F_TCC0_WO0 _L_(5) +#define PINMUX_PC16F_TCC0_WO0 ((PIN_PC16F_TCC0_WO0 << 16) | MUX_PC16F_TCC0_WO0) +#define PORT_PC16F_TCC0_WO0 (_UL_(1) << 16) +#define PIN_PA21G_TCC0_WO1 _L_(21) /**< \brief TCC0 signal: WO1 on PA21 mux G */ +#define MUX_PA21G_TCC0_WO1 _L_(6) +#define PINMUX_PA21G_TCC0_WO1 ((PIN_PA21G_TCC0_WO1 << 16) | MUX_PA21G_TCC0_WO1) +#define PORT_PA21G_TCC0_WO1 (_UL_(1) << 21) +#define PIN_PB13G_TCC0_WO1 _L_(45) /**< \brief TCC0 signal: WO1 on PB13 mux G */ +#define MUX_PB13G_TCC0_WO1 _L_(6) +#define PINMUX_PB13G_TCC0_WO1 ((PIN_PB13G_TCC0_WO1 << 16) | MUX_PB13G_TCC0_WO1) +#define PORT_PB13G_TCC0_WO1 (_UL_(1) << 13) +#define PIN_PA09F_TCC0_WO1 _L_(9) /**< \brief TCC0 signal: WO1 on PA09 mux F */ +#define MUX_PA09F_TCC0_WO1 _L_(5) +#define PINMUX_PA09F_TCC0_WO1 ((PIN_PA09F_TCC0_WO1 << 16) | MUX_PA09F_TCC0_WO1) +#define PORT_PA09F_TCC0_WO1 (_UL_(1) << 9) +#define PIN_PC11F_TCC0_WO1 _L_(75) /**< \brief TCC0 signal: WO1 on PC11 mux F */ +#define MUX_PC11F_TCC0_WO1 _L_(5) +#define PINMUX_PC11F_TCC0_WO1 ((PIN_PC11F_TCC0_WO1 << 16) | MUX_PC11F_TCC0_WO1) +#define PORT_PC11F_TCC0_WO1 (_UL_(1) << 11) +#define PIN_PC17F_TCC0_WO1 _L_(81) /**< \brief TCC0 signal: WO1 on PC17 mux F */ +#define MUX_PC17F_TCC0_WO1 _L_(5) +#define PINMUX_PC17F_TCC0_WO1 ((PIN_PC17F_TCC0_WO1 << 16) | MUX_PC17F_TCC0_WO1) +#define PORT_PC17F_TCC0_WO1 (_UL_(1) << 17) +#define PIN_PD08F_TCC0_WO1 _L_(104) /**< \brief TCC0 signal: WO1 on PD08 mux F */ +#define MUX_PD08F_TCC0_WO1 _L_(5) +#define PINMUX_PD08F_TCC0_WO1 ((PIN_PD08F_TCC0_WO1 << 16) | MUX_PD08F_TCC0_WO1) +#define PORT_PD08F_TCC0_WO1 (_UL_(1) << 8) +#define PIN_PA22G_TCC0_WO2 _L_(22) /**< \brief TCC0 signal: WO2 on PA22 mux G */ +#define MUX_PA22G_TCC0_WO2 _L_(6) +#define PINMUX_PA22G_TCC0_WO2 ((PIN_PA22G_TCC0_WO2 << 16) | MUX_PA22G_TCC0_WO2) +#define PORT_PA22G_TCC0_WO2 (_UL_(1) << 22) +#define PIN_PB14G_TCC0_WO2 _L_(46) /**< \brief TCC0 signal: WO2 on PB14 mux G */ +#define MUX_PB14G_TCC0_WO2 _L_(6) +#define PINMUX_PB14G_TCC0_WO2 ((PIN_PB14G_TCC0_WO2 << 16) | MUX_PB14G_TCC0_WO2) +#define PORT_PB14G_TCC0_WO2 (_UL_(1) << 14) +#define PIN_PA10F_TCC0_WO2 _L_(10) /**< \brief TCC0 signal: WO2 on PA10 mux F */ +#define MUX_PA10F_TCC0_WO2 _L_(5) +#define PINMUX_PA10F_TCC0_WO2 ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2) +#define PORT_PA10F_TCC0_WO2 (_UL_(1) << 10) +#define PIN_PC12F_TCC0_WO2 _L_(76) /**< \brief TCC0 signal: WO2 on PC12 mux F */ +#define MUX_PC12F_TCC0_WO2 _L_(5) +#define PINMUX_PC12F_TCC0_WO2 ((PIN_PC12F_TCC0_WO2 << 16) | MUX_PC12F_TCC0_WO2) +#define PORT_PC12F_TCC0_WO2 (_UL_(1) << 12) +#define PIN_PC18F_TCC0_WO2 _L_(82) /**< \brief TCC0 signal: WO2 on PC18 mux F */ +#define MUX_PC18F_TCC0_WO2 _L_(5) +#define PINMUX_PC18F_TCC0_WO2 ((PIN_PC18F_TCC0_WO2 << 16) | MUX_PC18F_TCC0_WO2) +#define PORT_PC18F_TCC0_WO2 (_UL_(1) << 18) +#define PIN_PD09F_TCC0_WO2 _L_(105) /**< \brief TCC0 signal: WO2 on PD09 mux F */ +#define MUX_PD09F_TCC0_WO2 _L_(5) +#define PINMUX_PD09F_TCC0_WO2 ((PIN_PD09F_TCC0_WO2 << 16) | MUX_PD09F_TCC0_WO2) +#define PORT_PD09F_TCC0_WO2 (_UL_(1) << 9) +#define PIN_PA23G_TCC0_WO3 _L_(23) /**< \brief TCC0 signal: WO3 on PA23 mux G */ +#define MUX_PA23G_TCC0_WO3 _L_(6) +#define PINMUX_PA23G_TCC0_WO3 ((PIN_PA23G_TCC0_WO3 << 16) | MUX_PA23G_TCC0_WO3) +#define PORT_PA23G_TCC0_WO3 (_UL_(1) << 23) +#define PIN_PB15G_TCC0_WO3 _L_(47) /**< \brief TCC0 signal: WO3 on PB15 mux G */ +#define MUX_PB15G_TCC0_WO3 _L_(6) +#define PINMUX_PB15G_TCC0_WO3 ((PIN_PB15G_TCC0_WO3 << 16) | MUX_PB15G_TCC0_WO3) +#define PORT_PB15G_TCC0_WO3 (_UL_(1) << 15) +#define PIN_PA11F_TCC0_WO3 _L_(11) /**< \brief TCC0 signal: WO3 on PA11 mux F */ +#define MUX_PA11F_TCC0_WO3 _L_(5) +#define PINMUX_PA11F_TCC0_WO3 ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3) +#define PORT_PA11F_TCC0_WO3 (_UL_(1) << 11) +#define PIN_PC13F_TCC0_WO3 _L_(77) /**< \brief TCC0 signal: WO3 on PC13 mux F */ +#define MUX_PC13F_TCC0_WO3 _L_(5) +#define PINMUX_PC13F_TCC0_WO3 ((PIN_PC13F_TCC0_WO3 << 16) | MUX_PC13F_TCC0_WO3) +#define PORT_PC13F_TCC0_WO3 (_UL_(1) << 13) +#define PIN_PC19F_TCC0_WO3 _L_(83) /**< \brief TCC0 signal: WO3 on PC19 mux F */ +#define MUX_PC19F_TCC0_WO3 _L_(5) +#define PINMUX_PC19F_TCC0_WO3 ((PIN_PC19F_TCC0_WO3 << 16) | MUX_PC19F_TCC0_WO3) +#define PORT_PC19F_TCC0_WO3 (_UL_(1) << 19) +#define PIN_PD10F_TCC0_WO3 _L_(106) /**< \brief TCC0 signal: WO3 on PD10 mux F */ +#define MUX_PD10F_TCC0_WO3 _L_(5) +#define PINMUX_PD10F_TCC0_WO3 ((PIN_PD10F_TCC0_WO3 << 16) | MUX_PD10F_TCC0_WO3) +#define PORT_PD10F_TCC0_WO3 (_UL_(1) << 10) +#define PIN_PA16G_TCC0_WO4 _L_(16) /**< \brief TCC0 signal: WO4 on PA16 mux G */ +#define MUX_PA16G_TCC0_WO4 _L_(6) +#define PINMUX_PA16G_TCC0_WO4 ((PIN_PA16G_TCC0_WO4 << 16) | MUX_PA16G_TCC0_WO4) +#define PORT_PA16G_TCC0_WO4 (_UL_(1) << 16) +#define PIN_PB16G_TCC0_WO4 _L_(48) /**< \brief TCC0 signal: WO4 on PB16 mux G */ +#define MUX_PB16G_TCC0_WO4 _L_(6) +#define PINMUX_PB16G_TCC0_WO4 ((PIN_PB16G_TCC0_WO4 << 16) | MUX_PB16G_TCC0_WO4) +#define PORT_PB16G_TCC0_WO4 (_UL_(1) << 16) +#define PIN_PB10F_TCC0_WO4 _L_(42) /**< \brief TCC0 signal: WO4 on PB10 mux F */ +#define MUX_PB10F_TCC0_WO4 _L_(5) +#define PINMUX_PB10F_TCC0_WO4 ((PIN_PB10F_TCC0_WO4 << 16) | MUX_PB10F_TCC0_WO4) +#define PORT_PB10F_TCC0_WO4 (_UL_(1) << 10) +#define PIN_PC14F_TCC0_WO4 _L_(78) /**< \brief TCC0 signal: WO4 on PC14 mux F */ +#define MUX_PC14F_TCC0_WO4 _L_(5) +#define PINMUX_PC14F_TCC0_WO4 ((PIN_PC14F_TCC0_WO4 << 16) | MUX_PC14F_TCC0_WO4) +#define PORT_PC14F_TCC0_WO4 (_UL_(1) << 14) +#define PIN_PC20F_TCC0_WO4 _L_(84) /**< \brief TCC0 signal: WO4 on PC20 mux F */ +#define MUX_PC20F_TCC0_WO4 _L_(5) +#define PINMUX_PC20F_TCC0_WO4 ((PIN_PC20F_TCC0_WO4 << 16) | MUX_PC20F_TCC0_WO4) +#define PORT_PC20F_TCC0_WO4 (_UL_(1) << 20) +#define PIN_PD11F_TCC0_WO4 _L_(107) /**< \brief TCC0 signal: WO4 on PD11 mux F */ +#define MUX_PD11F_TCC0_WO4 _L_(5) +#define PINMUX_PD11F_TCC0_WO4 ((PIN_PD11F_TCC0_WO4 << 16) | MUX_PD11F_TCC0_WO4) +#define PORT_PD11F_TCC0_WO4 (_UL_(1) << 11) +#define PIN_PA17G_TCC0_WO5 _L_(17) /**< \brief TCC0 signal: WO5 on PA17 mux G */ +#define MUX_PA17G_TCC0_WO5 _L_(6) +#define PINMUX_PA17G_TCC0_WO5 ((PIN_PA17G_TCC0_WO5 << 16) | MUX_PA17G_TCC0_WO5) +#define PORT_PA17G_TCC0_WO5 (_UL_(1) << 17) +#define PIN_PB17G_TCC0_WO5 _L_(49) /**< \brief TCC0 signal: WO5 on PB17 mux G */ +#define MUX_PB17G_TCC0_WO5 _L_(6) +#define PINMUX_PB17G_TCC0_WO5 ((PIN_PB17G_TCC0_WO5 << 16) | MUX_PB17G_TCC0_WO5) +#define PORT_PB17G_TCC0_WO5 (_UL_(1) << 17) +#define PIN_PB11F_TCC0_WO5 _L_(43) /**< \brief TCC0 signal: WO5 on PB11 mux F */ +#define MUX_PB11F_TCC0_WO5 _L_(5) +#define PINMUX_PB11F_TCC0_WO5 ((PIN_PB11F_TCC0_WO5 << 16) | MUX_PB11F_TCC0_WO5) +#define PORT_PB11F_TCC0_WO5 (_UL_(1) << 11) +#define PIN_PC15F_TCC0_WO5 _L_(79) /**< \brief TCC0 signal: WO5 on PC15 mux F */ +#define MUX_PC15F_TCC0_WO5 _L_(5) +#define PINMUX_PC15F_TCC0_WO5 ((PIN_PC15F_TCC0_WO5 << 16) | MUX_PC15F_TCC0_WO5) +#define PORT_PC15F_TCC0_WO5 (_UL_(1) << 15) +#define PIN_PC21F_TCC0_WO5 _L_(85) /**< \brief TCC0 signal: WO5 on PC21 mux F */ +#define MUX_PC21F_TCC0_WO5 _L_(5) +#define PINMUX_PC21F_TCC0_WO5 ((PIN_PC21F_TCC0_WO5 << 16) | MUX_PC21F_TCC0_WO5) +#define PORT_PC21F_TCC0_WO5 (_UL_(1) << 21) +#define PIN_PD12F_TCC0_WO5 _L_(108) /**< \brief TCC0 signal: WO5 on PD12 mux F */ +#define MUX_PD12F_TCC0_WO5 _L_(5) +#define PINMUX_PD12F_TCC0_WO5 ((PIN_PD12F_TCC0_WO5 << 16) | MUX_PD12F_TCC0_WO5) +#define PORT_PD12F_TCC0_WO5 (_UL_(1) << 12) +#define PIN_PA18G_TCC0_WO6 _L_(18) /**< \brief TCC0 signal: WO6 on PA18 mux G */ +#define MUX_PA18G_TCC0_WO6 _L_(6) +#define PINMUX_PA18G_TCC0_WO6 ((PIN_PA18G_TCC0_WO6 << 16) | MUX_PA18G_TCC0_WO6) +#define PORT_PA18G_TCC0_WO6 (_UL_(1) << 18) +#define PIN_PB30G_TCC0_WO6 _L_(62) /**< \brief TCC0 signal: WO6 on PB30 mux G */ +#define MUX_PB30G_TCC0_WO6 _L_(6) +#define PINMUX_PB30G_TCC0_WO6 ((PIN_PB30G_TCC0_WO6 << 16) | MUX_PB30G_TCC0_WO6) +#define PORT_PB30G_TCC0_WO6 (_UL_(1) << 30) +#define PIN_PA12F_TCC0_WO6 _L_(12) /**< \brief TCC0 signal: WO6 on PA12 mux F */ +#define MUX_PA12F_TCC0_WO6 _L_(5) +#define PINMUX_PA12F_TCC0_WO6 ((PIN_PA12F_TCC0_WO6 << 16) | MUX_PA12F_TCC0_WO6) +#define PORT_PA12F_TCC0_WO6 (_UL_(1) << 12) +#define PIN_PC22F_TCC0_WO6 _L_(86) /**< \brief TCC0 signal: WO6 on PC22 mux F */ +#define MUX_PC22F_TCC0_WO6 _L_(5) +#define PINMUX_PC22F_TCC0_WO6 ((PIN_PC22F_TCC0_WO6 << 16) | MUX_PC22F_TCC0_WO6) +#define PORT_PC22F_TCC0_WO6 (_UL_(1) << 22) +#define PIN_PA19G_TCC0_WO7 _L_(19) /**< \brief TCC0 signal: WO7 on PA19 mux G */ +#define MUX_PA19G_TCC0_WO7 _L_(6) +#define PINMUX_PA19G_TCC0_WO7 ((PIN_PA19G_TCC0_WO7 << 16) | MUX_PA19G_TCC0_WO7) +#define PORT_PA19G_TCC0_WO7 (_UL_(1) << 19) +#define PIN_PB31G_TCC0_WO7 _L_(63) /**< \brief TCC0 signal: WO7 on PB31 mux G */ +#define MUX_PB31G_TCC0_WO7 _L_(6) +#define PINMUX_PB31G_TCC0_WO7 ((PIN_PB31G_TCC0_WO7 << 16) | MUX_PB31G_TCC0_WO7) +#define PORT_PB31G_TCC0_WO7 (_UL_(1) << 31) +#define PIN_PA13F_TCC0_WO7 _L_(13) /**< \brief TCC0 signal: WO7 on PA13 mux F */ +#define MUX_PA13F_TCC0_WO7 _L_(5) +#define PINMUX_PA13F_TCC0_WO7 ((PIN_PA13F_TCC0_WO7 << 16) | MUX_PA13F_TCC0_WO7) +#define PORT_PA13F_TCC0_WO7 (_UL_(1) << 13) +#define PIN_PC23F_TCC0_WO7 _L_(87) /**< \brief TCC0 signal: WO7 on PC23 mux F */ +#define MUX_PC23F_TCC0_WO7 _L_(5) +#define PINMUX_PC23F_TCC0_WO7 ((PIN_PC23F_TCC0_WO7 << 16) | MUX_PC23F_TCC0_WO7) +#define PORT_PC23F_TCC0_WO7 (_UL_(1) << 23) +/* ========== PORT definition for TCC1 peripheral ========== */ +#define PIN_PB10G_TCC1_WO0 _L_(42) /**< \brief TCC1 signal: WO0 on PB10 mux G */ +#define MUX_PB10G_TCC1_WO0 _L_(6) +#define PINMUX_PB10G_TCC1_WO0 ((PIN_PB10G_TCC1_WO0 << 16) | MUX_PB10G_TCC1_WO0) +#define PORT_PB10G_TCC1_WO0 (_UL_(1) << 10) +#define PIN_PC14G_TCC1_WO0 _L_(78) /**< \brief TCC1 signal: WO0 on PC14 mux G */ +#define MUX_PC14G_TCC1_WO0 _L_(6) +#define PINMUX_PC14G_TCC1_WO0 ((PIN_PC14G_TCC1_WO0 << 16) | MUX_PC14G_TCC1_WO0) +#define PORT_PC14G_TCC1_WO0 (_UL_(1) << 14) +#define PIN_PA16F_TCC1_WO0 _L_(16) /**< \brief TCC1 signal: WO0 on PA16 mux F */ +#define MUX_PA16F_TCC1_WO0 _L_(5) +#define PINMUX_PA16F_TCC1_WO0 ((PIN_PA16F_TCC1_WO0 << 16) | MUX_PA16F_TCC1_WO0) +#define PORT_PA16F_TCC1_WO0 (_UL_(1) << 16) +#define PIN_PB18F_TCC1_WO0 _L_(50) /**< \brief TCC1 signal: WO0 on PB18 mux F */ +#define MUX_PB18F_TCC1_WO0 _L_(5) +#define PINMUX_PB18F_TCC1_WO0 ((PIN_PB18F_TCC1_WO0 << 16) | MUX_PB18F_TCC1_WO0) +#define PORT_PB18F_TCC1_WO0 (_UL_(1) << 18) +#define PIN_PD20F_TCC1_WO0 _L_(116) /**< \brief TCC1 signal: WO0 on PD20 mux F */ +#define MUX_PD20F_TCC1_WO0 _L_(5) +#define PINMUX_PD20F_TCC1_WO0 ((PIN_PD20F_TCC1_WO0 << 16) | MUX_PD20F_TCC1_WO0) +#define PORT_PD20F_TCC1_WO0 (_UL_(1) << 20) +#define PIN_PB11G_TCC1_WO1 _L_(43) /**< \brief TCC1 signal: WO1 on PB11 mux G */ +#define MUX_PB11G_TCC1_WO1 _L_(6) +#define PINMUX_PB11G_TCC1_WO1 ((PIN_PB11G_TCC1_WO1 << 16) | MUX_PB11G_TCC1_WO1) +#define PORT_PB11G_TCC1_WO1 (_UL_(1) << 11) +#define PIN_PC15G_TCC1_WO1 _L_(79) /**< \brief TCC1 signal: WO1 on PC15 mux G */ +#define MUX_PC15G_TCC1_WO1 _L_(6) +#define PINMUX_PC15G_TCC1_WO1 ((PIN_PC15G_TCC1_WO1 << 16) | MUX_PC15G_TCC1_WO1) +#define PORT_PC15G_TCC1_WO1 (_UL_(1) << 15) +#define PIN_PA17F_TCC1_WO1 _L_(17) /**< \brief TCC1 signal: WO1 on PA17 mux F */ +#define MUX_PA17F_TCC1_WO1 _L_(5) +#define PINMUX_PA17F_TCC1_WO1 ((PIN_PA17F_TCC1_WO1 << 16) | MUX_PA17F_TCC1_WO1) +#define PORT_PA17F_TCC1_WO1 (_UL_(1) << 17) +#define PIN_PB19F_TCC1_WO1 _L_(51) /**< \brief TCC1 signal: WO1 on PB19 mux F */ +#define MUX_PB19F_TCC1_WO1 _L_(5) +#define PINMUX_PB19F_TCC1_WO1 ((PIN_PB19F_TCC1_WO1 << 16) | MUX_PB19F_TCC1_WO1) +#define PORT_PB19F_TCC1_WO1 (_UL_(1) << 19) +#define PIN_PD21F_TCC1_WO1 _L_(117) /**< \brief TCC1 signal: WO1 on PD21 mux F */ +#define MUX_PD21F_TCC1_WO1 _L_(5) +#define PINMUX_PD21F_TCC1_WO1 ((PIN_PD21F_TCC1_WO1 << 16) | MUX_PD21F_TCC1_WO1) +#define PORT_PD21F_TCC1_WO1 (_UL_(1) << 21) +#define PIN_PA12G_TCC1_WO2 _L_(12) /**< \brief TCC1 signal: WO2 on PA12 mux G */ +#define MUX_PA12G_TCC1_WO2 _L_(6) +#define PINMUX_PA12G_TCC1_WO2 ((PIN_PA12G_TCC1_WO2 << 16) | MUX_PA12G_TCC1_WO2) +#define PORT_PA12G_TCC1_WO2 (_UL_(1) << 12) +#define PIN_PA14G_TCC1_WO2 _L_(14) /**< \brief TCC1 signal: WO2 on PA14 mux G */ +#define MUX_PA14G_TCC1_WO2 _L_(6) +#define PINMUX_PA14G_TCC1_WO2 ((PIN_PA14G_TCC1_WO2 << 16) | MUX_PA14G_TCC1_WO2) +#define PORT_PA14G_TCC1_WO2 (_UL_(1) << 14) +#define PIN_PA18F_TCC1_WO2 _L_(18) /**< \brief TCC1 signal: WO2 on PA18 mux F */ +#define MUX_PA18F_TCC1_WO2 _L_(5) +#define PINMUX_PA18F_TCC1_WO2 ((PIN_PA18F_TCC1_WO2 << 16) | MUX_PA18F_TCC1_WO2) +#define PORT_PA18F_TCC1_WO2 (_UL_(1) << 18) +#define PIN_PB20F_TCC1_WO2 _L_(52) /**< \brief TCC1 signal: WO2 on PB20 mux F */ +#define MUX_PB20F_TCC1_WO2 _L_(5) +#define PINMUX_PB20F_TCC1_WO2 ((PIN_PB20F_TCC1_WO2 << 16) | MUX_PB20F_TCC1_WO2) +#define PORT_PB20F_TCC1_WO2 (_UL_(1) << 20) +#define PIN_PB26F_TCC1_WO2 _L_(58) /**< \brief TCC1 signal: WO2 on PB26 mux F */ +#define MUX_PB26F_TCC1_WO2 _L_(5) +#define PINMUX_PB26F_TCC1_WO2 ((PIN_PB26F_TCC1_WO2 << 16) | MUX_PB26F_TCC1_WO2) +#define PORT_PB26F_TCC1_WO2 (_UL_(1) << 26) +#define PIN_PA13G_TCC1_WO3 _L_(13) /**< \brief TCC1 signal: WO3 on PA13 mux G */ +#define MUX_PA13G_TCC1_WO3 _L_(6) +#define PINMUX_PA13G_TCC1_WO3 ((PIN_PA13G_TCC1_WO3 << 16) | MUX_PA13G_TCC1_WO3) +#define PORT_PA13G_TCC1_WO3 (_UL_(1) << 13) +#define PIN_PA15G_TCC1_WO3 _L_(15) /**< \brief TCC1 signal: WO3 on PA15 mux G */ +#define MUX_PA15G_TCC1_WO3 _L_(6) +#define PINMUX_PA15G_TCC1_WO3 ((PIN_PA15G_TCC1_WO3 << 16) | MUX_PA15G_TCC1_WO3) +#define PORT_PA15G_TCC1_WO3 (_UL_(1) << 15) +#define PIN_PA19F_TCC1_WO3 _L_(19) /**< \brief TCC1 signal: WO3 on PA19 mux F */ +#define MUX_PA19F_TCC1_WO3 _L_(5) +#define PINMUX_PA19F_TCC1_WO3 ((PIN_PA19F_TCC1_WO3 << 16) | MUX_PA19F_TCC1_WO3) +#define PORT_PA19F_TCC1_WO3 (_UL_(1) << 19) +#define PIN_PB21F_TCC1_WO3 _L_(53) /**< \brief TCC1 signal: WO3 on PB21 mux F */ +#define MUX_PB21F_TCC1_WO3 _L_(5) +#define PINMUX_PB21F_TCC1_WO3 ((PIN_PB21F_TCC1_WO3 << 16) | MUX_PB21F_TCC1_WO3) +#define PORT_PB21F_TCC1_WO3 (_UL_(1) << 21) +#define PIN_PB27F_TCC1_WO3 _L_(59) /**< \brief TCC1 signal: WO3 on PB27 mux F */ +#define MUX_PB27F_TCC1_WO3 _L_(5) +#define PINMUX_PB27F_TCC1_WO3 ((PIN_PB27F_TCC1_WO3 << 16) | MUX_PB27F_TCC1_WO3) +#define PORT_PB27F_TCC1_WO3 (_UL_(1) << 27) +#define PIN_PA08G_TCC1_WO4 _L_(8) /**< \brief TCC1 signal: WO4 on PA08 mux G */ +#define MUX_PA08G_TCC1_WO4 _L_(6) +#define PINMUX_PA08G_TCC1_WO4 ((PIN_PA08G_TCC1_WO4 << 16) | MUX_PA08G_TCC1_WO4) +#define PORT_PA08G_TCC1_WO4 (_UL_(1) << 8) +#define PIN_PC10G_TCC1_WO4 _L_(74) /**< \brief TCC1 signal: WO4 on PC10 mux G */ +#define MUX_PC10G_TCC1_WO4 _L_(6) +#define PINMUX_PC10G_TCC1_WO4 ((PIN_PC10G_TCC1_WO4 << 16) | MUX_PC10G_TCC1_WO4) +#define PORT_PC10G_TCC1_WO4 (_UL_(1) << 10) +#define PIN_PA20F_TCC1_WO4 _L_(20) /**< \brief TCC1 signal: WO4 on PA20 mux F */ +#define MUX_PA20F_TCC1_WO4 _L_(5) +#define PINMUX_PA20F_TCC1_WO4 ((PIN_PA20F_TCC1_WO4 << 16) | MUX_PA20F_TCC1_WO4) +#define PORT_PA20F_TCC1_WO4 (_UL_(1) << 20) +#define PIN_PB28F_TCC1_WO4 _L_(60) /**< \brief TCC1 signal: WO4 on PB28 mux F */ +#define MUX_PB28F_TCC1_WO4 _L_(5) +#define PINMUX_PB28F_TCC1_WO4 ((PIN_PB28F_TCC1_WO4 << 16) | MUX_PB28F_TCC1_WO4) +#define PORT_PB28F_TCC1_WO4 (_UL_(1) << 28) +#define PIN_PA09G_TCC1_WO5 _L_(9) /**< \brief TCC1 signal: WO5 on PA09 mux G */ +#define MUX_PA09G_TCC1_WO5 _L_(6) +#define PINMUX_PA09G_TCC1_WO5 ((PIN_PA09G_TCC1_WO5 << 16) | MUX_PA09G_TCC1_WO5) +#define PORT_PA09G_TCC1_WO5 (_UL_(1) << 9) +#define PIN_PC11G_TCC1_WO5 _L_(75) /**< \brief TCC1 signal: WO5 on PC11 mux G */ +#define MUX_PC11G_TCC1_WO5 _L_(6) +#define PINMUX_PC11G_TCC1_WO5 ((PIN_PC11G_TCC1_WO5 << 16) | MUX_PC11G_TCC1_WO5) +#define PORT_PC11G_TCC1_WO5 (_UL_(1) << 11) +#define PIN_PA21F_TCC1_WO5 _L_(21) /**< \brief TCC1 signal: WO5 on PA21 mux F */ +#define MUX_PA21F_TCC1_WO5 _L_(5) +#define PINMUX_PA21F_TCC1_WO5 ((PIN_PA21F_TCC1_WO5 << 16) | MUX_PA21F_TCC1_WO5) +#define PORT_PA21F_TCC1_WO5 (_UL_(1) << 21) +#define PIN_PB29F_TCC1_WO5 _L_(61) /**< \brief TCC1 signal: WO5 on PB29 mux F */ +#define MUX_PB29F_TCC1_WO5 _L_(5) +#define PINMUX_PB29F_TCC1_WO5 ((PIN_PB29F_TCC1_WO5 << 16) | MUX_PB29F_TCC1_WO5) +#define PORT_PB29F_TCC1_WO5 (_UL_(1) << 29) +#define PIN_PA10G_TCC1_WO6 _L_(10) /**< \brief TCC1 signal: WO6 on PA10 mux G */ +#define MUX_PA10G_TCC1_WO6 _L_(6) +#define PINMUX_PA10G_TCC1_WO6 ((PIN_PA10G_TCC1_WO6 << 16) | MUX_PA10G_TCC1_WO6) +#define PORT_PA10G_TCC1_WO6 (_UL_(1) << 10) +#define PIN_PC12G_TCC1_WO6 _L_(76) /**< \brief TCC1 signal: WO6 on PC12 mux G */ +#define MUX_PC12G_TCC1_WO6 _L_(6) +#define PINMUX_PC12G_TCC1_WO6 ((PIN_PC12G_TCC1_WO6 << 16) | MUX_PC12G_TCC1_WO6) +#define PORT_PC12G_TCC1_WO6 (_UL_(1) << 12) +#define PIN_PA22F_TCC1_WO6 _L_(22) /**< \brief TCC1 signal: WO6 on PA22 mux F */ +#define MUX_PA22F_TCC1_WO6 _L_(5) +#define PINMUX_PA22F_TCC1_WO6 ((PIN_PA22F_TCC1_WO6 << 16) | MUX_PA22F_TCC1_WO6) +#define PORT_PA22F_TCC1_WO6 (_UL_(1) << 22) +#define PIN_PA11G_TCC1_WO7 _L_(11) /**< \brief TCC1 signal: WO7 on PA11 mux G */ +#define MUX_PA11G_TCC1_WO7 _L_(6) +#define PINMUX_PA11G_TCC1_WO7 ((PIN_PA11G_TCC1_WO7 << 16) | MUX_PA11G_TCC1_WO7) +#define PORT_PA11G_TCC1_WO7 (_UL_(1) << 11) +#define PIN_PC13G_TCC1_WO7 _L_(77) /**< \brief TCC1 signal: WO7 on PC13 mux G */ +#define MUX_PC13G_TCC1_WO7 _L_(6) +#define PINMUX_PC13G_TCC1_WO7 ((PIN_PC13G_TCC1_WO7 << 16) | MUX_PC13G_TCC1_WO7) +#define PORT_PC13G_TCC1_WO7 (_UL_(1) << 13) +#define PIN_PA23F_TCC1_WO7 _L_(23) /**< \brief TCC1 signal: WO7 on PA23 mux F */ +#define MUX_PA23F_TCC1_WO7 _L_(5) +#define PINMUX_PA23F_TCC1_WO7 ((PIN_PA23F_TCC1_WO7 << 16) | MUX_PA23F_TCC1_WO7) +#define PORT_PA23F_TCC1_WO7 (_UL_(1) << 23) +/* ========== PORT definition for TC2 peripheral ========== */ +#define PIN_PA12E_TC2_WO0 _L_(12) /**< \brief TC2 signal: WO0 on PA12 mux E */ +#define MUX_PA12E_TC2_WO0 _L_(4) +#define PINMUX_PA12E_TC2_WO0 ((PIN_PA12E_TC2_WO0 << 16) | MUX_PA12E_TC2_WO0) +#define PORT_PA12E_TC2_WO0 (_UL_(1) << 12) +#define PIN_PA16E_TC2_WO0 _L_(16) /**< \brief TC2 signal: WO0 on PA16 mux E */ +#define MUX_PA16E_TC2_WO0 _L_(4) +#define PINMUX_PA16E_TC2_WO0 ((PIN_PA16E_TC2_WO0 << 16) | MUX_PA16E_TC2_WO0) +#define PORT_PA16E_TC2_WO0 (_UL_(1) << 16) +#define PIN_PA00E_TC2_WO0 _L_(0) /**< \brief TC2 signal: WO0 on PA00 mux E */ +#define MUX_PA00E_TC2_WO0 _L_(4) +#define PINMUX_PA00E_TC2_WO0 ((PIN_PA00E_TC2_WO0 << 16) | MUX_PA00E_TC2_WO0) +#define PORT_PA00E_TC2_WO0 (_UL_(1) << 0) +#define PIN_PA01E_TC2_WO1 _L_(1) /**< \brief TC2 signal: WO1 on PA01 mux E */ +#define MUX_PA01E_TC2_WO1 _L_(4) +#define PINMUX_PA01E_TC2_WO1 ((PIN_PA01E_TC2_WO1 << 16) | MUX_PA01E_TC2_WO1) +#define PORT_PA01E_TC2_WO1 (_UL_(1) << 1) +#define PIN_PA13E_TC2_WO1 _L_(13) /**< \brief TC2 signal: WO1 on PA13 mux E */ +#define MUX_PA13E_TC2_WO1 _L_(4) +#define PINMUX_PA13E_TC2_WO1 ((PIN_PA13E_TC2_WO1 << 16) | MUX_PA13E_TC2_WO1) +#define PORT_PA13E_TC2_WO1 (_UL_(1) << 13) +#define PIN_PA17E_TC2_WO1 _L_(17) /**< \brief TC2 signal: WO1 on PA17 mux E */ +#define MUX_PA17E_TC2_WO1 _L_(4) +#define PINMUX_PA17E_TC2_WO1 ((PIN_PA17E_TC2_WO1 << 16) | MUX_PA17E_TC2_WO1) +#define PORT_PA17E_TC2_WO1 (_UL_(1) << 17) +/* ========== PORT definition for TC3 peripheral ========== */ +#define PIN_PA18E_TC3_WO0 _L_(18) /**< \brief TC3 signal: WO0 on PA18 mux E */ +#define MUX_PA18E_TC3_WO0 _L_(4) +#define PINMUX_PA18E_TC3_WO0 ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0) +#define PORT_PA18E_TC3_WO0 (_UL_(1) << 18) +#define PIN_PA14E_TC3_WO0 _L_(14) /**< \brief TC3 signal: WO0 on PA14 mux E */ +#define MUX_PA14E_TC3_WO0 _L_(4) +#define PINMUX_PA14E_TC3_WO0 ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0) +#define PORT_PA14E_TC3_WO0 (_UL_(1) << 14) +#define PIN_PA15E_TC3_WO1 _L_(15) /**< \brief TC3 signal: WO1 on PA15 mux E */ +#define MUX_PA15E_TC3_WO1 _L_(4) +#define PINMUX_PA15E_TC3_WO1 ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1) +#define PORT_PA15E_TC3_WO1 (_UL_(1) << 15) +#define PIN_PA19E_TC3_WO1 _L_(19) /**< \brief TC3 signal: WO1 on PA19 mux E */ +#define MUX_PA19E_TC3_WO1 _L_(4) +#define PINMUX_PA19E_TC3_WO1 ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1) +#define PORT_PA19E_TC3_WO1 (_UL_(1) << 19) +/* ========== PORT definition for CAN0 peripheral ========== */ +#define PIN_PA23I_CAN0_RX _L_(23) /**< \brief CAN0 signal: RX on PA23 mux I */ +#define MUX_PA23I_CAN0_RX _L_(8) +#define PINMUX_PA23I_CAN0_RX ((PIN_PA23I_CAN0_RX << 16) | MUX_PA23I_CAN0_RX) +#define PORT_PA23I_CAN0_RX (_UL_(1) << 23) +#define PIN_PA25I_CAN0_RX _L_(25) /**< \brief CAN0 signal: RX on PA25 mux I */ +#define MUX_PA25I_CAN0_RX _L_(8) +#define PINMUX_PA25I_CAN0_RX ((PIN_PA25I_CAN0_RX << 16) | MUX_PA25I_CAN0_RX) +#define PORT_PA25I_CAN0_RX (_UL_(1) << 25) +#define PIN_PA22I_CAN0_TX _L_(22) /**< \brief CAN0 signal: TX on PA22 mux I */ +#define MUX_PA22I_CAN0_TX _L_(8) +#define PINMUX_PA22I_CAN0_TX ((PIN_PA22I_CAN0_TX << 16) | MUX_PA22I_CAN0_TX) +#define PORT_PA22I_CAN0_TX (_UL_(1) << 22) +#define PIN_PA24I_CAN0_TX _L_(24) /**< \brief CAN0 signal: TX on PA24 mux I */ +#define MUX_PA24I_CAN0_TX _L_(8) +#define PINMUX_PA24I_CAN0_TX ((PIN_PA24I_CAN0_TX << 16) | MUX_PA24I_CAN0_TX) +#define PORT_PA24I_CAN0_TX (_UL_(1) << 24) +/* ========== PORT definition for CAN1 peripheral ========== */ +#define PIN_PB13H_CAN1_RX _L_(45) /**< \brief CAN1 signal: RX on PB13 mux H */ +#define MUX_PB13H_CAN1_RX _L_(7) +#define PINMUX_PB13H_CAN1_RX ((PIN_PB13H_CAN1_RX << 16) | MUX_PB13H_CAN1_RX) +#define PORT_PB13H_CAN1_RX (_UL_(1) << 13) +#define PIN_PB15H_CAN1_RX _L_(47) /**< \brief CAN1 signal: RX on PB15 mux H */ +#define MUX_PB15H_CAN1_RX _L_(7) +#define PINMUX_PB15H_CAN1_RX ((PIN_PB15H_CAN1_RX << 16) | MUX_PB15H_CAN1_RX) +#define PORT_PB15H_CAN1_RX (_UL_(1) << 15) +#define PIN_PB12H_CAN1_TX _L_(44) /**< \brief CAN1 signal: TX on PB12 mux H */ +#define MUX_PB12H_CAN1_TX _L_(7) +#define PINMUX_PB12H_CAN1_TX ((PIN_PB12H_CAN1_TX << 16) | MUX_PB12H_CAN1_TX) +#define PORT_PB12H_CAN1_TX (_UL_(1) << 12) +#define PIN_PB14H_CAN1_TX _L_(46) /**< \brief CAN1 signal: TX on PB14 mux H */ +#define MUX_PB14H_CAN1_TX _L_(7) +#define PINMUX_PB14H_CAN1_TX ((PIN_PB14H_CAN1_TX << 16) | MUX_PB14H_CAN1_TX) +#define PORT_PB14H_CAN1_TX (_UL_(1) << 14) +/* ========== PORT definition for GMAC peripheral ========== */ +#define PIN_PC21L_GMAC_GCOL _L_(85) /**< \brief GMAC signal: GCOL on PC21 mux L */ +#define MUX_PC21L_GMAC_GCOL _L_(11) +#define PINMUX_PC21L_GMAC_GCOL ((PIN_PC21L_GMAC_GCOL << 16) | MUX_PC21L_GMAC_GCOL) +#define PORT_PC21L_GMAC_GCOL (_UL_(1) << 21) +#define PIN_PA16L_GMAC_GCRS _L_(16) /**< \brief GMAC signal: GCRS on PA16 mux L */ +#define MUX_PA16L_GMAC_GCRS _L_(11) +#define PINMUX_PA16L_GMAC_GCRS ((PIN_PA16L_GMAC_GCRS << 16) | MUX_PA16L_GMAC_GCRS) +#define PORT_PA16L_GMAC_GCRS (_UL_(1) << 16) +#define PIN_PA20L_GMAC_GMDC _L_(20) /**< \brief GMAC signal: GMDC on PA20 mux L */ +#define MUX_PA20L_GMAC_GMDC _L_(11) +#define PINMUX_PA20L_GMAC_GMDC ((PIN_PA20L_GMAC_GMDC << 16) | MUX_PA20L_GMAC_GMDC) +#define PORT_PA20L_GMAC_GMDC (_UL_(1) << 20) +#define PIN_PB14L_GMAC_GMDC _L_(46) /**< \brief GMAC signal: GMDC on PB14 mux L */ +#define MUX_PB14L_GMAC_GMDC _L_(11) +#define PINMUX_PB14L_GMAC_GMDC ((PIN_PB14L_GMAC_GMDC << 16) | MUX_PB14L_GMAC_GMDC) +#define PORT_PB14L_GMAC_GMDC (_UL_(1) << 14) +#define PIN_PC11L_GMAC_GMDC _L_(75) /**< \brief GMAC signal: GMDC on PC11 mux L */ +#define MUX_PC11L_GMAC_GMDC _L_(11) +#define PINMUX_PC11L_GMAC_GMDC ((PIN_PC11L_GMAC_GMDC << 16) | MUX_PC11L_GMAC_GMDC) +#define PORT_PC11L_GMAC_GMDC (_UL_(1) << 11) +#define PIN_PC22L_GMAC_GMDC _L_(86) /**< \brief GMAC signal: GMDC on PC22 mux L */ +#define MUX_PC22L_GMAC_GMDC _L_(11) +#define PINMUX_PC22L_GMAC_GMDC ((PIN_PC22L_GMAC_GMDC << 16) | MUX_PC22L_GMAC_GMDC) +#define PORT_PC22L_GMAC_GMDC (_UL_(1) << 22) +#define PIN_PA21L_GMAC_GMDIO _L_(21) /**< \brief GMAC signal: GMDIO on PA21 mux L */ +#define MUX_PA21L_GMAC_GMDIO _L_(11) +#define PINMUX_PA21L_GMAC_GMDIO ((PIN_PA21L_GMAC_GMDIO << 16) | MUX_PA21L_GMAC_GMDIO) +#define PORT_PA21L_GMAC_GMDIO (_UL_(1) << 21) +#define PIN_PB15L_GMAC_GMDIO _L_(47) /**< \brief GMAC signal: GMDIO on PB15 mux L */ +#define MUX_PB15L_GMAC_GMDIO _L_(11) +#define PINMUX_PB15L_GMAC_GMDIO ((PIN_PB15L_GMAC_GMDIO << 16) | MUX_PB15L_GMAC_GMDIO) +#define PORT_PB15L_GMAC_GMDIO (_UL_(1) << 15) +#define PIN_PC12L_GMAC_GMDIO _L_(76) /**< \brief GMAC signal: GMDIO on PC12 mux L */ +#define MUX_PC12L_GMAC_GMDIO _L_(11) +#define PINMUX_PC12L_GMAC_GMDIO ((PIN_PC12L_GMAC_GMDIO << 16) | MUX_PC12L_GMAC_GMDIO) +#define PORT_PC12L_GMAC_GMDIO (_UL_(1) << 12) +#define PIN_PC23L_GMAC_GMDIO _L_(87) /**< \brief GMAC signal: GMDIO on PC23 mux L */ +#define MUX_PC23L_GMAC_GMDIO _L_(11) +#define PINMUX_PC23L_GMAC_GMDIO ((PIN_PC23L_GMAC_GMDIO << 16) | MUX_PC23L_GMAC_GMDIO) +#define PORT_PC23L_GMAC_GMDIO (_UL_(1) << 23) +#define PIN_PA13L_GMAC_GRX0 _L_(13) /**< \brief GMAC signal: GRX0 on PA13 mux L */ +#define MUX_PA13L_GMAC_GRX0 _L_(11) +#define PINMUX_PA13L_GMAC_GRX0 ((PIN_PA13L_GMAC_GRX0 << 16) | MUX_PA13L_GMAC_GRX0) +#define PORT_PA13L_GMAC_GRX0 (_UL_(1) << 13) +#define PIN_PA12L_GMAC_GRX1 _L_(12) /**< \brief GMAC signal: GRX1 on PA12 mux L */ +#define MUX_PA12L_GMAC_GRX1 _L_(11) +#define PINMUX_PA12L_GMAC_GRX1 ((PIN_PA12L_GMAC_GRX1 << 16) | MUX_PA12L_GMAC_GRX1) +#define PORT_PA12L_GMAC_GRX1 (_UL_(1) << 12) +#define PIN_PC15L_GMAC_GRX2 _L_(79) /**< \brief GMAC signal: GRX2 on PC15 mux L */ +#define MUX_PC15L_GMAC_GRX2 _L_(11) +#define PINMUX_PC15L_GMAC_GRX2 ((PIN_PC15L_GMAC_GRX2 << 16) | MUX_PC15L_GMAC_GRX2) +#define PORT_PC15L_GMAC_GRX2 (_UL_(1) << 15) +#define PIN_PC14L_GMAC_GRX3 _L_(78) /**< \brief GMAC signal: GRX3 on PC14 mux L */ +#define MUX_PC14L_GMAC_GRX3 _L_(11) +#define PINMUX_PC14L_GMAC_GRX3 ((PIN_PC14L_GMAC_GRX3 << 16) | MUX_PC14L_GMAC_GRX3) +#define PORT_PC14L_GMAC_GRX3 (_UL_(1) << 14) +#define PIN_PC18L_GMAC_GRXCK _L_(82) /**< \brief GMAC signal: GRXCK on PC18 mux L */ +#define MUX_PC18L_GMAC_GRXCK _L_(11) +#define PINMUX_PC18L_GMAC_GRXCK ((PIN_PC18L_GMAC_GRXCK << 16) | MUX_PC18L_GMAC_GRXCK) +#define PORT_PC18L_GMAC_GRXCK (_UL_(1) << 18) +#define PIN_PC20L_GMAC_GRXDV _L_(84) /**< \brief GMAC signal: GRXDV on PC20 mux L */ +#define MUX_PC20L_GMAC_GRXDV _L_(11) +#define PINMUX_PC20L_GMAC_GRXDV ((PIN_PC20L_GMAC_GRXDV << 16) | MUX_PC20L_GMAC_GRXDV) +#define PORT_PC20L_GMAC_GRXDV (_UL_(1) << 20) +#define PIN_PA15L_GMAC_GRXER _L_(15) /**< \brief GMAC signal: GRXER on PA15 mux L */ +#define MUX_PA15L_GMAC_GRXER _L_(11) +#define PINMUX_PA15L_GMAC_GRXER ((PIN_PA15L_GMAC_GRXER << 16) | MUX_PA15L_GMAC_GRXER) +#define PORT_PA15L_GMAC_GRXER (_UL_(1) << 15) +#define PIN_PA18L_GMAC_GTX0 _L_(18) /**< \brief GMAC signal: GTX0 on PA18 mux L */ +#define MUX_PA18L_GMAC_GTX0 _L_(11) +#define PINMUX_PA18L_GMAC_GTX0 ((PIN_PA18L_GMAC_GTX0 << 16) | MUX_PA18L_GMAC_GTX0) +#define PORT_PA18L_GMAC_GTX0 (_UL_(1) << 18) +#define PIN_PA19L_GMAC_GTX1 _L_(19) /**< \brief GMAC signal: GTX1 on PA19 mux L */ +#define MUX_PA19L_GMAC_GTX1 _L_(11) +#define PINMUX_PA19L_GMAC_GTX1 ((PIN_PA19L_GMAC_GTX1 << 16) | MUX_PA19L_GMAC_GTX1) +#define PORT_PA19L_GMAC_GTX1 (_UL_(1) << 19) +#define PIN_PC16L_GMAC_GTX2 _L_(80) /**< \brief GMAC signal: GTX2 on PC16 mux L */ +#define MUX_PC16L_GMAC_GTX2 _L_(11) +#define PINMUX_PC16L_GMAC_GTX2 ((PIN_PC16L_GMAC_GTX2 << 16) | MUX_PC16L_GMAC_GTX2) +#define PORT_PC16L_GMAC_GTX2 (_UL_(1) << 16) +#define PIN_PC17L_GMAC_GTX3 _L_(81) /**< \brief GMAC signal: GTX3 on PC17 mux L */ +#define MUX_PC17L_GMAC_GTX3 _L_(11) +#define PINMUX_PC17L_GMAC_GTX3 ((PIN_PC17L_GMAC_GTX3 << 16) | MUX_PC17L_GMAC_GTX3) +#define PORT_PC17L_GMAC_GTX3 (_UL_(1) << 17) +#define PIN_PA14L_GMAC_GTXCK _L_(14) /**< \brief GMAC signal: GTXCK on PA14 mux L */ +#define MUX_PA14L_GMAC_GTXCK _L_(11) +#define PINMUX_PA14L_GMAC_GTXCK ((PIN_PA14L_GMAC_GTXCK << 16) | MUX_PA14L_GMAC_GTXCK) +#define PORT_PA14L_GMAC_GTXCK (_UL_(1) << 14) +#define PIN_PA17L_GMAC_GTXEN _L_(17) /**< \brief GMAC signal: GTXEN on PA17 mux L */ +#define MUX_PA17L_GMAC_GTXEN _L_(11) +#define PINMUX_PA17L_GMAC_GTXEN ((PIN_PA17L_GMAC_GTXEN << 16) | MUX_PA17L_GMAC_GTXEN) +#define PORT_PA17L_GMAC_GTXEN (_UL_(1) << 17) +#define PIN_PC19L_GMAC_GTXER _L_(83) /**< \brief GMAC signal: GTXER on PC19 mux L */ +#define MUX_PC19L_GMAC_GTXER _L_(11) +#define PINMUX_PC19L_GMAC_GTXER ((PIN_PC19L_GMAC_GTXER << 16) | MUX_PC19L_GMAC_GTXER) +#define PORT_PC19L_GMAC_GTXER (_UL_(1) << 19) +/* ========== PORT definition for TCC2 peripheral ========== */ +#define PIN_PA14F_TCC2_WO0 _L_(14) /**< \brief TCC2 signal: WO0 on PA14 mux F */ +#define MUX_PA14F_TCC2_WO0 _L_(5) +#define PINMUX_PA14F_TCC2_WO0 ((PIN_PA14F_TCC2_WO0 << 16) | MUX_PA14F_TCC2_WO0) +#define PORT_PA14F_TCC2_WO0 (_UL_(1) << 14) +#define PIN_PA30F_TCC2_WO0 _L_(30) /**< \brief TCC2 signal: WO0 on PA30 mux F */ +#define MUX_PA30F_TCC2_WO0 _L_(5) +#define PINMUX_PA30F_TCC2_WO0 ((PIN_PA30F_TCC2_WO0 << 16) | MUX_PA30F_TCC2_WO0) +#define PORT_PA30F_TCC2_WO0 (_UL_(1) << 30) +#define PIN_PA15F_TCC2_WO1 _L_(15) /**< \brief TCC2 signal: WO1 on PA15 mux F */ +#define MUX_PA15F_TCC2_WO1 _L_(5) +#define PINMUX_PA15F_TCC2_WO1 ((PIN_PA15F_TCC2_WO1 << 16) | MUX_PA15F_TCC2_WO1) +#define PORT_PA15F_TCC2_WO1 (_UL_(1) << 15) +#define PIN_PA31F_TCC2_WO1 _L_(31) /**< \brief TCC2 signal: WO1 on PA31 mux F */ +#define MUX_PA31F_TCC2_WO1 _L_(5) +#define PINMUX_PA31F_TCC2_WO1 ((PIN_PA31F_TCC2_WO1 << 16) | MUX_PA31F_TCC2_WO1) +#define PORT_PA31F_TCC2_WO1 (_UL_(1) << 31) +#define PIN_PA24F_TCC2_WO2 _L_(24) /**< \brief TCC2 signal: WO2 on PA24 mux F */ +#define MUX_PA24F_TCC2_WO2 _L_(5) +#define PINMUX_PA24F_TCC2_WO2 ((PIN_PA24F_TCC2_WO2 << 16) | MUX_PA24F_TCC2_WO2) +#define PORT_PA24F_TCC2_WO2 (_UL_(1) << 24) +#define PIN_PB02F_TCC2_WO2 _L_(34) /**< \brief TCC2 signal: WO2 on PB02 mux F */ +#define MUX_PB02F_TCC2_WO2 _L_(5) +#define PINMUX_PB02F_TCC2_WO2 ((PIN_PB02F_TCC2_WO2 << 16) | MUX_PB02F_TCC2_WO2) +#define PORT_PB02F_TCC2_WO2 (_UL_(1) << 2) +/* ========== PORT definition for TCC3 peripheral ========== */ +#define PIN_PB12F_TCC3_WO0 _L_(44) /**< \brief TCC3 signal: WO0 on PB12 mux F */ +#define MUX_PB12F_TCC3_WO0 _L_(5) +#define PINMUX_PB12F_TCC3_WO0 ((PIN_PB12F_TCC3_WO0 << 16) | MUX_PB12F_TCC3_WO0) +#define PORT_PB12F_TCC3_WO0 (_UL_(1) << 12) +#define PIN_PB16F_TCC3_WO0 _L_(48) /**< \brief TCC3 signal: WO0 on PB16 mux F */ +#define MUX_PB16F_TCC3_WO0 _L_(5) +#define PINMUX_PB16F_TCC3_WO0 ((PIN_PB16F_TCC3_WO0 << 16) | MUX_PB16F_TCC3_WO0) +#define PORT_PB16F_TCC3_WO0 (_UL_(1) << 16) +#define PIN_PB13F_TCC3_WO1 _L_(45) /**< \brief TCC3 signal: WO1 on PB13 mux F */ +#define MUX_PB13F_TCC3_WO1 _L_(5) +#define PINMUX_PB13F_TCC3_WO1 ((PIN_PB13F_TCC3_WO1 << 16) | MUX_PB13F_TCC3_WO1) +#define PORT_PB13F_TCC3_WO1 (_UL_(1) << 13) +#define PIN_PB17F_TCC3_WO1 _L_(49) /**< \brief TCC3 signal: WO1 on PB17 mux F */ +#define MUX_PB17F_TCC3_WO1 _L_(5) +#define PINMUX_PB17F_TCC3_WO1 ((PIN_PB17F_TCC3_WO1 << 16) | MUX_PB17F_TCC3_WO1) +#define PORT_PB17F_TCC3_WO1 (_UL_(1) << 17) +/* ========== PORT definition for TC4 peripheral ========== */ +#define PIN_PA22E_TC4_WO0 _L_(22) /**< \brief TC4 signal: WO0 on PA22 mux E */ +#define MUX_PA22E_TC4_WO0 _L_(4) +#define PINMUX_PA22E_TC4_WO0 ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0) +#define PORT_PA22E_TC4_WO0 (_UL_(1) << 22) +#define PIN_PB08E_TC4_WO0 _L_(40) /**< \brief TC4 signal: WO0 on PB08 mux E */ +#define MUX_PB08E_TC4_WO0 _L_(4) +#define PINMUX_PB08E_TC4_WO0 ((PIN_PB08E_TC4_WO0 << 16) | MUX_PB08E_TC4_WO0) +#define PORT_PB08E_TC4_WO0 (_UL_(1) << 8) +#define PIN_PB12E_TC4_WO0 _L_(44) /**< \brief TC4 signal: WO0 on PB12 mux E */ +#define MUX_PB12E_TC4_WO0 _L_(4) +#define PINMUX_PB12E_TC4_WO0 ((PIN_PB12E_TC4_WO0 << 16) | MUX_PB12E_TC4_WO0) +#define PORT_PB12E_TC4_WO0 (_UL_(1) << 12) +#define PIN_PA23E_TC4_WO1 _L_(23) /**< \brief TC4 signal: WO1 on PA23 mux E */ +#define MUX_PA23E_TC4_WO1 _L_(4) +#define PINMUX_PA23E_TC4_WO1 ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1) +#define PORT_PA23E_TC4_WO1 (_UL_(1) << 23) +#define PIN_PB09E_TC4_WO1 _L_(41) /**< \brief TC4 signal: WO1 on PB09 mux E */ +#define MUX_PB09E_TC4_WO1 _L_(4) +#define PINMUX_PB09E_TC4_WO1 ((PIN_PB09E_TC4_WO1 << 16) | MUX_PB09E_TC4_WO1) +#define PORT_PB09E_TC4_WO1 (_UL_(1) << 9) +#define PIN_PB13E_TC4_WO1 _L_(45) /**< \brief TC4 signal: WO1 on PB13 mux E */ +#define MUX_PB13E_TC4_WO1 _L_(4) +#define PINMUX_PB13E_TC4_WO1 ((PIN_PB13E_TC4_WO1 << 16) | MUX_PB13E_TC4_WO1) +#define PORT_PB13E_TC4_WO1 (_UL_(1) << 13) +/* ========== PORT definition for TC5 peripheral ========== */ +#define PIN_PA24E_TC5_WO0 _L_(24) /**< \brief TC5 signal: WO0 on PA24 mux E */ +#define MUX_PA24E_TC5_WO0 _L_(4) +#define PINMUX_PA24E_TC5_WO0 ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0) +#define PORT_PA24E_TC5_WO0 (_UL_(1) << 24) +#define PIN_PB10E_TC5_WO0 _L_(42) /**< \brief TC5 signal: WO0 on PB10 mux E */ +#define MUX_PB10E_TC5_WO0 _L_(4) +#define PINMUX_PB10E_TC5_WO0 ((PIN_PB10E_TC5_WO0 << 16) | MUX_PB10E_TC5_WO0) +#define PORT_PB10E_TC5_WO0 (_UL_(1) << 10) +#define PIN_PB14E_TC5_WO0 _L_(46) /**< \brief TC5 signal: WO0 on PB14 mux E */ +#define MUX_PB14E_TC5_WO0 _L_(4) +#define PINMUX_PB14E_TC5_WO0 ((PIN_PB14E_TC5_WO0 << 16) | MUX_PB14E_TC5_WO0) +#define PORT_PB14E_TC5_WO0 (_UL_(1) << 14) +#define PIN_PA25E_TC5_WO1 _L_(25) /**< \brief TC5 signal: WO1 on PA25 mux E */ +#define MUX_PA25E_TC5_WO1 _L_(4) +#define PINMUX_PA25E_TC5_WO1 ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1) +#define PORT_PA25E_TC5_WO1 (_UL_(1) << 25) +#define PIN_PB11E_TC5_WO1 _L_(43) /**< \brief TC5 signal: WO1 on PB11 mux E */ +#define MUX_PB11E_TC5_WO1 _L_(4) +#define PINMUX_PB11E_TC5_WO1 ((PIN_PB11E_TC5_WO1 << 16) | MUX_PB11E_TC5_WO1) +#define PORT_PB11E_TC5_WO1 (_UL_(1) << 11) +#define PIN_PB15E_TC5_WO1 _L_(47) /**< \brief TC5 signal: WO1 on PB15 mux E */ +#define MUX_PB15E_TC5_WO1 _L_(4) +#define PINMUX_PB15E_TC5_WO1 ((PIN_PB15E_TC5_WO1 << 16) | MUX_PB15E_TC5_WO1) +#define PORT_PB15E_TC5_WO1 (_UL_(1) << 15) +/* ========== PORT definition for PDEC peripheral ========== */ +#define PIN_PB18G_PDEC_QDI0 _L_(50) /**< \brief PDEC signal: QDI0 on PB18 mux G */ +#define MUX_PB18G_PDEC_QDI0 _L_(6) +#define PINMUX_PB18G_PDEC_QDI0 ((PIN_PB18G_PDEC_QDI0 << 16) | MUX_PB18G_PDEC_QDI0) +#define PORT_PB18G_PDEC_QDI0 (_UL_(1) << 18) +#define PIN_PB23G_PDEC_QDI0 _L_(55) /**< \brief PDEC signal: QDI0 on PB23 mux G */ +#define MUX_PB23G_PDEC_QDI0 _L_(6) +#define PINMUX_PB23G_PDEC_QDI0 ((PIN_PB23G_PDEC_QDI0 << 16) | MUX_PB23G_PDEC_QDI0) +#define PORT_PB23G_PDEC_QDI0 (_UL_(1) << 23) +#define PIN_PC16G_PDEC_QDI0 _L_(80) /**< \brief PDEC signal: QDI0 on PC16 mux G */ +#define MUX_PC16G_PDEC_QDI0 _L_(6) +#define PINMUX_PC16G_PDEC_QDI0 ((PIN_PC16G_PDEC_QDI0 << 16) | MUX_PC16G_PDEC_QDI0) +#define PORT_PC16G_PDEC_QDI0 (_UL_(1) << 16) +#define PIN_PA24G_PDEC_QDI0 _L_(24) /**< \brief PDEC signal: QDI0 on PA24 mux G */ +#define MUX_PA24G_PDEC_QDI0 _L_(6) +#define PINMUX_PA24G_PDEC_QDI0 ((PIN_PA24G_PDEC_QDI0 << 16) | MUX_PA24G_PDEC_QDI0) +#define PORT_PA24G_PDEC_QDI0 (_UL_(1) << 24) +#define PIN_PB19G_PDEC_QDI1 _L_(51) /**< \brief PDEC signal: QDI1 on PB19 mux G */ +#define MUX_PB19G_PDEC_QDI1 _L_(6) +#define PINMUX_PB19G_PDEC_QDI1 ((PIN_PB19G_PDEC_QDI1 << 16) | MUX_PB19G_PDEC_QDI1) +#define PORT_PB19G_PDEC_QDI1 (_UL_(1) << 19) +#define PIN_PB24G_PDEC_QDI1 _L_(56) /**< \brief PDEC signal: QDI1 on PB24 mux G */ +#define MUX_PB24G_PDEC_QDI1 _L_(6) +#define PINMUX_PB24G_PDEC_QDI1 ((PIN_PB24G_PDEC_QDI1 << 16) | MUX_PB24G_PDEC_QDI1) +#define PORT_PB24G_PDEC_QDI1 (_UL_(1) << 24) +#define PIN_PC17G_PDEC_QDI1 _L_(81) /**< \brief PDEC signal: QDI1 on PC17 mux G */ +#define MUX_PC17G_PDEC_QDI1 _L_(6) +#define PINMUX_PC17G_PDEC_QDI1 ((PIN_PC17G_PDEC_QDI1 << 16) | MUX_PC17G_PDEC_QDI1) +#define PORT_PC17G_PDEC_QDI1 (_UL_(1) << 17) +#define PIN_PA25G_PDEC_QDI1 _L_(25) /**< \brief PDEC signal: QDI1 on PA25 mux G */ +#define MUX_PA25G_PDEC_QDI1 _L_(6) +#define PINMUX_PA25G_PDEC_QDI1 ((PIN_PA25G_PDEC_QDI1 << 16) | MUX_PA25G_PDEC_QDI1) +#define PORT_PA25G_PDEC_QDI1 (_UL_(1) << 25) +#define PIN_PB20G_PDEC_QDI2 _L_(52) /**< \brief PDEC signal: QDI2 on PB20 mux G */ +#define MUX_PB20G_PDEC_QDI2 _L_(6) +#define PINMUX_PB20G_PDEC_QDI2 ((PIN_PB20G_PDEC_QDI2 << 16) | MUX_PB20G_PDEC_QDI2) +#define PORT_PB20G_PDEC_QDI2 (_UL_(1) << 20) +#define PIN_PB25G_PDEC_QDI2 _L_(57) /**< \brief PDEC signal: QDI2 on PB25 mux G */ +#define MUX_PB25G_PDEC_QDI2 _L_(6) +#define PINMUX_PB25G_PDEC_QDI2 ((PIN_PB25G_PDEC_QDI2 << 16) | MUX_PB25G_PDEC_QDI2) +#define PORT_PB25G_PDEC_QDI2 (_UL_(1) << 25) +#define PIN_PC18G_PDEC_QDI2 _L_(82) /**< \brief PDEC signal: QDI2 on PC18 mux G */ +#define MUX_PC18G_PDEC_QDI2 _L_(6) +#define PINMUX_PC18G_PDEC_QDI2 ((PIN_PC18G_PDEC_QDI2 << 16) | MUX_PC18G_PDEC_QDI2) +#define PORT_PC18G_PDEC_QDI2 (_UL_(1) << 18) +#define PIN_PB22G_PDEC_QDI2 _L_(54) /**< \brief PDEC signal: QDI2 on PB22 mux G */ +#define MUX_PB22G_PDEC_QDI2 _L_(6) +#define PINMUX_PB22G_PDEC_QDI2 ((PIN_PB22G_PDEC_QDI2 << 16) | MUX_PB22G_PDEC_QDI2) +#define PORT_PB22G_PDEC_QDI2 (_UL_(1) << 22) +/* ========== PORT definition for AC peripheral ========== */ +#define PIN_PA04B_AC_AIN0 _L_(4) /**< \brief AC signal: AIN0 on PA04 mux B */ +#define MUX_PA04B_AC_AIN0 _L_(1) +#define PINMUX_PA04B_AC_AIN0 ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0) +#define PORT_PA04B_AC_AIN0 (_UL_(1) << 4) +#define PIN_PA05B_AC_AIN1 _L_(5) /**< \brief AC signal: AIN1 on PA05 mux B */ +#define MUX_PA05B_AC_AIN1 _L_(1) +#define PINMUX_PA05B_AC_AIN1 ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1) +#define PORT_PA05B_AC_AIN1 (_UL_(1) << 5) +#define PIN_PA06B_AC_AIN2 _L_(6) /**< \brief AC signal: AIN2 on PA06 mux B */ +#define MUX_PA06B_AC_AIN2 _L_(1) +#define PINMUX_PA06B_AC_AIN2 ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2) +#define PORT_PA06B_AC_AIN2 (_UL_(1) << 6) +#define PIN_PA07B_AC_AIN3 _L_(7) /**< \brief AC signal: AIN3 on PA07 mux B */ +#define MUX_PA07B_AC_AIN3 _L_(1) +#define PINMUX_PA07B_AC_AIN3 ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3) +#define PORT_PA07B_AC_AIN3 (_UL_(1) << 7) +#define PIN_PA12M_AC_CMP0 _L_(12) /**< \brief AC signal: CMP0 on PA12 mux M */ +#define MUX_PA12M_AC_CMP0 _L_(12) +#define PINMUX_PA12M_AC_CMP0 ((PIN_PA12M_AC_CMP0 << 16) | MUX_PA12M_AC_CMP0) +#define PORT_PA12M_AC_CMP0 (_UL_(1) << 12) +#define PIN_PA18M_AC_CMP0 _L_(18) /**< \brief AC signal: CMP0 on PA18 mux M */ +#define MUX_PA18M_AC_CMP0 _L_(12) +#define PINMUX_PA18M_AC_CMP0 ((PIN_PA18M_AC_CMP0 << 16) | MUX_PA18M_AC_CMP0) +#define PORT_PA18M_AC_CMP0 (_UL_(1) << 18) +#define PIN_PB24M_AC_CMP0 _L_(56) /**< \brief AC signal: CMP0 on PB24 mux M */ +#define MUX_PB24M_AC_CMP0 _L_(12) +#define PINMUX_PB24M_AC_CMP0 ((PIN_PB24M_AC_CMP0 << 16) | MUX_PB24M_AC_CMP0) +#define PORT_PB24M_AC_CMP0 (_UL_(1) << 24) +#define PIN_PA13M_AC_CMP1 _L_(13) /**< \brief AC signal: CMP1 on PA13 mux M */ +#define MUX_PA13M_AC_CMP1 _L_(12) +#define PINMUX_PA13M_AC_CMP1 ((PIN_PA13M_AC_CMP1 << 16) | MUX_PA13M_AC_CMP1) +#define PORT_PA13M_AC_CMP1 (_UL_(1) << 13) +#define PIN_PA19M_AC_CMP1 _L_(19) /**< \brief AC signal: CMP1 on PA19 mux M */ +#define MUX_PA19M_AC_CMP1 _L_(12) +#define PINMUX_PA19M_AC_CMP1 ((PIN_PA19M_AC_CMP1 << 16) | MUX_PA19M_AC_CMP1) +#define PORT_PA19M_AC_CMP1 (_UL_(1) << 19) +#define PIN_PB25M_AC_CMP1 _L_(57) /**< \brief AC signal: CMP1 on PB25 mux M */ +#define MUX_PB25M_AC_CMP1 _L_(12) +#define PINMUX_PB25M_AC_CMP1 ((PIN_PB25M_AC_CMP1 << 16) | MUX_PB25M_AC_CMP1) +#define PORT_PB25M_AC_CMP1 (_UL_(1) << 25) +/* ========== PORT definition for QSPI peripheral ========== */ +#define PIN_PB11H_QSPI_CS _L_(43) /**< \brief QSPI signal: CS on PB11 mux H */ +#define MUX_PB11H_QSPI_CS _L_(7) +#define PINMUX_PB11H_QSPI_CS ((PIN_PB11H_QSPI_CS << 16) | MUX_PB11H_QSPI_CS) +#define PORT_PB11H_QSPI_CS (_UL_(1) << 11) +#define PIN_PA08H_QSPI_DATA0 _L_(8) /**< \brief QSPI signal: DATA0 on PA08 mux H */ +#define MUX_PA08H_QSPI_DATA0 _L_(7) +#define PINMUX_PA08H_QSPI_DATA0 ((PIN_PA08H_QSPI_DATA0 << 16) | MUX_PA08H_QSPI_DATA0) +#define PORT_PA08H_QSPI_DATA0 (_UL_(1) << 8) +#define PIN_PA09H_QSPI_DATA1 _L_(9) /**< \brief QSPI signal: DATA1 on PA09 mux H */ +#define MUX_PA09H_QSPI_DATA1 _L_(7) +#define PINMUX_PA09H_QSPI_DATA1 ((PIN_PA09H_QSPI_DATA1 << 16) | MUX_PA09H_QSPI_DATA1) +#define PORT_PA09H_QSPI_DATA1 (_UL_(1) << 9) +#define PIN_PA10H_QSPI_DATA2 _L_(10) /**< \brief QSPI signal: DATA2 on PA10 mux H */ +#define MUX_PA10H_QSPI_DATA2 _L_(7) +#define PINMUX_PA10H_QSPI_DATA2 ((PIN_PA10H_QSPI_DATA2 << 16) | MUX_PA10H_QSPI_DATA2) +#define PORT_PA10H_QSPI_DATA2 (_UL_(1) << 10) +#define PIN_PA11H_QSPI_DATA3 _L_(11) /**< \brief QSPI signal: DATA3 on PA11 mux H */ +#define MUX_PA11H_QSPI_DATA3 _L_(7) +#define PINMUX_PA11H_QSPI_DATA3 ((PIN_PA11H_QSPI_DATA3 << 16) | MUX_PA11H_QSPI_DATA3) +#define PORT_PA11H_QSPI_DATA3 (_UL_(1) << 11) +#define PIN_PB10H_QSPI_SCK _L_(42) /**< \brief QSPI signal: SCK on PB10 mux H */ +#define MUX_PB10H_QSPI_SCK _L_(7) +#define PINMUX_PB10H_QSPI_SCK ((PIN_PB10H_QSPI_SCK << 16) | MUX_PB10H_QSPI_SCK) +#define PORT_PB10H_QSPI_SCK (_UL_(1) << 10) +/* ========== PORT definition for CCL peripheral ========== */ +#define PIN_PA04N_CCL_IN0 _L_(4) /**< \brief CCL signal: IN0 on PA04 mux N */ +#define MUX_PA04N_CCL_IN0 _L_(13) +#define PINMUX_PA04N_CCL_IN0 ((PIN_PA04N_CCL_IN0 << 16) | MUX_PA04N_CCL_IN0) +#define PORT_PA04N_CCL_IN0 (_UL_(1) << 4) +#define PIN_PA16N_CCL_IN0 _L_(16) /**< \brief CCL signal: IN0 on PA16 mux N */ +#define MUX_PA16N_CCL_IN0 _L_(13) +#define PINMUX_PA16N_CCL_IN0 ((PIN_PA16N_CCL_IN0 << 16) | MUX_PA16N_CCL_IN0) +#define PORT_PA16N_CCL_IN0 (_UL_(1) << 16) +#define PIN_PB22N_CCL_IN0 _L_(54) /**< \brief CCL signal: IN0 on PB22 mux N */ +#define MUX_PB22N_CCL_IN0 _L_(13) +#define PINMUX_PB22N_CCL_IN0 ((PIN_PB22N_CCL_IN0 << 16) | MUX_PB22N_CCL_IN0) +#define PORT_PB22N_CCL_IN0 (_UL_(1) << 22) +#define PIN_PA05N_CCL_IN1 _L_(5) /**< \brief CCL signal: IN1 on PA05 mux N */ +#define MUX_PA05N_CCL_IN1 _L_(13) +#define PINMUX_PA05N_CCL_IN1 ((PIN_PA05N_CCL_IN1 << 16) | MUX_PA05N_CCL_IN1) +#define PORT_PA05N_CCL_IN1 (_UL_(1) << 5) +#define PIN_PA17N_CCL_IN1 _L_(17) /**< \brief CCL signal: IN1 on PA17 mux N */ +#define MUX_PA17N_CCL_IN1 _L_(13) +#define PINMUX_PA17N_CCL_IN1 ((PIN_PA17N_CCL_IN1 << 16) | MUX_PA17N_CCL_IN1) +#define PORT_PA17N_CCL_IN1 (_UL_(1) << 17) +#define PIN_PB00N_CCL_IN1 _L_(32) /**< \brief CCL signal: IN1 on PB00 mux N */ +#define MUX_PB00N_CCL_IN1 _L_(13) +#define PINMUX_PB00N_CCL_IN1 ((PIN_PB00N_CCL_IN1 << 16) | MUX_PB00N_CCL_IN1) +#define PORT_PB00N_CCL_IN1 (_UL_(1) << 0) +#define PIN_PA06N_CCL_IN2 _L_(6) /**< \brief CCL signal: IN2 on PA06 mux N */ +#define MUX_PA06N_CCL_IN2 _L_(13) +#define PINMUX_PA06N_CCL_IN2 ((PIN_PA06N_CCL_IN2 << 16) | MUX_PA06N_CCL_IN2) +#define PORT_PA06N_CCL_IN2 (_UL_(1) << 6) +#define PIN_PA18N_CCL_IN2 _L_(18) /**< \brief CCL signal: IN2 on PA18 mux N */ +#define MUX_PA18N_CCL_IN2 _L_(13) +#define PINMUX_PA18N_CCL_IN2 ((PIN_PA18N_CCL_IN2 << 16) | MUX_PA18N_CCL_IN2) +#define PORT_PA18N_CCL_IN2 (_UL_(1) << 18) +#define PIN_PB01N_CCL_IN2 _L_(33) /**< \brief CCL signal: IN2 on PB01 mux N */ +#define MUX_PB01N_CCL_IN2 _L_(13) +#define PINMUX_PB01N_CCL_IN2 ((PIN_PB01N_CCL_IN2 << 16) | MUX_PB01N_CCL_IN2) +#define PORT_PB01N_CCL_IN2 (_UL_(1) << 1) +#define PIN_PA08N_CCL_IN3 _L_(8) /**< \brief CCL signal: IN3 on PA08 mux N */ +#define MUX_PA08N_CCL_IN3 _L_(13) +#define PINMUX_PA08N_CCL_IN3 ((PIN_PA08N_CCL_IN3 << 16) | MUX_PA08N_CCL_IN3) +#define PORT_PA08N_CCL_IN3 (_UL_(1) << 8) +#define PIN_PA30N_CCL_IN3 _L_(30) /**< \brief CCL signal: IN3 on PA30 mux N */ +#define MUX_PA30N_CCL_IN3 _L_(13) +#define PINMUX_PA30N_CCL_IN3 ((PIN_PA30N_CCL_IN3 << 16) | MUX_PA30N_CCL_IN3) +#define PORT_PA30N_CCL_IN3 (_UL_(1) << 30) +#define PIN_PA09N_CCL_IN4 _L_(9) /**< \brief CCL signal: IN4 on PA09 mux N */ +#define MUX_PA09N_CCL_IN4 _L_(13) +#define PINMUX_PA09N_CCL_IN4 ((PIN_PA09N_CCL_IN4 << 16) | MUX_PA09N_CCL_IN4) +#define PORT_PA09N_CCL_IN4 (_UL_(1) << 9) +#define PIN_PC27N_CCL_IN4 _L_(91) /**< \brief CCL signal: IN4 on PC27 mux N */ +#define MUX_PC27N_CCL_IN4 _L_(13) +#define PINMUX_PC27N_CCL_IN4 ((PIN_PC27N_CCL_IN4 << 16) | MUX_PC27N_CCL_IN4) +#define PORT_PC27N_CCL_IN4 (_UL_(1) << 27) +#define PIN_PA10N_CCL_IN5 _L_(10) /**< \brief CCL signal: IN5 on PA10 mux N */ +#define MUX_PA10N_CCL_IN5 _L_(13) +#define PINMUX_PA10N_CCL_IN5 ((PIN_PA10N_CCL_IN5 << 16) | MUX_PA10N_CCL_IN5) +#define PORT_PA10N_CCL_IN5 (_UL_(1) << 10) +#define PIN_PC28N_CCL_IN5 _L_(92) /**< \brief CCL signal: IN5 on PC28 mux N */ +#define MUX_PC28N_CCL_IN5 _L_(13) +#define PINMUX_PC28N_CCL_IN5 ((PIN_PC28N_CCL_IN5 << 16) | MUX_PC28N_CCL_IN5) +#define PORT_PC28N_CCL_IN5 (_UL_(1) << 28) +#define PIN_PA22N_CCL_IN6 _L_(22) /**< \brief CCL signal: IN6 on PA22 mux N */ +#define MUX_PA22N_CCL_IN6 _L_(13) +#define PINMUX_PA22N_CCL_IN6 ((PIN_PA22N_CCL_IN6 << 16) | MUX_PA22N_CCL_IN6) +#define PORT_PA22N_CCL_IN6 (_UL_(1) << 22) +#define PIN_PB06N_CCL_IN6 _L_(38) /**< \brief CCL signal: IN6 on PB06 mux N */ +#define MUX_PB06N_CCL_IN6 _L_(13) +#define PINMUX_PB06N_CCL_IN6 ((PIN_PB06N_CCL_IN6 << 16) | MUX_PB06N_CCL_IN6) +#define PORT_PB06N_CCL_IN6 (_UL_(1) << 6) +#define PIN_PA23N_CCL_IN7 _L_(23) /**< \brief CCL signal: IN7 on PA23 mux N */ +#define MUX_PA23N_CCL_IN7 _L_(13) +#define PINMUX_PA23N_CCL_IN7 ((PIN_PA23N_CCL_IN7 << 16) | MUX_PA23N_CCL_IN7) +#define PORT_PA23N_CCL_IN7 (_UL_(1) << 23) +#define PIN_PB07N_CCL_IN7 _L_(39) /**< \brief CCL signal: IN7 on PB07 mux N */ +#define MUX_PB07N_CCL_IN7 _L_(13) +#define PINMUX_PB07N_CCL_IN7 ((PIN_PB07N_CCL_IN7 << 16) | MUX_PB07N_CCL_IN7) +#define PORT_PB07N_CCL_IN7 (_UL_(1) << 7) +#define PIN_PA24N_CCL_IN8 _L_(24) /**< \brief CCL signal: IN8 on PA24 mux N */ +#define MUX_PA24N_CCL_IN8 _L_(13) +#define PINMUX_PA24N_CCL_IN8 ((PIN_PA24N_CCL_IN8 << 16) | MUX_PA24N_CCL_IN8) +#define PORT_PA24N_CCL_IN8 (_UL_(1) << 24) +#define PIN_PB08N_CCL_IN8 _L_(40) /**< \brief CCL signal: IN8 on PB08 mux N */ +#define MUX_PB08N_CCL_IN8 _L_(13) +#define PINMUX_PB08N_CCL_IN8 ((PIN_PB08N_CCL_IN8 << 16) | MUX_PB08N_CCL_IN8) +#define PORT_PB08N_CCL_IN8 (_UL_(1) << 8) +#define PIN_PB14N_CCL_IN9 _L_(46) /**< \brief CCL signal: IN9 on PB14 mux N */ +#define MUX_PB14N_CCL_IN9 _L_(13) +#define PINMUX_PB14N_CCL_IN9 ((PIN_PB14N_CCL_IN9 << 16) | MUX_PB14N_CCL_IN9) +#define PORT_PB14N_CCL_IN9 (_UL_(1) << 14) +#define PIN_PC20N_CCL_IN9 _L_(84) /**< \brief CCL signal: IN9 on PC20 mux N */ +#define MUX_PC20N_CCL_IN9 _L_(13) +#define PINMUX_PC20N_CCL_IN9 ((PIN_PC20N_CCL_IN9 << 16) | MUX_PC20N_CCL_IN9) +#define PORT_PC20N_CCL_IN9 (_UL_(1) << 20) +#define PIN_PB15N_CCL_IN10 _L_(47) /**< \brief CCL signal: IN10 on PB15 mux N */ +#define MUX_PB15N_CCL_IN10 _L_(13) +#define PINMUX_PB15N_CCL_IN10 ((PIN_PB15N_CCL_IN10 << 16) | MUX_PB15N_CCL_IN10) +#define PORT_PB15N_CCL_IN10 (_UL_(1) << 15) +#define PIN_PC21N_CCL_IN10 _L_(85) /**< \brief CCL signal: IN10 on PC21 mux N */ +#define MUX_PC21N_CCL_IN10 _L_(13) +#define PINMUX_PC21N_CCL_IN10 ((PIN_PC21N_CCL_IN10 << 16) | MUX_PC21N_CCL_IN10) +#define PORT_PC21N_CCL_IN10 (_UL_(1) << 21) +#define PIN_PB10N_CCL_IN11 _L_(42) /**< \brief CCL signal: IN11 on PB10 mux N */ +#define MUX_PB10N_CCL_IN11 _L_(13) +#define PINMUX_PB10N_CCL_IN11 ((PIN_PB10N_CCL_IN11 << 16) | MUX_PB10N_CCL_IN11) +#define PORT_PB10N_CCL_IN11 (_UL_(1) << 10) +#define PIN_PB16N_CCL_IN11 _L_(48) /**< \brief CCL signal: IN11 on PB16 mux N */ +#define MUX_PB16N_CCL_IN11 _L_(13) +#define PINMUX_PB16N_CCL_IN11 ((PIN_PB16N_CCL_IN11 << 16) | MUX_PB16N_CCL_IN11) +#define PORT_PB16N_CCL_IN11 (_UL_(1) << 16) +#define PIN_PA07N_CCL_OUT0 _L_(7) /**< \brief CCL signal: OUT0 on PA07 mux N */ +#define MUX_PA07N_CCL_OUT0 _L_(13) +#define PINMUX_PA07N_CCL_OUT0 ((PIN_PA07N_CCL_OUT0 << 16) | MUX_PA07N_CCL_OUT0) +#define PORT_PA07N_CCL_OUT0 (_UL_(1) << 7) +#define PIN_PA19N_CCL_OUT0 _L_(19) /**< \brief CCL signal: OUT0 on PA19 mux N */ +#define MUX_PA19N_CCL_OUT0 _L_(13) +#define PINMUX_PA19N_CCL_OUT0 ((PIN_PA19N_CCL_OUT0 << 16) | MUX_PA19N_CCL_OUT0) +#define PORT_PA19N_CCL_OUT0 (_UL_(1) << 19) +#define PIN_PB02N_CCL_OUT0 _L_(34) /**< \brief CCL signal: OUT0 on PB02 mux N */ +#define MUX_PB02N_CCL_OUT0 _L_(13) +#define PINMUX_PB02N_CCL_OUT0 ((PIN_PB02N_CCL_OUT0 << 16) | MUX_PB02N_CCL_OUT0) +#define PORT_PB02N_CCL_OUT0 (_UL_(1) << 2) +#define PIN_PB23N_CCL_OUT0 _L_(55) /**< \brief CCL signal: OUT0 on PB23 mux N */ +#define MUX_PB23N_CCL_OUT0 _L_(13) +#define PINMUX_PB23N_CCL_OUT0 ((PIN_PB23N_CCL_OUT0 << 16) | MUX_PB23N_CCL_OUT0) +#define PORT_PB23N_CCL_OUT0 (_UL_(1) << 23) +#define PIN_PA11N_CCL_OUT1 _L_(11) /**< \brief CCL signal: OUT1 on PA11 mux N */ +#define MUX_PA11N_CCL_OUT1 _L_(13) +#define PINMUX_PA11N_CCL_OUT1 ((PIN_PA11N_CCL_OUT1 << 16) | MUX_PA11N_CCL_OUT1) +#define PORT_PA11N_CCL_OUT1 (_UL_(1) << 11) +#define PIN_PA31N_CCL_OUT1 _L_(31) /**< \brief CCL signal: OUT1 on PA31 mux N */ +#define MUX_PA31N_CCL_OUT1 _L_(13) +#define PINMUX_PA31N_CCL_OUT1 ((PIN_PA31N_CCL_OUT1 << 16) | MUX_PA31N_CCL_OUT1) +#define PORT_PA31N_CCL_OUT1 (_UL_(1) << 31) +#define PIN_PB11N_CCL_OUT1 _L_(43) /**< \brief CCL signal: OUT1 on PB11 mux N */ +#define MUX_PB11N_CCL_OUT1 _L_(13) +#define PINMUX_PB11N_CCL_OUT1 ((PIN_PB11N_CCL_OUT1 << 16) | MUX_PB11N_CCL_OUT1) +#define PORT_PB11N_CCL_OUT1 (_UL_(1) << 11) +#define PIN_PA25N_CCL_OUT2 _L_(25) /**< \brief CCL signal: OUT2 on PA25 mux N */ +#define MUX_PA25N_CCL_OUT2 _L_(13) +#define PINMUX_PA25N_CCL_OUT2 ((PIN_PA25N_CCL_OUT2 << 16) | MUX_PA25N_CCL_OUT2) +#define PORT_PA25N_CCL_OUT2 (_UL_(1) << 25) +#define PIN_PB09N_CCL_OUT2 _L_(41) /**< \brief CCL signal: OUT2 on PB09 mux N */ +#define MUX_PB09N_CCL_OUT2 _L_(13) +#define PINMUX_PB09N_CCL_OUT2 ((PIN_PB09N_CCL_OUT2 << 16) | MUX_PB09N_CCL_OUT2) +#define PORT_PB09N_CCL_OUT2 (_UL_(1) << 9) +#define PIN_PB17N_CCL_OUT3 _L_(49) /**< \brief CCL signal: OUT3 on PB17 mux N */ +#define MUX_PB17N_CCL_OUT3 _L_(13) +#define PINMUX_PB17N_CCL_OUT3 ((PIN_PB17N_CCL_OUT3 << 16) | MUX_PB17N_CCL_OUT3) +#define PORT_PB17N_CCL_OUT3 (_UL_(1) << 17) +/* ========== PORT definition for SERCOM4 peripheral ========== */ +#define PIN_PA13D_SERCOM4_PAD0 _L_(13) /**< \brief SERCOM4 signal: PAD0 on PA13 mux D */ +#define MUX_PA13D_SERCOM4_PAD0 _L_(3) +#define PINMUX_PA13D_SERCOM4_PAD0 ((PIN_PA13D_SERCOM4_PAD0 << 16) | MUX_PA13D_SERCOM4_PAD0) +#define PORT_PA13D_SERCOM4_PAD0 (_UL_(1) << 13) +#define PIN_PB08D_SERCOM4_PAD0 _L_(40) /**< \brief SERCOM4 signal: PAD0 on PB08 mux D */ +#define MUX_PB08D_SERCOM4_PAD0 _L_(3) +#define PINMUX_PB08D_SERCOM4_PAD0 ((PIN_PB08D_SERCOM4_PAD0 << 16) | MUX_PB08D_SERCOM4_PAD0) +#define PORT_PB08D_SERCOM4_PAD0 (_UL_(1) << 8) +#define PIN_PB27D_SERCOM4_PAD0 _L_(59) /**< \brief SERCOM4 signal: PAD0 on PB27 mux D */ +#define MUX_PB27D_SERCOM4_PAD0 _L_(3) +#define PINMUX_PB27D_SERCOM4_PAD0 ((PIN_PB27D_SERCOM4_PAD0 << 16) | MUX_PB27D_SERCOM4_PAD0) +#define PORT_PB27D_SERCOM4_PAD0 (_UL_(1) << 27) +#define PIN_PB12C_SERCOM4_PAD0 _L_(44) /**< \brief SERCOM4 signal: PAD0 on PB12 mux C */ +#define MUX_PB12C_SERCOM4_PAD0 _L_(2) +#define PINMUX_PB12C_SERCOM4_PAD0 ((PIN_PB12C_SERCOM4_PAD0 << 16) | MUX_PB12C_SERCOM4_PAD0) +#define PORT_PB12C_SERCOM4_PAD0 (_UL_(1) << 12) +#define PIN_PA12D_SERCOM4_PAD1 _L_(12) /**< \brief SERCOM4 signal: PAD1 on PA12 mux D */ +#define MUX_PA12D_SERCOM4_PAD1 _L_(3) +#define PINMUX_PA12D_SERCOM4_PAD1 ((PIN_PA12D_SERCOM4_PAD1 << 16) | MUX_PA12D_SERCOM4_PAD1) +#define PORT_PA12D_SERCOM4_PAD1 (_UL_(1) << 12) +#define PIN_PB09D_SERCOM4_PAD1 _L_(41) /**< \brief SERCOM4 signal: PAD1 on PB09 mux D */ +#define MUX_PB09D_SERCOM4_PAD1 _L_(3) +#define PINMUX_PB09D_SERCOM4_PAD1 ((PIN_PB09D_SERCOM4_PAD1 << 16) | MUX_PB09D_SERCOM4_PAD1) +#define PORT_PB09D_SERCOM4_PAD1 (_UL_(1) << 9) +#define PIN_PB26D_SERCOM4_PAD1 _L_(58) /**< \brief SERCOM4 signal: PAD1 on PB26 mux D */ +#define MUX_PB26D_SERCOM4_PAD1 _L_(3) +#define PINMUX_PB26D_SERCOM4_PAD1 ((PIN_PB26D_SERCOM4_PAD1 << 16) | MUX_PB26D_SERCOM4_PAD1) +#define PORT_PB26D_SERCOM4_PAD1 (_UL_(1) << 26) +#define PIN_PB13C_SERCOM4_PAD1 _L_(45) /**< \brief SERCOM4 signal: PAD1 on PB13 mux C */ +#define MUX_PB13C_SERCOM4_PAD1 _L_(2) +#define PINMUX_PB13C_SERCOM4_PAD1 ((PIN_PB13C_SERCOM4_PAD1 << 16) | MUX_PB13C_SERCOM4_PAD1) +#define PORT_PB13C_SERCOM4_PAD1 (_UL_(1) << 13) +#define PIN_PA14D_SERCOM4_PAD2 _L_(14) /**< \brief SERCOM4 signal: PAD2 on PA14 mux D */ +#define MUX_PA14D_SERCOM4_PAD2 _L_(3) +#define PINMUX_PA14D_SERCOM4_PAD2 ((PIN_PA14D_SERCOM4_PAD2 << 16) | MUX_PA14D_SERCOM4_PAD2) +#define PORT_PA14D_SERCOM4_PAD2 (_UL_(1) << 14) +#define PIN_PB10D_SERCOM4_PAD2 _L_(42) /**< \brief SERCOM4 signal: PAD2 on PB10 mux D */ +#define MUX_PB10D_SERCOM4_PAD2 _L_(3) +#define PINMUX_PB10D_SERCOM4_PAD2 ((PIN_PB10D_SERCOM4_PAD2 << 16) | MUX_PB10D_SERCOM4_PAD2) +#define PORT_PB10D_SERCOM4_PAD2 (_UL_(1) << 10) +#define PIN_PB28D_SERCOM4_PAD2 _L_(60) /**< \brief SERCOM4 signal: PAD2 on PB28 mux D */ +#define MUX_PB28D_SERCOM4_PAD2 _L_(3) +#define PINMUX_PB28D_SERCOM4_PAD2 ((PIN_PB28D_SERCOM4_PAD2 << 16) | MUX_PB28D_SERCOM4_PAD2) +#define PORT_PB28D_SERCOM4_PAD2 (_UL_(1) << 28) +#define PIN_PB14C_SERCOM4_PAD2 _L_(46) /**< \brief SERCOM4 signal: PAD2 on PB14 mux C */ +#define MUX_PB14C_SERCOM4_PAD2 _L_(2) +#define PINMUX_PB14C_SERCOM4_PAD2 ((PIN_PB14C_SERCOM4_PAD2 << 16) | MUX_PB14C_SERCOM4_PAD2) +#define PORT_PB14C_SERCOM4_PAD2 (_UL_(1) << 14) +#define PIN_PB11D_SERCOM4_PAD3 _L_(43) /**< \brief SERCOM4 signal: PAD3 on PB11 mux D */ +#define MUX_PB11D_SERCOM4_PAD3 _L_(3) +#define PINMUX_PB11D_SERCOM4_PAD3 ((PIN_PB11D_SERCOM4_PAD3 << 16) | MUX_PB11D_SERCOM4_PAD3) +#define PORT_PB11D_SERCOM4_PAD3 (_UL_(1) << 11) +#define PIN_PB29D_SERCOM4_PAD3 _L_(61) /**< \brief SERCOM4 signal: PAD3 on PB29 mux D */ +#define MUX_PB29D_SERCOM4_PAD3 _L_(3) +#define PINMUX_PB29D_SERCOM4_PAD3 ((PIN_PB29D_SERCOM4_PAD3 << 16) | MUX_PB29D_SERCOM4_PAD3) +#define PORT_PB29D_SERCOM4_PAD3 (_UL_(1) << 29) +#define PIN_PA15D_SERCOM4_PAD3 _L_(15) /**< \brief SERCOM4 signal: PAD3 on PA15 mux D */ +#define MUX_PA15D_SERCOM4_PAD3 _L_(3) +#define PINMUX_PA15D_SERCOM4_PAD3 ((PIN_PA15D_SERCOM4_PAD3 << 16) | MUX_PA15D_SERCOM4_PAD3) +#define PORT_PA15D_SERCOM4_PAD3 (_UL_(1) << 15) +#define PIN_PB15C_SERCOM4_PAD3 _L_(47) /**< \brief SERCOM4 signal: PAD3 on PB15 mux C */ +#define MUX_PB15C_SERCOM4_PAD3 _L_(2) +#define PINMUX_PB15C_SERCOM4_PAD3 ((PIN_PB15C_SERCOM4_PAD3 << 16) | MUX_PB15C_SERCOM4_PAD3) +#define PORT_PB15C_SERCOM4_PAD3 (_UL_(1) << 15) +/* ========== PORT definition for SERCOM5 peripheral ========== */ +#define PIN_PA23D_SERCOM5_PAD0 _L_(23) /**< \brief SERCOM5 signal: PAD0 on PA23 mux D */ +#define MUX_PA23D_SERCOM5_PAD0 _L_(3) +#define PINMUX_PA23D_SERCOM5_PAD0 ((PIN_PA23D_SERCOM5_PAD0 << 16) | MUX_PA23D_SERCOM5_PAD0) +#define PORT_PA23D_SERCOM5_PAD0 (_UL_(1) << 23) +#define PIN_PB02D_SERCOM5_PAD0 _L_(34) /**< \brief SERCOM5 signal: PAD0 on PB02 mux D */ +#define MUX_PB02D_SERCOM5_PAD0 _L_(3) +#define PINMUX_PB02D_SERCOM5_PAD0 ((PIN_PB02D_SERCOM5_PAD0 << 16) | MUX_PB02D_SERCOM5_PAD0) +#define PORT_PB02D_SERCOM5_PAD0 (_UL_(1) << 2) +#define PIN_PB31D_SERCOM5_PAD0 _L_(63) /**< \brief SERCOM5 signal: PAD0 on PB31 mux D */ +#define MUX_PB31D_SERCOM5_PAD0 _L_(3) +#define PINMUX_PB31D_SERCOM5_PAD0 ((PIN_PB31D_SERCOM5_PAD0 << 16) | MUX_PB31D_SERCOM5_PAD0) +#define PORT_PB31D_SERCOM5_PAD0 (_UL_(1) << 31) +#define PIN_PB16C_SERCOM5_PAD0 _L_(48) /**< \brief SERCOM5 signal: PAD0 on PB16 mux C */ +#define MUX_PB16C_SERCOM5_PAD0 _L_(2) +#define PINMUX_PB16C_SERCOM5_PAD0 ((PIN_PB16C_SERCOM5_PAD0 << 16) | MUX_PB16C_SERCOM5_PAD0) +#define PORT_PB16C_SERCOM5_PAD0 (_UL_(1) << 16) +#define PIN_PA22D_SERCOM5_PAD1 _L_(22) /**< \brief SERCOM5 signal: PAD1 on PA22 mux D */ +#define MUX_PA22D_SERCOM5_PAD1 _L_(3) +#define PINMUX_PA22D_SERCOM5_PAD1 ((PIN_PA22D_SERCOM5_PAD1 << 16) | MUX_PA22D_SERCOM5_PAD1) +#define PORT_PA22D_SERCOM5_PAD1 (_UL_(1) << 22) +#define PIN_PB03D_SERCOM5_PAD1 _L_(35) /**< \brief SERCOM5 signal: PAD1 on PB03 mux D */ +#define MUX_PB03D_SERCOM5_PAD1 _L_(3) +#define PINMUX_PB03D_SERCOM5_PAD1 ((PIN_PB03D_SERCOM5_PAD1 << 16) | MUX_PB03D_SERCOM5_PAD1) +#define PORT_PB03D_SERCOM5_PAD1 (_UL_(1) << 3) +#define PIN_PB30D_SERCOM5_PAD1 _L_(62) /**< \brief SERCOM5 signal: PAD1 on PB30 mux D */ +#define MUX_PB30D_SERCOM5_PAD1 _L_(3) +#define PINMUX_PB30D_SERCOM5_PAD1 ((PIN_PB30D_SERCOM5_PAD1 << 16) | MUX_PB30D_SERCOM5_PAD1) +#define PORT_PB30D_SERCOM5_PAD1 (_UL_(1) << 30) +#define PIN_PB17C_SERCOM5_PAD1 _L_(49) /**< \brief SERCOM5 signal: PAD1 on PB17 mux C */ +#define MUX_PB17C_SERCOM5_PAD1 _L_(2) +#define PINMUX_PB17C_SERCOM5_PAD1 ((PIN_PB17C_SERCOM5_PAD1 << 16) | MUX_PB17C_SERCOM5_PAD1) +#define PORT_PB17C_SERCOM5_PAD1 (_UL_(1) << 17) +#define PIN_PA24D_SERCOM5_PAD2 _L_(24) /**< \brief SERCOM5 signal: PAD2 on PA24 mux D */ +#define MUX_PA24D_SERCOM5_PAD2 _L_(3) +#define PINMUX_PA24D_SERCOM5_PAD2 ((PIN_PA24D_SERCOM5_PAD2 << 16) | MUX_PA24D_SERCOM5_PAD2) +#define PORT_PA24D_SERCOM5_PAD2 (_UL_(1) << 24) +#define PIN_PB00D_SERCOM5_PAD2 _L_(32) /**< \brief SERCOM5 signal: PAD2 on PB00 mux D */ +#define MUX_PB00D_SERCOM5_PAD2 _L_(3) +#define PINMUX_PB00D_SERCOM5_PAD2 ((PIN_PB00D_SERCOM5_PAD2 << 16) | MUX_PB00D_SERCOM5_PAD2) +#define PORT_PB00D_SERCOM5_PAD2 (_UL_(1) << 0) +#define PIN_PB22D_SERCOM5_PAD2 _L_(54) /**< \brief SERCOM5 signal: PAD2 on PB22 mux D */ +#define MUX_PB22D_SERCOM5_PAD2 _L_(3) +#define PINMUX_PB22D_SERCOM5_PAD2 ((PIN_PB22D_SERCOM5_PAD2 << 16) | MUX_PB22D_SERCOM5_PAD2) +#define PORT_PB22D_SERCOM5_PAD2 (_UL_(1) << 22) +#define PIN_PA20C_SERCOM5_PAD2 _L_(20) /**< \brief SERCOM5 signal: PAD2 on PA20 mux C */ +#define MUX_PA20C_SERCOM5_PAD2 _L_(2) +#define PINMUX_PA20C_SERCOM5_PAD2 ((PIN_PA20C_SERCOM5_PAD2 << 16) | MUX_PA20C_SERCOM5_PAD2) +#define PORT_PA20C_SERCOM5_PAD2 (_UL_(1) << 20) +#define PIN_PB18C_SERCOM5_PAD2 _L_(50) /**< \brief SERCOM5 signal: PAD2 on PB18 mux C */ +#define MUX_PB18C_SERCOM5_PAD2 _L_(2) +#define PINMUX_PB18C_SERCOM5_PAD2 ((PIN_PB18C_SERCOM5_PAD2 << 16) | MUX_PB18C_SERCOM5_PAD2) +#define PORT_PB18C_SERCOM5_PAD2 (_UL_(1) << 18) +#define PIN_PA25D_SERCOM5_PAD3 _L_(25) /**< \brief SERCOM5 signal: PAD3 on PA25 mux D */ +#define MUX_PA25D_SERCOM5_PAD3 _L_(3) +#define PINMUX_PA25D_SERCOM5_PAD3 ((PIN_PA25D_SERCOM5_PAD3 << 16) | MUX_PA25D_SERCOM5_PAD3) +#define PORT_PA25D_SERCOM5_PAD3 (_UL_(1) << 25) +#define PIN_PB01D_SERCOM5_PAD3 _L_(33) /**< \brief SERCOM5 signal: PAD3 on PB01 mux D */ +#define MUX_PB01D_SERCOM5_PAD3 _L_(3) +#define PINMUX_PB01D_SERCOM5_PAD3 ((PIN_PB01D_SERCOM5_PAD3 << 16) | MUX_PB01D_SERCOM5_PAD3) +#define PORT_PB01D_SERCOM5_PAD3 (_UL_(1) << 1) +#define PIN_PB23D_SERCOM5_PAD3 _L_(55) /**< \brief SERCOM5 signal: PAD3 on PB23 mux D */ +#define MUX_PB23D_SERCOM5_PAD3 _L_(3) +#define PINMUX_PB23D_SERCOM5_PAD3 ((PIN_PB23D_SERCOM5_PAD3 << 16) | MUX_PB23D_SERCOM5_PAD3) +#define PORT_PB23D_SERCOM5_PAD3 (_UL_(1) << 23) +#define PIN_PA21C_SERCOM5_PAD3 _L_(21) /**< \brief SERCOM5 signal: PAD3 on PA21 mux C */ +#define MUX_PA21C_SERCOM5_PAD3 _L_(2) +#define PINMUX_PA21C_SERCOM5_PAD3 ((PIN_PA21C_SERCOM5_PAD3 << 16) | MUX_PA21C_SERCOM5_PAD3) +#define PORT_PA21C_SERCOM5_PAD3 (_UL_(1) << 21) +#define PIN_PB19C_SERCOM5_PAD3 _L_(51) /**< \brief SERCOM5 signal: PAD3 on PB19 mux C */ +#define MUX_PB19C_SERCOM5_PAD3 _L_(2) +#define PINMUX_PB19C_SERCOM5_PAD3 ((PIN_PB19C_SERCOM5_PAD3 << 16) | MUX_PB19C_SERCOM5_PAD3) +#define PORT_PB19C_SERCOM5_PAD3 (_UL_(1) << 19) +/* ========== PORT definition for SERCOM6 peripheral ========== */ +#define PIN_PD09D_SERCOM6_PAD0 _L_(105) /**< \brief SERCOM6 signal: PAD0 on PD09 mux D */ +#define MUX_PD09D_SERCOM6_PAD0 _L_(3) +#define PINMUX_PD09D_SERCOM6_PAD0 ((PIN_PD09D_SERCOM6_PAD0 << 16) | MUX_PD09D_SERCOM6_PAD0) +#define PORT_PD09D_SERCOM6_PAD0 (_UL_(1) << 9) +#define PIN_PC13D_SERCOM6_PAD0 _L_(77) /**< \brief SERCOM6 signal: PAD0 on PC13 mux D */ +#define MUX_PC13D_SERCOM6_PAD0 _L_(3) +#define PINMUX_PC13D_SERCOM6_PAD0 ((PIN_PC13D_SERCOM6_PAD0 << 16) | MUX_PC13D_SERCOM6_PAD0) +#define PORT_PC13D_SERCOM6_PAD0 (_UL_(1) << 13) +#define PIN_PC04C_SERCOM6_PAD0 _L_(68) /**< \brief SERCOM6 signal: PAD0 on PC04 mux C */ +#define MUX_PC04C_SERCOM6_PAD0 _L_(2) +#define PINMUX_PC04C_SERCOM6_PAD0 ((PIN_PC04C_SERCOM6_PAD0 << 16) | MUX_PC04C_SERCOM6_PAD0) +#define PORT_PC04C_SERCOM6_PAD0 (_UL_(1) << 4) +#define PIN_PC16C_SERCOM6_PAD0 _L_(80) /**< \brief SERCOM6 signal: PAD0 on PC16 mux C */ +#define MUX_PC16C_SERCOM6_PAD0 _L_(2) +#define PINMUX_PC16C_SERCOM6_PAD0 ((PIN_PC16C_SERCOM6_PAD0 << 16) | MUX_PC16C_SERCOM6_PAD0) +#define PORT_PC16C_SERCOM6_PAD0 (_UL_(1) << 16) +#define PIN_PD08D_SERCOM6_PAD1 _L_(104) /**< \brief SERCOM6 signal: PAD1 on PD08 mux D */ +#define MUX_PD08D_SERCOM6_PAD1 _L_(3) +#define PINMUX_PD08D_SERCOM6_PAD1 ((PIN_PD08D_SERCOM6_PAD1 << 16) | MUX_PD08D_SERCOM6_PAD1) +#define PORT_PD08D_SERCOM6_PAD1 (_UL_(1) << 8) +#define PIN_PC12D_SERCOM6_PAD1 _L_(76) /**< \brief SERCOM6 signal: PAD1 on PC12 mux D */ +#define MUX_PC12D_SERCOM6_PAD1 _L_(3) +#define PINMUX_PC12D_SERCOM6_PAD1 ((PIN_PC12D_SERCOM6_PAD1 << 16) | MUX_PC12D_SERCOM6_PAD1) +#define PORT_PC12D_SERCOM6_PAD1 (_UL_(1) << 12) +#define PIN_PC05C_SERCOM6_PAD1 _L_(69) /**< \brief SERCOM6 signal: PAD1 on PC05 mux C */ +#define MUX_PC05C_SERCOM6_PAD1 _L_(2) +#define PINMUX_PC05C_SERCOM6_PAD1 ((PIN_PC05C_SERCOM6_PAD1 << 16) | MUX_PC05C_SERCOM6_PAD1) +#define PORT_PC05C_SERCOM6_PAD1 (_UL_(1) << 5) +#define PIN_PC17C_SERCOM6_PAD1 _L_(81) /**< \brief SERCOM6 signal: PAD1 on PC17 mux C */ +#define MUX_PC17C_SERCOM6_PAD1 _L_(2) +#define PINMUX_PC17C_SERCOM6_PAD1 ((PIN_PC17C_SERCOM6_PAD1 << 16) | MUX_PC17C_SERCOM6_PAD1) +#define PORT_PC17C_SERCOM6_PAD1 (_UL_(1) << 17) +#define PIN_PC14D_SERCOM6_PAD2 _L_(78) /**< \brief SERCOM6 signal: PAD2 on PC14 mux D */ +#define MUX_PC14D_SERCOM6_PAD2 _L_(3) +#define PINMUX_PC14D_SERCOM6_PAD2 ((PIN_PC14D_SERCOM6_PAD2 << 16) | MUX_PC14D_SERCOM6_PAD2) +#define PORT_PC14D_SERCOM6_PAD2 (_UL_(1) << 14) +#define PIN_PD10D_SERCOM6_PAD2 _L_(106) /**< \brief SERCOM6 signal: PAD2 on PD10 mux D */ +#define MUX_PD10D_SERCOM6_PAD2 _L_(3) +#define PINMUX_PD10D_SERCOM6_PAD2 ((PIN_PD10D_SERCOM6_PAD2 << 16) | MUX_PD10D_SERCOM6_PAD2) +#define PORT_PD10D_SERCOM6_PAD2 (_UL_(1) << 10) +#define PIN_PC06C_SERCOM6_PAD2 _L_(70) /**< \brief SERCOM6 signal: PAD2 on PC06 mux C */ +#define MUX_PC06C_SERCOM6_PAD2 _L_(2) +#define PINMUX_PC06C_SERCOM6_PAD2 ((PIN_PC06C_SERCOM6_PAD2 << 16) | MUX_PC06C_SERCOM6_PAD2) +#define PORT_PC06C_SERCOM6_PAD2 (_UL_(1) << 6) +#define PIN_PC10C_SERCOM6_PAD2 _L_(74) /**< \brief SERCOM6 signal: PAD2 on PC10 mux C */ +#define MUX_PC10C_SERCOM6_PAD2 _L_(2) +#define PINMUX_PC10C_SERCOM6_PAD2 ((PIN_PC10C_SERCOM6_PAD2 << 16) | MUX_PC10C_SERCOM6_PAD2) +#define PORT_PC10C_SERCOM6_PAD2 (_UL_(1) << 10) +#define PIN_PC18C_SERCOM6_PAD2 _L_(82) /**< \brief SERCOM6 signal: PAD2 on PC18 mux C */ +#define MUX_PC18C_SERCOM6_PAD2 _L_(2) +#define PINMUX_PC18C_SERCOM6_PAD2 ((PIN_PC18C_SERCOM6_PAD2 << 16) | MUX_PC18C_SERCOM6_PAD2) +#define PORT_PC18C_SERCOM6_PAD2 (_UL_(1) << 18) +#define PIN_PC15D_SERCOM6_PAD3 _L_(79) /**< \brief SERCOM6 signal: PAD3 on PC15 mux D */ +#define MUX_PC15D_SERCOM6_PAD3 _L_(3) +#define PINMUX_PC15D_SERCOM6_PAD3 ((PIN_PC15D_SERCOM6_PAD3 << 16) | MUX_PC15D_SERCOM6_PAD3) +#define PORT_PC15D_SERCOM6_PAD3 (_UL_(1) << 15) +#define PIN_PD11D_SERCOM6_PAD3 _L_(107) /**< \brief SERCOM6 signal: PAD3 on PD11 mux D */ +#define MUX_PD11D_SERCOM6_PAD3 _L_(3) +#define PINMUX_PD11D_SERCOM6_PAD3 ((PIN_PD11D_SERCOM6_PAD3 << 16) | MUX_PD11D_SERCOM6_PAD3) +#define PORT_PD11D_SERCOM6_PAD3 (_UL_(1) << 11) +#define PIN_PC07C_SERCOM6_PAD3 _L_(71) /**< \brief SERCOM6 signal: PAD3 on PC07 mux C */ +#define MUX_PC07C_SERCOM6_PAD3 _L_(2) +#define PINMUX_PC07C_SERCOM6_PAD3 ((PIN_PC07C_SERCOM6_PAD3 << 16) | MUX_PC07C_SERCOM6_PAD3) +#define PORT_PC07C_SERCOM6_PAD3 (_UL_(1) << 7) +#define PIN_PC11C_SERCOM6_PAD3 _L_(75) /**< \brief SERCOM6 signal: PAD3 on PC11 mux C */ +#define MUX_PC11C_SERCOM6_PAD3 _L_(2) +#define PINMUX_PC11C_SERCOM6_PAD3 ((PIN_PC11C_SERCOM6_PAD3 << 16) | MUX_PC11C_SERCOM6_PAD3) +#define PORT_PC11C_SERCOM6_PAD3 (_UL_(1) << 11) +#define PIN_PC19C_SERCOM6_PAD3 _L_(83) /**< \brief SERCOM6 signal: PAD3 on PC19 mux C */ +#define MUX_PC19C_SERCOM6_PAD3 _L_(2) +#define PINMUX_PC19C_SERCOM6_PAD3 ((PIN_PC19C_SERCOM6_PAD3 << 16) | MUX_PC19C_SERCOM6_PAD3) +#define PORT_PC19C_SERCOM6_PAD3 (_UL_(1) << 19) +/* ========== PORT definition for SERCOM7 peripheral ========== */ +#define PIN_PB21D_SERCOM7_PAD0 _L_(53) /**< \brief SERCOM7 signal: PAD0 on PB21 mux D */ +#define MUX_PB21D_SERCOM7_PAD0 _L_(3) +#define PINMUX_PB21D_SERCOM7_PAD0 ((PIN_PB21D_SERCOM7_PAD0 << 16) | MUX_PB21D_SERCOM7_PAD0) +#define PORT_PB21D_SERCOM7_PAD0 (_UL_(1) << 21) +#define PIN_PD08C_SERCOM7_PAD0 _L_(104) /**< \brief SERCOM7 signal: PAD0 on PD08 mux C */ +#define MUX_PD08C_SERCOM7_PAD0 _L_(2) +#define PINMUX_PD08C_SERCOM7_PAD0 ((PIN_PD08C_SERCOM7_PAD0 << 16) | MUX_PD08C_SERCOM7_PAD0) +#define PORT_PD08C_SERCOM7_PAD0 (_UL_(1) << 8) +#define PIN_PB30C_SERCOM7_PAD0 _L_(62) /**< \brief SERCOM7 signal: PAD0 on PB30 mux C */ +#define MUX_PB30C_SERCOM7_PAD0 _L_(2) +#define PINMUX_PB30C_SERCOM7_PAD0 ((PIN_PB30C_SERCOM7_PAD0 << 16) | MUX_PB30C_SERCOM7_PAD0) +#define PORT_PB30C_SERCOM7_PAD0 (_UL_(1) << 30) +#define PIN_PC12C_SERCOM7_PAD0 _L_(76) /**< \brief SERCOM7 signal: PAD0 on PC12 mux C */ +#define MUX_PC12C_SERCOM7_PAD0 _L_(2) +#define PINMUX_PC12C_SERCOM7_PAD0 ((PIN_PC12C_SERCOM7_PAD0 << 16) | MUX_PC12C_SERCOM7_PAD0) +#define PORT_PC12C_SERCOM7_PAD0 (_UL_(1) << 12) +#define PIN_PB20D_SERCOM7_PAD1 _L_(52) /**< \brief SERCOM7 signal: PAD1 on PB20 mux D */ +#define MUX_PB20D_SERCOM7_PAD1 _L_(3) +#define PINMUX_PB20D_SERCOM7_PAD1 ((PIN_PB20D_SERCOM7_PAD1 << 16) | MUX_PB20D_SERCOM7_PAD1) +#define PORT_PB20D_SERCOM7_PAD1 (_UL_(1) << 20) +#define PIN_PD09C_SERCOM7_PAD1 _L_(105) /**< \brief SERCOM7 signal: PAD1 on PD09 mux C */ +#define MUX_PD09C_SERCOM7_PAD1 _L_(2) +#define PINMUX_PD09C_SERCOM7_PAD1 ((PIN_PD09C_SERCOM7_PAD1 << 16) | MUX_PD09C_SERCOM7_PAD1) +#define PORT_PD09C_SERCOM7_PAD1 (_UL_(1) << 9) +#define PIN_PB31C_SERCOM7_PAD1 _L_(63) /**< \brief SERCOM7 signal: PAD1 on PB31 mux C */ +#define MUX_PB31C_SERCOM7_PAD1 _L_(2) +#define PINMUX_PB31C_SERCOM7_PAD1 ((PIN_PB31C_SERCOM7_PAD1 << 16) | MUX_PB31C_SERCOM7_PAD1) +#define PORT_PB31C_SERCOM7_PAD1 (_UL_(1) << 31) +#define PIN_PC13C_SERCOM7_PAD1 _L_(77) /**< \brief SERCOM7 signal: PAD1 on PC13 mux C */ +#define MUX_PC13C_SERCOM7_PAD1 _L_(2) +#define PINMUX_PC13C_SERCOM7_PAD1 ((PIN_PC13C_SERCOM7_PAD1 << 16) | MUX_PC13C_SERCOM7_PAD1) +#define PORT_PC13C_SERCOM7_PAD1 (_UL_(1) << 13) +#define PIN_PB18D_SERCOM7_PAD2 _L_(50) /**< \brief SERCOM7 signal: PAD2 on PB18 mux D */ +#define MUX_PB18D_SERCOM7_PAD2 _L_(3) +#define PINMUX_PB18D_SERCOM7_PAD2 ((PIN_PB18D_SERCOM7_PAD2 << 16) | MUX_PB18D_SERCOM7_PAD2) +#define PORT_PB18D_SERCOM7_PAD2 (_UL_(1) << 18) +#define PIN_PC10D_SERCOM7_PAD2 _L_(74) /**< \brief SERCOM7 signal: PAD2 on PC10 mux D */ +#define MUX_PC10D_SERCOM7_PAD2 _L_(3) +#define PINMUX_PC10D_SERCOM7_PAD2 ((PIN_PC10D_SERCOM7_PAD2 << 16) | MUX_PC10D_SERCOM7_PAD2) +#define PORT_PC10D_SERCOM7_PAD2 (_UL_(1) << 10) +#define PIN_PC14C_SERCOM7_PAD2 _L_(78) /**< \brief SERCOM7 signal: PAD2 on PC14 mux C */ +#define MUX_PC14C_SERCOM7_PAD2 _L_(2) +#define PINMUX_PC14C_SERCOM7_PAD2 ((PIN_PC14C_SERCOM7_PAD2 << 16) | MUX_PC14C_SERCOM7_PAD2) +#define PORT_PC14C_SERCOM7_PAD2 (_UL_(1) << 14) +#define PIN_PD10C_SERCOM7_PAD2 _L_(106) /**< \brief SERCOM7 signal: PAD2 on PD10 mux C */ +#define MUX_PD10C_SERCOM7_PAD2 _L_(2) +#define PINMUX_PD10C_SERCOM7_PAD2 ((PIN_PD10C_SERCOM7_PAD2 << 16) | MUX_PD10C_SERCOM7_PAD2) +#define PORT_PD10C_SERCOM7_PAD2 (_UL_(1) << 10) +#define PIN_PA30C_SERCOM7_PAD2 _L_(30) /**< \brief SERCOM7 signal: PAD2 on PA30 mux C */ +#define MUX_PA30C_SERCOM7_PAD2 _L_(2) +#define PINMUX_PA30C_SERCOM7_PAD2 ((PIN_PA30C_SERCOM7_PAD2 << 16) | MUX_PA30C_SERCOM7_PAD2) +#define PORT_PA30C_SERCOM7_PAD2 (_UL_(1) << 30) +#define PIN_PB19D_SERCOM7_PAD3 _L_(51) /**< \brief SERCOM7 signal: PAD3 on PB19 mux D */ +#define MUX_PB19D_SERCOM7_PAD3 _L_(3) +#define PINMUX_PB19D_SERCOM7_PAD3 ((PIN_PB19D_SERCOM7_PAD3 << 16) | MUX_PB19D_SERCOM7_PAD3) +#define PORT_PB19D_SERCOM7_PAD3 (_UL_(1) << 19) +#define PIN_PC11D_SERCOM7_PAD3 _L_(75) /**< \brief SERCOM7 signal: PAD3 on PC11 mux D */ +#define MUX_PC11D_SERCOM7_PAD3 _L_(3) +#define PINMUX_PC11D_SERCOM7_PAD3 ((PIN_PC11D_SERCOM7_PAD3 << 16) | MUX_PC11D_SERCOM7_PAD3) +#define PORT_PC11D_SERCOM7_PAD3 (_UL_(1) << 11) +#define PIN_PC15C_SERCOM7_PAD3 _L_(79) /**< \brief SERCOM7 signal: PAD3 on PC15 mux C */ +#define MUX_PC15C_SERCOM7_PAD3 _L_(2) +#define PINMUX_PC15C_SERCOM7_PAD3 ((PIN_PC15C_SERCOM7_PAD3 << 16) | MUX_PC15C_SERCOM7_PAD3) +#define PORT_PC15C_SERCOM7_PAD3 (_UL_(1) << 15) +#define PIN_PD11C_SERCOM7_PAD3 _L_(107) /**< \brief SERCOM7 signal: PAD3 on PD11 mux C */ +#define MUX_PD11C_SERCOM7_PAD3 _L_(2) +#define PINMUX_PD11C_SERCOM7_PAD3 ((PIN_PD11C_SERCOM7_PAD3 << 16) | MUX_PD11C_SERCOM7_PAD3) +#define PORT_PD11C_SERCOM7_PAD3 (_UL_(1) << 11) +#define PIN_PA31C_SERCOM7_PAD3 _L_(31) /**< \brief SERCOM7 signal: PAD3 on PA31 mux C */ +#define MUX_PA31C_SERCOM7_PAD3 _L_(2) +#define PINMUX_PA31C_SERCOM7_PAD3 ((PIN_PA31C_SERCOM7_PAD3 << 16) | MUX_PA31C_SERCOM7_PAD3) +#define PORT_PA31C_SERCOM7_PAD3 (_UL_(1) << 31) +/* ========== PORT definition for TCC4 peripheral ========== */ +#define PIN_PB14F_TCC4_WO0 _L_(46) /**< \brief TCC4 signal: WO0 on PB14 mux F */ +#define MUX_PB14F_TCC4_WO0 _L_(5) +#define PINMUX_PB14F_TCC4_WO0 ((PIN_PB14F_TCC4_WO0 << 16) | MUX_PB14F_TCC4_WO0) +#define PORT_PB14F_TCC4_WO0 (_UL_(1) << 14) +#define PIN_PB30F_TCC4_WO0 _L_(62) /**< \brief TCC4 signal: WO0 on PB30 mux F */ +#define MUX_PB30F_TCC4_WO0 _L_(5) +#define PINMUX_PB30F_TCC4_WO0 ((PIN_PB30F_TCC4_WO0 << 16) | MUX_PB30F_TCC4_WO0) +#define PORT_PB30F_TCC4_WO0 (_UL_(1) << 30) +#define PIN_PB15F_TCC4_WO1 _L_(47) /**< \brief TCC4 signal: WO1 on PB15 mux F */ +#define MUX_PB15F_TCC4_WO1 _L_(5) +#define PINMUX_PB15F_TCC4_WO1 ((PIN_PB15F_TCC4_WO1 << 16) | MUX_PB15F_TCC4_WO1) +#define PORT_PB15F_TCC4_WO1 (_UL_(1) << 15) +#define PIN_PB31F_TCC4_WO1 _L_(63) /**< \brief TCC4 signal: WO1 on PB31 mux F */ +#define MUX_PB31F_TCC4_WO1 _L_(5) +#define PINMUX_PB31F_TCC4_WO1 ((PIN_PB31F_TCC4_WO1 << 16) | MUX_PB31F_TCC4_WO1) +#define PORT_PB31F_TCC4_WO1 (_UL_(1) << 31) +/* ========== PORT definition for TC6 peripheral ========== */ +#define PIN_PA30E_TC6_WO0 _L_(30) /**< \brief TC6 signal: WO0 on PA30 mux E */ +#define MUX_PA30E_TC6_WO0 _L_(4) +#define PINMUX_PA30E_TC6_WO0 ((PIN_PA30E_TC6_WO0 << 16) | MUX_PA30E_TC6_WO0) +#define PORT_PA30E_TC6_WO0 (_UL_(1) << 30) +#define PIN_PB02E_TC6_WO0 _L_(34) /**< \brief TC6 signal: WO0 on PB02 mux E */ +#define MUX_PB02E_TC6_WO0 _L_(4) +#define PINMUX_PB02E_TC6_WO0 ((PIN_PB02E_TC6_WO0 << 16) | MUX_PB02E_TC6_WO0) +#define PORT_PB02E_TC6_WO0 (_UL_(1) << 2) +#define PIN_PB16E_TC6_WO0 _L_(48) /**< \brief TC6 signal: WO0 on PB16 mux E */ +#define MUX_PB16E_TC6_WO0 _L_(4) +#define PINMUX_PB16E_TC6_WO0 ((PIN_PB16E_TC6_WO0 << 16) | MUX_PB16E_TC6_WO0) +#define PORT_PB16E_TC6_WO0 (_UL_(1) << 16) +#define PIN_PA31E_TC6_WO1 _L_(31) /**< \brief TC6 signal: WO1 on PA31 mux E */ +#define MUX_PA31E_TC6_WO1 _L_(4) +#define PINMUX_PA31E_TC6_WO1 ((PIN_PA31E_TC6_WO1 << 16) | MUX_PA31E_TC6_WO1) +#define PORT_PA31E_TC6_WO1 (_UL_(1) << 31) +#define PIN_PB03E_TC6_WO1 _L_(35) /**< \brief TC6 signal: WO1 on PB03 mux E */ +#define MUX_PB03E_TC6_WO1 _L_(4) +#define PINMUX_PB03E_TC6_WO1 ((PIN_PB03E_TC6_WO1 << 16) | MUX_PB03E_TC6_WO1) +#define PORT_PB03E_TC6_WO1 (_UL_(1) << 3) +#define PIN_PB17E_TC6_WO1 _L_(49) /**< \brief TC6 signal: WO1 on PB17 mux E */ +#define MUX_PB17E_TC6_WO1 _L_(4) +#define PINMUX_PB17E_TC6_WO1 ((PIN_PB17E_TC6_WO1 << 16) | MUX_PB17E_TC6_WO1) +#define PORT_PB17E_TC6_WO1 (_UL_(1) << 17) +/* ========== PORT definition for TC7 peripheral ========== */ +#define PIN_PA20E_TC7_WO0 _L_(20) /**< \brief TC7 signal: WO0 on PA20 mux E */ +#define MUX_PA20E_TC7_WO0 _L_(4) +#define PINMUX_PA20E_TC7_WO0 ((PIN_PA20E_TC7_WO0 << 16) | MUX_PA20E_TC7_WO0) +#define PORT_PA20E_TC7_WO0 (_UL_(1) << 20) +#define PIN_PB00E_TC7_WO0 _L_(32) /**< \brief TC7 signal: WO0 on PB00 mux E */ +#define MUX_PB00E_TC7_WO0 _L_(4) +#define PINMUX_PB00E_TC7_WO0 ((PIN_PB00E_TC7_WO0 << 16) | MUX_PB00E_TC7_WO0) +#define PORT_PB00E_TC7_WO0 (_UL_(1) << 0) +#define PIN_PB22E_TC7_WO0 _L_(54) /**< \brief TC7 signal: WO0 on PB22 mux E */ +#define MUX_PB22E_TC7_WO0 _L_(4) +#define PINMUX_PB22E_TC7_WO0 ((PIN_PB22E_TC7_WO0 << 16) | MUX_PB22E_TC7_WO0) +#define PORT_PB22E_TC7_WO0 (_UL_(1) << 22) +#define PIN_PA21E_TC7_WO1 _L_(21) /**< \brief TC7 signal: WO1 on PA21 mux E */ +#define MUX_PA21E_TC7_WO1 _L_(4) +#define PINMUX_PA21E_TC7_WO1 ((PIN_PA21E_TC7_WO1 << 16) | MUX_PA21E_TC7_WO1) +#define PORT_PA21E_TC7_WO1 (_UL_(1) << 21) +#define PIN_PB01E_TC7_WO1 _L_(33) /**< \brief TC7 signal: WO1 on PB01 mux E */ +#define MUX_PB01E_TC7_WO1 _L_(4) +#define PINMUX_PB01E_TC7_WO1 ((PIN_PB01E_TC7_WO1 << 16) | MUX_PB01E_TC7_WO1) +#define PORT_PB01E_TC7_WO1 (_UL_(1) << 1) +#define PIN_PB23E_TC7_WO1 _L_(55) /**< \brief TC7 signal: WO1 on PB23 mux E */ +#define MUX_PB23E_TC7_WO1 _L_(4) +#define PINMUX_PB23E_TC7_WO1 ((PIN_PB23E_TC7_WO1 << 16) | MUX_PB23E_TC7_WO1) +#define PORT_PB23E_TC7_WO1 (_UL_(1) << 23) +/* ========== PORT definition for ADC0 peripheral ========== */ +#define PIN_PA02B_ADC0_AIN0 _L_(2) /**< \brief ADC0 signal: AIN0 on PA02 mux B */ +#define MUX_PA02B_ADC0_AIN0 _L_(1) +#define PINMUX_PA02B_ADC0_AIN0 ((PIN_PA02B_ADC0_AIN0 << 16) | MUX_PA02B_ADC0_AIN0) +#define PORT_PA02B_ADC0_AIN0 (_UL_(1) << 2) +#define PIN_PA03B_ADC0_AIN1 _L_(3) /**< \brief ADC0 signal: AIN1 on PA03 mux B */ +#define MUX_PA03B_ADC0_AIN1 _L_(1) +#define PINMUX_PA03B_ADC0_AIN1 ((PIN_PA03B_ADC0_AIN1 << 16) | MUX_PA03B_ADC0_AIN1) +#define PORT_PA03B_ADC0_AIN1 (_UL_(1) << 3) +#define PIN_PB08B_ADC0_AIN2 _L_(40) /**< \brief ADC0 signal: AIN2 on PB08 mux B */ +#define MUX_PB08B_ADC0_AIN2 _L_(1) +#define PINMUX_PB08B_ADC0_AIN2 ((PIN_PB08B_ADC0_AIN2 << 16) | MUX_PB08B_ADC0_AIN2) +#define PORT_PB08B_ADC0_AIN2 (_UL_(1) << 8) +#define PIN_PB09B_ADC0_AIN3 _L_(41) /**< \brief ADC0 signal: AIN3 on PB09 mux B */ +#define MUX_PB09B_ADC0_AIN3 _L_(1) +#define PINMUX_PB09B_ADC0_AIN3 ((PIN_PB09B_ADC0_AIN3 << 16) | MUX_PB09B_ADC0_AIN3) +#define PORT_PB09B_ADC0_AIN3 (_UL_(1) << 9) +#define PIN_PA04B_ADC0_AIN4 _L_(4) /**< \brief ADC0 signal: AIN4 on PA04 mux B */ +#define MUX_PA04B_ADC0_AIN4 _L_(1) +#define PINMUX_PA04B_ADC0_AIN4 ((PIN_PA04B_ADC0_AIN4 << 16) | MUX_PA04B_ADC0_AIN4) +#define PORT_PA04B_ADC0_AIN4 (_UL_(1) << 4) +#define PIN_PA05B_ADC0_AIN5 _L_(5) /**< \brief ADC0 signal: AIN5 on PA05 mux B */ +#define MUX_PA05B_ADC0_AIN5 _L_(1) +#define PINMUX_PA05B_ADC0_AIN5 ((PIN_PA05B_ADC0_AIN5 << 16) | MUX_PA05B_ADC0_AIN5) +#define PORT_PA05B_ADC0_AIN5 (_UL_(1) << 5) +#define PIN_PA06B_ADC0_AIN6 _L_(6) /**< \brief ADC0 signal: AIN6 on PA06 mux B */ +#define MUX_PA06B_ADC0_AIN6 _L_(1) +#define PINMUX_PA06B_ADC0_AIN6 ((PIN_PA06B_ADC0_AIN6 << 16) | MUX_PA06B_ADC0_AIN6) +#define PORT_PA06B_ADC0_AIN6 (_UL_(1) << 6) +#define PIN_PA07B_ADC0_AIN7 _L_(7) /**< \brief ADC0 signal: AIN7 on PA07 mux B */ +#define MUX_PA07B_ADC0_AIN7 _L_(1) +#define PINMUX_PA07B_ADC0_AIN7 ((PIN_PA07B_ADC0_AIN7 << 16) | MUX_PA07B_ADC0_AIN7) +#define PORT_PA07B_ADC0_AIN7 (_UL_(1) << 7) +#define PIN_PA08B_ADC0_AIN8 _L_(8) /**< \brief ADC0 signal: AIN8 on PA08 mux B */ +#define MUX_PA08B_ADC0_AIN8 _L_(1) +#define PINMUX_PA08B_ADC0_AIN8 ((PIN_PA08B_ADC0_AIN8 << 16) | MUX_PA08B_ADC0_AIN8) +#define PORT_PA08B_ADC0_AIN8 (_UL_(1) << 8) +#define PIN_PA09B_ADC0_AIN9 _L_(9) /**< \brief ADC0 signal: AIN9 on PA09 mux B */ +#define MUX_PA09B_ADC0_AIN9 _L_(1) +#define PINMUX_PA09B_ADC0_AIN9 ((PIN_PA09B_ADC0_AIN9 << 16) | MUX_PA09B_ADC0_AIN9) +#define PORT_PA09B_ADC0_AIN9 (_UL_(1) << 9) +#define PIN_PA10B_ADC0_AIN10 _L_(10) /**< \brief ADC0 signal: AIN10 on PA10 mux B */ +#define MUX_PA10B_ADC0_AIN10 _L_(1) +#define PINMUX_PA10B_ADC0_AIN10 ((PIN_PA10B_ADC0_AIN10 << 16) | MUX_PA10B_ADC0_AIN10) +#define PORT_PA10B_ADC0_AIN10 (_UL_(1) << 10) +#define PIN_PA11B_ADC0_AIN11 _L_(11) /**< \brief ADC0 signal: AIN11 on PA11 mux B */ +#define MUX_PA11B_ADC0_AIN11 _L_(1) +#define PINMUX_PA11B_ADC0_AIN11 ((PIN_PA11B_ADC0_AIN11 << 16) | MUX_PA11B_ADC0_AIN11) +#define PORT_PA11B_ADC0_AIN11 (_UL_(1) << 11) +#define PIN_PB00B_ADC0_AIN12 _L_(32) /**< \brief ADC0 signal: AIN12 on PB00 mux B */ +#define MUX_PB00B_ADC0_AIN12 _L_(1) +#define PINMUX_PB00B_ADC0_AIN12 ((PIN_PB00B_ADC0_AIN12 << 16) | MUX_PB00B_ADC0_AIN12) +#define PORT_PB00B_ADC0_AIN12 (_UL_(1) << 0) +#define PIN_PB01B_ADC0_AIN13 _L_(33) /**< \brief ADC0 signal: AIN13 on PB01 mux B */ +#define MUX_PB01B_ADC0_AIN13 _L_(1) +#define PINMUX_PB01B_ADC0_AIN13 ((PIN_PB01B_ADC0_AIN13 << 16) | MUX_PB01B_ADC0_AIN13) +#define PORT_PB01B_ADC0_AIN13 (_UL_(1) << 1) +#define PIN_PB02B_ADC0_AIN14 _L_(34) /**< \brief ADC0 signal: AIN14 on PB02 mux B */ +#define MUX_PB02B_ADC0_AIN14 _L_(1) +#define PINMUX_PB02B_ADC0_AIN14 ((PIN_PB02B_ADC0_AIN14 << 16) | MUX_PB02B_ADC0_AIN14) +#define PORT_PB02B_ADC0_AIN14 (_UL_(1) << 2) +#define PIN_PB03B_ADC0_AIN15 _L_(35) /**< \brief ADC0 signal: AIN15 on PB03 mux B */ +#define MUX_PB03B_ADC0_AIN15 _L_(1) +#define PINMUX_PB03B_ADC0_AIN15 ((PIN_PB03B_ADC0_AIN15 << 16) | MUX_PB03B_ADC0_AIN15) +#define PORT_PB03B_ADC0_AIN15 (_UL_(1) << 3) +#define PIN_PA03O_ADC0_DRV0 _L_(3) /**< \brief ADC0 signal: DRV0 on PA03 mux O */ +#define MUX_PA03O_ADC0_DRV0 _L_(14) +#define PINMUX_PA03O_ADC0_DRV0 ((PIN_PA03O_ADC0_DRV0 << 16) | MUX_PA03O_ADC0_DRV0) +#define PORT_PA03O_ADC0_DRV0 (_UL_(1) << 3) +#define PIN_PB08O_ADC0_DRV1 _L_(40) /**< \brief ADC0 signal: DRV1 on PB08 mux O */ +#define MUX_PB08O_ADC0_DRV1 _L_(14) +#define PINMUX_PB08O_ADC0_DRV1 ((PIN_PB08O_ADC0_DRV1 << 16) | MUX_PB08O_ADC0_DRV1) +#define PORT_PB08O_ADC0_DRV1 (_UL_(1) << 8) +#define PIN_PB09O_ADC0_DRV2 _L_(41) /**< \brief ADC0 signal: DRV2 on PB09 mux O */ +#define MUX_PB09O_ADC0_DRV2 _L_(14) +#define PINMUX_PB09O_ADC0_DRV2 ((PIN_PB09O_ADC0_DRV2 << 16) | MUX_PB09O_ADC0_DRV2) +#define PORT_PB09O_ADC0_DRV2 (_UL_(1) << 9) +#define PIN_PA04O_ADC0_DRV3 _L_(4) /**< \brief ADC0 signal: DRV3 on PA04 mux O */ +#define MUX_PA04O_ADC0_DRV3 _L_(14) +#define PINMUX_PA04O_ADC0_DRV3 ((PIN_PA04O_ADC0_DRV3 << 16) | MUX_PA04O_ADC0_DRV3) +#define PORT_PA04O_ADC0_DRV3 (_UL_(1) << 4) +#define PIN_PA06O_ADC0_DRV4 _L_(6) /**< \brief ADC0 signal: DRV4 on PA06 mux O */ +#define MUX_PA06O_ADC0_DRV4 _L_(14) +#define PINMUX_PA06O_ADC0_DRV4 ((PIN_PA06O_ADC0_DRV4 << 16) | MUX_PA06O_ADC0_DRV4) +#define PORT_PA06O_ADC0_DRV4 (_UL_(1) << 6) +#define PIN_PA07O_ADC0_DRV5 _L_(7) /**< \brief ADC0 signal: DRV5 on PA07 mux O */ +#define MUX_PA07O_ADC0_DRV5 _L_(14) +#define PINMUX_PA07O_ADC0_DRV5 ((PIN_PA07O_ADC0_DRV5 << 16) | MUX_PA07O_ADC0_DRV5) +#define PORT_PA07O_ADC0_DRV5 (_UL_(1) << 7) +#define PIN_PA08O_ADC0_DRV6 _L_(8) /**< \brief ADC0 signal: DRV6 on PA08 mux O */ +#define MUX_PA08O_ADC0_DRV6 _L_(14) +#define PINMUX_PA08O_ADC0_DRV6 ((PIN_PA08O_ADC0_DRV6 << 16) | MUX_PA08O_ADC0_DRV6) +#define PORT_PA08O_ADC0_DRV6 (_UL_(1) << 8) +#define PIN_PA09O_ADC0_DRV7 _L_(9) /**< \brief ADC0 signal: DRV7 on PA09 mux O */ +#define MUX_PA09O_ADC0_DRV7 _L_(14) +#define PINMUX_PA09O_ADC0_DRV7 ((PIN_PA09O_ADC0_DRV7 << 16) | MUX_PA09O_ADC0_DRV7) +#define PORT_PA09O_ADC0_DRV7 (_UL_(1) << 9) +#define PIN_PA10O_ADC0_DRV8 _L_(10) /**< \brief ADC0 signal: DRV8 on PA10 mux O */ +#define MUX_PA10O_ADC0_DRV8 _L_(14) +#define PINMUX_PA10O_ADC0_DRV8 ((PIN_PA10O_ADC0_DRV8 << 16) | MUX_PA10O_ADC0_DRV8) +#define PORT_PA10O_ADC0_DRV8 (_UL_(1) << 10) +#define PIN_PA11O_ADC0_DRV9 _L_(11) /**< \brief ADC0 signal: DRV9 on PA11 mux O */ +#define MUX_PA11O_ADC0_DRV9 _L_(14) +#define PINMUX_PA11O_ADC0_DRV9 ((PIN_PA11O_ADC0_DRV9 << 16) | MUX_PA11O_ADC0_DRV9) +#define PORT_PA11O_ADC0_DRV9 (_UL_(1) << 11) +#define PIN_PA16O_ADC0_DRV10 _L_(16) /**< \brief ADC0 signal: DRV10 on PA16 mux O */ +#define MUX_PA16O_ADC0_DRV10 _L_(14) +#define PINMUX_PA16O_ADC0_DRV10 ((PIN_PA16O_ADC0_DRV10 << 16) | MUX_PA16O_ADC0_DRV10) +#define PORT_PA16O_ADC0_DRV10 (_UL_(1) << 16) +#define PIN_PA17O_ADC0_DRV11 _L_(17) /**< \brief ADC0 signal: DRV11 on PA17 mux O */ +#define MUX_PA17O_ADC0_DRV11 _L_(14) +#define PINMUX_PA17O_ADC0_DRV11 ((PIN_PA17O_ADC0_DRV11 << 16) | MUX_PA17O_ADC0_DRV11) +#define PORT_PA17O_ADC0_DRV11 (_UL_(1) << 17) +#define PIN_PA18O_ADC0_DRV12 _L_(18) /**< \brief ADC0 signal: DRV12 on PA18 mux O */ +#define MUX_PA18O_ADC0_DRV12 _L_(14) +#define PINMUX_PA18O_ADC0_DRV12 ((PIN_PA18O_ADC0_DRV12 << 16) | MUX_PA18O_ADC0_DRV12) +#define PORT_PA18O_ADC0_DRV12 (_UL_(1) << 18) +#define PIN_PA19O_ADC0_DRV13 _L_(19) /**< \brief ADC0 signal: DRV13 on PA19 mux O */ +#define MUX_PA19O_ADC0_DRV13 _L_(14) +#define PINMUX_PA19O_ADC0_DRV13 ((PIN_PA19O_ADC0_DRV13 << 16) | MUX_PA19O_ADC0_DRV13) +#define PORT_PA19O_ADC0_DRV13 (_UL_(1) << 19) +#define PIN_PA20O_ADC0_DRV14 _L_(20) /**< \brief ADC0 signal: DRV14 on PA20 mux O */ +#define MUX_PA20O_ADC0_DRV14 _L_(14) +#define PINMUX_PA20O_ADC0_DRV14 ((PIN_PA20O_ADC0_DRV14 << 16) | MUX_PA20O_ADC0_DRV14) +#define PORT_PA20O_ADC0_DRV14 (_UL_(1) << 20) +#define PIN_PA21O_ADC0_DRV15 _L_(21) /**< \brief ADC0 signal: DRV15 on PA21 mux O */ +#define MUX_PA21O_ADC0_DRV15 _L_(14) +#define PINMUX_PA21O_ADC0_DRV15 ((PIN_PA21O_ADC0_DRV15 << 16) | MUX_PA21O_ADC0_DRV15) +#define PORT_PA21O_ADC0_DRV15 (_UL_(1) << 21) +#define PIN_PA22O_ADC0_DRV16 _L_(22) /**< \brief ADC0 signal: DRV16 on PA22 mux O */ +#define MUX_PA22O_ADC0_DRV16 _L_(14) +#define PINMUX_PA22O_ADC0_DRV16 ((PIN_PA22O_ADC0_DRV16 << 16) | MUX_PA22O_ADC0_DRV16) +#define PORT_PA22O_ADC0_DRV16 (_UL_(1) << 22) +#define PIN_PA23O_ADC0_DRV17 _L_(23) /**< \brief ADC0 signal: DRV17 on PA23 mux O */ +#define MUX_PA23O_ADC0_DRV17 _L_(14) +#define PINMUX_PA23O_ADC0_DRV17 ((PIN_PA23O_ADC0_DRV17 << 16) | MUX_PA23O_ADC0_DRV17) +#define PORT_PA23O_ADC0_DRV17 (_UL_(1) << 23) +#define PIN_PA27O_ADC0_DRV18 _L_(27) /**< \brief ADC0 signal: DRV18 on PA27 mux O */ +#define MUX_PA27O_ADC0_DRV18 _L_(14) +#define PINMUX_PA27O_ADC0_DRV18 ((PIN_PA27O_ADC0_DRV18 << 16) | MUX_PA27O_ADC0_DRV18) +#define PORT_PA27O_ADC0_DRV18 (_UL_(1) << 27) +#define PIN_PA30O_ADC0_DRV19 _L_(30) /**< \brief ADC0 signal: DRV19 on PA30 mux O */ +#define MUX_PA30O_ADC0_DRV19 _L_(14) +#define PINMUX_PA30O_ADC0_DRV19 ((PIN_PA30O_ADC0_DRV19 << 16) | MUX_PA30O_ADC0_DRV19) +#define PORT_PA30O_ADC0_DRV19 (_UL_(1) << 30) +#define PIN_PB02O_ADC0_DRV20 _L_(34) /**< \brief ADC0 signal: DRV20 on PB02 mux O */ +#define MUX_PB02O_ADC0_DRV20 _L_(14) +#define PINMUX_PB02O_ADC0_DRV20 ((PIN_PB02O_ADC0_DRV20 << 16) | MUX_PB02O_ADC0_DRV20) +#define PORT_PB02O_ADC0_DRV20 (_UL_(1) << 2) +#define PIN_PB03O_ADC0_DRV21 _L_(35) /**< \brief ADC0 signal: DRV21 on PB03 mux O */ +#define MUX_PB03O_ADC0_DRV21 _L_(14) +#define PINMUX_PB03O_ADC0_DRV21 ((PIN_PB03O_ADC0_DRV21 << 16) | MUX_PB03O_ADC0_DRV21) +#define PORT_PB03O_ADC0_DRV21 (_UL_(1) << 3) +#define PIN_PB04O_ADC0_DRV22 _L_(36) /**< \brief ADC0 signal: DRV22 on PB04 mux O */ +#define MUX_PB04O_ADC0_DRV22 _L_(14) +#define PINMUX_PB04O_ADC0_DRV22 ((PIN_PB04O_ADC0_DRV22 << 16) | MUX_PB04O_ADC0_DRV22) +#define PORT_PB04O_ADC0_DRV22 (_UL_(1) << 4) +#define PIN_PB05O_ADC0_DRV23 _L_(37) /**< \brief ADC0 signal: DRV23 on PB05 mux O */ +#define MUX_PB05O_ADC0_DRV23 _L_(14) +#define PINMUX_PB05O_ADC0_DRV23 ((PIN_PB05O_ADC0_DRV23 << 16) | MUX_PB05O_ADC0_DRV23) +#define PORT_PB05O_ADC0_DRV23 (_UL_(1) << 5) +#define PIN_PB06O_ADC0_DRV24 _L_(38) /**< \brief ADC0 signal: DRV24 on PB06 mux O */ +#define MUX_PB06O_ADC0_DRV24 _L_(14) +#define PINMUX_PB06O_ADC0_DRV24 ((PIN_PB06O_ADC0_DRV24 << 16) | MUX_PB06O_ADC0_DRV24) +#define PORT_PB06O_ADC0_DRV24 (_UL_(1) << 6) +#define PIN_PB07O_ADC0_DRV25 _L_(39) /**< \brief ADC0 signal: DRV25 on PB07 mux O */ +#define MUX_PB07O_ADC0_DRV25 _L_(14) +#define PINMUX_PB07O_ADC0_DRV25 ((PIN_PB07O_ADC0_DRV25 << 16) | MUX_PB07O_ADC0_DRV25) +#define PORT_PB07O_ADC0_DRV25 (_UL_(1) << 7) +#define PIN_PB12O_ADC0_DRV26 _L_(44) /**< \brief ADC0 signal: DRV26 on PB12 mux O */ +#define MUX_PB12O_ADC0_DRV26 _L_(14) +#define PINMUX_PB12O_ADC0_DRV26 ((PIN_PB12O_ADC0_DRV26 << 16) | MUX_PB12O_ADC0_DRV26) +#define PORT_PB12O_ADC0_DRV26 (_UL_(1) << 12) +#define PIN_PB13O_ADC0_DRV27 _L_(45) /**< \brief ADC0 signal: DRV27 on PB13 mux O */ +#define MUX_PB13O_ADC0_DRV27 _L_(14) +#define PINMUX_PB13O_ADC0_DRV27 ((PIN_PB13O_ADC0_DRV27 << 16) | MUX_PB13O_ADC0_DRV27) +#define PORT_PB13O_ADC0_DRV27 (_UL_(1) << 13) +#define PIN_PB14O_ADC0_DRV28 _L_(46) /**< \brief ADC0 signal: DRV28 on PB14 mux O */ +#define MUX_PB14O_ADC0_DRV28 _L_(14) +#define PINMUX_PB14O_ADC0_DRV28 ((PIN_PB14O_ADC0_DRV28 << 16) | MUX_PB14O_ADC0_DRV28) +#define PORT_PB14O_ADC0_DRV28 (_UL_(1) << 14) +#define PIN_PB15O_ADC0_DRV29 _L_(47) /**< \brief ADC0 signal: DRV29 on PB15 mux O */ +#define MUX_PB15O_ADC0_DRV29 _L_(14) +#define PINMUX_PB15O_ADC0_DRV29 ((PIN_PB15O_ADC0_DRV29 << 16) | MUX_PB15O_ADC0_DRV29) +#define PORT_PB15O_ADC0_DRV29 (_UL_(1) << 15) +#define PIN_PB00O_ADC0_DRV30 _L_(32) /**< \brief ADC0 signal: DRV30 on PB00 mux O */ +#define MUX_PB00O_ADC0_DRV30 _L_(14) +#define PINMUX_PB00O_ADC0_DRV30 ((PIN_PB00O_ADC0_DRV30 << 16) | MUX_PB00O_ADC0_DRV30) +#define PORT_PB00O_ADC0_DRV30 (_UL_(1) << 0) +#define PIN_PB01O_ADC0_DRV31 _L_(33) /**< \brief ADC0 signal: DRV31 on PB01 mux O */ +#define MUX_PB01O_ADC0_DRV31 _L_(14) +#define PINMUX_PB01O_ADC0_DRV31 ((PIN_PB01O_ADC0_DRV31 << 16) | MUX_PB01O_ADC0_DRV31) +#define PORT_PB01O_ADC0_DRV31 (_UL_(1) << 1) +#define PIN_PA03B_ADC0_PTCXY0 _L_(3) /**< \brief ADC0 signal: PTCXY0 on PA03 mux B */ +#define MUX_PA03B_ADC0_PTCXY0 _L_(1) +#define PINMUX_PA03B_ADC0_PTCXY0 ((PIN_PA03B_ADC0_PTCXY0 << 16) | MUX_PA03B_ADC0_PTCXY0) +#define PORT_PA03B_ADC0_PTCXY0 (_UL_(1) << 3) +#define PIN_PB08B_ADC0_PTCXY1 _L_(40) /**< \brief ADC0 signal: PTCXY1 on PB08 mux B */ +#define MUX_PB08B_ADC0_PTCXY1 _L_(1) +#define PINMUX_PB08B_ADC0_PTCXY1 ((PIN_PB08B_ADC0_PTCXY1 << 16) | MUX_PB08B_ADC0_PTCXY1) +#define PORT_PB08B_ADC0_PTCXY1 (_UL_(1) << 8) +#define PIN_PB09B_ADC0_PTCXY2 _L_(41) /**< \brief ADC0 signal: PTCXY2 on PB09 mux B */ +#define MUX_PB09B_ADC0_PTCXY2 _L_(1) +#define PINMUX_PB09B_ADC0_PTCXY2 ((PIN_PB09B_ADC0_PTCXY2 << 16) | MUX_PB09B_ADC0_PTCXY2) +#define PORT_PB09B_ADC0_PTCXY2 (_UL_(1) << 9) +#define PIN_PA04B_ADC0_PTCXY3 _L_(4) /**< \brief ADC0 signal: PTCXY3 on PA04 mux B */ +#define MUX_PA04B_ADC0_PTCXY3 _L_(1) +#define PINMUX_PA04B_ADC0_PTCXY3 ((PIN_PA04B_ADC0_PTCXY3 << 16) | MUX_PA04B_ADC0_PTCXY3) +#define PORT_PA04B_ADC0_PTCXY3 (_UL_(1) << 4) +#define PIN_PA06B_ADC0_PTCXY4 _L_(6) /**< \brief ADC0 signal: PTCXY4 on PA06 mux B */ +#define MUX_PA06B_ADC0_PTCXY4 _L_(1) +#define PINMUX_PA06B_ADC0_PTCXY4 ((PIN_PA06B_ADC0_PTCXY4 << 16) | MUX_PA06B_ADC0_PTCXY4) +#define PORT_PA06B_ADC0_PTCXY4 (_UL_(1) << 6) +#define PIN_PA07B_ADC0_PTCXY5 _L_(7) /**< \brief ADC0 signal: PTCXY5 on PA07 mux B */ +#define MUX_PA07B_ADC0_PTCXY5 _L_(1) +#define PINMUX_PA07B_ADC0_PTCXY5 ((PIN_PA07B_ADC0_PTCXY5 << 16) | MUX_PA07B_ADC0_PTCXY5) +#define PORT_PA07B_ADC0_PTCXY5 (_UL_(1) << 7) +#define PIN_PA08B_ADC0_PTCXY6 _L_(8) /**< \brief ADC0 signal: PTCXY6 on PA08 mux B */ +#define MUX_PA08B_ADC0_PTCXY6 _L_(1) +#define PINMUX_PA08B_ADC0_PTCXY6 ((PIN_PA08B_ADC0_PTCXY6 << 16) | MUX_PA08B_ADC0_PTCXY6) +#define PORT_PA08B_ADC0_PTCXY6 (_UL_(1) << 8) +#define PIN_PA09B_ADC0_PTCXY7 _L_(9) /**< \brief ADC0 signal: PTCXY7 on PA09 mux B */ +#define MUX_PA09B_ADC0_PTCXY7 _L_(1) +#define PINMUX_PA09B_ADC0_PTCXY7 ((PIN_PA09B_ADC0_PTCXY7 << 16) | MUX_PA09B_ADC0_PTCXY7) +#define PORT_PA09B_ADC0_PTCXY7 (_UL_(1) << 9) +#define PIN_PA10B_ADC0_PTCXY8 _L_(10) /**< \brief ADC0 signal: PTCXY8 on PA10 mux B */ +#define MUX_PA10B_ADC0_PTCXY8 _L_(1) +#define PINMUX_PA10B_ADC0_PTCXY8 ((PIN_PA10B_ADC0_PTCXY8 << 16) | MUX_PA10B_ADC0_PTCXY8) +#define PORT_PA10B_ADC0_PTCXY8 (_UL_(1) << 10) +#define PIN_PA11B_ADC0_PTCXY9 _L_(11) /**< \brief ADC0 signal: PTCXY9 on PA11 mux B */ +#define MUX_PA11B_ADC0_PTCXY9 _L_(1) +#define PINMUX_PA11B_ADC0_PTCXY9 ((PIN_PA11B_ADC0_PTCXY9 << 16) | MUX_PA11B_ADC0_PTCXY9) +#define PORT_PA11B_ADC0_PTCXY9 (_UL_(1) << 11) +#define PIN_PA16B_ADC0_PTCXY10 _L_(16) /**< \brief ADC0 signal: PTCXY10 on PA16 mux B */ +#define MUX_PA16B_ADC0_PTCXY10 _L_(1) +#define PINMUX_PA16B_ADC0_PTCXY10 ((PIN_PA16B_ADC0_PTCXY10 << 16) | MUX_PA16B_ADC0_PTCXY10) +#define PORT_PA16B_ADC0_PTCXY10 (_UL_(1) << 16) +#define PIN_PA17B_ADC0_PTCXY11 _L_(17) /**< \brief ADC0 signal: PTCXY11 on PA17 mux B */ +#define MUX_PA17B_ADC0_PTCXY11 _L_(1) +#define PINMUX_PA17B_ADC0_PTCXY11 ((PIN_PA17B_ADC0_PTCXY11 << 16) | MUX_PA17B_ADC0_PTCXY11) +#define PORT_PA17B_ADC0_PTCXY11 (_UL_(1) << 17) +#define PIN_PA18B_ADC0_PTCXY12 _L_(18) /**< \brief ADC0 signal: PTCXY12 on PA18 mux B */ +#define MUX_PA18B_ADC0_PTCXY12 _L_(1) +#define PINMUX_PA18B_ADC0_PTCXY12 ((PIN_PA18B_ADC0_PTCXY12 << 16) | MUX_PA18B_ADC0_PTCXY12) +#define PORT_PA18B_ADC0_PTCXY12 (_UL_(1) << 18) +#define PIN_PA19B_ADC0_PTCXY13 _L_(19) /**< \brief ADC0 signal: PTCXY13 on PA19 mux B */ +#define MUX_PA19B_ADC0_PTCXY13 _L_(1) +#define PINMUX_PA19B_ADC0_PTCXY13 ((PIN_PA19B_ADC0_PTCXY13 << 16) | MUX_PA19B_ADC0_PTCXY13) +#define PORT_PA19B_ADC0_PTCXY13 (_UL_(1) << 19) +#define PIN_PA20B_ADC0_PTCXY14 _L_(20) /**< \brief ADC0 signal: PTCXY14 on PA20 mux B */ +#define MUX_PA20B_ADC0_PTCXY14 _L_(1) +#define PINMUX_PA20B_ADC0_PTCXY14 ((PIN_PA20B_ADC0_PTCXY14 << 16) | MUX_PA20B_ADC0_PTCXY14) +#define PORT_PA20B_ADC0_PTCXY14 (_UL_(1) << 20) +#define PIN_PA21B_ADC0_PTCXY15 _L_(21) /**< \brief ADC0 signal: PTCXY15 on PA21 mux B */ +#define MUX_PA21B_ADC0_PTCXY15 _L_(1) +#define PINMUX_PA21B_ADC0_PTCXY15 ((PIN_PA21B_ADC0_PTCXY15 << 16) | MUX_PA21B_ADC0_PTCXY15) +#define PORT_PA21B_ADC0_PTCXY15 (_UL_(1) << 21) +#define PIN_PA22B_ADC0_PTCXY16 _L_(22) /**< \brief ADC0 signal: PTCXY16 on PA22 mux B */ +#define MUX_PA22B_ADC0_PTCXY16 _L_(1) +#define PINMUX_PA22B_ADC0_PTCXY16 ((PIN_PA22B_ADC0_PTCXY16 << 16) | MUX_PA22B_ADC0_PTCXY16) +#define PORT_PA22B_ADC0_PTCXY16 (_UL_(1) << 22) +#define PIN_PA23B_ADC0_PTCXY17 _L_(23) /**< \brief ADC0 signal: PTCXY17 on PA23 mux B */ +#define MUX_PA23B_ADC0_PTCXY17 _L_(1) +#define PINMUX_PA23B_ADC0_PTCXY17 ((PIN_PA23B_ADC0_PTCXY17 << 16) | MUX_PA23B_ADC0_PTCXY17) +#define PORT_PA23B_ADC0_PTCXY17 (_UL_(1) << 23) +#define PIN_PA27B_ADC0_PTCXY18 _L_(27) /**< \brief ADC0 signal: PTCXY18 on PA27 mux B */ +#define MUX_PA27B_ADC0_PTCXY18 _L_(1) +#define PINMUX_PA27B_ADC0_PTCXY18 ((PIN_PA27B_ADC0_PTCXY18 << 16) | MUX_PA27B_ADC0_PTCXY18) +#define PORT_PA27B_ADC0_PTCXY18 (_UL_(1) << 27) +#define PIN_PA30B_ADC0_PTCXY19 _L_(30) /**< \brief ADC0 signal: PTCXY19 on PA30 mux B */ +#define MUX_PA30B_ADC0_PTCXY19 _L_(1) +#define PINMUX_PA30B_ADC0_PTCXY19 ((PIN_PA30B_ADC0_PTCXY19 << 16) | MUX_PA30B_ADC0_PTCXY19) +#define PORT_PA30B_ADC0_PTCXY19 (_UL_(1) << 30) +#define PIN_PB02B_ADC0_PTCXY20 _L_(34) /**< \brief ADC0 signal: PTCXY20 on PB02 mux B */ +#define MUX_PB02B_ADC0_PTCXY20 _L_(1) +#define PINMUX_PB02B_ADC0_PTCXY20 ((PIN_PB02B_ADC0_PTCXY20 << 16) | MUX_PB02B_ADC0_PTCXY20) +#define PORT_PB02B_ADC0_PTCXY20 (_UL_(1) << 2) +#define PIN_PB03B_ADC0_PTCXY21 _L_(35) /**< \brief ADC0 signal: PTCXY21 on PB03 mux B */ +#define MUX_PB03B_ADC0_PTCXY21 _L_(1) +#define PINMUX_PB03B_ADC0_PTCXY21 ((PIN_PB03B_ADC0_PTCXY21 << 16) | MUX_PB03B_ADC0_PTCXY21) +#define PORT_PB03B_ADC0_PTCXY21 (_UL_(1) << 3) +#define PIN_PB04B_ADC0_PTCXY22 _L_(36) /**< \brief ADC0 signal: PTCXY22 on PB04 mux B */ +#define MUX_PB04B_ADC0_PTCXY22 _L_(1) +#define PINMUX_PB04B_ADC0_PTCXY22 ((PIN_PB04B_ADC0_PTCXY22 << 16) | MUX_PB04B_ADC0_PTCXY22) +#define PORT_PB04B_ADC0_PTCXY22 (_UL_(1) << 4) +#define PIN_PB05B_ADC0_PTCXY23 _L_(37) /**< \brief ADC0 signal: PTCXY23 on PB05 mux B */ +#define MUX_PB05B_ADC0_PTCXY23 _L_(1) +#define PINMUX_PB05B_ADC0_PTCXY23 ((PIN_PB05B_ADC0_PTCXY23 << 16) | MUX_PB05B_ADC0_PTCXY23) +#define PORT_PB05B_ADC0_PTCXY23 (_UL_(1) << 5) +#define PIN_PB06B_ADC0_PTCXY24 _L_(38) /**< \brief ADC0 signal: PTCXY24 on PB06 mux B */ +#define MUX_PB06B_ADC0_PTCXY24 _L_(1) +#define PINMUX_PB06B_ADC0_PTCXY24 ((PIN_PB06B_ADC0_PTCXY24 << 16) | MUX_PB06B_ADC0_PTCXY24) +#define PORT_PB06B_ADC0_PTCXY24 (_UL_(1) << 6) +#define PIN_PB07B_ADC0_PTCXY25 _L_(39) /**< \brief ADC0 signal: PTCXY25 on PB07 mux B */ +#define MUX_PB07B_ADC0_PTCXY25 _L_(1) +#define PINMUX_PB07B_ADC0_PTCXY25 ((PIN_PB07B_ADC0_PTCXY25 << 16) | MUX_PB07B_ADC0_PTCXY25) +#define PORT_PB07B_ADC0_PTCXY25 (_UL_(1) << 7) +#define PIN_PB12B_ADC0_PTCXY26 _L_(44) /**< \brief ADC0 signal: PTCXY26 on PB12 mux B */ +#define MUX_PB12B_ADC0_PTCXY26 _L_(1) +#define PINMUX_PB12B_ADC0_PTCXY26 ((PIN_PB12B_ADC0_PTCXY26 << 16) | MUX_PB12B_ADC0_PTCXY26) +#define PORT_PB12B_ADC0_PTCXY26 (_UL_(1) << 12) +#define PIN_PB13B_ADC0_PTCXY27 _L_(45) /**< \brief ADC0 signal: PTCXY27 on PB13 mux B */ +#define MUX_PB13B_ADC0_PTCXY27 _L_(1) +#define PINMUX_PB13B_ADC0_PTCXY27 ((PIN_PB13B_ADC0_PTCXY27 << 16) | MUX_PB13B_ADC0_PTCXY27) +#define PORT_PB13B_ADC0_PTCXY27 (_UL_(1) << 13) +#define PIN_PB14B_ADC0_PTCXY28 _L_(46) /**< \brief ADC0 signal: PTCXY28 on PB14 mux B */ +#define MUX_PB14B_ADC0_PTCXY28 _L_(1) +#define PINMUX_PB14B_ADC0_PTCXY28 ((PIN_PB14B_ADC0_PTCXY28 << 16) | MUX_PB14B_ADC0_PTCXY28) +#define PORT_PB14B_ADC0_PTCXY28 (_UL_(1) << 14) +#define PIN_PB15B_ADC0_PTCXY29 _L_(47) /**< \brief ADC0 signal: PTCXY29 on PB15 mux B */ +#define MUX_PB15B_ADC0_PTCXY29 _L_(1) +#define PINMUX_PB15B_ADC0_PTCXY29 ((PIN_PB15B_ADC0_PTCXY29 << 16) | MUX_PB15B_ADC0_PTCXY29) +#define PORT_PB15B_ADC0_PTCXY29 (_UL_(1) << 15) +#define PIN_PB00B_ADC0_PTCXY30 _L_(32) /**< \brief ADC0 signal: PTCXY30 on PB00 mux B */ +#define MUX_PB00B_ADC0_PTCXY30 _L_(1) +#define PINMUX_PB00B_ADC0_PTCXY30 ((PIN_PB00B_ADC0_PTCXY30 << 16) | MUX_PB00B_ADC0_PTCXY30) +#define PORT_PB00B_ADC0_PTCXY30 (_UL_(1) << 0) +#define PIN_PB01B_ADC0_PTCXY31 _L_(33) /**< \brief ADC0 signal: PTCXY31 on PB01 mux B */ +#define MUX_PB01B_ADC0_PTCXY31 _L_(1) +#define PINMUX_PB01B_ADC0_PTCXY31 ((PIN_PB01B_ADC0_PTCXY31 << 16) | MUX_PB01B_ADC0_PTCXY31) +#define PORT_PB01B_ADC0_PTCXY31 (_UL_(1) << 1) +/* ========== PORT definition for ADC1 peripheral ========== */ +#define PIN_PB08B_ADC1_AIN0 _L_(40) /**< \brief ADC1 signal: AIN0 on PB08 mux B */ +#define MUX_PB08B_ADC1_AIN0 _L_(1) +#define PINMUX_PB08B_ADC1_AIN0 ((PIN_PB08B_ADC1_AIN0 << 16) | MUX_PB08B_ADC1_AIN0) +#define PORT_PB08B_ADC1_AIN0 (_UL_(1) << 8) +#define PIN_PB09B_ADC1_AIN1 _L_(41) /**< \brief ADC1 signal: AIN1 on PB09 mux B */ +#define MUX_PB09B_ADC1_AIN1 _L_(1) +#define PINMUX_PB09B_ADC1_AIN1 ((PIN_PB09B_ADC1_AIN1 << 16) | MUX_PB09B_ADC1_AIN1) +#define PORT_PB09B_ADC1_AIN1 (_UL_(1) << 9) +#define PIN_PA08B_ADC1_AIN2 _L_(8) /**< \brief ADC1 signal: AIN2 on PA08 mux B */ +#define MUX_PA08B_ADC1_AIN2 _L_(1) +#define PINMUX_PA08B_ADC1_AIN2 ((PIN_PA08B_ADC1_AIN2 << 16) | MUX_PA08B_ADC1_AIN2) +#define PORT_PA08B_ADC1_AIN2 (_UL_(1) << 8) +#define PIN_PA09B_ADC1_AIN3 _L_(9) /**< \brief ADC1 signal: AIN3 on PA09 mux B */ +#define MUX_PA09B_ADC1_AIN3 _L_(1) +#define PINMUX_PA09B_ADC1_AIN3 ((PIN_PA09B_ADC1_AIN3 << 16) | MUX_PA09B_ADC1_AIN3) +#define PORT_PA09B_ADC1_AIN3 (_UL_(1) << 9) +#define PIN_PC02B_ADC1_AIN4 _L_(66) /**< \brief ADC1 signal: AIN4 on PC02 mux B */ +#define MUX_PC02B_ADC1_AIN4 _L_(1) +#define PINMUX_PC02B_ADC1_AIN4 ((PIN_PC02B_ADC1_AIN4 << 16) | MUX_PC02B_ADC1_AIN4) +#define PORT_PC02B_ADC1_AIN4 (_UL_(1) << 2) +#define PIN_PC03B_ADC1_AIN5 _L_(67) /**< \brief ADC1 signal: AIN5 on PC03 mux B */ +#define MUX_PC03B_ADC1_AIN5 _L_(1) +#define PINMUX_PC03B_ADC1_AIN5 ((PIN_PC03B_ADC1_AIN5 << 16) | MUX_PC03B_ADC1_AIN5) +#define PORT_PC03B_ADC1_AIN5 (_UL_(1) << 3) +#define PIN_PB04B_ADC1_AIN6 _L_(36) /**< \brief ADC1 signal: AIN6 on PB04 mux B */ +#define MUX_PB04B_ADC1_AIN6 _L_(1) +#define PINMUX_PB04B_ADC1_AIN6 ((PIN_PB04B_ADC1_AIN6 << 16) | MUX_PB04B_ADC1_AIN6) +#define PORT_PB04B_ADC1_AIN6 (_UL_(1) << 4) +#define PIN_PB05B_ADC1_AIN7 _L_(37) /**< \brief ADC1 signal: AIN7 on PB05 mux B */ +#define MUX_PB05B_ADC1_AIN7 _L_(1) +#define PINMUX_PB05B_ADC1_AIN7 ((PIN_PB05B_ADC1_AIN7 << 16) | MUX_PB05B_ADC1_AIN7) +#define PORT_PB05B_ADC1_AIN7 (_UL_(1) << 5) +#define PIN_PB06B_ADC1_AIN8 _L_(38) /**< \brief ADC1 signal: AIN8 on PB06 mux B */ +#define MUX_PB06B_ADC1_AIN8 _L_(1) +#define PINMUX_PB06B_ADC1_AIN8 ((PIN_PB06B_ADC1_AIN8 << 16) | MUX_PB06B_ADC1_AIN8) +#define PORT_PB06B_ADC1_AIN8 (_UL_(1) << 6) +#define PIN_PB07B_ADC1_AIN9 _L_(39) /**< \brief ADC1 signal: AIN9 on PB07 mux B */ +#define MUX_PB07B_ADC1_AIN9 _L_(1) +#define PINMUX_PB07B_ADC1_AIN9 ((PIN_PB07B_ADC1_AIN9 << 16) | MUX_PB07B_ADC1_AIN9) +#define PORT_PB07B_ADC1_AIN9 (_UL_(1) << 7) +#define PIN_PC00B_ADC1_AIN10 _L_(64) /**< \brief ADC1 signal: AIN10 on PC00 mux B */ +#define MUX_PC00B_ADC1_AIN10 _L_(1) +#define PINMUX_PC00B_ADC1_AIN10 ((PIN_PC00B_ADC1_AIN10 << 16) | MUX_PC00B_ADC1_AIN10) +#define PORT_PC00B_ADC1_AIN10 (_UL_(1) << 0) +#define PIN_PC01B_ADC1_AIN11 _L_(65) /**< \brief ADC1 signal: AIN11 on PC01 mux B */ +#define MUX_PC01B_ADC1_AIN11 _L_(1) +#define PINMUX_PC01B_ADC1_AIN11 ((PIN_PC01B_ADC1_AIN11 << 16) | MUX_PC01B_ADC1_AIN11) +#define PORT_PC01B_ADC1_AIN11 (_UL_(1) << 1) +#define PIN_PC30B_ADC1_AIN12 _L_(94) /**< \brief ADC1 signal: AIN12 on PC30 mux B */ +#define MUX_PC30B_ADC1_AIN12 _L_(1) +#define PINMUX_PC30B_ADC1_AIN12 ((PIN_PC30B_ADC1_AIN12 << 16) | MUX_PC30B_ADC1_AIN12) +#define PORT_PC30B_ADC1_AIN12 (_UL_(1) << 30) +#define PIN_PC31B_ADC1_AIN13 _L_(95) /**< \brief ADC1 signal: AIN13 on PC31 mux B */ +#define MUX_PC31B_ADC1_AIN13 _L_(1) +#define PINMUX_PC31B_ADC1_AIN13 ((PIN_PC31B_ADC1_AIN13 << 16) | MUX_PC31B_ADC1_AIN13) +#define PORT_PC31B_ADC1_AIN13 (_UL_(1) << 31) +#define PIN_PD00B_ADC1_AIN14 _L_(96) /**< \brief ADC1 signal: AIN14 on PD00 mux B */ +#define MUX_PD00B_ADC1_AIN14 _L_(1) +#define PINMUX_PD00B_ADC1_AIN14 ((PIN_PD00B_ADC1_AIN14 << 16) | MUX_PD00B_ADC1_AIN14) +#define PORT_PD00B_ADC1_AIN14 (_UL_(1) << 0) +#define PIN_PD01B_ADC1_AIN15 _L_(97) /**< \brief ADC1 signal: AIN15 on PD01 mux B */ +#define MUX_PD01B_ADC1_AIN15 _L_(1) +#define PINMUX_PD01B_ADC1_AIN15 ((PIN_PD01B_ADC1_AIN15 << 16) | MUX_PD01B_ADC1_AIN15) +#define PORT_PD01B_ADC1_AIN15 (_UL_(1) << 1) +/* ========== PORT definition for DAC peripheral ========== */ +#define PIN_PA02B_DAC_VOUT0 _L_(2) /**< \brief DAC signal: VOUT0 on PA02 mux B */ +#define MUX_PA02B_DAC_VOUT0 _L_(1) +#define PINMUX_PA02B_DAC_VOUT0 ((PIN_PA02B_DAC_VOUT0 << 16) | MUX_PA02B_DAC_VOUT0) +#define PORT_PA02B_DAC_VOUT0 (_UL_(1) << 2) +#define PIN_PA05B_DAC_VOUT1 _L_(5) /**< \brief DAC signal: VOUT1 on PA05 mux B */ +#define MUX_PA05B_DAC_VOUT1 _L_(1) +#define PINMUX_PA05B_DAC_VOUT1 ((PIN_PA05B_DAC_VOUT1 << 16) | MUX_PA05B_DAC_VOUT1) +#define PORT_PA05B_DAC_VOUT1 (_UL_(1) << 5) +/* ========== PORT definition for I2S peripheral ========== */ +#define PIN_PA09J_I2S_FS0 _L_(9) /**< \brief I2S signal: FS0 on PA09 mux J */ +#define MUX_PA09J_I2S_FS0 _L_(9) +#define PINMUX_PA09J_I2S_FS0 ((PIN_PA09J_I2S_FS0 << 16) | MUX_PA09J_I2S_FS0) +#define PORT_PA09J_I2S_FS0 (_UL_(1) << 9) +#define PIN_PA20J_I2S_FS0 _L_(20) /**< \brief I2S signal: FS0 on PA20 mux J */ +#define MUX_PA20J_I2S_FS0 _L_(9) +#define PINMUX_PA20J_I2S_FS0 ((PIN_PA20J_I2S_FS0 << 16) | MUX_PA20J_I2S_FS0) +#define PORT_PA20J_I2S_FS0 (_UL_(1) << 20) +#define PIN_PA23J_I2S_FS1 _L_(23) /**< \brief I2S signal: FS1 on PA23 mux J */ +#define MUX_PA23J_I2S_FS1 _L_(9) +#define PINMUX_PA23J_I2S_FS1 ((PIN_PA23J_I2S_FS1 << 16) | MUX_PA23J_I2S_FS1) +#define PORT_PA23J_I2S_FS1 (_UL_(1) << 23) +#define PIN_PB11J_I2S_FS1 _L_(43) /**< \brief I2S signal: FS1 on PB11 mux J */ +#define MUX_PB11J_I2S_FS1 _L_(9) +#define PINMUX_PB11J_I2S_FS1 ((PIN_PB11J_I2S_FS1 << 16) | MUX_PB11J_I2S_FS1) +#define PORT_PB11J_I2S_FS1 (_UL_(1) << 11) +#define PIN_PA08J_I2S_MCK0 _L_(8) /**< \brief I2S signal: MCK0 on PA08 mux J */ +#define MUX_PA08J_I2S_MCK0 _L_(9) +#define PINMUX_PA08J_I2S_MCK0 ((PIN_PA08J_I2S_MCK0 << 16) | MUX_PA08J_I2S_MCK0) +#define PORT_PA08J_I2S_MCK0 (_UL_(1) << 8) +#define PIN_PB17J_I2S_MCK0 _L_(49) /**< \brief I2S signal: MCK0 on PB17 mux J */ +#define MUX_PB17J_I2S_MCK0 _L_(9) +#define PINMUX_PB17J_I2S_MCK0 ((PIN_PB17J_I2S_MCK0 << 16) | MUX_PB17J_I2S_MCK0) +#define PORT_PB17J_I2S_MCK0 (_UL_(1) << 17) +#define PIN_PB29J_I2S_MCK1 _L_(61) /**< \brief I2S signal: MCK1 on PB29 mux J */ +#define MUX_PB29J_I2S_MCK1 _L_(9) +#define PINMUX_PB29J_I2S_MCK1 ((PIN_PB29J_I2S_MCK1 << 16) | MUX_PB29J_I2S_MCK1) +#define PORT_PB29J_I2S_MCK1 (_UL_(1) << 29) +#define PIN_PB13J_I2S_MCK1 _L_(45) /**< \brief I2S signal: MCK1 on PB13 mux J */ +#define MUX_PB13J_I2S_MCK1 _L_(9) +#define PINMUX_PB13J_I2S_MCK1 ((PIN_PB13J_I2S_MCK1 << 16) | MUX_PB13J_I2S_MCK1) +#define PORT_PB13J_I2S_MCK1 (_UL_(1) << 13) +#define PIN_PA10J_I2S_SCK0 _L_(10) /**< \brief I2S signal: SCK0 on PA10 mux J */ +#define MUX_PA10J_I2S_SCK0 _L_(9) +#define PINMUX_PA10J_I2S_SCK0 ((PIN_PA10J_I2S_SCK0 << 16) | MUX_PA10J_I2S_SCK0) +#define PORT_PA10J_I2S_SCK0 (_UL_(1) << 10) +#define PIN_PB16J_I2S_SCK0 _L_(48) /**< \brief I2S signal: SCK0 on PB16 mux J */ +#define MUX_PB16J_I2S_SCK0 _L_(9) +#define PINMUX_PB16J_I2S_SCK0 ((PIN_PB16J_I2S_SCK0 << 16) | MUX_PB16J_I2S_SCK0) +#define PORT_PB16J_I2S_SCK0 (_UL_(1) << 16) +#define PIN_PB28J_I2S_SCK1 _L_(60) /**< \brief I2S signal: SCK1 on PB28 mux J */ +#define MUX_PB28J_I2S_SCK1 _L_(9) +#define PINMUX_PB28J_I2S_SCK1 ((PIN_PB28J_I2S_SCK1 << 16) | MUX_PB28J_I2S_SCK1) +#define PORT_PB28J_I2S_SCK1 (_UL_(1) << 28) +#define PIN_PB12J_I2S_SCK1 _L_(44) /**< \brief I2S signal: SCK1 on PB12 mux J */ +#define MUX_PB12J_I2S_SCK1 _L_(9) +#define PINMUX_PB12J_I2S_SCK1 ((PIN_PB12J_I2S_SCK1 << 16) | MUX_PB12J_I2S_SCK1) +#define PORT_PB12J_I2S_SCK1 (_UL_(1) << 12) +#define PIN_PA22J_I2S_SDI _L_(22) /**< \brief I2S signal: SDI on PA22 mux J */ +#define MUX_PA22J_I2S_SDI _L_(9) +#define PINMUX_PA22J_I2S_SDI ((PIN_PA22J_I2S_SDI << 16) | MUX_PA22J_I2S_SDI) +#define PORT_PA22J_I2S_SDI (_UL_(1) << 22) +#define PIN_PB10J_I2S_SDI _L_(42) /**< \brief I2S signal: SDI on PB10 mux J */ +#define MUX_PB10J_I2S_SDI _L_(9) +#define PINMUX_PB10J_I2S_SDI ((PIN_PB10J_I2S_SDI << 16) | MUX_PB10J_I2S_SDI) +#define PORT_PB10J_I2S_SDI (_UL_(1) << 10) +#define PIN_PA11J_I2S_SDO _L_(11) /**< \brief I2S signal: SDO on PA11 mux J */ +#define MUX_PA11J_I2S_SDO _L_(9) +#define PINMUX_PA11J_I2S_SDO ((PIN_PA11J_I2S_SDO << 16) | MUX_PA11J_I2S_SDO) +#define PORT_PA11J_I2S_SDO (_UL_(1) << 11) +#define PIN_PA21J_I2S_SDO _L_(21) /**< \brief I2S signal: SDO on PA21 mux J */ +#define MUX_PA21J_I2S_SDO _L_(9) +#define PINMUX_PA21J_I2S_SDO ((PIN_PA21J_I2S_SDO << 16) | MUX_PA21J_I2S_SDO) +#define PORT_PA21J_I2S_SDO (_UL_(1) << 21) +/* ========== PORT definition for PCC peripheral ========== */ +#define PIN_PA14K_PCC_CLK _L_(14) /**< \brief PCC signal: CLK on PA14 mux K */ +#define MUX_PA14K_PCC_CLK _L_(10) +#define PINMUX_PA14K_PCC_CLK ((PIN_PA14K_PCC_CLK << 16) | MUX_PA14K_PCC_CLK) +#define PORT_PA14K_PCC_CLK (_UL_(1) << 14) +#define PIN_PA16K_PCC_DATA0 _L_(16) /**< \brief PCC signal: DATA0 on PA16 mux K */ +#define MUX_PA16K_PCC_DATA0 _L_(10) +#define PINMUX_PA16K_PCC_DATA0 ((PIN_PA16K_PCC_DATA0 << 16) | MUX_PA16K_PCC_DATA0) +#define PORT_PA16K_PCC_DATA0 (_UL_(1) << 16) +#define PIN_PA17K_PCC_DATA1 _L_(17) /**< \brief PCC signal: DATA1 on PA17 mux K */ +#define MUX_PA17K_PCC_DATA1 _L_(10) +#define PINMUX_PA17K_PCC_DATA1 ((PIN_PA17K_PCC_DATA1 << 16) | MUX_PA17K_PCC_DATA1) +#define PORT_PA17K_PCC_DATA1 (_UL_(1) << 17) +#define PIN_PA18K_PCC_DATA2 _L_(18) /**< \brief PCC signal: DATA2 on PA18 mux K */ +#define MUX_PA18K_PCC_DATA2 _L_(10) +#define PINMUX_PA18K_PCC_DATA2 ((PIN_PA18K_PCC_DATA2 << 16) | MUX_PA18K_PCC_DATA2) +#define PORT_PA18K_PCC_DATA2 (_UL_(1) << 18) +#define PIN_PA19K_PCC_DATA3 _L_(19) /**< \brief PCC signal: DATA3 on PA19 mux K */ +#define MUX_PA19K_PCC_DATA3 _L_(10) +#define PINMUX_PA19K_PCC_DATA3 ((PIN_PA19K_PCC_DATA3 << 16) | MUX_PA19K_PCC_DATA3) +#define PORT_PA19K_PCC_DATA3 (_UL_(1) << 19) +#define PIN_PA20K_PCC_DATA4 _L_(20) /**< \brief PCC signal: DATA4 on PA20 mux K */ +#define MUX_PA20K_PCC_DATA4 _L_(10) +#define PINMUX_PA20K_PCC_DATA4 ((PIN_PA20K_PCC_DATA4 << 16) | MUX_PA20K_PCC_DATA4) +#define PORT_PA20K_PCC_DATA4 (_UL_(1) << 20) +#define PIN_PA21K_PCC_DATA5 _L_(21) /**< \brief PCC signal: DATA5 on PA21 mux K */ +#define MUX_PA21K_PCC_DATA5 _L_(10) +#define PINMUX_PA21K_PCC_DATA5 ((PIN_PA21K_PCC_DATA5 << 16) | MUX_PA21K_PCC_DATA5) +#define PORT_PA21K_PCC_DATA5 (_UL_(1) << 21) +#define PIN_PA22K_PCC_DATA6 _L_(22) /**< \brief PCC signal: DATA6 on PA22 mux K */ +#define MUX_PA22K_PCC_DATA6 _L_(10) +#define PINMUX_PA22K_PCC_DATA6 ((PIN_PA22K_PCC_DATA6 << 16) | MUX_PA22K_PCC_DATA6) +#define PORT_PA22K_PCC_DATA6 (_UL_(1) << 22) +#define PIN_PA23K_PCC_DATA7 _L_(23) /**< \brief PCC signal: DATA7 on PA23 mux K */ +#define MUX_PA23K_PCC_DATA7 _L_(10) +#define PINMUX_PA23K_PCC_DATA7 ((PIN_PA23K_PCC_DATA7 << 16) | MUX_PA23K_PCC_DATA7) +#define PORT_PA23K_PCC_DATA7 (_UL_(1) << 23) +#define PIN_PB14K_PCC_DATA8 _L_(46) /**< \brief PCC signal: DATA8 on PB14 mux K */ +#define MUX_PB14K_PCC_DATA8 _L_(10) +#define PINMUX_PB14K_PCC_DATA8 ((PIN_PB14K_PCC_DATA8 << 16) | MUX_PB14K_PCC_DATA8) +#define PORT_PB14K_PCC_DATA8 (_UL_(1) << 14) +#define PIN_PB15K_PCC_DATA9 _L_(47) /**< \brief PCC signal: DATA9 on PB15 mux K */ +#define MUX_PB15K_PCC_DATA9 _L_(10) +#define PINMUX_PB15K_PCC_DATA9 ((PIN_PB15K_PCC_DATA9 << 16) | MUX_PB15K_PCC_DATA9) +#define PORT_PB15K_PCC_DATA9 (_UL_(1) << 15) +#define PIN_PC12K_PCC_DATA10 _L_(76) /**< \brief PCC signal: DATA10 on PC12 mux K */ +#define MUX_PC12K_PCC_DATA10 _L_(10) +#define PINMUX_PC12K_PCC_DATA10 ((PIN_PC12K_PCC_DATA10 << 16) | MUX_PC12K_PCC_DATA10) +#define PORT_PC12K_PCC_DATA10 (_UL_(1) << 12) +#define PIN_PC13K_PCC_DATA11 _L_(77) /**< \brief PCC signal: DATA11 on PC13 mux K */ +#define MUX_PC13K_PCC_DATA11 _L_(10) +#define PINMUX_PC13K_PCC_DATA11 ((PIN_PC13K_PCC_DATA11 << 16) | MUX_PC13K_PCC_DATA11) +#define PORT_PC13K_PCC_DATA11 (_UL_(1) << 13) +#define PIN_PC14K_PCC_DATA12 _L_(78) /**< \brief PCC signal: DATA12 on PC14 mux K */ +#define MUX_PC14K_PCC_DATA12 _L_(10) +#define PINMUX_PC14K_PCC_DATA12 ((PIN_PC14K_PCC_DATA12 << 16) | MUX_PC14K_PCC_DATA12) +#define PORT_PC14K_PCC_DATA12 (_UL_(1) << 14) +#define PIN_PC15K_PCC_DATA13 _L_(79) /**< \brief PCC signal: DATA13 on PC15 mux K */ +#define MUX_PC15K_PCC_DATA13 _L_(10) +#define PINMUX_PC15K_PCC_DATA13 ((PIN_PC15K_PCC_DATA13 << 16) | MUX_PC15K_PCC_DATA13) +#define PORT_PC15K_PCC_DATA13 (_UL_(1) << 15) +#define PIN_PA12K_PCC_DEN1 _L_(12) /**< \brief PCC signal: DEN1 on PA12 mux K */ +#define MUX_PA12K_PCC_DEN1 _L_(10) +#define PINMUX_PA12K_PCC_DEN1 ((PIN_PA12K_PCC_DEN1 << 16) | MUX_PA12K_PCC_DEN1) +#define PORT_PA12K_PCC_DEN1 (_UL_(1) << 12) +#define PIN_PA13K_PCC_DEN2 _L_(13) /**< \brief PCC signal: DEN2 on PA13 mux K */ +#define MUX_PA13K_PCC_DEN2 _L_(10) +#define PINMUX_PA13K_PCC_DEN2 ((PIN_PA13K_PCC_DEN2 << 16) | MUX_PA13K_PCC_DEN2) +#define PORT_PA13K_PCC_DEN2 (_UL_(1) << 13) +/* ========== PORT definition for SDHC0 peripheral ========== */ +#define PIN_PA06I_SDHC0_SDCD _L_(6) /**< \brief SDHC0 signal: SDCD on PA06 mux I */ +#define MUX_PA06I_SDHC0_SDCD _L_(8) +#define PINMUX_PA06I_SDHC0_SDCD ((PIN_PA06I_SDHC0_SDCD << 16) | MUX_PA06I_SDHC0_SDCD) +#define PORT_PA06I_SDHC0_SDCD (_UL_(1) << 6) +#define PIN_PA12I_SDHC0_SDCD _L_(12) /**< \brief SDHC0 signal: SDCD on PA12 mux I */ +#define MUX_PA12I_SDHC0_SDCD _L_(8) +#define PINMUX_PA12I_SDHC0_SDCD ((PIN_PA12I_SDHC0_SDCD << 16) | MUX_PA12I_SDHC0_SDCD) +#define PORT_PA12I_SDHC0_SDCD (_UL_(1) << 12) +#define PIN_PB12I_SDHC0_SDCD _L_(44) /**< \brief SDHC0 signal: SDCD on PB12 mux I */ +#define MUX_PB12I_SDHC0_SDCD _L_(8) +#define PINMUX_PB12I_SDHC0_SDCD ((PIN_PB12I_SDHC0_SDCD << 16) | MUX_PB12I_SDHC0_SDCD) +#define PORT_PB12I_SDHC0_SDCD (_UL_(1) << 12) +#define PIN_PC06I_SDHC0_SDCD _L_(70) /**< \brief SDHC0 signal: SDCD on PC06 mux I */ +#define MUX_PC06I_SDHC0_SDCD _L_(8) +#define PINMUX_PC06I_SDHC0_SDCD ((PIN_PC06I_SDHC0_SDCD << 16) | MUX_PC06I_SDHC0_SDCD) +#define PORT_PC06I_SDHC0_SDCD (_UL_(1) << 6) +#define PIN_PB11I_SDHC0_SDCK _L_(43) /**< \brief SDHC0 signal: SDCK on PB11 mux I */ +#define MUX_PB11I_SDHC0_SDCK _L_(8) +#define PINMUX_PB11I_SDHC0_SDCK ((PIN_PB11I_SDHC0_SDCK << 16) | MUX_PB11I_SDHC0_SDCK) +#define PORT_PB11I_SDHC0_SDCK (_UL_(1) << 11) +#define PIN_PA08I_SDHC0_SDCMD _L_(8) /**< \brief SDHC0 signal: SDCMD on PA08 mux I */ +#define MUX_PA08I_SDHC0_SDCMD _L_(8) +#define PINMUX_PA08I_SDHC0_SDCMD ((PIN_PA08I_SDHC0_SDCMD << 16) | MUX_PA08I_SDHC0_SDCMD) +#define PORT_PA08I_SDHC0_SDCMD (_UL_(1) << 8) +#define PIN_PA09I_SDHC0_SDDAT0 _L_(9) /**< \brief SDHC0 signal: SDDAT0 on PA09 mux I */ +#define MUX_PA09I_SDHC0_SDDAT0 _L_(8) +#define PINMUX_PA09I_SDHC0_SDDAT0 ((PIN_PA09I_SDHC0_SDDAT0 << 16) | MUX_PA09I_SDHC0_SDDAT0) +#define PORT_PA09I_SDHC0_SDDAT0 (_UL_(1) << 9) +#define PIN_PA10I_SDHC0_SDDAT1 _L_(10) /**< \brief SDHC0 signal: SDDAT1 on PA10 mux I */ +#define MUX_PA10I_SDHC0_SDDAT1 _L_(8) +#define PINMUX_PA10I_SDHC0_SDDAT1 ((PIN_PA10I_SDHC0_SDDAT1 << 16) | MUX_PA10I_SDHC0_SDDAT1) +#define PORT_PA10I_SDHC0_SDDAT1 (_UL_(1) << 10) +#define PIN_PA11I_SDHC0_SDDAT2 _L_(11) /**< \brief SDHC0 signal: SDDAT2 on PA11 mux I */ +#define MUX_PA11I_SDHC0_SDDAT2 _L_(8) +#define PINMUX_PA11I_SDHC0_SDDAT2 ((PIN_PA11I_SDHC0_SDDAT2 << 16) | MUX_PA11I_SDHC0_SDDAT2) +#define PORT_PA11I_SDHC0_SDDAT2 (_UL_(1) << 11) +#define PIN_PB10I_SDHC0_SDDAT3 _L_(42) /**< \brief SDHC0 signal: SDDAT3 on PB10 mux I */ +#define MUX_PB10I_SDHC0_SDDAT3 _L_(8) +#define PINMUX_PB10I_SDHC0_SDDAT3 ((PIN_PB10I_SDHC0_SDDAT3 << 16) | MUX_PB10I_SDHC0_SDDAT3) +#define PORT_PB10I_SDHC0_SDDAT3 (_UL_(1) << 10) +#define PIN_PA07I_SDHC0_SDWP _L_(7) /**< \brief SDHC0 signal: SDWP on PA07 mux I */ +#define MUX_PA07I_SDHC0_SDWP _L_(8) +#define PINMUX_PA07I_SDHC0_SDWP ((PIN_PA07I_SDHC0_SDWP << 16) | MUX_PA07I_SDHC0_SDWP) +#define PORT_PA07I_SDHC0_SDWP (_UL_(1) << 7) +#define PIN_PA13I_SDHC0_SDWP _L_(13) /**< \brief SDHC0 signal: SDWP on PA13 mux I */ +#define MUX_PA13I_SDHC0_SDWP _L_(8) +#define PINMUX_PA13I_SDHC0_SDWP ((PIN_PA13I_SDHC0_SDWP << 16) | MUX_PA13I_SDHC0_SDWP) +#define PORT_PA13I_SDHC0_SDWP (_UL_(1) << 13) +#define PIN_PB13I_SDHC0_SDWP _L_(45) /**< \brief SDHC0 signal: SDWP on PB13 mux I */ +#define MUX_PB13I_SDHC0_SDWP _L_(8) +#define PINMUX_PB13I_SDHC0_SDWP ((PIN_PB13I_SDHC0_SDWP << 16) | MUX_PB13I_SDHC0_SDWP) +#define PORT_PB13I_SDHC0_SDWP (_UL_(1) << 13) +#define PIN_PC07I_SDHC0_SDWP _L_(71) /**< \brief SDHC0 signal: SDWP on PC07 mux I */ +#define MUX_PC07I_SDHC0_SDWP _L_(8) +#define PINMUX_PC07I_SDHC0_SDWP ((PIN_PC07I_SDHC0_SDWP << 16) | MUX_PC07I_SDHC0_SDWP) +#define PORT_PC07I_SDHC0_SDWP (_UL_(1) << 7) +/* ========== PORT definition for SDHC1 peripheral ========== */ +#define PIN_PB16I_SDHC1_SDCD _L_(48) /**< \brief SDHC1 signal: SDCD on PB16 mux I */ +#define MUX_PB16I_SDHC1_SDCD _L_(8) +#define PINMUX_PB16I_SDHC1_SDCD ((PIN_PB16I_SDHC1_SDCD << 16) | MUX_PB16I_SDHC1_SDCD) +#define PORT_PB16I_SDHC1_SDCD (_UL_(1) << 16) +#define PIN_PC20I_SDHC1_SDCD _L_(84) /**< \brief SDHC1 signal: SDCD on PC20 mux I */ +#define MUX_PC20I_SDHC1_SDCD _L_(8) +#define PINMUX_PC20I_SDHC1_SDCD ((PIN_PC20I_SDHC1_SDCD << 16) | MUX_PC20I_SDHC1_SDCD) +#define PORT_PC20I_SDHC1_SDCD (_UL_(1) << 20) +#define PIN_PD20I_SDHC1_SDCD _L_(116) /**< \brief SDHC1 signal: SDCD on PD20 mux I */ +#define MUX_PD20I_SDHC1_SDCD _L_(8) +#define PINMUX_PD20I_SDHC1_SDCD ((PIN_PD20I_SDHC1_SDCD << 16) | MUX_PD20I_SDHC1_SDCD) +#define PORT_PD20I_SDHC1_SDCD (_UL_(1) << 20) +#define PIN_PA21I_SDHC1_SDCK _L_(21) /**< \brief SDHC1 signal: SDCK on PA21 mux I */ +#define MUX_PA21I_SDHC1_SDCK _L_(8) +#define PINMUX_PA21I_SDHC1_SDCK ((PIN_PA21I_SDHC1_SDCK << 16) | MUX_PA21I_SDHC1_SDCK) +#define PORT_PA21I_SDHC1_SDCK (_UL_(1) << 21) +#define PIN_PA20I_SDHC1_SDCMD _L_(20) /**< \brief SDHC1 signal: SDCMD on PA20 mux I */ +#define MUX_PA20I_SDHC1_SDCMD _L_(8) +#define PINMUX_PA20I_SDHC1_SDCMD ((PIN_PA20I_SDHC1_SDCMD << 16) | MUX_PA20I_SDHC1_SDCMD) +#define PORT_PA20I_SDHC1_SDCMD (_UL_(1) << 20) +#define PIN_PB18I_SDHC1_SDDAT0 _L_(50) /**< \brief SDHC1 signal: SDDAT0 on PB18 mux I */ +#define MUX_PB18I_SDHC1_SDDAT0 _L_(8) +#define PINMUX_PB18I_SDHC1_SDDAT0 ((PIN_PB18I_SDHC1_SDDAT0 << 16) | MUX_PB18I_SDHC1_SDDAT0) +#define PORT_PB18I_SDHC1_SDDAT0 (_UL_(1) << 18) +#define PIN_PB19I_SDHC1_SDDAT1 _L_(51) /**< \brief SDHC1 signal: SDDAT1 on PB19 mux I */ +#define MUX_PB19I_SDHC1_SDDAT1 _L_(8) +#define PINMUX_PB19I_SDHC1_SDDAT1 ((PIN_PB19I_SDHC1_SDDAT1 << 16) | MUX_PB19I_SDHC1_SDDAT1) +#define PORT_PB19I_SDHC1_SDDAT1 (_UL_(1) << 19) +#define PIN_PB20I_SDHC1_SDDAT2 _L_(52) /**< \brief SDHC1 signal: SDDAT2 on PB20 mux I */ +#define MUX_PB20I_SDHC1_SDDAT2 _L_(8) +#define PINMUX_PB20I_SDHC1_SDDAT2 ((PIN_PB20I_SDHC1_SDDAT2 << 16) | MUX_PB20I_SDHC1_SDDAT2) +#define PORT_PB20I_SDHC1_SDDAT2 (_UL_(1) << 20) +#define PIN_PB21I_SDHC1_SDDAT3 _L_(53) /**< \brief SDHC1 signal: SDDAT3 on PB21 mux I */ +#define MUX_PB21I_SDHC1_SDDAT3 _L_(8) +#define PINMUX_PB21I_SDHC1_SDDAT3 ((PIN_PB21I_SDHC1_SDDAT3 << 16) | MUX_PB21I_SDHC1_SDDAT3) +#define PORT_PB21I_SDHC1_SDDAT3 (_UL_(1) << 21) +#define PIN_PB17I_SDHC1_SDWP _L_(49) /**< \brief SDHC1 signal: SDWP on PB17 mux I */ +#define MUX_PB17I_SDHC1_SDWP _L_(8) +#define PINMUX_PB17I_SDHC1_SDWP ((PIN_PB17I_SDHC1_SDWP << 16) | MUX_PB17I_SDHC1_SDWP) +#define PORT_PB17I_SDHC1_SDWP (_UL_(1) << 17) +#define PIN_PC21I_SDHC1_SDWP _L_(85) /**< \brief SDHC1 signal: SDWP on PC21 mux I */ +#define MUX_PC21I_SDHC1_SDWP _L_(8) +#define PINMUX_PC21I_SDHC1_SDWP ((PIN_PC21I_SDHC1_SDWP << 16) | MUX_PC21I_SDHC1_SDWP) +#define PORT_PC21I_SDHC1_SDWP (_UL_(1) << 21) +#define PIN_PD21I_SDHC1_SDWP _L_(117) /**< \brief SDHC1 signal: SDWP on PD21 mux I */ +#define MUX_PD21I_SDHC1_SDWP _L_(8) +#define PINMUX_PD21I_SDHC1_SDWP ((PIN_PD21I_SDHC1_SDWP << 16) | MUX_PD21I_SDHC1_SDWP) +#define PORT_PD21I_SDHC1_SDWP (_UL_(1) << 21) + +#endif /* _SAME54P20A_PIO_ */ diff --git a/arch/arm/SAME54/SAME54A/mcu/inc/sam.h b/arch/arm/SAME54/SAME54A/mcu/inc/sam.h index fe1586ae..310d8abf 100644 --- a/arch/arm/SAME54/SAME54A/mcu/inc/sam.h +++ b/arch/arm/SAME54/SAME54A/mcu/inc/sam.h @@ -1,46 +1,46 @@ -/** - * \file - * - * \brief Top level header file - * - * Copyright (c) 2020 Microchip Technology Inc. - * - * \license_start - * - * \page License - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \license_stop - * - */ - -#ifndef _SAM_ -#define _SAM_ - -#if defined(__SAME54P20A__) || defined(__ATSAME54P20A__) - #include "same54p20a.h" -#elif defined(__SAME54N20A__) || defined(__ATSAME54N20A__) - #include "same54n20a.h" -#elif defined(__SAME54P19A__) || defined(__ATSAME54P19A__) - #include "same54p19a.h" -#elif defined(__SAME54N19A__) || defined(__ATSAME54N19A__) - #include "same54n19a.h" -#else - #error Library does not support the specified device -#endif - -#endif /* _SAM_ */ - +/** + * \file + * + * \brief Top level header file + * + * Copyright (c) 2019 Microchip Technology Inc. + * + * \license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \license_stop + * + */ + +#ifndef _SAM_ +#define _SAM_ + +#if defined(__SAME54N19A__) || defined(__ATSAME54N19A__) + #include "same54n19a.h" +#elif defined(__SAME54N20A__) || defined(__ATSAME54N20A__) + #include "same54n20a.h" +#elif defined(__SAME54P19A__) || defined(__ATSAME54P19A__) + #include "same54p19a.h" +#elif defined(__SAME54P20A__) || defined(__ATSAME54P20A__) + #include "same54p20a.h" +#else + #error Library does not support the specified device +#endif + +#endif /* _SAM_ */ + diff --git a/arch/arm/SAME54/SAME54A/mcu/inc/same54.h b/arch/arm/SAME54/SAME54A/mcu/inc/same54.h new file mode 100644 index 00000000..7da756eb --- /dev/null +++ b/arch/arm/SAME54/SAME54A/mcu/inc/same54.h @@ -0,0 +1,50 @@ +/** + * \file + * + * \brief Top header file for SAME54 + * + * Copyright (c) 2019 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAME54_ +#define _SAME54_ + +/** + * \defgroup SAME54_definitions SAME54 Device Definitions + * \brief SAME54 CMSIS Definitions. + */ + +#if defined(__SAME54N19A__) || defined(__ATSAME54N19A__) + #include "same54n19a.h" +#elif defined(__SAME54N20A__) || defined(__ATSAME54N20A__) + #include "same54n20a.h" +#elif defined(__SAME54P19A__) || defined(__ATSAME54P19A__) + #include "same54p19a.h" +#elif defined(__SAME54P20A__) || defined(__ATSAME54P20A__) + #include "same54p20a.h" +#else + #error Library does not support the specified device. +#endif + +#endif /* _SAME54_ */ diff --git a/arch/arm/SAME54/SAME54A/mcu/inc/same54n19a.h b/arch/arm/SAME54/SAME54A/mcu/inc/same54n19a.h index 34e9d947..cb183bb9 100644 --- a/arch/arm/SAME54/SAME54A/mcu/inc/same54n19a.h +++ b/arch/arm/SAME54/SAME54A/mcu/inc/same54n19a.h @@ -1,1113 +1,1085 @@ -/** - * \brief Header file for ATSAME54N19A - * - * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries. - * - * Subject to your compliance with these terms, you may use Microchip software and any derivatives - * exclusively with Microchip products. It is your responsibility to comply with third party license - * terms applicable to your use of third party software (including open source software) that may - * accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, - * APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND - * FITNESS FOR A PARTICULAR PURPOSE. - * - * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF - * MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT - * EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - */ - -/* file generated from device description version 2020-03-12T17:26:56Z */ -#ifndef _SAME54N19A_H_ -#define _SAME54N19A_H_ - -// Header version uses Semantic Versioning 2.0.0 (https://semver.org/) -#define HEADER_FORMAT_VERSION "2.0.0" - -#define HEADER_FORMAT_VERSION_MAJOR (2) -#define HEADER_FORMAT_VERSION_MINOR (0) - -/** \addtogroup SAME54N19A_definitions SAME54N19A definitions - This file defines all structures and symbols for SAME54N19A: - - registers and bitfields - - peripheral base address - - peripheral ID - - PIO definitions - * @{ - */ - -#ifdef __cplusplus - extern "C" { -#endif - -#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) -# include -#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#if !defined(SKIP_INTEGER_LITERALS) -# if defined(_U_) || defined(_L_) || defined(_UL_) -# error "Integer Literals macros already defined elsewhere" -# endif - -#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) -/* Macros that deal with adding suffixes to integer literal constants for C/C++ */ -# define _U_(x) (x ## U) /**< C code: Unsigned integer literal constant value */ -# define _L_(x) (x ## L) /**< C code: Long integer literal constant value */ -# define _UL_(x) (x ## UL) /**< C code: Unsigned Long integer literal constant value */ - -#else /* Assembler */ - -# define _U_(x) x /**< Assembler: Unsigned integer literal constant value */ -# define _L_(x) x /**< Assembler: Long integer literal constant value */ -# define _UL_(x) x /**< Assembler: Unsigned Long integer literal constant value */ -#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ -#endif /* SKIP_INTEGER_LITERALS */ -/** @} end of Atmel Global Defines */ - -/* ************************************************************************** */ -/* CMSIS DEFINITIONS FOR SAME54N19A */ -/* ************************************************************************** */ -#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) -/** Interrupt Number Definition */ -typedef enum IRQn -{ -/****** CORTEX-M4 Processor Exceptions Numbers ******************************/ - Reset_IRQn = -15, /**< -15 Reset Vector, invoked on Power up and warm reset */ - NonMaskableInt_IRQn = -14, /**< -14 Non maskable Interrupt, cannot be stopped or preempted */ - HardFault_IRQn = -13, /**< -13 Hard Fault, all classes of Fault */ - MemoryManagement_IRQn = -12, /**< -12 Memory Management, MPU mismatch, including Access Violation and No Match */ - BusFault_IRQn = -11, /**< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */ - UsageFault_IRQn = -10, /**< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ - SVCall_IRQn = -5, /**< -5 System Service Call via SVC instruction */ - DebugMonitor_IRQn = -4, /**< -4 Debug Monitor */ - PendSV_IRQn = -2, /**< -2 Pendable request for system service */ - SysTick_IRQn = -1, /**< -1 System Tick Timer */ -/****** SAME54N19A specific Interrupt Numbers ***********************************/ - PM_IRQn = 0, /**< 0 Power Manager (PM) */ - MCLK_IRQn = 1, /**< 1 Main Clock (MCLK) */ - OSCCTRL_XOSC0_IRQn = 2, /**< 2 Oscillators Control (OSCCTRL) */ - OSCCTRL_XOSC1_IRQn = 3, /**< 3 Oscillators Control (OSCCTRL) */ - OSCCTRL_DFLL_IRQn = 4, /**< 4 Oscillators Control (OSCCTRL) */ - OSCCTRL_DPLL0_IRQn = 5, /**< 5 Oscillators Control (OSCCTRL) */ - OSCCTRL_DPLL1_IRQn = 6, /**< 6 Oscillators Control (OSCCTRL) */ - OSC32KCTRL_IRQn = 7, /**< 7 32kHz Oscillators Control (OSC32KCTRL) */ - SUPC_OTHER_IRQn = 8, /**< 8 Supply Controller (SUPC) */ - SUPC_BODDET_IRQn = 9, /**< 9 Supply Controller (SUPC) */ - WDT_IRQn = 10, /**< 10 Watchdog Timer (WDT) */ - RTC_IRQn = 11, /**< 11 Real-Time Counter (RTC) */ - EIC_EXTINT_0_IRQn = 12, /**< 12 External Interrupt Controller (EIC) */ - EIC_EXTINT_1_IRQn = 13, /**< 13 External Interrupt Controller (EIC) */ - EIC_EXTINT_2_IRQn = 14, /**< 14 External Interrupt Controller (EIC) */ - EIC_EXTINT_3_IRQn = 15, /**< 15 External Interrupt Controller (EIC) */ - EIC_EXTINT_4_IRQn = 16, /**< 16 External Interrupt Controller (EIC) */ - EIC_EXTINT_5_IRQn = 17, /**< 17 External Interrupt Controller (EIC) */ - EIC_EXTINT_6_IRQn = 18, /**< 18 External Interrupt Controller (EIC) */ - EIC_EXTINT_7_IRQn = 19, /**< 19 External Interrupt Controller (EIC) */ - EIC_EXTINT_8_IRQn = 20, /**< 20 External Interrupt Controller (EIC) */ - EIC_EXTINT_9_IRQn = 21, /**< 21 External Interrupt Controller (EIC) */ - EIC_EXTINT_10_IRQn = 22, /**< 22 External Interrupt Controller (EIC) */ - EIC_EXTINT_11_IRQn = 23, /**< 23 External Interrupt Controller (EIC) */ - EIC_EXTINT_12_IRQn = 24, /**< 24 External Interrupt Controller (EIC) */ - EIC_EXTINT_13_IRQn = 25, /**< 25 External Interrupt Controller (EIC) */ - EIC_EXTINT_14_IRQn = 26, /**< 26 External Interrupt Controller (EIC) */ - EIC_EXTINT_15_IRQn = 27, /**< 27 External Interrupt Controller (EIC) */ - FREQM_IRQn = 28, /**< 28 Frequency Meter (FREQM) */ - NVMCTRL_0_IRQn = 29, /**< 29 Non-Volatile Memory Controller (NVMCTRL) */ - NVMCTRL_1_IRQn = 30, /**< 30 Non-Volatile Memory Controller (NVMCTRL) */ - DMAC_0_IRQn = 31, /**< 31 Direct Memory Access Controller (DMAC) */ - DMAC_1_IRQn = 32, /**< 32 Direct Memory Access Controller (DMAC) */ - DMAC_2_IRQn = 33, /**< 33 Direct Memory Access Controller (DMAC) */ - DMAC_3_IRQn = 34, /**< 34 Direct Memory Access Controller (DMAC) */ - DMAC_OTHER_IRQn = 35, /**< 35 Direct Memory Access Controller (DMAC) */ - EVSYS_0_IRQn = 36, /**< 36 Event System Interface (EVSYS) */ - EVSYS_1_IRQn = 37, /**< 37 Event System Interface (EVSYS) */ - EVSYS_2_IRQn = 38, /**< 38 Event System Interface (EVSYS) */ - EVSYS_3_IRQn = 39, /**< 39 Event System Interface (EVSYS) */ - EVSYS_OTHER_IRQn = 40, /**< 40 Event System Interface (EVSYS) */ - PAC_IRQn = 41, /**< 41 Peripheral Access Controller (PAC) */ - RAMECC_IRQn = 45, /**< 45 RAM ECC (RAMECC) */ - SERCOM0_0_IRQn = 46, /**< 46 Serial Communication Interface (SERCOM0) */ - SERCOM0_1_IRQn = 47, /**< 47 Serial Communication Interface (SERCOM0) */ - SERCOM0_2_IRQn = 48, /**< 48 Serial Communication Interface (SERCOM0) */ - SERCOM0_OTHER_IRQn = 49, /**< 49 Serial Communication Interface (SERCOM0) */ - SERCOM1_0_IRQn = 50, /**< 50 Serial Communication Interface (SERCOM1) */ - SERCOM1_1_IRQn = 51, /**< 51 Serial Communication Interface (SERCOM1) */ - SERCOM1_2_IRQn = 52, /**< 52 Serial Communication Interface (SERCOM1) */ - SERCOM1_OTHER_IRQn = 53, /**< 53 Serial Communication Interface (SERCOM1) */ - SERCOM2_0_IRQn = 54, /**< 54 Serial Communication Interface (SERCOM2) */ - SERCOM2_1_IRQn = 55, /**< 55 Serial Communication Interface (SERCOM2) */ - SERCOM2_2_IRQn = 56, /**< 56 Serial Communication Interface (SERCOM2) */ - SERCOM2_OTHER_IRQn = 57, /**< 57 Serial Communication Interface (SERCOM2) */ - SERCOM3_0_IRQn = 58, /**< 58 Serial Communication Interface (SERCOM3) */ - SERCOM3_1_IRQn = 59, /**< 59 Serial Communication Interface (SERCOM3) */ - SERCOM3_2_IRQn = 60, /**< 60 Serial Communication Interface (SERCOM3) */ - SERCOM3_OTHER_IRQn = 61, /**< 61 Serial Communication Interface (SERCOM3) */ - SERCOM4_0_IRQn = 62, /**< 62 Serial Communication Interface (SERCOM4) */ - SERCOM4_1_IRQn = 63, /**< 63 Serial Communication Interface (SERCOM4) */ - SERCOM4_2_IRQn = 64, /**< 64 Serial Communication Interface (SERCOM4) */ - SERCOM4_OTHER_IRQn = 65, /**< 65 Serial Communication Interface (SERCOM4) */ - SERCOM5_0_IRQn = 66, /**< 66 Serial Communication Interface (SERCOM5) */ - SERCOM5_1_IRQn = 67, /**< 67 Serial Communication Interface (SERCOM5) */ - SERCOM5_2_IRQn = 68, /**< 68 Serial Communication Interface (SERCOM5) */ - SERCOM5_OTHER_IRQn = 69, /**< 69 Serial Communication Interface (SERCOM5) */ - SERCOM6_0_IRQn = 70, /**< 70 Serial Communication Interface (SERCOM6) */ - SERCOM6_1_IRQn = 71, /**< 71 Serial Communication Interface (SERCOM6) */ - SERCOM6_2_IRQn = 72, /**< 72 Serial Communication Interface (SERCOM6) */ - SERCOM6_OTHER_IRQn = 73, /**< 73 Serial Communication Interface (SERCOM6) */ - SERCOM7_0_IRQn = 74, /**< 74 Serial Communication Interface (SERCOM7) */ - SERCOM7_1_IRQn = 75, /**< 75 Serial Communication Interface (SERCOM7) */ - SERCOM7_2_IRQn = 76, /**< 76 Serial Communication Interface (SERCOM7) */ - SERCOM7_OTHER_IRQn = 77, /**< 77 Serial Communication Interface (SERCOM7) */ - CAN0_IRQn = 78, /**< 78 Control Area Network (CAN0) */ - CAN1_IRQn = 79, /**< 79 Control Area Network (CAN1) */ - USB_OTHER_IRQn = 80, /**< 80 Universal Serial Bus (USB) */ - USB_SOF_HSOF_IRQn = 81, /**< 81 Universal Serial Bus (USB) */ - USB_TRCPT0_IRQn = 82, /**< 82 Universal Serial Bus (USB) */ - USB_TRCPT1_IRQn = 83, /**< 83 Universal Serial Bus (USB) */ - GMAC_IRQn = 84, /**< 84 Ethernet MAC (GMAC) */ - TCC0_OTHER_IRQn = 85, /**< 85 Timer Counter Control (TCC0) */ - TCC0_MC0_IRQn = 86, /**< 86 Timer Counter Control (TCC0) */ - TCC0_MC1_IRQn = 87, /**< 87 Timer Counter Control (TCC0) */ - TCC0_MC2_IRQn = 88, /**< 88 Timer Counter Control (TCC0) */ - TCC0_MC3_IRQn = 89, /**< 89 Timer Counter Control (TCC0) */ - TCC0_MC4_IRQn = 90, /**< 90 Timer Counter Control (TCC0) */ - TCC0_MC5_IRQn = 91, /**< 91 Timer Counter Control (TCC0) */ - TCC1_OTHER_IRQn = 92, /**< 92 Timer Counter Control (TCC1) */ - TCC1_MC0_IRQn = 93, /**< 93 Timer Counter Control (TCC1) */ - TCC1_MC1_IRQn = 94, /**< 94 Timer Counter Control (TCC1) */ - TCC1_MC2_IRQn = 95, /**< 95 Timer Counter Control (TCC1) */ - TCC1_MC3_IRQn = 96, /**< 96 Timer Counter Control (TCC1) */ - TCC2_OTHER_IRQn = 97, /**< 97 Timer Counter Control (TCC2) */ - TCC2_MC0_IRQn = 98, /**< 98 Timer Counter Control (TCC2) */ - TCC2_MC1_IRQn = 99, /**< 99 Timer Counter Control (TCC2) */ - TCC2_MC2_IRQn = 100, /**< 100 Timer Counter Control (TCC2) */ - TCC3_OTHER_IRQn = 101, /**< 101 Timer Counter Control (TCC3) */ - TCC3_MC0_IRQn = 102, /**< 102 Timer Counter Control (TCC3) */ - TCC3_MC1_IRQn = 103, /**< 103 Timer Counter Control (TCC3) */ - TCC4_OTHER_IRQn = 104, /**< 104 Timer Counter Control (TCC4) */ - TCC4_MC0_IRQn = 105, /**< 105 Timer Counter Control (TCC4) */ - TCC4_MC1_IRQn = 106, /**< 106 Timer Counter Control (TCC4) */ - TC0_IRQn = 107, /**< 107 Basic Timer Counter (TC0) */ - TC1_IRQn = 108, /**< 108 Basic Timer Counter (TC1) */ - TC2_IRQn = 109, /**< 109 Basic Timer Counter (TC2) */ - TC3_IRQn = 110, /**< 110 Basic Timer Counter (TC3) */ - TC4_IRQn = 111, /**< 111 Basic Timer Counter (TC4) */ - TC5_IRQn = 112, /**< 112 Basic Timer Counter (TC5) */ - TC6_IRQn = 113, /**< 113 Basic Timer Counter (TC6) */ - TC7_IRQn = 114, /**< 114 Basic Timer Counter (TC7) */ - PDEC_OTHER_IRQn = 115, /**< 115 Quadrature Decodeur (PDEC) */ - PDEC_MC0_IRQn = 116, /**< 116 Quadrature Decodeur (PDEC) */ - PDEC_MC1_IRQn = 117, /**< 117 Quadrature Decodeur (PDEC) */ - ADC0_OTHER_IRQn = 118, /**< 118 Analog Digital Converter (ADC0) */ - ADC0_RESRDY_IRQn = 119, /**< 119 Analog Digital Converter (ADC0) */ - ADC1_OTHER_IRQn = 120, /**< 120 Analog Digital Converter (ADC1) */ - ADC1_RESRDY_IRQn = 121, /**< 121 Analog Digital Converter (ADC1) */ - AC_IRQn = 122, /**< 122 Analog Comparators (AC) */ - DAC_OTHER_IRQn = 123, /**< 123 Digital-to-Analog Converter (DAC) */ - DAC_EMPTY_0_IRQn = 124, /**< 124 Digital-to-Analog Converter (DAC) */ - DAC_EMPTY_1_IRQn = 125, /**< 125 Digital-to-Analog Converter (DAC) */ - DAC_RESRDY_0_IRQn = 126, /**< 126 Digital-to-Analog Converter (DAC) */ - DAC_RESRDY_1_IRQn = 127, /**< 127 Digital-to-Analog Converter (DAC) */ - I2S_IRQn = 128, /**< 128 Inter-IC Sound Interface (I2S) */ - PCC_IRQn = 129, /**< 129 Parallel Capture Controller (PCC) */ - AES_IRQn = 130, /**< 130 Advanced Encryption Standard (AES) */ - TRNG_IRQn = 131, /**< 131 True Random Generator (TRNG) */ - ICM_IRQn = 132, /**< 132 Integrity Check Monitor (ICM) */ - PUKCC_IRQn = 133, /**< 133 PUblic-Key Cryptography Controller (PUKCC) */ - QSPI_IRQn = 134, /**< 134 Quad SPI interface (QSPI) */ - SDHC0_IRQn = 135, /**< 135 SD/MMC Host Controller (SDHC0) */ - SDHC1_IRQn = 136, /**< 136 SD/MMC Host Controller (SDHC1) */ - - PERIPH_MAX_IRQn = 136 /**< Max peripheral ID */ -} IRQn_Type; -#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) -typedef struct _DeviceVectors -{ - /* Stack pointer */ - void* pvStack; - /* Cortex-M handlers */ - void* pfnReset_Handler; /* -15 Reset Vector, invoked on Power up and warm reset */ - void* pfnNonMaskableInt_Handler; /* -14 Non maskable Interrupt, cannot be stopped or preempted */ - void* pfnHardFault_Handler; /* -13 Hard Fault, all classes of Fault */ - void* pfnMemoryManagement_Handler; /* -12 Memory Management, MPU mismatch, including Access Violation and No Match */ - void* pfnBusFault_Handler; /* -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */ - void* pfnUsageFault_Handler; /* -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ - void* pvReservedC9; - void* pvReservedC8; - void* pvReservedC7; - void* pvReservedC6; - void* pfnSVCall_Handler; /* -5 System Service Call via SVC instruction */ - void* pfnDebugMonitor_Handler; /* -4 Debug Monitor */ - void* pvReservedC3; - void* pfnPendSV_Handler; /* -2 Pendable request for system service */ - void* pfnSysTick_Handler; /* -1 System Tick Timer */ - - /* Peripheral handlers */ - void* pfnPM_Handler; /* 0 Power Manager (PM) */ - void* pfnMCLK_Handler; /* 1 Main Clock (MCLK) */ - void* pfnOSCCTRL_XOSC0_Handler; /* 2 Oscillators Control (OSCCTRL) */ - void* pfnOSCCTRL_XOSC1_Handler; /* 3 Oscillators Control (OSCCTRL) */ - void* pfnOSCCTRL_DFLL_Handler; /* 4 Oscillators Control (OSCCTRL) */ - void* pfnOSCCTRL_DPLL0_Handler; /* 5 Oscillators Control (OSCCTRL) */ - void* pfnOSCCTRL_DPLL1_Handler; /* 6 Oscillators Control (OSCCTRL) */ - void* pfnOSC32KCTRL_Handler; /* 7 32kHz Oscillators Control (OSC32KCTRL) */ - void* pfnSUPC_OTHER_Handler; /* 8 Supply Controller (SUPC) */ - void* pfnSUPC_BODDET_Handler; /* 9 Supply Controller (SUPC) */ - void* pfnWDT_Handler; /* 10 Watchdog Timer (WDT) */ - void* pfnRTC_Handler; /* 11 Real-Time Counter (RTC) */ - void* pfnEIC_EXTINT_0_Handler; /* 12 External Interrupt Controller (EIC) */ - void* pfnEIC_EXTINT_1_Handler; /* 13 External Interrupt Controller (EIC) */ - void* pfnEIC_EXTINT_2_Handler; /* 14 External Interrupt Controller (EIC) */ - void* pfnEIC_EXTINT_3_Handler; /* 15 External Interrupt Controller (EIC) */ - void* pfnEIC_EXTINT_4_Handler; /* 16 External Interrupt Controller (EIC) */ - void* pfnEIC_EXTINT_5_Handler; /* 17 External Interrupt Controller (EIC) */ - void* pfnEIC_EXTINT_6_Handler; /* 18 External Interrupt Controller (EIC) */ - void* pfnEIC_EXTINT_7_Handler; /* 19 External Interrupt Controller (EIC) */ - void* pfnEIC_EXTINT_8_Handler; /* 20 External Interrupt Controller (EIC) */ - void* pfnEIC_EXTINT_9_Handler; /* 21 External Interrupt Controller (EIC) */ - void* pfnEIC_EXTINT_10_Handler; /* 22 External Interrupt Controller (EIC) */ - void* pfnEIC_EXTINT_11_Handler; /* 23 External Interrupt Controller (EIC) */ - void* pfnEIC_EXTINT_12_Handler; /* 24 External Interrupt Controller (EIC) */ - void* pfnEIC_EXTINT_13_Handler; /* 25 External Interrupt Controller (EIC) */ - void* pfnEIC_EXTINT_14_Handler; /* 26 External Interrupt Controller (EIC) */ - void* pfnEIC_EXTINT_15_Handler; /* 27 External Interrupt Controller (EIC) */ - void* pfnFREQM_Handler; /* 28 Frequency Meter (FREQM) */ - void* pfnNVMCTRL_0_Handler; /* 29 Non-Volatile Memory Controller (NVMCTRL) */ - void* pfnNVMCTRL_1_Handler; /* 30 Non-Volatile Memory Controller (NVMCTRL) */ - void* pfnDMAC_0_Handler; /* 31 Direct Memory Access Controller (DMAC) */ - void* pfnDMAC_1_Handler; /* 32 Direct Memory Access Controller (DMAC) */ - void* pfnDMAC_2_Handler; /* 33 Direct Memory Access Controller (DMAC) */ - void* pfnDMAC_3_Handler; /* 34 Direct Memory Access Controller (DMAC) */ - void* pfnDMAC_OTHER_Handler; /* 35 Direct Memory Access Controller (DMAC) */ - void* pfnEVSYS_0_Handler; /* 36 Event System Interface (EVSYS) */ - void* pfnEVSYS_1_Handler; /* 37 Event System Interface (EVSYS) */ - void* pfnEVSYS_2_Handler; /* 38 Event System Interface (EVSYS) */ - void* pfnEVSYS_3_Handler; /* 39 Event System Interface (EVSYS) */ - void* pfnEVSYS_OTHER_Handler; /* 40 Event System Interface (EVSYS) */ - void* pfnPAC_Handler; /* 41 Peripheral Access Controller (PAC) */ - void* pvReserved42; - void* pvReserved43; - void* pvReserved44; - void* pfnRAMECC_Handler; /* 45 RAM ECC (RAMECC) */ - void* pfnSERCOM0_0_Handler; /* 46 Serial Communication Interface (SERCOM0) */ - void* pfnSERCOM0_1_Handler; /* 47 Serial Communication Interface (SERCOM0) */ - void* pfnSERCOM0_2_Handler; /* 48 Serial Communication Interface (SERCOM0) */ - void* pfnSERCOM0_OTHER_Handler; /* 49 Serial Communication Interface (SERCOM0) */ - void* pfnSERCOM1_0_Handler; /* 50 Serial Communication Interface (SERCOM1) */ - void* pfnSERCOM1_1_Handler; /* 51 Serial Communication Interface (SERCOM1) */ - void* pfnSERCOM1_2_Handler; /* 52 Serial Communication Interface (SERCOM1) */ - void* pfnSERCOM1_OTHER_Handler; /* 53 Serial Communication Interface (SERCOM1) */ - void* pfnSERCOM2_0_Handler; /* 54 Serial Communication Interface (SERCOM2) */ - void* pfnSERCOM2_1_Handler; /* 55 Serial Communication Interface (SERCOM2) */ - void* pfnSERCOM2_2_Handler; /* 56 Serial Communication Interface (SERCOM2) */ - void* pfnSERCOM2_OTHER_Handler; /* 57 Serial Communication Interface (SERCOM2) */ - void* pfnSERCOM3_0_Handler; /* 58 Serial Communication Interface (SERCOM3) */ - void* pfnSERCOM3_1_Handler; /* 59 Serial Communication Interface (SERCOM3) */ - void* pfnSERCOM3_2_Handler; /* 60 Serial Communication Interface (SERCOM3) */ - void* pfnSERCOM3_OTHER_Handler; /* 61 Serial Communication Interface (SERCOM3) */ - void* pfnSERCOM4_0_Handler; /* 62 Serial Communication Interface (SERCOM4) */ - void* pfnSERCOM4_1_Handler; /* 63 Serial Communication Interface (SERCOM4) */ - void* pfnSERCOM4_2_Handler; /* 64 Serial Communication Interface (SERCOM4) */ - void* pfnSERCOM4_OTHER_Handler; /* 65 Serial Communication Interface (SERCOM4) */ - void* pfnSERCOM5_0_Handler; /* 66 Serial Communication Interface (SERCOM5) */ - void* pfnSERCOM5_1_Handler; /* 67 Serial Communication Interface (SERCOM5) */ - void* pfnSERCOM5_2_Handler; /* 68 Serial Communication Interface (SERCOM5) */ - void* pfnSERCOM5_OTHER_Handler; /* 69 Serial Communication Interface (SERCOM5) */ - void* pfnSERCOM6_0_Handler; /* 70 Serial Communication Interface (SERCOM6) */ - void* pfnSERCOM6_1_Handler; /* 71 Serial Communication Interface (SERCOM6) */ - void* pfnSERCOM6_2_Handler; /* 72 Serial Communication Interface (SERCOM6) */ - void* pfnSERCOM6_OTHER_Handler; /* 73 Serial Communication Interface (SERCOM6) */ - void* pfnSERCOM7_0_Handler; /* 74 Serial Communication Interface (SERCOM7) */ - void* pfnSERCOM7_1_Handler; /* 75 Serial Communication Interface (SERCOM7) */ - void* pfnSERCOM7_2_Handler; /* 76 Serial Communication Interface (SERCOM7) */ - void* pfnSERCOM7_OTHER_Handler; /* 77 Serial Communication Interface (SERCOM7) */ - void* pfnCAN0_Handler; /* 78 Control Area Network (CAN0) */ - void* pfnCAN1_Handler; /* 79 Control Area Network (CAN1) */ - void* pfnUSB_OTHER_Handler; /* 80 Universal Serial Bus (USB) */ - void* pfnUSB_SOF_HSOF_Handler; /* 81 Universal Serial Bus (USB) */ - void* pfnUSB_TRCPT0_Handler; /* 82 Universal Serial Bus (USB) */ - void* pfnUSB_TRCPT1_Handler; /* 83 Universal Serial Bus (USB) */ - void* pfnGMAC_Handler; /* 84 Ethernet MAC (GMAC) */ - void* pfnTCC0_OTHER_Handler; /* 85 Timer Counter Control (TCC0) */ - void* pfnTCC0_MC0_Handler; /* 86 Timer Counter Control (TCC0) */ - void* pfnTCC0_MC1_Handler; /* 87 Timer Counter Control (TCC0) */ - void* pfnTCC0_MC2_Handler; /* 88 Timer Counter Control (TCC0) */ - void* pfnTCC0_MC3_Handler; /* 89 Timer Counter Control (TCC0) */ - void* pfnTCC0_MC4_Handler; /* 90 Timer Counter Control (TCC0) */ - void* pfnTCC0_MC5_Handler; /* 91 Timer Counter Control (TCC0) */ - void* pfnTCC1_OTHER_Handler; /* 92 Timer Counter Control (TCC1) */ - void* pfnTCC1_MC0_Handler; /* 93 Timer Counter Control (TCC1) */ - void* pfnTCC1_MC1_Handler; /* 94 Timer Counter Control (TCC1) */ - void* pfnTCC1_MC2_Handler; /* 95 Timer Counter Control (TCC1) */ - void* pfnTCC1_MC3_Handler; /* 96 Timer Counter Control (TCC1) */ - void* pfnTCC2_OTHER_Handler; /* 97 Timer Counter Control (TCC2) */ - void* pfnTCC2_MC0_Handler; /* 98 Timer Counter Control (TCC2) */ - void* pfnTCC2_MC1_Handler; /* 99 Timer Counter Control (TCC2) */ - void* pfnTCC2_MC2_Handler; /* 100 Timer Counter Control (TCC2) */ - void* pfnTCC3_OTHER_Handler; /* 101 Timer Counter Control (TCC3) */ - void* pfnTCC3_MC0_Handler; /* 102 Timer Counter Control (TCC3) */ - void* pfnTCC3_MC1_Handler; /* 103 Timer Counter Control (TCC3) */ - void* pfnTCC4_OTHER_Handler; /* 104 Timer Counter Control (TCC4) */ - void* pfnTCC4_MC0_Handler; /* 105 Timer Counter Control (TCC4) */ - void* pfnTCC4_MC1_Handler; /* 106 Timer Counter Control (TCC4) */ - void* pfnTC0_Handler; /* 107 Basic Timer Counter (TC0) */ - void* pfnTC1_Handler; /* 108 Basic Timer Counter (TC1) */ - void* pfnTC2_Handler; /* 109 Basic Timer Counter (TC2) */ - void* pfnTC3_Handler; /* 110 Basic Timer Counter (TC3) */ - void* pfnTC4_Handler; /* 111 Basic Timer Counter (TC4) */ - void* pfnTC5_Handler; /* 112 Basic Timer Counter (TC5) */ - void* pfnTC6_Handler; /* 113 Basic Timer Counter (TC6) */ - void* pfnTC7_Handler; /* 114 Basic Timer Counter (TC7) */ - void* pfnPDEC_OTHER_Handler; /* 115 Quadrature Decodeur (PDEC) */ - void* pfnPDEC_MC0_Handler; /* 116 Quadrature Decodeur (PDEC) */ - void* pfnPDEC_MC1_Handler; /* 117 Quadrature Decodeur (PDEC) */ - void* pfnADC0_OTHER_Handler; /* 118 Analog Digital Converter (ADC0) */ - void* pfnADC0_RESRDY_Handler; /* 119 Analog Digital Converter (ADC0) */ - void* pfnADC1_OTHER_Handler; /* 120 Analog Digital Converter (ADC1) */ - void* pfnADC1_RESRDY_Handler; /* 121 Analog Digital Converter (ADC1) */ - void* pfnAC_Handler; /* 122 Analog Comparators (AC) */ - void* pfnDAC_OTHER_Handler; /* 123 Digital-to-Analog Converter (DAC) */ - void* pfnDAC_EMPTY_0_Handler; /* 124 Digital-to-Analog Converter (DAC) */ - void* pfnDAC_EMPTY_1_Handler; /* 125 Digital-to-Analog Converter (DAC) */ - void* pfnDAC_RESRDY_0_Handler; /* 126 Digital-to-Analog Converter (DAC) */ - void* pfnDAC_RESRDY_1_Handler; /* 127 Digital-to-Analog Converter (DAC) */ - void* pfnI2S_Handler; /* 128 Inter-IC Sound Interface (I2S) */ - void* pfnPCC_Handler; /* 129 Parallel Capture Controller (PCC) */ - void* pfnAES_Handler; /* 130 Advanced Encryption Standard (AES) */ - void* pfnTRNG_Handler; /* 131 True Random Generator (TRNG) */ - void* pfnICM_Handler; /* 132 Integrity Check Monitor (ICM) */ - void* pfnPUKCC_Handler; /* 133 PUblic-Key Cryptography Controller (PUKCC) */ - void* pfnQSPI_Handler; /* 134 Quad SPI interface (QSPI) */ - void* pfnSDHC0_Handler; /* 135 SD/MMC Host Controller (SDHC0) */ - void* pfnSDHC1_Handler; /* 136 SD/MMC Host Controller (SDHC1) */ -} DeviceVectors; - -/* Defines for Deprecated Interrupt and Exceptions handler names */ -#define pfnMemManage_Handler pfnMemoryManagement_Handler /**< \deprecated Backward compatibility for ASF*/ -#define pfnDebugMon_Handler pfnDebugMonitor_Handler /**< \deprecated Backward compatibility for ASF*/ -#define pfnNMI_Handler pfnNonMaskableInt_Handler /**< \deprecated Backward compatibility for ASF*/ -#define pfnSVC_Handler pfnSVCall_Handler /**< \deprecated Backward compatibility for ASF*/ - -#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) -#if !defined DONT_USE_PREDEFINED_CORE_HANDLERS -/* CORTEX-M4 exception handlers */ -void Reset_Handler ( void ); -void NonMaskableInt_Handler ( void ); -void HardFault_Handler ( void ); -void MemoryManagement_Handler ( void ); -void BusFault_Handler ( void ); -void UsageFault_Handler ( void ); -void SVCall_Handler ( void ); -void DebugMonitor_Handler ( void ); -void PendSV_Handler ( void ); -void SysTick_Handler ( void ); -#endif /* DONT_USE_PREDEFINED_CORE_HANDLERS */ - -#if !defined DONT_USE_PREDEFINED_PERIPHERALS_HANDLERS -/* Peripherals interrupt handlers */ -void PM_Handler ( void ); -void MCLK_Handler ( void ); -void OSCCTRL_XOSC0_Handler ( void ); -void OSCCTRL_XOSC1_Handler ( void ); -void OSCCTRL_DFLL_Handler ( void ); -void OSCCTRL_DPLL0_Handler ( void ); -void OSCCTRL_DPLL1_Handler ( void ); -void OSC32KCTRL_Handler ( void ); -void SUPC_OTHER_Handler ( void ); -void SUPC_BODDET_Handler ( void ); -void WDT_Handler ( void ); -void RTC_Handler ( void ); -void EIC_EXTINT_0_Handler ( void ); -void EIC_EXTINT_1_Handler ( void ); -void EIC_EXTINT_2_Handler ( void ); -void EIC_EXTINT_3_Handler ( void ); -void EIC_EXTINT_4_Handler ( void ); -void EIC_EXTINT_5_Handler ( void ); -void EIC_EXTINT_6_Handler ( void ); -void EIC_EXTINT_7_Handler ( void ); -void EIC_EXTINT_8_Handler ( void ); -void EIC_EXTINT_9_Handler ( void ); -void EIC_EXTINT_10_Handler ( void ); -void EIC_EXTINT_11_Handler ( void ); -void EIC_EXTINT_12_Handler ( void ); -void EIC_EXTINT_13_Handler ( void ); -void EIC_EXTINT_14_Handler ( void ); -void EIC_EXTINT_15_Handler ( void ); -void FREQM_Handler ( void ); -void NVMCTRL_0_Handler ( void ); -void NVMCTRL_1_Handler ( void ); -void DMAC_0_Handler ( void ); -void DMAC_1_Handler ( void ); -void DMAC_2_Handler ( void ); -void DMAC_3_Handler ( void ); -void DMAC_OTHER_Handler ( void ); -void EVSYS_0_Handler ( void ); -void EVSYS_1_Handler ( void ); -void EVSYS_2_Handler ( void ); -void EVSYS_3_Handler ( void ); -void EVSYS_OTHER_Handler ( void ); -void PAC_Handler ( void ); -void RAMECC_Handler ( void ); -void SERCOM0_0_Handler ( void ); -void SERCOM0_1_Handler ( void ); -void SERCOM0_2_Handler ( void ); -void SERCOM0_OTHER_Handler ( void ); -void SERCOM1_0_Handler ( void ); -void SERCOM1_1_Handler ( void ); -void SERCOM1_2_Handler ( void ); -void SERCOM1_OTHER_Handler ( void ); -void SERCOM2_0_Handler ( void ); -void SERCOM2_1_Handler ( void ); -void SERCOM2_2_Handler ( void ); -void SERCOM2_OTHER_Handler ( void ); -void SERCOM3_0_Handler ( void ); -void SERCOM3_1_Handler ( void ); -void SERCOM3_2_Handler ( void ); -void SERCOM3_OTHER_Handler ( void ); -void SERCOM4_0_Handler ( void ); -void SERCOM4_1_Handler ( void ); -void SERCOM4_2_Handler ( void ); -void SERCOM4_OTHER_Handler ( void ); -void SERCOM5_0_Handler ( void ); -void SERCOM5_1_Handler ( void ); -void SERCOM5_2_Handler ( void ); -void SERCOM5_OTHER_Handler ( void ); -void SERCOM6_0_Handler ( void ); -void SERCOM6_1_Handler ( void ); -void SERCOM6_2_Handler ( void ); -void SERCOM6_OTHER_Handler ( void ); -void SERCOM7_0_Handler ( void ); -void SERCOM7_1_Handler ( void ); -void SERCOM7_2_Handler ( void ); -void SERCOM7_OTHER_Handler ( void ); -void CAN0_Handler ( void ); -void CAN1_Handler ( void ); -void USB_OTHER_Handler ( void ); -void USB_SOF_HSOF_Handler ( void ); -void USB_TRCPT0_Handler ( void ); -void USB_TRCPT1_Handler ( void ); -void GMAC_Handler ( void ); -void TCC0_OTHER_Handler ( void ); -void TCC0_MC0_Handler ( void ); -void TCC0_MC1_Handler ( void ); -void TCC0_MC2_Handler ( void ); -void TCC0_MC3_Handler ( void ); -void TCC0_MC4_Handler ( void ); -void TCC0_MC5_Handler ( void ); -void TCC1_OTHER_Handler ( void ); -void TCC1_MC0_Handler ( void ); -void TCC1_MC1_Handler ( void ); -void TCC1_MC2_Handler ( void ); -void TCC1_MC3_Handler ( void ); -void TCC2_OTHER_Handler ( void ); -void TCC2_MC0_Handler ( void ); -void TCC2_MC1_Handler ( void ); -void TCC2_MC2_Handler ( void ); -void TCC3_OTHER_Handler ( void ); -void TCC3_MC0_Handler ( void ); -void TCC3_MC1_Handler ( void ); -void TCC4_OTHER_Handler ( void ); -void TCC4_MC0_Handler ( void ); -void TCC4_MC1_Handler ( void ); -void TC0_Handler ( void ); -void TC1_Handler ( void ); -void TC2_Handler ( void ); -void TC3_Handler ( void ); -void TC4_Handler ( void ); -void TC5_Handler ( void ); -void TC6_Handler ( void ); -void TC7_Handler ( void ); -void PDEC_OTHER_Handler ( void ); -void PDEC_MC0_Handler ( void ); -void PDEC_MC1_Handler ( void ); -void ADC0_OTHER_Handler ( void ); -void ADC0_RESRDY_Handler ( void ); -void ADC1_OTHER_Handler ( void ); -void ADC1_RESRDY_Handler ( void ); -void AC_Handler ( void ); -void DAC_OTHER_Handler ( void ); -void DAC_EMPTY_0_Handler ( void ); -void DAC_EMPTY_1_Handler ( void ); -void DAC_RESRDY_0_Handler ( void ); -void DAC_RESRDY_1_Handler ( void ); -void I2S_Handler ( void ); -void PCC_Handler ( void ); -void AES_Handler ( void ); -void TRNG_Handler ( void ); -void ICM_Handler ( void ); -void PUKCC_Handler ( void ); -void QSPI_Handler ( void ); -void SDHC0_Handler ( void ); -void SDHC1_Handler ( void ); -#endif /* DONT_USE_PREDEFINED_PERIPHERALS_HANDLERS */ -/* Defines for Deprecated Interrupt and Exceptions handler names */ -#define MemManage_Handler MemoryManagement_Handler /**< \deprecated Backward compatibility*/ -#define DebugMon_Handler DebugMonitor_Handler /**< \deprecated Backward compatibility*/ -#define NMI_Handler NonMaskableInt_Handler /**< \deprecated Backward compatibility*/ -#define SVC_Handler SVCall_Handler /**< \deprecated Backward compatibility*/ - -#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/* - * \brief Configuration of the CORTEX-M4 Processor and Core Peripherals - */ -#define __CM4_REV 0x0001 /**< Cortex-M4 Core Revision */ -#define __DEBUG_LVL 3 /**< Debug Level */ -#define __FPU_PRESENT 1 /**< FPU present or not */ -#define __MPU_PRESENT 1 /**< MPU present or not */ -#define __NVIC_PRIO_BITS 3 /**< Number of Bits used for Priority Levels */ -#define __TRACE_LVL 2 /**< Trace Level */ -#define __VTOR_PRESENT 1 /**< Vector Table Offset Register present or not */ -#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */ -#define __ARCH_ARM 1 -#define __ARCH_ARM_CORTEX_M 1 -#define __DEVICE_IS_SAM 1 - -/* - * \brief CMSIS includes - */ -#include "core_cm4.h" -#if defined USE_CMSIS_INIT -#include "system_same54.h" -#endif /* USE_CMSIS_INIT */ - -/** \defgroup SAME54N19A_api Peripheral Software API - * @{ - */ - -/* ************************************************************************** */ -/** SOFTWARE PERIPHERAL API DEFINITION FOR SAME54N19A */ -/* ************************************************************************** */ -#include "component/ac.h" -#include "component/adc.h" -#include "component/aes.h" -#include "component/can.h" -#include "component/ccl.h" -#include "component/cmcc.h" -#include "component/dac.h" -#include "component/dmac.h" -#include "component/dsu.h" -#include "component/eic.h" -#include "component/evsys.h" -#include "component/freqm.h" -#include "component/gclk.h" -#include "component/gmac.h" -#include "component/hmatrixb.h" -#include "component/i2s.h" -#include "component/icm.h" -#include "component/mclk.h" -#include "component/nvmctrl.h" -#include "component/osc32kctrl.h" -#include "component/oscctrl.h" -#include "component/pac.h" -#include "component/pcc.h" -#include "component/pdec.h" -#include "component/pm.h" -#include "component/port.h" -#include "component/pukcc.h" -#include "component/qspi.h" -#include "component/ramecc.h" -#include "component/rstc.h" -#include "component/rtc.h" -#include "component/sdhc.h" -#include "component/sercom.h" -#include "component/supc.h" -#include "component/tc.h" -#include "component/tcc.h" -#include "component/trng.h" -#include "component/usb.h" -#include "component/wdt.h" -/** @} end of Peripheral Software API */ - -/** \addtogroup SAME54N19A_id Peripheral Ids Definitions - * @{ - */ - -/* ************************************************************************** */ -/* PERIPHERAL ID DEFINITIONS FOR SAME54N19A */ -/* ************************************************************************** */ -#define ID_PAC ( 0) /**< \brief Peripheral Access Controller (PAC) */ -#define ID_PM ( 1) /**< \brief Power Manager (PM) */ -#define ID_MCLK ( 2) /**< \brief Main Clock (MCLK) */ -#define ID_RSTC ( 3) /**< \brief Reset Controller (RSTC) */ -#define ID_OSCCTRL ( 4) /**< \brief Oscillators Control (OSCCTRL) */ -#define ID_OSC32KCTRL ( 5) /**< \brief 32kHz Oscillators Control (OSC32KCTRL) */ -#define ID_SUPC ( 6) /**< \brief Supply Controller (SUPC) */ -#define ID_GCLK ( 7) /**< \brief Generic Clock Generator (GCLK) */ -#define ID_WDT ( 8) /**< \brief Watchdog Timer (WDT) */ -#define ID_RTC ( 9) /**< \brief Real-Time Counter (RTC) */ -#define ID_EIC ( 10) /**< \brief External Interrupt Controller (EIC) */ -#define ID_FREQM ( 11) /**< \brief Frequency Meter (FREQM) */ -#define ID_SERCOM0 ( 12) /**< \brief Serial Communication Interface (SERCOM0) */ -#define ID_SERCOM1 ( 13) /**< \brief Serial Communication Interface (SERCOM1) */ -#define ID_TC0 ( 14) /**< \brief Basic Timer Counter (TC0) */ -#define ID_TC1 ( 15) /**< \brief Basic Timer Counter (TC1) */ -#define ID_USB ( 32) /**< \brief Universal Serial Bus (USB) */ -#define ID_DSU ( 33) /**< \brief Device Service Unit (DSU) */ -#define ID_NVMCTRL ( 34) /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ -#define ID_CMCC ( 35) /**< \brief Cortex M Cache Controller (CMCC) */ -#define ID_PORT ( 36) /**< \brief Port Module (PORT) */ -#define ID_DMAC ( 37) /**< \brief Direct Memory Access Controller (DMAC) */ -#define ID_HMATRIX ( 38) /**< \brief HSB Matrix (HMATRIX) */ -#define ID_EVSYS ( 39) /**< \brief Event System Interface (EVSYS) */ -#define ID_SERCOM2 ( 41) /**< \brief Serial Communication Interface (SERCOM2) */ -#define ID_SERCOM3 ( 42) /**< \brief Serial Communication Interface (SERCOM3) */ -#define ID_TCC0 ( 43) /**< \brief Timer Counter Control (TCC0) */ -#define ID_TCC1 ( 44) /**< \brief Timer Counter Control (TCC1) */ -#define ID_TC2 ( 45) /**< \brief Basic Timer Counter (TC2) */ -#define ID_TC3 ( 46) /**< \brief Basic Timer Counter (TC3) */ -#define ID_RAMECC ( 48) /**< \brief RAM ECC (RAMECC) */ -#define ID_CAN0 ( 64) /**< \brief Control Area Network (CAN0) */ -#define ID_CAN1 ( 65) /**< \brief Control Area Network (CAN1) */ -#define ID_GMAC ( 66) /**< \brief Ethernet MAC (GMAC) */ -#define ID_TCC2 ( 67) /**< \brief Timer Counter Control (TCC2) */ -#define ID_TCC3 ( 68) /**< \brief Timer Counter Control (TCC3) */ -#define ID_TC4 ( 69) /**< \brief Basic Timer Counter (TC4) */ -#define ID_TC5 ( 70) /**< \brief Basic Timer Counter (TC5) */ -#define ID_PDEC ( 71) /**< \brief Quadrature Decodeur (PDEC) */ -#define ID_AC ( 72) /**< \brief Analog Comparators (AC) */ -#define ID_AES ( 73) /**< \brief Advanced Encryption Standard (AES) */ -#define ID_TRNG ( 74) /**< \brief True Random Generator (TRNG) */ -#define ID_ICM ( 75) /**< \brief Integrity Check Monitor (ICM) */ -#define ID_PUKCC ( 76) /**< \brief PUblic-Key Cryptography Controller (PUKCC) */ -#define ID_QSPI ( 77) /**< \brief Quad SPI interface (QSPI) */ -#define ID_CCL ( 78) /**< \brief Configurable Custom Logic (CCL) */ -#define ID_SERCOM4 ( 96) /**< \brief Serial Communication Interface (SERCOM4) */ -#define ID_SERCOM5 ( 97) /**< \brief Serial Communication Interface (SERCOM5) */ -#define ID_SERCOM6 ( 98) /**< \brief Serial Communication Interface (SERCOM6) */ -#define ID_SERCOM7 ( 99) /**< \brief Serial Communication Interface (SERCOM7) */ -#define ID_TCC4 (100) /**< \brief Timer Counter Control (TCC4) */ -#define ID_TC6 (101) /**< \brief Basic Timer Counter (TC6) */ -#define ID_TC7 (102) /**< \brief Basic Timer Counter (TC7) */ -#define ID_ADC0 (103) /**< \brief Analog Digital Converter (ADC0) */ -#define ID_ADC1 (104) /**< \brief Analog Digital Converter (ADC1) */ -#define ID_DAC (105) /**< \brief Digital-to-Analog Converter (DAC) */ -#define ID_I2S (106) /**< \brief Inter-IC Sound Interface (I2S) */ -#define ID_PCC (107) /**< \brief Parallel Capture Controller (PCC) */ - -#define ID_PERIPH_MAX (107) /**< \brief Number of peripheral IDs */ -/** @} end of Peripheral Ids Definitions */ - -/** \addtogroup SAME54N19A_base Peripheral Base Address Definitions - * @{ - */ - -/* ************************************************************************** */ -/* REGISTER STRUCTURE ADDRESS DEFINITIONS FOR SAME54N19A */ -/* ************************************************************************** */ -#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) -#define AC_REGS ((ac_registers_t*)0x42002000) /**< \brief AC Registers Address */ -#define ADC0_REGS ((adc_registers_t*)0x43001c00) /**< \brief ADC0 Registers Address */ -#define ADC1_REGS ((adc_registers_t*)0x43002000) /**< \brief ADC1 Registers Address */ -#define AES_REGS ((aes_registers_t*)0x42002400) /**< \brief AES Registers Address */ -#define CAN0_REGS ((can_registers_t*)0x42000000) /**< \brief CAN0 Registers Address */ -#define CAN1_REGS ((can_registers_t*)0x42000400) /**< \brief CAN1 Registers Address */ -#define CCL_REGS ((ccl_registers_t*)0x42003800) /**< \brief CCL Registers Address */ -#define CMCC_REGS ((cmcc_registers_t*)0x41006000) /**< \brief CMCC Registers Address */ -#define DAC_REGS ((dac_registers_t*)0x43002400) /**< \brief DAC Registers Address */ -#define DMAC_REGS ((dmac_registers_t*)0x4100a000) /**< \brief DMAC Registers Address */ -#define DSU_REGS ((dsu_registers_t*)0x41002000) /**< \brief DSU Registers Address */ -#define EIC_REGS ((eic_registers_t*)0x40002800) /**< \brief EIC Registers Address */ -#define EVSYS_REGS ((evsys_registers_t*)0x4100e000) /**< \brief EVSYS Registers Address */ -#define FREQM_REGS ((freqm_registers_t*)0x40002c00) /**< \brief FREQM Registers Address */ -#define GCLK_REGS ((gclk_registers_t*)0x40001c00) /**< \brief GCLK Registers Address */ -#define GMAC_REGS ((gmac_registers_t*)0x42000800) /**< \brief GMAC Registers Address */ -#define HMATRIX_REGS ((hmatrixb_registers_t*)0x4100c000) /**< \brief HMATRIX Registers Address */ -#define ICM_REGS ((icm_registers_t*)0x42002c00) /**< \brief ICM Registers Address */ -#define I2S_REGS ((i2s_registers_t*)0x43002800) /**< \brief I2S Registers Address */ -#define MCLK_REGS ((mclk_registers_t*)0x40000800) /**< \brief MCLK Registers Address */ -#define NVMCTRL_REGS ((nvmctrl_registers_t*)0x41004000) /**< \brief NVMCTRL Registers Address */ -#define OSCCTRL_REGS ((oscctrl_registers_t*)0x40001000) /**< \brief OSCCTRL Registers Address */ -#define OSC32KCTRL_REGS ((osc32kctrl_registers_t*)0x40001400) /**< \brief OSC32KCTRL Registers Address */ -#define PAC_REGS ((pac_registers_t*)0x40000000) /**< \brief PAC Registers Address */ -#define PCC_REGS ((pcc_registers_t*)0x43002c00) /**< \brief PCC Registers Address */ -#define PDEC_REGS ((pdec_registers_t*)0x42001c00) /**< \brief PDEC Registers Address */ -#define PM_REGS ((pm_registers_t*)0x40000400) /**< \brief PM Registers Address */ -#define PORT_REGS ((port_registers_t*)0x41008000) /**< \brief PORT Registers Address */ -#define QSPI_REGS ((qspi_registers_t*)0x42003400) /**< \brief QSPI Registers Address */ -#define RAMECC_REGS ((ramecc_registers_t*)0x41020000) /**< \brief RAMECC Registers Address */ -#define RSTC_REGS ((rstc_registers_t*)0x40000c00) /**< \brief RSTC Registers Address */ -#define RTC_REGS ((rtc_registers_t*)0x40002400) /**< \brief RTC Registers Address */ -#define SDHC0_REGS ((sdhc_registers_t*)0x45000000) /**< \brief SDHC0 Registers Address */ -#define SDHC1_REGS ((sdhc_registers_t*)0x46000000) /**< \brief SDHC1 Registers Address */ -#define SERCOM0_REGS ((sercom_registers_t*)0x40003000) /**< \brief SERCOM0 Registers Address */ -#define SERCOM1_REGS ((sercom_registers_t*)0x40003400) /**< \brief SERCOM1 Registers Address */ -#define SERCOM2_REGS ((sercom_registers_t*)0x41012000) /**< \brief SERCOM2 Registers Address */ -#define SERCOM3_REGS ((sercom_registers_t*)0x41014000) /**< \brief SERCOM3 Registers Address */ -#define SERCOM4_REGS ((sercom_registers_t*)0x43000000) /**< \brief SERCOM4 Registers Address */ -#define SERCOM5_REGS ((sercom_registers_t*)0x43000400) /**< \brief SERCOM5 Registers Address */ -#define SERCOM6_REGS ((sercom_registers_t*)0x43000800) /**< \brief SERCOM6 Registers Address */ -#define SERCOM7_REGS ((sercom_registers_t*)0x43000c00) /**< \brief SERCOM7 Registers Address */ -#define SUPC_REGS ((supc_registers_t*)0x40001800) /**< \brief SUPC Registers Address */ -#define TC0_REGS ((tc_registers_t*)0x40003800) /**< \brief TC0 Registers Address */ -#define TC1_REGS ((tc_registers_t*)0x40003c00) /**< \brief TC1 Registers Address */ -#define TC2_REGS ((tc_registers_t*)0x4101a000) /**< \brief TC2 Registers Address */ -#define TC3_REGS ((tc_registers_t*)0x4101c000) /**< \brief TC3 Registers Address */ -#define TC4_REGS ((tc_registers_t*)0x42001400) /**< \brief TC4 Registers Address */ -#define TC5_REGS ((tc_registers_t*)0x42001800) /**< \brief TC5 Registers Address */ -#define TC6_REGS ((tc_registers_t*)0x43001400) /**< \brief TC6 Registers Address */ -#define TC7_REGS ((tc_registers_t*)0x43001800) /**< \brief TC7 Registers Address */ -#define TCC0_REGS ((tcc_registers_t*)0x41016000) /**< \brief TCC0 Registers Address */ -#define TCC1_REGS ((tcc_registers_t*)0x41018000) /**< \brief TCC1 Registers Address */ -#define TCC2_REGS ((tcc_registers_t*)0x42000c00) /**< \brief TCC2 Registers Address */ -#define TCC3_REGS ((tcc_registers_t*)0x42001000) /**< \brief TCC3 Registers Address */ -#define TCC4_REGS ((tcc_registers_t*)0x43001000) /**< \brief TCC4 Registers Address */ -#define TRNG_REGS ((trng_registers_t*)0x42002800) /**< \brief TRNG Registers Address */ -#define USB_REGS ((usb_registers_t*)0x41000000) /**< \brief USB Registers Address */ -#define WDT_REGS ((wdt_registers_t*)0x40002000) /**< \brief WDT Registers Address */ -#endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ -/** @} end of Peripheral Base Address Definitions */ - -/** \addtogroup SAME54N19A_base Peripheral Base Address Definitions - * @{ - */ - -/* ************************************************************************** */ -/* BASE ADDRESS DEFINITIONS FOR SAME54N19A */ -/* ************************************************************************** */ -#define AC_BASE_ADDRESS _UL_(0x42002000) /**< \brief AC Base Address */ -#define ADC0_BASE_ADDRESS _UL_(0x43001c00) /**< \brief ADC0 Base Address */ -#define ADC1_BASE_ADDRESS _UL_(0x43002000) /**< \brief ADC1 Base Address */ -#define AES_BASE_ADDRESS _UL_(0x42002400) /**< \brief AES Base Address */ -#define CAN0_BASE_ADDRESS _UL_(0x42000000) /**< \brief CAN0 Base Address */ -#define CAN1_BASE_ADDRESS _UL_(0x42000400) /**< \brief CAN1 Base Address */ -#define CCL_BASE_ADDRESS _UL_(0x42003800) /**< \brief CCL Base Address */ -#define CMCC_BASE_ADDRESS _UL_(0x41006000) /**< \brief CMCC Base Address */ -#define DAC_BASE_ADDRESS _UL_(0x43002400) /**< \brief DAC Base Address */ -#define DMAC_BASE_ADDRESS _UL_(0x4100a000) /**< \brief DMAC Base Address */ -#define DSU_BASE_ADDRESS _UL_(0x41002000) /**< \brief DSU Base Address */ -#define EIC_BASE_ADDRESS _UL_(0x40002800) /**< \brief EIC Base Address */ -#define EVSYS_BASE_ADDRESS _UL_(0x4100e000) /**< \brief EVSYS Base Address */ -#define FREQM_BASE_ADDRESS _UL_(0x40002c00) /**< \brief FREQM Base Address */ -#define GCLK_BASE_ADDRESS _UL_(0x40001c00) /**< \brief GCLK Base Address */ -#define GMAC_BASE_ADDRESS _UL_(0x42000800) /**< \brief GMAC Base Address */ -#define HMATRIX_BASE_ADDRESS _UL_(0x4100c000) /**< \brief HMATRIX Base Address */ -#define ICM_BASE_ADDRESS _UL_(0x42002c00) /**< \brief ICM Base Address */ -#define I2S_BASE_ADDRESS _UL_(0x43002800) /**< \brief I2S Base Address */ -#define MCLK_BASE_ADDRESS _UL_(0x40000800) /**< \brief MCLK Base Address */ -#define NVMCTRL_BASE_ADDRESS _UL_(0x41004000) /**< \brief NVMCTRL Base Address */ -#define OSCCTRL_BASE_ADDRESS _UL_(0x40001000) /**< \brief OSCCTRL Base Address */ -#define OSC32KCTRL_BASE_ADDRESS _UL_(0x40001400) /**< \brief OSC32KCTRL Base Address */ -#define PAC_BASE_ADDRESS _UL_(0x40000000) /**< \brief PAC Base Address */ -#define PCC_BASE_ADDRESS _UL_(0x43002c00) /**< \brief PCC Base Address */ -#define PDEC_BASE_ADDRESS _UL_(0x42001c00) /**< \brief PDEC Base Address */ -#define PM_BASE_ADDRESS _UL_(0x40000400) /**< \brief PM Base Address */ -#define PORT_BASE_ADDRESS _UL_(0x41008000) /**< \brief PORT Base Address */ -#define QSPI_BASE_ADDRESS _UL_(0x42003400) /**< \brief QSPI Base Address */ -#define RAMECC_BASE_ADDRESS _UL_(0x41020000) /**< \brief RAMECC Base Address */ -#define RSTC_BASE_ADDRESS _UL_(0x40000c00) /**< \brief RSTC Base Address */ -#define RTC_BASE_ADDRESS _UL_(0x40002400) /**< \brief RTC Base Address */ -#define SDHC0_BASE_ADDRESS _UL_(0x45000000) /**< \brief SDHC0 Base Address */ -#define SDHC1_BASE_ADDRESS _UL_(0x46000000) /**< \brief SDHC1 Base Address */ -#define SERCOM0_BASE_ADDRESS _UL_(0x40003000) /**< \brief SERCOM0 Base Address */ -#define SERCOM1_BASE_ADDRESS _UL_(0x40003400) /**< \brief SERCOM1 Base Address */ -#define SERCOM2_BASE_ADDRESS _UL_(0x41012000) /**< \brief SERCOM2 Base Address */ -#define SERCOM3_BASE_ADDRESS _UL_(0x41014000) /**< \brief SERCOM3 Base Address */ -#define SERCOM4_BASE_ADDRESS _UL_(0x43000000) /**< \brief SERCOM4 Base Address */ -#define SERCOM5_BASE_ADDRESS _UL_(0x43000400) /**< \brief SERCOM5 Base Address */ -#define SERCOM6_BASE_ADDRESS _UL_(0x43000800) /**< \brief SERCOM6 Base Address */ -#define SERCOM7_BASE_ADDRESS _UL_(0x43000c00) /**< \brief SERCOM7 Base Address */ -#define SUPC_BASE_ADDRESS _UL_(0x40001800) /**< \brief SUPC Base Address */ -#define TC0_BASE_ADDRESS _UL_(0x40003800) /**< \brief TC0 Base Address */ -#define TC1_BASE_ADDRESS _UL_(0x40003c00) /**< \brief TC1 Base Address */ -#define TC2_BASE_ADDRESS _UL_(0x4101a000) /**< \brief TC2 Base Address */ -#define TC3_BASE_ADDRESS _UL_(0x4101c000) /**< \brief TC3 Base Address */ -#define TC4_BASE_ADDRESS _UL_(0x42001400) /**< \brief TC4 Base Address */ -#define TC5_BASE_ADDRESS _UL_(0x42001800) /**< \brief TC5 Base Address */ -#define TC6_BASE_ADDRESS _UL_(0x43001400) /**< \brief TC6 Base Address */ -#define TC7_BASE_ADDRESS _UL_(0x43001800) /**< \brief TC7 Base Address */ -#define TCC0_BASE_ADDRESS _UL_(0x41016000) /**< \brief TCC0 Base Address */ -#define TCC1_BASE_ADDRESS _UL_(0x41018000) /**< \brief TCC1 Base Address */ -#define TCC2_BASE_ADDRESS _UL_(0x42000c00) /**< \brief TCC2 Base Address */ -#define TCC3_BASE_ADDRESS _UL_(0x42001000) /**< \brief TCC3 Base Address */ -#define TCC4_BASE_ADDRESS _UL_(0x43001000) /**< \brief TCC4 Base Address */ -#define TRNG_BASE_ADDRESS _UL_(0x42002800) /**< \brief TRNG Base Address */ -#define USB_BASE_ADDRESS _UL_(0x41000000) /**< \brief USB Base Address */ -#define WDT_BASE_ADDRESS _UL_(0x40002000) /**< \brief WDT Base Address */ -/** @} end of Peripheral Base Address Definitions */ - -/** \addtogroup SAME54N19A_pio Peripheral Pio Definitions - * @{ - */ - -/* ************************************************************************** */ -/* PIO DEFINITIONS FOR SAME54N19A */ -/* ************************************************************************** */ -#include "pio/same54n19a.h" -/** @} end of Peripheral Pio Definitions */ - -/* ************************************************************************** */ -/* MEMORY MAPPING DEFINITIONS FOR SAME54N19A */ -/* ************************************************************************** */ - -#define FLASH_SIZE _UL_(0x00080000) /* 512kB Memory segment type: flash */ -#define FLASH_PAGE_SIZE _UL_( 512) -#define FLASH_NB_OF_PAGES _UL_( 1024) - -#define SW0_SIZE _UL_(0x00000010) /* 0kB Memory segment type: fuses */ -#define TEMP_LOG_SIZE _UL_(0x00000200) /* 0kB Memory segment type: fuses */ -#define TEMP_LOG_PAGE_SIZE _UL_( 512) -#define TEMP_LOG_NB_OF_PAGES _UL_( 1) - -#define USER_PAGE_SIZE _UL_(0x00000200) /* 0kB Memory segment type: user_page */ -#define USER_PAGE_PAGE_SIZE _UL_( 512) -#define USER_PAGE_NB_OF_PAGES _UL_( 1) - -#define CMCC_SIZE _UL_(0x01000000) /* 16384kB Memory segment type: io */ -#define CMCC_DATARAM_SIZE _UL_(0x00001000) /* 4kB Memory segment type: io */ -#define CMCC_TAGRAM_SIZE _UL_(0x00000400) /* 1kB Memory segment type: io */ -#define CMCC_VALIDRAM_SIZE _UL_(0x00000040) /* 0kB Memory segment type: io */ -#define QSPI_SIZE _UL_(0x01000000) /* 16384kB Memory segment type: other */ -#define HSRAM_SIZE _UL_(0x00030000) /* 192kB Memory segment type: ram */ -#define HSRAM_ETB_SIZE _UL_(0x00008000) /* 32kB Memory segment type: ram */ -#define HSRAM_RET1_SIZE _UL_(0x00008000) /* 32kB Memory segment type: ram */ -#define HPB0_SIZE _UL_(0x00004400) /* 17kB Memory segment type: io */ -#define HPB1_SIZE _UL_(0x00022000) /* 136kB Memory segment type: io */ -#define HPB2_SIZE _UL_(0x00003c00) /* 15kB Memory segment type: io */ -#define HPB3_SIZE _UL_(0x00003000) /* 12kB Memory segment type: io */ -#define SEEPROM_SIZE _UL_(0x00020000) /* 128kB Memory segment type: io */ -#define SDHC0_SIZE _UL_(0x00000c00) /* 3kB Memory segment type: io */ -#define SDHC1_SIZE _UL_(0x00000c00) /* 3kB Memory segment type: io */ -#define BKUPRAM_SIZE _UL_(0x00002000) /* 8kB Memory segment type: ram */ -#define PPB_SIZE _UL_(0x00100000) /* 1024kB Memory segment type: io */ -#define SCS_SIZE _UL_(0x00001000) /* 4kB Memory segment type: io */ - -#define FLASH_ADDR _UL_(0x00000000) /**< FLASH base address (type: flash)*/ -#define SW0_ADDR _UL_(0x00800080) /**< SW0 base address (type: fuses)*/ -#define TEMP_LOG_ADDR _UL_(0x00800100) /**< TEMP_LOG base address (type: fuses)*/ -#define USER_PAGE_ADDR _UL_(0x00804000) /**< USER_PAGE base address (type: user_page)*/ -#define CMCC_ADDR _UL_(0x03000000) /**< CMCC base address (type: io)*/ -#define CMCC_DATARAM_ADDR _UL_(0x03000000) /**< CMCC_DATARAM base address (type: io)*/ -#define CMCC_TAGRAM_ADDR _UL_(0x03001000) /**< CMCC_TAGRAM base address (type: io)*/ -#define CMCC_VALIDRAM_ADDR _UL_(0x03002000) /**< CMCC_VALIDRAM base address (type: io)*/ -#define QSPI_ADDR _UL_(0x04000000) /**< QSPI base address (type: other)*/ -#define HSRAM_ADDR _UL_(0x20000000) /**< HSRAM base address (type: ram)*/ -#define HSRAM_ETB_ADDR _UL_(0x20000000) /**< HSRAM_ETB base address (type: ram)*/ -#define HSRAM_RET1_ADDR _UL_(0x20000000) /**< HSRAM_RET1 base address (type: ram)*/ -#define HPB0_ADDR _UL_(0x40000000) /**< HPB0 base address (type: io)*/ -#define HPB1_ADDR _UL_(0x41000000) /**< HPB1 base address (type: io)*/ -#define HPB2_ADDR _UL_(0x42000000) /**< HPB2 base address (type: io)*/ -#define HPB3_ADDR _UL_(0x43000000) /**< HPB3 base address (type: io)*/ -#define SEEPROM_ADDR _UL_(0x44000000) /**< SEEPROM base address (type: io)*/ -#define SDHC0_ADDR _UL_(0x45000000) /**< SDHC0 base address (type: io)*/ -#define SDHC1_ADDR _UL_(0x46000000) /**< SDHC1 base address (type: io)*/ -#define BKUPRAM_ADDR _UL_(0x47000000) /**< BKUPRAM base address (type: ram)*/ -#define PPB_ADDR _UL_(0xe0000000) /**< PPB base address (type: io)*/ -#define SCS_ADDR _UL_(0xe000e000) /**< SCS base address (type: io)*/ - -/* ************************************************************************** */ -/** DEVICE SIGNATURES FOR SAME54N19A */ -/* ************************************************************************** */ -#define CHIP_DSU_DID _UL_(0X61840303) - -/* ************************************************************************** */ -/** ELECTRICAL DEFINITIONS FOR SAME54N19A */ -/* ************************************************************************** */ - -/* ************************************************************************** */ -/** Event Generator IDs for SAME54N19A */ -/* ************************************************************************** */ -#define EVENT_ID_GEN_OSCCTRL_XOSC_FAIL_0 1 /**< ID for OSCCTRL event generator XOSC_FAIL_0 */ -#define EVENT_ID_GEN_OSCCTRL_XOSC_FAIL_1 2 /**< ID for OSCCTRL event generator XOSC_FAIL_1 */ -#define EVENT_ID_GEN_OSC32KCTRL_XOSC32K_FAIL 3 /**< ID for OSC32KCTRL event generator XOSC32K_FAIL */ -#define EVENT_ID_GEN_RTC_PER_0 4 /**< ID for RTC event generator PER_0 */ -#define EVENT_ID_GEN_RTC_PER_1 5 /**< ID for RTC event generator PER_1 */ -#define EVENT_ID_GEN_RTC_PER_2 6 /**< ID for RTC event generator PER_2 */ -#define EVENT_ID_GEN_RTC_PER_3 7 /**< ID for RTC event generator PER_3 */ -#define EVENT_ID_GEN_RTC_PER_4 8 /**< ID for RTC event generator PER_4 */ -#define EVENT_ID_GEN_RTC_PER_5 9 /**< ID for RTC event generator PER_5 */ -#define EVENT_ID_GEN_RTC_PER_6 10 /**< ID for RTC event generator PER_6 */ -#define EVENT_ID_GEN_RTC_PER_7 11 /**< ID for RTC event generator PER_7 */ -#define EVENT_ID_GEN_RTC_CMP_0 12 /**< ID for RTC event generator CMP_0 */ -#define EVENT_ID_GEN_RTC_CMP_1 13 /**< ID for RTC event generator CMP_1 */ -#define EVENT_ID_GEN_RTC_CMP_2 14 /**< ID for RTC event generator CMP_2 */ -#define EVENT_ID_GEN_RTC_CMP_3 15 /**< ID for RTC event generator CMP_3 */ -#define EVENT_ID_GEN_RTC_TAMPER 16 /**< ID for RTC event generator TAMPER */ -#define EVENT_ID_GEN_RTC_OVF 17 /**< ID for RTC event generator OVF */ -#define EVENT_ID_GEN_EIC_EXTINT_0 18 /**< ID for EIC event generator EXTINT_0 */ -#define EVENT_ID_GEN_EIC_EXTINT_1 19 /**< ID for EIC event generator EXTINT_1 */ -#define EVENT_ID_GEN_EIC_EXTINT_2 20 /**< ID for EIC event generator EXTINT_2 */ -#define EVENT_ID_GEN_EIC_EXTINT_3 21 /**< ID for EIC event generator EXTINT_3 */ -#define EVENT_ID_GEN_EIC_EXTINT_4 22 /**< ID for EIC event generator EXTINT_4 */ -#define EVENT_ID_GEN_EIC_EXTINT_5 23 /**< ID for EIC event generator EXTINT_5 */ -#define EVENT_ID_GEN_EIC_EXTINT_6 24 /**< ID for EIC event generator EXTINT_6 */ -#define EVENT_ID_GEN_EIC_EXTINT_7 25 /**< ID for EIC event generator EXTINT_7 */ -#define EVENT_ID_GEN_EIC_EXTINT_8 26 /**< ID for EIC event generator EXTINT_8 */ -#define EVENT_ID_GEN_EIC_EXTINT_9 27 /**< ID for EIC event generator EXTINT_9 */ -#define EVENT_ID_GEN_EIC_EXTINT_10 28 /**< ID for EIC event generator EXTINT_10 */ -#define EVENT_ID_GEN_EIC_EXTINT_11 29 /**< ID for EIC event generator EXTINT_11 */ -#define EVENT_ID_GEN_EIC_EXTINT_12 30 /**< ID for EIC event generator EXTINT_12 */ -#define EVENT_ID_GEN_EIC_EXTINT_13 31 /**< ID for EIC event generator EXTINT_13 */ -#define EVENT_ID_GEN_EIC_EXTINT_14 32 /**< ID for EIC event generator EXTINT_14 */ -#define EVENT_ID_GEN_EIC_EXTINT_15 33 /**< ID for EIC event generator EXTINT_15 */ -#define EVENT_ID_GEN_DMAC_CH_0 34 /**< ID for DMAC event generator CH_0 */ -#define EVENT_ID_GEN_DMAC_CH_1 35 /**< ID for DMAC event generator CH_1 */ -#define EVENT_ID_GEN_DMAC_CH_2 36 /**< ID for DMAC event generator CH_2 */ -#define EVENT_ID_GEN_DMAC_CH_3 37 /**< ID for DMAC event generator CH_3 */ -#define EVENT_ID_GEN_PAC_ACCERR 38 /**< ID for PAC event generator ACCERR */ -#define EVENT_ID_GEN_TCC0_OVF 41 /**< ID for TCC0 event generator OVF */ -#define EVENT_ID_GEN_TCC0_TRG 42 /**< ID for TCC0 event generator TRG */ -#define EVENT_ID_GEN_TCC0_CNT 43 /**< ID for TCC0 event generator CNT */ -#define EVENT_ID_GEN_TCC0_MC_0 44 /**< ID for TCC0 event generator MC_0 */ -#define EVENT_ID_GEN_TCC0_MC_1 45 /**< ID for TCC0 event generator MC_1 */ -#define EVENT_ID_GEN_TCC0_MC_2 46 /**< ID for TCC0 event generator MC_2 */ -#define EVENT_ID_GEN_TCC0_MC_3 47 /**< ID for TCC0 event generator MC_3 */ -#define EVENT_ID_GEN_TCC0_MC_4 48 /**< ID for TCC0 event generator MC_4 */ -#define EVENT_ID_GEN_TCC0_MC_5 49 /**< ID for TCC0 event generator MC_5 */ -#define EVENT_ID_GEN_TCC1_OVF 50 /**< ID for TCC1 event generator OVF */ -#define EVENT_ID_GEN_TCC1_TRG 51 /**< ID for TCC1 event generator TRG */ -#define EVENT_ID_GEN_TCC1_CNT 52 /**< ID for TCC1 event generator CNT */ -#define EVENT_ID_GEN_TCC1_MC_0 53 /**< ID for TCC1 event generator MC_0 */ -#define EVENT_ID_GEN_TCC1_MC_1 54 /**< ID for TCC1 event generator MC_1 */ -#define EVENT_ID_GEN_TCC1_MC_2 55 /**< ID for TCC1 event generator MC_2 */ -#define EVENT_ID_GEN_TCC1_MC_3 56 /**< ID for TCC1 event generator MC_3 */ -#define EVENT_ID_GEN_TCC2_OVF 57 /**< ID for TCC2 event generator OVF */ -#define EVENT_ID_GEN_TCC2_TRG 58 /**< ID for TCC2 event generator TRG */ -#define EVENT_ID_GEN_TCC2_CNT 59 /**< ID for TCC2 event generator CNT */ -#define EVENT_ID_GEN_TCC2_MC_0 60 /**< ID for TCC2 event generator MC_0 */ -#define EVENT_ID_GEN_TCC2_MC_1 61 /**< ID for TCC2 event generator MC_1 */ -#define EVENT_ID_GEN_TCC2_MC_2 62 /**< ID for TCC2 event generator MC_2 */ -#define EVENT_ID_GEN_TCC3_OVF 63 /**< ID for TCC3 event generator OVF */ -#define EVENT_ID_GEN_TCC3_TRG 64 /**< ID for TCC3 event generator TRG */ -#define EVENT_ID_GEN_TCC3_CNT 65 /**< ID for TCC3 event generator CNT */ -#define EVENT_ID_GEN_TCC3_MC_0 66 /**< ID for TCC3 event generator MC_0 */ -#define EVENT_ID_GEN_TCC3_MC_1 67 /**< ID for TCC3 event generator MC_1 */ -#define EVENT_ID_GEN_TCC4_OVF 68 /**< ID for TCC4 event generator OVF */ -#define EVENT_ID_GEN_TCC4_TRG 69 /**< ID for TCC4 event generator TRG */ -#define EVENT_ID_GEN_TCC4_CNT 70 /**< ID for TCC4 event generator CNT */ -#define EVENT_ID_GEN_TCC4_MC_0 71 /**< ID for TCC4 event generator MC_0 */ -#define EVENT_ID_GEN_TCC4_MC_1 72 /**< ID for TCC4 event generator MC_1 */ -#define EVENT_ID_GEN_TC0_OVF 73 /**< ID for TC0 event generator OVF */ -#define EVENT_ID_GEN_TC0_MC_0 74 /**< ID for TC0 event generator MC_0 */ -#define EVENT_ID_GEN_TC0_MC_1 75 /**< ID for TC0 event generator MC_1 */ -#define EVENT_ID_GEN_TC1_OVF 76 /**< ID for TC1 event generator OVF */ -#define EVENT_ID_GEN_TC1_MC_0 77 /**< ID for TC1 event generator MC_0 */ -#define EVENT_ID_GEN_TC1_MC_1 78 /**< ID for TC1 event generator MC_1 */ -#define EVENT_ID_GEN_TC2_OVF 79 /**< ID for TC2 event generator OVF */ -#define EVENT_ID_GEN_TC2_MC_0 80 /**< ID for TC2 event generator MC_0 */ -#define EVENT_ID_GEN_TC2_MC_1 81 /**< ID for TC2 event generator MC_1 */ -#define EVENT_ID_GEN_TC3_OVF 82 /**< ID for TC3 event generator OVF */ -#define EVENT_ID_GEN_TC3_MC_0 83 /**< ID for TC3 event generator MC_0 */ -#define EVENT_ID_GEN_TC3_MC_1 84 /**< ID for TC3 event generator MC_1 */ -#define EVENT_ID_GEN_TC4_OVF 85 /**< ID for TC4 event generator OVF */ -#define EVENT_ID_GEN_TC4_MC_0 86 /**< ID for TC4 event generator MC_0 */ -#define EVENT_ID_GEN_TC4_MC_1 87 /**< ID for TC4 event generator MC_1 */ -#define EVENT_ID_GEN_TC5_OVF 88 /**< ID for TC5 event generator OVF */ -#define EVENT_ID_GEN_TC5_MC_0 89 /**< ID for TC5 event generator MC_0 */ -#define EVENT_ID_GEN_TC5_MC_1 90 /**< ID for TC5 event generator MC_1 */ -#define EVENT_ID_GEN_TC6_OVF 91 /**< ID for TC6 event generator OVF */ -#define EVENT_ID_GEN_TC6_MC_0 92 /**< ID for TC6 event generator MC_0 */ -#define EVENT_ID_GEN_TC6_MC_1 93 /**< ID for TC6 event generator MC_1 */ -#define EVENT_ID_GEN_TC7_OVF 94 /**< ID for TC7 event generator OVF */ -#define EVENT_ID_GEN_TC7_MC_0 95 /**< ID for TC7 event generator MC_0 */ -#define EVENT_ID_GEN_TC7_MC_1 96 /**< ID for TC7 event generator MC_1 */ -#define EVENT_ID_GEN_PDEC_OVF 97 /**< ID for PDEC event generator OVF */ -#define EVENT_ID_GEN_PDEC_ERR 98 /**< ID for PDEC event generator ERR */ -#define EVENT_ID_GEN_PDEC_DIR 99 /**< ID for PDEC event generator DIR */ -#define EVENT_ID_GEN_PDEC_VLC 100 /**< ID for PDEC event generator VLC */ -#define EVENT_ID_GEN_PDEC_MC_0 101 /**< ID for PDEC event generator MC_0 */ -#define EVENT_ID_GEN_PDEC_MC_1 102 /**< ID for PDEC event generator MC_1 */ -#define EVENT_ID_GEN_ADC0_RESRDY 103 /**< ID for ADC0 event generator RESRDY */ -#define EVENT_ID_GEN_ADC0_WINMON 104 /**< ID for ADC0 event generator WINMON */ -#define EVENT_ID_GEN_ADC1_RESRDY 105 /**< ID for ADC1 event generator RESRDY */ -#define EVENT_ID_GEN_ADC1_WINMON 106 /**< ID for ADC1 event generator WINMON */ -#define EVENT_ID_GEN_AC_COMP_0 107 /**< ID for AC event generator COMP_0 */ -#define EVENT_ID_GEN_AC_COMP_1 108 /**< ID for AC event generator COMP_1 */ -#define EVENT_ID_GEN_AC_WIN_0 109 /**< ID for AC event generator WIN_0 */ -#define EVENT_ID_GEN_DAC_EMPTY_0 110 /**< ID for DAC event generator EMPTY_0 */ -#define EVENT_ID_GEN_DAC_EMPTY_1 111 /**< ID for DAC event generator EMPTY_1 */ -#define EVENT_ID_GEN_DAC_RESRDY_0 112 /**< ID for DAC event generator RESRDY_0 */ -#define EVENT_ID_GEN_DAC_RESRDY_1 113 /**< ID for DAC event generator RESRDY_1 */ -#define EVENT_ID_GEN_GMAC_TSU_CMP 114 /**< ID for GMAC event generator TSU_CMP */ -#define EVENT_ID_GEN_TRNG_READY 115 /**< ID for TRNG event generator READY */ -#define EVENT_ID_GEN_CCL_LUTOUT_0 116 /**< ID for CCL event generator LUTOUT_0 */ -#define EVENT_ID_GEN_CCL_LUTOUT_1 117 /**< ID for CCL event generator LUTOUT_1 */ -#define EVENT_ID_GEN_CCL_LUTOUT_2 118 /**< ID for CCL event generator LUTOUT_2 */ -#define EVENT_ID_GEN_CCL_LUTOUT_3 119 /**< ID for CCL event generator LUTOUT_3 */ - -/* ************************************************************************** */ -/** Event User IDs for SAME54N19A */ -/* ************************************************************************** */ -#define EVENT_ID_USER_RTC_TAMPER 0 /**< ID for RTC event user TAMPER */ -#define EVENT_ID_USER_PORT_EV_0 1 /**< ID for PORT event user EV_0 */ -#define EVENT_ID_USER_PORT_EV_1 2 /**< ID for PORT event user EV_1 */ -#define EVENT_ID_USER_PORT_EV_2 3 /**< ID for PORT event user EV_2 */ -#define EVENT_ID_USER_PORT_EV_3 4 /**< ID for PORT event user EV_3 */ -#define EVENT_ID_USER_DMAC_CH_0 5 /**< ID for DMAC event user CH_0 */ -#define EVENT_ID_USER_DMAC_CH_1 6 /**< ID for DMAC event user CH_1 */ -#define EVENT_ID_USER_DMAC_CH_2 7 /**< ID for DMAC event user CH_2 */ -#define EVENT_ID_USER_DMAC_CH_3 8 /**< ID for DMAC event user CH_3 */ -#define EVENT_ID_USER_DMAC_CH_4 9 /**< ID for DMAC event user CH_4 */ -#define EVENT_ID_USER_DMAC_CH_5 10 /**< ID for DMAC event user CH_5 */ -#define EVENT_ID_USER_DMAC_CH_6 11 /**< ID for DMAC event user CH_6 */ -#define EVENT_ID_USER_DMAC_CH_7 12 /**< ID for DMAC event user CH_7 */ -#define EVENT_ID_USER_CM4_TRACE_START 14 /**< ID for CM4 event user TRACE_START */ -#define EVENT_ID_USER_CM4_TRACE_STOP 15 /**< ID for CM4 event user TRACE_STOP */ -#define EVENT_ID_USER_CM4_TRACE_TRIG 16 /**< ID for CM4 event user TRACE_TRIG */ -#define EVENT_ID_USER_TCC0_EV_0 17 /**< ID for TCC0 event user EV_0 */ -#define EVENT_ID_USER_TCC0_EV_1 18 /**< ID for TCC0 event user EV_1 */ -#define EVENT_ID_USER_TCC0_MC_0 19 /**< ID for TCC0 event user MC_0 */ -#define EVENT_ID_USER_TCC0_MC_1 20 /**< ID for TCC0 event user MC_1 */ -#define EVENT_ID_USER_TCC0_MC_2 21 /**< ID for TCC0 event user MC_2 */ -#define EVENT_ID_USER_TCC0_MC_3 22 /**< ID for TCC0 event user MC_3 */ -#define EVENT_ID_USER_TCC0_MC_4 23 /**< ID for TCC0 event user MC_4 */ -#define EVENT_ID_USER_TCC0_MC_5 24 /**< ID for TCC0 event user MC_5 */ -#define EVENT_ID_USER_TCC1_EV_0 25 /**< ID for TCC1 event user EV_0 */ -#define EVENT_ID_USER_TCC1_EV_1 26 /**< ID for TCC1 event user EV_1 */ -#define EVENT_ID_USER_TCC1_MC_0 27 /**< ID for TCC1 event user MC_0 */ -#define EVENT_ID_USER_TCC1_MC_1 28 /**< ID for TCC1 event user MC_1 */ -#define EVENT_ID_USER_TCC1_MC_2 29 /**< ID for TCC1 event user MC_2 */ -#define EVENT_ID_USER_TCC1_MC_3 30 /**< ID for TCC1 event user MC_3 */ -#define EVENT_ID_USER_TCC2_EV_0 31 /**< ID for TCC2 event user EV_0 */ -#define EVENT_ID_USER_TCC2_EV_1 32 /**< ID for TCC2 event user EV_1 */ -#define EVENT_ID_USER_TCC2_MC_0 33 /**< ID for TCC2 event user MC_0 */ -#define EVENT_ID_USER_TCC2_MC_1 34 /**< ID for TCC2 event user MC_1 */ -#define EVENT_ID_USER_TCC2_MC_2 35 /**< ID for TCC2 event user MC_2 */ -#define EVENT_ID_USER_TCC3_EV_0 36 /**< ID for TCC3 event user EV_0 */ -#define EVENT_ID_USER_TCC3_EV_1 37 /**< ID for TCC3 event user EV_1 */ -#define EVENT_ID_USER_TCC3_MC_0 38 /**< ID for TCC3 event user MC_0 */ -#define EVENT_ID_USER_TCC3_MC_1 39 /**< ID for TCC3 event user MC_1 */ -#define EVENT_ID_USER_TCC4_EV_0 40 /**< ID for TCC4 event user EV_0 */ -#define EVENT_ID_USER_TCC4_EV_1 41 /**< ID for TCC4 event user EV_1 */ -#define EVENT_ID_USER_TCC4_MC_0 42 /**< ID for TCC4 event user MC_0 */ -#define EVENT_ID_USER_TCC4_MC_1 43 /**< ID for TCC4 event user MC_1 */ -#define EVENT_ID_USER_TC0_EVU 44 /**< ID for TC0 event user EVU */ -#define EVENT_ID_USER_TC1_EVU 45 /**< ID for TC1 event user EVU */ -#define EVENT_ID_USER_TC2_EVU 46 /**< ID for TC2 event user EVU */ -#define EVENT_ID_USER_TC3_EVU 47 /**< ID for TC3 event user EVU */ -#define EVENT_ID_USER_TC4_EVU 48 /**< ID for TC4 event user EVU */ -#define EVENT_ID_USER_TC5_EVU 49 /**< ID for TC5 event user EVU */ -#define EVENT_ID_USER_TC6_EVU 50 /**< ID for TC6 event user EVU */ -#define EVENT_ID_USER_TC7_EVU 51 /**< ID for TC7 event user EVU */ -#define EVENT_ID_USER_PDEC_EVU_0 52 /**< ID for PDEC event user EVU_0 */ -#define EVENT_ID_USER_PDEC_EVU_1 53 /**< ID for PDEC event user EVU_1 */ -#define EVENT_ID_USER_PDEC_EVU_2 54 /**< ID for PDEC event user EVU_2 */ -#define EVENT_ID_USER_ADC0_START 55 /**< ID for ADC0 event user START */ -#define EVENT_ID_USER_ADC0_SYNC 56 /**< ID for ADC0 event user SYNC */ -#define EVENT_ID_USER_ADC1_START 57 /**< ID for ADC1 event user START */ -#define EVENT_ID_USER_ADC1_SYNC 58 /**< ID for ADC1 event user SYNC */ -#define EVENT_ID_USER_AC_SOC_0 59 /**< ID for AC event user SOC_0 */ -#define EVENT_ID_USER_AC_SOC_1 60 /**< ID for AC event user SOC_1 */ -#define EVENT_ID_USER_DAC_START_0 61 /**< ID for DAC event user START_0 */ -#define EVENT_ID_USER_DAC_START_1 62 /**< ID for DAC event user START_1 */ -#define EVENT_ID_USER_CCL_LUTIN_0 63 /**< ID for CCL event user LUTIN_0 */ -#define EVENT_ID_USER_CCL_LUTIN_1 64 /**< ID for CCL event user LUTIN_1 */ -#define EVENT_ID_USER_CCL_LUTIN_2 65 /**< ID for CCL event user LUTIN_2 */ -#define EVENT_ID_USER_CCL_LUTIN_3 66 /**< ID for CCL event user LUTIN_3 */ - -#ifdef __cplusplus -} -#endif - -/** @} end of SAME54N19A definitions */ - - -#endif /* _SAME54N19A_H_ */ - +/** + * \file + * + * \brief Header file for SAME54N19A + * + * Copyright (c) 2019 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAME54N19A_ +#define _SAME54N19A_ + +/** + * \ingroup SAME54_definitions + * \addtogroup SAME54N19A_definitions SAME54N19A definitions + * This file defines all structures and symbols for SAME54N19A: + * - registers and bitfields + * - peripheral base address + * - peripheral ID + * - PIO definitions +*/ +/*@{*/ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#include +#ifndef __cplusplus +typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#else +typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#endif +typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ +typedef volatile uint8_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ +typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ +typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ +#endif + +#if !defined(SKIP_INTEGER_LITERALS) +#if defined(_U_) || defined(_L_) || defined(_UL_) + #error "Integer Literals macros already defined elsewhere" +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/* Macros that deal with adding suffixes to integer literal constants for C/C++ */ +#define _U_(x) x ## U /**< C code: Unsigned integer literal constant value */ +#define _L_(x) x ## L /**< C code: Long integer literal constant value */ +#define _UL_(x) x ## UL /**< C code: Unsigned Long integer literal constant value */ +#else /* Assembler */ +#define _U_(x) x /**< Assembler: Unsigned integer literal constant value */ +#define _L_(x) x /**< Assembler: Long integer literal constant value */ +#define _UL_(x) x /**< Assembler: Unsigned Long integer literal constant value */ +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +#endif /* SKIP_INTEGER_LITERALS */ + +/* ************************************************************************** */ +/** CMSIS DEFINITIONS FOR SAME54N19A */ +/* ************************************************************************** */ +/** \defgroup SAME54N19A_cmsis CMSIS Definitions */ +/*@{*/ + +/** Interrupt Number Definition */ +typedef enum IRQn +{ + /****** Cortex-M4 Processor Exceptions Numbers *******************/ + NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13,/**< 3 Hard Fault Interrupt */ + MemoryManagement_IRQn = -12,/**< 4 Memory Management Interrupt */ + BusFault_IRQn = -11,/**< 5 Bus Fault Interrupt */ + UsageFault_IRQn = -10,/**< 6 Usage Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /**< 12 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /**< 14 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 System Tick Interrupt */ + /****** SAME54N19A-specific Interrupt Numbers *********************/ + PM_IRQn = 0, /**< 0 SAME54N19A Power Manager (PM) */ + MCLK_IRQn = 1, /**< 1 SAME54N19A Main Clock (MCLK) */ + OSCCTRL_0_IRQn = 2, /**< 2 SAME54N19A Oscillators Control (OSCCTRL) IRQ 0 */ + OSCCTRL_1_IRQn = 3, /**< 3 SAME54N19A Oscillators Control (OSCCTRL) IRQ 1 */ + OSCCTRL_2_IRQn = 4, /**< 4 SAME54N19A Oscillators Control (OSCCTRL) IRQ 2 */ + OSCCTRL_3_IRQn = 5, /**< 5 SAME54N19A Oscillators Control (OSCCTRL) IRQ 3 */ + OSCCTRL_4_IRQn = 6, /**< 6 SAME54N19A Oscillators Control (OSCCTRL) IRQ 4 */ + OSC32KCTRL_IRQn = 7, /**< 7 SAME54N19A 32kHz Oscillators Control (OSC32KCTRL) */ + SUPC_0_IRQn = 8, /**< 8 SAME54N19A Supply Controller (SUPC) IRQ 0 */ + SUPC_1_IRQn = 9, /**< 9 SAME54N19A Supply Controller (SUPC) IRQ 1 */ + WDT_IRQn = 10, /**< 10 SAME54N19A Watchdog Timer (WDT) */ + RTC_IRQn = 11, /**< 11 SAME54N19A Real-Time Counter (RTC) */ + EIC_0_IRQn = 12, /**< 12 SAME54N19A External Interrupt Controller (EIC) IRQ 0 */ + EIC_1_IRQn = 13, /**< 13 SAME54N19A External Interrupt Controller (EIC) IRQ 1 */ + EIC_2_IRQn = 14, /**< 14 SAME54N19A External Interrupt Controller (EIC) IRQ 2 */ + EIC_3_IRQn = 15, /**< 15 SAME54N19A External Interrupt Controller (EIC) IRQ 3 */ + EIC_4_IRQn = 16, /**< 16 SAME54N19A External Interrupt Controller (EIC) IRQ 4 */ + EIC_5_IRQn = 17, /**< 17 SAME54N19A External Interrupt Controller (EIC) IRQ 5 */ + EIC_6_IRQn = 18, /**< 18 SAME54N19A External Interrupt Controller (EIC) IRQ 6 */ + EIC_7_IRQn = 19, /**< 19 SAME54N19A External Interrupt Controller (EIC) IRQ 7 */ + EIC_8_IRQn = 20, /**< 20 SAME54N19A External Interrupt Controller (EIC) IRQ 8 */ + EIC_9_IRQn = 21, /**< 21 SAME54N19A External Interrupt Controller (EIC) IRQ 9 */ + EIC_10_IRQn = 22, /**< 22 SAME54N19A External Interrupt Controller (EIC) IRQ 10 */ + EIC_11_IRQn = 23, /**< 23 SAME54N19A External Interrupt Controller (EIC) IRQ 11 */ + EIC_12_IRQn = 24, /**< 24 SAME54N19A External Interrupt Controller (EIC) IRQ 12 */ + EIC_13_IRQn = 25, /**< 25 SAME54N19A External Interrupt Controller (EIC) IRQ 13 */ + EIC_14_IRQn = 26, /**< 26 SAME54N19A External Interrupt Controller (EIC) IRQ 14 */ + EIC_15_IRQn = 27, /**< 27 SAME54N19A External Interrupt Controller (EIC) IRQ 15 */ + FREQM_IRQn = 28, /**< 28 SAME54N19A Frequency Meter (FREQM) */ + NVMCTRL_0_IRQn = 29, /**< 29 SAME54N19A Non-Volatile Memory Controller (NVMCTRL) IRQ 0 */ + NVMCTRL_1_IRQn = 30, /**< 30 SAME54N19A Non-Volatile Memory Controller (NVMCTRL) IRQ 1 */ + DMAC_0_IRQn = 31, /**< 31 SAME54N19A Direct Memory Access Controller (DMAC) IRQ 0 */ + DMAC_1_IRQn = 32, /**< 32 SAME54N19A Direct Memory Access Controller (DMAC) IRQ 1 */ + DMAC_2_IRQn = 33, /**< 33 SAME54N19A Direct Memory Access Controller (DMAC) IRQ 2 */ + DMAC_3_IRQn = 34, /**< 34 SAME54N19A Direct Memory Access Controller (DMAC) IRQ 3 */ + DMAC_4_IRQn = 35, /**< 35 SAME54N19A Direct Memory Access Controller (DMAC) IRQ 4 */ + EVSYS_0_IRQn = 36, /**< 36 SAME54N19A Event System Interface (EVSYS) IRQ 0 */ + EVSYS_1_IRQn = 37, /**< 37 SAME54N19A Event System Interface (EVSYS) IRQ 1 */ + EVSYS_2_IRQn = 38, /**< 38 SAME54N19A Event System Interface (EVSYS) IRQ 2 */ + EVSYS_3_IRQn = 39, /**< 39 SAME54N19A Event System Interface (EVSYS) IRQ 3 */ + EVSYS_4_IRQn = 40, /**< 40 SAME54N19A Event System Interface (EVSYS) IRQ 4 */ + PAC_IRQn = 41, /**< 41 SAME54N19A Peripheral Access Controller (PAC) */ + RAMECC_IRQn = 45, /**< 45 SAME54N19A RAM ECC (RAMECC) */ + SERCOM0_0_IRQn = 46, /**< 46 SAME54N19A Serial Communication Interface 0 (SERCOM0) IRQ 0 */ + SERCOM0_1_IRQn = 47, /**< 47 SAME54N19A Serial Communication Interface 0 (SERCOM0) IRQ 1 */ + SERCOM0_2_IRQn = 48, /**< 48 SAME54N19A Serial Communication Interface 0 (SERCOM0) IRQ 2 */ + SERCOM0_3_IRQn = 49, /**< 49 SAME54N19A Serial Communication Interface 0 (SERCOM0) IRQ 3 */ + SERCOM1_0_IRQn = 50, /**< 50 SAME54N19A Serial Communication Interface 1 (SERCOM1) IRQ 0 */ + SERCOM1_1_IRQn = 51, /**< 51 SAME54N19A Serial Communication Interface 1 (SERCOM1) IRQ 1 */ + SERCOM1_2_IRQn = 52, /**< 52 SAME54N19A Serial Communication Interface 1 (SERCOM1) IRQ 2 */ + SERCOM1_3_IRQn = 53, /**< 53 SAME54N19A Serial Communication Interface 1 (SERCOM1) IRQ 3 */ + SERCOM2_0_IRQn = 54, /**< 54 SAME54N19A Serial Communication Interface 2 (SERCOM2) IRQ 0 */ + SERCOM2_1_IRQn = 55, /**< 55 SAME54N19A Serial Communication Interface 2 (SERCOM2) IRQ 1 */ + SERCOM2_2_IRQn = 56, /**< 56 SAME54N19A Serial Communication Interface 2 (SERCOM2) IRQ 2 */ + SERCOM2_3_IRQn = 57, /**< 57 SAME54N19A Serial Communication Interface 2 (SERCOM2) IRQ 3 */ + SERCOM3_0_IRQn = 58, /**< 58 SAME54N19A Serial Communication Interface 3 (SERCOM3) IRQ 0 */ + SERCOM3_1_IRQn = 59, /**< 59 SAME54N19A Serial Communication Interface 3 (SERCOM3) IRQ 1 */ + SERCOM3_2_IRQn = 60, /**< 60 SAME54N19A Serial Communication Interface 3 (SERCOM3) IRQ 2 */ + SERCOM3_3_IRQn = 61, /**< 61 SAME54N19A Serial Communication Interface 3 (SERCOM3) IRQ 3 */ + SERCOM4_0_IRQn = 62, /**< 62 SAME54N19A Serial Communication Interface 4 (SERCOM4) IRQ 0 */ + SERCOM4_1_IRQn = 63, /**< 63 SAME54N19A Serial Communication Interface 4 (SERCOM4) IRQ 1 */ + SERCOM4_2_IRQn = 64, /**< 64 SAME54N19A Serial Communication Interface 4 (SERCOM4) IRQ 2 */ + SERCOM4_3_IRQn = 65, /**< 65 SAME54N19A Serial Communication Interface 4 (SERCOM4) IRQ 3 */ + SERCOM5_0_IRQn = 66, /**< 66 SAME54N19A Serial Communication Interface 5 (SERCOM5) IRQ 0 */ + SERCOM5_1_IRQn = 67, /**< 67 SAME54N19A Serial Communication Interface 5 (SERCOM5) IRQ 1 */ + SERCOM5_2_IRQn = 68, /**< 68 SAME54N19A Serial Communication Interface 5 (SERCOM5) IRQ 2 */ + SERCOM5_3_IRQn = 69, /**< 69 SAME54N19A Serial Communication Interface 5 (SERCOM5) IRQ 3 */ + SERCOM6_0_IRQn = 70, /**< 70 SAME54N19A Serial Communication Interface 6 (SERCOM6) IRQ 0 */ + SERCOM6_1_IRQn = 71, /**< 71 SAME54N19A Serial Communication Interface 6 (SERCOM6) IRQ 1 */ + SERCOM6_2_IRQn = 72, /**< 72 SAME54N19A Serial Communication Interface 6 (SERCOM6) IRQ 2 */ + SERCOM6_3_IRQn = 73, /**< 73 SAME54N19A Serial Communication Interface 6 (SERCOM6) IRQ 3 */ + SERCOM7_0_IRQn = 74, /**< 74 SAME54N19A Serial Communication Interface 7 (SERCOM7) IRQ 0 */ + SERCOM7_1_IRQn = 75, /**< 75 SAME54N19A Serial Communication Interface 7 (SERCOM7) IRQ 1 */ + SERCOM7_2_IRQn = 76, /**< 76 SAME54N19A Serial Communication Interface 7 (SERCOM7) IRQ 2 */ + SERCOM7_3_IRQn = 77, /**< 77 SAME54N19A Serial Communication Interface 7 (SERCOM7) IRQ 3 */ + CAN0_IRQn = 78, /**< 78 SAME54N19A Control Area Network 0 (CAN0) */ + CAN1_IRQn = 79, /**< 79 SAME54N19A Control Area Network 1 (CAN1) */ + USB_0_IRQn = 80, /**< 80 SAME54N19A Universal Serial Bus (USB) IRQ 0 */ + USB_1_IRQn = 81, /**< 81 SAME54N19A Universal Serial Bus (USB) IRQ 1 */ + USB_2_IRQn = 82, /**< 82 SAME54N19A Universal Serial Bus (USB) IRQ 2 */ + USB_3_IRQn = 83, /**< 83 SAME54N19A Universal Serial Bus (USB) IRQ 3 */ + GMAC_IRQn = 84, /**< 84 SAME54N19A Ethernet MAC (GMAC) */ + TCC0_0_IRQn = 85, /**< 85 SAME54N19A Timer Counter Control 0 (TCC0) IRQ 0 */ + TCC0_1_IRQn = 86, /**< 86 SAME54N19A Timer Counter Control 0 (TCC0) IRQ 1 */ + TCC0_2_IRQn = 87, /**< 87 SAME54N19A Timer Counter Control 0 (TCC0) IRQ 2 */ + TCC0_3_IRQn = 88, /**< 88 SAME54N19A Timer Counter Control 0 (TCC0) IRQ 3 */ + TCC0_4_IRQn = 89, /**< 89 SAME54N19A Timer Counter Control 0 (TCC0) IRQ 4 */ + TCC0_5_IRQn = 90, /**< 90 SAME54N19A Timer Counter Control 0 (TCC0) IRQ 5 */ + TCC0_6_IRQn = 91, /**< 91 SAME54N19A Timer Counter Control 0 (TCC0) IRQ 6 */ + TCC1_0_IRQn = 92, /**< 92 SAME54N19A Timer Counter Control 1 (TCC1) IRQ 0 */ + TCC1_1_IRQn = 93, /**< 93 SAME54N19A Timer Counter Control 1 (TCC1) IRQ 1 */ + TCC1_2_IRQn = 94, /**< 94 SAME54N19A Timer Counter Control 1 (TCC1) IRQ 2 */ + TCC1_3_IRQn = 95, /**< 95 SAME54N19A Timer Counter Control 1 (TCC1) IRQ 3 */ + TCC1_4_IRQn = 96, /**< 96 SAME54N19A Timer Counter Control 1 (TCC1) IRQ 4 */ + TCC2_0_IRQn = 97, /**< 97 SAME54N19A Timer Counter Control 2 (TCC2) IRQ 0 */ + TCC2_1_IRQn = 98, /**< 98 SAME54N19A Timer Counter Control 2 (TCC2) IRQ 1 */ + TCC2_2_IRQn = 99, /**< 99 SAME54N19A Timer Counter Control 2 (TCC2) IRQ 2 */ + TCC2_3_IRQn = 100, /**< 100 SAME54N19A Timer Counter Control 2 (TCC2) IRQ 3 */ + TCC3_0_IRQn = 101, /**< 101 SAME54N19A Timer Counter Control 3 (TCC3) IRQ 0 */ + TCC3_1_IRQn = 102, /**< 102 SAME54N19A Timer Counter Control 3 (TCC3) IRQ 1 */ + TCC3_2_IRQn = 103, /**< 103 SAME54N19A Timer Counter Control 3 (TCC3) IRQ 2 */ + TCC4_0_IRQn = 104, /**< 104 SAME54N19A Timer Counter Control 4 (TCC4) IRQ 0 */ + TCC4_1_IRQn = 105, /**< 105 SAME54N19A Timer Counter Control 4 (TCC4) IRQ 1 */ + TCC4_2_IRQn = 106, /**< 106 SAME54N19A Timer Counter Control 4 (TCC4) IRQ 2 */ + TC0_IRQn = 107, /**< 107 SAME54N19A Basic Timer Counter 0 (TC0) */ + TC1_IRQn = 108, /**< 108 SAME54N19A Basic Timer Counter 1 (TC1) */ + TC2_IRQn = 109, /**< 109 SAME54N19A Basic Timer Counter 2 (TC2) */ + TC3_IRQn = 110, /**< 110 SAME54N19A Basic Timer Counter 3 (TC3) */ + TC4_IRQn = 111, /**< 111 SAME54N19A Basic Timer Counter 4 (TC4) */ + TC5_IRQn = 112, /**< 112 SAME54N19A Basic Timer Counter 5 (TC5) */ + TC6_IRQn = 113, /**< 113 SAME54N19A Basic Timer Counter 6 (TC6) */ + TC7_IRQn = 114, /**< 114 SAME54N19A Basic Timer Counter 7 (TC7) */ + PDEC_0_IRQn = 115, /**< 115 SAME54N19A Quadrature Decodeur (PDEC) IRQ 0 */ + PDEC_1_IRQn = 116, /**< 116 SAME54N19A Quadrature Decodeur (PDEC) IRQ 1 */ + PDEC_2_IRQn = 117, /**< 117 SAME54N19A Quadrature Decodeur (PDEC) IRQ 2 */ + ADC0_0_IRQn = 118, /**< 118 SAME54N19A Analog Digital Converter 0 (ADC0) IRQ 0 */ + ADC0_1_IRQn = 119, /**< 119 SAME54N19A Analog Digital Converter 0 (ADC0) IRQ 1 */ + ADC1_0_IRQn = 120, /**< 120 SAME54N19A Analog Digital Converter 1 (ADC1) IRQ 0 */ + ADC1_1_IRQn = 121, /**< 121 SAME54N19A Analog Digital Converter 1 (ADC1) IRQ 1 */ + AC_IRQn = 122, /**< 122 SAME54N19A Analog Comparators (AC) */ + DAC_0_IRQn = 123, /**< 123 SAME54N19A Digital-to-Analog Converter (DAC) IRQ 0 */ + DAC_1_IRQn = 124, /**< 124 SAME54N19A Digital-to-Analog Converter (DAC) IRQ 1 */ + DAC_2_IRQn = 125, /**< 125 SAME54N19A Digital-to-Analog Converter (DAC) IRQ 2 */ + DAC_3_IRQn = 126, /**< 126 SAME54N19A Digital-to-Analog Converter (DAC) IRQ 3 */ + DAC_4_IRQn = 127, /**< 127 SAME54N19A Digital-to-Analog Converter (DAC) IRQ 4 */ + I2S_IRQn = 128, /**< 128 SAME54N19A Inter-IC Sound Interface (I2S) */ + PCC_IRQn = 129, /**< 129 SAME54N19A Parallel Capture Controller (PCC) */ + AES_IRQn = 130, /**< 130 SAME54N19A Advanced Encryption Standard (AES) */ + TRNG_IRQn = 131, /**< 131 SAME54N19A True Random Generator (TRNG) */ + ICM_IRQn = 132, /**< 132 SAME54N19A Integrity Check Monitor (ICM) */ + PUKCC_IRQn = 133, /**< 133 SAME54N19A PUblic-Key Cryptography Controller (PUKCC) */ + QSPI_IRQn = 134, /**< 134 SAME54N19A Quad SPI interface (QSPI) */ + SDHC0_IRQn = 135, /**< 135 SAME54N19A SD/MMC Host Controller 0 (SDHC0) */ + SDHC1_IRQn = 136, /**< 136 SAME54N19A SD/MMC Host Controller 1 (SDHC1) */ + + PERIPH_COUNT_IRQn = 137 /**< Number of peripheral IDs */ +} IRQn_Type; + +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNonMaskableInt_Handler; + void* pfnHardFault_Handler; + void* pfnMemManagement_Handler; + void* pfnBusFault_Handler; + void* pfnUsageFault_Handler; + void* pvReservedM9; + void* pvReservedM8; + void* pvReservedM7; + void* pvReservedM6; + void* pfnSVCall_Handler; + void* pfnDebugMonitor_Handler; + void* pvReservedM3; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; + + /* Peripheral handlers */ + void* pfnPM_Handler; /* 0 Power Manager */ + void* pfnMCLK_Handler; /* 1 Main Clock */ + void* pfnOSCCTRL_0_Handler; /* 2 Oscillators Control IRQ 0 */ + void* pfnOSCCTRL_1_Handler; /* 3 Oscillators Control IRQ 1 */ + void* pfnOSCCTRL_2_Handler; /* 4 Oscillators Control IRQ 2 */ + void* pfnOSCCTRL_3_Handler; /* 5 Oscillators Control IRQ 3 */ + void* pfnOSCCTRL_4_Handler; /* 6 Oscillators Control IRQ 4 */ + void* pfnOSC32KCTRL_Handler; /* 7 32kHz Oscillators Control */ + void* pfnSUPC_0_Handler; /* 8 Supply Controller IRQ 0 */ + void* pfnSUPC_1_Handler; /* 9 Supply Controller IRQ 1 */ + void* pfnWDT_Handler; /* 10 Watchdog Timer */ + void* pfnRTC_Handler; /* 11 Real-Time Counter */ + void* pfnEIC_0_Handler; /* 12 External Interrupt Controller IRQ 0 */ + void* pfnEIC_1_Handler; /* 13 External Interrupt Controller IRQ 1 */ + void* pfnEIC_2_Handler; /* 14 External Interrupt Controller IRQ 2 */ + void* pfnEIC_3_Handler; /* 15 External Interrupt Controller IRQ 3 */ + void* pfnEIC_4_Handler; /* 16 External Interrupt Controller IRQ 4 */ + void* pfnEIC_5_Handler; /* 17 External Interrupt Controller IRQ 5 */ + void* pfnEIC_6_Handler; /* 18 External Interrupt Controller IRQ 6 */ + void* pfnEIC_7_Handler; /* 19 External Interrupt Controller IRQ 7 */ + void* pfnEIC_8_Handler; /* 20 External Interrupt Controller IRQ 8 */ + void* pfnEIC_9_Handler; /* 21 External Interrupt Controller IRQ 9 */ + void* pfnEIC_10_Handler; /* 22 External Interrupt Controller IRQ 10 */ + void* pfnEIC_11_Handler; /* 23 External Interrupt Controller IRQ 11 */ + void* pfnEIC_12_Handler; /* 24 External Interrupt Controller IRQ 12 */ + void* pfnEIC_13_Handler; /* 25 External Interrupt Controller IRQ 13 */ + void* pfnEIC_14_Handler; /* 26 External Interrupt Controller IRQ 14 */ + void* pfnEIC_15_Handler; /* 27 External Interrupt Controller IRQ 15 */ + void* pfnFREQM_Handler; /* 28 Frequency Meter */ + void* pfnNVMCTRL_0_Handler; /* 29 Non-Volatile Memory Controller IRQ 0 */ + void* pfnNVMCTRL_1_Handler; /* 30 Non-Volatile Memory Controller IRQ 1 */ + void* pfnDMAC_0_Handler; /* 31 Direct Memory Access Controller IRQ 0 */ + void* pfnDMAC_1_Handler; /* 32 Direct Memory Access Controller IRQ 1 */ + void* pfnDMAC_2_Handler; /* 33 Direct Memory Access Controller IRQ 2 */ + void* pfnDMAC_3_Handler; /* 34 Direct Memory Access Controller IRQ 3 */ + void* pfnDMAC_4_Handler; /* 35 Direct Memory Access Controller IRQ 4 */ + void* pfnEVSYS_0_Handler; /* 36 Event System Interface IRQ 0 */ + void* pfnEVSYS_1_Handler; /* 37 Event System Interface IRQ 1 */ + void* pfnEVSYS_2_Handler; /* 38 Event System Interface IRQ 2 */ + void* pfnEVSYS_3_Handler; /* 39 Event System Interface IRQ 3 */ + void* pfnEVSYS_4_Handler; /* 40 Event System Interface IRQ 4 */ + void* pfnPAC_Handler; /* 41 Peripheral Access Controller */ + void* pvReserved42; + void* pvReserved43; + void* pvReserved44; + void* pfnRAMECC_Handler; /* 45 RAM ECC */ + void* pfnSERCOM0_0_Handler; /* 46 Serial Communication Interface 0 IRQ 0 */ + void* pfnSERCOM0_1_Handler; /* 47 Serial Communication Interface 0 IRQ 1 */ + void* pfnSERCOM0_2_Handler; /* 48 Serial Communication Interface 0 IRQ 2 */ + void* pfnSERCOM0_3_Handler; /* 49 Serial Communication Interface 0 IRQ 3 */ + void* pfnSERCOM1_0_Handler; /* 50 Serial Communication Interface 1 IRQ 0 */ + void* pfnSERCOM1_1_Handler; /* 51 Serial Communication Interface 1 IRQ 1 */ + void* pfnSERCOM1_2_Handler; /* 52 Serial Communication Interface 1 IRQ 2 */ + void* pfnSERCOM1_3_Handler; /* 53 Serial Communication Interface 1 IRQ 3 */ + void* pfnSERCOM2_0_Handler; /* 54 Serial Communication Interface 2 IRQ 0 */ + void* pfnSERCOM2_1_Handler; /* 55 Serial Communication Interface 2 IRQ 1 */ + void* pfnSERCOM2_2_Handler; /* 56 Serial Communication Interface 2 IRQ 2 */ + void* pfnSERCOM2_3_Handler; /* 57 Serial Communication Interface 2 IRQ 3 */ + void* pfnSERCOM3_0_Handler; /* 58 Serial Communication Interface 3 IRQ 0 */ + void* pfnSERCOM3_1_Handler; /* 59 Serial Communication Interface 3 IRQ 1 */ + void* pfnSERCOM3_2_Handler; /* 60 Serial Communication Interface 3 IRQ 2 */ + void* pfnSERCOM3_3_Handler; /* 61 Serial Communication Interface 3 IRQ 3 */ + void* pfnSERCOM4_0_Handler; /* 62 Serial Communication Interface 4 IRQ 0 */ + void* pfnSERCOM4_1_Handler; /* 63 Serial Communication Interface 4 IRQ 1 */ + void* pfnSERCOM4_2_Handler; /* 64 Serial Communication Interface 4 IRQ 2 */ + void* pfnSERCOM4_3_Handler; /* 65 Serial Communication Interface 4 IRQ 3 */ + void* pfnSERCOM5_0_Handler; /* 66 Serial Communication Interface 5 IRQ 0 */ + void* pfnSERCOM5_1_Handler; /* 67 Serial Communication Interface 5 IRQ 1 */ + void* pfnSERCOM5_2_Handler; /* 68 Serial Communication Interface 5 IRQ 2 */ + void* pfnSERCOM5_3_Handler; /* 69 Serial Communication Interface 5 IRQ 3 */ + void* pfnSERCOM6_0_Handler; /* 70 Serial Communication Interface 6 IRQ 0 */ + void* pfnSERCOM6_1_Handler; /* 71 Serial Communication Interface 6 IRQ 1 */ + void* pfnSERCOM6_2_Handler; /* 72 Serial Communication Interface 6 IRQ 2 */ + void* pfnSERCOM6_3_Handler; /* 73 Serial Communication Interface 6 IRQ 3 */ + void* pfnSERCOM7_0_Handler; /* 74 Serial Communication Interface 7 IRQ 0 */ + void* pfnSERCOM7_1_Handler; /* 75 Serial Communication Interface 7 IRQ 1 */ + void* pfnSERCOM7_2_Handler; /* 76 Serial Communication Interface 7 IRQ 2 */ + void* pfnSERCOM7_3_Handler; /* 77 Serial Communication Interface 7 IRQ 3 */ + void* pfnCAN0_Handler; /* 78 Control Area Network 0 */ + void* pfnCAN1_Handler; /* 79 Control Area Network 1 */ + void* pfnUSB_0_Handler; /* 80 Universal Serial Bus IRQ 0 */ + void* pfnUSB_1_Handler; /* 81 Universal Serial Bus IRQ 1 */ + void* pfnUSB_2_Handler; /* 82 Universal Serial Bus IRQ 2 */ + void* pfnUSB_3_Handler; /* 83 Universal Serial Bus IRQ 3 */ + void* pfnGMAC_Handler; /* 84 Ethernet MAC */ + void* pfnTCC0_0_Handler; /* 85 Timer Counter Control 0 IRQ 0 */ + void* pfnTCC0_1_Handler; /* 86 Timer Counter Control 0 IRQ 1 */ + void* pfnTCC0_2_Handler; /* 87 Timer Counter Control 0 IRQ 2 */ + void* pfnTCC0_3_Handler; /* 88 Timer Counter Control 0 IRQ 3 */ + void* pfnTCC0_4_Handler; /* 89 Timer Counter Control 0 IRQ 4 */ + void* pfnTCC0_5_Handler; /* 90 Timer Counter Control 0 IRQ 5 */ + void* pfnTCC0_6_Handler; /* 91 Timer Counter Control 0 IRQ 6 */ + void* pfnTCC1_0_Handler; /* 92 Timer Counter Control 1 IRQ 0 */ + void* pfnTCC1_1_Handler; /* 93 Timer Counter Control 1 IRQ 1 */ + void* pfnTCC1_2_Handler; /* 94 Timer Counter Control 1 IRQ 2 */ + void* pfnTCC1_3_Handler; /* 95 Timer Counter Control 1 IRQ 3 */ + void* pfnTCC1_4_Handler; /* 96 Timer Counter Control 1 IRQ 4 */ + void* pfnTCC2_0_Handler; /* 97 Timer Counter Control 2 IRQ 0 */ + void* pfnTCC2_1_Handler; /* 98 Timer Counter Control 2 IRQ 1 */ + void* pfnTCC2_2_Handler; /* 99 Timer Counter Control 2 IRQ 2 */ + void* pfnTCC2_3_Handler; /* 100 Timer Counter Control 2 IRQ 3 */ + void* pfnTCC3_0_Handler; /* 101 Timer Counter Control 3 IRQ 0 */ + void* pfnTCC3_1_Handler; /* 102 Timer Counter Control 3 IRQ 1 */ + void* pfnTCC3_2_Handler; /* 103 Timer Counter Control 3 IRQ 2 */ + void* pfnTCC4_0_Handler; /* 104 Timer Counter Control 4 IRQ 0 */ + void* pfnTCC4_1_Handler; /* 105 Timer Counter Control 4 IRQ 1 */ + void* pfnTCC4_2_Handler; /* 106 Timer Counter Control 4 IRQ 2 */ + void* pfnTC0_Handler; /* 107 Basic Timer Counter 0 */ + void* pfnTC1_Handler; /* 108 Basic Timer Counter 1 */ + void* pfnTC2_Handler; /* 109 Basic Timer Counter 2 */ + void* pfnTC3_Handler; /* 110 Basic Timer Counter 3 */ + void* pfnTC4_Handler; /* 111 Basic Timer Counter 4 */ + void* pfnTC5_Handler; /* 112 Basic Timer Counter 5 */ + void* pfnTC6_Handler; /* 113 Basic Timer Counter 6 */ + void* pfnTC7_Handler; /* 114 Basic Timer Counter 7 */ + void* pfnPDEC_0_Handler; /* 115 Quadrature Decodeur IRQ 0 */ + void* pfnPDEC_1_Handler; /* 116 Quadrature Decodeur IRQ 1 */ + void* pfnPDEC_2_Handler; /* 117 Quadrature Decodeur IRQ 2 */ + void* pfnADC0_0_Handler; /* 118 Analog Digital Converter 0 IRQ 0 */ + void* pfnADC0_1_Handler; /* 119 Analog Digital Converter 0 IRQ 1 */ + void* pfnADC1_0_Handler; /* 120 Analog Digital Converter 1 IRQ 0 */ + void* pfnADC1_1_Handler; /* 121 Analog Digital Converter 1 IRQ 1 */ + void* pfnAC_Handler; /* 122 Analog Comparators */ + void* pfnDAC_0_Handler; /* 123 Digital-to-Analog Converter IRQ 0 */ + void* pfnDAC_1_Handler; /* 124 Digital-to-Analog Converter IRQ 1 */ + void* pfnDAC_2_Handler; /* 125 Digital-to-Analog Converter IRQ 2 */ + void* pfnDAC_3_Handler; /* 126 Digital-to-Analog Converter IRQ 3 */ + void* pfnDAC_4_Handler; /* 127 Digital-to-Analog Converter IRQ 4 */ + void* pfnI2S_Handler; /* 128 Inter-IC Sound Interface */ + void* pfnPCC_Handler; /* 129 Parallel Capture Controller */ + void* pfnAES_Handler; /* 130 Advanced Encryption Standard */ + void* pfnTRNG_Handler; /* 131 True Random Generator */ + void* pfnICM_Handler; /* 132 Integrity Check Monitor */ + void* pfnPUKCC_Handler; /* 133 PUblic-Key Cryptography Controller */ + void* pfnQSPI_Handler; /* 134 Quad SPI interface */ + void* pfnSDHC0_Handler; /* 135 SD/MMC Host Controller 0 */ + void* pfnSDHC1_Handler; /* 136 SD/MMC Host Controller 1 */ +} DeviceVectors; + +/* Cortex-M4 processor handlers */ +void Reset_Handler ( void ); +void NonMaskableInt_Handler ( void ); +void HardFault_Handler ( void ); +void MemManagement_Handler ( void ); +void BusFault_Handler ( void ); +void UsageFault_Handler ( void ); +void SVCall_Handler ( void ); +void DebugMonitor_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); + +/* Peripherals handlers */ +void PM_Handler ( void ); +void MCLK_Handler ( void ); +void OSCCTRL_0_Handler ( void ); +void OSCCTRL_1_Handler ( void ); +void OSCCTRL_2_Handler ( void ); +void OSCCTRL_3_Handler ( void ); +void OSCCTRL_4_Handler ( void ); +void OSC32KCTRL_Handler ( void ); +void SUPC_0_Handler ( void ); +void SUPC_1_Handler ( void ); +void WDT_Handler ( void ); +void RTC_Handler ( void ); +void EIC_0_Handler ( void ); +void EIC_1_Handler ( void ); +void EIC_2_Handler ( void ); +void EIC_3_Handler ( void ); +void EIC_4_Handler ( void ); +void EIC_5_Handler ( void ); +void EIC_6_Handler ( void ); +void EIC_7_Handler ( void ); +void EIC_8_Handler ( void ); +void EIC_9_Handler ( void ); +void EIC_10_Handler ( void ); +void EIC_11_Handler ( void ); +void EIC_12_Handler ( void ); +void EIC_13_Handler ( void ); +void EIC_14_Handler ( void ); +void EIC_15_Handler ( void ); +void FREQM_Handler ( void ); +void NVMCTRL_0_Handler ( void ); +void NVMCTRL_1_Handler ( void ); +void DMAC_0_Handler ( void ); +void DMAC_1_Handler ( void ); +void DMAC_2_Handler ( void ); +void DMAC_3_Handler ( void ); +void DMAC_4_Handler ( void ); +void EVSYS_0_Handler ( void ); +void EVSYS_1_Handler ( void ); +void EVSYS_2_Handler ( void ); +void EVSYS_3_Handler ( void ); +void EVSYS_4_Handler ( void ); +void PAC_Handler ( void ); +void RAMECC_Handler ( void ); +void SERCOM0_0_Handler ( void ); +void SERCOM0_1_Handler ( void ); +void SERCOM0_2_Handler ( void ); +void SERCOM0_3_Handler ( void ); +void SERCOM1_0_Handler ( void ); +void SERCOM1_1_Handler ( void ); +void SERCOM1_2_Handler ( void ); +void SERCOM1_3_Handler ( void ); +void SERCOM2_0_Handler ( void ); +void SERCOM2_1_Handler ( void ); +void SERCOM2_2_Handler ( void ); +void SERCOM2_3_Handler ( void ); +void SERCOM3_0_Handler ( void ); +void SERCOM3_1_Handler ( void ); +void SERCOM3_2_Handler ( void ); +void SERCOM3_3_Handler ( void ); +void SERCOM4_0_Handler ( void ); +void SERCOM4_1_Handler ( void ); +void SERCOM4_2_Handler ( void ); +void SERCOM4_3_Handler ( void ); +void SERCOM5_0_Handler ( void ); +void SERCOM5_1_Handler ( void ); +void SERCOM5_2_Handler ( void ); +void SERCOM5_3_Handler ( void ); +void SERCOM6_0_Handler ( void ); +void SERCOM6_1_Handler ( void ); +void SERCOM6_2_Handler ( void ); +void SERCOM6_3_Handler ( void ); +void SERCOM7_0_Handler ( void ); +void SERCOM7_1_Handler ( void ); +void SERCOM7_2_Handler ( void ); +void SERCOM7_3_Handler ( void ); +void CAN0_Handler ( void ); +void CAN1_Handler ( void ); +void USB_0_Handler ( void ); +void USB_1_Handler ( void ); +void USB_2_Handler ( void ); +void USB_3_Handler ( void ); +void GMAC_Handler ( void ); +void TCC0_0_Handler ( void ); +void TCC0_1_Handler ( void ); +void TCC0_2_Handler ( void ); +void TCC0_3_Handler ( void ); +void TCC0_4_Handler ( void ); +void TCC0_5_Handler ( void ); +void TCC0_6_Handler ( void ); +void TCC1_0_Handler ( void ); +void TCC1_1_Handler ( void ); +void TCC1_2_Handler ( void ); +void TCC1_3_Handler ( void ); +void TCC1_4_Handler ( void ); +void TCC2_0_Handler ( void ); +void TCC2_1_Handler ( void ); +void TCC2_2_Handler ( void ); +void TCC2_3_Handler ( void ); +void TCC3_0_Handler ( void ); +void TCC3_1_Handler ( void ); +void TCC3_2_Handler ( void ); +void TCC4_0_Handler ( void ); +void TCC4_1_Handler ( void ); +void TCC4_2_Handler ( void ); +void TC0_Handler ( void ); +void TC1_Handler ( void ); +void TC2_Handler ( void ); +void TC3_Handler ( void ); +void TC4_Handler ( void ); +void TC5_Handler ( void ); +void TC6_Handler ( void ); +void TC7_Handler ( void ); +void PDEC_0_Handler ( void ); +void PDEC_1_Handler ( void ); +void PDEC_2_Handler ( void ); +void ADC0_0_Handler ( void ); +void ADC0_1_Handler ( void ); +void ADC1_0_Handler ( void ); +void ADC1_1_Handler ( void ); +void AC_Handler ( void ); +void DAC_0_Handler ( void ); +void DAC_1_Handler ( void ); +void DAC_2_Handler ( void ); +void DAC_3_Handler ( void ); +void DAC_4_Handler ( void ); +void I2S_Handler ( void ); +void PCC_Handler ( void ); +void AES_Handler ( void ); +void TRNG_Handler ( void ); +void ICM_Handler ( void ); +void PUKCC_Handler ( void ); +void QSPI_Handler ( void ); +void SDHC0_Handler ( void ); +void SDHC1_Handler ( void ); + +/* + * \brief Configuration of the Cortex-M4 Processor and Core Peripherals + */ + +#define __CM4_REV 1 /*!< Core revision r0p1 */ +#define __DEBUG_LVL 3 /*!< Full debug plus DWT data matching */ +#define __FPU_PRESENT 1 /*!< FPU present or not */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ +#define __NVIC_PRIO_BITS 3 /*!< Number of bits used for Priority Levels */ +#define __TRACE_LVL 2 /*!< Full trace: ITM, DWT triggers and counters, ETM */ +#define __VTOR_PRESENT 1 /*!< VTOR present or not */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + +/** + * \brief CMSIS includes + */ + +#include +#if !defined DONT_USE_CMSIS_INIT +#include "system_same54.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/*@}*/ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAME54N19A */ +/* ************************************************************************** */ +/** \defgroup SAME54N19A_api Peripheral Software API */ +/*@{*/ + +#include "component/ac.h" +#include "component/adc.h" +#include "component/aes.h" +#include "component/can.h" +#include "component/ccl.h" +#include "component/cmcc.h" +#include "component/dac.h" +#include "component/dmac.h" +#include "component/dsu.h" +#include "component/eic.h" +#include "component/evsys.h" +#include "component/freqm.h" +#include "component/gclk.h" +#include "component/gmac.h" +#include "component/hmatrixb.h" +#include "component/icm.h" +#include "component/i2s.h" +#include "component/mclk.h" +#include "component/nvmctrl.h" +#include "component/oscctrl.h" +#include "component/osc32kctrl.h" +#include "component/pac.h" +#include "component/pcc.h" +#include "component/pdec.h" +#include "component/pm.h" +#include "component/port.h" +#include "component/qspi.h" +#include "component/ramecc.h" +#include "component/rstc.h" +#include "component/rtc.h" +#include "component/sdhc.h" +#include "component/sercom.h" +#include "component/supc.h" +#include "component/tc.h" +#include "component/tcc.h" +#include "component/trng.h" +#include "component/usb.h" +#include "component/wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/** REGISTERS ACCESS DEFINITIONS FOR SAME54N19A */ +/* ************************************************************************** */ +/** \defgroup SAME54N19A_reg Registers Access Definitions */ +/*@{*/ + +#include "instance/ac.h" +#include "instance/adc0.h" +#include "instance/adc1.h" +#include "instance/aes.h" +#include "instance/can0.h" +#include "instance/can1.h" +#include "instance/ccl.h" +#include "instance/cmcc.h" +#include "instance/dac.h" +#include "instance/dmac.h" +#include "instance/dsu.h" +#include "instance/eic.h" +#include "instance/evsys.h" +#include "instance/freqm.h" +#include "instance/gclk.h" +#include "instance/gmac.h" +#include "instance/hmatrix.h" +#include "instance/icm.h" +#include "instance/i2s.h" +#include "instance/mclk.h" +#include "instance/nvmctrl.h" +#include "instance/oscctrl.h" +#include "instance/osc32kctrl.h" +#include "instance/pac.h" +#include "instance/pcc.h" +#include "instance/pdec.h" +#include "instance/pm.h" +#include "instance/port.h" +#include "instance/pukcc.h" +#include "instance/qspi.h" +#include "instance/ramecc.h" +#include "instance/rstc.h" +#include "instance/rtc.h" +#include "instance/sdhc0.h" +#include "instance/sdhc1.h" +#include "instance/sercom0.h" +#include "instance/sercom1.h" +#include "instance/sercom2.h" +#include "instance/sercom3.h" +#include "instance/sercom4.h" +#include "instance/sercom5.h" +#include "instance/sercom6.h" +#include "instance/sercom7.h" +#include "instance/supc.h" +#include "instance/tc0.h" +#include "instance/tc1.h" +#include "instance/tc2.h" +#include "instance/tc3.h" +#include "instance/tc4.h" +#include "instance/tc5.h" +#include "instance/tc6.h" +#include "instance/tc7.h" +#include "instance/tcc0.h" +#include "instance/tcc1.h" +#include "instance/tcc2.h" +#include "instance/tcc3.h" +#include "instance/tcc4.h" +#include "instance/trng.h" +#include "instance/usb.h" +#include "instance/wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/** PERIPHERAL ID DEFINITIONS FOR SAME54N19A */ +/* ************************************************************************** */ +/** \defgroup SAME54N19A_id Peripheral Ids Definitions */ +/*@{*/ + +// Peripheral instances on HPB0 bridge +#define ID_PAC 0 /**< \brief Peripheral Access Controller (PAC) */ +#define ID_PM 1 /**< \brief Power Manager (PM) */ +#define ID_MCLK 2 /**< \brief Main Clock (MCLK) */ +#define ID_RSTC 3 /**< \brief Reset Controller (RSTC) */ +#define ID_OSCCTRL 4 /**< \brief Oscillators Control (OSCCTRL) */ +#define ID_OSC32KCTRL 5 /**< \brief 32kHz Oscillators Control (OSC32KCTRL) */ +#define ID_SUPC 6 /**< \brief Supply Controller (SUPC) */ +#define ID_GCLK 7 /**< \brief Generic Clock Generator (GCLK) */ +#define ID_WDT 8 /**< \brief Watchdog Timer (WDT) */ +#define ID_RTC 9 /**< \brief Real-Time Counter (RTC) */ +#define ID_EIC 10 /**< \brief External Interrupt Controller (EIC) */ +#define ID_FREQM 11 /**< \brief Frequency Meter (FREQM) */ +#define ID_SERCOM0 12 /**< \brief Serial Communication Interface 0 (SERCOM0) */ +#define ID_SERCOM1 13 /**< \brief Serial Communication Interface 1 (SERCOM1) */ +#define ID_TC0 14 /**< \brief Basic Timer Counter 0 (TC0) */ +#define ID_TC1 15 /**< \brief Basic Timer Counter 1 (TC1) */ + +// Peripheral instances on HPB1 bridge +#define ID_USB 32 /**< \brief Universal Serial Bus (USB) */ +#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ +#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ +#define ID_CMCC 35 /**< \brief Cortex M Cache Controller (CMCC) */ +#define ID_PORT 36 /**< \brief Port Module (PORT) */ +#define ID_DMAC 37 /**< \brief Direct Memory Access Controller (DMAC) */ +#define ID_HMATRIX 38 /**< \brief HSB Matrix (HMATRIX) */ +#define ID_EVSYS 39 /**< \brief Event System Interface (EVSYS) */ +#define ID_SERCOM2 41 /**< \brief Serial Communication Interface 2 (SERCOM2) */ +#define ID_SERCOM3 42 /**< \brief Serial Communication Interface 3 (SERCOM3) */ +#define ID_TCC0 43 /**< \brief Timer Counter Control 0 (TCC0) */ +#define ID_TCC1 44 /**< \brief Timer Counter Control 1 (TCC1) */ +#define ID_TC2 45 /**< \brief Basic Timer Counter 2 (TC2) */ +#define ID_TC3 46 /**< \brief Basic Timer Counter 3 (TC3) */ +#define ID_RAMECC 48 /**< \brief RAM ECC (RAMECC) */ + +// Peripheral instances on HPB2 bridge +#define ID_CAN0 64 /**< \brief Control Area Network 0 (CAN0) */ +#define ID_CAN1 65 /**< \brief Control Area Network 1 (CAN1) */ +#define ID_GMAC 66 /**< \brief Ethernet MAC (GMAC) */ +#define ID_TCC2 67 /**< \brief Timer Counter Control 2 (TCC2) */ +#define ID_TCC3 68 /**< \brief Timer Counter Control 3 (TCC3) */ +#define ID_TC4 69 /**< \brief Basic Timer Counter 4 (TC4) */ +#define ID_TC5 70 /**< \brief Basic Timer Counter 5 (TC5) */ +#define ID_PDEC 71 /**< \brief Quadrature Decodeur (PDEC) */ +#define ID_AC 72 /**< \brief Analog Comparators (AC) */ +#define ID_AES 73 /**< \brief Advanced Encryption Standard (AES) */ +#define ID_TRNG 74 /**< \brief True Random Generator (TRNG) */ +#define ID_ICM 75 /**< \brief Integrity Check Monitor (ICM) */ +#define ID_PUKCC 76 /**< \brief PUblic-Key Cryptography Controller (PUKCC) */ +#define ID_QSPI 77 /**< \brief Quad SPI interface (QSPI) */ +#define ID_CCL 78 /**< \brief Configurable Custom Logic (CCL) */ + +// Peripheral instances on HPB3 bridge +#define ID_SERCOM4 96 /**< \brief Serial Communication Interface 4 (SERCOM4) */ +#define ID_SERCOM5 97 /**< \brief Serial Communication Interface 5 (SERCOM5) */ +#define ID_SERCOM6 98 /**< \brief Serial Communication Interface 6 (SERCOM6) */ +#define ID_SERCOM7 99 /**< \brief Serial Communication Interface 7 (SERCOM7) */ +#define ID_TCC4 100 /**< \brief Timer Counter Control 4 (TCC4) */ +#define ID_TC6 101 /**< \brief Basic Timer Counter 6 (TC6) */ +#define ID_TC7 102 /**< \brief Basic Timer Counter 7 (TC7) */ +#define ID_ADC0 103 /**< \brief Analog Digital Converter 0 (ADC0) */ +#define ID_ADC1 104 /**< \brief Analog Digital Converter 1 (ADC1) */ +#define ID_DAC 105 /**< \brief Digital-to-Analog Converter (DAC) */ +#define ID_I2S 106 /**< \brief Inter-IC Sound Interface (I2S) */ +#define ID_PCC 107 /**< \brief Parallel Capture Controller (PCC) */ + +// Peripheral instances on AHB (as if on bridge 4) +#define ID_SDHC0 128 /**< \brief SD/MMC Host Controller (SDHC0) */ +#define ID_SDHC1 129 /**< \brief SD/MMC Host Controller (SDHC1) */ + +#define ID_PERIPH_COUNT 130 /**< \brief Max number of peripheral IDs */ +/*@}*/ + +/* ************************************************************************** */ +/** BASE ADDRESS DEFINITIONS FOR SAME54N19A */ +/* ************************************************************************** */ +/** \defgroup SAME54N19A_base Peripheral Base Address Definitions */ +/*@{*/ + +#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) +#define AC (0x42002000) /**< \brief (AC) APB Base Address */ +#define ADC0 (0x43001C00) /**< \brief (ADC0) APB Base Address */ +#define ADC1 (0x43002000) /**< \brief (ADC1) APB Base Address */ +#define AES (0x42002400) /**< \brief (AES) APB Base Address */ +#define CAN0 (0x42000000) /**< \brief (CAN0) APB Base Address */ +#define CAN1 (0x42000400) /**< \brief (CAN1) APB Base Address */ +#define CCL (0x42003800) /**< \brief (CCL) APB Base Address */ +#define CMCC (0x41006000) /**< \brief (CMCC) APB Base Address */ +#define CMCC_AHB (0x03000000) /**< \brief (CMCC) AHB Base Address */ +#define DAC (0x43002400) /**< \brief (DAC) APB Base Address */ +#define DMAC (0x4100A000) /**< \brief (DMAC) APB Base Address */ +#define DSU (0x41002000) /**< \brief (DSU) APB Base Address */ +#define EIC (0x40002800) /**< \brief (EIC) APB Base Address */ +#define EVSYS (0x4100E000) /**< \brief (EVSYS) APB Base Address */ +#define FREQM (0x40002C00) /**< \brief (FREQM) APB Base Address */ +#define GCLK (0x40001C00) /**< \brief (GCLK) APB Base Address */ +#define GMAC (0x42000800) /**< \brief (GMAC) APB Base Address */ +#define HMATRIX (0x4100C000) /**< \brief (HMATRIX) APB Base Address */ +#define ICM (0x42002C00) /**< \brief (ICM) APB Base Address */ +#define I2S (0x43002800) /**< \brief (I2S) APB Base Address */ +#define MCLK (0x40000800) /**< \brief (MCLK) APB Base Address */ +#define NVMCTRL (0x41004000) /**< \brief (NVMCTRL) APB Base Address */ +#define NVMCTRL_SW0 (0x00800080) /**< \brief (NVMCTRL) SW0 Base Address */ +#define NVMCTRL_TEMP_LOG (0x00800100) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ +#define NVMCTRL_USER (0x00804000) /**< \brief (NVMCTRL) USER Base Address */ +#define OSCCTRL (0x40001000) /**< \brief (OSCCTRL) APB Base Address */ +#define OSC32KCTRL (0x40001400) /**< \brief (OSC32KCTRL) APB Base Address */ +#define PAC (0x40000000) /**< \brief (PAC) APB Base Address */ +#define PCC (0x43002C00) /**< \brief (PCC) APB Base Address */ +#define PDEC (0x42001C00) /**< \brief (PDEC) APB Base Address */ +#define PM (0x40000400) /**< \brief (PM) APB Base Address */ +#define PORT (0x41008000) /**< \brief (PORT) APB Base Address */ +#define PUKCC (0x42003000) /**< \brief (PUKCC) APB Base Address */ +#define PUKCC_AHB (0x02000000) /**< \brief (PUKCC) AHB Base Address */ +#define QSPI (0x42003400) /**< \brief (QSPI) APB Base Address */ +#define QSPI_AHB (0x04000000) /**< \brief (QSPI) AHB Base Address */ +#define RAMECC (0x41020000) /**< \brief (RAMECC) APB Base Address */ +#define RSTC (0x40000C00) /**< \brief (RSTC) APB Base Address */ +#define RTC (0x40002400) /**< \brief (RTC) APB Base Address */ +#define SDHC0 (0x45000000) /**< \brief (SDHC0) AHB Base Address */ +#define SDHC1 (0x46000000) /**< \brief (SDHC1) AHB Base Address */ +#define SERCOM0 (0x40003000) /**< \brief (SERCOM0) APB Base Address */ +#define SERCOM1 (0x40003400) /**< \brief (SERCOM1) APB Base Address */ +#define SERCOM2 (0x41012000) /**< \brief (SERCOM2) APB Base Address */ +#define SERCOM3 (0x41014000) /**< \brief (SERCOM3) APB Base Address */ +#define SERCOM4 (0x43000000) /**< \brief (SERCOM4) APB Base Address */ +#define SERCOM5 (0x43000400) /**< \brief (SERCOM5) APB Base Address */ +#define SERCOM6 (0x43000800) /**< \brief (SERCOM6) APB Base Address */ +#define SERCOM7 (0x43000C00) /**< \brief (SERCOM7) APB Base Address */ +#define SUPC (0x40001800) /**< \brief (SUPC) APB Base Address */ +#define TC0 (0x40003800) /**< \brief (TC0) APB Base Address */ +#define TC1 (0x40003C00) /**< \brief (TC1) APB Base Address */ +#define TC2 (0x4101A000) /**< \brief (TC2) APB Base Address */ +#define TC3 (0x4101C000) /**< \brief (TC3) APB Base Address */ +#define TC4 (0x42001400) /**< \brief (TC4) APB Base Address */ +#define TC5 (0x42001800) /**< \brief (TC5) APB Base Address */ +#define TC6 (0x43001400) /**< \brief (TC6) APB Base Address */ +#define TC7 (0x43001800) /**< \brief (TC7) APB Base Address */ +#define TCC0 (0x41016000) /**< \brief (TCC0) APB Base Address */ +#define TCC1 (0x41018000) /**< \brief (TCC1) APB Base Address */ +#define TCC2 (0x42000C00) /**< \brief (TCC2) APB Base Address */ +#define TCC3 (0x42001000) /**< \brief (TCC3) APB Base Address */ +#define TCC4 (0x43001000) /**< \brief (TCC4) APB Base Address */ +#define TRNG (0x42002800) /**< \brief (TRNG) APB Base Address */ +#define USB (0x41000000) /**< \brief (USB) APB Base Address */ +#define WDT (0x40002000) /**< \brief (WDT) APB Base Address */ +#else +#define AC ((Ac *)0x42002000UL) /**< \brief (AC) APB Base Address */ +#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ +#define AC_INSTS { AC } /**< \brief (AC) Instances List */ + +#define ADC0 ((Adc *)0x43001C00UL) /**< \brief (ADC0) APB Base Address */ +#define ADC1 ((Adc *)0x43002000UL) /**< \brief (ADC1) APB Base Address */ +#define ADC_INST_NUM 2 /**< \brief (ADC) Number of instances */ +#define ADC_INSTS { ADC0, ADC1 } /**< \brief (ADC) Instances List */ + +#define AES ((Aes *)0x42002400UL) /**< \brief (AES) APB Base Address */ +#define AES_INST_NUM 1 /**< \brief (AES) Number of instances */ +#define AES_INSTS { AES } /**< \brief (AES) Instances List */ + +#define CAN0 ((Can *)0x42000000UL) /**< \brief (CAN0) APB Base Address */ +#define CAN1 ((Can *)0x42000400UL) /**< \brief (CAN1) APB Base Address */ +#define CAN_INST_NUM 2 /**< \brief (CAN) Number of instances */ +#define CAN_INSTS { CAN0, CAN1 } /**< \brief (CAN) Instances List */ + +#define CCL ((Ccl *)0x42003800UL) /**< \brief (CCL) APB Base Address */ +#define CCL_INST_NUM 1 /**< \brief (CCL) Number of instances */ +#define CCL_INSTS { CCL } /**< \brief (CCL) Instances List */ + +#define CMCC ((Cmcc *)0x41006000UL) /**< \brief (CMCC) APB Base Address */ +#define CMCC_AHB (0x03000000UL) /**< \brief (CMCC) AHB Base Address */ +#define CMCC_INST_NUM 1 /**< \brief (CMCC) Number of instances */ +#define CMCC_INSTS { CMCC } /**< \brief (CMCC) Instances List */ + +#define DAC ((Dac *)0x43002400UL) /**< \brief (DAC) APB Base Address */ +#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */ +#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */ + +#define DMAC ((Dmac *)0x4100A000UL) /**< \brief (DMAC) APB Base Address */ +#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ +#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ + +#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ +#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ +#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ + +#define EIC ((Eic *)0x40002800UL) /**< \brief (EIC) APB Base Address */ +#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ +#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ + +#define EVSYS ((Evsys *)0x4100E000UL) /**< \brief (EVSYS) APB Base Address */ +#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ +#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ + +#define FREQM ((Freqm *)0x40002C00UL) /**< \brief (FREQM) APB Base Address */ +#define FREQM_INST_NUM 1 /**< \brief (FREQM) Number of instances */ +#define FREQM_INSTS { FREQM } /**< \brief (FREQM) Instances List */ + +#define GCLK ((Gclk *)0x40001C00UL) /**< \brief (GCLK) APB Base Address */ +#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ +#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ + +#define GMAC ((Gmac *)0x42000800UL) /**< \brief (GMAC) APB Base Address */ +#define GMAC_INST_NUM 1 /**< \brief (GMAC) Number of instances */ +#define GMAC_INSTS { GMAC } /**< \brief (GMAC) Instances List */ + +#define HMATRIX ((Hmatrixb *)0x4100C000UL) /**< \brief (HMATRIX) APB Base Address */ +#define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */ +#define HMATRIXB_INSTS { HMATRIX } /**< \brief (HMATRIXB) Instances List */ + +#define ICM ((Icm *)0x42002C00UL) /**< \brief (ICM) APB Base Address */ +#define ICM_INST_NUM 1 /**< \brief (ICM) Number of instances */ +#define ICM_INSTS { ICM } /**< \brief (ICM) Instances List */ + +#define I2S ((I2s *)0x43002800UL) /**< \brief (I2S) APB Base Address */ +#define I2S_INST_NUM 1 /**< \brief (I2S) Number of instances */ +#define I2S_INSTS { I2S } /**< \brief (I2S) Instances List */ + +#define MCLK ((Mclk *)0x40000800UL) /**< \brief (MCLK) APB Base Address */ +#define MCLK_INST_NUM 1 /**< \brief (MCLK) Number of instances */ +#define MCLK_INSTS { MCLK } /**< \brief (MCLK) Instances List */ + +#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ +#define NVMCTRL_SW0 (0x00800080UL) /**< \brief (NVMCTRL) SW0 Base Address */ +#define NVMCTRL_TEMP_LOG (0x00800100UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ +#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ +#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ +#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ + +#define OSCCTRL ((Oscctrl *)0x40001000UL) /**< \brief (OSCCTRL) APB Base Address */ +#define OSCCTRL_INST_NUM 1 /**< \brief (OSCCTRL) Number of instances */ +#define OSCCTRL_INSTS { OSCCTRL } /**< \brief (OSCCTRL) Instances List */ + +#define OSC32KCTRL ((Osc32kctrl *)0x40001400UL) /**< \brief (OSC32KCTRL) APB Base Address */ +#define OSC32KCTRL_INST_NUM 1 /**< \brief (OSC32KCTRL) Number of instances */ +#define OSC32KCTRL_INSTS { OSC32KCTRL } /**< \brief (OSC32KCTRL) Instances List */ + +#define PAC ((Pac *)0x40000000UL) /**< \brief (PAC) APB Base Address */ +#define PAC_INST_NUM 1 /**< \brief (PAC) Number of instances */ +#define PAC_INSTS { PAC } /**< \brief (PAC) Instances List */ + +#define PCC ((Pcc *)0x43002C00UL) /**< \brief (PCC) APB Base Address */ +#define PCC_INST_NUM 1 /**< \brief (PCC) Number of instances */ +#define PCC_INSTS { PCC } /**< \brief (PCC) Instances List */ + +#define PDEC ((Pdec *)0x42001C00UL) /**< \brief (PDEC) APB Base Address */ +#define PDEC_INST_NUM 1 /**< \brief (PDEC) Number of instances */ +#define PDEC_INSTS { PDEC } /**< \brief (PDEC) Instances List */ + +#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */ +#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ +#define PM_INSTS { PM } /**< \brief (PM) Instances List */ + +#define PORT ((Port *)0x41008000UL) /**< \brief (PORT) APB Base Address */ +#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ +#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ + +#define PUKCC ((void *)0x42003000UL) /**< \brief (PUKCC) APB Base Address */ +#define PUKCC_AHB ((void *)0x02000000UL) /**< \brief (PUKCC) AHB Base Address */ +#define PUKCC_INST_NUM 1 /**< \brief (PUKCC) Number of instances */ +#define PUKCC_INSTS { PUKCC } /**< \brief (PUKCC) Instances List */ + +#define QSPI ((Qspi *)0x42003400UL) /**< \brief (QSPI) APB Base Address */ +#define QSPI_AHB (0x04000000UL) /**< \brief (QSPI) AHB Base Address */ +#define QSPI_INST_NUM 1 /**< \brief (QSPI) Number of instances */ +#define QSPI_INSTS { QSPI } /**< \brief (QSPI) Instances List */ + +#define RAMECC ((Ramecc *)0x41020000UL) /**< \brief (RAMECC) APB Base Address */ +#define RAMECC_INST_NUM 1 /**< \brief (RAMECC) Number of instances */ +#define RAMECC_INSTS { RAMECC } /**< \brief (RAMECC) Instances List */ + +#define RSTC ((Rstc *)0x40000C00UL) /**< \brief (RSTC) APB Base Address */ +#define RSTC_INST_NUM 1 /**< \brief (RSTC) Number of instances */ +#define RSTC_INSTS { RSTC } /**< \brief (RSTC) Instances List */ + +#define RTC ((Rtc *)0x40002400UL) /**< \brief (RTC) APB Base Address */ +#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ +#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ + +#define SDHC0 ((Sdhc *)0x45000000UL) /**< \brief (SDHC0) AHB Base Address */ +#define SDHC1 ((Sdhc *)0x46000000UL) /**< \brief (SDHC1) AHB Base Address */ +#define SDHC_INST_NUM 2 /**< \brief (SDHC) Number of instances */ +#define SDHC_INSTS { SDHC0, SDHC1 } /**< \brief (SDHC) Instances List */ + +#define SERCOM0 ((Sercom *)0x40003000UL) /**< \brief (SERCOM0) APB Base Address */ +#define SERCOM1 ((Sercom *)0x40003400UL) /**< \brief (SERCOM1) APB Base Address */ +#define SERCOM2 ((Sercom *)0x41012000UL) /**< \brief (SERCOM2) APB Base Address */ +#define SERCOM3 ((Sercom *)0x41014000UL) /**< \brief (SERCOM3) APB Base Address */ +#define SERCOM4 ((Sercom *)0x43000000UL) /**< \brief (SERCOM4) APB Base Address */ +#define SERCOM5 ((Sercom *)0x43000400UL) /**< \brief (SERCOM5) APB Base Address */ +#define SERCOM6 ((Sercom *)0x43000800UL) /**< \brief (SERCOM6) APB Base Address */ +#define SERCOM7 ((Sercom *)0x43000C00UL) /**< \brief (SERCOM7) APB Base Address */ +#define SERCOM_INST_NUM 8 /**< \brief (SERCOM) Number of instances */ +#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5, SERCOM6, SERCOM7 } /**< \brief (SERCOM) Instances List */ + +#define SUPC ((Supc *)0x40001800UL) /**< \brief (SUPC) APB Base Address */ +#define SUPC_INST_NUM 1 /**< \brief (SUPC) Number of instances */ +#define SUPC_INSTS { SUPC } /**< \brief (SUPC) Instances List */ + +#define TC0 ((Tc *)0x40003800UL) /**< \brief (TC0) APB Base Address */ +#define TC1 ((Tc *)0x40003C00UL) /**< \brief (TC1) APB Base Address */ +#define TC2 ((Tc *)0x4101A000UL) /**< \brief (TC2) APB Base Address */ +#define TC3 ((Tc *)0x4101C000UL) /**< \brief (TC3) APB Base Address */ +#define TC4 ((Tc *)0x42001400UL) /**< \brief (TC4) APB Base Address */ +#define TC5 ((Tc *)0x42001800UL) /**< \brief (TC5) APB Base Address */ +#define TC6 ((Tc *)0x43001400UL) /**< \brief (TC6) APB Base Address */ +#define TC7 ((Tc *)0x43001800UL) /**< \brief (TC7) APB Base Address */ +#define TC_INST_NUM 8 /**< \brief (TC) Number of instances */ +#define TC_INSTS { TC0, TC1, TC2, TC3, TC4, TC5, TC6, TC7 } /**< \brief (TC) Instances List */ + +#define TCC0 ((Tcc *)0x41016000UL) /**< \brief (TCC0) APB Base Address */ +#define TCC1 ((Tcc *)0x41018000UL) /**< \brief (TCC1) APB Base Address */ +#define TCC2 ((Tcc *)0x42000C00UL) /**< \brief (TCC2) APB Base Address */ +#define TCC3 ((Tcc *)0x42001000UL) /**< \brief (TCC3) APB Base Address */ +#define TCC4 ((Tcc *)0x43001000UL) /**< \brief (TCC4) APB Base Address */ +#define TCC_INST_NUM 5 /**< \brief (TCC) Number of instances */ +#define TCC_INSTS { TCC0, TCC1, TCC2, TCC3, TCC4 } /**< \brief (TCC) Instances List */ + +#define TRNG ((Trng *)0x42002800UL) /**< \brief (TRNG) APB Base Address */ +#define TRNG_INST_NUM 1 /**< \brief (TRNG) Number of instances */ +#define TRNG_INSTS { TRNG } /**< \brief (TRNG) Instances List */ + +#define USB ((Usb *)0x41000000UL) /**< \brief (USB) APB Base Address */ +#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ +#define USB_INSTS { USB } /**< \brief (USB) Instances List */ + +#define WDT ((Wdt *)0x40002000UL) /**< \brief (WDT) APB Base Address */ +#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ +#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ + +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/*@}*/ + +/* ************************************************************************** */ +/** PORT DEFINITIONS FOR SAME54N19A */ +/* ************************************************************************** */ +/** \defgroup SAME54N19A_port PORT Definitions */ +/*@{*/ + +#include "pio/same54n19a.h" +/*@}*/ + +/* ************************************************************************** */ +/** MEMORY MAPPING DEFINITIONS FOR SAME54N19A */ +/* ************************************************************************** */ + +#define HSRAM_SIZE _UL_(0x00030000) /* 192 kB */ +#define FLASH_SIZE _UL_(0x00080000) /* 512 kB */ +#define FLASH_PAGE_SIZE 512 +#define FLASH_NB_OF_PAGES 1024 +#define FLASH_USER_PAGE_SIZE 512 +#define BKUPRAM_SIZE _UL_(0x00002000) /* 8 kB */ +#define QSPI_SIZE _UL_(0x01000000) /* 16384 kB */ + +#define FLASH_ADDR _UL_(0x00000000) /**< FLASH base address */ +#define CMCC_DATARAM_ADDR _UL_(0x03000000) /**< CMCC_DATARAM base address */ +#define CMCC_DATARAM_SIZE _UL_(0x00001000) /**< CMCC_DATARAM size */ +#define CMCC_TAGRAM_ADDR _UL_(0x03001000) /**< CMCC_TAGRAM base address */ +#define CMCC_TAGRAM_SIZE _UL_(0x00000400) /**< CMCC_TAGRAM size */ +#define CMCC_VALIDRAM_ADDR _UL_(0x03002000) /**< CMCC_VALIDRAM base address */ +#define CMCC_VALIDRAM_SIZE _UL_(0x00000040) /**< CMCC_VALIDRAM size */ +#define HSRAM_ADDR _UL_(0x20000000) /**< HSRAM base address */ +#define HSRAM_ETB_ADDR _UL_(0x20000000) /**< HSRAM_ETB base address */ +#define HSRAM_ETB_SIZE _UL_(0x00008000) /**< HSRAM_ETB size */ +#define HSRAM_RET1_ADDR _UL_(0x20000000) /**< HSRAM_RET1 base address */ +#define HSRAM_RET1_SIZE _UL_(0x00008000) /**< HSRAM_RET1 size */ +#define HPB0_ADDR _UL_(0x40000000) /**< HPB0 base address */ +#define HPB1_ADDR _UL_(0x41000000) /**< HPB1 base address */ +#define HPB2_ADDR _UL_(0x42000000) /**< HPB2 base address */ +#define HPB3_ADDR _UL_(0x43000000) /**< HPB3 base address */ +#define SEEPROM_ADDR _UL_(0x44000000) /**< SEEPROM base address */ +#define BKUPRAM_ADDR _UL_(0x47000000) /**< BKUPRAM base address */ +#define PPB_ADDR _UL_(0xE0000000) /**< PPB base address */ + +#define DSU_DID_RESETVALUE _UL_(0x61840303) +#define ADC0_TOUCH_LINES_NUM 32 +#define PORT_GROUPS 3 + +/* ************************************************************************** */ +/** ELECTRICAL DEFINITIONS FOR SAME54N19A */ +/* ************************************************************************** */ + + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* SAME54N19A_H */ diff --git a/arch/arm/SAME54/SAME54A/mcu/inc/same54n20a.h b/arch/arm/SAME54/SAME54A/mcu/inc/same54n20a.h index 2842aba2..4d4e23d6 100644 --- a/arch/arm/SAME54/SAME54A/mcu/inc/same54n20a.h +++ b/arch/arm/SAME54/SAME54A/mcu/inc/same54n20a.h @@ -1,1113 +1,1085 @@ -/** - * \brief Header file for ATSAME54N20A - * - * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries. - * - * Subject to your compliance with these terms, you may use Microchip software and any derivatives - * exclusively with Microchip products. It is your responsibility to comply with third party license - * terms applicable to your use of third party software (including open source software) that may - * accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, - * APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND - * FITNESS FOR A PARTICULAR PURPOSE. - * - * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF - * MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT - * EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - */ - -/* file generated from device description version 2020-03-12T17:26:59Z */ -#ifndef _SAME54N20A_H_ -#define _SAME54N20A_H_ - -// Header version uses Semantic Versioning 2.0.0 (https://semver.org/) -#define HEADER_FORMAT_VERSION "2.0.0" - -#define HEADER_FORMAT_VERSION_MAJOR (2) -#define HEADER_FORMAT_VERSION_MINOR (0) - -/** \addtogroup SAME54N20A_definitions SAME54N20A definitions - This file defines all structures and symbols for SAME54N20A: - - registers and bitfields - - peripheral base address - - peripheral ID - - PIO definitions - * @{ - */ - -#ifdef __cplusplus - extern "C" { -#endif - -#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) -# include -#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#if !defined(SKIP_INTEGER_LITERALS) -# if defined(_U_) || defined(_L_) || defined(_UL_) -# error "Integer Literals macros already defined elsewhere" -# endif - -#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) -/* Macros that deal with adding suffixes to integer literal constants for C/C++ */ -# define _U_(x) (x ## U) /**< C code: Unsigned integer literal constant value */ -# define _L_(x) (x ## L) /**< C code: Long integer literal constant value */ -# define _UL_(x) (x ## UL) /**< C code: Unsigned Long integer literal constant value */ - -#else /* Assembler */ - -# define _U_(x) x /**< Assembler: Unsigned integer literal constant value */ -# define _L_(x) x /**< Assembler: Long integer literal constant value */ -# define _UL_(x) x /**< Assembler: Unsigned Long integer literal constant value */ -#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ -#endif /* SKIP_INTEGER_LITERALS */ -/** @} end of Atmel Global Defines */ - -/* ************************************************************************** */ -/* CMSIS DEFINITIONS FOR SAME54N20A */ -/* ************************************************************************** */ -#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) -/** Interrupt Number Definition */ -typedef enum IRQn -{ -/****** CORTEX-M4 Processor Exceptions Numbers ******************************/ - Reset_IRQn = -15, /**< -15 Reset Vector, invoked on Power up and warm reset */ - NonMaskableInt_IRQn = -14, /**< -14 Non maskable Interrupt, cannot be stopped or preempted */ - HardFault_IRQn = -13, /**< -13 Hard Fault, all classes of Fault */ - MemoryManagement_IRQn = -12, /**< -12 Memory Management, MPU mismatch, including Access Violation and No Match */ - BusFault_IRQn = -11, /**< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */ - UsageFault_IRQn = -10, /**< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ - SVCall_IRQn = -5, /**< -5 System Service Call via SVC instruction */ - DebugMonitor_IRQn = -4, /**< -4 Debug Monitor */ - PendSV_IRQn = -2, /**< -2 Pendable request for system service */ - SysTick_IRQn = -1, /**< -1 System Tick Timer */ -/****** SAME54N20A specific Interrupt Numbers ***********************************/ - PM_IRQn = 0, /**< 0 Power Manager (PM) */ - MCLK_IRQn = 1, /**< 1 Main Clock (MCLK) */ - OSCCTRL_XOSC0_IRQn = 2, /**< 2 Oscillators Control (OSCCTRL) */ - OSCCTRL_XOSC1_IRQn = 3, /**< 3 Oscillators Control (OSCCTRL) */ - OSCCTRL_DFLL_IRQn = 4, /**< 4 Oscillators Control (OSCCTRL) */ - OSCCTRL_DPLL0_IRQn = 5, /**< 5 Oscillators Control (OSCCTRL) */ - OSCCTRL_DPLL1_IRQn = 6, /**< 6 Oscillators Control (OSCCTRL) */ - OSC32KCTRL_IRQn = 7, /**< 7 32kHz Oscillators Control (OSC32KCTRL) */ - SUPC_OTHER_IRQn = 8, /**< 8 Supply Controller (SUPC) */ - SUPC_BODDET_IRQn = 9, /**< 9 Supply Controller (SUPC) */ - WDT_IRQn = 10, /**< 10 Watchdog Timer (WDT) */ - RTC_IRQn = 11, /**< 11 Real-Time Counter (RTC) */ - EIC_EXTINT_0_IRQn = 12, /**< 12 External Interrupt Controller (EIC) */ - EIC_EXTINT_1_IRQn = 13, /**< 13 External Interrupt Controller (EIC) */ - EIC_EXTINT_2_IRQn = 14, /**< 14 External Interrupt Controller (EIC) */ - EIC_EXTINT_3_IRQn = 15, /**< 15 External Interrupt Controller (EIC) */ - EIC_EXTINT_4_IRQn = 16, /**< 16 External Interrupt Controller (EIC) */ - EIC_EXTINT_5_IRQn = 17, /**< 17 External Interrupt Controller (EIC) */ - EIC_EXTINT_6_IRQn = 18, /**< 18 External Interrupt Controller (EIC) */ - EIC_EXTINT_7_IRQn = 19, /**< 19 External Interrupt Controller (EIC) */ - EIC_EXTINT_8_IRQn = 20, /**< 20 External Interrupt Controller (EIC) */ - EIC_EXTINT_9_IRQn = 21, /**< 21 External Interrupt Controller (EIC) */ - EIC_EXTINT_10_IRQn = 22, /**< 22 External Interrupt Controller (EIC) */ - EIC_EXTINT_11_IRQn = 23, /**< 23 External Interrupt Controller (EIC) */ - EIC_EXTINT_12_IRQn = 24, /**< 24 External Interrupt Controller (EIC) */ - EIC_EXTINT_13_IRQn = 25, /**< 25 External Interrupt Controller (EIC) */ - EIC_EXTINT_14_IRQn = 26, /**< 26 External Interrupt Controller (EIC) */ - EIC_EXTINT_15_IRQn = 27, /**< 27 External Interrupt Controller (EIC) */ - FREQM_IRQn = 28, /**< 28 Frequency Meter (FREQM) */ - NVMCTRL_0_IRQn = 29, /**< 29 Non-Volatile Memory Controller (NVMCTRL) */ - NVMCTRL_1_IRQn = 30, /**< 30 Non-Volatile Memory Controller (NVMCTRL) */ - DMAC_0_IRQn = 31, /**< 31 Direct Memory Access Controller (DMAC) */ - DMAC_1_IRQn = 32, /**< 32 Direct Memory Access Controller (DMAC) */ - DMAC_2_IRQn = 33, /**< 33 Direct Memory Access Controller (DMAC) */ - DMAC_3_IRQn = 34, /**< 34 Direct Memory Access Controller (DMAC) */ - DMAC_OTHER_IRQn = 35, /**< 35 Direct Memory Access Controller (DMAC) */ - EVSYS_0_IRQn = 36, /**< 36 Event System Interface (EVSYS) */ - EVSYS_1_IRQn = 37, /**< 37 Event System Interface (EVSYS) */ - EVSYS_2_IRQn = 38, /**< 38 Event System Interface (EVSYS) */ - EVSYS_3_IRQn = 39, /**< 39 Event System Interface (EVSYS) */ - EVSYS_OTHER_IRQn = 40, /**< 40 Event System Interface (EVSYS) */ - PAC_IRQn = 41, /**< 41 Peripheral Access Controller (PAC) */ - RAMECC_IRQn = 45, /**< 45 RAM ECC (RAMECC) */ - SERCOM0_0_IRQn = 46, /**< 46 Serial Communication Interface (SERCOM0) */ - SERCOM0_1_IRQn = 47, /**< 47 Serial Communication Interface (SERCOM0) */ - SERCOM0_2_IRQn = 48, /**< 48 Serial Communication Interface (SERCOM0) */ - SERCOM0_OTHER_IRQn = 49, /**< 49 Serial Communication Interface (SERCOM0) */ - SERCOM1_0_IRQn = 50, /**< 50 Serial Communication Interface (SERCOM1) */ - SERCOM1_1_IRQn = 51, /**< 51 Serial Communication Interface (SERCOM1) */ - SERCOM1_2_IRQn = 52, /**< 52 Serial Communication Interface (SERCOM1) */ - SERCOM1_OTHER_IRQn = 53, /**< 53 Serial Communication Interface (SERCOM1) */ - SERCOM2_0_IRQn = 54, /**< 54 Serial Communication Interface (SERCOM2) */ - SERCOM2_1_IRQn = 55, /**< 55 Serial Communication Interface (SERCOM2) */ - SERCOM2_2_IRQn = 56, /**< 56 Serial Communication Interface (SERCOM2) */ - SERCOM2_OTHER_IRQn = 57, /**< 57 Serial Communication Interface (SERCOM2) */ - SERCOM3_0_IRQn = 58, /**< 58 Serial Communication Interface (SERCOM3) */ - SERCOM3_1_IRQn = 59, /**< 59 Serial Communication Interface (SERCOM3) */ - SERCOM3_2_IRQn = 60, /**< 60 Serial Communication Interface (SERCOM3) */ - SERCOM3_OTHER_IRQn = 61, /**< 61 Serial Communication Interface (SERCOM3) */ - SERCOM4_0_IRQn = 62, /**< 62 Serial Communication Interface (SERCOM4) */ - SERCOM4_1_IRQn = 63, /**< 63 Serial Communication Interface (SERCOM4) */ - SERCOM4_2_IRQn = 64, /**< 64 Serial Communication Interface (SERCOM4) */ - SERCOM4_OTHER_IRQn = 65, /**< 65 Serial Communication Interface (SERCOM4) */ - SERCOM5_0_IRQn = 66, /**< 66 Serial Communication Interface (SERCOM5) */ - SERCOM5_1_IRQn = 67, /**< 67 Serial Communication Interface (SERCOM5) */ - SERCOM5_2_IRQn = 68, /**< 68 Serial Communication Interface (SERCOM5) */ - SERCOM5_OTHER_IRQn = 69, /**< 69 Serial Communication Interface (SERCOM5) */ - SERCOM6_0_IRQn = 70, /**< 70 Serial Communication Interface (SERCOM6) */ - SERCOM6_1_IRQn = 71, /**< 71 Serial Communication Interface (SERCOM6) */ - SERCOM6_2_IRQn = 72, /**< 72 Serial Communication Interface (SERCOM6) */ - SERCOM6_OTHER_IRQn = 73, /**< 73 Serial Communication Interface (SERCOM6) */ - SERCOM7_0_IRQn = 74, /**< 74 Serial Communication Interface (SERCOM7) */ - SERCOM7_1_IRQn = 75, /**< 75 Serial Communication Interface (SERCOM7) */ - SERCOM7_2_IRQn = 76, /**< 76 Serial Communication Interface (SERCOM7) */ - SERCOM7_OTHER_IRQn = 77, /**< 77 Serial Communication Interface (SERCOM7) */ - CAN0_IRQn = 78, /**< 78 Control Area Network (CAN0) */ - CAN1_IRQn = 79, /**< 79 Control Area Network (CAN1) */ - USB_OTHER_IRQn = 80, /**< 80 Universal Serial Bus (USB) */ - USB_SOF_HSOF_IRQn = 81, /**< 81 Universal Serial Bus (USB) */ - USB_TRCPT0_IRQn = 82, /**< 82 Universal Serial Bus (USB) */ - USB_TRCPT1_IRQn = 83, /**< 83 Universal Serial Bus (USB) */ - GMAC_IRQn = 84, /**< 84 Ethernet MAC (GMAC) */ - TCC0_OTHER_IRQn = 85, /**< 85 Timer Counter Control (TCC0) */ - TCC0_MC0_IRQn = 86, /**< 86 Timer Counter Control (TCC0) */ - TCC0_MC1_IRQn = 87, /**< 87 Timer Counter Control (TCC0) */ - TCC0_MC2_IRQn = 88, /**< 88 Timer Counter Control (TCC0) */ - TCC0_MC3_IRQn = 89, /**< 89 Timer Counter Control (TCC0) */ - TCC0_MC4_IRQn = 90, /**< 90 Timer Counter Control (TCC0) */ - TCC0_MC5_IRQn = 91, /**< 91 Timer Counter Control (TCC0) */ - TCC1_OTHER_IRQn = 92, /**< 92 Timer Counter Control (TCC1) */ - TCC1_MC0_IRQn = 93, /**< 93 Timer Counter Control (TCC1) */ - TCC1_MC1_IRQn = 94, /**< 94 Timer Counter Control (TCC1) */ - TCC1_MC2_IRQn = 95, /**< 95 Timer Counter Control (TCC1) */ - TCC1_MC3_IRQn = 96, /**< 96 Timer Counter Control (TCC1) */ - TCC2_OTHER_IRQn = 97, /**< 97 Timer Counter Control (TCC2) */ - TCC2_MC0_IRQn = 98, /**< 98 Timer Counter Control (TCC2) */ - TCC2_MC1_IRQn = 99, /**< 99 Timer Counter Control (TCC2) */ - TCC2_MC2_IRQn = 100, /**< 100 Timer Counter Control (TCC2) */ - TCC3_OTHER_IRQn = 101, /**< 101 Timer Counter Control (TCC3) */ - TCC3_MC0_IRQn = 102, /**< 102 Timer Counter Control (TCC3) */ - TCC3_MC1_IRQn = 103, /**< 103 Timer Counter Control (TCC3) */ - TCC4_OTHER_IRQn = 104, /**< 104 Timer Counter Control (TCC4) */ - TCC4_MC0_IRQn = 105, /**< 105 Timer Counter Control (TCC4) */ - TCC4_MC1_IRQn = 106, /**< 106 Timer Counter Control (TCC4) */ - TC0_IRQn = 107, /**< 107 Basic Timer Counter (TC0) */ - TC1_IRQn = 108, /**< 108 Basic Timer Counter (TC1) */ - TC2_IRQn = 109, /**< 109 Basic Timer Counter (TC2) */ - TC3_IRQn = 110, /**< 110 Basic Timer Counter (TC3) */ - TC4_IRQn = 111, /**< 111 Basic Timer Counter (TC4) */ - TC5_IRQn = 112, /**< 112 Basic Timer Counter (TC5) */ - TC6_IRQn = 113, /**< 113 Basic Timer Counter (TC6) */ - TC7_IRQn = 114, /**< 114 Basic Timer Counter (TC7) */ - PDEC_OTHER_IRQn = 115, /**< 115 Quadrature Decodeur (PDEC) */ - PDEC_MC0_IRQn = 116, /**< 116 Quadrature Decodeur (PDEC) */ - PDEC_MC1_IRQn = 117, /**< 117 Quadrature Decodeur (PDEC) */ - ADC0_OTHER_IRQn = 118, /**< 118 Analog Digital Converter (ADC0) */ - ADC0_RESRDY_IRQn = 119, /**< 119 Analog Digital Converter (ADC0) */ - ADC1_OTHER_IRQn = 120, /**< 120 Analog Digital Converter (ADC1) */ - ADC1_RESRDY_IRQn = 121, /**< 121 Analog Digital Converter (ADC1) */ - AC_IRQn = 122, /**< 122 Analog Comparators (AC) */ - DAC_OTHER_IRQn = 123, /**< 123 Digital-to-Analog Converter (DAC) */ - DAC_EMPTY_0_IRQn = 124, /**< 124 Digital-to-Analog Converter (DAC) */ - DAC_EMPTY_1_IRQn = 125, /**< 125 Digital-to-Analog Converter (DAC) */ - DAC_RESRDY_0_IRQn = 126, /**< 126 Digital-to-Analog Converter (DAC) */ - DAC_RESRDY_1_IRQn = 127, /**< 127 Digital-to-Analog Converter (DAC) */ - I2S_IRQn = 128, /**< 128 Inter-IC Sound Interface (I2S) */ - PCC_IRQn = 129, /**< 129 Parallel Capture Controller (PCC) */ - AES_IRQn = 130, /**< 130 Advanced Encryption Standard (AES) */ - TRNG_IRQn = 131, /**< 131 True Random Generator (TRNG) */ - ICM_IRQn = 132, /**< 132 Integrity Check Monitor (ICM) */ - PUKCC_IRQn = 133, /**< 133 PUblic-Key Cryptography Controller (PUKCC) */ - QSPI_IRQn = 134, /**< 134 Quad SPI interface (QSPI) */ - SDHC0_IRQn = 135, /**< 135 SD/MMC Host Controller (SDHC0) */ - SDHC1_IRQn = 136, /**< 136 SD/MMC Host Controller (SDHC1) */ - - PERIPH_MAX_IRQn = 136 /**< Max peripheral ID */ -} IRQn_Type; -#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) -typedef struct _DeviceVectors -{ - /* Stack pointer */ - void* pvStack; - /* Cortex-M handlers */ - void* pfnReset_Handler; /* -15 Reset Vector, invoked on Power up and warm reset */ - void* pfnNonMaskableInt_Handler; /* -14 Non maskable Interrupt, cannot be stopped or preempted */ - void* pfnHardFault_Handler; /* -13 Hard Fault, all classes of Fault */ - void* pfnMemoryManagement_Handler; /* -12 Memory Management, MPU mismatch, including Access Violation and No Match */ - void* pfnBusFault_Handler; /* -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */ - void* pfnUsageFault_Handler; /* -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ - void* pvReservedC9; - void* pvReservedC8; - void* pvReservedC7; - void* pvReservedC6; - void* pfnSVCall_Handler; /* -5 System Service Call via SVC instruction */ - void* pfnDebugMonitor_Handler; /* -4 Debug Monitor */ - void* pvReservedC3; - void* pfnPendSV_Handler; /* -2 Pendable request for system service */ - void* pfnSysTick_Handler; /* -1 System Tick Timer */ - - /* Peripheral handlers */ - void* pfnPM_Handler; /* 0 Power Manager (PM) */ - void* pfnMCLK_Handler; /* 1 Main Clock (MCLK) */ - void* pfnOSCCTRL_XOSC0_Handler; /* 2 Oscillators Control (OSCCTRL) */ - void* pfnOSCCTRL_XOSC1_Handler; /* 3 Oscillators Control (OSCCTRL) */ - void* pfnOSCCTRL_DFLL_Handler; /* 4 Oscillators Control (OSCCTRL) */ - void* pfnOSCCTRL_DPLL0_Handler; /* 5 Oscillators Control (OSCCTRL) */ - void* pfnOSCCTRL_DPLL1_Handler; /* 6 Oscillators Control (OSCCTRL) */ - void* pfnOSC32KCTRL_Handler; /* 7 32kHz Oscillators Control (OSC32KCTRL) */ - void* pfnSUPC_OTHER_Handler; /* 8 Supply Controller (SUPC) */ - void* pfnSUPC_BODDET_Handler; /* 9 Supply Controller (SUPC) */ - void* pfnWDT_Handler; /* 10 Watchdog Timer (WDT) */ - void* pfnRTC_Handler; /* 11 Real-Time Counter (RTC) */ - void* pfnEIC_EXTINT_0_Handler; /* 12 External Interrupt Controller (EIC) */ - void* pfnEIC_EXTINT_1_Handler; /* 13 External Interrupt Controller (EIC) */ - void* pfnEIC_EXTINT_2_Handler; /* 14 External Interrupt Controller (EIC) */ - void* pfnEIC_EXTINT_3_Handler; /* 15 External Interrupt Controller (EIC) */ - void* pfnEIC_EXTINT_4_Handler; /* 16 External Interrupt Controller (EIC) */ - void* pfnEIC_EXTINT_5_Handler; /* 17 External Interrupt Controller (EIC) */ - void* pfnEIC_EXTINT_6_Handler; /* 18 External Interrupt Controller (EIC) */ - void* pfnEIC_EXTINT_7_Handler; /* 19 External Interrupt Controller (EIC) */ - void* pfnEIC_EXTINT_8_Handler; /* 20 External Interrupt Controller (EIC) */ - void* pfnEIC_EXTINT_9_Handler; /* 21 External Interrupt Controller (EIC) */ - void* pfnEIC_EXTINT_10_Handler; /* 22 External Interrupt Controller (EIC) */ - void* pfnEIC_EXTINT_11_Handler; /* 23 External Interrupt Controller (EIC) */ - void* pfnEIC_EXTINT_12_Handler; /* 24 External Interrupt Controller (EIC) */ - void* pfnEIC_EXTINT_13_Handler; /* 25 External Interrupt Controller (EIC) */ - void* pfnEIC_EXTINT_14_Handler; /* 26 External Interrupt Controller (EIC) */ - void* pfnEIC_EXTINT_15_Handler; /* 27 External Interrupt Controller (EIC) */ - void* pfnFREQM_Handler; /* 28 Frequency Meter (FREQM) */ - void* pfnNVMCTRL_0_Handler; /* 29 Non-Volatile Memory Controller (NVMCTRL) */ - void* pfnNVMCTRL_1_Handler; /* 30 Non-Volatile Memory Controller (NVMCTRL) */ - void* pfnDMAC_0_Handler; /* 31 Direct Memory Access Controller (DMAC) */ - void* pfnDMAC_1_Handler; /* 32 Direct Memory Access Controller (DMAC) */ - void* pfnDMAC_2_Handler; /* 33 Direct Memory Access Controller (DMAC) */ - void* pfnDMAC_3_Handler; /* 34 Direct Memory Access Controller (DMAC) */ - void* pfnDMAC_OTHER_Handler; /* 35 Direct Memory Access Controller (DMAC) */ - void* pfnEVSYS_0_Handler; /* 36 Event System Interface (EVSYS) */ - void* pfnEVSYS_1_Handler; /* 37 Event System Interface (EVSYS) */ - void* pfnEVSYS_2_Handler; /* 38 Event System Interface (EVSYS) */ - void* pfnEVSYS_3_Handler; /* 39 Event System Interface (EVSYS) */ - void* pfnEVSYS_OTHER_Handler; /* 40 Event System Interface (EVSYS) */ - void* pfnPAC_Handler; /* 41 Peripheral Access Controller (PAC) */ - void* pvReserved42; - void* pvReserved43; - void* pvReserved44; - void* pfnRAMECC_Handler; /* 45 RAM ECC (RAMECC) */ - void* pfnSERCOM0_0_Handler; /* 46 Serial Communication Interface (SERCOM0) */ - void* pfnSERCOM0_1_Handler; /* 47 Serial Communication Interface (SERCOM0) */ - void* pfnSERCOM0_2_Handler; /* 48 Serial Communication Interface (SERCOM0) */ - void* pfnSERCOM0_OTHER_Handler; /* 49 Serial Communication Interface (SERCOM0) */ - void* pfnSERCOM1_0_Handler; /* 50 Serial Communication Interface (SERCOM1) */ - void* pfnSERCOM1_1_Handler; /* 51 Serial Communication Interface (SERCOM1) */ - void* pfnSERCOM1_2_Handler; /* 52 Serial Communication Interface (SERCOM1) */ - void* pfnSERCOM1_OTHER_Handler; /* 53 Serial Communication Interface (SERCOM1) */ - void* pfnSERCOM2_0_Handler; /* 54 Serial Communication Interface (SERCOM2) */ - void* pfnSERCOM2_1_Handler; /* 55 Serial Communication Interface (SERCOM2) */ - void* pfnSERCOM2_2_Handler; /* 56 Serial Communication Interface (SERCOM2) */ - void* pfnSERCOM2_OTHER_Handler; /* 57 Serial Communication Interface (SERCOM2) */ - void* pfnSERCOM3_0_Handler; /* 58 Serial Communication Interface (SERCOM3) */ - void* pfnSERCOM3_1_Handler; /* 59 Serial Communication Interface (SERCOM3) */ - void* pfnSERCOM3_2_Handler; /* 60 Serial Communication Interface (SERCOM3) */ - void* pfnSERCOM3_OTHER_Handler; /* 61 Serial Communication Interface (SERCOM3) */ - void* pfnSERCOM4_0_Handler; /* 62 Serial Communication Interface (SERCOM4) */ - void* pfnSERCOM4_1_Handler; /* 63 Serial Communication Interface (SERCOM4) */ - void* pfnSERCOM4_2_Handler; /* 64 Serial Communication Interface (SERCOM4) */ - void* pfnSERCOM4_OTHER_Handler; /* 65 Serial Communication Interface (SERCOM4) */ - void* pfnSERCOM5_0_Handler; /* 66 Serial Communication Interface (SERCOM5) */ - void* pfnSERCOM5_1_Handler; /* 67 Serial Communication Interface (SERCOM5) */ - void* pfnSERCOM5_2_Handler; /* 68 Serial Communication Interface (SERCOM5) */ - void* pfnSERCOM5_OTHER_Handler; /* 69 Serial Communication Interface (SERCOM5) */ - void* pfnSERCOM6_0_Handler; /* 70 Serial Communication Interface (SERCOM6) */ - void* pfnSERCOM6_1_Handler; /* 71 Serial Communication Interface (SERCOM6) */ - void* pfnSERCOM6_2_Handler; /* 72 Serial Communication Interface (SERCOM6) */ - void* pfnSERCOM6_OTHER_Handler; /* 73 Serial Communication Interface (SERCOM6) */ - void* pfnSERCOM7_0_Handler; /* 74 Serial Communication Interface (SERCOM7) */ - void* pfnSERCOM7_1_Handler; /* 75 Serial Communication Interface (SERCOM7) */ - void* pfnSERCOM7_2_Handler; /* 76 Serial Communication Interface (SERCOM7) */ - void* pfnSERCOM7_OTHER_Handler; /* 77 Serial Communication Interface (SERCOM7) */ - void* pfnCAN0_Handler; /* 78 Control Area Network (CAN0) */ - void* pfnCAN1_Handler; /* 79 Control Area Network (CAN1) */ - void* pfnUSB_OTHER_Handler; /* 80 Universal Serial Bus (USB) */ - void* pfnUSB_SOF_HSOF_Handler; /* 81 Universal Serial Bus (USB) */ - void* pfnUSB_TRCPT0_Handler; /* 82 Universal Serial Bus (USB) */ - void* pfnUSB_TRCPT1_Handler; /* 83 Universal Serial Bus (USB) */ - void* pfnGMAC_Handler; /* 84 Ethernet MAC (GMAC) */ - void* pfnTCC0_OTHER_Handler; /* 85 Timer Counter Control (TCC0) */ - void* pfnTCC0_MC0_Handler; /* 86 Timer Counter Control (TCC0) */ - void* pfnTCC0_MC1_Handler; /* 87 Timer Counter Control (TCC0) */ - void* pfnTCC0_MC2_Handler; /* 88 Timer Counter Control (TCC0) */ - void* pfnTCC0_MC3_Handler; /* 89 Timer Counter Control (TCC0) */ - void* pfnTCC0_MC4_Handler; /* 90 Timer Counter Control (TCC0) */ - void* pfnTCC0_MC5_Handler; /* 91 Timer Counter Control (TCC0) */ - void* pfnTCC1_OTHER_Handler; /* 92 Timer Counter Control (TCC1) */ - void* pfnTCC1_MC0_Handler; /* 93 Timer Counter Control (TCC1) */ - void* pfnTCC1_MC1_Handler; /* 94 Timer Counter Control (TCC1) */ - void* pfnTCC1_MC2_Handler; /* 95 Timer Counter Control (TCC1) */ - void* pfnTCC1_MC3_Handler; /* 96 Timer Counter Control (TCC1) */ - void* pfnTCC2_OTHER_Handler; /* 97 Timer Counter Control (TCC2) */ - void* pfnTCC2_MC0_Handler; /* 98 Timer Counter Control (TCC2) */ - void* pfnTCC2_MC1_Handler; /* 99 Timer Counter Control (TCC2) */ - void* pfnTCC2_MC2_Handler; /* 100 Timer Counter Control (TCC2) */ - void* pfnTCC3_OTHER_Handler; /* 101 Timer Counter Control (TCC3) */ - void* pfnTCC3_MC0_Handler; /* 102 Timer Counter Control (TCC3) */ - void* pfnTCC3_MC1_Handler; /* 103 Timer Counter Control (TCC3) */ - void* pfnTCC4_OTHER_Handler; /* 104 Timer Counter Control (TCC4) */ - void* pfnTCC4_MC0_Handler; /* 105 Timer Counter Control (TCC4) */ - void* pfnTCC4_MC1_Handler; /* 106 Timer Counter Control (TCC4) */ - void* pfnTC0_Handler; /* 107 Basic Timer Counter (TC0) */ - void* pfnTC1_Handler; /* 108 Basic Timer Counter (TC1) */ - void* pfnTC2_Handler; /* 109 Basic Timer Counter (TC2) */ - void* pfnTC3_Handler; /* 110 Basic Timer Counter (TC3) */ - void* pfnTC4_Handler; /* 111 Basic Timer Counter (TC4) */ - void* pfnTC5_Handler; /* 112 Basic Timer Counter (TC5) */ - void* pfnTC6_Handler; /* 113 Basic Timer Counter (TC6) */ - void* pfnTC7_Handler; /* 114 Basic Timer Counter (TC7) */ - void* pfnPDEC_OTHER_Handler; /* 115 Quadrature Decodeur (PDEC) */ - void* pfnPDEC_MC0_Handler; /* 116 Quadrature Decodeur (PDEC) */ - void* pfnPDEC_MC1_Handler; /* 117 Quadrature Decodeur (PDEC) */ - void* pfnADC0_OTHER_Handler; /* 118 Analog Digital Converter (ADC0) */ - void* pfnADC0_RESRDY_Handler; /* 119 Analog Digital Converter (ADC0) */ - void* pfnADC1_OTHER_Handler; /* 120 Analog Digital Converter (ADC1) */ - void* pfnADC1_RESRDY_Handler; /* 121 Analog Digital Converter (ADC1) */ - void* pfnAC_Handler; /* 122 Analog Comparators (AC) */ - void* pfnDAC_OTHER_Handler; /* 123 Digital-to-Analog Converter (DAC) */ - void* pfnDAC_EMPTY_0_Handler; /* 124 Digital-to-Analog Converter (DAC) */ - void* pfnDAC_EMPTY_1_Handler; /* 125 Digital-to-Analog Converter (DAC) */ - void* pfnDAC_RESRDY_0_Handler; /* 126 Digital-to-Analog Converter (DAC) */ - void* pfnDAC_RESRDY_1_Handler; /* 127 Digital-to-Analog Converter (DAC) */ - void* pfnI2S_Handler; /* 128 Inter-IC Sound Interface (I2S) */ - void* pfnPCC_Handler; /* 129 Parallel Capture Controller (PCC) */ - void* pfnAES_Handler; /* 130 Advanced Encryption Standard (AES) */ - void* pfnTRNG_Handler; /* 131 True Random Generator (TRNG) */ - void* pfnICM_Handler; /* 132 Integrity Check Monitor (ICM) */ - void* pfnPUKCC_Handler; /* 133 PUblic-Key Cryptography Controller (PUKCC) */ - void* pfnQSPI_Handler; /* 134 Quad SPI interface (QSPI) */ - void* pfnSDHC0_Handler; /* 135 SD/MMC Host Controller (SDHC0) */ - void* pfnSDHC1_Handler; /* 136 SD/MMC Host Controller (SDHC1) */ -} DeviceVectors; - -/* Defines for Deprecated Interrupt and Exceptions handler names */ -#define pfnMemManage_Handler pfnMemoryManagement_Handler /**< \deprecated Backward compatibility for ASF*/ -#define pfnDebugMon_Handler pfnDebugMonitor_Handler /**< \deprecated Backward compatibility for ASF*/ -#define pfnNMI_Handler pfnNonMaskableInt_Handler /**< \deprecated Backward compatibility for ASF*/ -#define pfnSVC_Handler pfnSVCall_Handler /**< \deprecated Backward compatibility for ASF*/ - -#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) -#if !defined DONT_USE_PREDEFINED_CORE_HANDLERS -/* CORTEX-M4 exception handlers */ -void Reset_Handler ( void ); -void NonMaskableInt_Handler ( void ); -void HardFault_Handler ( void ); -void MemoryManagement_Handler ( void ); -void BusFault_Handler ( void ); -void UsageFault_Handler ( void ); -void SVCall_Handler ( void ); -void DebugMonitor_Handler ( void ); -void PendSV_Handler ( void ); -void SysTick_Handler ( void ); -#endif /* DONT_USE_PREDEFINED_CORE_HANDLERS */ - -#if !defined DONT_USE_PREDEFINED_PERIPHERALS_HANDLERS -/* Peripherals interrupt handlers */ -void PM_Handler ( void ); -void MCLK_Handler ( void ); -void OSCCTRL_XOSC0_Handler ( void ); -void OSCCTRL_XOSC1_Handler ( void ); -void OSCCTRL_DFLL_Handler ( void ); -void OSCCTRL_DPLL0_Handler ( void ); -void OSCCTRL_DPLL1_Handler ( void ); -void OSC32KCTRL_Handler ( void ); -void SUPC_OTHER_Handler ( void ); -void SUPC_BODDET_Handler ( void ); -void WDT_Handler ( void ); -void RTC_Handler ( void ); -void EIC_EXTINT_0_Handler ( void ); -void EIC_EXTINT_1_Handler ( void ); -void EIC_EXTINT_2_Handler ( void ); -void EIC_EXTINT_3_Handler ( void ); -void EIC_EXTINT_4_Handler ( void ); -void EIC_EXTINT_5_Handler ( void ); -void EIC_EXTINT_6_Handler ( void ); -void EIC_EXTINT_7_Handler ( void ); -void EIC_EXTINT_8_Handler ( void ); -void EIC_EXTINT_9_Handler ( void ); -void EIC_EXTINT_10_Handler ( void ); -void EIC_EXTINT_11_Handler ( void ); -void EIC_EXTINT_12_Handler ( void ); -void EIC_EXTINT_13_Handler ( void ); -void EIC_EXTINT_14_Handler ( void ); -void EIC_EXTINT_15_Handler ( void ); -void FREQM_Handler ( void ); -void NVMCTRL_0_Handler ( void ); -void NVMCTRL_1_Handler ( void ); -void DMAC_0_Handler ( void ); -void DMAC_1_Handler ( void ); -void DMAC_2_Handler ( void ); -void DMAC_3_Handler ( void ); -void DMAC_OTHER_Handler ( void ); -void EVSYS_0_Handler ( void ); -void EVSYS_1_Handler ( void ); -void EVSYS_2_Handler ( void ); -void EVSYS_3_Handler ( void ); -void EVSYS_OTHER_Handler ( void ); -void PAC_Handler ( void ); -void RAMECC_Handler ( void ); -void SERCOM0_0_Handler ( void ); -void SERCOM0_1_Handler ( void ); -void SERCOM0_2_Handler ( void ); -void SERCOM0_OTHER_Handler ( void ); -void SERCOM1_0_Handler ( void ); -void SERCOM1_1_Handler ( void ); -void SERCOM1_2_Handler ( void ); -void SERCOM1_OTHER_Handler ( void ); -void SERCOM2_0_Handler ( void ); -void SERCOM2_1_Handler ( void ); -void SERCOM2_2_Handler ( void ); -void SERCOM2_OTHER_Handler ( void ); -void SERCOM3_0_Handler ( void ); -void SERCOM3_1_Handler ( void ); -void SERCOM3_2_Handler ( void ); -void SERCOM3_OTHER_Handler ( void ); -void SERCOM4_0_Handler ( void ); -void SERCOM4_1_Handler ( void ); -void SERCOM4_2_Handler ( void ); -void SERCOM4_OTHER_Handler ( void ); -void SERCOM5_0_Handler ( void ); -void SERCOM5_1_Handler ( void ); -void SERCOM5_2_Handler ( void ); -void SERCOM5_OTHER_Handler ( void ); -void SERCOM6_0_Handler ( void ); -void SERCOM6_1_Handler ( void ); -void SERCOM6_2_Handler ( void ); -void SERCOM6_OTHER_Handler ( void ); -void SERCOM7_0_Handler ( void ); -void SERCOM7_1_Handler ( void ); -void SERCOM7_2_Handler ( void ); -void SERCOM7_OTHER_Handler ( void ); -void CAN0_Handler ( void ); -void CAN1_Handler ( void ); -void USB_OTHER_Handler ( void ); -void USB_SOF_HSOF_Handler ( void ); -void USB_TRCPT0_Handler ( void ); -void USB_TRCPT1_Handler ( void ); -void GMAC_Handler ( void ); -void TCC0_OTHER_Handler ( void ); -void TCC0_MC0_Handler ( void ); -void TCC0_MC1_Handler ( void ); -void TCC0_MC2_Handler ( void ); -void TCC0_MC3_Handler ( void ); -void TCC0_MC4_Handler ( void ); -void TCC0_MC5_Handler ( void ); -void TCC1_OTHER_Handler ( void ); -void TCC1_MC0_Handler ( void ); -void TCC1_MC1_Handler ( void ); -void TCC1_MC2_Handler ( void ); -void TCC1_MC3_Handler ( void ); -void TCC2_OTHER_Handler ( void ); -void TCC2_MC0_Handler ( void ); -void TCC2_MC1_Handler ( void ); -void TCC2_MC2_Handler ( void ); -void TCC3_OTHER_Handler ( void ); -void TCC3_MC0_Handler ( void ); -void TCC3_MC1_Handler ( void ); -void TCC4_OTHER_Handler ( void ); -void TCC4_MC0_Handler ( void ); -void TCC4_MC1_Handler ( void ); -void TC0_Handler ( void ); -void TC1_Handler ( void ); -void TC2_Handler ( void ); -void TC3_Handler ( void ); -void TC4_Handler ( void ); -void TC5_Handler ( void ); -void TC6_Handler ( void ); -void TC7_Handler ( void ); -void PDEC_OTHER_Handler ( void ); -void PDEC_MC0_Handler ( void ); -void PDEC_MC1_Handler ( void ); -void ADC0_OTHER_Handler ( void ); -void ADC0_RESRDY_Handler ( void ); -void ADC1_OTHER_Handler ( void ); -void ADC1_RESRDY_Handler ( void ); -void AC_Handler ( void ); -void DAC_OTHER_Handler ( void ); -void DAC_EMPTY_0_Handler ( void ); -void DAC_EMPTY_1_Handler ( void ); -void DAC_RESRDY_0_Handler ( void ); -void DAC_RESRDY_1_Handler ( void ); -void I2S_Handler ( void ); -void PCC_Handler ( void ); -void AES_Handler ( void ); -void TRNG_Handler ( void ); -void ICM_Handler ( void ); -void PUKCC_Handler ( void ); -void QSPI_Handler ( void ); -void SDHC0_Handler ( void ); -void SDHC1_Handler ( void ); -#endif /* DONT_USE_PREDEFINED_PERIPHERALS_HANDLERS */ -/* Defines for Deprecated Interrupt and Exceptions handler names */ -#define MemManage_Handler MemoryManagement_Handler /**< \deprecated Backward compatibility*/ -#define DebugMon_Handler DebugMonitor_Handler /**< \deprecated Backward compatibility*/ -#define NMI_Handler NonMaskableInt_Handler /**< \deprecated Backward compatibility*/ -#define SVC_Handler SVCall_Handler /**< \deprecated Backward compatibility*/ - -#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/* - * \brief Configuration of the CORTEX-M4 Processor and Core Peripherals - */ -#define __CM4_REV 0x0001 /**< Cortex-M4 Core Revision */ -#define __DEBUG_LVL 3 /**< Debug Level */ -#define __FPU_PRESENT 1 /**< FPU present or not */ -#define __MPU_PRESENT 1 /**< MPU present or not */ -#define __NVIC_PRIO_BITS 3 /**< Number of Bits used for Priority Levels */ -#define __TRACE_LVL 2 /**< Trace Level */ -#define __VTOR_PRESENT 1 /**< Vector Table Offset Register present or not */ -#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */ -#define __ARCH_ARM 1 -#define __ARCH_ARM_CORTEX_M 1 -#define __DEVICE_IS_SAM 1 - -/* - * \brief CMSIS includes - */ -#include "core_cm4.h" -#if defined USE_CMSIS_INIT -#include "system_same54.h" -#endif /* USE_CMSIS_INIT */ - -/** \defgroup SAME54N20A_api Peripheral Software API - * @{ - */ - -/* ************************************************************************** */ -/** SOFTWARE PERIPHERAL API DEFINITION FOR SAME54N20A */ -/* ************************************************************************** */ -#include "component/ac.h" -#include "component/adc.h" -#include "component/aes.h" -#include "component/can.h" -#include "component/ccl.h" -#include "component/cmcc.h" -#include "component/dac.h" -#include "component/dmac.h" -#include "component/dsu.h" -#include "component/eic.h" -#include "component/evsys.h" -#include "component/freqm.h" -#include "component/gclk.h" -#include "component/gmac.h" -#include "component/hmatrixb.h" -#include "component/i2s.h" -#include "component/icm.h" -#include "component/mclk.h" -#include "component/nvmctrl.h" -#include "component/osc32kctrl.h" -#include "component/oscctrl.h" -#include "component/pac.h" -#include "component/pcc.h" -#include "component/pdec.h" -#include "component/pm.h" -#include "component/port.h" -#include "component/pukcc.h" -#include "component/qspi.h" -#include "component/ramecc.h" -#include "component/rstc.h" -#include "component/rtc.h" -#include "component/sdhc.h" -#include "component/sercom.h" -#include "component/supc.h" -#include "component/tc.h" -#include "component/tcc.h" -#include "component/trng.h" -#include "component/usb.h" -#include "component/wdt.h" -/** @} end of Peripheral Software API */ - -/** \addtogroup SAME54N20A_id Peripheral Ids Definitions - * @{ - */ - -/* ************************************************************************** */ -/* PERIPHERAL ID DEFINITIONS FOR SAME54N20A */ -/* ************************************************************************** */ -#define ID_PAC ( 0) /**< \brief Peripheral Access Controller (PAC) */ -#define ID_PM ( 1) /**< \brief Power Manager (PM) */ -#define ID_MCLK ( 2) /**< \brief Main Clock (MCLK) */ -#define ID_RSTC ( 3) /**< \brief Reset Controller (RSTC) */ -#define ID_OSCCTRL ( 4) /**< \brief Oscillators Control (OSCCTRL) */ -#define ID_OSC32KCTRL ( 5) /**< \brief 32kHz Oscillators Control (OSC32KCTRL) */ -#define ID_SUPC ( 6) /**< \brief Supply Controller (SUPC) */ -#define ID_GCLK ( 7) /**< \brief Generic Clock Generator (GCLK) */ -#define ID_WDT ( 8) /**< \brief Watchdog Timer (WDT) */ -#define ID_RTC ( 9) /**< \brief Real-Time Counter (RTC) */ -#define ID_EIC ( 10) /**< \brief External Interrupt Controller (EIC) */ -#define ID_FREQM ( 11) /**< \brief Frequency Meter (FREQM) */ -#define ID_SERCOM0 ( 12) /**< \brief Serial Communication Interface (SERCOM0) */ -#define ID_SERCOM1 ( 13) /**< \brief Serial Communication Interface (SERCOM1) */ -#define ID_TC0 ( 14) /**< \brief Basic Timer Counter (TC0) */ -#define ID_TC1 ( 15) /**< \brief Basic Timer Counter (TC1) */ -#define ID_USB ( 32) /**< \brief Universal Serial Bus (USB) */ -#define ID_DSU ( 33) /**< \brief Device Service Unit (DSU) */ -#define ID_NVMCTRL ( 34) /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ -#define ID_CMCC ( 35) /**< \brief Cortex M Cache Controller (CMCC) */ -#define ID_PORT ( 36) /**< \brief Port Module (PORT) */ -#define ID_DMAC ( 37) /**< \brief Direct Memory Access Controller (DMAC) */ -#define ID_HMATRIX ( 38) /**< \brief HSB Matrix (HMATRIX) */ -#define ID_EVSYS ( 39) /**< \brief Event System Interface (EVSYS) */ -#define ID_SERCOM2 ( 41) /**< \brief Serial Communication Interface (SERCOM2) */ -#define ID_SERCOM3 ( 42) /**< \brief Serial Communication Interface (SERCOM3) */ -#define ID_TCC0 ( 43) /**< \brief Timer Counter Control (TCC0) */ -#define ID_TCC1 ( 44) /**< \brief Timer Counter Control (TCC1) */ -#define ID_TC2 ( 45) /**< \brief Basic Timer Counter (TC2) */ -#define ID_TC3 ( 46) /**< \brief Basic Timer Counter (TC3) */ -#define ID_RAMECC ( 48) /**< \brief RAM ECC (RAMECC) */ -#define ID_CAN0 ( 64) /**< \brief Control Area Network (CAN0) */ -#define ID_CAN1 ( 65) /**< \brief Control Area Network (CAN1) */ -#define ID_GMAC ( 66) /**< \brief Ethernet MAC (GMAC) */ -#define ID_TCC2 ( 67) /**< \brief Timer Counter Control (TCC2) */ -#define ID_TCC3 ( 68) /**< \brief Timer Counter Control (TCC3) */ -#define ID_TC4 ( 69) /**< \brief Basic Timer Counter (TC4) */ -#define ID_TC5 ( 70) /**< \brief Basic Timer Counter (TC5) */ -#define ID_PDEC ( 71) /**< \brief Quadrature Decodeur (PDEC) */ -#define ID_AC ( 72) /**< \brief Analog Comparators (AC) */ -#define ID_AES ( 73) /**< \brief Advanced Encryption Standard (AES) */ -#define ID_TRNG ( 74) /**< \brief True Random Generator (TRNG) */ -#define ID_ICM ( 75) /**< \brief Integrity Check Monitor (ICM) */ -#define ID_PUKCC ( 76) /**< \brief PUblic-Key Cryptography Controller (PUKCC) */ -#define ID_QSPI ( 77) /**< \brief Quad SPI interface (QSPI) */ -#define ID_CCL ( 78) /**< \brief Configurable Custom Logic (CCL) */ -#define ID_SERCOM4 ( 96) /**< \brief Serial Communication Interface (SERCOM4) */ -#define ID_SERCOM5 ( 97) /**< \brief Serial Communication Interface (SERCOM5) */ -#define ID_SERCOM6 ( 98) /**< \brief Serial Communication Interface (SERCOM6) */ -#define ID_SERCOM7 ( 99) /**< \brief Serial Communication Interface (SERCOM7) */ -#define ID_TCC4 (100) /**< \brief Timer Counter Control (TCC4) */ -#define ID_TC6 (101) /**< \brief Basic Timer Counter (TC6) */ -#define ID_TC7 (102) /**< \brief Basic Timer Counter (TC7) */ -#define ID_ADC0 (103) /**< \brief Analog Digital Converter (ADC0) */ -#define ID_ADC1 (104) /**< \brief Analog Digital Converter (ADC1) */ -#define ID_DAC (105) /**< \brief Digital-to-Analog Converter (DAC) */ -#define ID_I2S (106) /**< \brief Inter-IC Sound Interface (I2S) */ -#define ID_PCC (107) /**< \brief Parallel Capture Controller (PCC) */ - -#define ID_PERIPH_MAX (107) /**< \brief Number of peripheral IDs */ -/** @} end of Peripheral Ids Definitions */ - -/** \addtogroup SAME54N20A_base Peripheral Base Address Definitions - * @{ - */ - -/* ************************************************************************** */ -/* REGISTER STRUCTURE ADDRESS DEFINITIONS FOR SAME54N20A */ -/* ************************************************************************** */ -#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) -#define AC_REGS ((ac_registers_t*)0x42002000) /**< \brief AC Registers Address */ -#define ADC0_REGS ((adc_registers_t*)0x43001c00) /**< \brief ADC0 Registers Address */ -#define ADC1_REGS ((adc_registers_t*)0x43002000) /**< \brief ADC1 Registers Address */ -#define AES_REGS ((aes_registers_t*)0x42002400) /**< \brief AES Registers Address */ -#define CAN0_REGS ((can_registers_t*)0x42000000) /**< \brief CAN0 Registers Address */ -#define CAN1_REGS ((can_registers_t*)0x42000400) /**< \brief CAN1 Registers Address */ -#define CCL_REGS ((ccl_registers_t*)0x42003800) /**< \brief CCL Registers Address */ -#define CMCC_REGS ((cmcc_registers_t*)0x41006000) /**< \brief CMCC Registers Address */ -#define DAC_REGS ((dac_registers_t*)0x43002400) /**< \brief DAC Registers Address */ -#define DMAC_REGS ((dmac_registers_t*)0x4100a000) /**< \brief DMAC Registers Address */ -#define DSU_REGS ((dsu_registers_t*)0x41002000) /**< \brief DSU Registers Address */ -#define EIC_REGS ((eic_registers_t*)0x40002800) /**< \brief EIC Registers Address */ -#define EVSYS_REGS ((evsys_registers_t*)0x4100e000) /**< \brief EVSYS Registers Address */ -#define FREQM_REGS ((freqm_registers_t*)0x40002c00) /**< \brief FREQM Registers Address */ -#define GCLK_REGS ((gclk_registers_t*)0x40001c00) /**< \brief GCLK Registers Address */ -#define GMAC_REGS ((gmac_registers_t*)0x42000800) /**< \brief GMAC Registers Address */ -#define HMATRIX_REGS ((hmatrixb_registers_t*)0x4100c000) /**< \brief HMATRIX Registers Address */ -#define ICM_REGS ((icm_registers_t*)0x42002c00) /**< \brief ICM Registers Address */ -#define I2S_REGS ((i2s_registers_t*)0x43002800) /**< \brief I2S Registers Address */ -#define MCLK_REGS ((mclk_registers_t*)0x40000800) /**< \brief MCLK Registers Address */ -#define NVMCTRL_REGS ((nvmctrl_registers_t*)0x41004000) /**< \brief NVMCTRL Registers Address */ -#define OSCCTRL_REGS ((oscctrl_registers_t*)0x40001000) /**< \brief OSCCTRL Registers Address */ -#define OSC32KCTRL_REGS ((osc32kctrl_registers_t*)0x40001400) /**< \brief OSC32KCTRL Registers Address */ -#define PAC_REGS ((pac_registers_t*)0x40000000) /**< \brief PAC Registers Address */ -#define PCC_REGS ((pcc_registers_t*)0x43002c00) /**< \brief PCC Registers Address */ -#define PDEC_REGS ((pdec_registers_t*)0x42001c00) /**< \brief PDEC Registers Address */ -#define PM_REGS ((pm_registers_t*)0x40000400) /**< \brief PM Registers Address */ -#define PORT_REGS ((port_registers_t*)0x41008000) /**< \brief PORT Registers Address */ -#define QSPI_REGS ((qspi_registers_t*)0x42003400) /**< \brief QSPI Registers Address */ -#define RAMECC_REGS ((ramecc_registers_t*)0x41020000) /**< \brief RAMECC Registers Address */ -#define RSTC_REGS ((rstc_registers_t*)0x40000c00) /**< \brief RSTC Registers Address */ -#define RTC_REGS ((rtc_registers_t*)0x40002400) /**< \brief RTC Registers Address */ -#define SDHC0_REGS ((sdhc_registers_t*)0x45000000) /**< \brief SDHC0 Registers Address */ -#define SDHC1_REGS ((sdhc_registers_t*)0x46000000) /**< \brief SDHC1 Registers Address */ -#define SERCOM0_REGS ((sercom_registers_t*)0x40003000) /**< \brief SERCOM0 Registers Address */ -#define SERCOM1_REGS ((sercom_registers_t*)0x40003400) /**< \brief SERCOM1 Registers Address */ -#define SERCOM2_REGS ((sercom_registers_t*)0x41012000) /**< \brief SERCOM2 Registers Address */ -#define SERCOM3_REGS ((sercom_registers_t*)0x41014000) /**< \brief SERCOM3 Registers Address */ -#define SERCOM4_REGS ((sercom_registers_t*)0x43000000) /**< \brief SERCOM4 Registers Address */ -#define SERCOM5_REGS ((sercom_registers_t*)0x43000400) /**< \brief SERCOM5 Registers Address */ -#define SERCOM6_REGS ((sercom_registers_t*)0x43000800) /**< \brief SERCOM6 Registers Address */ -#define SERCOM7_REGS ((sercom_registers_t*)0x43000c00) /**< \brief SERCOM7 Registers Address */ -#define SUPC_REGS ((supc_registers_t*)0x40001800) /**< \brief SUPC Registers Address */ -#define TC0_REGS ((tc_registers_t*)0x40003800) /**< \brief TC0 Registers Address */ -#define TC1_REGS ((tc_registers_t*)0x40003c00) /**< \brief TC1 Registers Address */ -#define TC2_REGS ((tc_registers_t*)0x4101a000) /**< \brief TC2 Registers Address */ -#define TC3_REGS ((tc_registers_t*)0x4101c000) /**< \brief TC3 Registers Address */ -#define TC4_REGS ((tc_registers_t*)0x42001400) /**< \brief TC4 Registers Address */ -#define TC5_REGS ((tc_registers_t*)0x42001800) /**< \brief TC5 Registers Address */ -#define TC6_REGS ((tc_registers_t*)0x43001400) /**< \brief TC6 Registers Address */ -#define TC7_REGS ((tc_registers_t*)0x43001800) /**< \brief TC7 Registers Address */ -#define TCC0_REGS ((tcc_registers_t*)0x41016000) /**< \brief TCC0 Registers Address */ -#define TCC1_REGS ((tcc_registers_t*)0x41018000) /**< \brief TCC1 Registers Address */ -#define TCC2_REGS ((tcc_registers_t*)0x42000c00) /**< \brief TCC2 Registers Address */ -#define TCC3_REGS ((tcc_registers_t*)0x42001000) /**< \brief TCC3 Registers Address */ -#define TCC4_REGS ((tcc_registers_t*)0x43001000) /**< \brief TCC4 Registers Address */ -#define TRNG_REGS ((trng_registers_t*)0x42002800) /**< \brief TRNG Registers Address */ -#define USB_REGS ((usb_registers_t*)0x41000000) /**< \brief USB Registers Address */ -#define WDT_REGS ((wdt_registers_t*)0x40002000) /**< \brief WDT Registers Address */ -#endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ -/** @} end of Peripheral Base Address Definitions */ - -/** \addtogroup SAME54N20A_base Peripheral Base Address Definitions - * @{ - */ - -/* ************************************************************************** */ -/* BASE ADDRESS DEFINITIONS FOR SAME54N20A */ -/* ************************************************************************** */ -#define AC_BASE_ADDRESS _UL_(0x42002000) /**< \brief AC Base Address */ -#define ADC0_BASE_ADDRESS _UL_(0x43001c00) /**< \brief ADC0 Base Address */ -#define ADC1_BASE_ADDRESS _UL_(0x43002000) /**< \brief ADC1 Base Address */ -#define AES_BASE_ADDRESS _UL_(0x42002400) /**< \brief AES Base Address */ -#define CAN0_BASE_ADDRESS _UL_(0x42000000) /**< \brief CAN0 Base Address */ -#define CAN1_BASE_ADDRESS _UL_(0x42000400) /**< \brief CAN1 Base Address */ -#define CCL_BASE_ADDRESS _UL_(0x42003800) /**< \brief CCL Base Address */ -#define CMCC_BASE_ADDRESS _UL_(0x41006000) /**< \brief CMCC Base Address */ -#define DAC_BASE_ADDRESS _UL_(0x43002400) /**< \brief DAC Base Address */ -#define DMAC_BASE_ADDRESS _UL_(0x4100a000) /**< \brief DMAC Base Address */ -#define DSU_BASE_ADDRESS _UL_(0x41002000) /**< \brief DSU Base Address */ -#define EIC_BASE_ADDRESS _UL_(0x40002800) /**< \brief EIC Base Address */ -#define EVSYS_BASE_ADDRESS _UL_(0x4100e000) /**< \brief EVSYS Base Address */ -#define FREQM_BASE_ADDRESS _UL_(0x40002c00) /**< \brief FREQM Base Address */ -#define GCLK_BASE_ADDRESS _UL_(0x40001c00) /**< \brief GCLK Base Address */ -#define GMAC_BASE_ADDRESS _UL_(0x42000800) /**< \brief GMAC Base Address */ -#define HMATRIX_BASE_ADDRESS _UL_(0x4100c000) /**< \brief HMATRIX Base Address */ -#define ICM_BASE_ADDRESS _UL_(0x42002c00) /**< \brief ICM Base Address */ -#define I2S_BASE_ADDRESS _UL_(0x43002800) /**< \brief I2S Base Address */ -#define MCLK_BASE_ADDRESS _UL_(0x40000800) /**< \brief MCLK Base Address */ -#define NVMCTRL_BASE_ADDRESS _UL_(0x41004000) /**< \brief NVMCTRL Base Address */ -#define OSCCTRL_BASE_ADDRESS _UL_(0x40001000) /**< \brief OSCCTRL Base Address */ -#define OSC32KCTRL_BASE_ADDRESS _UL_(0x40001400) /**< \brief OSC32KCTRL Base Address */ -#define PAC_BASE_ADDRESS _UL_(0x40000000) /**< \brief PAC Base Address */ -#define PCC_BASE_ADDRESS _UL_(0x43002c00) /**< \brief PCC Base Address */ -#define PDEC_BASE_ADDRESS _UL_(0x42001c00) /**< \brief PDEC Base Address */ -#define PM_BASE_ADDRESS _UL_(0x40000400) /**< \brief PM Base Address */ -#define PORT_BASE_ADDRESS _UL_(0x41008000) /**< \brief PORT Base Address */ -#define QSPI_BASE_ADDRESS _UL_(0x42003400) /**< \brief QSPI Base Address */ -#define RAMECC_BASE_ADDRESS _UL_(0x41020000) /**< \brief RAMECC Base Address */ -#define RSTC_BASE_ADDRESS _UL_(0x40000c00) /**< \brief RSTC Base Address */ -#define RTC_BASE_ADDRESS _UL_(0x40002400) /**< \brief RTC Base Address */ -#define SDHC0_BASE_ADDRESS _UL_(0x45000000) /**< \brief SDHC0 Base Address */ -#define SDHC1_BASE_ADDRESS _UL_(0x46000000) /**< \brief SDHC1 Base Address */ -#define SERCOM0_BASE_ADDRESS _UL_(0x40003000) /**< \brief SERCOM0 Base Address */ -#define SERCOM1_BASE_ADDRESS _UL_(0x40003400) /**< \brief SERCOM1 Base Address */ -#define SERCOM2_BASE_ADDRESS _UL_(0x41012000) /**< \brief SERCOM2 Base Address */ -#define SERCOM3_BASE_ADDRESS _UL_(0x41014000) /**< \brief SERCOM3 Base Address */ -#define SERCOM4_BASE_ADDRESS _UL_(0x43000000) /**< \brief SERCOM4 Base Address */ -#define SERCOM5_BASE_ADDRESS _UL_(0x43000400) /**< \brief SERCOM5 Base Address */ -#define SERCOM6_BASE_ADDRESS _UL_(0x43000800) /**< \brief SERCOM6 Base Address */ -#define SERCOM7_BASE_ADDRESS _UL_(0x43000c00) /**< \brief SERCOM7 Base Address */ -#define SUPC_BASE_ADDRESS _UL_(0x40001800) /**< \brief SUPC Base Address */ -#define TC0_BASE_ADDRESS _UL_(0x40003800) /**< \brief TC0 Base Address */ -#define TC1_BASE_ADDRESS _UL_(0x40003c00) /**< \brief TC1 Base Address */ -#define TC2_BASE_ADDRESS _UL_(0x4101a000) /**< \brief TC2 Base Address */ -#define TC3_BASE_ADDRESS _UL_(0x4101c000) /**< \brief TC3 Base Address */ -#define TC4_BASE_ADDRESS _UL_(0x42001400) /**< \brief TC4 Base Address */ -#define TC5_BASE_ADDRESS _UL_(0x42001800) /**< \brief TC5 Base Address */ -#define TC6_BASE_ADDRESS _UL_(0x43001400) /**< \brief TC6 Base Address */ -#define TC7_BASE_ADDRESS _UL_(0x43001800) /**< \brief TC7 Base Address */ -#define TCC0_BASE_ADDRESS _UL_(0x41016000) /**< \brief TCC0 Base Address */ -#define TCC1_BASE_ADDRESS _UL_(0x41018000) /**< \brief TCC1 Base Address */ -#define TCC2_BASE_ADDRESS _UL_(0x42000c00) /**< \brief TCC2 Base Address */ -#define TCC3_BASE_ADDRESS _UL_(0x42001000) /**< \brief TCC3 Base Address */ -#define TCC4_BASE_ADDRESS _UL_(0x43001000) /**< \brief TCC4 Base Address */ -#define TRNG_BASE_ADDRESS _UL_(0x42002800) /**< \brief TRNG Base Address */ -#define USB_BASE_ADDRESS _UL_(0x41000000) /**< \brief USB Base Address */ -#define WDT_BASE_ADDRESS _UL_(0x40002000) /**< \brief WDT Base Address */ -/** @} end of Peripheral Base Address Definitions */ - -/** \addtogroup SAME54N20A_pio Peripheral Pio Definitions - * @{ - */ - -/* ************************************************************************** */ -/* PIO DEFINITIONS FOR SAME54N20A */ -/* ************************************************************************** */ -#include "pio/same54n20a.h" -/** @} end of Peripheral Pio Definitions */ - -/* ************************************************************************** */ -/* MEMORY MAPPING DEFINITIONS FOR SAME54N20A */ -/* ************************************************************************** */ - -#define FLASH_SIZE _UL_(0x00100000) /* 1024kB Memory segment type: flash */ -#define FLASH_PAGE_SIZE _UL_( 512) -#define FLASH_NB_OF_PAGES _UL_( 2048) - -#define SW0_SIZE _UL_(0x00000010) /* 0kB Memory segment type: fuses */ -#define TEMP_LOG_SIZE _UL_(0x00000200) /* 0kB Memory segment type: fuses */ -#define TEMP_LOG_PAGE_SIZE _UL_( 512) -#define TEMP_LOG_NB_OF_PAGES _UL_( 1) - -#define USER_PAGE_SIZE _UL_(0x00000200) /* 0kB Memory segment type: user_page */ -#define USER_PAGE_PAGE_SIZE _UL_( 512) -#define USER_PAGE_NB_OF_PAGES _UL_( 1) - -#define CMCC_SIZE _UL_(0x01000000) /* 16384kB Memory segment type: io */ -#define CMCC_DATARAM_SIZE _UL_(0x00001000) /* 4kB Memory segment type: io */ -#define CMCC_TAGRAM_SIZE _UL_(0x00000400) /* 1kB Memory segment type: io */ -#define CMCC_VALIDRAM_SIZE _UL_(0x00000040) /* 0kB Memory segment type: io */ -#define QSPI_SIZE _UL_(0x01000000) /* 16384kB Memory segment type: other */ -#define HSRAM_SIZE _UL_(0x00040000) /* 256kB Memory segment type: ram */ -#define HSRAM_ETB_SIZE _UL_(0x00008000) /* 32kB Memory segment type: ram */ -#define HSRAM_RET1_SIZE _UL_(0x00008000) /* 32kB Memory segment type: ram */ -#define HPB0_SIZE _UL_(0x00004400) /* 17kB Memory segment type: io */ -#define HPB1_SIZE _UL_(0x00022000) /* 136kB Memory segment type: io */ -#define HPB2_SIZE _UL_(0x00003c00) /* 15kB Memory segment type: io */ -#define HPB3_SIZE _UL_(0x00003000) /* 12kB Memory segment type: io */ -#define SEEPROM_SIZE _UL_(0x00020000) /* 128kB Memory segment type: io */ -#define SDHC0_SIZE _UL_(0x00000c00) /* 3kB Memory segment type: io */ -#define SDHC1_SIZE _UL_(0x00000c00) /* 3kB Memory segment type: io */ -#define BKUPRAM_SIZE _UL_(0x00002000) /* 8kB Memory segment type: ram */ -#define PPB_SIZE _UL_(0x00100000) /* 1024kB Memory segment type: io */ -#define SCS_SIZE _UL_(0x00001000) /* 4kB Memory segment type: io */ - -#define FLASH_ADDR _UL_(0x00000000) /**< FLASH base address (type: flash)*/ -#define SW0_ADDR _UL_(0x00800080) /**< SW0 base address (type: fuses)*/ -#define TEMP_LOG_ADDR _UL_(0x00800100) /**< TEMP_LOG base address (type: fuses)*/ -#define USER_PAGE_ADDR _UL_(0x00804000) /**< USER_PAGE base address (type: user_page)*/ -#define CMCC_ADDR _UL_(0x03000000) /**< CMCC base address (type: io)*/ -#define CMCC_DATARAM_ADDR _UL_(0x03000000) /**< CMCC_DATARAM base address (type: io)*/ -#define CMCC_TAGRAM_ADDR _UL_(0x03001000) /**< CMCC_TAGRAM base address (type: io)*/ -#define CMCC_VALIDRAM_ADDR _UL_(0x03002000) /**< CMCC_VALIDRAM base address (type: io)*/ -#define QSPI_ADDR _UL_(0x04000000) /**< QSPI base address (type: other)*/ -#define HSRAM_ADDR _UL_(0x20000000) /**< HSRAM base address (type: ram)*/ -#define HSRAM_ETB_ADDR _UL_(0x20000000) /**< HSRAM_ETB base address (type: ram)*/ -#define HSRAM_RET1_ADDR _UL_(0x20000000) /**< HSRAM_RET1 base address (type: ram)*/ -#define HPB0_ADDR _UL_(0x40000000) /**< HPB0 base address (type: io)*/ -#define HPB1_ADDR _UL_(0x41000000) /**< HPB1 base address (type: io)*/ -#define HPB2_ADDR _UL_(0x42000000) /**< HPB2 base address (type: io)*/ -#define HPB3_ADDR _UL_(0x43000000) /**< HPB3 base address (type: io)*/ -#define SEEPROM_ADDR _UL_(0x44000000) /**< SEEPROM base address (type: io)*/ -#define SDHC0_ADDR _UL_(0x45000000) /**< SDHC0 base address (type: io)*/ -#define SDHC1_ADDR _UL_(0x46000000) /**< SDHC1 base address (type: io)*/ -#define BKUPRAM_ADDR _UL_(0x47000000) /**< BKUPRAM base address (type: ram)*/ -#define PPB_ADDR _UL_(0xe0000000) /**< PPB base address (type: io)*/ -#define SCS_ADDR _UL_(0xe000e000) /**< SCS base address (type: io)*/ - -/* ************************************************************************** */ -/** DEVICE SIGNATURES FOR SAME54N20A */ -/* ************************************************************************** */ -#define CHIP_DSU_DID _UL_(0X61840302) - -/* ************************************************************************** */ -/** ELECTRICAL DEFINITIONS FOR SAME54N20A */ -/* ************************************************************************** */ - -/* ************************************************************************** */ -/** Event Generator IDs for SAME54N20A */ -/* ************************************************************************** */ -#define EVENT_ID_GEN_OSCCTRL_XOSC_FAIL_0 1 /**< ID for OSCCTRL event generator XOSC_FAIL_0 */ -#define EVENT_ID_GEN_OSCCTRL_XOSC_FAIL_1 2 /**< ID for OSCCTRL event generator XOSC_FAIL_1 */ -#define EVENT_ID_GEN_OSC32KCTRL_XOSC32K_FAIL 3 /**< ID for OSC32KCTRL event generator XOSC32K_FAIL */ -#define EVENT_ID_GEN_RTC_PER_0 4 /**< ID for RTC event generator PER_0 */ -#define EVENT_ID_GEN_RTC_PER_1 5 /**< ID for RTC event generator PER_1 */ -#define EVENT_ID_GEN_RTC_PER_2 6 /**< ID for RTC event generator PER_2 */ -#define EVENT_ID_GEN_RTC_PER_3 7 /**< ID for RTC event generator PER_3 */ -#define EVENT_ID_GEN_RTC_PER_4 8 /**< ID for RTC event generator PER_4 */ -#define EVENT_ID_GEN_RTC_PER_5 9 /**< ID for RTC event generator PER_5 */ -#define EVENT_ID_GEN_RTC_PER_6 10 /**< ID for RTC event generator PER_6 */ -#define EVENT_ID_GEN_RTC_PER_7 11 /**< ID for RTC event generator PER_7 */ -#define EVENT_ID_GEN_RTC_CMP_0 12 /**< ID for RTC event generator CMP_0 */ -#define EVENT_ID_GEN_RTC_CMP_1 13 /**< ID for RTC event generator CMP_1 */ -#define EVENT_ID_GEN_RTC_CMP_2 14 /**< ID for RTC event generator CMP_2 */ -#define EVENT_ID_GEN_RTC_CMP_3 15 /**< ID for RTC event generator CMP_3 */ -#define EVENT_ID_GEN_RTC_TAMPER 16 /**< ID for RTC event generator TAMPER */ -#define EVENT_ID_GEN_RTC_OVF 17 /**< ID for RTC event generator OVF */ -#define EVENT_ID_GEN_EIC_EXTINT_0 18 /**< ID for EIC event generator EXTINT_0 */ -#define EVENT_ID_GEN_EIC_EXTINT_1 19 /**< ID for EIC event generator EXTINT_1 */ -#define EVENT_ID_GEN_EIC_EXTINT_2 20 /**< ID for EIC event generator EXTINT_2 */ -#define EVENT_ID_GEN_EIC_EXTINT_3 21 /**< ID for EIC event generator EXTINT_3 */ -#define EVENT_ID_GEN_EIC_EXTINT_4 22 /**< ID for EIC event generator EXTINT_4 */ -#define EVENT_ID_GEN_EIC_EXTINT_5 23 /**< ID for EIC event generator EXTINT_5 */ -#define EVENT_ID_GEN_EIC_EXTINT_6 24 /**< ID for EIC event generator EXTINT_6 */ -#define EVENT_ID_GEN_EIC_EXTINT_7 25 /**< ID for EIC event generator EXTINT_7 */ -#define EVENT_ID_GEN_EIC_EXTINT_8 26 /**< ID for EIC event generator EXTINT_8 */ -#define EVENT_ID_GEN_EIC_EXTINT_9 27 /**< ID for EIC event generator EXTINT_9 */ -#define EVENT_ID_GEN_EIC_EXTINT_10 28 /**< ID for EIC event generator EXTINT_10 */ -#define EVENT_ID_GEN_EIC_EXTINT_11 29 /**< ID for EIC event generator EXTINT_11 */ -#define EVENT_ID_GEN_EIC_EXTINT_12 30 /**< ID for EIC event generator EXTINT_12 */ -#define EVENT_ID_GEN_EIC_EXTINT_13 31 /**< ID for EIC event generator EXTINT_13 */ -#define EVENT_ID_GEN_EIC_EXTINT_14 32 /**< ID for EIC event generator EXTINT_14 */ -#define EVENT_ID_GEN_EIC_EXTINT_15 33 /**< ID for EIC event generator EXTINT_15 */ -#define EVENT_ID_GEN_DMAC_CH_0 34 /**< ID for DMAC event generator CH_0 */ -#define EVENT_ID_GEN_DMAC_CH_1 35 /**< ID for DMAC event generator CH_1 */ -#define EVENT_ID_GEN_DMAC_CH_2 36 /**< ID for DMAC event generator CH_2 */ -#define EVENT_ID_GEN_DMAC_CH_3 37 /**< ID for DMAC event generator CH_3 */ -#define EVENT_ID_GEN_PAC_ACCERR 38 /**< ID for PAC event generator ACCERR */ -#define EVENT_ID_GEN_TCC0_OVF 41 /**< ID for TCC0 event generator OVF */ -#define EVENT_ID_GEN_TCC0_TRG 42 /**< ID for TCC0 event generator TRG */ -#define EVENT_ID_GEN_TCC0_CNT 43 /**< ID for TCC0 event generator CNT */ -#define EVENT_ID_GEN_TCC0_MC_0 44 /**< ID for TCC0 event generator MC_0 */ -#define EVENT_ID_GEN_TCC0_MC_1 45 /**< ID for TCC0 event generator MC_1 */ -#define EVENT_ID_GEN_TCC0_MC_2 46 /**< ID for TCC0 event generator MC_2 */ -#define EVENT_ID_GEN_TCC0_MC_3 47 /**< ID for TCC0 event generator MC_3 */ -#define EVENT_ID_GEN_TCC0_MC_4 48 /**< ID for TCC0 event generator MC_4 */ -#define EVENT_ID_GEN_TCC0_MC_5 49 /**< ID for TCC0 event generator MC_5 */ -#define EVENT_ID_GEN_TCC1_OVF 50 /**< ID for TCC1 event generator OVF */ -#define EVENT_ID_GEN_TCC1_TRG 51 /**< ID for TCC1 event generator TRG */ -#define EVENT_ID_GEN_TCC1_CNT 52 /**< ID for TCC1 event generator CNT */ -#define EVENT_ID_GEN_TCC1_MC_0 53 /**< ID for TCC1 event generator MC_0 */ -#define EVENT_ID_GEN_TCC1_MC_1 54 /**< ID for TCC1 event generator MC_1 */ -#define EVENT_ID_GEN_TCC1_MC_2 55 /**< ID for TCC1 event generator MC_2 */ -#define EVENT_ID_GEN_TCC1_MC_3 56 /**< ID for TCC1 event generator MC_3 */ -#define EVENT_ID_GEN_TCC2_OVF 57 /**< ID for TCC2 event generator OVF */ -#define EVENT_ID_GEN_TCC2_TRG 58 /**< ID for TCC2 event generator TRG */ -#define EVENT_ID_GEN_TCC2_CNT 59 /**< ID for TCC2 event generator CNT */ -#define EVENT_ID_GEN_TCC2_MC_0 60 /**< ID for TCC2 event generator MC_0 */ -#define EVENT_ID_GEN_TCC2_MC_1 61 /**< ID for TCC2 event generator MC_1 */ -#define EVENT_ID_GEN_TCC2_MC_2 62 /**< ID for TCC2 event generator MC_2 */ -#define EVENT_ID_GEN_TCC3_OVF 63 /**< ID for TCC3 event generator OVF */ -#define EVENT_ID_GEN_TCC3_TRG 64 /**< ID for TCC3 event generator TRG */ -#define EVENT_ID_GEN_TCC3_CNT 65 /**< ID for TCC3 event generator CNT */ -#define EVENT_ID_GEN_TCC3_MC_0 66 /**< ID for TCC3 event generator MC_0 */ -#define EVENT_ID_GEN_TCC3_MC_1 67 /**< ID for TCC3 event generator MC_1 */ -#define EVENT_ID_GEN_TCC4_OVF 68 /**< ID for TCC4 event generator OVF */ -#define EVENT_ID_GEN_TCC4_TRG 69 /**< ID for TCC4 event generator TRG */ -#define EVENT_ID_GEN_TCC4_CNT 70 /**< ID for TCC4 event generator CNT */ -#define EVENT_ID_GEN_TCC4_MC_0 71 /**< ID for TCC4 event generator MC_0 */ -#define EVENT_ID_GEN_TCC4_MC_1 72 /**< ID for TCC4 event generator MC_1 */ -#define EVENT_ID_GEN_TC0_OVF 73 /**< ID for TC0 event generator OVF */ -#define EVENT_ID_GEN_TC0_MC_0 74 /**< ID for TC0 event generator MC_0 */ -#define EVENT_ID_GEN_TC0_MC_1 75 /**< ID for TC0 event generator MC_1 */ -#define EVENT_ID_GEN_TC1_OVF 76 /**< ID for TC1 event generator OVF */ -#define EVENT_ID_GEN_TC1_MC_0 77 /**< ID for TC1 event generator MC_0 */ -#define EVENT_ID_GEN_TC1_MC_1 78 /**< ID for TC1 event generator MC_1 */ -#define EVENT_ID_GEN_TC2_OVF 79 /**< ID for TC2 event generator OVF */ -#define EVENT_ID_GEN_TC2_MC_0 80 /**< ID for TC2 event generator MC_0 */ -#define EVENT_ID_GEN_TC2_MC_1 81 /**< ID for TC2 event generator MC_1 */ -#define EVENT_ID_GEN_TC3_OVF 82 /**< ID for TC3 event generator OVF */ -#define EVENT_ID_GEN_TC3_MC_0 83 /**< ID for TC3 event generator MC_0 */ -#define EVENT_ID_GEN_TC3_MC_1 84 /**< ID for TC3 event generator MC_1 */ -#define EVENT_ID_GEN_TC4_OVF 85 /**< ID for TC4 event generator OVF */ -#define EVENT_ID_GEN_TC4_MC_0 86 /**< ID for TC4 event generator MC_0 */ -#define EVENT_ID_GEN_TC4_MC_1 87 /**< ID for TC4 event generator MC_1 */ -#define EVENT_ID_GEN_TC5_OVF 88 /**< ID for TC5 event generator OVF */ -#define EVENT_ID_GEN_TC5_MC_0 89 /**< ID for TC5 event generator MC_0 */ -#define EVENT_ID_GEN_TC5_MC_1 90 /**< ID for TC5 event generator MC_1 */ -#define EVENT_ID_GEN_TC6_OVF 91 /**< ID for TC6 event generator OVF */ -#define EVENT_ID_GEN_TC6_MC_0 92 /**< ID for TC6 event generator MC_0 */ -#define EVENT_ID_GEN_TC6_MC_1 93 /**< ID for TC6 event generator MC_1 */ -#define EVENT_ID_GEN_TC7_OVF 94 /**< ID for TC7 event generator OVF */ -#define EVENT_ID_GEN_TC7_MC_0 95 /**< ID for TC7 event generator MC_0 */ -#define EVENT_ID_GEN_TC7_MC_1 96 /**< ID for TC7 event generator MC_1 */ -#define EVENT_ID_GEN_PDEC_OVF 97 /**< ID for PDEC event generator OVF */ -#define EVENT_ID_GEN_PDEC_ERR 98 /**< ID for PDEC event generator ERR */ -#define EVENT_ID_GEN_PDEC_DIR 99 /**< ID for PDEC event generator DIR */ -#define EVENT_ID_GEN_PDEC_VLC 100 /**< ID for PDEC event generator VLC */ -#define EVENT_ID_GEN_PDEC_MC_0 101 /**< ID for PDEC event generator MC_0 */ -#define EVENT_ID_GEN_PDEC_MC_1 102 /**< ID for PDEC event generator MC_1 */ -#define EVENT_ID_GEN_ADC0_RESRDY 103 /**< ID for ADC0 event generator RESRDY */ -#define EVENT_ID_GEN_ADC0_WINMON 104 /**< ID for ADC0 event generator WINMON */ -#define EVENT_ID_GEN_ADC1_RESRDY 105 /**< ID for ADC1 event generator RESRDY */ -#define EVENT_ID_GEN_ADC1_WINMON 106 /**< ID for ADC1 event generator WINMON */ -#define EVENT_ID_GEN_AC_COMP_0 107 /**< ID for AC event generator COMP_0 */ -#define EVENT_ID_GEN_AC_COMP_1 108 /**< ID for AC event generator COMP_1 */ -#define EVENT_ID_GEN_AC_WIN_0 109 /**< ID for AC event generator WIN_0 */ -#define EVENT_ID_GEN_DAC_EMPTY_0 110 /**< ID for DAC event generator EMPTY_0 */ -#define EVENT_ID_GEN_DAC_EMPTY_1 111 /**< ID for DAC event generator EMPTY_1 */ -#define EVENT_ID_GEN_DAC_RESRDY_0 112 /**< ID for DAC event generator RESRDY_0 */ -#define EVENT_ID_GEN_DAC_RESRDY_1 113 /**< ID for DAC event generator RESRDY_1 */ -#define EVENT_ID_GEN_GMAC_TSU_CMP 114 /**< ID for GMAC event generator TSU_CMP */ -#define EVENT_ID_GEN_TRNG_READY 115 /**< ID for TRNG event generator READY */ -#define EVENT_ID_GEN_CCL_LUTOUT_0 116 /**< ID for CCL event generator LUTOUT_0 */ -#define EVENT_ID_GEN_CCL_LUTOUT_1 117 /**< ID for CCL event generator LUTOUT_1 */ -#define EVENT_ID_GEN_CCL_LUTOUT_2 118 /**< ID for CCL event generator LUTOUT_2 */ -#define EVENT_ID_GEN_CCL_LUTOUT_3 119 /**< ID for CCL event generator LUTOUT_3 */ - -/* ************************************************************************** */ -/** Event User IDs for SAME54N20A */ -/* ************************************************************************** */ -#define EVENT_ID_USER_RTC_TAMPER 0 /**< ID for RTC event user TAMPER */ -#define EVENT_ID_USER_PORT_EV_0 1 /**< ID for PORT event user EV_0 */ -#define EVENT_ID_USER_PORT_EV_1 2 /**< ID for PORT event user EV_1 */ -#define EVENT_ID_USER_PORT_EV_2 3 /**< ID for PORT event user EV_2 */ -#define EVENT_ID_USER_PORT_EV_3 4 /**< ID for PORT event user EV_3 */ -#define EVENT_ID_USER_DMAC_CH_0 5 /**< ID for DMAC event user CH_0 */ -#define EVENT_ID_USER_DMAC_CH_1 6 /**< ID for DMAC event user CH_1 */ -#define EVENT_ID_USER_DMAC_CH_2 7 /**< ID for DMAC event user CH_2 */ -#define EVENT_ID_USER_DMAC_CH_3 8 /**< ID for DMAC event user CH_3 */ -#define EVENT_ID_USER_DMAC_CH_4 9 /**< ID for DMAC event user CH_4 */ -#define EVENT_ID_USER_DMAC_CH_5 10 /**< ID for DMAC event user CH_5 */ -#define EVENT_ID_USER_DMAC_CH_6 11 /**< ID for DMAC event user CH_6 */ -#define EVENT_ID_USER_DMAC_CH_7 12 /**< ID for DMAC event user CH_7 */ -#define EVENT_ID_USER_CM4_TRACE_START 14 /**< ID for CM4 event user TRACE_START */ -#define EVENT_ID_USER_CM4_TRACE_STOP 15 /**< ID for CM4 event user TRACE_STOP */ -#define EVENT_ID_USER_CM4_TRACE_TRIG 16 /**< ID for CM4 event user TRACE_TRIG */ -#define EVENT_ID_USER_TCC0_EV_0 17 /**< ID for TCC0 event user EV_0 */ -#define EVENT_ID_USER_TCC0_EV_1 18 /**< ID for TCC0 event user EV_1 */ -#define EVENT_ID_USER_TCC0_MC_0 19 /**< ID for TCC0 event user MC_0 */ -#define EVENT_ID_USER_TCC0_MC_1 20 /**< ID for TCC0 event user MC_1 */ -#define EVENT_ID_USER_TCC0_MC_2 21 /**< ID for TCC0 event user MC_2 */ -#define EVENT_ID_USER_TCC0_MC_3 22 /**< ID for TCC0 event user MC_3 */ -#define EVENT_ID_USER_TCC0_MC_4 23 /**< ID for TCC0 event user MC_4 */ -#define EVENT_ID_USER_TCC0_MC_5 24 /**< ID for TCC0 event user MC_5 */ -#define EVENT_ID_USER_TCC1_EV_0 25 /**< ID for TCC1 event user EV_0 */ -#define EVENT_ID_USER_TCC1_EV_1 26 /**< ID for TCC1 event user EV_1 */ -#define EVENT_ID_USER_TCC1_MC_0 27 /**< ID for TCC1 event user MC_0 */ -#define EVENT_ID_USER_TCC1_MC_1 28 /**< ID for TCC1 event user MC_1 */ -#define EVENT_ID_USER_TCC1_MC_2 29 /**< ID for TCC1 event user MC_2 */ -#define EVENT_ID_USER_TCC1_MC_3 30 /**< ID for TCC1 event user MC_3 */ -#define EVENT_ID_USER_TCC2_EV_0 31 /**< ID for TCC2 event user EV_0 */ -#define EVENT_ID_USER_TCC2_EV_1 32 /**< ID for TCC2 event user EV_1 */ -#define EVENT_ID_USER_TCC2_MC_0 33 /**< ID for TCC2 event user MC_0 */ -#define EVENT_ID_USER_TCC2_MC_1 34 /**< ID for TCC2 event user MC_1 */ -#define EVENT_ID_USER_TCC2_MC_2 35 /**< ID for TCC2 event user MC_2 */ -#define EVENT_ID_USER_TCC3_EV_0 36 /**< ID for TCC3 event user EV_0 */ -#define EVENT_ID_USER_TCC3_EV_1 37 /**< ID for TCC3 event user EV_1 */ -#define EVENT_ID_USER_TCC3_MC_0 38 /**< ID for TCC3 event user MC_0 */ -#define EVENT_ID_USER_TCC3_MC_1 39 /**< ID for TCC3 event user MC_1 */ -#define EVENT_ID_USER_TCC4_EV_0 40 /**< ID for TCC4 event user EV_0 */ -#define EVENT_ID_USER_TCC4_EV_1 41 /**< ID for TCC4 event user EV_1 */ -#define EVENT_ID_USER_TCC4_MC_0 42 /**< ID for TCC4 event user MC_0 */ -#define EVENT_ID_USER_TCC4_MC_1 43 /**< ID for TCC4 event user MC_1 */ -#define EVENT_ID_USER_TC0_EVU 44 /**< ID for TC0 event user EVU */ -#define EVENT_ID_USER_TC1_EVU 45 /**< ID for TC1 event user EVU */ -#define EVENT_ID_USER_TC2_EVU 46 /**< ID for TC2 event user EVU */ -#define EVENT_ID_USER_TC3_EVU 47 /**< ID for TC3 event user EVU */ -#define EVENT_ID_USER_TC4_EVU 48 /**< ID for TC4 event user EVU */ -#define EVENT_ID_USER_TC5_EVU 49 /**< ID for TC5 event user EVU */ -#define EVENT_ID_USER_TC6_EVU 50 /**< ID for TC6 event user EVU */ -#define EVENT_ID_USER_TC7_EVU 51 /**< ID for TC7 event user EVU */ -#define EVENT_ID_USER_PDEC_EVU_0 52 /**< ID for PDEC event user EVU_0 */ -#define EVENT_ID_USER_PDEC_EVU_1 53 /**< ID for PDEC event user EVU_1 */ -#define EVENT_ID_USER_PDEC_EVU_2 54 /**< ID for PDEC event user EVU_2 */ -#define EVENT_ID_USER_ADC0_START 55 /**< ID for ADC0 event user START */ -#define EVENT_ID_USER_ADC0_SYNC 56 /**< ID for ADC0 event user SYNC */ -#define EVENT_ID_USER_ADC1_START 57 /**< ID for ADC1 event user START */ -#define EVENT_ID_USER_ADC1_SYNC 58 /**< ID for ADC1 event user SYNC */ -#define EVENT_ID_USER_AC_SOC_0 59 /**< ID for AC event user SOC_0 */ -#define EVENT_ID_USER_AC_SOC_1 60 /**< ID for AC event user SOC_1 */ -#define EVENT_ID_USER_DAC_START_0 61 /**< ID for DAC event user START_0 */ -#define EVENT_ID_USER_DAC_START_1 62 /**< ID for DAC event user START_1 */ -#define EVENT_ID_USER_CCL_LUTIN_0 63 /**< ID for CCL event user LUTIN_0 */ -#define EVENT_ID_USER_CCL_LUTIN_1 64 /**< ID for CCL event user LUTIN_1 */ -#define EVENT_ID_USER_CCL_LUTIN_2 65 /**< ID for CCL event user LUTIN_2 */ -#define EVENT_ID_USER_CCL_LUTIN_3 66 /**< ID for CCL event user LUTIN_3 */ - -#ifdef __cplusplus -} -#endif - -/** @} end of SAME54N20A definitions */ - - -#endif /* _SAME54N20A_H_ */ - +/** + * \file + * + * \brief Header file for SAME54N20A + * + * Copyright (c) 2019 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAME54N20A_ +#define _SAME54N20A_ + +/** + * \ingroup SAME54_definitions + * \addtogroup SAME54N20A_definitions SAME54N20A definitions + * This file defines all structures and symbols for SAME54N20A: + * - registers and bitfields + * - peripheral base address + * - peripheral ID + * - PIO definitions +*/ +/*@{*/ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#include +#ifndef __cplusplus +typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#else +typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#endif +typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ +typedef volatile uint8_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ +typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ +typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ +#endif + +#if !defined(SKIP_INTEGER_LITERALS) +#if defined(_U_) || defined(_L_) || defined(_UL_) + #error "Integer Literals macros already defined elsewhere" +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/* Macros that deal with adding suffixes to integer literal constants for C/C++ */ +#define _U_(x) x ## U /**< C code: Unsigned integer literal constant value */ +#define _L_(x) x ## L /**< C code: Long integer literal constant value */ +#define _UL_(x) x ## UL /**< C code: Unsigned Long integer literal constant value */ +#else /* Assembler */ +#define _U_(x) x /**< Assembler: Unsigned integer literal constant value */ +#define _L_(x) x /**< Assembler: Long integer literal constant value */ +#define _UL_(x) x /**< Assembler: Unsigned Long integer literal constant value */ +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +#endif /* SKIP_INTEGER_LITERALS */ + +/* ************************************************************************** */ +/** CMSIS DEFINITIONS FOR SAME54N20A */ +/* ************************************************************************** */ +/** \defgroup SAME54N20A_cmsis CMSIS Definitions */ +/*@{*/ + +/** Interrupt Number Definition */ +typedef enum IRQn +{ + /****** Cortex-M4 Processor Exceptions Numbers *******************/ + NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13,/**< 3 Hard Fault Interrupt */ + MemoryManagement_IRQn = -12,/**< 4 Memory Management Interrupt */ + BusFault_IRQn = -11,/**< 5 Bus Fault Interrupt */ + UsageFault_IRQn = -10,/**< 6 Usage Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /**< 12 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /**< 14 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 System Tick Interrupt */ + /****** SAME54N20A-specific Interrupt Numbers *********************/ + PM_IRQn = 0, /**< 0 SAME54N20A Power Manager (PM) */ + MCLK_IRQn = 1, /**< 1 SAME54N20A Main Clock (MCLK) */ + OSCCTRL_0_IRQn = 2, /**< 2 SAME54N20A Oscillators Control (OSCCTRL) IRQ 0 */ + OSCCTRL_1_IRQn = 3, /**< 3 SAME54N20A Oscillators Control (OSCCTRL) IRQ 1 */ + OSCCTRL_2_IRQn = 4, /**< 4 SAME54N20A Oscillators Control (OSCCTRL) IRQ 2 */ + OSCCTRL_3_IRQn = 5, /**< 5 SAME54N20A Oscillators Control (OSCCTRL) IRQ 3 */ + OSCCTRL_4_IRQn = 6, /**< 6 SAME54N20A Oscillators Control (OSCCTRL) IRQ 4 */ + OSC32KCTRL_IRQn = 7, /**< 7 SAME54N20A 32kHz Oscillators Control (OSC32KCTRL) */ + SUPC_0_IRQn = 8, /**< 8 SAME54N20A Supply Controller (SUPC) IRQ 0 */ + SUPC_1_IRQn = 9, /**< 9 SAME54N20A Supply Controller (SUPC) IRQ 1 */ + WDT_IRQn = 10, /**< 10 SAME54N20A Watchdog Timer (WDT) */ + RTC_IRQn = 11, /**< 11 SAME54N20A Real-Time Counter (RTC) */ + EIC_0_IRQn = 12, /**< 12 SAME54N20A External Interrupt Controller (EIC) IRQ 0 */ + EIC_1_IRQn = 13, /**< 13 SAME54N20A External Interrupt Controller (EIC) IRQ 1 */ + EIC_2_IRQn = 14, /**< 14 SAME54N20A External Interrupt Controller (EIC) IRQ 2 */ + EIC_3_IRQn = 15, /**< 15 SAME54N20A External Interrupt Controller (EIC) IRQ 3 */ + EIC_4_IRQn = 16, /**< 16 SAME54N20A External Interrupt Controller (EIC) IRQ 4 */ + EIC_5_IRQn = 17, /**< 17 SAME54N20A External Interrupt Controller (EIC) IRQ 5 */ + EIC_6_IRQn = 18, /**< 18 SAME54N20A External Interrupt Controller (EIC) IRQ 6 */ + EIC_7_IRQn = 19, /**< 19 SAME54N20A External Interrupt Controller (EIC) IRQ 7 */ + EIC_8_IRQn = 20, /**< 20 SAME54N20A External Interrupt Controller (EIC) IRQ 8 */ + EIC_9_IRQn = 21, /**< 21 SAME54N20A External Interrupt Controller (EIC) IRQ 9 */ + EIC_10_IRQn = 22, /**< 22 SAME54N20A External Interrupt Controller (EIC) IRQ 10 */ + EIC_11_IRQn = 23, /**< 23 SAME54N20A External Interrupt Controller (EIC) IRQ 11 */ + EIC_12_IRQn = 24, /**< 24 SAME54N20A External Interrupt Controller (EIC) IRQ 12 */ + EIC_13_IRQn = 25, /**< 25 SAME54N20A External Interrupt Controller (EIC) IRQ 13 */ + EIC_14_IRQn = 26, /**< 26 SAME54N20A External Interrupt Controller (EIC) IRQ 14 */ + EIC_15_IRQn = 27, /**< 27 SAME54N20A External Interrupt Controller (EIC) IRQ 15 */ + FREQM_IRQn = 28, /**< 28 SAME54N20A Frequency Meter (FREQM) */ + NVMCTRL_0_IRQn = 29, /**< 29 SAME54N20A Non-Volatile Memory Controller (NVMCTRL) IRQ 0 */ + NVMCTRL_1_IRQn = 30, /**< 30 SAME54N20A Non-Volatile Memory Controller (NVMCTRL) IRQ 1 */ + DMAC_0_IRQn = 31, /**< 31 SAME54N20A Direct Memory Access Controller (DMAC) IRQ 0 */ + DMAC_1_IRQn = 32, /**< 32 SAME54N20A Direct Memory Access Controller (DMAC) IRQ 1 */ + DMAC_2_IRQn = 33, /**< 33 SAME54N20A Direct Memory Access Controller (DMAC) IRQ 2 */ + DMAC_3_IRQn = 34, /**< 34 SAME54N20A Direct Memory Access Controller (DMAC) IRQ 3 */ + DMAC_4_IRQn = 35, /**< 35 SAME54N20A Direct Memory Access Controller (DMAC) IRQ 4 */ + EVSYS_0_IRQn = 36, /**< 36 SAME54N20A Event System Interface (EVSYS) IRQ 0 */ + EVSYS_1_IRQn = 37, /**< 37 SAME54N20A Event System Interface (EVSYS) IRQ 1 */ + EVSYS_2_IRQn = 38, /**< 38 SAME54N20A Event System Interface (EVSYS) IRQ 2 */ + EVSYS_3_IRQn = 39, /**< 39 SAME54N20A Event System Interface (EVSYS) IRQ 3 */ + EVSYS_4_IRQn = 40, /**< 40 SAME54N20A Event System Interface (EVSYS) IRQ 4 */ + PAC_IRQn = 41, /**< 41 SAME54N20A Peripheral Access Controller (PAC) */ + RAMECC_IRQn = 45, /**< 45 SAME54N20A RAM ECC (RAMECC) */ + SERCOM0_0_IRQn = 46, /**< 46 SAME54N20A Serial Communication Interface 0 (SERCOM0) IRQ 0 */ + SERCOM0_1_IRQn = 47, /**< 47 SAME54N20A Serial Communication Interface 0 (SERCOM0) IRQ 1 */ + SERCOM0_2_IRQn = 48, /**< 48 SAME54N20A Serial Communication Interface 0 (SERCOM0) IRQ 2 */ + SERCOM0_3_IRQn = 49, /**< 49 SAME54N20A Serial Communication Interface 0 (SERCOM0) IRQ 3 */ + SERCOM1_0_IRQn = 50, /**< 50 SAME54N20A Serial Communication Interface 1 (SERCOM1) IRQ 0 */ + SERCOM1_1_IRQn = 51, /**< 51 SAME54N20A Serial Communication Interface 1 (SERCOM1) IRQ 1 */ + SERCOM1_2_IRQn = 52, /**< 52 SAME54N20A Serial Communication Interface 1 (SERCOM1) IRQ 2 */ + SERCOM1_3_IRQn = 53, /**< 53 SAME54N20A Serial Communication Interface 1 (SERCOM1) IRQ 3 */ + SERCOM2_0_IRQn = 54, /**< 54 SAME54N20A Serial Communication Interface 2 (SERCOM2) IRQ 0 */ + SERCOM2_1_IRQn = 55, /**< 55 SAME54N20A Serial Communication Interface 2 (SERCOM2) IRQ 1 */ + SERCOM2_2_IRQn = 56, /**< 56 SAME54N20A Serial Communication Interface 2 (SERCOM2) IRQ 2 */ + SERCOM2_3_IRQn = 57, /**< 57 SAME54N20A Serial Communication Interface 2 (SERCOM2) IRQ 3 */ + SERCOM3_0_IRQn = 58, /**< 58 SAME54N20A Serial Communication Interface 3 (SERCOM3) IRQ 0 */ + SERCOM3_1_IRQn = 59, /**< 59 SAME54N20A Serial Communication Interface 3 (SERCOM3) IRQ 1 */ + SERCOM3_2_IRQn = 60, /**< 60 SAME54N20A Serial Communication Interface 3 (SERCOM3) IRQ 2 */ + SERCOM3_3_IRQn = 61, /**< 61 SAME54N20A Serial Communication Interface 3 (SERCOM3) IRQ 3 */ + SERCOM4_0_IRQn = 62, /**< 62 SAME54N20A Serial Communication Interface 4 (SERCOM4) IRQ 0 */ + SERCOM4_1_IRQn = 63, /**< 63 SAME54N20A Serial Communication Interface 4 (SERCOM4) IRQ 1 */ + SERCOM4_2_IRQn = 64, /**< 64 SAME54N20A Serial Communication Interface 4 (SERCOM4) IRQ 2 */ + SERCOM4_3_IRQn = 65, /**< 65 SAME54N20A Serial Communication Interface 4 (SERCOM4) IRQ 3 */ + SERCOM5_0_IRQn = 66, /**< 66 SAME54N20A Serial Communication Interface 5 (SERCOM5) IRQ 0 */ + SERCOM5_1_IRQn = 67, /**< 67 SAME54N20A Serial Communication Interface 5 (SERCOM5) IRQ 1 */ + SERCOM5_2_IRQn = 68, /**< 68 SAME54N20A Serial Communication Interface 5 (SERCOM5) IRQ 2 */ + SERCOM5_3_IRQn = 69, /**< 69 SAME54N20A Serial Communication Interface 5 (SERCOM5) IRQ 3 */ + SERCOM6_0_IRQn = 70, /**< 70 SAME54N20A Serial Communication Interface 6 (SERCOM6) IRQ 0 */ + SERCOM6_1_IRQn = 71, /**< 71 SAME54N20A Serial Communication Interface 6 (SERCOM6) IRQ 1 */ + SERCOM6_2_IRQn = 72, /**< 72 SAME54N20A Serial Communication Interface 6 (SERCOM6) IRQ 2 */ + SERCOM6_3_IRQn = 73, /**< 73 SAME54N20A Serial Communication Interface 6 (SERCOM6) IRQ 3 */ + SERCOM7_0_IRQn = 74, /**< 74 SAME54N20A Serial Communication Interface 7 (SERCOM7) IRQ 0 */ + SERCOM7_1_IRQn = 75, /**< 75 SAME54N20A Serial Communication Interface 7 (SERCOM7) IRQ 1 */ + SERCOM7_2_IRQn = 76, /**< 76 SAME54N20A Serial Communication Interface 7 (SERCOM7) IRQ 2 */ + SERCOM7_3_IRQn = 77, /**< 77 SAME54N20A Serial Communication Interface 7 (SERCOM7) IRQ 3 */ + CAN0_IRQn = 78, /**< 78 SAME54N20A Control Area Network 0 (CAN0) */ + CAN1_IRQn = 79, /**< 79 SAME54N20A Control Area Network 1 (CAN1) */ + USB_0_IRQn = 80, /**< 80 SAME54N20A Universal Serial Bus (USB) IRQ 0 */ + USB_1_IRQn = 81, /**< 81 SAME54N20A Universal Serial Bus (USB) IRQ 1 */ + USB_2_IRQn = 82, /**< 82 SAME54N20A Universal Serial Bus (USB) IRQ 2 */ + USB_3_IRQn = 83, /**< 83 SAME54N20A Universal Serial Bus (USB) IRQ 3 */ + GMAC_IRQn = 84, /**< 84 SAME54N20A Ethernet MAC (GMAC) */ + TCC0_0_IRQn = 85, /**< 85 SAME54N20A Timer Counter Control 0 (TCC0) IRQ 0 */ + TCC0_1_IRQn = 86, /**< 86 SAME54N20A Timer Counter Control 0 (TCC0) IRQ 1 */ + TCC0_2_IRQn = 87, /**< 87 SAME54N20A Timer Counter Control 0 (TCC0) IRQ 2 */ + TCC0_3_IRQn = 88, /**< 88 SAME54N20A Timer Counter Control 0 (TCC0) IRQ 3 */ + TCC0_4_IRQn = 89, /**< 89 SAME54N20A Timer Counter Control 0 (TCC0) IRQ 4 */ + TCC0_5_IRQn = 90, /**< 90 SAME54N20A Timer Counter Control 0 (TCC0) IRQ 5 */ + TCC0_6_IRQn = 91, /**< 91 SAME54N20A Timer Counter Control 0 (TCC0) IRQ 6 */ + TCC1_0_IRQn = 92, /**< 92 SAME54N20A Timer Counter Control 1 (TCC1) IRQ 0 */ + TCC1_1_IRQn = 93, /**< 93 SAME54N20A Timer Counter Control 1 (TCC1) IRQ 1 */ + TCC1_2_IRQn = 94, /**< 94 SAME54N20A Timer Counter Control 1 (TCC1) IRQ 2 */ + TCC1_3_IRQn = 95, /**< 95 SAME54N20A Timer Counter Control 1 (TCC1) IRQ 3 */ + TCC1_4_IRQn = 96, /**< 96 SAME54N20A Timer Counter Control 1 (TCC1) IRQ 4 */ + TCC2_0_IRQn = 97, /**< 97 SAME54N20A Timer Counter Control 2 (TCC2) IRQ 0 */ + TCC2_1_IRQn = 98, /**< 98 SAME54N20A Timer Counter Control 2 (TCC2) IRQ 1 */ + TCC2_2_IRQn = 99, /**< 99 SAME54N20A Timer Counter Control 2 (TCC2) IRQ 2 */ + TCC2_3_IRQn = 100, /**< 100 SAME54N20A Timer Counter Control 2 (TCC2) IRQ 3 */ + TCC3_0_IRQn = 101, /**< 101 SAME54N20A Timer Counter Control 3 (TCC3) IRQ 0 */ + TCC3_1_IRQn = 102, /**< 102 SAME54N20A Timer Counter Control 3 (TCC3) IRQ 1 */ + TCC3_2_IRQn = 103, /**< 103 SAME54N20A Timer Counter Control 3 (TCC3) IRQ 2 */ + TCC4_0_IRQn = 104, /**< 104 SAME54N20A Timer Counter Control 4 (TCC4) IRQ 0 */ + TCC4_1_IRQn = 105, /**< 105 SAME54N20A Timer Counter Control 4 (TCC4) IRQ 1 */ + TCC4_2_IRQn = 106, /**< 106 SAME54N20A Timer Counter Control 4 (TCC4) IRQ 2 */ + TC0_IRQn = 107, /**< 107 SAME54N20A Basic Timer Counter 0 (TC0) */ + TC1_IRQn = 108, /**< 108 SAME54N20A Basic Timer Counter 1 (TC1) */ + TC2_IRQn = 109, /**< 109 SAME54N20A Basic Timer Counter 2 (TC2) */ + TC3_IRQn = 110, /**< 110 SAME54N20A Basic Timer Counter 3 (TC3) */ + TC4_IRQn = 111, /**< 111 SAME54N20A Basic Timer Counter 4 (TC4) */ + TC5_IRQn = 112, /**< 112 SAME54N20A Basic Timer Counter 5 (TC5) */ + TC6_IRQn = 113, /**< 113 SAME54N20A Basic Timer Counter 6 (TC6) */ + TC7_IRQn = 114, /**< 114 SAME54N20A Basic Timer Counter 7 (TC7) */ + PDEC_0_IRQn = 115, /**< 115 SAME54N20A Quadrature Decodeur (PDEC) IRQ 0 */ + PDEC_1_IRQn = 116, /**< 116 SAME54N20A Quadrature Decodeur (PDEC) IRQ 1 */ + PDEC_2_IRQn = 117, /**< 117 SAME54N20A Quadrature Decodeur (PDEC) IRQ 2 */ + ADC0_0_IRQn = 118, /**< 118 SAME54N20A Analog Digital Converter 0 (ADC0) IRQ 0 */ + ADC0_1_IRQn = 119, /**< 119 SAME54N20A Analog Digital Converter 0 (ADC0) IRQ 1 */ + ADC1_0_IRQn = 120, /**< 120 SAME54N20A Analog Digital Converter 1 (ADC1) IRQ 0 */ + ADC1_1_IRQn = 121, /**< 121 SAME54N20A Analog Digital Converter 1 (ADC1) IRQ 1 */ + AC_IRQn = 122, /**< 122 SAME54N20A Analog Comparators (AC) */ + DAC_0_IRQn = 123, /**< 123 SAME54N20A Digital-to-Analog Converter (DAC) IRQ 0 */ + DAC_1_IRQn = 124, /**< 124 SAME54N20A Digital-to-Analog Converter (DAC) IRQ 1 */ + DAC_2_IRQn = 125, /**< 125 SAME54N20A Digital-to-Analog Converter (DAC) IRQ 2 */ + DAC_3_IRQn = 126, /**< 126 SAME54N20A Digital-to-Analog Converter (DAC) IRQ 3 */ + DAC_4_IRQn = 127, /**< 127 SAME54N20A Digital-to-Analog Converter (DAC) IRQ 4 */ + I2S_IRQn = 128, /**< 128 SAME54N20A Inter-IC Sound Interface (I2S) */ + PCC_IRQn = 129, /**< 129 SAME54N20A Parallel Capture Controller (PCC) */ + AES_IRQn = 130, /**< 130 SAME54N20A Advanced Encryption Standard (AES) */ + TRNG_IRQn = 131, /**< 131 SAME54N20A True Random Generator (TRNG) */ + ICM_IRQn = 132, /**< 132 SAME54N20A Integrity Check Monitor (ICM) */ + PUKCC_IRQn = 133, /**< 133 SAME54N20A PUblic-Key Cryptography Controller (PUKCC) */ + QSPI_IRQn = 134, /**< 134 SAME54N20A Quad SPI interface (QSPI) */ + SDHC0_IRQn = 135, /**< 135 SAME54N20A SD/MMC Host Controller 0 (SDHC0) */ + SDHC1_IRQn = 136, /**< 136 SAME54N20A SD/MMC Host Controller 1 (SDHC1) */ + + PERIPH_COUNT_IRQn = 137 /**< Number of peripheral IDs */ +} IRQn_Type; + +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNonMaskableInt_Handler; + void* pfnHardFault_Handler; + void* pfnMemManagement_Handler; + void* pfnBusFault_Handler; + void* pfnUsageFault_Handler; + void* pvReservedM9; + void* pvReservedM8; + void* pvReservedM7; + void* pvReservedM6; + void* pfnSVCall_Handler; + void* pfnDebugMonitor_Handler; + void* pvReservedM3; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; + + /* Peripheral handlers */ + void* pfnPM_Handler; /* 0 Power Manager */ + void* pfnMCLK_Handler; /* 1 Main Clock */ + void* pfnOSCCTRL_0_Handler; /* 2 Oscillators Control IRQ 0 */ + void* pfnOSCCTRL_1_Handler; /* 3 Oscillators Control IRQ 1 */ + void* pfnOSCCTRL_2_Handler; /* 4 Oscillators Control IRQ 2 */ + void* pfnOSCCTRL_3_Handler; /* 5 Oscillators Control IRQ 3 */ + void* pfnOSCCTRL_4_Handler; /* 6 Oscillators Control IRQ 4 */ + void* pfnOSC32KCTRL_Handler; /* 7 32kHz Oscillators Control */ + void* pfnSUPC_0_Handler; /* 8 Supply Controller IRQ 0 */ + void* pfnSUPC_1_Handler; /* 9 Supply Controller IRQ 1 */ + void* pfnWDT_Handler; /* 10 Watchdog Timer */ + void* pfnRTC_Handler; /* 11 Real-Time Counter */ + void* pfnEIC_0_Handler; /* 12 External Interrupt Controller IRQ 0 */ + void* pfnEIC_1_Handler; /* 13 External Interrupt Controller IRQ 1 */ + void* pfnEIC_2_Handler; /* 14 External Interrupt Controller IRQ 2 */ + void* pfnEIC_3_Handler; /* 15 External Interrupt Controller IRQ 3 */ + void* pfnEIC_4_Handler; /* 16 External Interrupt Controller IRQ 4 */ + void* pfnEIC_5_Handler; /* 17 External Interrupt Controller IRQ 5 */ + void* pfnEIC_6_Handler; /* 18 External Interrupt Controller IRQ 6 */ + void* pfnEIC_7_Handler; /* 19 External Interrupt Controller IRQ 7 */ + void* pfnEIC_8_Handler; /* 20 External Interrupt Controller IRQ 8 */ + void* pfnEIC_9_Handler; /* 21 External Interrupt Controller IRQ 9 */ + void* pfnEIC_10_Handler; /* 22 External Interrupt Controller IRQ 10 */ + void* pfnEIC_11_Handler; /* 23 External Interrupt Controller IRQ 11 */ + void* pfnEIC_12_Handler; /* 24 External Interrupt Controller IRQ 12 */ + void* pfnEIC_13_Handler; /* 25 External Interrupt Controller IRQ 13 */ + void* pfnEIC_14_Handler; /* 26 External Interrupt Controller IRQ 14 */ + void* pfnEIC_15_Handler; /* 27 External Interrupt Controller IRQ 15 */ + void* pfnFREQM_Handler; /* 28 Frequency Meter */ + void* pfnNVMCTRL_0_Handler; /* 29 Non-Volatile Memory Controller IRQ 0 */ + void* pfnNVMCTRL_1_Handler; /* 30 Non-Volatile Memory Controller IRQ 1 */ + void* pfnDMAC_0_Handler; /* 31 Direct Memory Access Controller IRQ 0 */ + void* pfnDMAC_1_Handler; /* 32 Direct Memory Access Controller IRQ 1 */ + void* pfnDMAC_2_Handler; /* 33 Direct Memory Access Controller IRQ 2 */ + void* pfnDMAC_3_Handler; /* 34 Direct Memory Access Controller IRQ 3 */ + void* pfnDMAC_4_Handler; /* 35 Direct Memory Access Controller IRQ 4 */ + void* pfnEVSYS_0_Handler; /* 36 Event System Interface IRQ 0 */ + void* pfnEVSYS_1_Handler; /* 37 Event System Interface IRQ 1 */ + void* pfnEVSYS_2_Handler; /* 38 Event System Interface IRQ 2 */ + void* pfnEVSYS_3_Handler; /* 39 Event System Interface IRQ 3 */ + void* pfnEVSYS_4_Handler; /* 40 Event System Interface IRQ 4 */ + void* pfnPAC_Handler; /* 41 Peripheral Access Controller */ + void* pvReserved42; + void* pvReserved43; + void* pvReserved44; + void* pfnRAMECC_Handler; /* 45 RAM ECC */ + void* pfnSERCOM0_0_Handler; /* 46 Serial Communication Interface 0 IRQ 0 */ + void* pfnSERCOM0_1_Handler; /* 47 Serial Communication Interface 0 IRQ 1 */ + void* pfnSERCOM0_2_Handler; /* 48 Serial Communication Interface 0 IRQ 2 */ + void* pfnSERCOM0_3_Handler; /* 49 Serial Communication Interface 0 IRQ 3 */ + void* pfnSERCOM1_0_Handler; /* 50 Serial Communication Interface 1 IRQ 0 */ + void* pfnSERCOM1_1_Handler; /* 51 Serial Communication Interface 1 IRQ 1 */ + void* pfnSERCOM1_2_Handler; /* 52 Serial Communication Interface 1 IRQ 2 */ + void* pfnSERCOM1_3_Handler; /* 53 Serial Communication Interface 1 IRQ 3 */ + void* pfnSERCOM2_0_Handler; /* 54 Serial Communication Interface 2 IRQ 0 */ + void* pfnSERCOM2_1_Handler; /* 55 Serial Communication Interface 2 IRQ 1 */ + void* pfnSERCOM2_2_Handler; /* 56 Serial Communication Interface 2 IRQ 2 */ + void* pfnSERCOM2_3_Handler; /* 57 Serial Communication Interface 2 IRQ 3 */ + void* pfnSERCOM3_0_Handler; /* 58 Serial Communication Interface 3 IRQ 0 */ + void* pfnSERCOM3_1_Handler; /* 59 Serial Communication Interface 3 IRQ 1 */ + void* pfnSERCOM3_2_Handler; /* 60 Serial Communication Interface 3 IRQ 2 */ + void* pfnSERCOM3_3_Handler; /* 61 Serial Communication Interface 3 IRQ 3 */ + void* pfnSERCOM4_0_Handler; /* 62 Serial Communication Interface 4 IRQ 0 */ + void* pfnSERCOM4_1_Handler; /* 63 Serial Communication Interface 4 IRQ 1 */ + void* pfnSERCOM4_2_Handler; /* 64 Serial Communication Interface 4 IRQ 2 */ + void* pfnSERCOM4_3_Handler; /* 65 Serial Communication Interface 4 IRQ 3 */ + void* pfnSERCOM5_0_Handler; /* 66 Serial Communication Interface 5 IRQ 0 */ + void* pfnSERCOM5_1_Handler; /* 67 Serial Communication Interface 5 IRQ 1 */ + void* pfnSERCOM5_2_Handler; /* 68 Serial Communication Interface 5 IRQ 2 */ + void* pfnSERCOM5_3_Handler; /* 69 Serial Communication Interface 5 IRQ 3 */ + void* pfnSERCOM6_0_Handler; /* 70 Serial Communication Interface 6 IRQ 0 */ + void* pfnSERCOM6_1_Handler; /* 71 Serial Communication Interface 6 IRQ 1 */ + void* pfnSERCOM6_2_Handler; /* 72 Serial Communication Interface 6 IRQ 2 */ + void* pfnSERCOM6_3_Handler; /* 73 Serial Communication Interface 6 IRQ 3 */ + void* pfnSERCOM7_0_Handler; /* 74 Serial Communication Interface 7 IRQ 0 */ + void* pfnSERCOM7_1_Handler; /* 75 Serial Communication Interface 7 IRQ 1 */ + void* pfnSERCOM7_2_Handler; /* 76 Serial Communication Interface 7 IRQ 2 */ + void* pfnSERCOM7_3_Handler; /* 77 Serial Communication Interface 7 IRQ 3 */ + void* pfnCAN0_Handler; /* 78 Control Area Network 0 */ + void* pfnCAN1_Handler; /* 79 Control Area Network 1 */ + void* pfnUSB_0_Handler; /* 80 Universal Serial Bus IRQ 0 */ + void* pfnUSB_1_Handler; /* 81 Universal Serial Bus IRQ 1 */ + void* pfnUSB_2_Handler; /* 82 Universal Serial Bus IRQ 2 */ + void* pfnUSB_3_Handler; /* 83 Universal Serial Bus IRQ 3 */ + void* pfnGMAC_Handler; /* 84 Ethernet MAC */ + void* pfnTCC0_0_Handler; /* 85 Timer Counter Control 0 IRQ 0 */ + void* pfnTCC0_1_Handler; /* 86 Timer Counter Control 0 IRQ 1 */ + void* pfnTCC0_2_Handler; /* 87 Timer Counter Control 0 IRQ 2 */ + void* pfnTCC0_3_Handler; /* 88 Timer Counter Control 0 IRQ 3 */ + void* pfnTCC0_4_Handler; /* 89 Timer Counter Control 0 IRQ 4 */ + void* pfnTCC0_5_Handler; /* 90 Timer Counter Control 0 IRQ 5 */ + void* pfnTCC0_6_Handler; /* 91 Timer Counter Control 0 IRQ 6 */ + void* pfnTCC1_0_Handler; /* 92 Timer Counter Control 1 IRQ 0 */ + void* pfnTCC1_1_Handler; /* 93 Timer Counter Control 1 IRQ 1 */ + void* pfnTCC1_2_Handler; /* 94 Timer Counter Control 1 IRQ 2 */ + void* pfnTCC1_3_Handler; /* 95 Timer Counter Control 1 IRQ 3 */ + void* pfnTCC1_4_Handler; /* 96 Timer Counter Control 1 IRQ 4 */ + void* pfnTCC2_0_Handler; /* 97 Timer Counter Control 2 IRQ 0 */ + void* pfnTCC2_1_Handler; /* 98 Timer Counter Control 2 IRQ 1 */ + void* pfnTCC2_2_Handler; /* 99 Timer Counter Control 2 IRQ 2 */ + void* pfnTCC2_3_Handler; /* 100 Timer Counter Control 2 IRQ 3 */ + void* pfnTCC3_0_Handler; /* 101 Timer Counter Control 3 IRQ 0 */ + void* pfnTCC3_1_Handler; /* 102 Timer Counter Control 3 IRQ 1 */ + void* pfnTCC3_2_Handler; /* 103 Timer Counter Control 3 IRQ 2 */ + void* pfnTCC4_0_Handler; /* 104 Timer Counter Control 4 IRQ 0 */ + void* pfnTCC4_1_Handler; /* 105 Timer Counter Control 4 IRQ 1 */ + void* pfnTCC4_2_Handler; /* 106 Timer Counter Control 4 IRQ 2 */ + void* pfnTC0_Handler; /* 107 Basic Timer Counter 0 */ + void* pfnTC1_Handler; /* 108 Basic Timer Counter 1 */ + void* pfnTC2_Handler; /* 109 Basic Timer Counter 2 */ + void* pfnTC3_Handler; /* 110 Basic Timer Counter 3 */ + void* pfnTC4_Handler; /* 111 Basic Timer Counter 4 */ + void* pfnTC5_Handler; /* 112 Basic Timer Counter 5 */ + void* pfnTC6_Handler; /* 113 Basic Timer Counter 6 */ + void* pfnTC7_Handler; /* 114 Basic Timer Counter 7 */ + void* pfnPDEC_0_Handler; /* 115 Quadrature Decodeur IRQ 0 */ + void* pfnPDEC_1_Handler; /* 116 Quadrature Decodeur IRQ 1 */ + void* pfnPDEC_2_Handler; /* 117 Quadrature Decodeur IRQ 2 */ + void* pfnADC0_0_Handler; /* 118 Analog Digital Converter 0 IRQ 0 */ + void* pfnADC0_1_Handler; /* 119 Analog Digital Converter 0 IRQ 1 */ + void* pfnADC1_0_Handler; /* 120 Analog Digital Converter 1 IRQ 0 */ + void* pfnADC1_1_Handler; /* 121 Analog Digital Converter 1 IRQ 1 */ + void* pfnAC_Handler; /* 122 Analog Comparators */ + void* pfnDAC_0_Handler; /* 123 Digital-to-Analog Converter IRQ 0 */ + void* pfnDAC_1_Handler; /* 124 Digital-to-Analog Converter IRQ 1 */ + void* pfnDAC_2_Handler; /* 125 Digital-to-Analog Converter IRQ 2 */ + void* pfnDAC_3_Handler; /* 126 Digital-to-Analog Converter IRQ 3 */ + void* pfnDAC_4_Handler; /* 127 Digital-to-Analog Converter IRQ 4 */ + void* pfnI2S_Handler; /* 128 Inter-IC Sound Interface */ + void* pfnPCC_Handler; /* 129 Parallel Capture Controller */ + void* pfnAES_Handler; /* 130 Advanced Encryption Standard */ + void* pfnTRNG_Handler; /* 131 True Random Generator */ + void* pfnICM_Handler; /* 132 Integrity Check Monitor */ + void* pfnPUKCC_Handler; /* 133 PUblic-Key Cryptography Controller */ + void* pfnQSPI_Handler; /* 134 Quad SPI interface */ + void* pfnSDHC0_Handler; /* 135 SD/MMC Host Controller 0 */ + void* pfnSDHC1_Handler; /* 136 SD/MMC Host Controller 1 */ +} DeviceVectors; + +/* Cortex-M4 processor handlers */ +void Reset_Handler ( void ); +void NonMaskableInt_Handler ( void ); +void HardFault_Handler ( void ); +void MemManagement_Handler ( void ); +void BusFault_Handler ( void ); +void UsageFault_Handler ( void ); +void SVCall_Handler ( void ); +void DebugMonitor_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); + +/* Peripherals handlers */ +void PM_Handler ( void ); +void MCLK_Handler ( void ); +void OSCCTRL_0_Handler ( void ); +void OSCCTRL_1_Handler ( void ); +void OSCCTRL_2_Handler ( void ); +void OSCCTRL_3_Handler ( void ); +void OSCCTRL_4_Handler ( void ); +void OSC32KCTRL_Handler ( void ); +void SUPC_0_Handler ( void ); +void SUPC_1_Handler ( void ); +void WDT_Handler ( void ); +void RTC_Handler ( void ); +void EIC_0_Handler ( void ); +void EIC_1_Handler ( void ); +void EIC_2_Handler ( void ); +void EIC_3_Handler ( void ); +void EIC_4_Handler ( void ); +void EIC_5_Handler ( void ); +void EIC_6_Handler ( void ); +void EIC_7_Handler ( void ); +void EIC_8_Handler ( void ); +void EIC_9_Handler ( void ); +void EIC_10_Handler ( void ); +void EIC_11_Handler ( void ); +void EIC_12_Handler ( void ); +void EIC_13_Handler ( void ); +void EIC_14_Handler ( void ); +void EIC_15_Handler ( void ); +void FREQM_Handler ( void ); +void NVMCTRL_0_Handler ( void ); +void NVMCTRL_1_Handler ( void ); +void DMAC_0_Handler ( void ); +void DMAC_1_Handler ( void ); +void DMAC_2_Handler ( void ); +void DMAC_3_Handler ( void ); +void DMAC_4_Handler ( void ); +void EVSYS_0_Handler ( void ); +void EVSYS_1_Handler ( void ); +void EVSYS_2_Handler ( void ); +void EVSYS_3_Handler ( void ); +void EVSYS_4_Handler ( void ); +void PAC_Handler ( void ); +void RAMECC_Handler ( void ); +void SERCOM0_0_Handler ( void ); +void SERCOM0_1_Handler ( void ); +void SERCOM0_2_Handler ( void ); +void SERCOM0_3_Handler ( void ); +void SERCOM1_0_Handler ( void ); +void SERCOM1_1_Handler ( void ); +void SERCOM1_2_Handler ( void ); +void SERCOM1_3_Handler ( void ); +void SERCOM2_0_Handler ( void ); +void SERCOM2_1_Handler ( void ); +void SERCOM2_2_Handler ( void ); +void SERCOM2_3_Handler ( void ); +void SERCOM3_0_Handler ( void ); +void SERCOM3_1_Handler ( void ); +void SERCOM3_2_Handler ( void ); +void SERCOM3_3_Handler ( void ); +void SERCOM4_0_Handler ( void ); +void SERCOM4_1_Handler ( void ); +void SERCOM4_2_Handler ( void ); +void SERCOM4_3_Handler ( void ); +void SERCOM5_0_Handler ( void ); +void SERCOM5_1_Handler ( void ); +void SERCOM5_2_Handler ( void ); +void SERCOM5_3_Handler ( void ); +void SERCOM6_0_Handler ( void ); +void SERCOM6_1_Handler ( void ); +void SERCOM6_2_Handler ( void ); +void SERCOM6_3_Handler ( void ); +void SERCOM7_0_Handler ( void ); +void SERCOM7_1_Handler ( void ); +void SERCOM7_2_Handler ( void ); +void SERCOM7_3_Handler ( void ); +void CAN0_Handler ( void ); +void CAN1_Handler ( void ); +void USB_0_Handler ( void ); +void USB_1_Handler ( void ); +void USB_2_Handler ( void ); +void USB_3_Handler ( void ); +void GMAC_Handler ( void ); +void TCC0_0_Handler ( void ); +void TCC0_1_Handler ( void ); +void TCC0_2_Handler ( void ); +void TCC0_3_Handler ( void ); +void TCC0_4_Handler ( void ); +void TCC0_5_Handler ( void ); +void TCC0_6_Handler ( void ); +void TCC1_0_Handler ( void ); +void TCC1_1_Handler ( void ); +void TCC1_2_Handler ( void ); +void TCC1_3_Handler ( void ); +void TCC1_4_Handler ( void ); +void TCC2_0_Handler ( void ); +void TCC2_1_Handler ( void ); +void TCC2_2_Handler ( void ); +void TCC2_3_Handler ( void ); +void TCC3_0_Handler ( void ); +void TCC3_1_Handler ( void ); +void TCC3_2_Handler ( void ); +void TCC4_0_Handler ( void ); +void TCC4_1_Handler ( void ); +void TCC4_2_Handler ( void ); +void TC0_Handler ( void ); +void TC1_Handler ( void ); +void TC2_Handler ( void ); +void TC3_Handler ( void ); +void TC4_Handler ( void ); +void TC5_Handler ( void ); +void TC6_Handler ( void ); +void TC7_Handler ( void ); +void PDEC_0_Handler ( void ); +void PDEC_1_Handler ( void ); +void PDEC_2_Handler ( void ); +void ADC0_0_Handler ( void ); +void ADC0_1_Handler ( void ); +void ADC1_0_Handler ( void ); +void ADC1_1_Handler ( void ); +void AC_Handler ( void ); +void DAC_0_Handler ( void ); +void DAC_1_Handler ( void ); +void DAC_2_Handler ( void ); +void DAC_3_Handler ( void ); +void DAC_4_Handler ( void ); +void I2S_Handler ( void ); +void PCC_Handler ( void ); +void AES_Handler ( void ); +void TRNG_Handler ( void ); +void ICM_Handler ( void ); +void PUKCC_Handler ( void ); +void QSPI_Handler ( void ); +void SDHC0_Handler ( void ); +void SDHC1_Handler ( void ); + +/* + * \brief Configuration of the Cortex-M4 Processor and Core Peripherals + */ + +#define __CM4_REV 1 /*!< Core revision r0p1 */ +#define __DEBUG_LVL 3 /*!< Full debug plus DWT data matching */ +#define __FPU_PRESENT 1 /*!< FPU present or not */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ +#define __NVIC_PRIO_BITS 3 /*!< Number of bits used for Priority Levels */ +#define __TRACE_LVL 2 /*!< Full trace: ITM, DWT triggers and counters, ETM */ +#define __VTOR_PRESENT 1 /*!< VTOR present or not */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + +/** + * \brief CMSIS includes + */ + +#include +#if !defined DONT_USE_CMSIS_INIT +#include "system_same54.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/*@}*/ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAME54N20A */ +/* ************************************************************************** */ +/** \defgroup SAME54N20A_api Peripheral Software API */ +/*@{*/ + +#include "component/ac.h" +#include "component/adc.h" +#include "component/aes.h" +#include "component/can.h" +#include "component/ccl.h" +#include "component/cmcc.h" +#include "component/dac.h" +#include "component/dmac.h" +#include "component/dsu.h" +#include "component/eic.h" +#include "component/evsys.h" +#include "component/freqm.h" +#include "component/gclk.h" +#include "component/gmac.h" +#include "component/hmatrixb.h" +#include "component/icm.h" +#include "component/i2s.h" +#include "component/mclk.h" +#include "component/nvmctrl.h" +#include "component/oscctrl.h" +#include "component/osc32kctrl.h" +#include "component/pac.h" +#include "component/pcc.h" +#include "component/pdec.h" +#include "component/pm.h" +#include "component/port.h" +#include "component/qspi.h" +#include "component/ramecc.h" +#include "component/rstc.h" +#include "component/rtc.h" +#include "component/sdhc.h" +#include "component/sercom.h" +#include "component/supc.h" +#include "component/tc.h" +#include "component/tcc.h" +#include "component/trng.h" +#include "component/usb.h" +#include "component/wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/** REGISTERS ACCESS DEFINITIONS FOR SAME54N20A */ +/* ************************************************************************** */ +/** \defgroup SAME54N20A_reg Registers Access Definitions */ +/*@{*/ + +#include "instance/ac.h" +#include "instance/adc0.h" +#include "instance/adc1.h" +#include "instance/aes.h" +#include "instance/can0.h" +#include "instance/can1.h" +#include "instance/ccl.h" +#include "instance/cmcc.h" +#include "instance/dac.h" +#include "instance/dmac.h" +#include "instance/dsu.h" +#include "instance/eic.h" +#include "instance/evsys.h" +#include "instance/freqm.h" +#include "instance/gclk.h" +#include "instance/gmac.h" +#include "instance/hmatrix.h" +#include "instance/icm.h" +#include "instance/i2s.h" +#include "instance/mclk.h" +#include "instance/nvmctrl.h" +#include "instance/oscctrl.h" +#include "instance/osc32kctrl.h" +#include "instance/pac.h" +#include "instance/pcc.h" +#include "instance/pdec.h" +#include "instance/pm.h" +#include "instance/port.h" +#include "instance/pukcc.h" +#include "instance/qspi.h" +#include "instance/ramecc.h" +#include "instance/rstc.h" +#include "instance/rtc.h" +#include "instance/sdhc0.h" +#include "instance/sdhc1.h" +#include "instance/sercom0.h" +#include "instance/sercom1.h" +#include "instance/sercom2.h" +#include "instance/sercom3.h" +#include "instance/sercom4.h" +#include "instance/sercom5.h" +#include "instance/sercom6.h" +#include "instance/sercom7.h" +#include "instance/supc.h" +#include "instance/tc0.h" +#include "instance/tc1.h" +#include "instance/tc2.h" +#include "instance/tc3.h" +#include "instance/tc4.h" +#include "instance/tc5.h" +#include "instance/tc6.h" +#include "instance/tc7.h" +#include "instance/tcc0.h" +#include "instance/tcc1.h" +#include "instance/tcc2.h" +#include "instance/tcc3.h" +#include "instance/tcc4.h" +#include "instance/trng.h" +#include "instance/usb.h" +#include "instance/wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/** PERIPHERAL ID DEFINITIONS FOR SAME54N20A */ +/* ************************************************************************** */ +/** \defgroup SAME54N20A_id Peripheral Ids Definitions */ +/*@{*/ + +// Peripheral instances on HPB0 bridge +#define ID_PAC 0 /**< \brief Peripheral Access Controller (PAC) */ +#define ID_PM 1 /**< \brief Power Manager (PM) */ +#define ID_MCLK 2 /**< \brief Main Clock (MCLK) */ +#define ID_RSTC 3 /**< \brief Reset Controller (RSTC) */ +#define ID_OSCCTRL 4 /**< \brief Oscillators Control (OSCCTRL) */ +#define ID_OSC32KCTRL 5 /**< \brief 32kHz Oscillators Control (OSC32KCTRL) */ +#define ID_SUPC 6 /**< \brief Supply Controller (SUPC) */ +#define ID_GCLK 7 /**< \brief Generic Clock Generator (GCLK) */ +#define ID_WDT 8 /**< \brief Watchdog Timer (WDT) */ +#define ID_RTC 9 /**< \brief Real-Time Counter (RTC) */ +#define ID_EIC 10 /**< \brief External Interrupt Controller (EIC) */ +#define ID_FREQM 11 /**< \brief Frequency Meter (FREQM) */ +#define ID_SERCOM0 12 /**< \brief Serial Communication Interface 0 (SERCOM0) */ +#define ID_SERCOM1 13 /**< \brief Serial Communication Interface 1 (SERCOM1) */ +#define ID_TC0 14 /**< \brief Basic Timer Counter 0 (TC0) */ +#define ID_TC1 15 /**< \brief Basic Timer Counter 1 (TC1) */ + +// Peripheral instances on HPB1 bridge +#define ID_USB 32 /**< \brief Universal Serial Bus (USB) */ +#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ +#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ +#define ID_CMCC 35 /**< \brief Cortex M Cache Controller (CMCC) */ +#define ID_PORT 36 /**< \brief Port Module (PORT) */ +#define ID_DMAC 37 /**< \brief Direct Memory Access Controller (DMAC) */ +#define ID_HMATRIX 38 /**< \brief HSB Matrix (HMATRIX) */ +#define ID_EVSYS 39 /**< \brief Event System Interface (EVSYS) */ +#define ID_SERCOM2 41 /**< \brief Serial Communication Interface 2 (SERCOM2) */ +#define ID_SERCOM3 42 /**< \brief Serial Communication Interface 3 (SERCOM3) */ +#define ID_TCC0 43 /**< \brief Timer Counter Control 0 (TCC0) */ +#define ID_TCC1 44 /**< \brief Timer Counter Control 1 (TCC1) */ +#define ID_TC2 45 /**< \brief Basic Timer Counter 2 (TC2) */ +#define ID_TC3 46 /**< \brief Basic Timer Counter 3 (TC3) */ +#define ID_RAMECC 48 /**< \brief RAM ECC (RAMECC) */ + +// Peripheral instances on HPB2 bridge +#define ID_CAN0 64 /**< \brief Control Area Network 0 (CAN0) */ +#define ID_CAN1 65 /**< \brief Control Area Network 1 (CAN1) */ +#define ID_GMAC 66 /**< \brief Ethernet MAC (GMAC) */ +#define ID_TCC2 67 /**< \brief Timer Counter Control 2 (TCC2) */ +#define ID_TCC3 68 /**< \brief Timer Counter Control 3 (TCC3) */ +#define ID_TC4 69 /**< \brief Basic Timer Counter 4 (TC4) */ +#define ID_TC5 70 /**< \brief Basic Timer Counter 5 (TC5) */ +#define ID_PDEC 71 /**< \brief Quadrature Decodeur (PDEC) */ +#define ID_AC 72 /**< \brief Analog Comparators (AC) */ +#define ID_AES 73 /**< \brief Advanced Encryption Standard (AES) */ +#define ID_TRNG 74 /**< \brief True Random Generator (TRNG) */ +#define ID_ICM 75 /**< \brief Integrity Check Monitor (ICM) */ +#define ID_PUKCC 76 /**< \brief PUblic-Key Cryptography Controller (PUKCC) */ +#define ID_QSPI 77 /**< \brief Quad SPI interface (QSPI) */ +#define ID_CCL 78 /**< \brief Configurable Custom Logic (CCL) */ + +// Peripheral instances on HPB3 bridge +#define ID_SERCOM4 96 /**< \brief Serial Communication Interface 4 (SERCOM4) */ +#define ID_SERCOM5 97 /**< \brief Serial Communication Interface 5 (SERCOM5) */ +#define ID_SERCOM6 98 /**< \brief Serial Communication Interface 6 (SERCOM6) */ +#define ID_SERCOM7 99 /**< \brief Serial Communication Interface 7 (SERCOM7) */ +#define ID_TCC4 100 /**< \brief Timer Counter Control 4 (TCC4) */ +#define ID_TC6 101 /**< \brief Basic Timer Counter 6 (TC6) */ +#define ID_TC7 102 /**< \brief Basic Timer Counter 7 (TC7) */ +#define ID_ADC0 103 /**< \brief Analog Digital Converter 0 (ADC0) */ +#define ID_ADC1 104 /**< \brief Analog Digital Converter 1 (ADC1) */ +#define ID_DAC 105 /**< \brief Digital-to-Analog Converter (DAC) */ +#define ID_I2S 106 /**< \brief Inter-IC Sound Interface (I2S) */ +#define ID_PCC 107 /**< \brief Parallel Capture Controller (PCC) */ + +// Peripheral instances on AHB (as if on bridge 4) +#define ID_SDHC0 128 /**< \brief SD/MMC Host Controller (SDHC0) */ +#define ID_SDHC1 129 /**< \brief SD/MMC Host Controller (SDHC1) */ + +#define ID_PERIPH_COUNT 130 /**< \brief Max number of peripheral IDs */ +/*@}*/ + +/* ************************************************************************** */ +/** BASE ADDRESS DEFINITIONS FOR SAME54N20A */ +/* ************************************************************************** */ +/** \defgroup SAME54N20A_base Peripheral Base Address Definitions */ +/*@{*/ + +#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) +#define AC (0x42002000) /**< \brief (AC) APB Base Address */ +#define ADC0 (0x43001C00) /**< \brief (ADC0) APB Base Address */ +#define ADC1 (0x43002000) /**< \brief (ADC1) APB Base Address */ +#define AES (0x42002400) /**< \brief (AES) APB Base Address */ +#define CAN0 (0x42000000) /**< \brief (CAN0) APB Base Address */ +#define CAN1 (0x42000400) /**< \brief (CAN1) APB Base Address */ +#define CCL (0x42003800) /**< \brief (CCL) APB Base Address */ +#define CMCC (0x41006000) /**< \brief (CMCC) APB Base Address */ +#define CMCC_AHB (0x03000000) /**< \brief (CMCC) AHB Base Address */ +#define DAC (0x43002400) /**< \brief (DAC) APB Base Address */ +#define DMAC (0x4100A000) /**< \brief (DMAC) APB Base Address */ +#define DSU (0x41002000) /**< \brief (DSU) APB Base Address */ +#define EIC (0x40002800) /**< \brief (EIC) APB Base Address */ +#define EVSYS (0x4100E000) /**< \brief (EVSYS) APB Base Address */ +#define FREQM (0x40002C00) /**< \brief (FREQM) APB Base Address */ +#define GCLK (0x40001C00) /**< \brief (GCLK) APB Base Address */ +#define GMAC (0x42000800) /**< \brief (GMAC) APB Base Address */ +#define HMATRIX (0x4100C000) /**< \brief (HMATRIX) APB Base Address */ +#define ICM (0x42002C00) /**< \brief (ICM) APB Base Address */ +#define I2S (0x43002800) /**< \brief (I2S) APB Base Address */ +#define MCLK (0x40000800) /**< \brief (MCLK) APB Base Address */ +#define NVMCTRL (0x41004000) /**< \brief (NVMCTRL) APB Base Address */ +#define NVMCTRL_SW0 (0x00800080) /**< \brief (NVMCTRL) SW0 Base Address */ +#define NVMCTRL_TEMP_LOG (0x00800100) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ +#define NVMCTRL_USER (0x00804000) /**< \brief (NVMCTRL) USER Base Address */ +#define OSCCTRL (0x40001000) /**< \brief (OSCCTRL) APB Base Address */ +#define OSC32KCTRL (0x40001400) /**< \brief (OSC32KCTRL) APB Base Address */ +#define PAC (0x40000000) /**< \brief (PAC) APB Base Address */ +#define PCC (0x43002C00) /**< \brief (PCC) APB Base Address */ +#define PDEC (0x42001C00) /**< \brief (PDEC) APB Base Address */ +#define PM (0x40000400) /**< \brief (PM) APB Base Address */ +#define PORT (0x41008000) /**< \brief (PORT) APB Base Address */ +#define PUKCC (0x42003000) /**< \brief (PUKCC) APB Base Address */ +#define PUKCC_AHB (0x02000000) /**< \brief (PUKCC) AHB Base Address */ +#define QSPI (0x42003400) /**< \brief (QSPI) APB Base Address */ +#define QSPI_AHB (0x04000000) /**< \brief (QSPI) AHB Base Address */ +#define RAMECC (0x41020000) /**< \brief (RAMECC) APB Base Address */ +#define RSTC (0x40000C00) /**< \brief (RSTC) APB Base Address */ +#define RTC (0x40002400) /**< \brief (RTC) APB Base Address */ +#define SDHC0 (0x45000000) /**< \brief (SDHC0) AHB Base Address */ +#define SDHC1 (0x46000000) /**< \brief (SDHC1) AHB Base Address */ +#define SERCOM0 (0x40003000) /**< \brief (SERCOM0) APB Base Address */ +#define SERCOM1 (0x40003400) /**< \brief (SERCOM1) APB Base Address */ +#define SERCOM2 (0x41012000) /**< \brief (SERCOM2) APB Base Address */ +#define SERCOM3 (0x41014000) /**< \brief (SERCOM3) APB Base Address */ +#define SERCOM4 (0x43000000) /**< \brief (SERCOM4) APB Base Address */ +#define SERCOM5 (0x43000400) /**< \brief (SERCOM5) APB Base Address */ +#define SERCOM6 (0x43000800) /**< \brief (SERCOM6) APB Base Address */ +#define SERCOM7 (0x43000C00) /**< \brief (SERCOM7) APB Base Address */ +#define SUPC (0x40001800) /**< \brief (SUPC) APB Base Address */ +#define TC0 (0x40003800) /**< \brief (TC0) APB Base Address */ +#define TC1 (0x40003C00) /**< \brief (TC1) APB Base Address */ +#define TC2 (0x4101A000) /**< \brief (TC2) APB Base Address */ +#define TC3 (0x4101C000) /**< \brief (TC3) APB Base Address */ +#define TC4 (0x42001400) /**< \brief (TC4) APB Base Address */ +#define TC5 (0x42001800) /**< \brief (TC5) APB Base Address */ +#define TC6 (0x43001400) /**< \brief (TC6) APB Base Address */ +#define TC7 (0x43001800) /**< \brief (TC7) APB Base Address */ +#define TCC0 (0x41016000) /**< \brief (TCC0) APB Base Address */ +#define TCC1 (0x41018000) /**< \brief (TCC1) APB Base Address */ +#define TCC2 (0x42000C00) /**< \brief (TCC2) APB Base Address */ +#define TCC3 (0x42001000) /**< \brief (TCC3) APB Base Address */ +#define TCC4 (0x43001000) /**< \brief (TCC4) APB Base Address */ +#define TRNG (0x42002800) /**< \brief (TRNG) APB Base Address */ +#define USB (0x41000000) /**< \brief (USB) APB Base Address */ +#define WDT (0x40002000) /**< \brief (WDT) APB Base Address */ +#else +#define AC ((Ac *)0x42002000UL) /**< \brief (AC) APB Base Address */ +#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ +#define AC_INSTS { AC } /**< \brief (AC) Instances List */ + +#define ADC0 ((Adc *)0x43001C00UL) /**< \brief (ADC0) APB Base Address */ +#define ADC1 ((Adc *)0x43002000UL) /**< \brief (ADC1) APB Base Address */ +#define ADC_INST_NUM 2 /**< \brief (ADC) Number of instances */ +#define ADC_INSTS { ADC0, ADC1 } /**< \brief (ADC) Instances List */ + +#define AES ((Aes *)0x42002400UL) /**< \brief (AES) APB Base Address */ +#define AES_INST_NUM 1 /**< \brief (AES) Number of instances */ +#define AES_INSTS { AES } /**< \brief (AES) Instances List */ + +#define CAN0 ((Can *)0x42000000UL) /**< \brief (CAN0) APB Base Address */ +#define CAN1 ((Can *)0x42000400UL) /**< \brief (CAN1) APB Base Address */ +#define CAN_INST_NUM 2 /**< \brief (CAN) Number of instances */ +#define CAN_INSTS { CAN0, CAN1 } /**< \brief (CAN) Instances List */ + +#define CCL ((Ccl *)0x42003800UL) /**< \brief (CCL) APB Base Address */ +#define CCL_INST_NUM 1 /**< \brief (CCL) Number of instances */ +#define CCL_INSTS { CCL } /**< \brief (CCL) Instances List */ + +#define CMCC ((Cmcc *)0x41006000UL) /**< \brief (CMCC) APB Base Address */ +#define CMCC_AHB (0x03000000UL) /**< \brief (CMCC) AHB Base Address */ +#define CMCC_INST_NUM 1 /**< \brief (CMCC) Number of instances */ +#define CMCC_INSTS { CMCC } /**< \brief (CMCC) Instances List */ + +#define DAC ((Dac *)0x43002400UL) /**< \brief (DAC) APB Base Address */ +#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */ +#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */ + +#define DMAC ((Dmac *)0x4100A000UL) /**< \brief (DMAC) APB Base Address */ +#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ +#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ + +#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ +#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ +#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ + +#define EIC ((Eic *)0x40002800UL) /**< \brief (EIC) APB Base Address */ +#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ +#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ + +#define EVSYS ((Evsys *)0x4100E000UL) /**< \brief (EVSYS) APB Base Address */ +#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ +#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ + +#define FREQM ((Freqm *)0x40002C00UL) /**< \brief (FREQM) APB Base Address */ +#define FREQM_INST_NUM 1 /**< \brief (FREQM) Number of instances */ +#define FREQM_INSTS { FREQM } /**< \brief (FREQM) Instances List */ + +#define GCLK ((Gclk *)0x40001C00UL) /**< \brief (GCLK) APB Base Address */ +#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ +#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ + +#define GMAC ((Gmac *)0x42000800UL) /**< \brief (GMAC) APB Base Address */ +#define GMAC_INST_NUM 1 /**< \brief (GMAC) Number of instances */ +#define GMAC_INSTS { GMAC } /**< \brief (GMAC) Instances List */ + +#define HMATRIX ((Hmatrixb *)0x4100C000UL) /**< \brief (HMATRIX) APB Base Address */ +#define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */ +#define HMATRIXB_INSTS { HMATRIX } /**< \brief (HMATRIXB) Instances List */ + +#define ICM ((Icm *)0x42002C00UL) /**< \brief (ICM) APB Base Address */ +#define ICM_INST_NUM 1 /**< \brief (ICM) Number of instances */ +#define ICM_INSTS { ICM } /**< \brief (ICM) Instances List */ + +#define I2S ((I2s *)0x43002800UL) /**< \brief (I2S) APB Base Address */ +#define I2S_INST_NUM 1 /**< \brief (I2S) Number of instances */ +#define I2S_INSTS { I2S } /**< \brief (I2S) Instances List */ + +#define MCLK ((Mclk *)0x40000800UL) /**< \brief (MCLK) APB Base Address */ +#define MCLK_INST_NUM 1 /**< \brief (MCLK) Number of instances */ +#define MCLK_INSTS { MCLK } /**< \brief (MCLK) Instances List */ + +#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ +#define NVMCTRL_SW0 (0x00800080UL) /**< \brief (NVMCTRL) SW0 Base Address */ +#define NVMCTRL_TEMP_LOG (0x00800100UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ +#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ +#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ +#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ + +#define OSCCTRL ((Oscctrl *)0x40001000UL) /**< \brief (OSCCTRL) APB Base Address */ +#define OSCCTRL_INST_NUM 1 /**< \brief (OSCCTRL) Number of instances */ +#define OSCCTRL_INSTS { OSCCTRL } /**< \brief (OSCCTRL) Instances List */ + +#define OSC32KCTRL ((Osc32kctrl *)0x40001400UL) /**< \brief (OSC32KCTRL) APB Base Address */ +#define OSC32KCTRL_INST_NUM 1 /**< \brief (OSC32KCTRL) Number of instances */ +#define OSC32KCTRL_INSTS { OSC32KCTRL } /**< \brief (OSC32KCTRL) Instances List */ + +#define PAC ((Pac *)0x40000000UL) /**< \brief (PAC) APB Base Address */ +#define PAC_INST_NUM 1 /**< \brief (PAC) Number of instances */ +#define PAC_INSTS { PAC } /**< \brief (PAC) Instances List */ + +#define PCC ((Pcc *)0x43002C00UL) /**< \brief (PCC) APB Base Address */ +#define PCC_INST_NUM 1 /**< \brief (PCC) Number of instances */ +#define PCC_INSTS { PCC } /**< \brief (PCC) Instances List */ + +#define PDEC ((Pdec *)0x42001C00UL) /**< \brief (PDEC) APB Base Address */ +#define PDEC_INST_NUM 1 /**< \brief (PDEC) Number of instances */ +#define PDEC_INSTS { PDEC } /**< \brief (PDEC) Instances List */ + +#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */ +#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ +#define PM_INSTS { PM } /**< \brief (PM) Instances List */ + +#define PORT ((Port *)0x41008000UL) /**< \brief (PORT) APB Base Address */ +#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ +#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ + +#define PUKCC ((void *)0x42003000UL) /**< \brief (PUKCC) APB Base Address */ +#define PUKCC_AHB ((void *)0x02000000UL) /**< \brief (PUKCC) AHB Base Address */ +#define PUKCC_INST_NUM 1 /**< \brief (PUKCC) Number of instances */ +#define PUKCC_INSTS { PUKCC } /**< \brief (PUKCC) Instances List */ + +#define QSPI ((Qspi *)0x42003400UL) /**< \brief (QSPI) APB Base Address */ +#define QSPI_AHB (0x04000000UL) /**< \brief (QSPI) AHB Base Address */ +#define QSPI_INST_NUM 1 /**< \brief (QSPI) Number of instances */ +#define QSPI_INSTS { QSPI } /**< \brief (QSPI) Instances List */ + +#define RAMECC ((Ramecc *)0x41020000UL) /**< \brief (RAMECC) APB Base Address */ +#define RAMECC_INST_NUM 1 /**< \brief (RAMECC) Number of instances */ +#define RAMECC_INSTS { RAMECC } /**< \brief (RAMECC) Instances List */ + +#define RSTC ((Rstc *)0x40000C00UL) /**< \brief (RSTC) APB Base Address */ +#define RSTC_INST_NUM 1 /**< \brief (RSTC) Number of instances */ +#define RSTC_INSTS { RSTC } /**< \brief (RSTC) Instances List */ + +#define RTC ((Rtc *)0x40002400UL) /**< \brief (RTC) APB Base Address */ +#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ +#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ + +#define SDHC0 ((Sdhc *)0x45000000UL) /**< \brief (SDHC0) AHB Base Address */ +#define SDHC1 ((Sdhc *)0x46000000UL) /**< \brief (SDHC1) AHB Base Address */ +#define SDHC_INST_NUM 2 /**< \brief (SDHC) Number of instances */ +#define SDHC_INSTS { SDHC0, SDHC1 } /**< \brief (SDHC) Instances List */ + +#define SERCOM0 ((Sercom *)0x40003000UL) /**< \brief (SERCOM0) APB Base Address */ +#define SERCOM1 ((Sercom *)0x40003400UL) /**< \brief (SERCOM1) APB Base Address */ +#define SERCOM2 ((Sercom *)0x41012000UL) /**< \brief (SERCOM2) APB Base Address */ +#define SERCOM3 ((Sercom *)0x41014000UL) /**< \brief (SERCOM3) APB Base Address */ +#define SERCOM4 ((Sercom *)0x43000000UL) /**< \brief (SERCOM4) APB Base Address */ +#define SERCOM5 ((Sercom *)0x43000400UL) /**< \brief (SERCOM5) APB Base Address */ +#define SERCOM6 ((Sercom *)0x43000800UL) /**< \brief (SERCOM6) APB Base Address */ +#define SERCOM7 ((Sercom *)0x43000C00UL) /**< \brief (SERCOM7) APB Base Address */ +#define SERCOM_INST_NUM 8 /**< \brief (SERCOM) Number of instances */ +#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5, SERCOM6, SERCOM7 } /**< \brief (SERCOM) Instances List */ + +#define SUPC ((Supc *)0x40001800UL) /**< \brief (SUPC) APB Base Address */ +#define SUPC_INST_NUM 1 /**< \brief (SUPC) Number of instances */ +#define SUPC_INSTS { SUPC } /**< \brief (SUPC) Instances List */ + +#define TC0 ((Tc *)0x40003800UL) /**< \brief (TC0) APB Base Address */ +#define TC1 ((Tc *)0x40003C00UL) /**< \brief (TC1) APB Base Address */ +#define TC2 ((Tc *)0x4101A000UL) /**< \brief (TC2) APB Base Address */ +#define TC3 ((Tc *)0x4101C000UL) /**< \brief (TC3) APB Base Address */ +#define TC4 ((Tc *)0x42001400UL) /**< \brief (TC4) APB Base Address */ +#define TC5 ((Tc *)0x42001800UL) /**< \brief (TC5) APB Base Address */ +#define TC6 ((Tc *)0x43001400UL) /**< \brief (TC6) APB Base Address */ +#define TC7 ((Tc *)0x43001800UL) /**< \brief (TC7) APB Base Address */ +#define TC_INST_NUM 8 /**< \brief (TC) Number of instances */ +#define TC_INSTS { TC0, TC1, TC2, TC3, TC4, TC5, TC6, TC7 } /**< \brief (TC) Instances List */ + +#define TCC0 ((Tcc *)0x41016000UL) /**< \brief (TCC0) APB Base Address */ +#define TCC1 ((Tcc *)0x41018000UL) /**< \brief (TCC1) APB Base Address */ +#define TCC2 ((Tcc *)0x42000C00UL) /**< \brief (TCC2) APB Base Address */ +#define TCC3 ((Tcc *)0x42001000UL) /**< \brief (TCC3) APB Base Address */ +#define TCC4 ((Tcc *)0x43001000UL) /**< \brief (TCC4) APB Base Address */ +#define TCC_INST_NUM 5 /**< \brief (TCC) Number of instances */ +#define TCC_INSTS { TCC0, TCC1, TCC2, TCC3, TCC4 } /**< \brief (TCC) Instances List */ + +#define TRNG ((Trng *)0x42002800UL) /**< \brief (TRNG) APB Base Address */ +#define TRNG_INST_NUM 1 /**< \brief (TRNG) Number of instances */ +#define TRNG_INSTS { TRNG } /**< \brief (TRNG) Instances List */ + +#define USB ((Usb *)0x41000000UL) /**< \brief (USB) APB Base Address */ +#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ +#define USB_INSTS { USB } /**< \brief (USB) Instances List */ + +#define WDT ((Wdt *)0x40002000UL) /**< \brief (WDT) APB Base Address */ +#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ +#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ + +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/*@}*/ + +/* ************************************************************************** */ +/** PORT DEFINITIONS FOR SAME54N20A */ +/* ************************************************************************** */ +/** \defgroup SAME54N20A_port PORT Definitions */ +/*@{*/ + +#include "pio/same54n20a.h" +/*@}*/ + +/* ************************************************************************** */ +/** MEMORY MAPPING DEFINITIONS FOR SAME54N20A */ +/* ************************************************************************** */ + +#define HSRAM_SIZE _UL_(0x00040000) /* 256 kB */ +#define FLASH_SIZE _UL_(0x00100000) /* 1024 kB */ +#define FLASH_PAGE_SIZE 512 +#define FLASH_NB_OF_PAGES 2048 +#define FLASH_USER_PAGE_SIZE 512 +#define BKUPRAM_SIZE _UL_(0x00002000) /* 8 kB */ +#define QSPI_SIZE _UL_(0x01000000) /* 16384 kB */ + +#define FLASH_ADDR _UL_(0x00000000) /**< FLASH base address */ +#define CMCC_DATARAM_ADDR _UL_(0x03000000) /**< CMCC_DATARAM base address */ +#define CMCC_DATARAM_SIZE _UL_(0x00001000) /**< CMCC_DATARAM size */ +#define CMCC_TAGRAM_ADDR _UL_(0x03001000) /**< CMCC_TAGRAM base address */ +#define CMCC_TAGRAM_SIZE _UL_(0x00000400) /**< CMCC_TAGRAM size */ +#define CMCC_VALIDRAM_ADDR _UL_(0x03002000) /**< CMCC_VALIDRAM base address */ +#define CMCC_VALIDRAM_SIZE _UL_(0x00000040) /**< CMCC_VALIDRAM size */ +#define HSRAM_ADDR _UL_(0x20000000) /**< HSRAM base address */ +#define HSRAM_ETB_ADDR _UL_(0x20000000) /**< HSRAM_ETB base address */ +#define HSRAM_ETB_SIZE _UL_(0x00008000) /**< HSRAM_ETB size */ +#define HSRAM_RET1_ADDR _UL_(0x20000000) /**< HSRAM_RET1 base address */ +#define HSRAM_RET1_SIZE _UL_(0x00008000) /**< HSRAM_RET1 size */ +#define HPB0_ADDR _UL_(0x40000000) /**< HPB0 base address */ +#define HPB1_ADDR _UL_(0x41000000) /**< HPB1 base address */ +#define HPB2_ADDR _UL_(0x42000000) /**< HPB2 base address */ +#define HPB3_ADDR _UL_(0x43000000) /**< HPB3 base address */ +#define SEEPROM_ADDR _UL_(0x44000000) /**< SEEPROM base address */ +#define BKUPRAM_ADDR _UL_(0x47000000) /**< BKUPRAM base address */ +#define PPB_ADDR _UL_(0xE0000000) /**< PPB base address */ + +#define DSU_DID_RESETVALUE _UL_(0x61840302) +#define ADC0_TOUCH_LINES_NUM 32 +#define PORT_GROUPS 3 + +/* ************************************************************************** */ +/** ELECTRICAL DEFINITIONS FOR SAME54N20A */ +/* ************************************************************************** */ + + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* SAME54N20A_H */ diff --git a/arch/arm/SAME54/SAME54A/mcu/inc/same54p19a.h b/arch/arm/SAME54/SAME54A/mcu/inc/same54p19a.h index fab2edc9..ed3ae044 100644 --- a/arch/arm/SAME54/SAME54A/mcu/inc/same54p19a.h +++ b/arch/arm/SAME54/SAME54A/mcu/inc/same54p19a.h @@ -1,1113 +1,1085 @@ -/** - * \brief Header file for ATSAME54P19A - * - * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries. - * - * Subject to your compliance with these terms, you may use Microchip software and any derivatives - * exclusively with Microchip products. It is your responsibility to comply with third party license - * terms applicable to your use of third party software (including open source software) that may - * accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, - * APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND - * FITNESS FOR A PARTICULAR PURPOSE. - * - * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF - * MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT - * EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - */ - -/* file generated from device description version 2020-03-12T17:27:01Z */ -#ifndef _SAME54P19A_H_ -#define _SAME54P19A_H_ - -// Header version uses Semantic Versioning 2.0.0 (https://semver.org/) -#define HEADER_FORMAT_VERSION "2.0.0" - -#define HEADER_FORMAT_VERSION_MAJOR (2) -#define HEADER_FORMAT_VERSION_MINOR (0) - -/** \addtogroup SAME54P19A_definitions SAME54P19A definitions - This file defines all structures and symbols for SAME54P19A: - - registers and bitfields - - peripheral base address - - peripheral ID - - PIO definitions - * @{ - */ - -#ifdef __cplusplus - extern "C" { -#endif - -#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) -# include -#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#if !defined(SKIP_INTEGER_LITERALS) -# if defined(_U_) || defined(_L_) || defined(_UL_) -# error "Integer Literals macros already defined elsewhere" -# endif - -#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) -/* Macros that deal with adding suffixes to integer literal constants for C/C++ */ -# define _U_(x) (x ## U) /**< C code: Unsigned integer literal constant value */ -# define _L_(x) (x ## L) /**< C code: Long integer literal constant value */ -# define _UL_(x) (x ## UL) /**< C code: Unsigned Long integer literal constant value */ - -#else /* Assembler */ - -# define _U_(x) x /**< Assembler: Unsigned integer literal constant value */ -# define _L_(x) x /**< Assembler: Long integer literal constant value */ -# define _UL_(x) x /**< Assembler: Unsigned Long integer literal constant value */ -#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ -#endif /* SKIP_INTEGER_LITERALS */ -/** @} end of Atmel Global Defines */ - -/* ************************************************************************** */ -/* CMSIS DEFINITIONS FOR SAME54P19A */ -/* ************************************************************************** */ -#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) -/** Interrupt Number Definition */ -typedef enum IRQn -{ -/****** CORTEX-M4 Processor Exceptions Numbers ******************************/ - Reset_IRQn = -15, /**< -15 Reset Vector, invoked on Power up and warm reset */ - NonMaskableInt_IRQn = -14, /**< -14 Non maskable Interrupt, cannot be stopped or preempted */ - HardFault_IRQn = -13, /**< -13 Hard Fault, all classes of Fault */ - MemoryManagement_IRQn = -12, /**< -12 Memory Management, MPU mismatch, including Access Violation and No Match */ - BusFault_IRQn = -11, /**< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */ - UsageFault_IRQn = -10, /**< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ - SVCall_IRQn = -5, /**< -5 System Service Call via SVC instruction */ - DebugMonitor_IRQn = -4, /**< -4 Debug Monitor */ - PendSV_IRQn = -2, /**< -2 Pendable request for system service */ - SysTick_IRQn = -1, /**< -1 System Tick Timer */ -/****** SAME54P19A specific Interrupt Numbers ***********************************/ - PM_IRQn = 0, /**< 0 Power Manager (PM) */ - MCLK_IRQn = 1, /**< 1 Main Clock (MCLK) */ - OSCCTRL_XOSC0_IRQn = 2, /**< 2 Oscillators Control (OSCCTRL) */ - OSCCTRL_XOSC1_IRQn = 3, /**< 3 Oscillators Control (OSCCTRL) */ - OSCCTRL_DFLL_IRQn = 4, /**< 4 Oscillators Control (OSCCTRL) */ - OSCCTRL_DPLL0_IRQn = 5, /**< 5 Oscillators Control (OSCCTRL) */ - OSCCTRL_DPLL1_IRQn = 6, /**< 6 Oscillators Control (OSCCTRL) */ - OSC32KCTRL_IRQn = 7, /**< 7 32kHz Oscillators Control (OSC32KCTRL) */ - SUPC_OTHER_IRQn = 8, /**< 8 Supply Controller (SUPC) */ - SUPC_BODDET_IRQn = 9, /**< 9 Supply Controller (SUPC) */ - WDT_IRQn = 10, /**< 10 Watchdog Timer (WDT) */ - RTC_IRQn = 11, /**< 11 Real-Time Counter (RTC) */ - EIC_EXTINT_0_IRQn = 12, /**< 12 External Interrupt Controller (EIC) */ - EIC_EXTINT_1_IRQn = 13, /**< 13 External Interrupt Controller (EIC) */ - EIC_EXTINT_2_IRQn = 14, /**< 14 External Interrupt Controller (EIC) */ - EIC_EXTINT_3_IRQn = 15, /**< 15 External Interrupt Controller (EIC) */ - EIC_EXTINT_4_IRQn = 16, /**< 16 External Interrupt Controller (EIC) */ - EIC_EXTINT_5_IRQn = 17, /**< 17 External Interrupt Controller (EIC) */ - EIC_EXTINT_6_IRQn = 18, /**< 18 External Interrupt Controller (EIC) */ - EIC_EXTINT_7_IRQn = 19, /**< 19 External Interrupt Controller (EIC) */ - EIC_EXTINT_8_IRQn = 20, /**< 20 External Interrupt Controller (EIC) */ - EIC_EXTINT_9_IRQn = 21, /**< 21 External Interrupt Controller (EIC) */ - EIC_EXTINT_10_IRQn = 22, /**< 22 External Interrupt Controller (EIC) */ - EIC_EXTINT_11_IRQn = 23, /**< 23 External Interrupt Controller (EIC) */ - EIC_EXTINT_12_IRQn = 24, /**< 24 External Interrupt Controller (EIC) */ - EIC_EXTINT_13_IRQn = 25, /**< 25 External Interrupt Controller (EIC) */ - EIC_EXTINT_14_IRQn = 26, /**< 26 External Interrupt Controller (EIC) */ - EIC_EXTINT_15_IRQn = 27, /**< 27 External Interrupt Controller (EIC) */ - FREQM_IRQn = 28, /**< 28 Frequency Meter (FREQM) */ - NVMCTRL_0_IRQn = 29, /**< 29 Non-Volatile Memory Controller (NVMCTRL) */ - NVMCTRL_1_IRQn = 30, /**< 30 Non-Volatile Memory Controller (NVMCTRL) */ - DMAC_0_IRQn = 31, /**< 31 Direct Memory Access Controller (DMAC) */ - DMAC_1_IRQn = 32, /**< 32 Direct Memory Access Controller (DMAC) */ - DMAC_2_IRQn = 33, /**< 33 Direct Memory Access Controller (DMAC) */ - DMAC_3_IRQn = 34, /**< 34 Direct Memory Access Controller (DMAC) */ - DMAC_OTHER_IRQn = 35, /**< 35 Direct Memory Access Controller (DMAC) */ - EVSYS_0_IRQn = 36, /**< 36 Event System Interface (EVSYS) */ - EVSYS_1_IRQn = 37, /**< 37 Event System Interface (EVSYS) */ - EVSYS_2_IRQn = 38, /**< 38 Event System Interface (EVSYS) */ - EVSYS_3_IRQn = 39, /**< 39 Event System Interface (EVSYS) */ - EVSYS_OTHER_IRQn = 40, /**< 40 Event System Interface (EVSYS) */ - PAC_IRQn = 41, /**< 41 Peripheral Access Controller (PAC) */ - RAMECC_IRQn = 45, /**< 45 RAM ECC (RAMECC) */ - SERCOM0_0_IRQn = 46, /**< 46 Serial Communication Interface (SERCOM0) */ - SERCOM0_1_IRQn = 47, /**< 47 Serial Communication Interface (SERCOM0) */ - SERCOM0_2_IRQn = 48, /**< 48 Serial Communication Interface (SERCOM0) */ - SERCOM0_OTHER_IRQn = 49, /**< 49 Serial Communication Interface (SERCOM0) */ - SERCOM1_0_IRQn = 50, /**< 50 Serial Communication Interface (SERCOM1) */ - SERCOM1_1_IRQn = 51, /**< 51 Serial Communication Interface (SERCOM1) */ - SERCOM1_2_IRQn = 52, /**< 52 Serial Communication Interface (SERCOM1) */ - SERCOM1_OTHER_IRQn = 53, /**< 53 Serial Communication Interface (SERCOM1) */ - SERCOM2_0_IRQn = 54, /**< 54 Serial Communication Interface (SERCOM2) */ - SERCOM2_1_IRQn = 55, /**< 55 Serial Communication Interface (SERCOM2) */ - SERCOM2_2_IRQn = 56, /**< 56 Serial Communication Interface (SERCOM2) */ - SERCOM2_OTHER_IRQn = 57, /**< 57 Serial Communication Interface (SERCOM2) */ - SERCOM3_0_IRQn = 58, /**< 58 Serial Communication Interface (SERCOM3) */ - SERCOM3_1_IRQn = 59, /**< 59 Serial Communication Interface (SERCOM3) */ - SERCOM3_2_IRQn = 60, /**< 60 Serial Communication Interface (SERCOM3) */ - SERCOM3_OTHER_IRQn = 61, /**< 61 Serial Communication Interface (SERCOM3) */ - SERCOM4_0_IRQn = 62, /**< 62 Serial Communication Interface (SERCOM4) */ - SERCOM4_1_IRQn = 63, /**< 63 Serial Communication Interface (SERCOM4) */ - SERCOM4_2_IRQn = 64, /**< 64 Serial Communication Interface (SERCOM4) */ - SERCOM4_OTHER_IRQn = 65, /**< 65 Serial Communication Interface (SERCOM4) */ - SERCOM5_0_IRQn = 66, /**< 66 Serial Communication Interface (SERCOM5) */ - SERCOM5_1_IRQn = 67, /**< 67 Serial Communication Interface (SERCOM5) */ - SERCOM5_2_IRQn = 68, /**< 68 Serial Communication Interface (SERCOM5) */ - SERCOM5_OTHER_IRQn = 69, /**< 69 Serial Communication Interface (SERCOM5) */ - SERCOM6_0_IRQn = 70, /**< 70 Serial Communication Interface (SERCOM6) */ - SERCOM6_1_IRQn = 71, /**< 71 Serial Communication Interface (SERCOM6) */ - SERCOM6_2_IRQn = 72, /**< 72 Serial Communication Interface (SERCOM6) */ - SERCOM6_OTHER_IRQn = 73, /**< 73 Serial Communication Interface (SERCOM6) */ - SERCOM7_0_IRQn = 74, /**< 74 Serial Communication Interface (SERCOM7) */ - SERCOM7_1_IRQn = 75, /**< 75 Serial Communication Interface (SERCOM7) */ - SERCOM7_2_IRQn = 76, /**< 76 Serial Communication Interface (SERCOM7) */ - SERCOM7_OTHER_IRQn = 77, /**< 77 Serial Communication Interface (SERCOM7) */ - CAN0_IRQn = 78, /**< 78 Control Area Network (CAN0) */ - CAN1_IRQn = 79, /**< 79 Control Area Network (CAN1) */ - USB_OTHER_IRQn = 80, /**< 80 Universal Serial Bus (USB) */ - USB_SOF_HSOF_IRQn = 81, /**< 81 Universal Serial Bus (USB) */ - USB_TRCPT0_IRQn = 82, /**< 82 Universal Serial Bus (USB) */ - USB_TRCPT1_IRQn = 83, /**< 83 Universal Serial Bus (USB) */ - GMAC_IRQn = 84, /**< 84 Ethernet MAC (GMAC) */ - TCC0_OTHER_IRQn = 85, /**< 85 Timer Counter Control (TCC0) */ - TCC0_MC0_IRQn = 86, /**< 86 Timer Counter Control (TCC0) */ - TCC0_MC1_IRQn = 87, /**< 87 Timer Counter Control (TCC0) */ - TCC0_MC2_IRQn = 88, /**< 88 Timer Counter Control (TCC0) */ - TCC0_MC3_IRQn = 89, /**< 89 Timer Counter Control (TCC0) */ - TCC0_MC4_IRQn = 90, /**< 90 Timer Counter Control (TCC0) */ - TCC0_MC5_IRQn = 91, /**< 91 Timer Counter Control (TCC0) */ - TCC1_OTHER_IRQn = 92, /**< 92 Timer Counter Control (TCC1) */ - TCC1_MC0_IRQn = 93, /**< 93 Timer Counter Control (TCC1) */ - TCC1_MC1_IRQn = 94, /**< 94 Timer Counter Control (TCC1) */ - TCC1_MC2_IRQn = 95, /**< 95 Timer Counter Control (TCC1) */ - TCC1_MC3_IRQn = 96, /**< 96 Timer Counter Control (TCC1) */ - TCC2_OTHER_IRQn = 97, /**< 97 Timer Counter Control (TCC2) */ - TCC2_MC0_IRQn = 98, /**< 98 Timer Counter Control (TCC2) */ - TCC2_MC1_IRQn = 99, /**< 99 Timer Counter Control (TCC2) */ - TCC2_MC2_IRQn = 100, /**< 100 Timer Counter Control (TCC2) */ - TCC3_OTHER_IRQn = 101, /**< 101 Timer Counter Control (TCC3) */ - TCC3_MC0_IRQn = 102, /**< 102 Timer Counter Control (TCC3) */ - TCC3_MC1_IRQn = 103, /**< 103 Timer Counter Control (TCC3) */ - TCC4_OTHER_IRQn = 104, /**< 104 Timer Counter Control (TCC4) */ - TCC4_MC0_IRQn = 105, /**< 105 Timer Counter Control (TCC4) */ - TCC4_MC1_IRQn = 106, /**< 106 Timer Counter Control (TCC4) */ - TC0_IRQn = 107, /**< 107 Basic Timer Counter (TC0) */ - TC1_IRQn = 108, /**< 108 Basic Timer Counter (TC1) */ - TC2_IRQn = 109, /**< 109 Basic Timer Counter (TC2) */ - TC3_IRQn = 110, /**< 110 Basic Timer Counter (TC3) */ - TC4_IRQn = 111, /**< 111 Basic Timer Counter (TC4) */ - TC5_IRQn = 112, /**< 112 Basic Timer Counter (TC5) */ - TC6_IRQn = 113, /**< 113 Basic Timer Counter (TC6) */ - TC7_IRQn = 114, /**< 114 Basic Timer Counter (TC7) */ - PDEC_OTHER_IRQn = 115, /**< 115 Quadrature Decodeur (PDEC) */ - PDEC_MC0_IRQn = 116, /**< 116 Quadrature Decodeur (PDEC) */ - PDEC_MC1_IRQn = 117, /**< 117 Quadrature Decodeur (PDEC) */ - ADC0_OTHER_IRQn = 118, /**< 118 Analog Digital Converter (ADC0) */ - ADC0_RESRDY_IRQn = 119, /**< 119 Analog Digital Converter (ADC0) */ - ADC1_OTHER_IRQn = 120, /**< 120 Analog Digital Converter (ADC1) */ - ADC1_RESRDY_IRQn = 121, /**< 121 Analog Digital Converter (ADC1) */ - AC_IRQn = 122, /**< 122 Analog Comparators (AC) */ - DAC_OTHER_IRQn = 123, /**< 123 Digital-to-Analog Converter (DAC) */ - DAC_EMPTY_0_IRQn = 124, /**< 124 Digital-to-Analog Converter (DAC) */ - DAC_EMPTY_1_IRQn = 125, /**< 125 Digital-to-Analog Converter (DAC) */ - DAC_RESRDY_0_IRQn = 126, /**< 126 Digital-to-Analog Converter (DAC) */ - DAC_RESRDY_1_IRQn = 127, /**< 127 Digital-to-Analog Converter (DAC) */ - I2S_IRQn = 128, /**< 128 Inter-IC Sound Interface (I2S) */ - PCC_IRQn = 129, /**< 129 Parallel Capture Controller (PCC) */ - AES_IRQn = 130, /**< 130 Advanced Encryption Standard (AES) */ - TRNG_IRQn = 131, /**< 131 True Random Generator (TRNG) */ - ICM_IRQn = 132, /**< 132 Integrity Check Monitor (ICM) */ - PUKCC_IRQn = 133, /**< 133 PUblic-Key Cryptography Controller (PUKCC) */ - QSPI_IRQn = 134, /**< 134 Quad SPI interface (QSPI) */ - SDHC0_IRQn = 135, /**< 135 SD/MMC Host Controller (SDHC0) */ - SDHC1_IRQn = 136, /**< 136 SD/MMC Host Controller (SDHC1) */ - - PERIPH_MAX_IRQn = 136 /**< Max peripheral ID */ -} IRQn_Type; -#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) -typedef struct _DeviceVectors -{ - /* Stack pointer */ - void* pvStack; - /* Cortex-M handlers */ - void* pfnReset_Handler; /* -15 Reset Vector, invoked on Power up and warm reset */ - void* pfnNonMaskableInt_Handler; /* -14 Non maskable Interrupt, cannot be stopped or preempted */ - void* pfnHardFault_Handler; /* -13 Hard Fault, all classes of Fault */ - void* pfnMemoryManagement_Handler; /* -12 Memory Management, MPU mismatch, including Access Violation and No Match */ - void* pfnBusFault_Handler; /* -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */ - void* pfnUsageFault_Handler; /* -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ - void* pvReservedC9; - void* pvReservedC8; - void* pvReservedC7; - void* pvReservedC6; - void* pfnSVCall_Handler; /* -5 System Service Call via SVC instruction */ - void* pfnDebugMonitor_Handler; /* -4 Debug Monitor */ - void* pvReservedC3; - void* pfnPendSV_Handler; /* -2 Pendable request for system service */ - void* pfnSysTick_Handler; /* -1 System Tick Timer */ - - /* Peripheral handlers */ - void* pfnPM_Handler; /* 0 Power Manager (PM) */ - void* pfnMCLK_Handler; /* 1 Main Clock (MCLK) */ - void* pfnOSCCTRL_XOSC0_Handler; /* 2 Oscillators Control (OSCCTRL) */ - void* pfnOSCCTRL_XOSC1_Handler; /* 3 Oscillators Control (OSCCTRL) */ - void* pfnOSCCTRL_DFLL_Handler; /* 4 Oscillators Control (OSCCTRL) */ - void* pfnOSCCTRL_DPLL0_Handler; /* 5 Oscillators Control (OSCCTRL) */ - void* pfnOSCCTRL_DPLL1_Handler; /* 6 Oscillators Control (OSCCTRL) */ - void* pfnOSC32KCTRL_Handler; /* 7 32kHz Oscillators Control (OSC32KCTRL) */ - void* pfnSUPC_OTHER_Handler; /* 8 Supply Controller (SUPC) */ - void* pfnSUPC_BODDET_Handler; /* 9 Supply Controller (SUPC) */ - void* pfnWDT_Handler; /* 10 Watchdog Timer (WDT) */ - void* pfnRTC_Handler; /* 11 Real-Time Counter (RTC) */ - void* pfnEIC_EXTINT_0_Handler; /* 12 External Interrupt Controller (EIC) */ - void* pfnEIC_EXTINT_1_Handler; /* 13 External Interrupt Controller (EIC) */ - void* pfnEIC_EXTINT_2_Handler; /* 14 External Interrupt Controller (EIC) */ - void* pfnEIC_EXTINT_3_Handler; /* 15 External Interrupt Controller (EIC) */ - void* pfnEIC_EXTINT_4_Handler; /* 16 External Interrupt Controller (EIC) */ - void* pfnEIC_EXTINT_5_Handler; /* 17 External Interrupt Controller (EIC) */ - void* pfnEIC_EXTINT_6_Handler; /* 18 External Interrupt Controller (EIC) */ - void* pfnEIC_EXTINT_7_Handler; /* 19 External Interrupt Controller (EIC) */ - void* pfnEIC_EXTINT_8_Handler; /* 20 External Interrupt Controller (EIC) */ - void* pfnEIC_EXTINT_9_Handler; /* 21 External Interrupt Controller (EIC) */ - void* pfnEIC_EXTINT_10_Handler; /* 22 External Interrupt Controller (EIC) */ - void* pfnEIC_EXTINT_11_Handler; /* 23 External Interrupt Controller (EIC) */ - void* pfnEIC_EXTINT_12_Handler; /* 24 External Interrupt Controller (EIC) */ - void* pfnEIC_EXTINT_13_Handler; /* 25 External Interrupt Controller (EIC) */ - void* pfnEIC_EXTINT_14_Handler; /* 26 External Interrupt Controller (EIC) */ - void* pfnEIC_EXTINT_15_Handler; /* 27 External Interrupt Controller (EIC) */ - void* pfnFREQM_Handler; /* 28 Frequency Meter (FREQM) */ - void* pfnNVMCTRL_0_Handler; /* 29 Non-Volatile Memory Controller (NVMCTRL) */ - void* pfnNVMCTRL_1_Handler; /* 30 Non-Volatile Memory Controller (NVMCTRL) */ - void* pfnDMAC_0_Handler; /* 31 Direct Memory Access Controller (DMAC) */ - void* pfnDMAC_1_Handler; /* 32 Direct Memory Access Controller (DMAC) */ - void* pfnDMAC_2_Handler; /* 33 Direct Memory Access Controller (DMAC) */ - void* pfnDMAC_3_Handler; /* 34 Direct Memory Access Controller (DMAC) */ - void* pfnDMAC_OTHER_Handler; /* 35 Direct Memory Access Controller (DMAC) */ - void* pfnEVSYS_0_Handler; /* 36 Event System Interface (EVSYS) */ - void* pfnEVSYS_1_Handler; /* 37 Event System Interface (EVSYS) */ - void* pfnEVSYS_2_Handler; /* 38 Event System Interface (EVSYS) */ - void* pfnEVSYS_3_Handler; /* 39 Event System Interface (EVSYS) */ - void* pfnEVSYS_OTHER_Handler; /* 40 Event System Interface (EVSYS) */ - void* pfnPAC_Handler; /* 41 Peripheral Access Controller (PAC) */ - void* pvReserved42; - void* pvReserved43; - void* pvReserved44; - void* pfnRAMECC_Handler; /* 45 RAM ECC (RAMECC) */ - void* pfnSERCOM0_0_Handler; /* 46 Serial Communication Interface (SERCOM0) */ - void* pfnSERCOM0_1_Handler; /* 47 Serial Communication Interface (SERCOM0) */ - void* pfnSERCOM0_2_Handler; /* 48 Serial Communication Interface (SERCOM0) */ - void* pfnSERCOM0_OTHER_Handler; /* 49 Serial Communication Interface (SERCOM0) */ - void* pfnSERCOM1_0_Handler; /* 50 Serial Communication Interface (SERCOM1) */ - void* pfnSERCOM1_1_Handler; /* 51 Serial Communication Interface (SERCOM1) */ - void* pfnSERCOM1_2_Handler; /* 52 Serial Communication Interface (SERCOM1) */ - void* pfnSERCOM1_OTHER_Handler; /* 53 Serial Communication Interface (SERCOM1) */ - void* pfnSERCOM2_0_Handler; /* 54 Serial Communication Interface (SERCOM2) */ - void* pfnSERCOM2_1_Handler; /* 55 Serial Communication Interface (SERCOM2) */ - void* pfnSERCOM2_2_Handler; /* 56 Serial Communication Interface (SERCOM2) */ - void* pfnSERCOM2_OTHER_Handler; /* 57 Serial Communication Interface (SERCOM2) */ - void* pfnSERCOM3_0_Handler; /* 58 Serial Communication Interface (SERCOM3) */ - void* pfnSERCOM3_1_Handler; /* 59 Serial Communication Interface (SERCOM3) */ - void* pfnSERCOM3_2_Handler; /* 60 Serial Communication Interface (SERCOM3) */ - void* pfnSERCOM3_OTHER_Handler; /* 61 Serial Communication Interface (SERCOM3) */ - void* pfnSERCOM4_0_Handler; /* 62 Serial Communication Interface (SERCOM4) */ - void* pfnSERCOM4_1_Handler; /* 63 Serial Communication Interface (SERCOM4) */ - void* pfnSERCOM4_2_Handler; /* 64 Serial Communication Interface (SERCOM4) */ - void* pfnSERCOM4_OTHER_Handler; /* 65 Serial Communication Interface (SERCOM4) */ - void* pfnSERCOM5_0_Handler; /* 66 Serial Communication Interface (SERCOM5) */ - void* pfnSERCOM5_1_Handler; /* 67 Serial Communication Interface (SERCOM5) */ - void* pfnSERCOM5_2_Handler; /* 68 Serial Communication Interface (SERCOM5) */ - void* pfnSERCOM5_OTHER_Handler; /* 69 Serial Communication Interface (SERCOM5) */ - void* pfnSERCOM6_0_Handler; /* 70 Serial Communication Interface (SERCOM6) */ - void* pfnSERCOM6_1_Handler; /* 71 Serial Communication Interface (SERCOM6) */ - void* pfnSERCOM6_2_Handler; /* 72 Serial Communication Interface (SERCOM6) */ - void* pfnSERCOM6_OTHER_Handler; /* 73 Serial Communication Interface (SERCOM6) */ - void* pfnSERCOM7_0_Handler; /* 74 Serial Communication Interface (SERCOM7) */ - void* pfnSERCOM7_1_Handler; /* 75 Serial Communication Interface (SERCOM7) */ - void* pfnSERCOM7_2_Handler; /* 76 Serial Communication Interface (SERCOM7) */ - void* pfnSERCOM7_OTHER_Handler; /* 77 Serial Communication Interface (SERCOM7) */ - void* pfnCAN0_Handler; /* 78 Control Area Network (CAN0) */ - void* pfnCAN1_Handler; /* 79 Control Area Network (CAN1) */ - void* pfnUSB_OTHER_Handler; /* 80 Universal Serial Bus (USB) */ - void* pfnUSB_SOF_HSOF_Handler; /* 81 Universal Serial Bus (USB) */ - void* pfnUSB_TRCPT0_Handler; /* 82 Universal Serial Bus (USB) */ - void* pfnUSB_TRCPT1_Handler; /* 83 Universal Serial Bus (USB) */ - void* pfnGMAC_Handler; /* 84 Ethernet MAC (GMAC) */ - void* pfnTCC0_OTHER_Handler; /* 85 Timer Counter Control (TCC0) */ - void* pfnTCC0_MC0_Handler; /* 86 Timer Counter Control (TCC0) */ - void* pfnTCC0_MC1_Handler; /* 87 Timer Counter Control (TCC0) */ - void* pfnTCC0_MC2_Handler; /* 88 Timer Counter Control (TCC0) */ - void* pfnTCC0_MC3_Handler; /* 89 Timer Counter Control (TCC0) */ - void* pfnTCC0_MC4_Handler; /* 90 Timer Counter Control (TCC0) */ - void* pfnTCC0_MC5_Handler; /* 91 Timer Counter Control (TCC0) */ - void* pfnTCC1_OTHER_Handler; /* 92 Timer Counter Control (TCC1) */ - void* pfnTCC1_MC0_Handler; /* 93 Timer Counter Control (TCC1) */ - void* pfnTCC1_MC1_Handler; /* 94 Timer Counter Control (TCC1) */ - void* pfnTCC1_MC2_Handler; /* 95 Timer Counter Control (TCC1) */ - void* pfnTCC1_MC3_Handler; /* 96 Timer Counter Control (TCC1) */ - void* pfnTCC2_OTHER_Handler; /* 97 Timer Counter Control (TCC2) */ - void* pfnTCC2_MC0_Handler; /* 98 Timer Counter Control (TCC2) */ - void* pfnTCC2_MC1_Handler; /* 99 Timer Counter Control (TCC2) */ - void* pfnTCC2_MC2_Handler; /* 100 Timer Counter Control (TCC2) */ - void* pfnTCC3_OTHER_Handler; /* 101 Timer Counter Control (TCC3) */ - void* pfnTCC3_MC0_Handler; /* 102 Timer Counter Control (TCC3) */ - void* pfnTCC3_MC1_Handler; /* 103 Timer Counter Control (TCC3) */ - void* pfnTCC4_OTHER_Handler; /* 104 Timer Counter Control (TCC4) */ - void* pfnTCC4_MC0_Handler; /* 105 Timer Counter Control (TCC4) */ - void* pfnTCC4_MC1_Handler; /* 106 Timer Counter Control (TCC4) */ - void* pfnTC0_Handler; /* 107 Basic Timer Counter (TC0) */ - void* pfnTC1_Handler; /* 108 Basic Timer Counter (TC1) */ - void* pfnTC2_Handler; /* 109 Basic Timer Counter (TC2) */ - void* pfnTC3_Handler; /* 110 Basic Timer Counter (TC3) */ - void* pfnTC4_Handler; /* 111 Basic Timer Counter (TC4) */ - void* pfnTC5_Handler; /* 112 Basic Timer Counter (TC5) */ - void* pfnTC6_Handler; /* 113 Basic Timer Counter (TC6) */ - void* pfnTC7_Handler; /* 114 Basic Timer Counter (TC7) */ - void* pfnPDEC_OTHER_Handler; /* 115 Quadrature Decodeur (PDEC) */ - void* pfnPDEC_MC0_Handler; /* 116 Quadrature Decodeur (PDEC) */ - void* pfnPDEC_MC1_Handler; /* 117 Quadrature Decodeur (PDEC) */ - void* pfnADC0_OTHER_Handler; /* 118 Analog Digital Converter (ADC0) */ - void* pfnADC0_RESRDY_Handler; /* 119 Analog Digital Converter (ADC0) */ - void* pfnADC1_OTHER_Handler; /* 120 Analog Digital Converter (ADC1) */ - void* pfnADC1_RESRDY_Handler; /* 121 Analog Digital Converter (ADC1) */ - void* pfnAC_Handler; /* 122 Analog Comparators (AC) */ - void* pfnDAC_OTHER_Handler; /* 123 Digital-to-Analog Converter (DAC) */ - void* pfnDAC_EMPTY_0_Handler; /* 124 Digital-to-Analog Converter (DAC) */ - void* pfnDAC_EMPTY_1_Handler; /* 125 Digital-to-Analog Converter (DAC) */ - void* pfnDAC_RESRDY_0_Handler; /* 126 Digital-to-Analog Converter (DAC) */ - void* pfnDAC_RESRDY_1_Handler; /* 127 Digital-to-Analog Converter (DAC) */ - void* pfnI2S_Handler; /* 128 Inter-IC Sound Interface (I2S) */ - void* pfnPCC_Handler; /* 129 Parallel Capture Controller (PCC) */ - void* pfnAES_Handler; /* 130 Advanced Encryption Standard (AES) */ - void* pfnTRNG_Handler; /* 131 True Random Generator (TRNG) */ - void* pfnICM_Handler; /* 132 Integrity Check Monitor (ICM) */ - void* pfnPUKCC_Handler; /* 133 PUblic-Key Cryptography Controller (PUKCC) */ - void* pfnQSPI_Handler; /* 134 Quad SPI interface (QSPI) */ - void* pfnSDHC0_Handler; /* 135 SD/MMC Host Controller (SDHC0) */ - void* pfnSDHC1_Handler; /* 136 SD/MMC Host Controller (SDHC1) */ -} DeviceVectors; - -/* Defines for Deprecated Interrupt and Exceptions handler names */ -#define pfnMemManage_Handler pfnMemoryManagement_Handler /**< \deprecated Backward compatibility for ASF*/ -#define pfnDebugMon_Handler pfnDebugMonitor_Handler /**< \deprecated Backward compatibility for ASF*/ -#define pfnNMI_Handler pfnNonMaskableInt_Handler /**< \deprecated Backward compatibility for ASF*/ -#define pfnSVC_Handler pfnSVCall_Handler /**< \deprecated Backward compatibility for ASF*/ - -#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) -#if !defined DONT_USE_PREDEFINED_CORE_HANDLERS -/* CORTEX-M4 exception handlers */ -void Reset_Handler ( void ); -void NonMaskableInt_Handler ( void ); -void HardFault_Handler ( void ); -void MemoryManagement_Handler ( void ); -void BusFault_Handler ( void ); -void UsageFault_Handler ( void ); -void SVCall_Handler ( void ); -void DebugMonitor_Handler ( void ); -void PendSV_Handler ( void ); -void SysTick_Handler ( void ); -#endif /* DONT_USE_PREDEFINED_CORE_HANDLERS */ - -#if !defined DONT_USE_PREDEFINED_PERIPHERALS_HANDLERS -/* Peripherals interrupt handlers */ -void PM_Handler ( void ); -void MCLK_Handler ( void ); -void OSCCTRL_XOSC0_Handler ( void ); -void OSCCTRL_XOSC1_Handler ( void ); -void OSCCTRL_DFLL_Handler ( void ); -void OSCCTRL_DPLL0_Handler ( void ); -void OSCCTRL_DPLL1_Handler ( void ); -void OSC32KCTRL_Handler ( void ); -void SUPC_OTHER_Handler ( void ); -void SUPC_BODDET_Handler ( void ); -void WDT_Handler ( void ); -void RTC_Handler ( void ); -void EIC_EXTINT_0_Handler ( void ); -void EIC_EXTINT_1_Handler ( void ); -void EIC_EXTINT_2_Handler ( void ); -void EIC_EXTINT_3_Handler ( void ); -void EIC_EXTINT_4_Handler ( void ); -void EIC_EXTINT_5_Handler ( void ); -void EIC_EXTINT_6_Handler ( void ); -void EIC_EXTINT_7_Handler ( void ); -void EIC_EXTINT_8_Handler ( void ); -void EIC_EXTINT_9_Handler ( void ); -void EIC_EXTINT_10_Handler ( void ); -void EIC_EXTINT_11_Handler ( void ); -void EIC_EXTINT_12_Handler ( void ); -void EIC_EXTINT_13_Handler ( void ); -void EIC_EXTINT_14_Handler ( void ); -void EIC_EXTINT_15_Handler ( void ); -void FREQM_Handler ( void ); -void NVMCTRL_0_Handler ( void ); -void NVMCTRL_1_Handler ( void ); -void DMAC_0_Handler ( void ); -void DMAC_1_Handler ( void ); -void DMAC_2_Handler ( void ); -void DMAC_3_Handler ( void ); -void DMAC_OTHER_Handler ( void ); -void EVSYS_0_Handler ( void ); -void EVSYS_1_Handler ( void ); -void EVSYS_2_Handler ( void ); -void EVSYS_3_Handler ( void ); -void EVSYS_OTHER_Handler ( void ); -void PAC_Handler ( void ); -void RAMECC_Handler ( void ); -void SERCOM0_0_Handler ( void ); -void SERCOM0_1_Handler ( void ); -void SERCOM0_2_Handler ( void ); -void SERCOM0_OTHER_Handler ( void ); -void SERCOM1_0_Handler ( void ); -void SERCOM1_1_Handler ( void ); -void SERCOM1_2_Handler ( void ); -void SERCOM1_OTHER_Handler ( void ); -void SERCOM2_0_Handler ( void ); -void SERCOM2_1_Handler ( void ); -void SERCOM2_2_Handler ( void ); -void SERCOM2_OTHER_Handler ( void ); -void SERCOM3_0_Handler ( void ); -void SERCOM3_1_Handler ( void ); -void SERCOM3_2_Handler ( void ); -void SERCOM3_OTHER_Handler ( void ); -void SERCOM4_0_Handler ( void ); -void SERCOM4_1_Handler ( void ); -void SERCOM4_2_Handler ( void ); -void SERCOM4_OTHER_Handler ( void ); -void SERCOM5_0_Handler ( void ); -void SERCOM5_1_Handler ( void ); -void SERCOM5_2_Handler ( void ); -void SERCOM5_OTHER_Handler ( void ); -void SERCOM6_0_Handler ( void ); -void SERCOM6_1_Handler ( void ); -void SERCOM6_2_Handler ( void ); -void SERCOM6_OTHER_Handler ( void ); -void SERCOM7_0_Handler ( void ); -void SERCOM7_1_Handler ( void ); -void SERCOM7_2_Handler ( void ); -void SERCOM7_OTHER_Handler ( void ); -void CAN0_Handler ( void ); -void CAN1_Handler ( void ); -void USB_OTHER_Handler ( void ); -void USB_SOF_HSOF_Handler ( void ); -void USB_TRCPT0_Handler ( void ); -void USB_TRCPT1_Handler ( void ); -void GMAC_Handler ( void ); -void TCC0_OTHER_Handler ( void ); -void TCC0_MC0_Handler ( void ); -void TCC0_MC1_Handler ( void ); -void TCC0_MC2_Handler ( void ); -void TCC0_MC3_Handler ( void ); -void TCC0_MC4_Handler ( void ); -void TCC0_MC5_Handler ( void ); -void TCC1_OTHER_Handler ( void ); -void TCC1_MC0_Handler ( void ); -void TCC1_MC1_Handler ( void ); -void TCC1_MC2_Handler ( void ); -void TCC1_MC3_Handler ( void ); -void TCC2_OTHER_Handler ( void ); -void TCC2_MC0_Handler ( void ); -void TCC2_MC1_Handler ( void ); -void TCC2_MC2_Handler ( void ); -void TCC3_OTHER_Handler ( void ); -void TCC3_MC0_Handler ( void ); -void TCC3_MC1_Handler ( void ); -void TCC4_OTHER_Handler ( void ); -void TCC4_MC0_Handler ( void ); -void TCC4_MC1_Handler ( void ); -void TC0_Handler ( void ); -void TC1_Handler ( void ); -void TC2_Handler ( void ); -void TC3_Handler ( void ); -void TC4_Handler ( void ); -void TC5_Handler ( void ); -void TC6_Handler ( void ); -void TC7_Handler ( void ); -void PDEC_OTHER_Handler ( void ); -void PDEC_MC0_Handler ( void ); -void PDEC_MC1_Handler ( void ); -void ADC0_OTHER_Handler ( void ); -void ADC0_RESRDY_Handler ( void ); -void ADC1_OTHER_Handler ( void ); -void ADC1_RESRDY_Handler ( void ); -void AC_Handler ( void ); -void DAC_OTHER_Handler ( void ); -void DAC_EMPTY_0_Handler ( void ); -void DAC_EMPTY_1_Handler ( void ); -void DAC_RESRDY_0_Handler ( void ); -void DAC_RESRDY_1_Handler ( void ); -void I2S_Handler ( void ); -void PCC_Handler ( void ); -void AES_Handler ( void ); -void TRNG_Handler ( void ); -void ICM_Handler ( void ); -void PUKCC_Handler ( void ); -void QSPI_Handler ( void ); -void SDHC0_Handler ( void ); -void SDHC1_Handler ( void ); -#endif /* DONT_USE_PREDEFINED_PERIPHERALS_HANDLERS */ -/* Defines for Deprecated Interrupt and Exceptions handler names */ -#define MemManage_Handler MemoryManagement_Handler /**< \deprecated Backward compatibility*/ -#define DebugMon_Handler DebugMonitor_Handler /**< \deprecated Backward compatibility*/ -#define NMI_Handler NonMaskableInt_Handler /**< \deprecated Backward compatibility*/ -#define SVC_Handler SVCall_Handler /**< \deprecated Backward compatibility*/ - -#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/* - * \brief Configuration of the CORTEX-M4 Processor and Core Peripherals - */ -#define __CM4_REV 0x0001 /**< Cortex-M4 Core Revision */ -#define __DEBUG_LVL 3 /**< Debug Level */ -#define __FPU_PRESENT 1 /**< FPU present or not */ -#define __MPU_PRESENT 1 /**< MPU present or not */ -#define __NVIC_PRIO_BITS 3 /**< Number of Bits used for Priority Levels */ -#define __TRACE_LVL 2 /**< Trace Level */ -#define __VTOR_PRESENT 1 /**< Vector Table Offset Register present or not */ -#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */ -#define __ARCH_ARM 1 -#define __ARCH_ARM_CORTEX_M 1 -#define __DEVICE_IS_SAM 1 - -/* - * \brief CMSIS includes - */ -#include "core_cm4.h" -#if defined USE_CMSIS_INIT -#include "system_same54.h" -#endif /* USE_CMSIS_INIT */ - -/** \defgroup SAME54P19A_api Peripheral Software API - * @{ - */ - -/* ************************************************************************** */ -/** SOFTWARE PERIPHERAL API DEFINITION FOR SAME54P19A */ -/* ************************************************************************** */ -#include "component/ac.h" -#include "component/adc.h" -#include "component/aes.h" -#include "component/can.h" -#include "component/ccl.h" -#include "component/cmcc.h" -#include "component/dac.h" -#include "component/dmac.h" -#include "component/dsu.h" -#include "component/eic.h" -#include "component/evsys.h" -#include "component/freqm.h" -#include "component/gclk.h" -#include "component/gmac.h" -#include "component/hmatrixb.h" -#include "component/i2s.h" -#include "component/icm.h" -#include "component/mclk.h" -#include "component/nvmctrl.h" -#include "component/osc32kctrl.h" -#include "component/oscctrl.h" -#include "component/pac.h" -#include "component/pcc.h" -#include "component/pdec.h" -#include "component/pm.h" -#include "component/port.h" -#include "component/pukcc.h" -#include "component/qspi.h" -#include "component/ramecc.h" -#include "component/rstc.h" -#include "component/rtc.h" -#include "component/sdhc.h" -#include "component/sercom.h" -#include "component/supc.h" -#include "component/tc.h" -#include "component/tcc.h" -#include "component/trng.h" -#include "component/usb.h" -#include "component/wdt.h" -/** @} end of Peripheral Software API */ - -/** \addtogroup SAME54P19A_id Peripheral Ids Definitions - * @{ - */ - -/* ************************************************************************** */ -/* PERIPHERAL ID DEFINITIONS FOR SAME54P19A */ -/* ************************************************************************** */ -#define ID_PAC ( 0) /**< \brief Peripheral Access Controller (PAC) */ -#define ID_PM ( 1) /**< \brief Power Manager (PM) */ -#define ID_MCLK ( 2) /**< \brief Main Clock (MCLK) */ -#define ID_RSTC ( 3) /**< \brief Reset Controller (RSTC) */ -#define ID_OSCCTRL ( 4) /**< \brief Oscillators Control (OSCCTRL) */ -#define ID_OSC32KCTRL ( 5) /**< \brief 32kHz Oscillators Control (OSC32KCTRL) */ -#define ID_SUPC ( 6) /**< \brief Supply Controller (SUPC) */ -#define ID_GCLK ( 7) /**< \brief Generic Clock Generator (GCLK) */ -#define ID_WDT ( 8) /**< \brief Watchdog Timer (WDT) */ -#define ID_RTC ( 9) /**< \brief Real-Time Counter (RTC) */ -#define ID_EIC ( 10) /**< \brief External Interrupt Controller (EIC) */ -#define ID_FREQM ( 11) /**< \brief Frequency Meter (FREQM) */ -#define ID_SERCOM0 ( 12) /**< \brief Serial Communication Interface (SERCOM0) */ -#define ID_SERCOM1 ( 13) /**< \brief Serial Communication Interface (SERCOM1) */ -#define ID_TC0 ( 14) /**< \brief Basic Timer Counter (TC0) */ -#define ID_TC1 ( 15) /**< \brief Basic Timer Counter (TC1) */ -#define ID_USB ( 32) /**< \brief Universal Serial Bus (USB) */ -#define ID_DSU ( 33) /**< \brief Device Service Unit (DSU) */ -#define ID_NVMCTRL ( 34) /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ -#define ID_CMCC ( 35) /**< \brief Cortex M Cache Controller (CMCC) */ -#define ID_PORT ( 36) /**< \brief Port Module (PORT) */ -#define ID_DMAC ( 37) /**< \brief Direct Memory Access Controller (DMAC) */ -#define ID_HMATRIX ( 38) /**< \brief HSB Matrix (HMATRIX) */ -#define ID_EVSYS ( 39) /**< \brief Event System Interface (EVSYS) */ -#define ID_SERCOM2 ( 41) /**< \brief Serial Communication Interface (SERCOM2) */ -#define ID_SERCOM3 ( 42) /**< \brief Serial Communication Interface (SERCOM3) */ -#define ID_TCC0 ( 43) /**< \brief Timer Counter Control (TCC0) */ -#define ID_TCC1 ( 44) /**< \brief Timer Counter Control (TCC1) */ -#define ID_TC2 ( 45) /**< \brief Basic Timer Counter (TC2) */ -#define ID_TC3 ( 46) /**< \brief Basic Timer Counter (TC3) */ -#define ID_RAMECC ( 48) /**< \brief RAM ECC (RAMECC) */ -#define ID_CAN0 ( 64) /**< \brief Control Area Network (CAN0) */ -#define ID_CAN1 ( 65) /**< \brief Control Area Network (CAN1) */ -#define ID_GMAC ( 66) /**< \brief Ethernet MAC (GMAC) */ -#define ID_TCC2 ( 67) /**< \brief Timer Counter Control (TCC2) */ -#define ID_TCC3 ( 68) /**< \brief Timer Counter Control (TCC3) */ -#define ID_TC4 ( 69) /**< \brief Basic Timer Counter (TC4) */ -#define ID_TC5 ( 70) /**< \brief Basic Timer Counter (TC5) */ -#define ID_PDEC ( 71) /**< \brief Quadrature Decodeur (PDEC) */ -#define ID_AC ( 72) /**< \brief Analog Comparators (AC) */ -#define ID_AES ( 73) /**< \brief Advanced Encryption Standard (AES) */ -#define ID_TRNG ( 74) /**< \brief True Random Generator (TRNG) */ -#define ID_ICM ( 75) /**< \brief Integrity Check Monitor (ICM) */ -#define ID_PUKCC ( 76) /**< \brief PUblic-Key Cryptography Controller (PUKCC) */ -#define ID_QSPI ( 77) /**< \brief Quad SPI interface (QSPI) */ -#define ID_CCL ( 78) /**< \brief Configurable Custom Logic (CCL) */ -#define ID_SERCOM4 ( 96) /**< \brief Serial Communication Interface (SERCOM4) */ -#define ID_SERCOM5 ( 97) /**< \brief Serial Communication Interface (SERCOM5) */ -#define ID_SERCOM6 ( 98) /**< \brief Serial Communication Interface (SERCOM6) */ -#define ID_SERCOM7 ( 99) /**< \brief Serial Communication Interface (SERCOM7) */ -#define ID_TCC4 (100) /**< \brief Timer Counter Control (TCC4) */ -#define ID_TC6 (101) /**< \brief Basic Timer Counter (TC6) */ -#define ID_TC7 (102) /**< \brief Basic Timer Counter (TC7) */ -#define ID_ADC0 (103) /**< \brief Analog Digital Converter (ADC0) */ -#define ID_ADC1 (104) /**< \brief Analog Digital Converter (ADC1) */ -#define ID_DAC (105) /**< \brief Digital-to-Analog Converter (DAC) */ -#define ID_I2S (106) /**< \brief Inter-IC Sound Interface (I2S) */ -#define ID_PCC (107) /**< \brief Parallel Capture Controller (PCC) */ - -#define ID_PERIPH_MAX (107) /**< \brief Number of peripheral IDs */ -/** @} end of Peripheral Ids Definitions */ - -/** \addtogroup SAME54P19A_base Peripheral Base Address Definitions - * @{ - */ - -/* ************************************************************************** */ -/* REGISTER STRUCTURE ADDRESS DEFINITIONS FOR SAME54P19A */ -/* ************************************************************************** */ -#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) -#define AC_REGS ((ac_registers_t*)0x42002000) /**< \brief AC Registers Address */ -#define ADC0_REGS ((adc_registers_t*)0x43001c00) /**< \brief ADC0 Registers Address */ -#define ADC1_REGS ((adc_registers_t*)0x43002000) /**< \brief ADC1 Registers Address */ -#define AES_REGS ((aes_registers_t*)0x42002400) /**< \brief AES Registers Address */ -#define CAN0_REGS ((can_registers_t*)0x42000000) /**< \brief CAN0 Registers Address */ -#define CAN1_REGS ((can_registers_t*)0x42000400) /**< \brief CAN1 Registers Address */ -#define CCL_REGS ((ccl_registers_t*)0x42003800) /**< \brief CCL Registers Address */ -#define CMCC_REGS ((cmcc_registers_t*)0x41006000) /**< \brief CMCC Registers Address */ -#define DAC_REGS ((dac_registers_t*)0x43002400) /**< \brief DAC Registers Address */ -#define DMAC_REGS ((dmac_registers_t*)0x4100a000) /**< \brief DMAC Registers Address */ -#define DSU_REGS ((dsu_registers_t*)0x41002000) /**< \brief DSU Registers Address */ -#define EIC_REGS ((eic_registers_t*)0x40002800) /**< \brief EIC Registers Address */ -#define EVSYS_REGS ((evsys_registers_t*)0x4100e000) /**< \brief EVSYS Registers Address */ -#define FREQM_REGS ((freqm_registers_t*)0x40002c00) /**< \brief FREQM Registers Address */ -#define GCLK_REGS ((gclk_registers_t*)0x40001c00) /**< \brief GCLK Registers Address */ -#define GMAC_REGS ((gmac_registers_t*)0x42000800) /**< \brief GMAC Registers Address */ -#define HMATRIX_REGS ((hmatrixb_registers_t*)0x4100c000) /**< \brief HMATRIX Registers Address */ -#define ICM_REGS ((icm_registers_t*)0x42002c00) /**< \brief ICM Registers Address */ -#define I2S_REGS ((i2s_registers_t*)0x43002800) /**< \brief I2S Registers Address */ -#define MCLK_REGS ((mclk_registers_t*)0x40000800) /**< \brief MCLK Registers Address */ -#define NVMCTRL_REGS ((nvmctrl_registers_t*)0x41004000) /**< \brief NVMCTRL Registers Address */ -#define OSCCTRL_REGS ((oscctrl_registers_t*)0x40001000) /**< \brief OSCCTRL Registers Address */ -#define OSC32KCTRL_REGS ((osc32kctrl_registers_t*)0x40001400) /**< \brief OSC32KCTRL Registers Address */ -#define PAC_REGS ((pac_registers_t*)0x40000000) /**< \brief PAC Registers Address */ -#define PCC_REGS ((pcc_registers_t*)0x43002c00) /**< \brief PCC Registers Address */ -#define PDEC_REGS ((pdec_registers_t*)0x42001c00) /**< \brief PDEC Registers Address */ -#define PM_REGS ((pm_registers_t*)0x40000400) /**< \brief PM Registers Address */ -#define PORT_REGS ((port_registers_t*)0x41008000) /**< \brief PORT Registers Address */ -#define QSPI_REGS ((qspi_registers_t*)0x42003400) /**< \brief QSPI Registers Address */ -#define RAMECC_REGS ((ramecc_registers_t*)0x41020000) /**< \brief RAMECC Registers Address */ -#define RSTC_REGS ((rstc_registers_t*)0x40000c00) /**< \brief RSTC Registers Address */ -#define RTC_REGS ((rtc_registers_t*)0x40002400) /**< \brief RTC Registers Address */ -#define SDHC0_REGS ((sdhc_registers_t*)0x45000000) /**< \brief SDHC0 Registers Address */ -#define SDHC1_REGS ((sdhc_registers_t*)0x46000000) /**< \brief SDHC1 Registers Address */ -#define SERCOM0_REGS ((sercom_registers_t*)0x40003000) /**< \brief SERCOM0 Registers Address */ -#define SERCOM1_REGS ((sercom_registers_t*)0x40003400) /**< \brief SERCOM1 Registers Address */ -#define SERCOM2_REGS ((sercom_registers_t*)0x41012000) /**< \brief SERCOM2 Registers Address */ -#define SERCOM3_REGS ((sercom_registers_t*)0x41014000) /**< \brief SERCOM3 Registers Address */ -#define SERCOM4_REGS ((sercom_registers_t*)0x43000000) /**< \brief SERCOM4 Registers Address */ -#define SERCOM5_REGS ((sercom_registers_t*)0x43000400) /**< \brief SERCOM5 Registers Address */ -#define SERCOM6_REGS ((sercom_registers_t*)0x43000800) /**< \brief SERCOM6 Registers Address */ -#define SERCOM7_REGS ((sercom_registers_t*)0x43000c00) /**< \brief SERCOM7 Registers Address */ -#define SUPC_REGS ((supc_registers_t*)0x40001800) /**< \brief SUPC Registers Address */ -#define TC0_REGS ((tc_registers_t*)0x40003800) /**< \brief TC0 Registers Address */ -#define TC1_REGS ((tc_registers_t*)0x40003c00) /**< \brief TC1 Registers Address */ -#define TC2_REGS ((tc_registers_t*)0x4101a000) /**< \brief TC2 Registers Address */ -#define TC3_REGS ((tc_registers_t*)0x4101c000) /**< \brief TC3 Registers Address */ -#define TC4_REGS ((tc_registers_t*)0x42001400) /**< \brief TC4 Registers Address */ -#define TC5_REGS ((tc_registers_t*)0x42001800) /**< \brief TC5 Registers Address */ -#define TC6_REGS ((tc_registers_t*)0x43001400) /**< \brief TC6 Registers Address */ -#define TC7_REGS ((tc_registers_t*)0x43001800) /**< \brief TC7 Registers Address */ -#define TCC0_REGS ((tcc_registers_t*)0x41016000) /**< \brief TCC0 Registers Address */ -#define TCC1_REGS ((tcc_registers_t*)0x41018000) /**< \brief TCC1 Registers Address */ -#define TCC2_REGS ((tcc_registers_t*)0x42000c00) /**< \brief TCC2 Registers Address */ -#define TCC3_REGS ((tcc_registers_t*)0x42001000) /**< \brief TCC3 Registers Address */ -#define TCC4_REGS ((tcc_registers_t*)0x43001000) /**< \brief TCC4 Registers Address */ -#define TRNG_REGS ((trng_registers_t*)0x42002800) /**< \brief TRNG Registers Address */ -#define USB_REGS ((usb_registers_t*)0x41000000) /**< \brief USB Registers Address */ -#define WDT_REGS ((wdt_registers_t*)0x40002000) /**< \brief WDT Registers Address */ -#endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ -/** @} end of Peripheral Base Address Definitions */ - -/** \addtogroup SAME54P19A_base Peripheral Base Address Definitions - * @{ - */ - -/* ************************************************************************** */ -/* BASE ADDRESS DEFINITIONS FOR SAME54P19A */ -/* ************************************************************************** */ -#define AC_BASE_ADDRESS _UL_(0x42002000) /**< \brief AC Base Address */ -#define ADC0_BASE_ADDRESS _UL_(0x43001c00) /**< \brief ADC0 Base Address */ -#define ADC1_BASE_ADDRESS _UL_(0x43002000) /**< \brief ADC1 Base Address */ -#define AES_BASE_ADDRESS _UL_(0x42002400) /**< \brief AES Base Address */ -#define CAN0_BASE_ADDRESS _UL_(0x42000000) /**< \brief CAN0 Base Address */ -#define CAN1_BASE_ADDRESS _UL_(0x42000400) /**< \brief CAN1 Base Address */ -#define CCL_BASE_ADDRESS _UL_(0x42003800) /**< \brief CCL Base Address */ -#define CMCC_BASE_ADDRESS _UL_(0x41006000) /**< \brief CMCC Base Address */ -#define DAC_BASE_ADDRESS _UL_(0x43002400) /**< \brief DAC Base Address */ -#define DMAC_BASE_ADDRESS _UL_(0x4100a000) /**< \brief DMAC Base Address */ -#define DSU_BASE_ADDRESS _UL_(0x41002000) /**< \brief DSU Base Address */ -#define EIC_BASE_ADDRESS _UL_(0x40002800) /**< \brief EIC Base Address */ -#define EVSYS_BASE_ADDRESS _UL_(0x4100e000) /**< \brief EVSYS Base Address */ -#define FREQM_BASE_ADDRESS _UL_(0x40002c00) /**< \brief FREQM Base Address */ -#define GCLK_BASE_ADDRESS _UL_(0x40001c00) /**< \brief GCLK Base Address */ -#define GMAC_BASE_ADDRESS _UL_(0x42000800) /**< \brief GMAC Base Address */ -#define HMATRIX_BASE_ADDRESS _UL_(0x4100c000) /**< \brief HMATRIX Base Address */ -#define ICM_BASE_ADDRESS _UL_(0x42002c00) /**< \brief ICM Base Address */ -#define I2S_BASE_ADDRESS _UL_(0x43002800) /**< \brief I2S Base Address */ -#define MCLK_BASE_ADDRESS _UL_(0x40000800) /**< \brief MCLK Base Address */ -#define NVMCTRL_BASE_ADDRESS _UL_(0x41004000) /**< \brief NVMCTRL Base Address */ -#define OSCCTRL_BASE_ADDRESS _UL_(0x40001000) /**< \brief OSCCTRL Base Address */ -#define OSC32KCTRL_BASE_ADDRESS _UL_(0x40001400) /**< \brief OSC32KCTRL Base Address */ -#define PAC_BASE_ADDRESS _UL_(0x40000000) /**< \brief PAC Base Address */ -#define PCC_BASE_ADDRESS _UL_(0x43002c00) /**< \brief PCC Base Address */ -#define PDEC_BASE_ADDRESS _UL_(0x42001c00) /**< \brief PDEC Base Address */ -#define PM_BASE_ADDRESS _UL_(0x40000400) /**< \brief PM Base Address */ -#define PORT_BASE_ADDRESS _UL_(0x41008000) /**< \brief PORT Base Address */ -#define QSPI_BASE_ADDRESS _UL_(0x42003400) /**< \brief QSPI Base Address */ -#define RAMECC_BASE_ADDRESS _UL_(0x41020000) /**< \brief RAMECC Base Address */ -#define RSTC_BASE_ADDRESS _UL_(0x40000c00) /**< \brief RSTC Base Address */ -#define RTC_BASE_ADDRESS _UL_(0x40002400) /**< \brief RTC Base Address */ -#define SDHC0_BASE_ADDRESS _UL_(0x45000000) /**< \brief SDHC0 Base Address */ -#define SDHC1_BASE_ADDRESS _UL_(0x46000000) /**< \brief SDHC1 Base Address */ -#define SERCOM0_BASE_ADDRESS _UL_(0x40003000) /**< \brief SERCOM0 Base Address */ -#define SERCOM1_BASE_ADDRESS _UL_(0x40003400) /**< \brief SERCOM1 Base Address */ -#define SERCOM2_BASE_ADDRESS _UL_(0x41012000) /**< \brief SERCOM2 Base Address */ -#define SERCOM3_BASE_ADDRESS _UL_(0x41014000) /**< \brief SERCOM3 Base Address */ -#define SERCOM4_BASE_ADDRESS _UL_(0x43000000) /**< \brief SERCOM4 Base Address */ -#define SERCOM5_BASE_ADDRESS _UL_(0x43000400) /**< \brief SERCOM5 Base Address */ -#define SERCOM6_BASE_ADDRESS _UL_(0x43000800) /**< \brief SERCOM6 Base Address */ -#define SERCOM7_BASE_ADDRESS _UL_(0x43000c00) /**< \brief SERCOM7 Base Address */ -#define SUPC_BASE_ADDRESS _UL_(0x40001800) /**< \brief SUPC Base Address */ -#define TC0_BASE_ADDRESS _UL_(0x40003800) /**< \brief TC0 Base Address */ -#define TC1_BASE_ADDRESS _UL_(0x40003c00) /**< \brief TC1 Base Address */ -#define TC2_BASE_ADDRESS _UL_(0x4101a000) /**< \brief TC2 Base Address */ -#define TC3_BASE_ADDRESS _UL_(0x4101c000) /**< \brief TC3 Base Address */ -#define TC4_BASE_ADDRESS _UL_(0x42001400) /**< \brief TC4 Base Address */ -#define TC5_BASE_ADDRESS _UL_(0x42001800) /**< \brief TC5 Base Address */ -#define TC6_BASE_ADDRESS _UL_(0x43001400) /**< \brief TC6 Base Address */ -#define TC7_BASE_ADDRESS _UL_(0x43001800) /**< \brief TC7 Base Address */ -#define TCC0_BASE_ADDRESS _UL_(0x41016000) /**< \brief TCC0 Base Address */ -#define TCC1_BASE_ADDRESS _UL_(0x41018000) /**< \brief TCC1 Base Address */ -#define TCC2_BASE_ADDRESS _UL_(0x42000c00) /**< \brief TCC2 Base Address */ -#define TCC3_BASE_ADDRESS _UL_(0x42001000) /**< \brief TCC3 Base Address */ -#define TCC4_BASE_ADDRESS _UL_(0x43001000) /**< \brief TCC4 Base Address */ -#define TRNG_BASE_ADDRESS _UL_(0x42002800) /**< \brief TRNG Base Address */ -#define USB_BASE_ADDRESS _UL_(0x41000000) /**< \brief USB Base Address */ -#define WDT_BASE_ADDRESS _UL_(0x40002000) /**< \brief WDT Base Address */ -/** @} end of Peripheral Base Address Definitions */ - -/** \addtogroup SAME54P19A_pio Peripheral Pio Definitions - * @{ - */ - -/* ************************************************************************** */ -/* PIO DEFINITIONS FOR SAME54P19A */ -/* ************************************************************************** */ -#include "pio/same54p19a.h" -/** @} end of Peripheral Pio Definitions */ - -/* ************************************************************************** */ -/* MEMORY MAPPING DEFINITIONS FOR SAME54P19A */ -/* ************************************************************************** */ - -#define FLASH_SIZE _UL_(0x00080000) /* 512kB Memory segment type: flash */ -#define FLASH_PAGE_SIZE _UL_( 512) -#define FLASH_NB_OF_PAGES _UL_( 1024) - -#define SW0_SIZE _UL_(0x00000010) /* 0kB Memory segment type: fuses */ -#define TEMP_LOG_SIZE _UL_(0x00000200) /* 0kB Memory segment type: fuses */ -#define TEMP_LOG_PAGE_SIZE _UL_( 512) -#define TEMP_LOG_NB_OF_PAGES _UL_( 1) - -#define USER_PAGE_SIZE _UL_(0x00000200) /* 0kB Memory segment type: user_page */ -#define USER_PAGE_PAGE_SIZE _UL_( 512) -#define USER_PAGE_NB_OF_PAGES _UL_( 1) - -#define CMCC_SIZE _UL_(0x01000000) /* 16384kB Memory segment type: io */ -#define CMCC_DATARAM_SIZE _UL_(0x00001000) /* 4kB Memory segment type: io */ -#define CMCC_TAGRAM_SIZE _UL_(0x00000400) /* 1kB Memory segment type: io */ -#define CMCC_VALIDRAM_SIZE _UL_(0x00000040) /* 0kB Memory segment type: io */ -#define QSPI_SIZE _UL_(0x01000000) /* 16384kB Memory segment type: other */ -#define HSRAM_SIZE _UL_(0x00030000) /* 192kB Memory segment type: ram */ -#define HSRAM_ETB_SIZE _UL_(0x00008000) /* 32kB Memory segment type: ram */ -#define HSRAM_RET1_SIZE _UL_(0x00008000) /* 32kB Memory segment type: ram */ -#define HPB0_SIZE _UL_(0x00004400) /* 17kB Memory segment type: io */ -#define HPB1_SIZE _UL_(0x00022000) /* 136kB Memory segment type: io */ -#define HPB2_SIZE _UL_(0x00003c00) /* 15kB Memory segment type: io */ -#define HPB3_SIZE _UL_(0x00003000) /* 12kB Memory segment type: io */ -#define SEEPROM_SIZE _UL_(0x00020000) /* 128kB Memory segment type: io */ -#define SDHC0_SIZE _UL_(0x00000c00) /* 3kB Memory segment type: io */ -#define SDHC1_SIZE _UL_(0x00000c00) /* 3kB Memory segment type: io */ -#define BKUPRAM_SIZE _UL_(0x00002000) /* 8kB Memory segment type: ram */ -#define PPB_SIZE _UL_(0x00100000) /* 1024kB Memory segment type: io */ -#define SCS_SIZE _UL_(0x00001000) /* 4kB Memory segment type: io */ - -#define FLASH_ADDR _UL_(0x00000000) /**< FLASH base address (type: flash)*/ -#define SW0_ADDR _UL_(0x00800080) /**< SW0 base address (type: fuses)*/ -#define TEMP_LOG_ADDR _UL_(0x00800100) /**< TEMP_LOG base address (type: fuses)*/ -#define USER_PAGE_ADDR _UL_(0x00804000) /**< USER_PAGE base address (type: user_page)*/ -#define CMCC_ADDR _UL_(0x03000000) /**< CMCC base address (type: io)*/ -#define CMCC_DATARAM_ADDR _UL_(0x03000000) /**< CMCC_DATARAM base address (type: io)*/ -#define CMCC_TAGRAM_ADDR _UL_(0x03001000) /**< CMCC_TAGRAM base address (type: io)*/ -#define CMCC_VALIDRAM_ADDR _UL_(0x03002000) /**< CMCC_VALIDRAM base address (type: io)*/ -#define QSPI_ADDR _UL_(0x04000000) /**< QSPI base address (type: other)*/ -#define HSRAM_ADDR _UL_(0x20000000) /**< HSRAM base address (type: ram)*/ -#define HSRAM_ETB_ADDR _UL_(0x20000000) /**< HSRAM_ETB base address (type: ram)*/ -#define HSRAM_RET1_ADDR _UL_(0x20000000) /**< HSRAM_RET1 base address (type: ram)*/ -#define HPB0_ADDR _UL_(0x40000000) /**< HPB0 base address (type: io)*/ -#define HPB1_ADDR _UL_(0x41000000) /**< HPB1 base address (type: io)*/ -#define HPB2_ADDR _UL_(0x42000000) /**< HPB2 base address (type: io)*/ -#define HPB3_ADDR _UL_(0x43000000) /**< HPB3 base address (type: io)*/ -#define SEEPROM_ADDR _UL_(0x44000000) /**< SEEPROM base address (type: io)*/ -#define SDHC0_ADDR _UL_(0x45000000) /**< SDHC0 base address (type: io)*/ -#define SDHC1_ADDR _UL_(0x46000000) /**< SDHC1 base address (type: io)*/ -#define BKUPRAM_ADDR _UL_(0x47000000) /**< BKUPRAM base address (type: ram)*/ -#define PPB_ADDR _UL_(0xe0000000) /**< PPB base address (type: io)*/ -#define SCS_ADDR _UL_(0xe000e000) /**< SCS base address (type: io)*/ - -/* ************************************************************************** */ -/** DEVICE SIGNATURES FOR SAME54P19A */ -/* ************************************************************************** */ -#define CHIP_DSU_DID _UL_(0X61840301) - -/* ************************************************************************** */ -/** ELECTRICAL DEFINITIONS FOR SAME54P19A */ -/* ************************************************************************** */ - -/* ************************************************************************** */ -/** Event Generator IDs for SAME54P19A */ -/* ************************************************************************** */ -#define EVENT_ID_GEN_OSCCTRL_XOSC_FAIL_0 1 /**< ID for OSCCTRL event generator XOSC_FAIL_0 */ -#define EVENT_ID_GEN_OSCCTRL_XOSC_FAIL_1 2 /**< ID for OSCCTRL event generator XOSC_FAIL_1 */ -#define EVENT_ID_GEN_OSC32KCTRL_XOSC32K_FAIL 3 /**< ID for OSC32KCTRL event generator XOSC32K_FAIL */ -#define EVENT_ID_GEN_RTC_PER_0 4 /**< ID for RTC event generator PER_0 */ -#define EVENT_ID_GEN_RTC_PER_1 5 /**< ID for RTC event generator PER_1 */ -#define EVENT_ID_GEN_RTC_PER_2 6 /**< ID for RTC event generator PER_2 */ -#define EVENT_ID_GEN_RTC_PER_3 7 /**< ID for RTC event generator PER_3 */ -#define EVENT_ID_GEN_RTC_PER_4 8 /**< ID for RTC event generator PER_4 */ -#define EVENT_ID_GEN_RTC_PER_5 9 /**< ID for RTC event generator PER_5 */ -#define EVENT_ID_GEN_RTC_PER_6 10 /**< ID for RTC event generator PER_6 */ -#define EVENT_ID_GEN_RTC_PER_7 11 /**< ID for RTC event generator PER_7 */ -#define EVENT_ID_GEN_RTC_CMP_0 12 /**< ID for RTC event generator CMP_0 */ -#define EVENT_ID_GEN_RTC_CMP_1 13 /**< ID for RTC event generator CMP_1 */ -#define EVENT_ID_GEN_RTC_CMP_2 14 /**< ID for RTC event generator CMP_2 */ -#define EVENT_ID_GEN_RTC_CMP_3 15 /**< ID for RTC event generator CMP_3 */ -#define EVENT_ID_GEN_RTC_TAMPER 16 /**< ID for RTC event generator TAMPER */ -#define EVENT_ID_GEN_RTC_OVF 17 /**< ID for RTC event generator OVF */ -#define EVENT_ID_GEN_EIC_EXTINT_0 18 /**< ID for EIC event generator EXTINT_0 */ -#define EVENT_ID_GEN_EIC_EXTINT_1 19 /**< ID for EIC event generator EXTINT_1 */ -#define EVENT_ID_GEN_EIC_EXTINT_2 20 /**< ID for EIC event generator EXTINT_2 */ -#define EVENT_ID_GEN_EIC_EXTINT_3 21 /**< ID for EIC event generator EXTINT_3 */ -#define EVENT_ID_GEN_EIC_EXTINT_4 22 /**< ID for EIC event generator EXTINT_4 */ -#define EVENT_ID_GEN_EIC_EXTINT_5 23 /**< ID for EIC event generator EXTINT_5 */ -#define EVENT_ID_GEN_EIC_EXTINT_6 24 /**< ID for EIC event generator EXTINT_6 */ -#define EVENT_ID_GEN_EIC_EXTINT_7 25 /**< ID for EIC event generator EXTINT_7 */ -#define EVENT_ID_GEN_EIC_EXTINT_8 26 /**< ID for EIC event generator EXTINT_8 */ -#define EVENT_ID_GEN_EIC_EXTINT_9 27 /**< ID for EIC event generator EXTINT_9 */ -#define EVENT_ID_GEN_EIC_EXTINT_10 28 /**< ID for EIC event generator EXTINT_10 */ -#define EVENT_ID_GEN_EIC_EXTINT_11 29 /**< ID for EIC event generator EXTINT_11 */ -#define EVENT_ID_GEN_EIC_EXTINT_12 30 /**< ID for EIC event generator EXTINT_12 */ -#define EVENT_ID_GEN_EIC_EXTINT_13 31 /**< ID for EIC event generator EXTINT_13 */ -#define EVENT_ID_GEN_EIC_EXTINT_14 32 /**< ID for EIC event generator EXTINT_14 */ -#define EVENT_ID_GEN_EIC_EXTINT_15 33 /**< ID for EIC event generator EXTINT_15 */ -#define EVENT_ID_GEN_DMAC_CH_0 34 /**< ID for DMAC event generator CH_0 */ -#define EVENT_ID_GEN_DMAC_CH_1 35 /**< ID for DMAC event generator CH_1 */ -#define EVENT_ID_GEN_DMAC_CH_2 36 /**< ID for DMAC event generator CH_2 */ -#define EVENT_ID_GEN_DMAC_CH_3 37 /**< ID for DMAC event generator CH_3 */ -#define EVENT_ID_GEN_PAC_ACCERR 38 /**< ID for PAC event generator ACCERR */ -#define EVENT_ID_GEN_TCC0_OVF 41 /**< ID for TCC0 event generator OVF */ -#define EVENT_ID_GEN_TCC0_TRG 42 /**< ID for TCC0 event generator TRG */ -#define EVENT_ID_GEN_TCC0_CNT 43 /**< ID for TCC0 event generator CNT */ -#define EVENT_ID_GEN_TCC0_MC_0 44 /**< ID for TCC0 event generator MC_0 */ -#define EVENT_ID_GEN_TCC0_MC_1 45 /**< ID for TCC0 event generator MC_1 */ -#define EVENT_ID_GEN_TCC0_MC_2 46 /**< ID for TCC0 event generator MC_2 */ -#define EVENT_ID_GEN_TCC0_MC_3 47 /**< ID for TCC0 event generator MC_3 */ -#define EVENT_ID_GEN_TCC0_MC_4 48 /**< ID for TCC0 event generator MC_4 */ -#define EVENT_ID_GEN_TCC0_MC_5 49 /**< ID for TCC0 event generator MC_5 */ -#define EVENT_ID_GEN_TCC1_OVF 50 /**< ID for TCC1 event generator OVF */ -#define EVENT_ID_GEN_TCC1_TRG 51 /**< ID for TCC1 event generator TRG */ -#define EVENT_ID_GEN_TCC1_CNT 52 /**< ID for TCC1 event generator CNT */ -#define EVENT_ID_GEN_TCC1_MC_0 53 /**< ID for TCC1 event generator MC_0 */ -#define EVENT_ID_GEN_TCC1_MC_1 54 /**< ID for TCC1 event generator MC_1 */ -#define EVENT_ID_GEN_TCC1_MC_2 55 /**< ID for TCC1 event generator MC_2 */ -#define EVENT_ID_GEN_TCC1_MC_3 56 /**< ID for TCC1 event generator MC_3 */ -#define EVENT_ID_GEN_TCC2_OVF 57 /**< ID for TCC2 event generator OVF */ -#define EVENT_ID_GEN_TCC2_TRG 58 /**< ID for TCC2 event generator TRG */ -#define EVENT_ID_GEN_TCC2_CNT 59 /**< ID for TCC2 event generator CNT */ -#define EVENT_ID_GEN_TCC2_MC_0 60 /**< ID for TCC2 event generator MC_0 */ -#define EVENT_ID_GEN_TCC2_MC_1 61 /**< ID for TCC2 event generator MC_1 */ -#define EVENT_ID_GEN_TCC2_MC_2 62 /**< ID for TCC2 event generator MC_2 */ -#define EVENT_ID_GEN_TCC3_OVF 63 /**< ID for TCC3 event generator OVF */ -#define EVENT_ID_GEN_TCC3_TRG 64 /**< ID for TCC3 event generator TRG */ -#define EVENT_ID_GEN_TCC3_CNT 65 /**< ID for TCC3 event generator CNT */ -#define EVENT_ID_GEN_TCC3_MC_0 66 /**< ID for TCC3 event generator MC_0 */ -#define EVENT_ID_GEN_TCC3_MC_1 67 /**< ID for TCC3 event generator MC_1 */ -#define EVENT_ID_GEN_TCC4_OVF 68 /**< ID for TCC4 event generator OVF */ -#define EVENT_ID_GEN_TCC4_TRG 69 /**< ID for TCC4 event generator TRG */ -#define EVENT_ID_GEN_TCC4_CNT 70 /**< ID for TCC4 event generator CNT */ -#define EVENT_ID_GEN_TCC4_MC_0 71 /**< ID for TCC4 event generator MC_0 */ -#define EVENT_ID_GEN_TCC4_MC_1 72 /**< ID for TCC4 event generator MC_1 */ -#define EVENT_ID_GEN_TC0_OVF 73 /**< ID for TC0 event generator OVF */ -#define EVENT_ID_GEN_TC0_MC_0 74 /**< ID for TC0 event generator MC_0 */ -#define EVENT_ID_GEN_TC0_MC_1 75 /**< ID for TC0 event generator MC_1 */ -#define EVENT_ID_GEN_TC1_OVF 76 /**< ID for TC1 event generator OVF */ -#define EVENT_ID_GEN_TC1_MC_0 77 /**< ID for TC1 event generator MC_0 */ -#define EVENT_ID_GEN_TC1_MC_1 78 /**< ID for TC1 event generator MC_1 */ -#define EVENT_ID_GEN_TC2_OVF 79 /**< ID for TC2 event generator OVF */ -#define EVENT_ID_GEN_TC2_MC_0 80 /**< ID for TC2 event generator MC_0 */ -#define EVENT_ID_GEN_TC2_MC_1 81 /**< ID for TC2 event generator MC_1 */ -#define EVENT_ID_GEN_TC3_OVF 82 /**< ID for TC3 event generator OVF */ -#define EVENT_ID_GEN_TC3_MC_0 83 /**< ID for TC3 event generator MC_0 */ -#define EVENT_ID_GEN_TC3_MC_1 84 /**< ID for TC3 event generator MC_1 */ -#define EVENT_ID_GEN_TC4_OVF 85 /**< ID for TC4 event generator OVF */ -#define EVENT_ID_GEN_TC4_MC_0 86 /**< ID for TC4 event generator MC_0 */ -#define EVENT_ID_GEN_TC4_MC_1 87 /**< ID for TC4 event generator MC_1 */ -#define EVENT_ID_GEN_TC5_OVF 88 /**< ID for TC5 event generator OVF */ -#define EVENT_ID_GEN_TC5_MC_0 89 /**< ID for TC5 event generator MC_0 */ -#define EVENT_ID_GEN_TC5_MC_1 90 /**< ID for TC5 event generator MC_1 */ -#define EVENT_ID_GEN_TC6_OVF 91 /**< ID for TC6 event generator OVF */ -#define EVENT_ID_GEN_TC6_MC_0 92 /**< ID for TC6 event generator MC_0 */ -#define EVENT_ID_GEN_TC6_MC_1 93 /**< ID for TC6 event generator MC_1 */ -#define EVENT_ID_GEN_TC7_OVF 94 /**< ID for TC7 event generator OVF */ -#define EVENT_ID_GEN_TC7_MC_0 95 /**< ID for TC7 event generator MC_0 */ -#define EVENT_ID_GEN_TC7_MC_1 96 /**< ID for TC7 event generator MC_1 */ -#define EVENT_ID_GEN_PDEC_OVF 97 /**< ID for PDEC event generator OVF */ -#define EVENT_ID_GEN_PDEC_ERR 98 /**< ID for PDEC event generator ERR */ -#define EVENT_ID_GEN_PDEC_DIR 99 /**< ID for PDEC event generator DIR */ -#define EVENT_ID_GEN_PDEC_VLC 100 /**< ID for PDEC event generator VLC */ -#define EVENT_ID_GEN_PDEC_MC_0 101 /**< ID for PDEC event generator MC_0 */ -#define EVENT_ID_GEN_PDEC_MC_1 102 /**< ID for PDEC event generator MC_1 */ -#define EVENT_ID_GEN_ADC0_RESRDY 103 /**< ID for ADC0 event generator RESRDY */ -#define EVENT_ID_GEN_ADC0_WINMON 104 /**< ID for ADC0 event generator WINMON */ -#define EVENT_ID_GEN_ADC1_RESRDY 105 /**< ID for ADC1 event generator RESRDY */ -#define EVENT_ID_GEN_ADC1_WINMON 106 /**< ID for ADC1 event generator WINMON */ -#define EVENT_ID_GEN_AC_COMP_0 107 /**< ID for AC event generator COMP_0 */ -#define EVENT_ID_GEN_AC_COMP_1 108 /**< ID for AC event generator COMP_1 */ -#define EVENT_ID_GEN_AC_WIN_0 109 /**< ID for AC event generator WIN_0 */ -#define EVENT_ID_GEN_DAC_EMPTY_0 110 /**< ID for DAC event generator EMPTY_0 */ -#define EVENT_ID_GEN_DAC_EMPTY_1 111 /**< ID for DAC event generator EMPTY_1 */ -#define EVENT_ID_GEN_DAC_RESRDY_0 112 /**< ID for DAC event generator RESRDY_0 */ -#define EVENT_ID_GEN_DAC_RESRDY_1 113 /**< ID for DAC event generator RESRDY_1 */ -#define EVENT_ID_GEN_GMAC_TSU_CMP 114 /**< ID for GMAC event generator TSU_CMP */ -#define EVENT_ID_GEN_TRNG_READY 115 /**< ID for TRNG event generator READY */ -#define EVENT_ID_GEN_CCL_LUTOUT_0 116 /**< ID for CCL event generator LUTOUT_0 */ -#define EVENT_ID_GEN_CCL_LUTOUT_1 117 /**< ID for CCL event generator LUTOUT_1 */ -#define EVENT_ID_GEN_CCL_LUTOUT_2 118 /**< ID for CCL event generator LUTOUT_2 */ -#define EVENT_ID_GEN_CCL_LUTOUT_3 119 /**< ID for CCL event generator LUTOUT_3 */ - -/* ************************************************************************** */ -/** Event User IDs for SAME54P19A */ -/* ************************************************************************** */ -#define EVENT_ID_USER_RTC_TAMPER 0 /**< ID for RTC event user TAMPER */ -#define EVENT_ID_USER_PORT_EV_0 1 /**< ID for PORT event user EV_0 */ -#define EVENT_ID_USER_PORT_EV_1 2 /**< ID for PORT event user EV_1 */ -#define EVENT_ID_USER_PORT_EV_2 3 /**< ID for PORT event user EV_2 */ -#define EVENT_ID_USER_PORT_EV_3 4 /**< ID for PORT event user EV_3 */ -#define EVENT_ID_USER_DMAC_CH_0 5 /**< ID for DMAC event user CH_0 */ -#define EVENT_ID_USER_DMAC_CH_1 6 /**< ID for DMAC event user CH_1 */ -#define EVENT_ID_USER_DMAC_CH_2 7 /**< ID for DMAC event user CH_2 */ -#define EVENT_ID_USER_DMAC_CH_3 8 /**< ID for DMAC event user CH_3 */ -#define EVENT_ID_USER_DMAC_CH_4 9 /**< ID for DMAC event user CH_4 */ -#define EVENT_ID_USER_DMAC_CH_5 10 /**< ID for DMAC event user CH_5 */ -#define EVENT_ID_USER_DMAC_CH_6 11 /**< ID for DMAC event user CH_6 */ -#define EVENT_ID_USER_DMAC_CH_7 12 /**< ID for DMAC event user CH_7 */ -#define EVENT_ID_USER_CM4_TRACE_START 14 /**< ID for CM4 event user TRACE_START */ -#define EVENT_ID_USER_CM4_TRACE_STOP 15 /**< ID for CM4 event user TRACE_STOP */ -#define EVENT_ID_USER_CM4_TRACE_TRIG 16 /**< ID for CM4 event user TRACE_TRIG */ -#define EVENT_ID_USER_TCC0_EV_0 17 /**< ID for TCC0 event user EV_0 */ -#define EVENT_ID_USER_TCC0_EV_1 18 /**< ID for TCC0 event user EV_1 */ -#define EVENT_ID_USER_TCC0_MC_0 19 /**< ID for TCC0 event user MC_0 */ -#define EVENT_ID_USER_TCC0_MC_1 20 /**< ID for TCC0 event user MC_1 */ -#define EVENT_ID_USER_TCC0_MC_2 21 /**< ID for TCC0 event user MC_2 */ -#define EVENT_ID_USER_TCC0_MC_3 22 /**< ID for TCC0 event user MC_3 */ -#define EVENT_ID_USER_TCC0_MC_4 23 /**< ID for TCC0 event user MC_4 */ -#define EVENT_ID_USER_TCC0_MC_5 24 /**< ID for TCC0 event user MC_5 */ -#define EVENT_ID_USER_TCC1_EV_0 25 /**< ID for TCC1 event user EV_0 */ -#define EVENT_ID_USER_TCC1_EV_1 26 /**< ID for TCC1 event user EV_1 */ -#define EVENT_ID_USER_TCC1_MC_0 27 /**< ID for TCC1 event user MC_0 */ -#define EVENT_ID_USER_TCC1_MC_1 28 /**< ID for TCC1 event user MC_1 */ -#define EVENT_ID_USER_TCC1_MC_2 29 /**< ID for TCC1 event user MC_2 */ -#define EVENT_ID_USER_TCC1_MC_3 30 /**< ID for TCC1 event user MC_3 */ -#define EVENT_ID_USER_TCC2_EV_0 31 /**< ID for TCC2 event user EV_0 */ -#define EVENT_ID_USER_TCC2_EV_1 32 /**< ID for TCC2 event user EV_1 */ -#define EVENT_ID_USER_TCC2_MC_0 33 /**< ID for TCC2 event user MC_0 */ -#define EVENT_ID_USER_TCC2_MC_1 34 /**< ID for TCC2 event user MC_1 */ -#define EVENT_ID_USER_TCC2_MC_2 35 /**< ID for TCC2 event user MC_2 */ -#define EVENT_ID_USER_TCC3_EV_0 36 /**< ID for TCC3 event user EV_0 */ -#define EVENT_ID_USER_TCC3_EV_1 37 /**< ID for TCC3 event user EV_1 */ -#define EVENT_ID_USER_TCC3_MC_0 38 /**< ID for TCC3 event user MC_0 */ -#define EVENT_ID_USER_TCC3_MC_1 39 /**< ID for TCC3 event user MC_1 */ -#define EVENT_ID_USER_TCC4_EV_0 40 /**< ID for TCC4 event user EV_0 */ -#define EVENT_ID_USER_TCC4_EV_1 41 /**< ID for TCC4 event user EV_1 */ -#define EVENT_ID_USER_TCC4_MC_0 42 /**< ID for TCC4 event user MC_0 */ -#define EVENT_ID_USER_TCC4_MC_1 43 /**< ID for TCC4 event user MC_1 */ -#define EVENT_ID_USER_TC0_EVU 44 /**< ID for TC0 event user EVU */ -#define EVENT_ID_USER_TC1_EVU 45 /**< ID for TC1 event user EVU */ -#define EVENT_ID_USER_TC2_EVU 46 /**< ID for TC2 event user EVU */ -#define EVENT_ID_USER_TC3_EVU 47 /**< ID for TC3 event user EVU */ -#define EVENT_ID_USER_TC4_EVU 48 /**< ID for TC4 event user EVU */ -#define EVENT_ID_USER_TC5_EVU 49 /**< ID for TC5 event user EVU */ -#define EVENT_ID_USER_TC6_EVU 50 /**< ID for TC6 event user EVU */ -#define EVENT_ID_USER_TC7_EVU 51 /**< ID for TC7 event user EVU */ -#define EVENT_ID_USER_PDEC_EVU_0 52 /**< ID for PDEC event user EVU_0 */ -#define EVENT_ID_USER_PDEC_EVU_1 53 /**< ID for PDEC event user EVU_1 */ -#define EVENT_ID_USER_PDEC_EVU_2 54 /**< ID for PDEC event user EVU_2 */ -#define EVENT_ID_USER_ADC0_START 55 /**< ID for ADC0 event user START */ -#define EVENT_ID_USER_ADC0_SYNC 56 /**< ID for ADC0 event user SYNC */ -#define EVENT_ID_USER_ADC1_START 57 /**< ID for ADC1 event user START */ -#define EVENT_ID_USER_ADC1_SYNC 58 /**< ID for ADC1 event user SYNC */ -#define EVENT_ID_USER_AC_SOC_0 59 /**< ID for AC event user SOC_0 */ -#define EVENT_ID_USER_AC_SOC_1 60 /**< ID for AC event user SOC_1 */ -#define EVENT_ID_USER_DAC_START_0 61 /**< ID for DAC event user START_0 */ -#define EVENT_ID_USER_DAC_START_1 62 /**< ID for DAC event user START_1 */ -#define EVENT_ID_USER_CCL_LUTIN_0 63 /**< ID for CCL event user LUTIN_0 */ -#define EVENT_ID_USER_CCL_LUTIN_1 64 /**< ID for CCL event user LUTIN_1 */ -#define EVENT_ID_USER_CCL_LUTIN_2 65 /**< ID for CCL event user LUTIN_2 */ -#define EVENT_ID_USER_CCL_LUTIN_3 66 /**< ID for CCL event user LUTIN_3 */ - -#ifdef __cplusplus -} -#endif - -/** @} end of SAME54P19A definitions */ - - -#endif /* _SAME54P19A_H_ */ - +/** + * \file + * + * \brief Header file for SAME54P19A + * + * Copyright (c) 2019 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAME54P19A_ +#define _SAME54P19A_ + +/** + * \ingroup SAME54_definitions + * \addtogroup SAME54P19A_definitions SAME54P19A definitions + * This file defines all structures and symbols for SAME54P19A: + * - registers and bitfields + * - peripheral base address + * - peripheral ID + * - PIO definitions +*/ +/*@{*/ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#include +#ifndef __cplusplus +typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#else +typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#endif +typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ +typedef volatile uint8_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ +typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ +typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ +#endif + +#if !defined(SKIP_INTEGER_LITERALS) +#if defined(_U_) || defined(_L_) || defined(_UL_) + #error "Integer Literals macros already defined elsewhere" +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/* Macros that deal with adding suffixes to integer literal constants for C/C++ */ +#define _U_(x) x ## U /**< C code: Unsigned integer literal constant value */ +#define _L_(x) x ## L /**< C code: Long integer literal constant value */ +#define _UL_(x) x ## UL /**< C code: Unsigned Long integer literal constant value */ +#else /* Assembler */ +#define _U_(x) x /**< Assembler: Unsigned integer literal constant value */ +#define _L_(x) x /**< Assembler: Long integer literal constant value */ +#define _UL_(x) x /**< Assembler: Unsigned Long integer literal constant value */ +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +#endif /* SKIP_INTEGER_LITERALS */ + +/* ************************************************************************** */ +/** CMSIS DEFINITIONS FOR SAME54P19A */ +/* ************************************************************************** */ +/** \defgroup SAME54P19A_cmsis CMSIS Definitions */ +/*@{*/ + +/** Interrupt Number Definition */ +typedef enum IRQn +{ + /****** Cortex-M4 Processor Exceptions Numbers *******************/ + NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13,/**< 3 Hard Fault Interrupt */ + MemoryManagement_IRQn = -12,/**< 4 Memory Management Interrupt */ + BusFault_IRQn = -11,/**< 5 Bus Fault Interrupt */ + UsageFault_IRQn = -10,/**< 6 Usage Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /**< 12 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /**< 14 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 System Tick Interrupt */ + /****** SAME54P19A-specific Interrupt Numbers *********************/ + PM_IRQn = 0, /**< 0 SAME54P19A Power Manager (PM) */ + MCLK_IRQn = 1, /**< 1 SAME54P19A Main Clock (MCLK) */ + OSCCTRL_0_IRQn = 2, /**< 2 SAME54P19A Oscillators Control (OSCCTRL) IRQ 0 */ + OSCCTRL_1_IRQn = 3, /**< 3 SAME54P19A Oscillators Control (OSCCTRL) IRQ 1 */ + OSCCTRL_2_IRQn = 4, /**< 4 SAME54P19A Oscillators Control (OSCCTRL) IRQ 2 */ + OSCCTRL_3_IRQn = 5, /**< 5 SAME54P19A Oscillators Control (OSCCTRL) IRQ 3 */ + OSCCTRL_4_IRQn = 6, /**< 6 SAME54P19A Oscillators Control (OSCCTRL) IRQ 4 */ + OSC32KCTRL_IRQn = 7, /**< 7 SAME54P19A 32kHz Oscillators Control (OSC32KCTRL) */ + SUPC_0_IRQn = 8, /**< 8 SAME54P19A Supply Controller (SUPC) IRQ 0 */ + SUPC_1_IRQn = 9, /**< 9 SAME54P19A Supply Controller (SUPC) IRQ 1 */ + WDT_IRQn = 10, /**< 10 SAME54P19A Watchdog Timer (WDT) */ + RTC_IRQn = 11, /**< 11 SAME54P19A Real-Time Counter (RTC) */ + EIC_0_IRQn = 12, /**< 12 SAME54P19A External Interrupt Controller (EIC) IRQ 0 */ + EIC_1_IRQn = 13, /**< 13 SAME54P19A External Interrupt Controller (EIC) IRQ 1 */ + EIC_2_IRQn = 14, /**< 14 SAME54P19A External Interrupt Controller (EIC) IRQ 2 */ + EIC_3_IRQn = 15, /**< 15 SAME54P19A External Interrupt Controller (EIC) IRQ 3 */ + EIC_4_IRQn = 16, /**< 16 SAME54P19A External Interrupt Controller (EIC) IRQ 4 */ + EIC_5_IRQn = 17, /**< 17 SAME54P19A External Interrupt Controller (EIC) IRQ 5 */ + EIC_6_IRQn = 18, /**< 18 SAME54P19A External Interrupt Controller (EIC) IRQ 6 */ + EIC_7_IRQn = 19, /**< 19 SAME54P19A External Interrupt Controller (EIC) IRQ 7 */ + EIC_8_IRQn = 20, /**< 20 SAME54P19A External Interrupt Controller (EIC) IRQ 8 */ + EIC_9_IRQn = 21, /**< 21 SAME54P19A External Interrupt Controller (EIC) IRQ 9 */ + EIC_10_IRQn = 22, /**< 22 SAME54P19A External Interrupt Controller (EIC) IRQ 10 */ + EIC_11_IRQn = 23, /**< 23 SAME54P19A External Interrupt Controller (EIC) IRQ 11 */ + EIC_12_IRQn = 24, /**< 24 SAME54P19A External Interrupt Controller (EIC) IRQ 12 */ + EIC_13_IRQn = 25, /**< 25 SAME54P19A External Interrupt Controller (EIC) IRQ 13 */ + EIC_14_IRQn = 26, /**< 26 SAME54P19A External Interrupt Controller (EIC) IRQ 14 */ + EIC_15_IRQn = 27, /**< 27 SAME54P19A External Interrupt Controller (EIC) IRQ 15 */ + FREQM_IRQn = 28, /**< 28 SAME54P19A Frequency Meter (FREQM) */ + NVMCTRL_0_IRQn = 29, /**< 29 SAME54P19A Non-Volatile Memory Controller (NVMCTRL) IRQ 0 */ + NVMCTRL_1_IRQn = 30, /**< 30 SAME54P19A Non-Volatile Memory Controller (NVMCTRL) IRQ 1 */ + DMAC_0_IRQn = 31, /**< 31 SAME54P19A Direct Memory Access Controller (DMAC) IRQ 0 */ + DMAC_1_IRQn = 32, /**< 32 SAME54P19A Direct Memory Access Controller (DMAC) IRQ 1 */ + DMAC_2_IRQn = 33, /**< 33 SAME54P19A Direct Memory Access Controller (DMAC) IRQ 2 */ + DMAC_3_IRQn = 34, /**< 34 SAME54P19A Direct Memory Access Controller (DMAC) IRQ 3 */ + DMAC_4_IRQn = 35, /**< 35 SAME54P19A Direct Memory Access Controller (DMAC) IRQ 4 */ + EVSYS_0_IRQn = 36, /**< 36 SAME54P19A Event System Interface (EVSYS) IRQ 0 */ + EVSYS_1_IRQn = 37, /**< 37 SAME54P19A Event System Interface (EVSYS) IRQ 1 */ + EVSYS_2_IRQn = 38, /**< 38 SAME54P19A Event System Interface (EVSYS) IRQ 2 */ + EVSYS_3_IRQn = 39, /**< 39 SAME54P19A Event System Interface (EVSYS) IRQ 3 */ + EVSYS_4_IRQn = 40, /**< 40 SAME54P19A Event System Interface (EVSYS) IRQ 4 */ + PAC_IRQn = 41, /**< 41 SAME54P19A Peripheral Access Controller (PAC) */ + RAMECC_IRQn = 45, /**< 45 SAME54P19A RAM ECC (RAMECC) */ + SERCOM0_0_IRQn = 46, /**< 46 SAME54P19A Serial Communication Interface 0 (SERCOM0) IRQ 0 */ + SERCOM0_1_IRQn = 47, /**< 47 SAME54P19A Serial Communication Interface 0 (SERCOM0) IRQ 1 */ + SERCOM0_2_IRQn = 48, /**< 48 SAME54P19A Serial Communication Interface 0 (SERCOM0) IRQ 2 */ + SERCOM0_3_IRQn = 49, /**< 49 SAME54P19A Serial Communication Interface 0 (SERCOM0) IRQ 3 */ + SERCOM1_0_IRQn = 50, /**< 50 SAME54P19A Serial Communication Interface 1 (SERCOM1) IRQ 0 */ + SERCOM1_1_IRQn = 51, /**< 51 SAME54P19A Serial Communication Interface 1 (SERCOM1) IRQ 1 */ + SERCOM1_2_IRQn = 52, /**< 52 SAME54P19A Serial Communication Interface 1 (SERCOM1) IRQ 2 */ + SERCOM1_3_IRQn = 53, /**< 53 SAME54P19A Serial Communication Interface 1 (SERCOM1) IRQ 3 */ + SERCOM2_0_IRQn = 54, /**< 54 SAME54P19A Serial Communication Interface 2 (SERCOM2) IRQ 0 */ + SERCOM2_1_IRQn = 55, /**< 55 SAME54P19A Serial Communication Interface 2 (SERCOM2) IRQ 1 */ + SERCOM2_2_IRQn = 56, /**< 56 SAME54P19A Serial Communication Interface 2 (SERCOM2) IRQ 2 */ + SERCOM2_3_IRQn = 57, /**< 57 SAME54P19A Serial Communication Interface 2 (SERCOM2) IRQ 3 */ + SERCOM3_0_IRQn = 58, /**< 58 SAME54P19A Serial Communication Interface 3 (SERCOM3) IRQ 0 */ + SERCOM3_1_IRQn = 59, /**< 59 SAME54P19A Serial Communication Interface 3 (SERCOM3) IRQ 1 */ + SERCOM3_2_IRQn = 60, /**< 60 SAME54P19A Serial Communication Interface 3 (SERCOM3) IRQ 2 */ + SERCOM3_3_IRQn = 61, /**< 61 SAME54P19A Serial Communication Interface 3 (SERCOM3) IRQ 3 */ + SERCOM4_0_IRQn = 62, /**< 62 SAME54P19A Serial Communication Interface 4 (SERCOM4) IRQ 0 */ + SERCOM4_1_IRQn = 63, /**< 63 SAME54P19A Serial Communication Interface 4 (SERCOM4) IRQ 1 */ + SERCOM4_2_IRQn = 64, /**< 64 SAME54P19A Serial Communication Interface 4 (SERCOM4) IRQ 2 */ + SERCOM4_3_IRQn = 65, /**< 65 SAME54P19A Serial Communication Interface 4 (SERCOM4) IRQ 3 */ + SERCOM5_0_IRQn = 66, /**< 66 SAME54P19A Serial Communication Interface 5 (SERCOM5) IRQ 0 */ + SERCOM5_1_IRQn = 67, /**< 67 SAME54P19A Serial Communication Interface 5 (SERCOM5) IRQ 1 */ + SERCOM5_2_IRQn = 68, /**< 68 SAME54P19A Serial Communication Interface 5 (SERCOM5) IRQ 2 */ + SERCOM5_3_IRQn = 69, /**< 69 SAME54P19A Serial Communication Interface 5 (SERCOM5) IRQ 3 */ + SERCOM6_0_IRQn = 70, /**< 70 SAME54P19A Serial Communication Interface 6 (SERCOM6) IRQ 0 */ + SERCOM6_1_IRQn = 71, /**< 71 SAME54P19A Serial Communication Interface 6 (SERCOM6) IRQ 1 */ + SERCOM6_2_IRQn = 72, /**< 72 SAME54P19A Serial Communication Interface 6 (SERCOM6) IRQ 2 */ + SERCOM6_3_IRQn = 73, /**< 73 SAME54P19A Serial Communication Interface 6 (SERCOM6) IRQ 3 */ + SERCOM7_0_IRQn = 74, /**< 74 SAME54P19A Serial Communication Interface 7 (SERCOM7) IRQ 0 */ + SERCOM7_1_IRQn = 75, /**< 75 SAME54P19A Serial Communication Interface 7 (SERCOM7) IRQ 1 */ + SERCOM7_2_IRQn = 76, /**< 76 SAME54P19A Serial Communication Interface 7 (SERCOM7) IRQ 2 */ + SERCOM7_3_IRQn = 77, /**< 77 SAME54P19A Serial Communication Interface 7 (SERCOM7) IRQ 3 */ + CAN0_IRQn = 78, /**< 78 SAME54P19A Control Area Network 0 (CAN0) */ + CAN1_IRQn = 79, /**< 79 SAME54P19A Control Area Network 1 (CAN1) */ + USB_0_IRQn = 80, /**< 80 SAME54P19A Universal Serial Bus (USB) IRQ 0 */ + USB_1_IRQn = 81, /**< 81 SAME54P19A Universal Serial Bus (USB) IRQ 1 */ + USB_2_IRQn = 82, /**< 82 SAME54P19A Universal Serial Bus (USB) IRQ 2 */ + USB_3_IRQn = 83, /**< 83 SAME54P19A Universal Serial Bus (USB) IRQ 3 */ + GMAC_IRQn = 84, /**< 84 SAME54P19A Ethernet MAC (GMAC) */ + TCC0_0_IRQn = 85, /**< 85 SAME54P19A Timer Counter Control 0 (TCC0) IRQ 0 */ + TCC0_1_IRQn = 86, /**< 86 SAME54P19A Timer Counter Control 0 (TCC0) IRQ 1 */ + TCC0_2_IRQn = 87, /**< 87 SAME54P19A Timer Counter Control 0 (TCC0) IRQ 2 */ + TCC0_3_IRQn = 88, /**< 88 SAME54P19A Timer Counter Control 0 (TCC0) IRQ 3 */ + TCC0_4_IRQn = 89, /**< 89 SAME54P19A Timer Counter Control 0 (TCC0) IRQ 4 */ + TCC0_5_IRQn = 90, /**< 90 SAME54P19A Timer Counter Control 0 (TCC0) IRQ 5 */ + TCC0_6_IRQn = 91, /**< 91 SAME54P19A Timer Counter Control 0 (TCC0) IRQ 6 */ + TCC1_0_IRQn = 92, /**< 92 SAME54P19A Timer Counter Control 1 (TCC1) IRQ 0 */ + TCC1_1_IRQn = 93, /**< 93 SAME54P19A Timer Counter Control 1 (TCC1) IRQ 1 */ + TCC1_2_IRQn = 94, /**< 94 SAME54P19A Timer Counter Control 1 (TCC1) IRQ 2 */ + TCC1_3_IRQn = 95, /**< 95 SAME54P19A Timer Counter Control 1 (TCC1) IRQ 3 */ + TCC1_4_IRQn = 96, /**< 96 SAME54P19A Timer Counter Control 1 (TCC1) IRQ 4 */ + TCC2_0_IRQn = 97, /**< 97 SAME54P19A Timer Counter Control 2 (TCC2) IRQ 0 */ + TCC2_1_IRQn = 98, /**< 98 SAME54P19A Timer Counter Control 2 (TCC2) IRQ 1 */ + TCC2_2_IRQn = 99, /**< 99 SAME54P19A Timer Counter Control 2 (TCC2) IRQ 2 */ + TCC2_3_IRQn = 100, /**< 100 SAME54P19A Timer Counter Control 2 (TCC2) IRQ 3 */ + TCC3_0_IRQn = 101, /**< 101 SAME54P19A Timer Counter Control 3 (TCC3) IRQ 0 */ + TCC3_1_IRQn = 102, /**< 102 SAME54P19A Timer Counter Control 3 (TCC3) IRQ 1 */ + TCC3_2_IRQn = 103, /**< 103 SAME54P19A Timer Counter Control 3 (TCC3) IRQ 2 */ + TCC4_0_IRQn = 104, /**< 104 SAME54P19A Timer Counter Control 4 (TCC4) IRQ 0 */ + TCC4_1_IRQn = 105, /**< 105 SAME54P19A Timer Counter Control 4 (TCC4) IRQ 1 */ + TCC4_2_IRQn = 106, /**< 106 SAME54P19A Timer Counter Control 4 (TCC4) IRQ 2 */ + TC0_IRQn = 107, /**< 107 SAME54P19A Basic Timer Counter 0 (TC0) */ + TC1_IRQn = 108, /**< 108 SAME54P19A Basic Timer Counter 1 (TC1) */ + TC2_IRQn = 109, /**< 109 SAME54P19A Basic Timer Counter 2 (TC2) */ + TC3_IRQn = 110, /**< 110 SAME54P19A Basic Timer Counter 3 (TC3) */ + TC4_IRQn = 111, /**< 111 SAME54P19A Basic Timer Counter 4 (TC4) */ + TC5_IRQn = 112, /**< 112 SAME54P19A Basic Timer Counter 5 (TC5) */ + TC6_IRQn = 113, /**< 113 SAME54P19A Basic Timer Counter 6 (TC6) */ + TC7_IRQn = 114, /**< 114 SAME54P19A Basic Timer Counter 7 (TC7) */ + PDEC_0_IRQn = 115, /**< 115 SAME54P19A Quadrature Decodeur (PDEC) IRQ 0 */ + PDEC_1_IRQn = 116, /**< 116 SAME54P19A Quadrature Decodeur (PDEC) IRQ 1 */ + PDEC_2_IRQn = 117, /**< 117 SAME54P19A Quadrature Decodeur (PDEC) IRQ 2 */ + ADC0_0_IRQn = 118, /**< 118 SAME54P19A Analog Digital Converter 0 (ADC0) IRQ 0 */ + ADC0_1_IRQn = 119, /**< 119 SAME54P19A Analog Digital Converter 0 (ADC0) IRQ 1 */ + ADC1_0_IRQn = 120, /**< 120 SAME54P19A Analog Digital Converter 1 (ADC1) IRQ 0 */ + ADC1_1_IRQn = 121, /**< 121 SAME54P19A Analog Digital Converter 1 (ADC1) IRQ 1 */ + AC_IRQn = 122, /**< 122 SAME54P19A Analog Comparators (AC) */ + DAC_0_IRQn = 123, /**< 123 SAME54P19A Digital-to-Analog Converter (DAC) IRQ 0 */ + DAC_1_IRQn = 124, /**< 124 SAME54P19A Digital-to-Analog Converter (DAC) IRQ 1 */ + DAC_2_IRQn = 125, /**< 125 SAME54P19A Digital-to-Analog Converter (DAC) IRQ 2 */ + DAC_3_IRQn = 126, /**< 126 SAME54P19A Digital-to-Analog Converter (DAC) IRQ 3 */ + DAC_4_IRQn = 127, /**< 127 SAME54P19A Digital-to-Analog Converter (DAC) IRQ 4 */ + I2S_IRQn = 128, /**< 128 SAME54P19A Inter-IC Sound Interface (I2S) */ + PCC_IRQn = 129, /**< 129 SAME54P19A Parallel Capture Controller (PCC) */ + AES_IRQn = 130, /**< 130 SAME54P19A Advanced Encryption Standard (AES) */ + TRNG_IRQn = 131, /**< 131 SAME54P19A True Random Generator (TRNG) */ + ICM_IRQn = 132, /**< 132 SAME54P19A Integrity Check Monitor (ICM) */ + PUKCC_IRQn = 133, /**< 133 SAME54P19A PUblic-Key Cryptography Controller (PUKCC) */ + QSPI_IRQn = 134, /**< 134 SAME54P19A Quad SPI interface (QSPI) */ + SDHC0_IRQn = 135, /**< 135 SAME54P19A SD/MMC Host Controller 0 (SDHC0) */ + SDHC1_IRQn = 136, /**< 136 SAME54P19A SD/MMC Host Controller 1 (SDHC1) */ + + PERIPH_COUNT_IRQn = 137 /**< Number of peripheral IDs */ +} IRQn_Type; + +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNonMaskableInt_Handler; + void* pfnHardFault_Handler; + void* pfnMemManagement_Handler; + void* pfnBusFault_Handler; + void* pfnUsageFault_Handler; + void* pvReservedM9; + void* pvReservedM8; + void* pvReservedM7; + void* pvReservedM6; + void* pfnSVCall_Handler; + void* pfnDebugMonitor_Handler; + void* pvReservedM3; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; + + /* Peripheral handlers */ + void* pfnPM_Handler; /* 0 Power Manager */ + void* pfnMCLK_Handler; /* 1 Main Clock */ + void* pfnOSCCTRL_0_Handler; /* 2 Oscillators Control IRQ 0 */ + void* pfnOSCCTRL_1_Handler; /* 3 Oscillators Control IRQ 1 */ + void* pfnOSCCTRL_2_Handler; /* 4 Oscillators Control IRQ 2 */ + void* pfnOSCCTRL_3_Handler; /* 5 Oscillators Control IRQ 3 */ + void* pfnOSCCTRL_4_Handler; /* 6 Oscillators Control IRQ 4 */ + void* pfnOSC32KCTRL_Handler; /* 7 32kHz Oscillators Control */ + void* pfnSUPC_0_Handler; /* 8 Supply Controller IRQ 0 */ + void* pfnSUPC_1_Handler; /* 9 Supply Controller IRQ 1 */ + void* pfnWDT_Handler; /* 10 Watchdog Timer */ + void* pfnRTC_Handler; /* 11 Real-Time Counter */ + void* pfnEIC_0_Handler; /* 12 External Interrupt Controller IRQ 0 */ + void* pfnEIC_1_Handler; /* 13 External Interrupt Controller IRQ 1 */ + void* pfnEIC_2_Handler; /* 14 External Interrupt Controller IRQ 2 */ + void* pfnEIC_3_Handler; /* 15 External Interrupt Controller IRQ 3 */ + void* pfnEIC_4_Handler; /* 16 External Interrupt Controller IRQ 4 */ + void* pfnEIC_5_Handler; /* 17 External Interrupt Controller IRQ 5 */ + void* pfnEIC_6_Handler; /* 18 External Interrupt Controller IRQ 6 */ + void* pfnEIC_7_Handler; /* 19 External Interrupt Controller IRQ 7 */ + void* pfnEIC_8_Handler; /* 20 External Interrupt Controller IRQ 8 */ + void* pfnEIC_9_Handler; /* 21 External Interrupt Controller IRQ 9 */ + void* pfnEIC_10_Handler; /* 22 External Interrupt Controller IRQ 10 */ + void* pfnEIC_11_Handler; /* 23 External Interrupt Controller IRQ 11 */ + void* pfnEIC_12_Handler; /* 24 External Interrupt Controller IRQ 12 */ + void* pfnEIC_13_Handler; /* 25 External Interrupt Controller IRQ 13 */ + void* pfnEIC_14_Handler; /* 26 External Interrupt Controller IRQ 14 */ + void* pfnEIC_15_Handler; /* 27 External Interrupt Controller IRQ 15 */ + void* pfnFREQM_Handler; /* 28 Frequency Meter */ + void* pfnNVMCTRL_0_Handler; /* 29 Non-Volatile Memory Controller IRQ 0 */ + void* pfnNVMCTRL_1_Handler; /* 30 Non-Volatile Memory Controller IRQ 1 */ + void* pfnDMAC_0_Handler; /* 31 Direct Memory Access Controller IRQ 0 */ + void* pfnDMAC_1_Handler; /* 32 Direct Memory Access Controller IRQ 1 */ + void* pfnDMAC_2_Handler; /* 33 Direct Memory Access Controller IRQ 2 */ + void* pfnDMAC_3_Handler; /* 34 Direct Memory Access Controller IRQ 3 */ + void* pfnDMAC_4_Handler; /* 35 Direct Memory Access Controller IRQ 4 */ + void* pfnEVSYS_0_Handler; /* 36 Event System Interface IRQ 0 */ + void* pfnEVSYS_1_Handler; /* 37 Event System Interface IRQ 1 */ + void* pfnEVSYS_2_Handler; /* 38 Event System Interface IRQ 2 */ + void* pfnEVSYS_3_Handler; /* 39 Event System Interface IRQ 3 */ + void* pfnEVSYS_4_Handler; /* 40 Event System Interface IRQ 4 */ + void* pfnPAC_Handler; /* 41 Peripheral Access Controller */ + void* pvReserved42; + void* pvReserved43; + void* pvReserved44; + void* pfnRAMECC_Handler; /* 45 RAM ECC */ + void* pfnSERCOM0_0_Handler; /* 46 Serial Communication Interface 0 IRQ 0 */ + void* pfnSERCOM0_1_Handler; /* 47 Serial Communication Interface 0 IRQ 1 */ + void* pfnSERCOM0_2_Handler; /* 48 Serial Communication Interface 0 IRQ 2 */ + void* pfnSERCOM0_3_Handler; /* 49 Serial Communication Interface 0 IRQ 3 */ + void* pfnSERCOM1_0_Handler; /* 50 Serial Communication Interface 1 IRQ 0 */ + void* pfnSERCOM1_1_Handler; /* 51 Serial Communication Interface 1 IRQ 1 */ + void* pfnSERCOM1_2_Handler; /* 52 Serial Communication Interface 1 IRQ 2 */ + void* pfnSERCOM1_3_Handler; /* 53 Serial Communication Interface 1 IRQ 3 */ + void* pfnSERCOM2_0_Handler; /* 54 Serial Communication Interface 2 IRQ 0 */ + void* pfnSERCOM2_1_Handler; /* 55 Serial Communication Interface 2 IRQ 1 */ + void* pfnSERCOM2_2_Handler; /* 56 Serial Communication Interface 2 IRQ 2 */ + void* pfnSERCOM2_3_Handler; /* 57 Serial Communication Interface 2 IRQ 3 */ + void* pfnSERCOM3_0_Handler; /* 58 Serial Communication Interface 3 IRQ 0 */ + void* pfnSERCOM3_1_Handler; /* 59 Serial Communication Interface 3 IRQ 1 */ + void* pfnSERCOM3_2_Handler; /* 60 Serial Communication Interface 3 IRQ 2 */ + void* pfnSERCOM3_3_Handler; /* 61 Serial Communication Interface 3 IRQ 3 */ + void* pfnSERCOM4_0_Handler; /* 62 Serial Communication Interface 4 IRQ 0 */ + void* pfnSERCOM4_1_Handler; /* 63 Serial Communication Interface 4 IRQ 1 */ + void* pfnSERCOM4_2_Handler; /* 64 Serial Communication Interface 4 IRQ 2 */ + void* pfnSERCOM4_3_Handler; /* 65 Serial Communication Interface 4 IRQ 3 */ + void* pfnSERCOM5_0_Handler; /* 66 Serial Communication Interface 5 IRQ 0 */ + void* pfnSERCOM5_1_Handler; /* 67 Serial Communication Interface 5 IRQ 1 */ + void* pfnSERCOM5_2_Handler; /* 68 Serial Communication Interface 5 IRQ 2 */ + void* pfnSERCOM5_3_Handler; /* 69 Serial Communication Interface 5 IRQ 3 */ + void* pfnSERCOM6_0_Handler; /* 70 Serial Communication Interface 6 IRQ 0 */ + void* pfnSERCOM6_1_Handler; /* 71 Serial Communication Interface 6 IRQ 1 */ + void* pfnSERCOM6_2_Handler; /* 72 Serial Communication Interface 6 IRQ 2 */ + void* pfnSERCOM6_3_Handler; /* 73 Serial Communication Interface 6 IRQ 3 */ + void* pfnSERCOM7_0_Handler; /* 74 Serial Communication Interface 7 IRQ 0 */ + void* pfnSERCOM7_1_Handler; /* 75 Serial Communication Interface 7 IRQ 1 */ + void* pfnSERCOM7_2_Handler; /* 76 Serial Communication Interface 7 IRQ 2 */ + void* pfnSERCOM7_3_Handler; /* 77 Serial Communication Interface 7 IRQ 3 */ + void* pfnCAN0_Handler; /* 78 Control Area Network 0 */ + void* pfnCAN1_Handler; /* 79 Control Area Network 1 */ + void* pfnUSB_0_Handler; /* 80 Universal Serial Bus IRQ 0 */ + void* pfnUSB_1_Handler; /* 81 Universal Serial Bus IRQ 1 */ + void* pfnUSB_2_Handler; /* 82 Universal Serial Bus IRQ 2 */ + void* pfnUSB_3_Handler; /* 83 Universal Serial Bus IRQ 3 */ + void* pfnGMAC_Handler; /* 84 Ethernet MAC */ + void* pfnTCC0_0_Handler; /* 85 Timer Counter Control 0 IRQ 0 */ + void* pfnTCC0_1_Handler; /* 86 Timer Counter Control 0 IRQ 1 */ + void* pfnTCC0_2_Handler; /* 87 Timer Counter Control 0 IRQ 2 */ + void* pfnTCC0_3_Handler; /* 88 Timer Counter Control 0 IRQ 3 */ + void* pfnTCC0_4_Handler; /* 89 Timer Counter Control 0 IRQ 4 */ + void* pfnTCC0_5_Handler; /* 90 Timer Counter Control 0 IRQ 5 */ + void* pfnTCC0_6_Handler; /* 91 Timer Counter Control 0 IRQ 6 */ + void* pfnTCC1_0_Handler; /* 92 Timer Counter Control 1 IRQ 0 */ + void* pfnTCC1_1_Handler; /* 93 Timer Counter Control 1 IRQ 1 */ + void* pfnTCC1_2_Handler; /* 94 Timer Counter Control 1 IRQ 2 */ + void* pfnTCC1_3_Handler; /* 95 Timer Counter Control 1 IRQ 3 */ + void* pfnTCC1_4_Handler; /* 96 Timer Counter Control 1 IRQ 4 */ + void* pfnTCC2_0_Handler; /* 97 Timer Counter Control 2 IRQ 0 */ + void* pfnTCC2_1_Handler; /* 98 Timer Counter Control 2 IRQ 1 */ + void* pfnTCC2_2_Handler; /* 99 Timer Counter Control 2 IRQ 2 */ + void* pfnTCC2_3_Handler; /* 100 Timer Counter Control 2 IRQ 3 */ + void* pfnTCC3_0_Handler; /* 101 Timer Counter Control 3 IRQ 0 */ + void* pfnTCC3_1_Handler; /* 102 Timer Counter Control 3 IRQ 1 */ + void* pfnTCC3_2_Handler; /* 103 Timer Counter Control 3 IRQ 2 */ + void* pfnTCC4_0_Handler; /* 104 Timer Counter Control 4 IRQ 0 */ + void* pfnTCC4_1_Handler; /* 105 Timer Counter Control 4 IRQ 1 */ + void* pfnTCC4_2_Handler; /* 106 Timer Counter Control 4 IRQ 2 */ + void* pfnTC0_Handler; /* 107 Basic Timer Counter 0 */ + void* pfnTC1_Handler; /* 108 Basic Timer Counter 1 */ + void* pfnTC2_Handler; /* 109 Basic Timer Counter 2 */ + void* pfnTC3_Handler; /* 110 Basic Timer Counter 3 */ + void* pfnTC4_Handler; /* 111 Basic Timer Counter 4 */ + void* pfnTC5_Handler; /* 112 Basic Timer Counter 5 */ + void* pfnTC6_Handler; /* 113 Basic Timer Counter 6 */ + void* pfnTC7_Handler; /* 114 Basic Timer Counter 7 */ + void* pfnPDEC_0_Handler; /* 115 Quadrature Decodeur IRQ 0 */ + void* pfnPDEC_1_Handler; /* 116 Quadrature Decodeur IRQ 1 */ + void* pfnPDEC_2_Handler; /* 117 Quadrature Decodeur IRQ 2 */ + void* pfnADC0_0_Handler; /* 118 Analog Digital Converter 0 IRQ 0 */ + void* pfnADC0_1_Handler; /* 119 Analog Digital Converter 0 IRQ 1 */ + void* pfnADC1_0_Handler; /* 120 Analog Digital Converter 1 IRQ 0 */ + void* pfnADC1_1_Handler; /* 121 Analog Digital Converter 1 IRQ 1 */ + void* pfnAC_Handler; /* 122 Analog Comparators */ + void* pfnDAC_0_Handler; /* 123 Digital-to-Analog Converter IRQ 0 */ + void* pfnDAC_1_Handler; /* 124 Digital-to-Analog Converter IRQ 1 */ + void* pfnDAC_2_Handler; /* 125 Digital-to-Analog Converter IRQ 2 */ + void* pfnDAC_3_Handler; /* 126 Digital-to-Analog Converter IRQ 3 */ + void* pfnDAC_4_Handler; /* 127 Digital-to-Analog Converter IRQ 4 */ + void* pfnI2S_Handler; /* 128 Inter-IC Sound Interface */ + void* pfnPCC_Handler; /* 129 Parallel Capture Controller */ + void* pfnAES_Handler; /* 130 Advanced Encryption Standard */ + void* pfnTRNG_Handler; /* 131 True Random Generator */ + void* pfnICM_Handler; /* 132 Integrity Check Monitor */ + void* pfnPUKCC_Handler; /* 133 PUblic-Key Cryptography Controller */ + void* pfnQSPI_Handler; /* 134 Quad SPI interface */ + void* pfnSDHC0_Handler; /* 135 SD/MMC Host Controller 0 */ + void* pfnSDHC1_Handler; /* 136 SD/MMC Host Controller 1 */ +} DeviceVectors; + +/* Cortex-M4 processor handlers */ +void Reset_Handler ( void ); +void NonMaskableInt_Handler ( void ); +void HardFault_Handler ( void ); +void MemManagement_Handler ( void ); +void BusFault_Handler ( void ); +void UsageFault_Handler ( void ); +void SVCall_Handler ( void ); +void DebugMonitor_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); + +/* Peripherals handlers */ +void PM_Handler ( void ); +void MCLK_Handler ( void ); +void OSCCTRL_0_Handler ( void ); +void OSCCTRL_1_Handler ( void ); +void OSCCTRL_2_Handler ( void ); +void OSCCTRL_3_Handler ( void ); +void OSCCTRL_4_Handler ( void ); +void OSC32KCTRL_Handler ( void ); +void SUPC_0_Handler ( void ); +void SUPC_1_Handler ( void ); +void WDT_Handler ( void ); +void RTC_Handler ( void ); +void EIC_0_Handler ( void ); +void EIC_1_Handler ( void ); +void EIC_2_Handler ( void ); +void EIC_3_Handler ( void ); +void EIC_4_Handler ( void ); +void EIC_5_Handler ( void ); +void EIC_6_Handler ( void ); +void EIC_7_Handler ( void ); +void EIC_8_Handler ( void ); +void EIC_9_Handler ( void ); +void EIC_10_Handler ( void ); +void EIC_11_Handler ( void ); +void EIC_12_Handler ( void ); +void EIC_13_Handler ( void ); +void EIC_14_Handler ( void ); +void EIC_15_Handler ( void ); +void FREQM_Handler ( void ); +void NVMCTRL_0_Handler ( void ); +void NVMCTRL_1_Handler ( void ); +void DMAC_0_Handler ( void ); +void DMAC_1_Handler ( void ); +void DMAC_2_Handler ( void ); +void DMAC_3_Handler ( void ); +void DMAC_4_Handler ( void ); +void EVSYS_0_Handler ( void ); +void EVSYS_1_Handler ( void ); +void EVSYS_2_Handler ( void ); +void EVSYS_3_Handler ( void ); +void EVSYS_4_Handler ( void ); +void PAC_Handler ( void ); +void RAMECC_Handler ( void ); +void SERCOM0_0_Handler ( void ); +void SERCOM0_1_Handler ( void ); +void SERCOM0_2_Handler ( void ); +void SERCOM0_3_Handler ( void ); +void SERCOM1_0_Handler ( void ); +void SERCOM1_1_Handler ( void ); +void SERCOM1_2_Handler ( void ); +void SERCOM1_3_Handler ( void ); +void SERCOM2_0_Handler ( void ); +void SERCOM2_1_Handler ( void ); +void SERCOM2_2_Handler ( void ); +void SERCOM2_3_Handler ( void ); +void SERCOM3_0_Handler ( void ); +void SERCOM3_1_Handler ( void ); +void SERCOM3_2_Handler ( void ); +void SERCOM3_3_Handler ( void ); +void SERCOM4_0_Handler ( void ); +void SERCOM4_1_Handler ( void ); +void SERCOM4_2_Handler ( void ); +void SERCOM4_3_Handler ( void ); +void SERCOM5_0_Handler ( void ); +void SERCOM5_1_Handler ( void ); +void SERCOM5_2_Handler ( void ); +void SERCOM5_3_Handler ( void ); +void SERCOM6_0_Handler ( void ); +void SERCOM6_1_Handler ( void ); +void SERCOM6_2_Handler ( void ); +void SERCOM6_3_Handler ( void ); +void SERCOM7_0_Handler ( void ); +void SERCOM7_1_Handler ( void ); +void SERCOM7_2_Handler ( void ); +void SERCOM7_3_Handler ( void ); +void CAN0_Handler ( void ); +void CAN1_Handler ( void ); +void USB_0_Handler ( void ); +void USB_1_Handler ( void ); +void USB_2_Handler ( void ); +void USB_3_Handler ( void ); +void GMAC_Handler ( void ); +void TCC0_0_Handler ( void ); +void TCC0_1_Handler ( void ); +void TCC0_2_Handler ( void ); +void TCC0_3_Handler ( void ); +void TCC0_4_Handler ( void ); +void TCC0_5_Handler ( void ); +void TCC0_6_Handler ( void ); +void TCC1_0_Handler ( void ); +void TCC1_1_Handler ( void ); +void TCC1_2_Handler ( void ); +void TCC1_3_Handler ( void ); +void TCC1_4_Handler ( void ); +void TCC2_0_Handler ( void ); +void TCC2_1_Handler ( void ); +void TCC2_2_Handler ( void ); +void TCC2_3_Handler ( void ); +void TCC3_0_Handler ( void ); +void TCC3_1_Handler ( void ); +void TCC3_2_Handler ( void ); +void TCC4_0_Handler ( void ); +void TCC4_1_Handler ( void ); +void TCC4_2_Handler ( void ); +void TC0_Handler ( void ); +void TC1_Handler ( void ); +void TC2_Handler ( void ); +void TC3_Handler ( void ); +void TC4_Handler ( void ); +void TC5_Handler ( void ); +void TC6_Handler ( void ); +void TC7_Handler ( void ); +void PDEC_0_Handler ( void ); +void PDEC_1_Handler ( void ); +void PDEC_2_Handler ( void ); +void ADC0_0_Handler ( void ); +void ADC0_1_Handler ( void ); +void ADC1_0_Handler ( void ); +void ADC1_1_Handler ( void ); +void AC_Handler ( void ); +void DAC_0_Handler ( void ); +void DAC_1_Handler ( void ); +void DAC_2_Handler ( void ); +void DAC_3_Handler ( void ); +void DAC_4_Handler ( void ); +void I2S_Handler ( void ); +void PCC_Handler ( void ); +void AES_Handler ( void ); +void TRNG_Handler ( void ); +void ICM_Handler ( void ); +void PUKCC_Handler ( void ); +void QSPI_Handler ( void ); +void SDHC0_Handler ( void ); +void SDHC1_Handler ( void ); + +/* + * \brief Configuration of the Cortex-M4 Processor and Core Peripherals + */ + +#define __CM4_REV 1 /*!< Core revision r0p1 */ +#define __DEBUG_LVL 3 /*!< Full debug plus DWT data matching */ +#define __FPU_PRESENT 1 /*!< FPU present or not */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ +#define __NVIC_PRIO_BITS 3 /*!< Number of bits used for Priority Levels */ +#define __TRACE_LVL 2 /*!< Full trace: ITM, DWT triggers and counters, ETM */ +#define __VTOR_PRESENT 1 /*!< VTOR present or not */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + +/** + * \brief CMSIS includes + */ + +#include +#if !defined DONT_USE_CMSIS_INIT +#include "system_same54.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/*@}*/ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAME54P19A */ +/* ************************************************************************** */ +/** \defgroup SAME54P19A_api Peripheral Software API */ +/*@{*/ + +#include "component/ac.h" +#include "component/adc.h" +#include "component/aes.h" +#include "component/can.h" +#include "component/ccl.h" +#include "component/cmcc.h" +#include "component/dac.h" +#include "component/dmac.h" +#include "component/dsu.h" +#include "component/eic.h" +#include "component/evsys.h" +#include "component/freqm.h" +#include "component/gclk.h" +#include "component/gmac.h" +#include "component/hmatrixb.h" +#include "component/icm.h" +#include "component/i2s.h" +#include "component/mclk.h" +#include "component/nvmctrl.h" +#include "component/oscctrl.h" +#include "component/osc32kctrl.h" +#include "component/pac.h" +#include "component/pcc.h" +#include "component/pdec.h" +#include "component/pm.h" +#include "component/port.h" +#include "component/qspi.h" +#include "component/ramecc.h" +#include "component/rstc.h" +#include "component/rtc.h" +#include "component/sdhc.h" +#include "component/sercom.h" +#include "component/supc.h" +#include "component/tc.h" +#include "component/tcc.h" +#include "component/trng.h" +#include "component/usb.h" +#include "component/wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/** REGISTERS ACCESS DEFINITIONS FOR SAME54P19A */ +/* ************************************************************************** */ +/** \defgroup SAME54P19A_reg Registers Access Definitions */ +/*@{*/ + +#include "instance/ac.h" +#include "instance/adc0.h" +#include "instance/adc1.h" +#include "instance/aes.h" +#include "instance/can0.h" +#include "instance/can1.h" +#include "instance/ccl.h" +#include "instance/cmcc.h" +#include "instance/dac.h" +#include "instance/dmac.h" +#include "instance/dsu.h" +#include "instance/eic.h" +#include "instance/evsys.h" +#include "instance/freqm.h" +#include "instance/gclk.h" +#include "instance/gmac.h" +#include "instance/hmatrix.h" +#include "instance/icm.h" +#include "instance/i2s.h" +#include "instance/mclk.h" +#include "instance/nvmctrl.h" +#include "instance/oscctrl.h" +#include "instance/osc32kctrl.h" +#include "instance/pac.h" +#include "instance/pcc.h" +#include "instance/pdec.h" +#include "instance/pm.h" +#include "instance/port.h" +#include "instance/pukcc.h" +#include "instance/qspi.h" +#include "instance/ramecc.h" +#include "instance/rstc.h" +#include "instance/rtc.h" +#include "instance/sdhc0.h" +#include "instance/sdhc1.h" +#include "instance/sercom0.h" +#include "instance/sercom1.h" +#include "instance/sercom2.h" +#include "instance/sercom3.h" +#include "instance/sercom4.h" +#include "instance/sercom5.h" +#include "instance/sercom6.h" +#include "instance/sercom7.h" +#include "instance/supc.h" +#include "instance/tc0.h" +#include "instance/tc1.h" +#include "instance/tc2.h" +#include "instance/tc3.h" +#include "instance/tc4.h" +#include "instance/tc5.h" +#include "instance/tc6.h" +#include "instance/tc7.h" +#include "instance/tcc0.h" +#include "instance/tcc1.h" +#include "instance/tcc2.h" +#include "instance/tcc3.h" +#include "instance/tcc4.h" +#include "instance/trng.h" +#include "instance/usb.h" +#include "instance/wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/** PERIPHERAL ID DEFINITIONS FOR SAME54P19A */ +/* ************************************************************************** */ +/** \defgroup SAME54P19A_id Peripheral Ids Definitions */ +/*@{*/ + +// Peripheral instances on HPB0 bridge +#define ID_PAC 0 /**< \brief Peripheral Access Controller (PAC) */ +#define ID_PM 1 /**< \brief Power Manager (PM) */ +#define ID_MCLK 2 /**< \brief Main Clock (MCLK) */ +#define ID_RSTC 3 /**< \brief Reset Controller (RSTC) */ +#define ID_OSCCTRL 4 /**< \brief Oscillators Control (OSCCTRL) */ +#define ID_OSC32KCTRL 5 /**< \brief 32kHz Oscillators Control (OSC32KCTRL) */ +#define ID_SUPC 6 /**< \brief Supply Controller (SUPC) */ +#define ID_GCLK 7 /**< \brief Generic Clock Generator (GCLK) */ +#define ID_WDT 8 /**< \brief Watchdog Timer (WDT) */ +#define ID_RTC 9 /**< \brief Real-Time Counter (RTC) */ +#define ID_EIC 10 /**< \brief External Interrupt Controller (EIC) */ +#define ID_FREQM 11 /**< \brief Frequency Meter (FREQM) */ +#define ID_SERCOM0 12 /**< \brief Serial Communication Interface 0 (SERCOM0) */ +#define ID_SERCOM1 13 /**< \brief Serial Communication Interface 1 (SERCOM1) */ +#define ID_TC0 14 /**< \brief Basic Timer Counter 0 (TC0) */ +#define ID_TC1 15 /**< \brief Basic Timer Counter 1 (TC1) */ + +// Peripheral instances on HPB1 bridge +#define ID_USB 32 /**< \brief Universal Serial Bus (USB) */ +#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ +#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ +#define ID_CMCC 35 /**< \brief Cortex M Cache Controller (CMCC) */ +#define ID_PORT 36 /**< \brief Port Module (PORT) */ +#define ID_DMAC 37 /**< \brief Direct Memory Access Controller (DMAC) */ +#define ID_HMATRIX 38 /**< \brief HSB Matrix (HMATRIX) */ +#define ID_EVSYS 39 /**< \brief Event System Interface (EVSYS) */ +#define ID_SERCOM2 41 /**< \brief Serial Communication Interface 2 (SERCOM2) */ +#define ID_SERCOM3 42 /**< \brief Serial Communication Interface 3 (SERCOM3) */ +#define ID_TCC0 43 /**< \brief Timer Counter Control 0 (TCC0) */ +#define ID_TCC1 44 /**< \brief Timer Counter Control 1 (TCC1) */ +#define ID_TC2 45 /**< \brief Basic Timer Counter 2 (TC2) */ +#define ID_TC3 46 /**< \brief Basic Timer Counter 3 (TC3) */ +#define ID_RAMECC 48 /**< \brief RAM ECC (RAMECC) */ + +// Peripheral instances on HPB2 bridge +#define ID_CAN0 64 /**< \brief Control Area Network 0 (CAN0) */ +#define ID_CAN1 65 /**< \brief Control Area Network 1 (CAN1) */ +#define ID_GMAC 66 /**< \brief Ethernet MAC (GMAC) */ +#define ID_TCC2 67 /**< \brief Timer Counter Control 2 (TCC2) */ +#define ID_TCC3 68 /**< \brief Timer Counter Control 3 (TCC3) */ +#define ID_TC4 69 /**< \brief Basic Timer Counter 4 (TC4) */ +#define ID_TC5 70 /**< \brief Basic Timer Counter 5 (TC5) */ +#define ID_PDEC 71 /**< \brief Quadrature Decodeur (PDEC) */ +#define ID_AC 72 /**< \brief Analog Comparators (AC) */ +#define ID_AES 73 /**< \brief Advanced Encryption Standard (AES) */ +#define ID_TRNG 74 /**< \brief True Random Generator (TRNG) */ +#define ID_ICM 75 /**< \brief Integrity Check Monitor (ICM) */ +#define ID_PUKCC 76 /**< \brief PUblic-Key Cryptography Controller (PUKCC) */ +#define ID_QSPI 77 /**< \brief Quad SPI interface (QSPI) */ +#define ID_CCL 78 /**< \brief Configurable Custom Logic (CCL) */ + +// Peripheral instances on HPB3 bridge +#define ID_SERCOM4 96 /**< \brief Serial Communication Interface 4 (SERCOM4) */ +#define ID_SERCOM5 97 /**< \brief Serial Communication Interface 5 (SERCOM5) */ +#define ID_SERCOM6 98 /**< \brief Serial Communication Interface 6 (SERCOM6) */ +#define ID_SERCOM7 99 /**< \brief Serial Communication Interface 7 (SERCOM7) */ +#define ID_TCC4 100 /**< \brief Timer Counter Control 4 (TCC4) */ +#define ID_TC6 101 /**< \brief Basic Timer Counter 6 (TC6) */ +#define ID_TC7 102 /**< \brief Basic Timer Counter 7 (TC7) */ +#define ID_ADC0 103 /**< \brief Analog Digital Converter 0 (ADC0) */ +#define ID_ADC1 104 /**< \brief Analog Digital Converter 1 (ADC1) */ +#define ID_DAC 105 /**< \brief Digital-to-Analog Converter (DAC) */ +#define ID_I2S 106 /**< \brief Inter-IC Sound Interface (I2S) */ +#define ID_PCC 107 /**< \brief Parallel Capture Controller (PCC) */ + +// Peripheral instances on AHB (as if on bridge 4) +#define ID_SDHC0 128 /**< \brief SD/MMC Host Controller (SDHC0) */ +#define ID_SDHC1 129 /**< \brief SD/MMC Host Controller (SDHC1) */ + +#define ID_PERIPH_COUNT 130 /**< \brief Max number of peripheral IDs */ +/*@}*/ + +/* ************************************************************************** */ +/** BASE ADDRESS DEFINITIONS FOR SAME54P19A */ +/* ************************************************************************** */ +/** \defgroup SAME54P19A_base Peripheral Base Address Definitions */ +/*@{*/ + +#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) +#define AC (0x42002000) /**< \brief (AC) APB Base Address */ +#define ADC0 (0x43001C00) /**< \brief (ADC0) APB Base Address */ +#define ADC1 (0x43002000) /**< \brief (ADC1) APB Base Address */ +#define AES (0x42002400) /**< \brief (AES) APB Base Address */ +#define CAN0 (0x42000000) /**< \brief (CAN0) APB Base Address */ +#define CAN1 (0x42000400) /**< \brief (CAN1) APB Base Address */ +#define CCL (0x42003800) /**< \brief (CCL) APB Base Address */ +#define CMCC (0x41006000) /**< \brief (CMCC) APB Base Address */ +#define CMCC_AHB (0x03000000) /**< \brief (CMCC) AHB Base Address */ +#define DAC (0x43002400) /**< \brief (DAC) APB Base Address */ +#define DMAC (0x4100A000) /**< \brief (DMAC) APB Base Address */ +#define DSU (0x41002000) /**< \brief (DSU) APB Base Address */ +#define EIC (0x40002800) /**< \brief (EIC) APB Base Address */ +#define EVSYS (0x4100E000) /**< \brief (EVSYS) APB Base Address */ +#define FREQM (0x40002C00) /**< \brief (FREQM) APB Base Address */ +#define GCLK (0x40001C00) /**< \brief (GCLK) APB Base Address */ +#define GMAC (0x42000800) /**< \brief (GMAC) APB Base Address */ +#define HMATRIX (0x4100C000) /**< \brief (HMATRIX) APB Base Address */ +#define ICM (0x42002C00) /**< \brief (ICM) APB Base Address */ +#define I2S (0x43002800) /**< \brief (I2S) APB Base Address */ +#define MCLK (0x40000800) /**< \brief (MCLK) APB Base Address */ +#define NVMCTRL (0x41004000) /**< \brief (NVMCTRL) APB Base Address */ +#define NVMCTRL_SW0 (0x00800080) /**< \brief (NVMCTRL) SW0 Base Address */ +#define NVMCTRL_TEMP_LOG (0x00800100) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ +#define NVMCTRL_USER (0x00804000) /**< \brief (NVMCTRL) USER Base Address */ +#define OSCCTRL (0x40001000) /**< \brief (OSCCTRL) APB Base Address */ +#define OSC32KCTRL (0x40001400) /**< \brief (OSC32KCTRL) APB Base Address */ +#define PAC (0x40000000) /**< \brief (PAC) APB Base Address */ +#define PCC (0x43002C00) /**< \brief (PCC) APB Base Address */ +#define PDEC (0x42001C00) /**< \brief (PDEC) APB Base Address */ +#define PM (0x40000400) /**< \brief (PM) APB Base Address */ +#define PORT (0x41008000) /**< \brief (PORT) APB Base Address */ +#define PUKCC (0x42003000) /**< \brief (PUKCC) APB Base Address */ +#define PUKCC_AHB (0x02000000) /**< \brief (PUKCC) AHB Base Address */ +#define QSPI (0x42003400) /**< \brief (QSPI) APB Base Address */ +#define QSPI_AHB (0x04000000) /**< \brief (QSPI) AHB Base Address */ +#define RAMECC (0x41020000) /**< \brief (RAMECC) APB Base Address */ +#define RSTC (0x40000C00) /**< \brief (RSTC) APB Base Address */ +#define RTC (0x40002400) /**< \brief (RTC) APB Base Address */ +#define SDHC0 (0x45000000) /**< \brief (SDHC0) AHB Base Address */ +#define SDHC1 (0x46000000) /**< \brief (SDHC1) AHB Base Address */ +#define SERCOM0 (0x40003000) /**< \brief (SERCOM0) APB Base Address */ +#define SERCOM1 (0x40003400) /**< \brief (SERCOM1) APB Base Address */ +#define SERCOM2 (0x41012000) /**< \brief (SERCOM2) APB Base Address */ +#define SERCOM3 (0x41014000) /**< \brief (SERCOM3) APB Base Address */ +#define SERCOM4 (0x43000000) /**< \brief (SERCOM4) APB Base Address */ +#define SERCOM5 (0x43000400) /**< \brief (SERCOM5) APB Base Address */ +#define SERCOM6 (0x43000800) /**< \brief (SERCOM6) APB Base Address */ +#define SERCOM7 (0x43000C00) /**< \brief (SERCOM7) APB Base Address */ +#define SUPC (0x40001800) /**< \brief (SUPC) APB Base Address */ +#define TC0 (0x40003800) /**< \brief (TC0) APB Base Address */ +#define TC1 (0x40003C00) /**< \brief (TC1) APB Base Address */ +#define TC2 (0x4101A000) /**< \brief (TC2) APB Base Address */ +#define TC3 (0x4101C000) /**< \brief (TC3) APB Base Address */ +#define TC4 (0x42001400) /**< \brief (TC4) APB Base Address */ +#define TC5 (0x42001800) /**< \brief (TC5) APB Base Address */ +#define TC6 (0x43001400) /**< \brief (TC6) APB Base Address */ +#define TC7 (0x43001800) /**< \brief (TC7) APB Base Address */ +#define TCC0 (0x41016000) /**< \brief (TCC0) APB Base Address */ +#define TCC1 (0x41018000) /**< \brief (TCC1) APB Base Address */ +#define TCC2 (0x42000C00) /**< \brief (TCC2) APB Base Address */ +#define TCC3 (0x42001000) /**< \brief (TCC3) APB Base Address */ +#define TCC4 (0x43001000) /**< \brief (TCC4) APB Base Address */ +#define TRNG (0x42002800) /**< \brief (TRNG) APB Base Address */ +#define USB (0x41000000) /**< \brief (USB) APB Base Address */ +#define WDT (0x40002000) /**< \brief (WDT) APB Base Address */ +#else +#define AC ((Ac *)0x42002000UL) /**< \brief (AC) APB Base Address */ +#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ +#define AC_INSTS { AC } /**< \brief (AC) Instances List */ + +#define ADC0 ((Adc *)0x43001C00UL) /**< \brief (ADC0) APB Base Address */ +#define ADC1 ((Adc *)0x43002000UL) /**< \brief (ADC1) APB Base Address */ +#define ADC_INST_NUM 2 /**< \brief (ADC) Number of instances */ +#define ADC_INSTS { ADC0, ADC1 } /**< \brief (ADC) Instances List */ + +#define AES ((Aes *)0x42002400UL) /**< \brief (AES) APB Base Address */ +#define AES_INST_NUM 1 /**< \brief (AES) Number of instances */ +#define AES_INSTS { AES } /**< \brief (AES) Instances List */ + +#define CAN0 ((Can *)0x42000000UL) /**< \brief (CAN0) APB Base Address */ +#define CAN1 ((Can *)0x42000400UL) /**< \brief (CAN1) APB Base Address */ +#define CAN_INST_NUM 2 /**< \brief (CAN) Number of instances */ +#define CAN_INSTS { CAN0, CAN1 } /**< \brief (CAN) Instances List */ + +#define CCL ((Ccl *)0x42003800UL) /**< \brief (CCL) APB Base Address */ +#define CCL_INST_NUM 1 /**< \brief (CCL) Number of instances */ +#define CCL_INSTS { CCL } /**< \brief (CCL) Instances List */ + +#define CMCC ((Cmcc *)0x41006000UL) /**< \brief (CMCC) APB Base Address */ +#define CMCC_AHB (0x03000000UL) /**< \brief (CMCC) AHB Base Address */ +#define CMCC_INST_NUM 1 /**< \brief (CMCC) Number of instances */ +#define CMCC_INSTS { CMCC } /**< \brief (CMCC) Instances List */ + +#define DAC ((Dac *)0x43002400UL) /**< \brief (DAC) APB Base Address */ +#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */ +#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */ + +#define DMAC ((Dmac *)0x4100A000UL) /**< \brief (DMAC) APB Base Address */ +#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ +#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ + +#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ +#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ +#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ + +#define EIC ((Eic *)0x40002800UL) /**< \brief (EIC) APB Base Address */ +#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ +#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ + +#define EVSYS ((Evsys *)0x4100E000UL) /**< \brief (EVSYS) APB Base Address */ +#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ +#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ + +#define FREQM ((Freqm *)0x40002C00UL) /**< \brief (FREQM) APB Base Address */ +#define FREQM_INST_NUM 1 /**< \brief (FREQM) Number of instances */ +#define FREQM_INSTS { FREQM } /**< \brief (FREQM) Instances List */ + +#define GCLK ((Gclk *)0x40001C00UL) /**< \brief (GCLK) APB Base Address */ +#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ +#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ + +#define GMAC ((Gmac *)0x42000800UL) /**< \brief (GMAC) APB Base Address */ +#define GMAC_INST_NUM 1 /**< \brief (GMAC) Number of instances */ +#define GMAC_INSTS { GMAC } /**< \brief (GMAC) Instances List */ + +#define HMATRIX ((Hmatrixb *)0x4100C000UL) /**< \brief (HMATRIX) APB Base Address */ +#define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */ +#define HMATRIXB_INSTS { HMATRIX } /**< \brief (HMATRIXB) Instances List */ + +#define ICM ((Icm *)0x42002C00UL) /**< \brief (ICM) APB Base Address */ +#define ICM_INST_NUM 1 /**< \brief (ICM) Number of instances */ +#define ICM_INSTS { ICM } /**< \brief (ICM) Instances List */ + +#define I2S ((I2s *)0x43002800UL) /**< \brief (I2S) APB Base Address */ +#define I2S_INST_NUM 1 /**< \brief (I2S) Number of instances */ +#define I2S_INSTS { I2S } /**< \brief (I2S) Instances List */ + +#define MCLK ((Mclk *)0x40000800UL) /**< \brief (MCLK) APB Base Address */ +#define MCLK_INST_NUM 1 /**< \brief (MCLK) Number of instances */ +#define MCLK_INSTS { MCLK } /**< \brief (MCLK) Instances List */ + +#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ +#define NVMCTRL_SW0 (0x00800080UL) /**< \brief (NVMCTRL) SW0 Base Address */ +#define NVMCTRL_TEMP_LOG (0x00800100UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ +#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ +#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ +#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ + +#define OSCCTRL ((Oscctrl *)0x40001000UL) /**< \brief (OSCCTRL) APB Base Address */ +#define OSCCTRL_INST_NUM 1 /**< \brief (OSCCTRL) Number of instances */ +#define OSCCTRL_INSTS { OSCCTRL } /**< \brief (OSCCTRL) Instances List */ + +#define OSC32KCTRL ((Osc32kctrl *)0x40001400UL) /**< \brief (OSC32KCTRL) APB Base Address */ +#define OSC32KCTRL_INST_NUM 1 /**< \brief (OSC32KCTRL) Number of instances */ +#define OSC32KCTRL_INSTS { OSC32KCTRL } /**< \brief (OSC32KCTRL) Instances List */ + +#define PAC ((Pac *)0x40000000UL) /**< \brief (PAC) APB Base Address */ +#define PAC_INST_NUM 1 /**< \brief (PAC) Number of instances */ +#define PAC_INSTS { PAC } /**< \brief (PAC) Instances List */ + +#define PCC ((Pcc *)0x43002C00UL) /**< \brief (PCC) APB Base Address */ +#define PCC_INST_NUM 1 /**< \brief (PCC) Number of instances */ +#define PCC_INSTS { PCC } /**< \brief (PCC) Instances List */ + +#define PDEC ((Pdec *)0x42001C00UL) /**< \brief (PDEC) APB Base Address */ +#define PDEC_INST_NUM 1 /**< \brief (PDEC) Number of instances */ +#define PDEC_INSTS { PDEC } /**< \brief (PDEC) Instances List */ + +#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */ +#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ +#define PM_INSTS { PM } /**< \brief (PM) Instances List */ + +#define PORT ((Port *)0x41008000UL) /**< \brief (PORT) APB Base Address */ +#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ +#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ + +#define PUKCC ((void *)0x42003000UL) /**< \brief (PUKCC) APB Base Address */ +#define PUKCC_AHB ((void *)0x02000000UL) /**< \brief (PUKCC) AHB Base Address */ +#define PUKCC_INST_NUM 1 /**< \brief (PUKCC) Number of instances */ +#define PUKCC_INSTS { PUKCC } /**< \brief (PUKCC) Instances List */ + +#define QSPI ((Qspi *)0x42003400UL) /**< \brief (QSPI) APB Base Address */ +#define QSPI_AHB (0x04000000UL) /**< \brief (QSPI) AHB Base Address */ +#define QSPI_INST_NUM 1 /**< \brief (QSPI) Number of instances */ +#define QSPI_INSTS { QSPI } /**< \brief (QSPI) Instances List */ + +#define RAMECC ((Ramecc *)0x41020000UL) /**< \brief (RAMECC) APB Base Address */ +#define RAMECC_INST_NUM 1 /**< \brief (RAMECC) Number of instances */ +#define RAMECC_INSTS { RAMECC } /**< \brief (RAMECC) Instances List */ + +#define RSTC ((Rstc *)0x40000C00UL) /**< \brief (RSTC) APB Base Address */ +#define RSTC_INST_NUM 1 /**< \brief (RSTC) Number of instances */ +#define RSTC_INSTS { RSTC } /**< \brief (RSTC) Instances List */ + +#define RTC ((Rtc *)0x40002400UL) /**< \brief (RTC) APB Base Address */ +#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ +#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ + +#define SDHC0 ((Sdhc *)0x45000000UL) /**< \brief (SDHC0) AHB Base Address */ +#define SDHC1 ((Sdhc *)0x46000000UL) /**< \brief (SDHC1) AHB Base Address */ +#define SDHC_INST_NUM 2 /**< \brief (SDHC) Number of instances */ +#define SDHC_INSTS { SDHC0, SDHC1 } /**< \brief (SDHC) Instances List */ + +#define SERCOM0 ((Sercom *)0x40003000UL) /**< \brief (SERCOM0) APB Base Address */ +#define SERCOM1 ((Sercom *)0x40003400UL) /**< \brief (SERCOM1) APB Base Address */ +#define SERCOM2 ((Sercom *)0x41012000UL) /**< \brief (SERCOM2) APB Base Address */ +#define SERCOM3 ((Sercom *)0x41014000UL) /**< \brief (SERCOM3) APB Base Address */ +#define SERCOM4 ((Sercom *)0x43000000UL) /**< \brief (SERCOM4) APB Base Address */ +#define SERCOM5 ((Sercom *)0x43000400UL) /**< \brief (SERCOM5) APB Base Address */ +#define SERCOM6 ((Sercom *)0x43000800UL) /**< \brief (SERCOM6) APB Base Address */ +#define SERCOM7 ((Sercom *)0x43000C00UL) /**< \brief (SERCOM7) APB Base Address */ +#define SERCOM_INST_NUM 8 /**< \brief (SERCOM) Number of instances */ +#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5, SERCOM6, SERCOM7 } /**< \brief (SERCOM) Instances List */ + +#define SUPC ((Supc *)0x40001800UL) /**< \brief (SUPC) APB Base Address */ +#define SUPC_INST_NUM 1 /**< \brief (SUPC) Number of instances */ +#define SUPC_INSTS { SUPC } /**< \brief (SUPC) Instances List */ + +#define TC0 ((Tc *)0x40003800UL) /**< \brief (TC0) APB Base Address */ +#define TC1 ((Tc *)0x40003C00UL) /**< \brief (TC1) APB Base Address */ +#define TC2 ((Tc *)0x4101A000UL) /**< \brief (TC2) APB Base Address */ +#define TC3 ((Tc *)0x4101C000UL) /**< \brief (TC3) APB Base Address */ +#define TC4 ((Tc *)0x42001400UL) /**< \brief (TC4) APB Base Address */ +#define TC5 ((Tc *)0x42001800UL) /**< \brief (TC5) APB Base Address */ +#define TC6 ((Tc *)0x43001400UL) /**< \brief (TC6) APB Base Address */ +#define TC7 ((Tc *)0x43001800UL) /**< \brief (TC7) APB Base Address */ +#define TC_INST_NUM 8 /**< \brief (TC) Number of instances */ +#define TC_INSTS { TC0, TC1, TC2, TC3, TC4, TC5, TC6, TC7 } /**< \brief (TC) Instances List */ + +#define TCC0 ((Tcc *)0x41016000UL) /**< \brief (TCC0) APB Base Address */ +#define TCC1 ((Tcc *)0x41018000UL) /**< \brief (TCC1) APB Base Address */ +#define TCC2 ((Tcc *)0x42000C00UL) /**< \brief (TCC2) APB Base Address */ +#define TCC3 ((Tcc *)0x42001000UL) /**< \brief (TCC3) APB Base Address */ +#define TCC4 ((Tcc *)0x43001000UL) /**< \brief (TCC4) APB Base Address */ +#define TCC_INST_NUM 5 /**< \brief (TCC) Number of instances */ +#define TCC_INSTS { TCC0, TCC1, TCC2, TCC3, TCC4 } /**< \brief (TCC) Instances List */ + +#define TRNG ((Trng *)0x42002800UL) /**< \brief (TRNG) APB Base Address */ +#define TRNG_INST_NUM 1 /**< \brief (TRNG) Number of instances */ +#define TRNG_INSTS { TRNG } /**< \brief (TRNG) Instances List */ + +#define USB ((Usb *)0x41000000UL) /**< \brief (USB) APB Base Address */ +#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ +#define USB_INSTS { USB } /**< \brief (USB) Instances List */ + +#define WDT ((Wdt *)0x40002000UL) /**< \brief (WDT) APB Base Address */ +#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ +#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ + +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/*@}*/ + +/* ************************************************************************** */ +/** PORT DEFINITIONS FOR SAME54P19A */ +/* ************************************************************************** */ +/** \defgroup SAME54P19A_port PORT Definitions */ +/*@{*/ + +#include "pio/same54p19a.h" +/*@}*/ + +/* ************************************************************************** */ +/** MEMORY MAPPING DEFINITIONS FOR SAME54P19A */ +/* ************************************************************************** */ + +#define HSRAM_SIZE _UL_(0x00030000) /* 192 kB */ +#define FLASH_SIZE _UL_(0x00080000) /* 512 kB */ +#define FLASH_PAGE_SIZE 512 +#define FLASH_NB_OF_PAGES 1024 +#define FLASH_USER_PAGE_SIZE 512 +#define BKUPRAM_SIZE _UL_(0x00002000) /* 8 kB */ +#define QSPI_SIZE _UL_(0x01000000) /* 16384 kB */ + +#define FLASH_ADDR _UL_(0x00000000) /**< FLASH base address */ +#define CMCC_DATARAM_ADDR _UL_(0x03000000) /**< CMCC_DATARAM base address */ +#define CMCC_DATARAM_SIZE _UL_(0x00001000) /**< CMCC_DATARAM size */ +#define CMCC_TAGRAM_ADDR _UL_(0x03001000) /**< CMCC_TAGRAM base address */ +#define CMCC_TAGRAM_SIZE _UL_(0x00000400) /**< CMCC_TAGRAM size */ +#define CMCC_VALIDRAM_ADDR _UL_(0x03002000) /**< CMCC_VALIDRAM base address */ +#define CMCC_VALIDRAM_SIZE _UL_(0x00000040) /**< CMCC_VALIDRAM size */ +#define HSRAM_ADDR _UL_(0x20000000) /**< HSRAM base address */ +#define HSRAM_ETB_ADDR _UL_(0x20000000) /**< HSRAM_ETB base address */ +#define HSRAM_ETB_SIZE _UL_(0x00008000) /**< HSRAM_ETB size */ +#define HSRAM_RET1_ADDR _UL_(0x20000000) /**< HSRAM_RET1 base address */ +#define HSRAM_RET1_SIZE _UL_(0x00008000) /**< HSRAM_RET1 size */ +#define HPB0_ADDR _UL_(0x40000000) /**< HPB0 base address */ +#define HPB1_ADDR _UL_(0x41000000) /**< HPB1 base address */ +#define HPB2_ADDR _UL_(0x42000000) /**< HPB2 base address */ +#define HPB3_ADDR _UL_(0x43000000) /**< HPB3 base address */ +#define SEEPROM_ADDR _UL_(0x44000000) /**< SEEPROM base address */ +#define BKUPRAM_ADDR _UL_(0x47000000) /**< BKUPRAM base address */ +#define PPB_ADDR _UL_(0xE0000000) /**< PPB base address */ + +#define DSU_DID_RESETVALUE _UL_(0x61840301) +#define ADC0_TOUCH_LINES_NUM 32 +#define PORT_GROUPS 4 + +/* ************************************************************************** */ +/** ELECTRICAL DEFINITIONS FOR SAME54P19A */ +/* ************************************************************************** */ + + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* SAME54P19A_H */ diff --git a/arch/arm/SAME54/SAME54A/mcu/inc/same54p20a.h b/arch/arm/SAME54/SAME54A/mcu/inc/same54p20a.h index ce9e2e93..2446095b 100644 --- a/arch/arm/SAME54/SAME54A/mcu/inc/same54p20a.h +++ b/arch/arm/SAME54/SAME54A/mcu/inc/same54p20a.h @@ -1,1113 +1,1085 @@ -/** - * \brief Header file for ATSAME54P20A - * - * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries. - * - * Subject to your compliance with these terms, you may use Microchip software and any derivatives - * exclusively with Microchip products. It is your responsibility to comply with third party license - * terms applicable to your use of third party software (including open source software) that may - * accompany Microchip software. - * - * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, - * APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND - * FITNESS FOR A PARTICULAR PURPOSE. - * - * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL - * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF - * MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT - * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT - * EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. - * - */ - -/* file generated from device description version 2020-03-12T17:27:04Z */ -#ifndef _SAME54P20A_H_ -#define _SAME54P20A_H_ - -// Header version uses Semantic Versioning 2.0.0 (https://semver.org/) -#define HEADER_FORMAT_VERSION "2.0.0" - -#define HEADER_FORMAT_VERSION_MAJOR (2) -#define HEADER_FORMAT_VERSION_MINOR (0) - -/** \addtogroup SAME54P20A_definitions SAME54P20A definitions - This file defines all structures and symbols for SAME54P20A: - - registers and bitfields - - peripheral base address - - peripheral ID - - PIO definitions - * @{ - */ - -#ifdef __cplusplus - extern "C" { -#endif - -#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) -# include -#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#if !defined(SKIP_INTEGER_LITERALS) -# if defined(_U_) || defined(_L_) || defined(_UL_) -# error "Integer Literals macros already defined elsewhere" -# endif - -#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) -/* Macros that deal with adding suffixes to integer literal constants for C/C++ */ -# define _U_(x) (x ## U) /**< C code: Unsigned integer literal constant value */ -# define _L_(x) (x ## L) /**< C code: Long integer literal constant value */ -# define _UL_(x) (x ## UL) /**< C code: Unsigned Long integer literal constant value */ - -#else /* Assembler */ - -# define _U_(x) x /**< Assembler: Unsigned integer literal constant value */ -# define _L_(x) x /**< Assembler: Long integer literal constant value */ -# define _UL_(x) x /**< Assembler: Unsigned Long integer literal constant value */ -#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ -#endif /* SKIP_INTEGER_LITERALS */ -/** @} end of Atmel Global Defines */ - -/* ************************************************************************** */ -/* CMSIS DEFINITIONS FOR SAME54P20A */ -/* ************************************************************************** */ -#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) -/** Interrupt Number Definition */ -typedef enum IRQn -{ -/****** CORTEX-M4 Processor Exceptions Numbers ******************************/ - Reset_IRQn = -15, /**< -15 Reset Vector, invoked on Power up and warm reset */ - NonMaskableInt_IRQn = -14, /**< -14 Non maskable Interrupt, cannot be stopped or preempted */ - HardFault_IRQn = -13, /**< -13 Hard Fault, all classes of Fault */ - MemoryManagement_IRQn = -12, /**< -12 Memory Management, MPU mismatch, including Access Violation and No Match */ - BusFault_IRQn = -11, /**< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */ - UsageFault_IRQn = -10, /**< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ - SVCall_IRQn = -5, /**< -5 System Service Call via SVC instruction */ - DebugMonitor_IRQn = -4, /**< -4 Debug Monitor */ - PendSV_IRQn = -2, /**< -2 Pendable request for system service */ - SysTick_IRQn = -1, /**< -1 System Tick Timer */ -/****** SAME54P20A specific Interrupt Numbers ***********************************/ - PM_IRQn = 0, /**< 0 Power Manager (PM) */ - MCLK_IRQn = 1, /**< 1 Main Clock (MCLK) */ - OSCCTRL_XOSC0_IRQn = 2, /**< 2 Oscillators Control (OSCCTRL) */ - OSCCTRL_XOSC1_IRQn = 3, /**< 3 Oscillators Control (OSCCTRL) */ - OSCCTRL_DFLL_IRQn = 4, /**< 4 Oscillators Control (OSCCTRL) */ - OSCCTRL_DPLL0_IRQn = 5, /**< 5 Oscillators Control (OSCCTRL) */ - OSCCTRL_DPLL1_IRQn = 6, /**< 6 Oscillators Control (OSCCTRL) */ - OSC32KCTRL_IRQn = 7, /**< 7 32kHz Oscillators Control (OSC32KCTRL) */ - SUPC_OTHER_IRQn = 8, /**< 8 Supply Controller (SUPC) */ - SUPC_BODDET_IRQn = 9, /**< 9 Supply Controller (SUPC) */ - WDT_IRQn = 10, /**< 10 Watchdog Timer (WDT) */ - RTC_IRQn = 11, /**< 11 Real-Time Counter (RTC) */ - EIC_EXTINT_0_IRQn = 12, /**< 12 External Interrupt Controller (EIC) */ - EIC_EXTINT_1_IRQn = 13, /**< 13 External Interrupt Controller (EIC) */ - EIC_EXTINT_2_IRQn = 14, /**< 14 External Interrupt Controller (EIC) */ - EIC_EXTINT_3_IRQn = 15, /**< 15 External Interrupt Controller (EIC) */ - EIC_EXTINT_4_IRQn = 16, /**< 16 External Interrupt Controller (EIC) */ - EIC_EXTINT_5_IRQn = 17, /**< 17 External Interrupt Controller (EIC) */ - EIC_EXTINT_6_IRQn = 18, /**< 18 External Interrupt Controller (EIC) */ - EIC_EXTINT_7_IRQn = 19, /**< 19 External Interrupt Controller (EIC) */ - EIC_EXTINT_8_IRQn = 20, /**< 20 External Interrupt Controller (EIC) */ - EIC_EXTINT_9_IRQn = 21, /**< 21 External Interrupt Controller (EIC) */ - EIC_EXTINT_10_IRQn = 22, /**< 22 External Interrupt Controller (EIC) */ - EIC_EXTINT_11_IRQn = 23, /**< 23 External Interrupt Controller (EIC) */ - EIC_EXTINT_12_IRQn = 24, /**< 24 External Interrupt Controller (EIC) */ - EIC_EXTINT_13_IRQn = 25, /**< 25 External Interrupt Controller (EIC) */ - EIC_EXTINT_14_IRQn = 26, /**< 26 External Interrupt Controller (EIC) */ - EIC_EXTINT_15_IRQn = 27, /**< 27 External Interrupt Controller (EIC) */ - FREQM_IRQn = 28, /**< 28 Frequency Meter (FREQM) */ - NVMCTRL_0_IRQn = 29, /**< 29 Non-Volatile Memory Controller (NVMCTRL) */ - NVMCTRL_1_IRQn = 30, /**< 30 Non-Volatile Memory Controller (NVMCTRL) */ - DMAC_0_IRQn = 31, /**< 31 Direct Memory Access Controller (DMAC) */ - DMAC_1_IRQn = 32, /**< 32 Direct Memory Access Controller (DMAC) */ - DMAC_2_IRQn = 33, /**< 33 Direct Memory Access Controller (DMAC) */ - DMAC_3_IRQn = 34, /**< 34 Direct Memory Access Controller (DMAC) */ - DMAC_OTHER_IRQn = 35, /**< 35 Direct Memory Access Controller (DMAC) */ - EVSYS_0_IRQn = 36, /**< 36 Event System Interface (EVSYS) */ - EVSYS_1_IRQn = 37, /**< 37 Event System Interface (EVSYS) */ - EVSYS_2_IRQn = 38, /**< 38 Event System Interface (EVSYS) */ - EVSYS_3_IRQn = 39, /**< 39 Event System Interface (EVSYS) */ - EVSYS_OTHER_IRQn = 40, /**< 40 Event System Interface (EVSYS) */ - PAC_IRQn = 41, /**< 41 Peripheral Access Controller (PAC) */ - RAMECC_IRQn = 45, /**< 45 RAM ECC (RAMECC) */ - SERCOM0_0_IRQn = 46, /**< 46 Serial Communication Interface (SERCOM0) */ - SERCOM0_1_IRQn = 47, /**< 47 Serial Communication Interface (SERCOM0) */ - SERCOM0_2_IRQn = 48, /**< 48 Serial Communication Interface (SERCOM0) */ - SERCOM0_OTHER_IRQn = 49, /**< 49 Serial Communication Interface (SERCOM0) */ - SERCOM1_0_IRQn = 50, /**< 50 Serial Communication Interface (SERCOM1) */ - SERCOM1_1_IRQn = 51, /**< 51 Serial Communication Interface (SERCOM1) */ - SERCOM1_2_IRQn = 52, /**< 52 Serial Communication Interface (SERCOM1) */ - SERCOM1_OTHER_IRQn = 53, /**< 53 Serial Communication Interface (SERCOM1) */ - SERCOM2_0_IRQn = 54, /**< 54 Serial Communication Interface (SERCOM2) */ - SERCOM2_1_IRQn = 55, /**< 55 Serial Communication Interface (SERCOM2) */ - SERCOM2_2_IRQn = 56, /**< 56 Serial Communication Interface (SERCOM2) */ - SERCOM2_OTHER_IRQn = 57, /**< 57 Serial Communication Interface (SERCOM2) */ - SERCOM3_0_IRQn = 58, /**< 58 Serial Communication Interface (SERCOM3) */ - SERCOM3_1_IRQn = 59, /**< 59 Serial Communication Interface (SERCOM3) */ - SERCOM3_2_IRQn = 60, /**< 60 Serial Communication Interface (SERCOM3) */ - SERCOM3_OTHER_IRQn = 61, /**< 61 Serial Communication Interface (SERCOM3) */ - SERCOM4_0_IRQn = 62, /**< 62 Serial Communication Interface (SERCOM4) */ - SERCOM4_1_IRQn = 63, /**< 63 Serial Communication Interface (SERCOM4) */ - SERCOM4_2_IRQn = 64, /**< 64 Serial Communication Interface (SERCOM4) */ - SERCOM4_OTHER_IRQn = 65, /**< 65 Serial Communication Interface (SERCOM4) */ - SERCOM5_0_IRQn = 66, /**< 66 Serial Communication Interface (SERCOM5) */ - SERCOM5_1_IRQn = 67, /**< 67 Serial Communication Interface (SERCOM5) */ - SERCOM5_2_IRQn = 68, /**< 68 Serial Communication Interface (SERCOM5) */ - SERCOM5_OTHER_IRQn = 69, /**< 69 Serial Communication Interface (SERCOM5) */ - SERCOM6_0_IRQn = 70, /**< 70 Serial Communication Interface (SERCOM6) */ - SERCOM6_1_IRQn = 71, /**< 71 Serial Communication Interface (SERCOM6) */ - SERCOM6_2_IRQn = 72, /**< 72 Serial Communication Interface (SERCOM6) */ - SERCOM6_OTHER_IRQn = 73, /**< 73 Serial Communication Interface (SERCOM6) */ - SERCOM7_0_IRQn = 74, /**< 74 Serial Communication Interface (SERCOM7) */ - SERCOM7_1_IRQn = 75, /**< 75 Serial Communication Interface (SERCOM7) */ - SERCOM7_2_IRQn = 76, /**< 76 Serial Communication Interface (SERCOM7) */ - SERCOM7_OTHER_IRQn = 77, /**< 77 Serial Communication Interface (SERCOM7) */ - CAN0_IRQn = 78, /**< 78 Control Area Network (CAN0) */ - CAN1_IRQn = 79, /**< 79 Control Area Network (CAN1) */ - USB_OTHER_IRQn = 80, /**< 80 Universal Serial Bus (USB) */ - USB_SOF_HSOF_IRQn = 81, /**< 81 Universal Serial Bus (USB) */ - USB_TRCPT0_IRQn = 82, /**< 82 Universal Serial Bus (USB) */ - USB_TRCPT1_IRQn = 83, /**< 83 Universal Serial Bus (USB) */ - GMAC_IRQn = 84, /**< 84 Ethernet MAC (GMAC) */ - TCC0_OTHER_IRQn = 85, /**< 85 Timer Counter Control (TCC0) */ - TCC0_MC0_IRQn = 86, /**< 86 Timer Counter Control (TCC0) */ - TCC0_MC1_IRQn = 87, /**< 87 Timer Counter Control (TCC0) */ - TCC0_MC2_IRQn = 88, /**< 88 Timer Counter Control (TCC0) */ - TCC0_MC3_IRQn = 89, /**< 89 Timer Counter Control (TCC0) */ - TCC0_MC4_IRQn = 90, /**< 90 Timer Counter Control (TCC0) */ - TCC0_MC5_IRQn = 91, /**< 91 Timer Counter Control (TCC0) */ - TCC1_OTHER_IRQn = 92, /**< 92 Timer Counter Control (TCC1) */ - TCC1_MC0_IRQn = 93, /**< 93 Timer Counter Control (TCC1) */ - TCC1_MC1_IRQn = 94, /**< 94 Timer Counter Control (TCC1) */ - TCC1_MC2_IRQn = 95, /**< 95 Timer Counter Control (TCC1) */ - TCC1_MC3_IRQn = 96, /**< 96 Timer Counter Control (TCC1) */ - TCC2_OTHER_IRQn = 97, /**< 97 Timer Counter Control (TCC2) */ - TCC2_MC0_IRQn = 98, /**< 98 Timer Counter Control (TCC2) */ - TCC2_MC1_IRQn = 99, /**< 99 Timer Counter Control (TCC2) */ - TCC2_MC2_IRQn = 100, /**< 100 Timer Counter Control (TCC2) */ - TCC3_OTHER_IRQn = 101, /**< 101 Timer Counter Control (TCC3) */ - TCC3_MC0_IRQn = 102, /**< 102 Timer Counter Control (TCC3) */ - TCC3_MC1_IRQn = 103, /**< 103 Timer Counter Control (TCC3) */ - TCC4_OTHER_IRQn = 104, /**< 104 Timer Counter Control (TCC4) */ - TCC4_MC0_IRQn = 105, /**< 105 Timer Counter Control (TCC4) */ - TCC4_MC1_IRQn = 106, /**< 106 Timer Counter Control (TCC4) */ - TC0_IRQn = 107, /**< 107 Basic Timer Counter (TC0) */ - TC1_IRQn = 108, /**< 108 Basic Timer Counter (TC1) */ - TC2_IRQn = 109, /**< 109 Basic Timer Counter (TC2) */ - TC3_IRQn = 110, /**< 110 Basic Timer Counter (TC3) */ - TC4_IRQn = 111, /**< 111 Basic Timer Counter (TC4) */ - TC5_IRQn = 112, /**< 112 Basic Timer Counter (TC5) */ - TC6_IRQn = 113, /**< 113 Basic Timer Counter (TC6) */ - TC7_IRQn = 114, /**< 114 Basic Timer Counter (TC7) */ - PDEC_OTHER_IRQn = 115, /**< 115 Quadrature Decodeur (PDEC) */ - PDEC_MC0_IRQn = 116, /**< 116 Quadrature Decodeur (PDEC) */ - PDEC_MC1_IRQn = 117, /**< 117 Quadrature Decodeur (PDEC) */ - ADC0_OTHER_IRQn = 118, /**< 118 Analog Digital Converter (ADC0) */ - ADC0_RESRDY_IRQn = 119, /**< 119 Analog Digital Converter (ADC0) */ - ADC1_OTHER_IRQn = 120, /**< 120 Analog Digital Converter (ADC1) */ - ADC1_RESRDY_IRQn = 121, /**< 121 Analog Digital Converter (ADC1) */ - AC_IRQn = 122, /**< 122 Analog Comparators (AC) */ - DAC_OTHER_IRQn = 123, /**< 123 Digital-to-Analog Converter (DAC) */ - DAC_EMPTY_0_IRQn = 124, /**< 124 Digital-to-Analog Converter (DAC) */ - DAC_EMPTY_1_IRQn = 125, /**< 125 Digital-to-Analog Converter (DAC) */ - DAC_RESRDY_0_IRQn = 126, /**< 126 Digital-to-Analog Converter (DAC) */ - DAC_RESRDY_1_IRQn = 127, /**< 127 Digital-to-Analog Converter (DAC) */ - I2S_IRQn = 128, /**< 128 Inter-IC Sound Interface (I2S) */ - PCC_IRQn = 129, /**< 129 Parallel Capture Controller (PCC) */ - AES_IRQn = 130, /**< 130 Advanced Encryption Standard (AES) */ - TRNG_IRQn = 131, /**< 131 True Random Generator (TRNG) */ - ICM_IRQn = 132, /**< 132 Integrity Check Monitor (ICM) */ - PUKCC_IRQn = 133, /**< 133 PUblic-Key Cryptography Controller (PUKCC) */ - QSPI_IRQn = 134, /**< 134 Quad SPI interface (QSPI) */ - SDHC0_IRQn = 135, /**< 135 SD/MMC Host Controller (SDHC0) */ - SDHC1_IRQn = 136, /**< 136 SD/MMC Host Controller (SDHC1) */ - - PERIPH_MAX_IRQn = 136 /**< Max peripheral ID */ -} IRQn_Type; -#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) -typedef struct _DeviceVectors -{ - /* Stack pointer */ - void* pvStack; - /* Cortex-M handlers */ - void* pfnReset_Handler; /* -15 Reset Vector, invoked on Power up and warm reset */ - void* pfnNonMaskableInt_Handler; /* -14 Non maskable Interrupt, cannot be stopped or preempted */ - void* pfnHardFault_Handler; /* -13 Hard Fault, all classes of Fault */ - void* pfnMemoryManagement_Handler; /* -12 Memory Management, MPU mismatch, including Access Violation and No Match */ - void* pfnBusFault_Handler; /* -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */ - void* pfnUsageFault_Handler; /* -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ - void* pvReservedC9; - void* pvReservedC8; - void* pvReservedC7; - void* pvReservedC6; - void* pfnSVCall_Handler; /* -5 System Service Call via SVC instruction */ - void* pfnDebugMonitor_Handler; /* -4 Debug Monitor */ - void* pvReservedC3; - void* pfnPendSV_Handler; /* -2 Pendable request for system service */ - void* pfnSysTick_Handler; /* -1 System Tick Timer */ - - /* Peripheral handlers */ - void* pfnPM_Handler; /* 0 Power Manager (PM) */ - void* pfnMCLK_Handler; /* 1 Main Clock (MCLK) */ - void* pfnOSCCTRL_XOSC0_Handler; /* 2 Oscillators Control (OSCCTRL) */ - void* pfnOSCCTRL_XOSC1_Handler; /* 3 Oscillators Control (OSCCTRL) */ - void* pfnOSCCTRL_DFLL_Handler; /* 4 Oscillators Control (OSCCTRL) */ - void* pfnOSCCTRL_DPLL0_Handler; /* 5 Oscillators Control (OSCCTRL) */ - void* pfnOSCCTRL_DPLL1_Handler; /* 6 Oscillators Control (OSCCTRL) */ - void* pfnOSC32KCTRL_Handler; /* 7 32kHz Oscillators Control (OSC32KCTRL) */ - void* pfnSUPC_OTHER_Handler; /* 8 Supply Controller (SUPC) */ - void* pfnSUPC_BODDET_Handler; /* 9 Supply Controller (SUPC) */ - void* pfnWDT_Handler; /* 10 Watchdog Timer (WDT) */ - void* pfnRTC_Handler; /* 11 Real-Time Counter (RTC) */ - void* pfnEIC_EXTINT_0_Handler; /* 12 External Interrupt Controller (EIC) */ - void* pfnEIC_EXTINT_1_Handler; /* 13 External Interrupt Controller (EIC) */ - void* pfnEIC_EXTINT_2_Handler; /* 14 External Interrupt Controller (EIC) */ - void* pfnEIC_EXTINT_3_Handler; /* 15 External Interrupt Controller (EIC) */ - void* pfnEIC_EXTINT_4_Handler; /* 16 External Interrupt Controller (EIC) */ - void* pfnEIC_EXTINT_5_Handler; /* 17 External Interrupt Controller (EIC) */ - void* pfnEIC_EXTINT_6_Handler; /* 18 External Interrupt Controller (EIC) */ - void* pfnEIC_EXTINT_7_Handler; /* 19 External Interrupt Controller (EIC) */ - void* pfnEIC_EXTINT_8_Handler; /* 20 External Interrupt Controller (EIC) */ - void* pfnEIC_EXTINT_9_Handler; /* 21 External Interrupt Controller (EIC) */ - void* pfnEIC_EXTINT_10_Handler; /* 22 External Interrupt Controller (EIC) */ - void* pfnEIC_EXTINT_11_Handler; /* 23 External Interrupt Controller (EIC) */ - void* pfnEIC_EXTINT_12_Handler; /* 24 External Interrupt Controller (EIC) */ - void* pfnEIC_EXTINT_13_Handler; /* 25 External Interrupt Controller (EIC) */ - void* pfnEIC_EXTINT_14_Handler; /* 26 External Interrupt Controller (EIC) */ - void* pfnEIC_EXTINT_15_Handler; /* 27 External Interrupt Controller (EIC) */ - void* pfnFREQM_Handler; /* 28 Frequency Meter (FREQM) */ - void* pfnNVMCTRL_0_Handler; /* 29 Non-Volatile Memory Controller (NVMCTRL) */ - void* pfnNVMCTRL_1_Handler; /* 30 Non-Volatile Memory Controller (NVMCTRL) */ - void* pfnDMAC_0_Handler; /* 31 Direct Memory Access Controller (DMAC) */ - void* pfnDMAC_1_Handler; /* 32 Direct Memory Access Controller (DMAC) */ - void* pfnDMAC_2_Handler; /* 33 Direct Memory Access Controller (DMAC) */ - void* pfnDMAC_3_Handler; /* 34 Direct Memory Access Controller (DMAC) */ - void* pfnDMAC_OTHER_Handler; /* 35 Direct Memory Access Controller (DMAC) */ - void* pfnEVSYS_0_Handler; /* 36 Event System Interface (EVSYS) */ - void* pfnEVSYS_1_Handler; /* 37 Event System Interface (EVSYS) */ - void* pfnEVSYS_2_Handler; /* 38 Event System Interface (EVSYS) */ - void* pfnEVSYS_3_Handler; /* 39 Event System Interface (EVSYS) */ - void* pfnEVSYS_OTHER_Handler; /* 40 Event System Interface (EVSYS) */ - void* pfnPAC_Handler; /* 41 Peripheral Access Controller (PAC) */ - void* pvReserved42; - void* pvReserved43; - void* pvReserved44; - void* pfnRAMECC_Handler; /* 45 RAM ECC (RAMECC) */ - void* pfnSERCOM0_0_Handler; /* 46 Serial Communication Interface (SERCOM0) */ - void* pfnSERCOM0_1_Handler; /* 47 Serial Communication Interface (SERCOM0) */ - void* pfnSERCOM0_2_Handler; /* 48 Serial Communication Interface (SERCOM0) */ - void* pfnSERCOM0_OTHER_Handler; /* 49 Serial Communication Interface (SERCOM0) */ - void* pfnSERCOM1_0_Handler; /* 50 Serial Communication Interface (SERCOM1) */ - void* pfnSERCOM1_1_Handler; /* 51 Serial Communication Interface (SERCOM1) */ - void* pfnSERCOM1_2_Handler; /* 52 Serial Communication Interface (SERCOM1) */ - void* pfnSERCOM1_OTHER_Handler; /* 53 Serial Communication Interface (SERCOM1) */ - void* pfnSERCOM2_0_Handler; /* 54 Serial Communication Interface (SERCOM2) */ - void* pfnSERCOM2_1_Handler; /* 55 Serial Communication Interface (SERCOM2) */ - void* pfnSERCOM2_2_Handler; /* 56 Serial Communication Interface (SERCOM2) */ - void* pfnSERCOM2_OTHER_Handler; /* 57 Serial Communication Interface (SERCOM2) */ - void* pfnSERCOM3_0_Handler; /* 58 Serial Communication Interface (SERCOM3) */ - void* pfnSERCOM3_1_Handler; /* 59 Serial Communication Interface (SERCOM3) */ - void* pfnSERCOM3_2_Handler; /* 60 Serial Communication Interface (SERCOM3) */ - void* pfnSERCOM3_OTHER_Handler; /* 61 Serial Communication Interface (SERCOM3) */ - void* pfnSERCOM4_0_Handler; /* 62 Serial Communication Interface (SERCOM4) */ - void* pfnSERCOM4_1_Handler; /* 63 Serial Communication Interface (SERCOM4) */ - void* pfnSERCOM4_2_Handler; /* 64 Serial Communication Interface (SERCOM4) */ - void* pfnSERCOM4_OTHER_Handler; /* 65 Serial Communication Interface (SERCOM4) */ - void* pfnSERCOM5_0_Handler; /* 66 Serial Communication Interface (SERCOM5) */ - void* pfnSERCOM5_1_Handler; /* 67 Serial Communication Interface (SERCOM5) */ - void* pfnSERCOM5_2_Handler; /* 68 Serial Communication Interface (SERCOM5) */ - void* pfnSERCOM5_OTHER_Handler; /* 69 Serial Communication Interface (SERCOM5) */ - void* pfnSERCOM6_0_Handler; /* 70 Serial Communication Interface (SERCOM6) */ - void* pfnSERCOM6_1_Handler; /* 71 Serial Communication Interface (SERCOM6) */ - void* pfnSERCOM6_2_Handler; /* 72 Serial Communication Interface (SERCOM6) */ - void* pfnSERCOM6_OTHER_Handler; /* 73 Serial Communication Interface (SERCOM6) */ - void* pfnSERCOM7_0_Handler; /* 74 Serial Communication Interface (SERCOM7) */ - void* pfnSERCOM7_1_Handler; /* 75 Serial Communication Interface (SERCOM7) */ - void* pfnSERCOM7_2_Handler; /* 76 Serial Communication Interface (SERCOM7) */ - void* pfnSERCOM7_OTHER_Handler; /* 77 Serial Communication Interface (SERCOM7) */ - void* pfnCAN0_Handler; /* 78 Control Area Network (CAN0) */ - void* pfnCAN1_Handler; /* 79 Control Area Network (CAN1) */ - void* pfnUSB_OTHER_Handler; /* 80 Universal Serial Bus (USB) */ - void* pfnUSB_SOF_HSOF_Handler; /* 81 Universal Serial Bus (USB) */ - void* pfnUSB_TRCPT0_Handler; /* 82 Universal Serial Bus (USB) */ - void* pfnUSB_TRCPT1_Handler; /* 83 Universal Serial Bus (USB) */ - void* pfnGMAC_Handler; /* 84 Ethernet MAC (GMAC) */ - void* pfnTCC0_OTHER_Handler; /* 85 Timer Counter Control (TCC0) */ - void* pfnTCC0_MC0_Handler; /* 86 Timer Counter Control (TCC0) */ - void* pfnTCC0_MC1_Handler; /* 87 Timer Counter Control (TCC0) */ - void* pfnTCC0_MC2_Handler; /* 88 Timer Counter Control (TCC0) */ - void* pfnTCC0_MC3_Handler; /* 89 Timer Counter Control (TCC0) */ - void* pfnTCC0_MC4_Handler; /* 90 Timer Counter Control (TCC0) */ - void* pfnTCC0_MC5_Handler; /* 91 Timer Counter Control (TCC0) */ - void* pfnTCC1_OTHER_Handler; /* 92 Timer Counter Control (TCC1) */ - void* pfnTCC1_MC0_Handler; /* 93 Timer Counter Control (TCC1) */ - void* pfnTCC1_MC1_Handler; /* 94 Timer Counter Control (TCC1) */ - void* pfnTCC1_MC2_Handler; /* 95 Timer Counter Control (TCC1) */ - void* pfnTCC1_MC3_Handler; /* 96 Timer Counter Control (TCC1) */ - void* pfnTCC2_OTHER_Handler; /* 97 Timer Counter Control (TCC2) */ - void* pfnTCC2_MC0_Handler; /* 98 Timer Counter Control (TCC2) */ - void* pfnTCC2_MC1_Handler; /* 99 Timer Counter Control (TCC2) */ - void* pfnTCC2_MC2_Handler; /* 100 Timer Counter Control (TCC2) */ - void* pfnTCC3_OTHER_Handler; /* 101 Timer Counter Control (TCC3) */ - void* pfnTCC3_MC0_Handler; /* 102 Timer Counter Control (TCC3) */ - void* pfnTCC3_MC1_Handler; /* 103 Timer Counter Control (TCC3) */ - void* pfnTCC4_OTHER_Handler; /* 104 Timer Counter Control (TCC4) */ - void* pfnTCC4_MC0_Handler; /* 105 Timer Counter Control (TCC4) */ - void* pfnTCC4_MC1_Handler; /* 106 Timer Counter Control (TCC4) */ - void* pfnTC0_Handler; /* 107 Basic Timer Counter (TC0) */ - void* pfnTC1_Handler; /* 108 Basic Timer Counter (TC1) */ - void* pfnTC2_Handler; /* 109 Basic Timer Counter (TC2) */ - void* pfnTC3_Handler; /* 110 Basic Timer Counter (TC3) */ - void* pfnTC4_Handler; /* 111 Basic Timer Counter (TC4) */ - void* pfnTC5_Handler; /* 112 Basic Timer Counter (TC5) */ - void* pfnTC6_Handler; /* 113 Basic Timer Counter (TC6) */ - void* pfnTC7_Handler; /* 114 Basic Timer Counter (TC7) */ - void* pfnPDEC_OTHER_Handler; /* 115 Quadrature Decodeur (PDEC) */ - void* pfnPDEC_MC0_Handler; /* 116 Quadrature Decodeur (PDEC) */ - void* pfnPDEC_MC1_Handler; /* 117 Quadrature Decodeur (PDEC) */ - void* pfnADC0_OTHER_Handler; /* 118 Analog Digital Converter (ADC0) */ - void* pfnADC0_RESRDY_Handler; /* 119 Analog Digital Converter (ADC0) */ - void* pfnADC1_OTHER_Handler; /* 120 Analog Digital Converter (ADC1) */ - void* pfnADC1_RESRDY_Handler; /* 121 Analog Digital Converter (ADC1) */ - void* pfnAC_Handler; /* 122 Analog Comparators (AC) */ - void* pfnDAC_OTHER_Handler; /* 123 Digital-to-Analog Converter (DAC) */ - void* pfnDAC_EMPTY_0_Handler; /* 124 Digital-to-Analog Converter (DAC) */ - void* pfnDAC_EMPTY_1_Handler; /* 125 Digital-to-Analog Converter (DAC) */ - void* pfnDAC_RESRDY_0_Handler; /* 126 Digital-to-Analog Converter (DAC) */ - void* pfnDAC_RESRDY_1_Handler; /* 127 Digital-to-Analog Converter (DAC) */ - void* pfnI2S_Handler; /* 128 Inter-IC Sound Interface (I2S) */ - void* pfnPCC_Handler; /* 129 Parallel Capture Controller (PCC) */ - void* pfnAES_Handler; /* 130 Advanced Encryption Standard (AES) */ - void* pfnTRNG_Handler; /* 131 True Random Generator (TRNG) */ - void* pfnICM_Handler; /* 132 Integrity Check Monitor (ICM) */ - void* pfnPUKCC_Handler; /* 133 PUblic-Key Cryptography Controller (PUKCC) */ - void* pfnQSPI_Handler; /* 134 Quad SPI interface (QSPI) */ - void* pfnSDHC0_Handler; /* 135 SD/MMC Host Controller (SDHC0) */ - void* pfnSDHC1_Handler; /* 136 SD/MMC Host Controller (SDHC1) */ -} DeviceVectors; - -/* Defines for Deprecated Interrupt and Exceptions handler names */ -#define pfnMemManage_Handler pfnMemoryManagement_Handler /**< \deprecated Backward compatibility for ASF*/ -#define pfnDebugMon_Handler pfnDebugMonitor_Handler /**< \deprecated Backward compatibility for ASF*/ -#define pfnNMI_Handler pfnNonMaskableInt_Handler /**< \deprecated Backward compatibility for ASF*/ -#define pfnSVC_Handler pfnSVCall_Handler /**< \deprecated Backward compatibility for ASF*/ - -#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) -#if !defined DONT_USE_PREDEFINED_CORE_HANDLERS -/* CORTEX-M4 exception handlers */ -void Reset_Handler ( void ); -void NonMaskableInt_Handler ( void ); -void HardFault_Handler ( void ); -void MemoryManagement_Handler ( void ); -void BusFault_Handler ( void ); -void UsageFault_Handler ( void ); -void SVCall_Handler ( void ); -void DebugMonitor_Handler ( void ); -void PendSV_Handler ( void ); -void SysTick_Handler ( void ); -#endif /* DONT_USE_PREDEFINED_CORE_HANDLERS */ - -#if !defined DONT_USE_PREDEFINED_PERIPHERALS_HANDLERS -/* Peripherals interrupt handlers */ -void PM_Handler ( void ); -void MCLK_Handler ( void ); -void OSCCTRL_XOSC0_Handler ( void ); -void OSCCTRL_XOSC1_Handler ( void ); -void OSCCTRL_DFLL_Handler ( void ); -void OSCCTRL_DPLL0_Handler ( void ); -void OSCCTRL_DPLL1_Handler ( void ); -void OSC32KCTRL_Handler ( void ); -void SUPC_OTHER_Handler ( void ); -void SUPC_BODDET_Handler ( void ); -void WDT_Handler ( void ); -void RTC_Handler ( void ); -void EIC_EXTINT_0_Handler ( void ); -void EIC_EXTINT_1_Handler ( void ); -void EIC_EXTINT_2_Handler ( void ); -void EIC_EXTINT_3_Handler ( void ); -void EIC_EXTINT_4_Handler ( void ); -void EIC_EXTINT_5_Handler ( void ); -void EIC_EXTINT_6_Handler ( void ); -void EIC_EXTINT_7_Handler ( void ); -void EIC_EXTINT_8_Handler ( void ); -void EIC_EXTINT_9_Handler ( void ); -void EIC_EXTINT_10_Handler ( void ); -void EIC_EXTINT_11_Handler ( void ); -void EIC_EXTINT_12_Handler ( void ); -void EIC_EXTINT_13_Handler ( void ); -void EIC_EXTINT_14_Handler ( void ); -void EIC_EXTINT_15_Handler ( void ); -void FREQM_Handler ( void ); -void NVMCTRL_0_Handler ( void ); -void NVMCTRL_1_Handler ( void ); -void DMAC_0_Handler ( void ); -void DMAC_1_Handler ( void ); -void DMAC_2_Handler ( void ); -void DMAC_3_Handler ( void ); -void DMAC_OTHER_Handler ( void ); -void EVSYS_0_Handler ( void ); -void EVSYS_1_Handler ( void ); -void EVSYS_2_Handler ( void ); -void EVSYS_3_Handler ( void ); -void EVSYS_OTHER_Handler ( void ); -void PAC_Handler ( void ); -void RAMECC_Handler ( void ); -void SERCOM0_0_Handler ( void ); -void SERCOM0_1_Handler ( void ); -void SERCOM0_2_Handler ( void ); -void SERCOM0_OTHER_Handler ( void ); -void SERCOM1_0_Handler ( void ); -void SERCOM1_1_Handler ( void ); -void SERCOM1_2_Handler ( void ); -void SERCOM1_OTHER_Handler ( void ); -void SERCOM2_0_Handler ( void ); -void SERCOM2_1_Handler ( void ); -void SERCOM2_2_Handler ( void ); -void SERCOM2_OTHER_Handler ( void ); -void SERCOM3_0_Handler ( void ); -void SERCOM3_1_Handler ( void ); -void SERCOM3_2_Handler ( void ); -void SERCOM3_OTHER_Handler ( void ); -void SERCOM4_0_Handler ( void ); -void SERCOM4_1_Handler ( void ); -void SERCOM4_2_Handler ( void ); -void SERCOM4_OTHER_Handler ( void ); -void SERCOM5_0_Handler ( void ); -void SERCOM5_1_Handler ( void ); -void SERCOM5_2_Handler ( void ); -void SERCOM5_OTHER_Handler ( void ); -void SERCOM6_0_Handler ( void ); -void SERCOM6_1_Handler ( void ); -void SERCOM6_2_Handler ( void ); -void SERCOM6_OTHER_Handler ( void ); -void SERCOM7_0_Handler ( void ); -void SERCOM7_1_Handler ( void ); -void SERCOM7_2_Handler ( void ); -void SERCOM7_OTHER_Handler ( void ); -void CAN0_Handler ( void ); -void CAN1_Handler ( void ); -void USB_OTHER_Handler ( void ); -void USB_SOF_HSOF_Handler ( void ); -void USB_TRCPT0_Handler ( void ); -void USB_TRCPT1_Handler ( void ); -void GMAC_Handler ( void ); -void TCC0_OTHER_Handler ( void ); -void TCC0_MC0_Handler ( void ); -void TCC0_MC1_Handler ( void ); -void TCC0_MC2_Handler ( void ); -void TCC0_MC3_Handler ( void ); -void TCC0_MC4_Handler ( void ); -void TCC0_MC5_Handler ( void ); -void TCC1_OTHER_Handler ( void ); -void TCC1_MC0_Handler ( void ); -void TCC1_MC1_Handler ( void ); -void TCC1_MC2_Handler ( void ); -void TCC1_MC3_Handler ( void ); -void TCC2_OTHER_Handler ( void ); -void TCC2_MC0_Handler ( void ); -void TCC2_MC1_Handler ( void ); -void TCC2_MC2_Handler ( void ); -void TCC3_OTHER_Handler ( void ); -void TCC3_MC0_Handler ( void ); -void TCC3_MC1_Handler ( void ); -void TCC4_OTHER_Handler ( void ); -void TCC4_MC0_Handler ( void ); -void TCC4_MC1_Handler ( void ); -void TC0_Handler ( void ); -void TC1_Handler ( void ); -void TC2_Handler ( void ); -void TC3_Handler ( void ); -void TC4_Handler ( void ); -void TC5_Handler ( void ); -void TC6_Handler ( void ); -void TC7_Handler ( void ); -void PDEC_OTHER_Handler ( void ); -void PDEC_MC0_Handler ( void ); -void PDEC_MC1_Handler ( void ); -void ADC0_OTHER_Handler ( void ); -void ADC0_RESRDY_Handler ( void ); -void ADC1_OTHER_Handler ( void ); -void ADC1_RESRDY_Handler ( void ); -void AC_Handler ( void ); -void DAC_OTHER_Handler ( void ); -void DAC_EMPTY_0_Handler ( void ); -void DAC_EMPTY_1_Handler ( void ); -void DAC_RESRDY_0_Handler ( void ); -void DAC_RESRDY_1_Handler ( void ); -void I2S_Handler ( void ); -void PCC_Handler ( void ); -void AES_Handler ( void ); -void TRNG_Handler ( void ); -void ICM_Handler ( void ); -void PUKCC_Handler ( void ); -void QSPI_Handler ( void ); -void SDHC0_Handler ( void ); -void SDHC1_Handler ( void ); -#endif /* DONT_USE_PREDEFINED_PERIPHERALS_HANDLERS */ -/* Defines for Deprecated Interrupt and Exceptions handler names */ -#define MemManage_Handler MemoryManagement_Handler /**< \deprecated Backward compatibility*/ -#define DebugMon_Handler DebugMonitor_Handler /**< \deprecated Backward compatibility*/ -#define NMI_Handler NonMaskableInt_Handler /**< \deprecated Backward compatibility*/ -#define SVC_Handler SVCall_Handler /**< \deprecated Backward compatibility*/ - -#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/* - * \brief Configuration of the CORTEX-M4 Processor and Core Peripherals - */ -#define __CM4_REV 0x0001 /**< Cortex-M4 Core Revision */ -#define __DEBUG_LVL 3 /**< Debug Level */ -#define __FPU_PRESENT 1 /**< FPU present or not */ -#define __MPU_PRESENT 1 /**< MPU present or not */ -#define __NVIC_PRIO_BITS 3 /**< Number of Bits used for Priority Levels */ -#define __TRACE_LVL 2 /**< Trace Level */ -#define __VTOR_PRESENT 1 /**< Vector Table Offset Register present or not */ -#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */ -#define __ARCH_ARM 1 -#define __ARCH_ARM_CORTEX_M 1 -#define __DEVICE_IS_SAM 1 - -/* - * \brief CMSIS includes - */ -#include "core_cm4.h" -#if defined USE_CMSIS_INIT -#include "system_same54.h" -#endif /* USE_CMSIS_INIT */ - -/** \defgroup SAME54P20A_api Peripheral Software API - * @{ - */ - -/* ************************************************************************** */ -/** SOFTWARE PERIPHERAL API DEFINITION FOR SAME54P20A */ -/* ************************************************************************** */ -#include "component/ac.h" -#include "component/adc.h" -#include "component/aes.h" -#include "component/can.h" -#include "component/ccl.h" -#include "component/cmcc.h" -#include "component/dac.h" -#include "component/dmac.h" -#include "component/dsu.h" -#include "component/eic.h" -#include "component/evsys.h" -#include "component/freqm.h" -#include "component/gclk.h" -#include "component/gmac.h" -#include "component/hmatrixb.h" -#include "component/i2s.h" -#include "component/icm.h" -#include "component/mclk.h" -#include "component/nvmctrl.h" -#include "component/osc32kctrl.h" -#include "component/oscctrl.h" -#include "component/pac.h" -#include "component/pcc.h" -#include "component/pdec.h" -#include "component/pm.h" -#include "component/port.h" -#include "component/pukcc.h" -#include "component/qspi.h" -#include "component/ramecc.h" -#include "component/rstc.h" -#include "component/rtc.h" -#include "component/sdhc.h" -#include "component/sercom.h" -#include "component/supc.h" -#include "component/tc.h" -#include "component/tcc.h" -#include "component/trng.h" -#include "component/usb.h" -#include "component/wdt.h" -/** @} end of Peripheral Software API */ - -/** \addtogroup SAME54P20A_id Peripheral Ids Definitions - * @{ - */ - -/* ************************************************************************** */ -/* PERIPHERAL ID DEFINITIONS FOR SAME54P20A */ -/* ************************************************************************** */ -#define ID_PAC ( 0) /**< \brief Peripheral Access Controller (PAC) */ -#define ID_PM ( 1) /**< \brief Power Manager (PM) */ -#define ID_MCLK ( 2) /**< \brief Main Clock (MCLK) */ -#define ID_RSTC ( 3) /**< \brief Reset Controller (RSTC) */ -#define ID_OSCCTRL ( 4) /**< \brief Oscillators Control (OSCCTRL) */ -#define ID_OSC32KCTRL ( 5) /**< \brief 32kHz Oscillators Control (OSC32KCTRL) */ -#define ID_SUPC ( 6) /**< \brief Supply Controller (SUPC) */ -#define ID_GCLK ( 7) /**< \brief Generic Clock Generator (GCLK) */ -#define ID_WDT ( 8) /**< \brief Watchdog Timer (WDT) */ -#define ID_RTC ( 9) /**< \brief Real-Time Counter (RTC) */ -#define ID_EIC ( 10) /**< \brief External Interrupt Controller (EIC) */ -#define ID_FREQM ( 11) /**< \brief Frequency Meter (FREQM) */ -#define ID_SERCOM0 ( 12) /**< \brief Serial Communication Interface (SERCOM0) */ -#define ID_SERCOM1 ( 13) /**< \brief Serial Communication Interface (SERCOM1) */ -#define ID_TC0 ( 14) /**< \brief Basic Timer Counter (TC0) */ -#define ID_TC1 ( 15) /**< \brief Basic Timer Counter (TC1) */ -#define ID_USB ( 32) /**< \brief Universal Serial Bus (USB) */ -#define ID_DSU ( 33) /**< \brief Device Service Unit (DSU) */ -#define ID_NVMCTRL ( 34) /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ -#define ID_CMCC ( 35) /**< \brief Cortex M Cache Controller (CMCC) */ -#define ID_PORT ( 36) /**< \brief Port Module (PORT) */ -#define ID_DMAC ( 37) /**< \brief Direct Memory Access Controller (DMAC) */ -#define ID_HMATRIX ( 38) /**< \brief HSB Matrix (HMATRIX) */ -#define ID_EVSYS ( 39) /**< \brief Event System Interface (EVSYS) */ -#define ID_SERCOM2 ( 41) /**< \brief Serial Communication Interface (SERCOM2) */ -#define ID_SERCOM3 ( 42) /**< \brief Serial Communication Interface (SERCOM3) */ -#define ID_TCC0 ( 43) /**< \brief Timer Counter Control (TCC0) */ -#define ID_TCC1 ( 44) /**< \brief Timer Counter Control (TCC1) */ -#define ID_TC2 ( 45) /**< \brief Basic Timer Counter (TC2) */ -#define ID_TC3 ( 46) /**< \brief Basic Timer Counter (TC3) */ -#define ID_RAMECC ( 48) /**< \brief RAM ECC (RAMECC) */ -#define ID_CAN0 ( 64) /**< \brief Control Area Network (CAN0) */ -#define ID_CAN1 ( 65) /**< \brief Control Area Network (CAN1) */ -#define ID_GMAC ( 66) /**< \brief Ethernet MAC (GMAC) */ -#define ID_TCC2 ( 67) /**< \brief Timer Counter Control (TCC2) */ -#define ID_TCC3 ( 68) /**< \brief Timer Counter Control (TCC3) */ -#define ID_TC4 ( 69) /**< \brief Basic Timer Counter (TC4) */ -#define ID_TC5 ( 70) /**< \brief Basic Timer Counter (TC5) */ -#define ID_PDEC ( 71) /**< \brief Quadrature Decodeur (PDEC) */ -#define ID_AC ( 72) /**< \brief Analog Comparators (AC) */ -#define ID_AES ( 73) /**< \brief Advanced Encryption Standard (AES) */ -#define ID_TRNG ( 74) /**< \brief True Random Generator (TRNG) */ -#define ID_ICM ( 75) /**< \brief Integrity Check Monitor (ICM) */ -#define ID_PUKCC ( 76) /**< \brief PUblic-Key Cryptography Controller (PUKCC) */ -#define ID_QSPI ( 77) /**< \brief Quad SPI interface (QSPI) */ -#define ID_CCL ( 78) /**< \brief Configurable Custom Logic (CCL) */ -#define ID_SERCOM4 ( 96) /**< \brief Serial Communication Interface (SERCOM4) */ -#define ID_SERCOM5 ( 97) /**< \brief Serial Communication Interface (SERCOM5) */ -#define ID_SERCOM6 ( 98) /**< \brief Serial Communication Interface (SERCOM6) */ -#define ID_SERCOM7 ( 99) /**< \brief Serial Communication Interface (SERCOM7) */ -#define ID_TCC4 (100) /**< \brief Timer Counter Control (TCC4) */ -#define ID_TC6 (101) /**< \brief Basic Timer Counter (TC6) */ -#define ID_TC7 (102) /**< \brief Basic Timer Counter (TC7) */ -#define ID_ADC0 (103) /**< \brief Analog Digital Converter (ADC0) */ -#define ID_ADC1 (104) /**< \brief Analog Digital Converter (ADC1) */ -#define ID_DAC (105) /**< \brief Digital-to-Analog Converter (DAC) */ -#define ID_I2S (106) /**< \brief Inter-IC Sound Interface (I2S) */ -#define ID_PCC (107) /**< \brief Parallel Capture Controller (PCC) */ - -#define ID_PERIPH_MAX (107) /**< \brief Number of peripheral IDs */ -/** @} end of Peripheral Ids Definitions */ - -/** \addtogroup SAME54P20A_base Peripheral Base Address Definitions - * @{ - */ - -/* ************************************************************************** */ -/* REGISTER STRUCTURE ADDRESS DEFINITIONS FOR SAME54P20A */ -/* ************************************************************************** */ -#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) -#define AC_REGS ((ac_registers_t*)0x42002000) /**< \brief AC Registers Address */ -#define ADC0_REGS ((adc_registers_t*)0x43001c00) /**< \brief ADC0 Registers Address */ -#define ADC1_REGS ((adc_registers_t*)0x43002000) /**< \brief ADC1 Registers Address */ -#define AES_REGS ((aes_registers_t*)0x42002400) /**< \brief AES Registers Address */ -#define CAN0_REGS ((can_registers_t*)0x42000000) /**< \brief CAN0 Registers Address */ -#define CAN1_REGS ((can_registers_t*)0x42000400) /**< \brief CAN1 Registers Address */ -#define CCL_REGS ((ccl_registers_t*)0x42003800) /**< \brief CCL Registers Address */ -#define CMCC_REGS ((cmcc_registers_t*)0x41006000) /**< \brief CMCC Registers Address */ -#define DAC_REGS ((dac_registers_t*)0x43002400) /**< \brief DAC Registers Address */ -#define DMAC_REGS ((dmac_registers_t*)0x4100a000) /**< \brief DMAC Registers Address */ -#define DSU_REGS ((dsu_registers_t*)0x41002000) /**< \brief DSU Registers Address */ -#define EIC_REGS ((eic_registers_t*)0x40002800) /**< \brief EIC Registers Address */ -#define EVSYS_REGS ((evsys_registers_t*)0x4100e000) /**< \brief EVSYS Registers Address */ -#define FREQM_REGS ((freqm_registers_t*)0x40002c00) /**< \brief FREQM Registers Address */ -#define GCLK_REGS ((gclk_registers_t*)0x40001c00) /**< \brief GCLK Registers Address */ -#define GMAC_REGS ((gmac_registers_t*)0x42000800) /**< \brief GMAC Registers Address */ -#define HMATRIX_REGS ((hmatrixb_registers_t*)0x4100c000) /**< \brief HMATRIX Registers Address */ -#define ICM_REGS ((icm_registers_t*)0x42002c00) /**< \brief ICM Registers Address */ -#define I2S_REGS ((i2s_registers_t*)0x43002800) /**< \brief I2S Registers Address */ -#define MCLK_REGS ((mclk_registers_t*)0x40000800) /**< \brief MCLK Registers Address */ -#define NVMCTRL_REGS ((nvmctrl_registers_t*)0x41004000) /**< \brief NVMCTRL Registers Address */ -#define OSCCTRL_REGS ((oscctrl_registers_t*)0x40001000) /**< \brief OSCCTRL Registers Address */ -#define OSC32KCTRL_REGS ((osc32kctrl_registers_t*)0x40001400) /**< \brief OSC32KCTRL Registers Address */ -#define PAC_REGS ((pac_registers_t*)0x40000000) /**< \brief PAC Registers Address */ -#define PCC_REGS ((pcc_registers_t*)0x43002c00) /**< \brief PCC Registers Address */ -#define PDEC_REGS ((pdec_registers_t*)0x42001c00) /**< \brief PDEC Registers Address */ -#define PM_REGS ((pm_registers_t*)0x40000400) /**< \brief PM Registers Address */ -#define PORT_REGS ((port_registers_t*)0x41008000) /**< \brief PORT Registers Address */ -#define QSPI_REGS ((qspi_registers_t*)0x42003400) /**< \brief QSPI Registers Address */ -#define RAMECC_REGS ((ramecc_registers_t*)0x41020000) /**< \brief RAMECC Registers Address */ -#define RSTC_REGS ((rstc_registers_t*)0x40000c00) /**< \brief RSTC Registers Address */ -#define RTC_REGS ((rtc_registers_t*)0x40002400) /**< \brief RTC Registers Address */ -#define SDHC0_REGS ((sdhc_registers_t*)0x45000000) /**< \brief SDHC0 Registers Address */ -#define SDHC1_REGS ((sdhc_registers_t*)0x46000000) /**< \brief SDHC1 Registers Address */ -#define SERCOM0_REGS ((sercom_registers_t*)0x40003000) /**< \brief SERCOM0 Registers Address */ -#define SERCOM1_REGS ((sercom_registers_t*)0x40003400) /**< \brief SERCOM1 Registers Address */ -#define SERCOM2_REGS ((sercom_registers_t*)0x41012000) /**< \brief SERCOM2 Registers Address */ -#define SERCOM3_REGS ((sercom_registers_t*)0x41014000) /**< \brief SERCOM3 Registers Address */ -#define SERCOM4_REGS ((sercom_registers_t*)0x43000000) /**< \brief SERCOM4 Registers Address */ -#define SERCOM5_REGS ((sercom_registers_t*)0x43000400) /**< \brief SERCOM5 Registers Address */ -#define SERCOM6_REGS ((sercom_registers_t*)0x43000800) /**< \brief SERCOM6 Registers Address */ -#define SERCOM7_REGS ((sercom_registers_t*)0x43000c00) /**< \brief SERCOM7 Registers Address */ -#define SUPC_REGS ((supc_registers_t*)0x40001800) /**< \brief SUPC Registers Address */ -#define TC0_REGS ((tc_registers_t*)0x40003800) /**< \brief TC0 Registers Address */ -#define TC1_REGS ((tc_registers_t*)0x40003c00) /**< \brief TC1 Registers Address */ -#define TC2_REGS ((tc_registers_t*)0x4101a000) /**< \brief TC2 Registers Address */ -#define TC3_REGS ((tc_registers_t*)0x4101c000) /**< \brief TC3 Registers Address */ -#define TC4_REGS ((tc_registers_t*)0x42001400) /**< \brief TC4 Registers Address */ -#define TC5_REGS ((tc_registers_t*)0x42001800) /**< \brief TC5 Registers Address */ -#define TC6_REGS ((tc_registers_t*)0x43001400) /**< \brief TC6 Registers Address */ -#define TC7_REGS ((tc_registers_t*)0x43001800) /**< \brief TC7 Registers Address */ -#define TCC0_REGS ((tcc_registers_t*)0x41016000) /**< \brief TCC0 Registers Address */ -#define TCC1_REGS ((tcc_registers_t*)0x41018000) /**< \brief TCC1 Registers Address */ -#define TCC2_REGS ((tcc_registers_t*)0x42000c00) /**< \brief TCC2 Registers Address */ -#define TCC3_REGS ((tcc_registers_t*)0x42001000) /**< \brief TCC3 Registers Address */ -#define TCC4_REGS ((tcc_registers_t*)0x43001000) /**< \brief TCC4 Registers Address */ -#define TRNG_REGS ((trng_registers_t*)0x42002800) /**< \brief TRNG Registers Address */ -#define USB_REGS ((usb_registers_t*)0x41000000) /**< \brief USB Registers Address */ -#define WDT_REGS ((wdt_registers_t*)0x40002000) /**< \brief WDT Registers Address */ -#endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ -/** @} end of Peripheral Base Address Definitions */ - -/** \addtogroup SAME54P20A_base Peripheral Base Address Definitions - * @{ - */ - -/* ************************************************************************** */ -/* BASE ADDRESS DEFINITIONS FOR SAME54P20A */ -/* ************************************************************************** */ -#define AC_BASE_ADDRESS _UL_(0x42002000) /**< \brief AC Base Address */ -#define ADC0_BASE_ADDRESS _UL_(0x43001c00) /**< \brief ADC0 Base Address */ -#define ADC1_BASE_ADDRESS _UL_(0x43002000) /**< \brief ADC1 Base Address */ -#define AES_BASE_ADDRESS _UL_(0x42002400) /**< \brief AES Base Address */ -#define CAN0_BASE_ADDRESS _UL_(0x42000000) /**< \brief CAN0 Base Address */ -#define CAN1_BASE_ADDRESS _UL_(0x42000400) /**< \brief CAN1 Base Address */ -#define CCL_BASE_ADDRESS _UL_(0x42003800) /**< \brief CCL Base Address */ -#define CMCC_BASE_ADDRESS _UL_(0x41006000) /**< \brief CMCC Base Address */ -#define DAC_BASE_ADDRESS _UL_(0x43002400) /**< \brief DAC Base Address */ -#define DMAC_BASE_ADDRESS _UL_(0x4100a000) /**< \brief DMAC Base Address */ -#define DSU_BASE_ADDRESS _UL_(0x41002000) /**< \brief DSU Base Address */ -#define EIC_BASE_ADDRESS _UL_(0x40002800) /**< \brief EIC Base Address */ -#define EVSYS_BASE_ADDRESS _UL_(0x4100e000) /**< \brief EVSYS Base Address */ -#define FREQM_BASE_ADDRESS _UL_(0x40002c00) /**< \brief FREQM Base Address */ -#define GCLK_BASE_ADDRESS _UL_(0x40001c00) /**< \brief GCLK Base Address */ -#define GMAC_BASE_ADDRESS _UL_(0x42000800) /**< \brief GMAC Base Address */ -#define HMATRIX_BASE_ADDRESS _UL_(0x4100c000) /**< \brief HMATRIX Base Address */ -#define ICM_BASE_ADDRESS _UL_(0x42002c00) /**< \brief ICM Base Address */ -#define I2S_BASE_ADDRESS _UL_(0x43002800) /**< \brief I2S Base Address */ -#define MCLK_BASE_ADDRESS _UL_(0x40000800) /**< \brief MCLK Base Address */ -#define NVMCTRL_BASE_ADDRESS _UL_(0x41004000) /**< \brief NVMCTRL Base Address */ -#define OSCCTRL_BASE_ADDRESS _UL_(0x40001000) /**< \brief OSCCTRL Base Address */ -#define OSC32KCTRL_BASE_ADDRESS _UL_(0x40001400) /**< \brief OSC32KCTRL Base Address */ -#define PAC_BASE_ADDRESS _UL_(0x40000000) /**< \brief PAC Base Address */ -#define PCC_BASE_ADDRESS _UL_(0x43002c00) /**< \brief PCC Base Address */ -#define PDEC_BASE_ADDRESS _UL_(0x42001c00) /**< \brief PDEC Base Address */ -#define PM_BASE_ADDRESS _UL_(0x40000400) /**< \brief PM Base Address */ -#define PORT_BASE_ADDRESS _UL_(0x41008000) /**< \brief PORT Base Address */ -#define QSPI_BASE_ADDRESS _UL_(0x42003400) /**< \brief QSPI Base Address */ -#define RAMECC_BASE_ADDRESS _UL_(0x41020000) /**< \brief RAMECC Base Address */ -#define RSTC_BASE_ADDRESS _UL_(0x40000c00) /**< \brief RSTC Base Address */ -#define RTC_BASE_ADDRESS _UL_(0x40002400) /**< \brief RTC Base Address */ -#define SDHC0_BASE_ADDRESS _UL_(0x45000000) /**< \brief SDHC0 Base Address */ -#define SDHC1_BASE_ADDRESS _UL_(0x46000000) /**< \brief SDHC1 Base Address */ -#define SERCOM0_BASE_ADDRESS _UL_(0x40003000) /**< \brief SERCOM0 Base Address */ -#define SERCOM1_BASE_ADDRESS _UL_(0x40003400) /**< \brief SERCOM1 Base Address */ -#define SERCOM2_BASE_ADDRESS _UL_(0x41012000) /**< \brief SERCOM2 Base Address */ -#define SERCOM3_BASE_ADDRESS _UL_(0x41014000) /**< \brief SERCOM3 Base Address */ -#define SERCOM4_BASE_ADDRESS _UL_(0x43000000) /**< \brief SERCOM4 Base Address */ -#define SERCOM5_BASE_ADDRESS _UL_(0x43000400) /**< \brief SERCOM5 Base Address */ -#define SERCOM6_BASE_ADDRESS _UL_(0x43000800) /**< \brief SERCOM6 Base Address */ -#define SERCOM7_BASE_ADDRESS _UL_(0x43000c00) /**< \brief SERCOM7 Base Address */ -#define SUPC_BASE_ADDRESS _UL_(0x40001800) /**< \brief SUPC Base Address */ -#define TC0_BASE_ADDRESS _UL_(0x40003800) /**< \brief TC0 Base Address */ -#define TC1_BASE_ADDRESS _UL_(0x40003c00) /**< \brief TC1 Base Address */ -#define TC2_BASE_ADDRESS _UL_(0x4101a000) /**< \brief TC2 Base Address */ -#define TC3_BASE_ADDRESS _UL_(0x4101c000) /**< \brief TC3 Base Address */ -#define TC4_BASE_ADDRESS _UL_(0x42001400) /**< \brief TC4 Base Address */ -#define TC5_BASE_ADDRESS _UL_(0x42001800) /**< \brief TC5 Base Address */ -#define TC6_BASE_ADDRESS _UL_(0x43001400) /**< \brief TC6 Base Address */ -#define TC7_BASE_ADDRESS _UL_(0x43001800) /**< \brief TC7 Base Address */ -#define TCC0_BASE_ADDRESS _UL_(0x41016000) /**< \brief TCC0 Base Address */ -#define TCC1_BASE_ADDRESS _UL_(0x41018000) /**< \brief TCC1 Base Address */ -#define TCC2_BASE_ADDRESS _UL_(0x42000c00) /**< \brief TCC2 Base Address */ -#define TCC3_BASE_ADDRESS _UL_(0x42001000) /**< \brief TCC3 Base Address */ -#define TCC4_BASE_ADDRESS _UL_(0x43001000) /**< \brief TCC4 Base Address */ -#define TRNG_BASE_ADDRESS _UL_(0x42002800) /**< \brief TRNG Base Address */ -#define USB_BASE_ADDRESS _UL_(0x41000000) /**< \brief USB Base Address */ -#define WDT_BASE_ADDRESS _UL_(0x40002000) /**< \brief WDT Base Address */ -/** @} end of Peripheral Base Address Definitions */ - -/** \addtogroup SAME54P20A_pio Peripheral Pio Definitions - * @{ - */ - -/* ************************************************************************** */ -/* PIO DEFINITIONS FOR SAME54P20A */ -/* ************************************************************************** */ -#include "pio/same54p20a.h" -/** @} end of Peripheral Pio Definitions */ - -/* ************************************************************************** */ -/* MEMORY MAPPING DEFINITIONS FOR SAME54P20A */ -/* ************************************************************************** */ - -#define FLASH_SIZE _UL_(0x00100000) /* 1024kB Memory segment type: flash */ -#define FLASH_PAGE_SIZE _UL_( 512) -#define FLASH_NB_OF_PAGES _UL_( 2048) - -#define SW0_SIZE _UL_(0x00000010) /* 0kB Memory segment type: fuses */ -#define TEMP_LOG_SIZE _UL_(0x00000200) /* 0kB Memory segment type: fuses */ -#define TEMP_LOG_PAGE_SIZE _UL_( 512) -#define TEMP_LOG_NB_OF_PAGES _UL_( 1) - -#define USER_PAGE_SIZE _UL_(0x00000200) /* 0kB Memory segment type: user_page */ -#define USER_PAGE_PAGE_SIZE _UL_( 512) -#define USER_PAGE_NB_OF_PAGES _UL_( 1) - -#define CMCC_SIZE _UL_(0x01000000) /* 16384kB Memory segment type: io */ -#define CMCC_DATARAM_SIZE _UL_(0x00001000) /* 4kB Memory segment type: io */ -#define CMCC_TAGRAM_SIZE _UL_(0x00000400) /* 1kB Memory segment type: io */ -#define CMCC_VALIDRAM_SIZE _UL_(0x00000040) /* 0kB Memory segment type: io */ -#define QSPI_SIZE _UL_(0x01000000) /* 16384kB Memory segment type: other */ -#define HSRAM_SIZE _UL_(0x00040000) /* 256kB Memory segment type: ram */ -#define HSRAM_ETB_SIZE _UL_(0x00008000) /* 32kB Memory segment type: ram */ -#define HSRAM_RET1_SIZE _UL_(0x00008000) /* 32kB Memory segment type: ram */ -#define HPB0_SIZE _UL_(0x00004400) /* 17kB Memory segment type: io */ -#define HPB1_SIZE _UL_(0x00022000) /* 136kB Memory segment type: io */ -#define HPB2_SIZE _UL_(0x00003c00) /* 15kB Memory segment type: io */ -#define HPB3_SIZE _UL_(0x00003000) /* 12kB Memory segment type: io */ -#define SEEPROM_SIZE _UL_(0x00020000) /* 128kB Memory segment type: io */ -#define SDHC0_SIZE _UL_(0x00000c00) /* 3kB Memory segment type: io */ -#define SDHC1_SIZE _UL_(0x00000c00) /* 3kB Memory segment type: io */ -#define BKUPRAM_SIZE _UL_(0x00002000) /* 8kB Memory segment type: ram */ -#define PPB_SIZE _UL_(0x00100000) /* 1024kB Memory segment type: io */ -#define SCS_SIZE _UL_(0x00001000) /* 4kB Memory segment type: io */ - -#define FLASH_ADDR _UL_(0x00000000) /**< FLASH base address (type: flash)*/ -#define SW0_ADDR _UL_(0x00800080) /**< SW0 base address (type: fuses)*/ -#define TEMP_LOG_ADDR _UL_(0x00800100) /**< TEMP_LOG base address (type: fuses)*/ -#define USER_PAGE_ADDR _UL_(0x00804000) /**< USER_PAGE base address (type: user_page)*/ -#define CMCC_ADDR _UL_(0x03000000) /**< CMCC base address (type: io)*/ -#define CMCC_DATARAM_ADDR _UL_(0x03000000) /**< CMCC_DATARAM base address (type: io)*/ -#define CMCC_TAGRAM_ADDR _UL_(0x03001000) /**< CMCC_TAGRAM base address (type: io)*/ -#define CMCC_VALIDRAM_ADDR _UL_(0x03002000) /**< CMCC_VALIDRAM base address (type: io)*/ -#define QSPI_ADDR _UL_(0x04000000) /**< QSPI base address (type: other)*/ -#define HSRAM_ADDR _UL_(0x20000000) /**< HSRAM base address (type: ram)*/ -#define HSRAM_ETB_ADDR _UL_(0x20000000) /**< HSRAM_ETB base address (type: ram)*/ -#define HSRAM_RET1_ADDR _UL_(0x20000000) /**< HSRAM_RET1 base address (type: ram)*/ -#define HPB0_ADDR _UL_(0x40000000) /**< HPB0 base address (type: io)*/ -#define HPB1_ADDR _UL_(0x41000000) /**< HPB1 base address (type: io)*/ -#define HPB2_ADDR _UL_(0x42000000) /**< HPB2 base address (type: io)*/ -#define HPB3_ADDR _UL_(0x43000000) /**< HPB3 base address (type: io)*/ -#define SEEPROM_ADDR _UL_(0x44000000) /**< SEEPROM base address (type: io)*/ -#define SDHC0_ADDR _UL_(0x45000000) /**< SDHC0 base address (type: io)*/ -#define SDHC1_ADDR _UL_(0x46000000) /**< SDHC1 base address (type: io)*/ -#define BKUPRAM_ADDR _UL_(0x47000000) /**< BKUPRAM base address (type: ram)*/ -#define PPB_ADDR _UL_(0xe0000000) /**< PPB base address (type: io)*/ -#define SCS_ADDR _UL_(0xe000e000) /**< SCS base address (type: io)*/ - -/* ************************************************************************** */ -/** DEVICE SIGNATURES FOR SAME54P20A */ -/* ************************************************************************** */ -#define CHIP_DSU_DID _UL_(0X61840300) - -/* ************************************************************************** */ -/** ELECTRICAL DEFINITIONS FOR SAME54P20A */ -/* ************************************************************************** */ - -/* ************************************************************************** */ -/** Event Generator IDs for SAME54P20A */ -/* ************************************************************************** */ -#define EVENT_ID_GEN_OSCCTRL_XOSC_FAIL_0 1 /**< ID for OSCCTRL event generator XOSC_FAIL_0 */ -#define EVENT_ID_GEN_OSCCTRL_XOSC_FAIL_1 2 /**< ID for OSCCTRL event generator XOSC_FAIL_1 */ -#define EVENT_ID_GEN_OSC32KCTRL_XOSC32K_FAIL 3 /**< ID for OSC32KCTRL event generator XOSC32K_FAIL */ -#define EVENT_ID_GEN_RTC_PER_0 4 /**< ID for RTC event generator PER_0 */ -#define EVENT_ID_GEN_RTC_PER_1 5 /**< ID for RTC event generator PER_1 */ -#define EVENT_ID_GEN_RTC_PER_2 6 /**< ID for RTC event generator PER_2 */ -#define EVENT_ID_GEN_RTC_PER_3 7 /**< ID for RTC event generator PER_3 */ -#define EVENT_ID_GEN_RTC_PER_4 8 /**< ID for RTC event generator PER_4 */ -#define EVENT_ID_GEN_RTC_PER_5 9 /**< ID for RTC event generator PER_5 */ -#define EVENT_ID_GEN_RTC_PER_6 10 /**< ID for RTC event generator PER_6 */ -#define EVENT_ID_GEN_RTC_PER_7 11 /**< ID for RTC event generator PER_7 */ -#define EVENT_ID_GEN_RTC_CMP_0 12 /**< ID for RTC event generator CMP_0 */ -#define EVENT_ID_GEN_RTC_CMP_1 13 /**< ID for RTC event generator CMP_1 */ -#define EVENT_ID_GEN_RTC_CMP_2 14 /**< ID for RTC event generator CMP_2 */ -#define EVENT_ID_GEN_RTC_CMP_3 15 /**< ID for RTC event generator CMP_3 */ -#define EVENT_ID_GEN_RTC_TAMPER 16 /**< ID for RTC event generator TAMPER */ -#define EVENT_ID_GEN_RTC_OVF 17 /**< ID for RTC event generator OVF */ -#define EVENT_ID_GEN_EIC_EXTINT_0 18 /**< ID for EIC event generator EXTINT_0 */ -#define EVENT_ID_GEN_EIC_EXTINT_1 19 /**< ID for EIC event generator EXTINT_1 */ -#define EVENT_ID_GEN_EIC_EXTINT_2 20 /**< ID for EIC event generator EXTINT_2 */ -#define EVENT_ID_GEN_EIC_EXTINT_3 21 /**< ID for EIC event generator EXTINT_3 */ -#define EVENT_ID_GEN_EIC_EXTINT_4 22 /**< ID for EIC event generator EXTINT_4 */ -#define EVENT_ID_GEN_EIC_EXTINT_5 23 /**< ID for EIC event generator EXTINT_5 */ -#define EVENT_ID_GEN_EIC_EXTINT_6 24 /**< ID for EIC event generator EXTINT_6 */ -#define EVENT_ID_GEN_EIC_EXTINT_7 25 /**< ID for EIC event generator EXTINT_7 */ -#define EVENT_ID_GEN_EIC_EXTINT_8 26 /**< ID for EIC event generator EXTINT_8 */ -#define EVENT_ID_GEN_EIC_EXTINT_9 27 /**< ID for EIC event generator EXTINT_9 */ -#define EVENT_ID_GEN_EIC_EXTINT_10 28 /**< ID for EIC event generator EXTINT_10 */ -#define EVENT_ID_GEN_EIC_EXTINT_11 29 /**< ID for EIC event generator EXTINT_11 */ -#define EVENT_ID_GEN_EIC_EXTINT_12 30 /**< ID for EIC event generator EXTINT_12 */ -#define EVENT_ID_GEN_EIC_EXTINT_13 31 /**< ID for EIC event generator EXTINT_13 */ -#define EVENT_ID_GEN_EIC_EXTINT_14 32 /**< ID for EIC event generator EXTINT_14 */ -#define EVENT_ID_GEN_EIC_EXTINT_15 33 /**< ID for EIC event generator EXTINT_15 */ -#define EVENT_ID_GEN_DMAC_CH_0 34 /**< ID for DMAC event generator CH_0 */ -#define EVENT_ID_GEN_DMAC_CH_1 35 /**< ID for DMAC event generator CH_1 */ -#define EVENT_ID_GEN_DMAC_CH_2 36 /**< ID for DMAC event generator CH_2 */ -#define EVENT_ID_GEN_DMAC_CH_3 37 /**< ID for DMAC event generator CH_3 */ -#define EVENT_ID_GEN_PAC_ACCERR 38 /**< ID for PAC event generator ACCERR */ -#define EVENT_ID_GEN_TCC0_OVF 41 /**< ID for TCC0 event generator OVF */ -#define EVENT_ID_GEN_TCC0_TRG 42 /**< ID for TCC0 event generator TRG */ -#define EVENT_ID_GEN_TCC0_CNT 43 /**< ID for TCC0 event generator CNT */ -#define EVENT_ID_GEN_TCC0_MC_0 44 /**< ID for TCC0 event generator MC_0 */ -#define EVENT_ID_GEN_TCC0_MC_1 45 /**< ID for TCC0 event generator MC_1 */ -#define EVENT_ID_GEN_TCC0_MC_2 46 /**< ID for TCC0 event generator MC_2 */ -#define EVENT_ID_GEN_TCC0_MC_3 47 /**< ID for TCC0 event generator MC_3 */ -#define EVENT_ID_GEN_TCC0_MC_4 48 /**< ID for TCC0 event generator MC_4 */ -#define EVENT_ID_GEN_TCC0_MC_5 49 /**< ID for TCC0 event generator MC_5 */ -#define EVENT_ID_GEN_TCC1_OVF 50 /**< ID for TCC1 event generator OVF */ -#define EVENT_ID_GEN_TCC1_TRG 51 /**< ID for TCC1 event generator TRG */ -#define EVENT_ID_GEN_TCC1_CNT 52 /**< ID for TCC1 event generator CNT */ -#define EVENT_ID_GEN_TCC1_MC_0 53 /**< ID for TCC1 event generator MC_0 */ -#define EVENT_ID_GEN_TCC1_MC_1 54 /**< ID for TCC1 event generator MC_1 */ -#define EVENT_ID_GEN_TCC1_MC_2 55 /**< ID for TCC1 event generator MC_2 */ -#define EVENT_ID_GEN_TCC1_MC_3 56 /**< ID for TCC1 event generator MC_3 */ -#define EVENT_ID_GEN_TCC2_OVF 57 /**< ID for TCC2 event generator OVF */ -#define EVENT_ID_GEN_TCC2_TRG 58 /**< ID for TCC2 event generator TRG */ -#define EVENT_ID_GEN_TCC2_CNT 59 /**< ID for TCC2 event generator CNT */ -#define EVENT_ID_GEN_TCC2_MC_0 60 /**< ID for TCC2 event generator MC_0 */ -#define EVENT_ID_GEN_TCC2_MC_1 61 /**< ID for TCC2 event generator MC_1 */ -#define EVENT_ID_GEN_TCC2_MC_2 62 /**< ID for TCC2 event generator MC_2 */ -#define EVENT_ID_GEN_TCC3_OVF 63 /**< ID for TCC3 event generator OVF */ -#define EVENT_ID_GEN_TCC3_TRG 64 /**< ID for TCC3 event generator TRG */ -#define EVENT_ID_GEN_TCC3_CNT 65 /**< ID for TCC3 event generator CNT */ -#define EVENT_ID_GEN_TCC3_MC_0 66 /**< ID for TCC3 event generator MC_0 */ -#define EVENT_ID_GEN_TCC3_MC_1 67 /**< ID for TCC3 event generator MC_1 */ -#define EVENT_ID_GEN_TCC4_OVF 68 /**< ID for TCC4 event generator OVF */ -#define EVENT_ID_GEN_TCC4_TRG 69 /**< ID for TCC4 event generator TRG */ -#define EVENT_ID_GEN_TCC4_CNT 70 /**< ID for TCC4 event generator CNT */ -#define EVENT_ID_GEN_TCC4_MC_0 71 /**< ID for TCC4 event generator MC_0 */ -#define EVENT_ID_GEN_TCC4_MC_1 72 /**< ID for TCC4 event generator MC_1 */ -#define EVENT_ID_GEN_TC0_OVF 73 /**< ID for TC0 event generator OVF */ -#define EVENT_ID_GEN_TC0_MC_0 74 /**< ID for TC0 event generator MC_0 */ -#define EVENT_ID_GEN_TC0_MC_1 75 /**< ID for TC0 event generator MC_1 */ -#define EVENT_ID_GEN_TC1_OVF 76 /**< ID for TC1 event generator OVF */ -#define EVENT_ID_GEN_TC1_MC_0 77 /**< ID for TC1 event generator MC_0 */ -#define EVENT_ID_GEN_TC1_MC_1 78 /**< ID for TC1 event generator MC_1 */ -#define EVENT_ID_GEN_TC2_OVF 79 /**< ID for TC2 event generator OVF */ -#define EVENT_ID_GEN_TC2_MC_0 80 /**< ID for TC2 event generator MC_0 */ -#define EVENT_ID_GEN_TC2_MC_1 81 /**< ID for TC2 event generator MC_1 */ -#define EVENT_ID_GEN_TC3_OVF 82 /**< ID for TC3 event generator OVF */ -#define EVENT_ID_GEN_TC3_MC_0 83 /**< ID for TC3 event generator MC_0 */ -#define EVENT_ID_GEN_TC3_MC_1 84 /**< ID for TC3 event generator MC_1 */ -#define EVENT_ID_GEN_TC4_OVF 85 /**< ID for TC4 event generator OVF */ -#define EVENT_ID_GEN_TC4_MC_0 86 /**< ID for TC4 event generator MC_0 */ -#define EVENT_ID_GEN_TC4_MC_1 87 /**< ID for TC4 event generator MC_1 */ -#define EVENT_ID_GEN_TC5_OVF 88 /**< ID for TC5 event generator OVF */ -#define EVENT_ID_GEN_TC5_MC_0 89 /**< ID for TC5 event generator MC_0 */ -#define EVENT_ID_GEN_TC5_MC_1 90 /**< ID for TC5 event generator MC_1 */ -#define EVENT_ID_GEN_TC6_OVF 91 /**< ID for TC6 event generator OVF */ -#define EVENT_ID_GEN_TC6_MC_0 92 /**< ID for TC6 event generator MC_0 */ -#define EVENT_ID_GEN_TC6_MC_1 93 /**< ID for TC6 event generator MC_1 */ -#define EVENT_ID_GEN_TC7_OVF 94 /**< ID for TC7 event generator OVF */ -#define EVENT_ID_GEN_TC7_MC_0 95 /**< ID for TC7 event generator MC_0 */ -#define EVENT_ID_GEN_TC7_MC_1 96 /**< ID for TC7 event generator MC_1 */ -#define EVENT_ID_GEN_PDEC_OVF 97 /**< ID for PDEC event generator OVF */ -#define EVENT_ID_GEN_PDEC_ERR 98 /**< ID for PDEC event generator ERR */ -#define EVENT_ID_GEN_PDEC_DIR 99 /**< ID for PDEC event generator DIR */ -#define EVENT_ID_GEN_PDEC_VLC 100 /**< ID for PDEC event generator VLC */ -#define EVENT_ID_GEN_PDEC_MC_0 101 /**< ID for PDEC event generator MC_0 */ -#define EVENT_ID_GEN_PDEC_MC_1 102 /**< ID for PDEC event generator MC_1 */ -#define EVENT_ID_GEN_ADC0_RESRDY 103 /**< ID for ADC0 event generator RESRDY */ -#define EVENT_ID_GEN_ADC0_WINMON 104 /**< ID for ADC0 event generator WINMON */ -#define EVENT_ID_GEN_ADC1_RESRDY 105 /**< ID for ADC1 event generator RESRDY */ -#define EVENT_ID_GEN_ADC1_WINMON 106 /**< ID for ADC1 event generator WINMON */ -#define EVENT_ID_GEN_AC_COMP_0 107 /**< ID for AC event generator COMP_0 */ -#define EVENT_ID_GEN_AC_COMP_1 108 /**< ID for AC event generator COMP_1 */ -#define EVENT_ID_GEN_AC_WIN_0 109 /**< ID for AC event generator WIN_0 */ -#define EVENT_ID_GEN_DAC_EMPTY_0 110 /**< ID for DAC event generator EMPTY_0 */ -#define EVENT_ID_GEN_DAC_EMPTY_1 111 /**< ID for DAC event generator EMPTY_1 */ -#define EVENT_ID_GEN_DAC_RESRDY_0 112 /**< ID for DAC event generator RESRDY_0 */ -#define EVENT_ID_GEN_DAC_RESRDY_1 113 /**< ID for DAC event generator RESRDY_1 */ -#define EVENT_ID_GEN_GMAC_TSU_CMP 114 /**< ID for GMAC event generator TSU_CMP */ -#define EVENT_ID_GEN_TRNG_READY 115 /**< ID for TRNG event generator READY */ -#define EVENT_ID_GEN_CCL_LUTOUT_0 116 /**< ID for CCL event generator LUTOUT_0 */ -#define EVENT_ID_GEN_CCL_LUTOUT_1 117 /**< ID for CCL event generator LUTOUT_1 */ -#define EVENT_ID_GEN_CCL_LUTOUT_2 118 /**< ID for CCL event generator LUTOUT_2 */ -#define EVENT_ID_GEN_CCL_LUTOUT_3 119 /**< ID for CCL event generator LUTOUT_3 */ - -/* ************************************************************************** */ -/** Event User IDs for SAME54P20A */ -/* ************************************************************************** */ -#define EVENT_ID_USER_RTC_TAMPER 0 /**< ID for RTC event user TAMPER */ -#define EVENT_ID_USER_PORT_EV_0 1 /**< ID for PORT event user EV_0 */ -#define EVENT_ID_USER_PORT_EV_1 2 /**< ID for PORT event user EV_1 */ -#define EVENT_ID_USER_PORT_EV_2 3 /**< ID for PORT event user EV_2 */ -#define EVENT_ID_USER_PORT_EV_3 4 /**< ID for PORT event user EV_3 */ -#define EVENT_ID_USER_DMAC_CH_0 5 /**< ID for DMAC event user CH_0 */ -#define EVENT_ID_USER_DMAC_CH_1 6 /**< ID for DMAC event user CH_1 */ -#define EVENT_ID_USER_DMAC_CH_2 7 /**< ID for DMAC event user CH_2 */ -#define EVENT_ID_USER_DMAC_CH_3 8 /**< ID for DMAC event user CH_3 */ -#define EVENT_ID_USER_DMAC_CH_4 9 /**< ID for DMAC event user CH_4 */ -#define EVENT_ID_USER_DMAC_CH_5 10 /**< ID for DMAC event user CH_5 */ -#define EVENT_ID_USER_DMAC_CH_6 11 /**< ID for DMAC event user CH_6 */ -#define EVENT_ID_USER_DMAC_CH_7 12 /**< ID for DMAC event user CH_7 */ -#define EVENT_ID_USER_CM4_TRACE_START 14 /**< ID for CM4 event user TRACE_START */ -#define EVENT_ID_USER_CM4_TRACE_STOP 15 /**< ID for CM4 event user TRACE_STOP */ -#define EVENT_ID_USER_CM4_TRACE_TRIG 16 /**< ID for CM4 event user TRACE_TRIG */ -#define EVENT_ID_USER_TCC0_EV_0 17 /**< ID for TCC0 event user EV_0 */ -#define EVENT_ID_USER_TCC0_EV_1 18 /**< ID for TCC0 event user EV_1 */ -#define EVENT_ID_USER_TCC0_MC_0 19 /**< ID for TCC0 event user MC_0 */ -#define EVENT_ID_USER_TCC0_MC_1 20 /**< ID for TCC0 event user MC_1 */ -#define EVENT_ID_USER_TCC0_MC_2 21 /**< ID for TCC0 event user MC_2 */ -#define EVENT_ID_USER_TCC0_MC_3 22 /**< ID for TCC0 event user MC_3 */ -#define EVENT_ID_USER_TCC0_MC_4 23 /**< ID for TCC0 event user MC_4 */ -#define EVENT_ID_USER_TCC0_MC_5 24 /**< ID for TCC0 event user MC_5 */ -#define EVENT_ID_USER_TCC1_EV_0 25 /**< ID for TCC1 event user EV_0 */ -#define EVENT_ID_USER_TCC1_EV_1 26 /**< ID for TCC1 event user EV_1 */ -#define EVENT_ID_USER_TCC1_MC_0 27 /**< ID for TCC1 event user MC_0 */ -#define EVENT_ID_USER_TCC1_MC_1 28 /**< ID for TCC1 event user MC_1 */ -#define EVENT_ID_USER_TCC1_MC_2 29 /**< ID for TCC1 event user MC_2 */ -#define EVENT_ID_USER_TCC1_MC_3 30 /**< ID for TCC1 event user MC_3 */ -#define EVENT_ID_USER_TCC2_EV_0 31 /**< ID for TCC2 event user EV_0 */ -#define EVENT_ID_USER_TCC2_EV_1 32 /**< ID for TCC2 event user EV_1 */ -#define EVENT_ID_USER_TCC2_MC_0 33 /**< ID for TCC2 event user MC_0 */ -#define EVENT_ID_USER_TCC2_MC_1 34 /**< ID for TCC2 event user MC_1 */ -#define EVENT_ID_USER_TCC2_MC_2 35 /**< ID for TCC2 event user MC_2 */ -#define EVENT_ID_USER_TCC3_EV_0 36 /**< ID for TCC3 event user EV_0 */ -#define EVENT_ID_USER_TCC3_EV_1 37 /**< ID for TCC3 event user EV_1 */ -#define EVENT_ID_USER_TCC3_MC_0 38 /**< ID for TCC3 event user MC_0 */ -#define EVENT_ID_USER_TCC3_MC_1 39 /**< ID for TCC3 event user MC_1 */ -#define EVENT_ID_USER_TCC4_EV_0 40 /**< ID for TCC4 event user EV_0 */ -#define EVENT_ID_USER_TCC4_EV_1 41 /**< ID for TCC4 event user EV_1 */ -#define EVENT_ID_USER_TCC4_MC_0 42 /**< ID for TCC4 event user MC_0 */ -#define EVENT_ID_USER_TCC4_MC_1 43 /**< ID for TCC4 event user MC_1 */ -#define EVENT_ID_USER_TC0_EVU 44 /**< ID for TC0 event user EVU */ -#define EVENT_ID_USER_TC1_EVU 45 /**< ID for TC1 event user EVU */ -#define EVENT_ID_USER_TC2_EVU 46 /**< ID for TC2 event user EVU */ -#define EVENT_ID_USER_TC3_EVU 47 /**< ID for TC3 event user EVU */ -#define EVENT_ID_USER_TC4_EVU 48 /**< ID for TC4 event user EVU */ -#define EVENT_ID_USER_TC5_EVU 49 /**< ID for TC5 event user EVU */ -#define EVENT_ID_USER_TC6_EVU 50 /**< ID for TC6 event user EVU */ -#define EVENT_ID_USER_TC7_EVU 51 /**< ID for TC7 event user EVU */ -#define EVENT_ID_USER_PDEC_EVU_0 52 /**< ID for PDEC event user EVU_0 */ -#define EVENT_ID_USER_PDEC_EVU_1 53 /**< ID for PDEC event user EVU_1 */ -#define EVENT_ID_USER_PDEC_EVU_2 54 /**< ID for PDEC event user EVU_2 */ -#define EVENT_ID_USER_ADC0_START 55 /**< ID for ADC0 event user START */ -#define EVENT_ID_USER_ADC0_SYNC 56 /**< ID for ADC0 event user SYNC */ -#define EVENT_ID_USER_ADC1_START 57 /**< ID for ADC1 event user START */ -#define EVENT_ID_USER_ADC1_SYNC 58 /**< ID for ADC1 event user SYNC */ -#define EVENT_ID_USER_AC_SOC_0 59 /**< ID for AC event user SOC_0 */ -#define EVENT_ID_USER_AC_SOC_1 60 /**< ID for AC event user SOC_1 */ -#define EVENT_ID_USER_DAC_START_0 61 /**< ID for DAC event user START_0 */ -#define EVENT_ID_USER_DAC_START_1 62 /**< ID for DAC event user START_1 */ -#define EVENT_ID_USER_CCL_LUTIN_0 63 /**< ID for CCL event user LUTIN_0 */ -#define EVENT_ID_USER_CCL_LUTIN_1 64 /**< ID for CCL event user LUTIN_1 */ -#define EVENT_ID_USER_CCL_LUTIN_2 65 /**< ID for CCL event user LUTIN_2 */ -#define EVENT_ID_USER_CCL_LUTIN_3 66 /**< ID for CCL event user LUTIN_3 */ - -#ifdef __cplusplus -} -#endif - -/** @} end of SAME54P20A definitions */ - - -#endif /* _SAME54P20A_H_ */ - +/** + * \file + * + * \brief Header file for SAME54P20A + * + * Copyright (c) 2019 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAME54P20A_ +#define _SAME54P20A_ + +/** + * \ingroup SAME54_definitions + * \addtogroup SAME54P20A_definitions SAME54P20A definitions + * This file defines all structures and symbols for SAME54P20A: + * - registers and bitfields + * - peripheral base address + * - peripheral ID + * - PIO definitions +*/ +/*@{*/ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#include +#ifndef __cplusplus +typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#else +typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#endif +typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ +typedef volatile uint8_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ +typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ +typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ +#endif + +#if !defined(SKIP_INTEGER_LITERALS) +#if defined(_U_) || defined(_L_) || defined(_UL_) + #error "Integer Literals macros already defined elsewhere" +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/* Macros that deal with adding suffixes to integer literal constants for C/C++ */ +#define _U_(x) x ## U /**< C code: Unsigned integer literal constant value */ +#define _L_(x) x ## L /**< C code: Long integer literal constant value */ +#define _UL_(x) x ## UL /**< C code: Unsigned Long integer literal constant value */ +#else /* Assembler */ +#define _U_(x) x /**< Assembler: Unsigned integer literal constant value */ +#define _L_(x) x /**< Assembler: Long integer literal constant value */ +#define _UL_(x) x /**< Assembler: Unsigned Long integer literal constant value */ +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +#endif /* SKIP_INTEGER_LITERALS */ + +/* ************************************************************************** */ +/** CMSIS DEFINITIONS FOR SAME54P20A */ +/* ************************************************************************** */ +/** \defgroup SAME54P20A_cmsis CMSIS Definitions */ +/*@{*/ + +/** Interrupt Number Definition */ +typedef enum IRQn +{ + /****** Cortex-M4 Processor Exceptions Numbers *******************/ + NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13,/**< 3 Hard Fault Interrupt */ + MemoryManagement_IRQn = -12,/**< 4 Memory Management Interrupt */ + BusFault_IRQn = -11,/**< 5 Bus Fault Interrupt */ + UsageFault_IRQn = -10,/**< 6 Usage Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /**< 12 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /**< 14 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 System Tick Interrupt */ + /****** SAME54P20A-specific Interrupt Numbers *********************/ + PM_IRQn = 0, /**< 0 SAME54P20A Power Manager (PM) */ + MCLK_IRQn = 1, /**< 1 SAME54P20A Main Clock (MCLK) */ + OSCCTRL_0_IRQn = 2, /**< 2 SAME54P20A Oscillators Control (OSCCTRL) IRQ 0 */ + OSCCTRL_1_IRQn = 3, /**< 3 SAME54P20A Oscillators Control (OSCCTRL) IRQ 1 */ + OSCCTRL_2_IRQn = 4, /**< 4 SAME54P20A Oscillators Control (OSCCTRL) IRQ 2 */ + OSCCTRL_3_IRQn = 5, /**< 5 SAME54P20A Oscillators Control (OSCCTRL) IRQ 3 */ + OSCCTRL_4_IRQn = 6, /**< 6 SAME54P20A Oscillators Control (OSCCTRL) IRQ 4 */ + OSC32KCTRL_IRQn = 7, /**< 7 SAME54P20A 32kHz Oscillators Control (OSC32KCTRL) */ + SUPC_0_IRQn = 8, /**< 8 SAME54P20A Supply Controller (SUPC) IRQ 0 */ + SUPC_1_IRQn = 9, /**< 9 SAME54P20A Supply Controller (SUPC) IRQ 1 */ + WDT_IRQn = 10, /**< 10 SAME54P20A Watchdog Timer (WDT) */ + RTC_IRQn = 11, /**< 11 SAME54P20A Real-Time Counter (RTC) */ + EIC_0_IRQn = 12, /**< 12 SAME54P20A External Interrupt Controller (EIC) IRQ 0 */ + EIC_1_IRQn = 13, /**< 13 SAME54P20A External Interrupt Controller (EIC) IRQ 1 */ + EIC_2_IRQn = 14, /**< 14 SAME54P20A External Interrupt Controller (EIC) IRQ 2 */ + EIC_3_IRQn = 15, /**< 15 SAME54P20A External Interrupt Controller (EIC) IRQ 3 */ + EIC_4_IRQn = 16, /**< 16 SAME54P20A External Interrupt Controller (EIC) IRQ 4 */ + EIC_5_IRQn = 17, /**< 17 SAME54P20A External Interrupt Controller (EIC) IRQ 5 */ + EIC_6_IRQn = 18, /**< 18 SAME54P20A External Interrupt Controller (EIC) IRQ 6 */ + EIC_7_IRQn = 19, /**< 19 SAME54P20A External Interrupt Controller (EIC) IRQ 7 */ + EIC_8_IRQn = 20, /**< 20 SAME54P20A External Interrupt Controller (EIC) IRQ 8 */ + EIC_9_IRQn = 21, /**< 21 SAME54P20A External Interrupt Controller (EIC) IRQ 9 */ + EIC_10_IRQn = 22, /**< 22 SAME54P20A External Interrupt Controller (EIC) IRQ 10 */ + EIC_11_IRQn = 23, /**< 23 SAME54P20A External Interrupt Controller (EIC) IRQ 11 */ + EIC_12_IRQn = 24, /**< 24 SAME54P20A External Interrupt Controller (EIC) IRQ 12 */ + EIC_13_IRQn = 25, /**< 25 SAME54P20A External Interrupt Controller (EIC) IRQ 13 */ + EIC_14_IRQn = 26, /**< 26 SAME54P20A External Interrupt Controller (EIC) IRQ 14 */ + EIC_15_IRQn = 27, /**< 27 SAME54P20A External Interrupt Controller (EIC) IRQ 15 */ + FREQM_IRQn = 28, /**< 28 SAME54P20A Frequency Meter (FREQM) */ + NVMCTRL_0_IRQn = 29, /**< 29 SAME54P20A Non-Volatile Memory Controller (NVMCTRL) IRQ 0 */ + NVMCTRL_1_IRQn = 30, /**< 30 SAME54P20A Non-Volatile Memory Controller (NVMCTRL) IRQ 1 */ + DMAC_0_IRQn = 31, /**< 31 SAME54P20A Direct Memory Access Controller (DMAC) IRQ 0 */ + DMAC_1_IRQn = 32, /**< 32 SAME54P20A Direct Memory Access Controller (DMAC) IRQ 1 */ + DMAC_2_IRQn = 33, /**< 33 SAME54P20A Direct Memory Access Controller (DMAC) IRQ 2 */ + DMAC_3_IRQn = 34, /**< 34 SAME54P20A Direct Memory Access Controller (DMAC) IRQ 3 */ + DMAC_4_IRQn = 35, /**< 35 SAME54P20A Direct Memory Access Controller (DMAC) IRQ 4 */ + EVSYS_0_IRQn = 36, /**< 36 SAME54P20A Event System Interface (EVSYS) IRQ 0 */ + EVSYS_1_IRQn = 37, /**< 37 SAME54P20A Event System Interface (EVSYS) IRQ 1 */ + EVSYS_2_IRQn = 38, /**< 38 SAME54P20A Event System Interface (EVSYS) IRQ 2 */ + EVSYS_3_IRQn = 39, /**< 39 SAME54P20A Event System Interface (EVSYS) IRQ 3 */ + EVSYS_4_IRQn = 40, /**< 40 SAME54P20A Event System Interface (EVSYS) IRQ 4 */ + PAC_IRQn = 41, /**< 41 SAME54P20A Peripheral Access Controller (PAC) */ + RAMECC_IRQn = 45, /**< 45 SAME54P20A RAM ECC (RAMECC) */ + SERCOM0_0_IRQn = 46, /**< 46 SAME54P20A Serial Communication Interface 0 (SERCOM0) IRQ 0 */ + SERCOM0_1_IRQn = 47, /**< 47 SAME54P20A Serial Communication Interface 0 (SERCOM0) IRQ 1 */ + SERCOM0_2_IRQn = 48, /**< 48 SAME54P20A Serial Communication Interface 0 (SERCOM0) IRQ 2 */ + SERCOM0_3_IRQn = 49, /**< 49 SAME54P20A Serial Communication Interface 0 (SERCOM0) IRQ 3 */ + SERCOM1_0_IRQn = 50, /**< 50 SAME54P20A Serial Communication Interface 1 (SERCOM1) IRQ 0 */ + SERCOM1_1_IRQn = 51, /**< 51 SAME54P20A Serial Communication Interface 1 (SERCOM1) IRQ 1 */ + SERCOM1_2_IRQn = 52, /**< 52 SAME54P20A Serial Communication Interface 1 (SERCOM1) IRQ 2 */ + SERCOM1_3_IRQn = 53, /**< 53 SAME54P20A Serial Communication Interface 1 (SERCOM1) IRQ 3 */ + SERCOM2_0_IRQn = 54, /**< 54 SAME54P20A Serial Communication Interface 2 (SERCOM2) IRQ 0 */ + SERCOM2_1_IRQn = 55, /**< 55 SAME54P20A Serial Communication Interface 2 (SERCOM2) IRQ 1 */ + SERCOM2_2_IRQn = 56, /**< 56 SAME54P20A Serial Communication Interface 2 (SERCOM2) IRQ 2 */ + SERCOM2_3_IRQn = 57, /**< 57 SAME54P20A Serial Communication Interface 2 (SERCOM2) IRQ 3 */ + SERCOM3_0_IRQn = 58, /**< 58 SAME54P20A Serial Communication Interface 3 (SERCOM3) IRQ 0 */ + SERCOM3_1_IRQn = 59, /**< 59 SAME54P20A Serial Communication Interface 3 (SERCOM3) IRQ 1 */ + SERCOM3_2_IRQn = 60, /**< 60 SAME54P20A Serial Communication Interface 3 (SERCOM3) IRQ 2 */ + SERCOM3_3_IRQn = 61, /**< 61 SAME54P20A Serial Communication Interface 3 (SERCOM3) IRQ 3 */ + SERCOM4_0_IRQn = 62, /**< 62 SAME54P20A Serial Communication Interface 4 (SERCOM4) IRQ 0 */ + SERCOM4_1_IRQn = 63, /**< 63 SAME54P20A Serial Communication Interface 4 (SERCOM4) IRQ 1 */ + SERCOM4_2_IRQn = 64, /**< 64 SAME54P20A Serial Communication Interface 4 (SERCOM4) IRQ 2 */ + SERCOM4_3_IRQn = 65, /**< 65 SAME54P20A Serial Communication Interface 4 (SERCOM4) IRQ 3 */ + SERCOM5_0_IRQn = 66, /**< 66 SAME54P20A Serial Communication Interface 5 (SERCOM5) IRQ 0 */ + SERCOM5_1_IRQn = 67, /**< 67 SAME54P20A Serial Communication Interface 5 (SERCOM5) IRQ 1 */ + SERCOM5_2_IRQn = 68, /**< 68 SAME54P20A Serial Communication Interface 5 (SERCOM5) IRQ 2 */ + SERCOM5_3_IRQn = 69, /**< 69 SAME54P20A Serial Communication Interface 5 (SERCOM5) IRQ 3 */ + SERCOM6_0_IRQn = 70, /**< 70 SAME54P20A Serial Communication Interface 6 (SERCOM6) IRQ 0 */ + SERCOM6_1_IRQn = 71, /**< 71 SAME54P20A Serial Communication Interface 6 (SERCOM6) IRQ 1 */ + SERCOM6_2_IRQn = 72, /**< 72 SAME54P20A Serial Communication Interface 6 (SERCOM6) IRQ 2 */ + SERCOM6_3_IRQn = 73, /**< 73 SAME54P20A Serial Communication Interface 6 (SERCOM6) IRQ 3 */ + SERCOM7_0_IRQn = 74, /**< 74 SAME54P20A Serial Communication Interface 7 (SERCOM7) IRQ 0 */ + SERCOM7_1_IRQn = 75, /**< 75 SAME54P20A Serial Communication Interface 7 (SERCOM7) IRQ 1 */ + SERCOM7_2_IRQn = 76, /**< 76 SAME54P20A Serial Communication Interface 7 (SERCOM7) IRQ 2 */ + SERCOM7_3_IRQn = 77, /**< 77 SAME54P20A Serial Communication Interface 7 (SERCOM7) IRQ 3 */ + CAN0_IRQn = 78, /**< 78 SAME54P20A Control Area Network 0 (CAN0) */ + CAN1_IRQn = 79, /**< 79 SAME54P20A Control Area Network 1 (CAN1) */ + USB_0_IRQn = 80, /**< 80 SAME54P20A Universal Serial Bus (USB) IRQ 0 */ + USB_1_IRQn = 81, /**< 81 SAME54P20A Universal Serial Bus (USB) IRQ 1 */ + USB_2_IRQn = 82, /**< 82 SAME54P20A Universal Serial Bus (USB) IRQ 2 */ + USB_3_IRQn = 83, /**< 83 SAME54P20A Universal Serial Bus (USB) IRQ 3 */ + GMAC_IRQn = 84, /**< 84 SAME54P20A Ethernet MAC (GMAC) */ + TCC0_0_IRQn = 85, /**< 85 SAME54P20A Timer Counter Control 0 (TCC0) IRQ 0 */ + TCC0_1_IRQn = 86, /**< 86 SAME54P20A Timer Counter Control 0 (TCC0) IRQ 1 */ + TCC0_2_IRQn = 87, /**< 87 SAME54P20A Timer Counter Control 0 (TCC0) IRQ 2 */ + TCC0_3_IRQn = 88, /**< 88 SAME54P20A Timer Counter Control 0 (TCC0) IRQ 3 */ + TCC0_4_IRQn = 89, /**< 89 SAME54P20A Timer Counter Control 0 (TCC0) IRQ 4 */ + TCC0_5_IRQn = 90, /**< 90 SAME54P20A Timer Counter Control 0 (TCC0) IRQ 5 */ + TCC0_6_IRQn = 91, /**< 91 SAME54P20A Timer Counter Control 0 (TCC0) IRQ 6 */ + TCC1_0_IRQn = 92, /**< 92 SAME54P20A Timer Counter Control 1 (TCC1) IRQ 0 */ + TCC1_1_IRQn = 93, /**< 93 SAME54P20A Timer Counter Control 1 (TCC1) IRQ 1 */ + TCC1_2_IRQn = 94, /**< 94 SAME54P20A Timer Counter Control 1 (TCC1) IRQ 2 */ + TCC1_3_IRQn = 95, /**< 95 SAME54P20A Timer Counter Control 1 (TCC1) IRQ 3 */ + TCC1_4_IRQn = 96, /**< 96 SAME54P20A Timer Counter Control 1 (TCC1) IRQ 4 */ + TCC2_0_IRQn = 97, /**< 97 SAME54P20A Timer Counter Control 2 (TCC2) IRQ 0 */ + TCC2_1_IRQn = 98, /**< 98 SAME54P20A Timer Counter Control 2 (TCC2) IRQ 1 */ + TCC2_2_IRQn = 99, /**< 99 SAME54P20A Timer Counter Control 2 (TCC2) IRQ 2 */ + TCC2_3_IRQn = 100, /**< 100 SAME54P20A Timer Counter Control 2 (TCC2) IRQ 3 */ + TCC3_0_IRQn = 101, /**< 101 SAME54P20A Timer Counter Control 3 (TCC3) IRQ 0 */ + TCC3_1_IRQn = 102, /**< 102 SAME54P20A Timer Counter Control 3 (TCC3) IRQ 1 */ + TCC3_2_IRQn = 103, /**< 103 SAME54P20A Timer Counter Control 3 (TCC3) IRQ 2 */ + TCC4_0_IRQn = 104, /**< 104 SAME54P20A Timer Counter Control 4 (TCC4) IRQ 0 */ + TCC4_1_IRQn = 105, /**< 105 SAME54P20A Timer Counter Control 4 (TCC4) IRQ 1 */ + TCC4_2_IRQn = 106, /**< 106 SAME54P20A Timer Counter Control 4 (TCC4) IRQ 2 */ + TC0_IRQn = 107, /**< 107 SAME54P20A Basic Timer Counter 0 (TC0) */ + TC1_IRQn = 108, /**< 108 SAME54P20A Basic Timer Counter 1 (TC1) */ + TC2_IRQn = 109, /**< 109 SAME54P20A Basic Timer Counter 2 (TC2) */ + TC3_IRQn = 110, /**< 110 SAME54P20A Basic Timer Counter 3 (TC3) */ + TC4_IRQn = 111, /**< 111 SAME54P20A Basic Timer Counter 4 (TC4) */ + TC5_IRQn = 112, /**< 112 SAME54P20A Basic Timer Counter 5 (TC5) */ + TC6_IRQn = 113, /**< 113 SAME54P20A Basic Timer Counter 6 (TC6) */ + TC7_IRQn = 114, /**< 114 SAME54P20A Basic Timer Counter 7 (TC7) */ + PDEC_0_IRQn = 115, /**< 115 SAME54P20A Quadrature Decodeur (PDEC) IRQ 0 */ + PDEC_1_IRQn = 116, /**< 116 SAME54P20A Quadrature Decodeur (PDEC) IRQ 1 */ + PDEC_2_IRQn = 117, /**< 117 SAME54P20A Quadrature Decodeur (PDEC) IRQ 2 */ + ADC0_0_IRQn = 118, /**< 118 SAME54P20A Analog Digital Converter 0 (ADC0) IRQ 0 */ + ADC0_1_IRQn = 119, /**< 119 SAME54P20A Analog Digital Converter 0 (ADC0) IRQ 1 */ + ADC1_0_IRQn = 120, /**< 120 SAME54P20A Analog Digital Converter 1 (ADC1) IRQ 0 */ + ADC1_1_IRQn = 121, /**< 121 SAME54P20A Analog Digital Converter 1 (ADC1) IRQ 1 */ + AC_IRQn = 122, /**< 122 SAME54P20A Analog Comparators (AC) */ + DAC_0_IRQn = 123, /**< 123 SAME54P20A Digital-to-Analog Converter (DAC) IRQ 0 */ + DAC_1_IRQn = 124, /**< 124 SAME54P20A Digital-to-Analog Converter (DAC) IRQ 1 */ + DAC_2_IRQn = 125, /**< 125 SAME54P20A Digital-to-Analog Converter (DAC) IRQ 2 */ + DAC_3_IRQn = 126, /**< 126 SAME54P20A Digital-to-Analog Converter (DAC) IRQ 3 */ + DAC_4_IRQn = 127, /**< 127 SAME54P20A Digital-to-Analog Converter (DAC) IRQ 4 */ + I2S_IRQn = 128, /**< 128 SAME54P20A Inter-IC Sound Interface (I2S) */ + PCC_IRQn = 129, /**< 129 SAME54P20A Parallel Capture Controller (PCC) */ + AES_IRQn = 130, /**< 130 SAME54P20A Advanced Encryption Standard (AES) */ + TRNG_IRQn = 131, /**< 131 SAME54P20A True Random Generator (TRNG) */ + ICM_IRQn = 132, /**< 132 SAME54P20A Integrity Check Monitor (ICM) */ + PUKCC_IRQn = 133, /**< 133 SAME54P20A PUblic-Key Cryptography Controller (PUKCC) */ + QSPI_IRQn = 134, /**< 134 SAME54P20A Quad SPI interface (QSPI) */ + SDHC0_IRQn = 135, /**< 135 SAME54P20A SD/MMC Host Controller 0 (SDHC0) */ + SDHC1_IRQn = 136, /**< 136 SAME54P20A SD/MMC Host Controller 1 (SDHC1) */ + + PERIPH_COUNT_IRQn = 137 /**< Number of peripheral IDs */ +} IRQn_Type; + +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNonMaskableInt_Handler; + void* pfnHardFault_Handler; + void* pfnMemManagement_Handler; + void* pfnBusFault_Handler; + void* pfnUsageFault_Handler; + void* pvReservedM9; + void* pvReservedM8; + void* pvReservedM7; + void* pvReservedM6; + void* pfnSVCall_Handler; + void* pfnDebugMonitor_Handler; + void* pvReservedM3; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; + + /* Peripheral handlers */ + void* pfnPM_Handler; /* 0 Power Manager */ + void* pfnMCLK_Handler; /* 1 Main Clock */ + void* pfnOSCCTRL_0_Handler; /* 2 Oscillators Control IRQ 0 */ + void* pfnOSCCTRL_1_Handler; /* 3 Oscillators Control IRQ 1 */ + void* pfnOSCCTRL_2_Handler; /* 4 Oscillators Control IRQ 2 */ + void* pfnOSCCTRL_3_Handler; /* 5 Oscillators Control IRQ 3 */ + void* pfnOSCCTRL_4_Handler; /* 6 Oscillators Control IRQ 4 */ + void* pfnOSC32KCTRL_Handler; /* 7 32kHz Oscillators Control */ + void* pfnSUPC_0_Handler; /* 8 Supply Controller IRQ 0 */ + void* pfnSUPC_1_Handler; /* 9 Supply Controller IRQ 1 */ + void* pfnWDT_Handler; /* 10 Watchdog Timer */ + void* pfnRTC_Handler; /* 11 Real-Time Counter */ + void* pfnEIC_0_Handler; /* 12 External Interrupt Controller IRQ 0 */ + void* pfnEIC_1_Handler; /* 13 External Interrupt Controller IRQ 1 */ + void* pfnEIC_2_Handler; /* 14 External Interrupt Controller IRQ 2 */ + void* pfnEIC_3_Handler; /* 15 External Interrupt Controller IRQ 3 */ + void* pfnEIC_4_Handler; /* 16 External Interrupt Controller IRQ 4 */ + void* pfnEIC_5_Handler; /* 17 External Interrupt Controller IRQ 5 */ + void* pfnEIC_6_Handler; /* 18 External Interrupt Controller IRQ 6 */ + void* pfnEIC_7_Handler; /* 19 External Interrupt Controller IRQ 7 */ + void* pfnEIC_8_Handler; /* 20 External Interrupt Controller IRQ 8 */ + void* pfnEIC_9_Handler; /* 21 External Interrupt Controller IRQ 9 */ + void* pfnEIC_10_Handler; /* 22 External Interrupt Controller IRQ 10 */ + void* pfnEIC_11_Handler; /* 23 External Interrupt Controller IRQ 11 */ + void* pfnEIC_12_Handler; /* 24 External Interrupt Controller IRQ 12 */ + void* pfnEIC_13_Handler; /* 25 External Interrupt Controller IRQ 13 */ + void* pfnEIC_14_Handler; /* 26 External Interrupt Controller IRQ 14 */ + void* pfnEIC_15_Handler; /* 27 External Interrupt Controller IRQ 15 */ + void* pfnFREQM_Handler; /* 28 Frequency Meter */ + void* pfnNVMCTRL_0_Handler; /* 29 Non-Volatile Memory Controller IRQ 0 */ + void* pfnNVMCTRL_1_Handler; /* 30 Non-Volatile Memory Controller IRQ 1 */ + void* pfnDMAC_0_Handler; /* 31 Direct Memory Access Controller IRQ 0 */ + void* pfnDMAC_1_Handler; /* 32 Direct Memory Access Controller IRQ 1 */ + void* pfnDMAC_2_Handler; /* 33 Direct Memory Access Controller IRQ 2 */ + void* pfnDMAC_3_Handler; /* 34 Direct Memory Access Controller IRQ 3 */ + void* pfnDMAC_4_Handler; /* 35 Direct Memory Access Controller IRQ 4 */ + void* pfnEVSYS_0_Handler; /* 36 Event System Interface IRQ 0 */ + void* pfnEVSYS_1_Handler; /* 37 Event System Interface IRQ 1 */ + void* pfnEVSYS_2_Handler; /* 38 Event System Interface IRQ 2 */ + void* pfnEVSYS_3_Handler; /* 39 Event System Interface IRQ 3 */ + void* pfnEVSYS_4_Handler; /* 40 Event System Interface IRQ 4 */ + void* pfnPAC_Handler; /* 41 Peripheral Access Controller */ + void* pvReserved42; + void* pvReserved43; + void* pvReserved44; + void* pfnRAMECC_Handler; /* 45 RAM ECC */ + void* pfnSERCOM0_0_Handler; /* 46 Serial Communication Interface 0 IRQ 0 */ + void* pfnSERCOM0_1_Handler; /* 47 Serial Communication Interface 0 IRQ 1 */ + void* pfnSERCOM0_2_Handler; /* 48 Serial Communication Interface 0 IRQ 2 */ + void* pfnSERCOM0_3_Handler; /* 49 Serial Communication Interface 0 IRQ 3 */ + void* pfnSERCOM1_0_Handler; /* 50 Serial Communication Interface 1 IRQ 0 */ + void* pfnSERCOM1_1_Handler; /* 51 Serial Communication Interface 1 IRQ 1 */ + void* pfnSERCOM1_2_Handler; /* 52 Serial Communication Interface 1 IRQ 2 */ + void* pfnSERCOM1_3_Handler; /* 53 Serial Communication Interface 1 IRQ 3 */ + void* pfnSERCOM2_0_Handler; /* 54 Serial Communication Interface 2 IRQ 0 */ + void* pfnSERCOM2_1_Handler; /* 55 Serial Communication Interface 2 IRQ 1 */ + void* pfnSERCOM2_2_Handler; /* 56 Serial Communication Interface 2 IRQ 2 */ + void* pfnSERCOM2_3_Handler; /* 57 Serial Communication Interface 2 IRQ 3 */ + void* pfnSERCOM3_0_Handler; /* 58 Serial Communication Interface 3 IRQ 0 */ + void* pfnSERCOM3_1_Handler; /* 59 Serial Communication Interface 3 IRQ 1 */ + void* pfnSERCOM3_2_Handler; /* 60 Serial Communication Interface 3 IRQ 2 */ + void* pfnSERCOM3_3_Handler; /* 61 Serial Communication Interface 3 IRQ 3 */ + void* pfnSERCOM4_0_Handler; /* 62 Serial Communication Interface 4 IRQ 0 */ + void* pfnSERCOM4_1_Handler; /* 63 Serial Communication Interface 4 IRQ 1 */ + void* pfnSERCOM4_2_Handler; /* 64 Serial Communication Interface 4 IRQ 2 */ + void* pfnSERCOM4_3_Handler; /* 65 Serial Communication Interface 4 IRQ 3 */ + void* pfnSERCOM5_0_Handler; /* 66 Serial Communication Interface 5 IRQ 0 */ + void* pfnSERCOM5_1_Handler; /* 67 Serial Communication Interface 5 IRQ 1 */ + void* pfnSERCOM5_2_Handler; /* 68 Serial Communication Interface 5 IRQ 2 */ + void* pfnSERCOM5_3_Handler; /* 69 Serial Communication Interface 5 IRQ 3 */ + void* pfnSERCOM6_0_Handler; /* 70 Serial Communication Interface 6 IRQ 0 */ + void* pfnSERCOM6_1_Handler; /* 71 Serial Communication Interface 6 IRQ 1 */ + void* pfnSERCOM6_2_Handler; /* 72 Serial Communication Interface 6 IRQ 2 */ + void* pfnSERCOM6_3_Handler; /* 73 Serial Communication Interface 6 IRQ 3 */ + void* pfnSERCOM7_0_Handler; /* 74 Serial Communication Interface 7 IRQ 0 */ + void* pfnSERCOM7_1_Handler; /* 75 Serial Communication Interface 7 IRQ 1 */ + void* pfnSERCOM7_2_Handler; /* 76 Serial Communication Interface 7 IRQ 2 */ + void* pfnSERCOM7_3_Handler; /* 77 Serial Communication Interface 7 IRQ 3 */ + void* pfnCAN0_Handler; /* 78 Control Area Network 0 */ + void* pfnCAN1_Handler; /* 79 Control Area Network 1 */ + void* pfnUSB_0_Handler; /* 80 Universal Serial Bus IRQ 0 */ + void* pfnUSB_1_Handler; /* 81 Universal Serial Bus IRQ 1 */ + void* pfnUSB_2_Handler; /* 82 Universal Serial Bus IRQ 2 */ + void* pfnUSB_3_Handler; /* 83 Universal Serial Bus IRQ 3 */ + void* pfnGMAC_Handler; /* 84 Ethernet MAC */ + void* pfnTCC0_0_Handler; /* 85 Timer Counter Control 0 IRQ 0 */ + void* pfnTCC0_1_Handler; /* 86 Timer Counter Control 0 IRQ 1 */ + void* pfnTCC0_2_Handler; /* 87 Timer Counter Control 0 IRQ 2 */ + void* pfnTCC0_3_Handler; /* 88 Timer Counter Control 0 IRQ 3 */ + void* pfnTCC0_4_Handler; /* 89 Timer Counter Control 0 IRQ 4 */ + void* pfnTCC0_5_Handler; /* 90 Timer Counter Control 0 IRQ 5 */ + void* pfnTCC0_6_Handler; /* 91 Timer Counter Control 0 IRQ 6 */ + void* pfnTCC1_0_Handler; /* 92 Timer Counter Control 1 IRQ 0 */ + void* pfnTCC1_1_Handler; /* 93 Timer Counter Control 1 IRQ 1 */ + void* pfnTCC1_2_Handler; /* 94 Timer Counter Control 1 IRQ 2 */ + void* pfnTCC1_3_Handler; /* 95 Timer Counter Control 1 IRQ 3 */ + void* pfnTCC1_4_Handler; /* 96 Timer Counter Control 1 IRQ 4 */ + void* pfnTCC2_0_Handler; /* 97 Timer Counter Control 2 IRQ 0 */ + void* pfnTCC2_1_Handler; /* 98 Timer Counter Control 2 IRQ 1 */ + void* pfnTCC2_2_Handler; /* 99 Timer Counter Control 2 IRQ 2 */ + void* pfnTCC2_3_Handler; /* 100 Timer Counter Control 2 IRQ 3 */ + void* pfnTCC3_0_Handler; /* 101 Timer Counter Control 3 IRQ 0 */ + void* pfnTCC3_1_Handler; /* 102 Timer Counter Control 3 IRQ 1 */ + void* pfnTCC3_2_Handler; /* 103 Timer Counter Control 3 IRQ 2 */ + void* pfnTCC4_0_Handler; /* 104 Timer Counter Control 4 IRQ 0 */ + void* pfnTCC4_1_Handler; /* 105 Timer Counter Control 4 IRQ 1 */ + void* pfnTCC4_2_Handler; /* 106 Timer Counter Control 4 IRQ 2 */ + void* pfnTC0_Handler; /* 107 Basic Timer Counter 0 */ + void* pfnTC1_Handler; /* 108 Basic Timer Counter 1 */ + void* pfnTC2_Handler; /* 109 Basic Timer Counter 2 */ + void* pfnTC3_Handler; /* 110 Basic Timer Counter 3 */ + void* pfnTC4_Handler; /* 111 Basic Timer Counter 4 */ + void* pfnTC5_Handler; /* 112 Basic Timer Counter 5 */ + void* pfnTC6_Handler; /* 113 Basic Timer Counter 6 */ + void* pfnTC7_Handler; /* 114 Basic Timer Counter 7 */ + void* pfnPDEC_0_Handler; /* 115 Quadrature Decodeur IRQ 0 */ + void* pfnPDEC_1_Handler; /* 116 Quadrature Decodeur IRQ 1 */ + void* pfnPDEC_2_Handler; /* 117 Quadrature Decodeur IRQ 2 */ + void* pfnADC0_0_Handler; /* 118 Analog Digital Converter 0 IRQ 0 */ + void* pfnADC0_1_Handler; /* 119 Analog Digital Converter 0 IRQ 1 */ + void* pfnADC1_0_Handler; /* 120 Analog Digital Converter 1 IRQ 0 */ + void* pfnADC1_1_Handler; /* 121 Analog Digital Converter 1 IRQ 1 */ + void* pfnAC_Handler; /* 122 Analog Comparators */ + void* pfnDAC_0_Handler; /* 123 Digital-to-Analog Converter IRQ 0 */ + void* pfnDAC_1_Handler; /* 124 Digital-to-Analog Converter IRQ 1 */ + void* pfnDAC_2_Handler; /* 125 Digital-to-Analog Converter IRQ 2 */ + void* pfnDAC_3_Handler; /* 126 Digital-to-Analog Converter IRQ 3 */ + void* pfnDAC_4_Handler; /* 127 Digital-to-Analog Converter IRQ 4 */ + void* pfnI2S_Handler; /* 128 Inter-IC Sound Interface */ + void* pfnPCC_Handler; /* 129 Parallel Capture Controller */ + void* pfnAES_Handler; /* 130 Advanced Encryption Standard */ + void* pfnTRNG_Handler; /* 131 True Random Generator */ + void* pfnICM_Handler; /* 132 Integrity Check Monitor */ + void* pfnPUKCC_Handler; /* 133 PUblic-Key Cryptography Controller */ + void* pfnQSPI_Handler; /* 134 Quad SPI interface */ + void* pfnSDHC0_Handler; /* 135 SD/MMC Host Controller 0 */ + void* pfnSDHC1_Handler; /* 136 SD/MMC Host Controller 1 */ +} DeviceVectors; + +/* Cortex-M4 processor handlers */ +void Reset_Handler ( void ); +void NonMaskableInt_Handler ( void ); +void HardFault_Handler ( void ); +void MemManagement_Handler ( void ); +void BusFault_Handler ( void ); +void UsageFault_Handler ( void ); +void SVCall_Handler ( void ); +void DebugMonitor_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); + +/* Peripherals handlers */ +void PM_Handler ( void ); +void MCLK_Handler ( void ); +void OSCCTRL_0_Handler ( void ); +void OSCCTRL_1_Handler ( void ); +void OSCCTRL_2_Handler ( void ); +void OSCCTRL_3_Handler ( void ); +void OSCCTRL_4_Handler ( void ); +void OSC32KCTRL_Handler ( void ); +void SUPC_0_Handler ( void ); +void SUPC_1_Handler ( void ); +void WDT_Handler ( void ); +void RTC_Handler ( void ); +void EIC_0_Handler ( void ); +void EIC_1_Handler ( void ); +void EIC_2_Handler ( void ); +void EIC_3_Handler ( void ); +void EIC_4_Handler ( void ); +void EIC_5_Handler ( void ); +void EIC_6_Handler ( void ); +void EIC_7_Handler ( void ); +void EIC_8_Handler ( void ); +void EIC_9_Handler ( void ); +void EIC_10_Handler ( void ); +void EIC_11_Handler ( void ); +void EIC_12_Handler ( void ); +void EIC_13_Handler ( void ); +void EIC_14_Handler ( void ); +void EIC_15_Handler ( void ); +void FREQM_Handler ( void ); +void NVMCTRL_0_Handler ( void ); +void NVMCTRL_1_Handler ( void ); +void DMAC_0_Handler ( void ); +void DMAC_1_Handler ( void ); +void DMAC_2_Handler ( void ); +void DMAC_3_Handler ( void ); +void DMAC_4_Handler ( void ); +void EVSYS_0_Handler ( void ); +void EVSYS_1_Handler ( void ); +void EVSYS_2_Handler ( void ); +void EVSYS_3_Handler ( void ); +void EVSYS_4_Handler ( void ); +void PAC_Handler ( void ); +void RAMECC_Handler ( void ); +void SERCOM0_0_Handler ( void ); +void SERCOM0_1_Handler ( void ); +void SERCOM0_2_Handler ( void ); +void SERCOM0_3_Handler ( void ); +void SERCOM1_0_Handler ( void ); +void SERCOM1_1_Handler ( void ); +void SERCOM1_2_Handler ( void ); +void SERCOM1_3_Handler ( void ); +void SERCOM2_0_Handler ( void ); +void SERCOM2_1_Handler ( void ); +void SERCOM2_2_Handler ( void ); +void SERCOM2_3_Handler ( void ); +void SERCOM3_0_Handler ( void ); +void SERCOM3_1_Handler ( void ); +void SERCOM3_2_Handler ( void ); +void SERCOM3_3_Handler ( void ); +void SERCOM4_0_Handler ( void ); +void SERCOM4_1_Handler ( void ); +void SERCOM4_2_Handler ( void ); +void SERCOM4_3_Handler ( void ); +void SERCOM5_0_Handler ( void ); +void SERCOM5_1_Handler ( void ); +void SERCOM5_2_Handler ( void ); +void SERCOM5_3_Handler ( void ); +void SERCOM6_0_Handler ( void ); +void SERCOM6_1_Handler ( void ); +void SERCOM6_2_Handler ( void ); +void SERCOM6_3_Handler ( void ); +void SERCOM7_0_Handler ( void ); +void SERCOM7_1_Handler ( void ); +void SERCOM7_2_Handler ( void ); +void SERCOM7_3_Handler ( void ); +void CAN0_Handler ( void ); +void CAN1_Handler ( void ); +void USB_0_Handler ( void ); +void USB_1_Handler ( void ); +void USB_2_Handler ( void ); +void USB_3_Handler ( void ); +void GMAC_Handler ( void ); +void TCC0_0_Handler ( void ); +void TCC0_1_Handler ( void ); +void TCC0_2_Handler ( void ); +void TCC0_3_Handler ( void ); +void TCC0_4_Handler ( void ); +void TCC0_5_Handler ( void ); +void TCC0_6_Handler ( void ); +void TCC1_0_Handler ( void ); +void TCC1_1_Handler ( void ); +void TCC1_2_Handler ( void ); +void TCC1_3_Handler ( void ); +void TCC1_4_Handler ( void ); +void TCC2_0_Handler ( void ); +void TCC2_1_Handler ( void ); +void TCC2_2_Handler ( void ); +void TCC2_3_Handler ( void ); +void TCC3_0_Handler ( void ); +void TCC3_1_Handler ( void ); +void TCC3_2_Handler ( void ); +void TCC4_0_Handler ( void ); +void TCC4_1_Handler ( void ); +void TCC4_2_Handler ( void ); +void TC0_Handler ( void ); +void TC1_Handler ( void ); +void TC2_Handler ( void ); +void TC3_Handler ( void ); +void TC4_Handler ( void ); +void TC5_Handler ( void ); +void TC6_Handler ( void ); +void TC7_Handler ( void ); +void PDEC_0_Handler ( void ); +void PDEC_1_Handler ( void ); +void PDEC_2_Handler ( void ); +void ADC0_0_Handler ( void ); +void ADC0_1_Handler ( void ); +void ADC1_0_Handler ( void ); +void ADC1_1_Handler ( void ); +void AC_Handler ( void ); +void DAC_0_Handler ( void ); +void DAC_1_Handler ( void ); +void DAC_2_Handler ( void ); +void DAC_3_Handler ( void ); +void DAC_4_Handler ( void ); +void I2S_Handler ( void ); +void PCC_Handler ( void ); +void AES_Handler ( void ); +void TRNG_Handler ( void ); +void ICM_Handler ( void ); +void PUKCC_Handler ( void ); +void QSPI_Handler ( void ); +void SDHC0_Handler ( void ); +void SDHC1_Handler ( void ); + +/* + * \brief Configuration of the Cortex-M4 Processor and Core Peripherals + */ + +#define __CM4_REV 1 /*!< Core revision r0p1 */ +#define __DEBUG_LVL 3 /*!< Full debug plus DWT data matching */ +#define __FPU_PRESENT 1 /*!< FPU present or not */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ +#define __NVIC_PRIO_BITS 3 /*!< Number of bits used for Priority Levels */ +#define __TRACE_LVL 2 /*!< Full trace: ITM, DWT triggers and counters, ETM */ +#define __VTOR_PRESENT 1 /*!< VTOR present or not */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + +/** + * \brief CMSIS includes + */ + +#include +#if !defined DONT_USE_CMSIS_INIT +#include "system_same54.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/*@}*/ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAME54P20A */ +/* ************************************************************************** */ +/** \defgroup SAME54P20A_api Peripheral Software API */ +/*@{*/ + +#include "component/ac.h" +#include "component/adc.h" +#include "component/aes.h" +#include "component/can.h" +#include "component/ccl.h" +#include "component/cmcc.h" +#include "component/dac.h" +#include "component/dmac.h" +#include "component/dsu.h" +#include "component/eic.h" +#include "component/evsys.h" +#include "component/freqm.h" +#include "component/gclk.h" +#include "component/gmac.h" +#include "component/hmatrixb.h" +#include "component/icm.h" +#include "component/i2s.h" +#include "component/mclk.h" +#include "component/nvmctrl.h" +#include "component/oscctrl.h" +#include "component/osc32kctrl.h" +#include "component/pac.h" +#include "component/pcc.h" +#include "component/pdec.h" +#include "component/pm.h" +#include "component/port.h" +#include "component/qspi.h" +#include "component/ramecc.h" +#include "component/rstc.h" +#include "component/rtc.h" +#include "component/sdhc.h" +#include "component/sercom.h" +#include "component/supc.h" +#include "component/tc.h" +#include "component/tcc.h" +#include "component/trng.h" +#include "component/usb.h" +#include "component/wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/** REGISTERS ACCESS DEFINITIONS FOR SAME54P20A */ +/* ************************************************************************** */ +/** \defgroup SAME54P20A_reg Registers Access Definitions */ +/*@{*/ + +#include "instance/ac.h" +#include "instance/adc0.h" +#include "instance/adc1.h" +#include "instance/aes.h" +#include "instance/can0.h" +#include "instance/can1.h" +#include "instance/ccl.h" +#include "instance/cmcc.h" +#include "instance/dac.h" +#include "instance/dmac.h" +#include "instance/dsu.h" +#include "instance/eic.h" +#include "instance/evsys.h" +#include "instance/freqm.h" +#include "instance/gclk.h" +#include "instance/gmac.h" +#include "instance/hmatrix.h" +#include "instance/icm.h" +#include "instance/i2s.h" +#include "instance/mclk.h" +#include "instance/nvmctrl.h" +#include "instance/oscctrl.h" +#include "instance/osc32kctrl.h" +#include "instance/pac.h" +#include "instance/pcc.h" +#include "instance/pdec.h" +#include "instance/pm.h" +#include "instance/port.h" +#include "instance/pukcc.h" +#include "instance/qspi.h" +#include "instance/ramecc.h" +#include "instance/rstc.h" +#include "instance/rtc.h" +#include "instance/sdhc0.h" +#include "instance/sdhc1.h" +#include "instance/sercom0.h" +#include "instance/sercom1.h" +#include "instance/sercom2.h" +#include "instance/sercom3.h" +#include "instance/sercom4.h" +#include "instance/sercom5.h" +#include "instance/sercom6.h" +#include "instance/sercom7.h" +#include "instance/supc.h" +#include "instance/tc0.h" +#include "instance/tc1.h" +#include "instance/tc2.h" +#include "instance/tc3.h" +#include "instance/tc4.h" +#include "instance/tc5.h" +#include "instance/tc6.h" +#include "instance/tc7.h" +#include "instance/tcc0.h" +#include "instance/tcc1.h" +#include "instance/tcc2.h" +#include "instance/tcc3.h" +#include "instance/tcc4.h" +#include "instance/trng.h" +#include "instance/usb.h" +#include "instance/wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/** PERIPHERAL ID DEFINITIONS FOR SAME54P20A */ +/* ************************************************************************** */ +/** \defgroup SAME54P20A_id Peripheral Ids Definitions */ +/*@{*/ + +// Peripheral instances on HPB0 bridge +#define ID_PAC 0 /**< \brief Peripheral Access Controller (PAC) */ +#define ID_PM 1 /**< \brief Power Manager (PM) */ +#define ID_MCLK 2 /**< \brief Main Clock (MCLK) */ +#define ID_RSTC 3 /**< \brief Reset Controller (RSTC) */ +#define ID_OSCCTRL 4 /**< \brief Oscillators Control (OSCCTRL) */ +#define ID_OSC32KCTRL 5 /**< \brief 32kHz Oscillators Control (OSC32KCTRL) */ +#define ID_SUPC 6 /**< \brief Supply Controller (SUPC) */ +#define ID_GCLK 7 /**< \brief Generic Clock Generator (GCLK) */ +#define ID_WDT 8 /**< \brief Watchdog Timer (WDT) */ +#define ID_RTC 9 /**< \brief Real-Time Counter (RTC) */ +#define ID_EIC 10 /**< \brief External Interrupt Controller (EIC) */ +#define ID_FREQM 11 /**< \brief Frequency Meter (FREQM) */ +#define ID_SERCOM0 12 /**< \brief Serial Communication Interface 0 (SERCOM0) */ +#define ID_SERCOM1 13 /**< \brief Serial Communication Interface 1 (SERCOM1) */ +#define ID_TC0 14 /**< \brief Basic Timer Counter 0 (TC0) */ +#define ID_TC1 15 /**< \brief Basic Timer Counter 1 (TC1) */ + +// Peripheral instances on HPB1 bridge +#define ID_USB 32 /**< \brief Universal Serial Bus (USB) */ +#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ +#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ +#define ID_CMCC 35 /**< \brief Cortex M Cache Controller (CMCC) */ +#define ID_PORT 36 /**< \brief Port Module (PORT) */ +#define ID_DMAC 37 /**< \brief Direct Memory Access Controller (DMAC) */ +#define ID_HMATRIX 38 /**< \brief HSB Matrix (HMATRIX) */ +#define ID_EVSYS 39 /**< \brief Event System Interface (EVSYS) */ +#define ID_SERCOM2 41 /**< \brief Serial Communication Interface 2 (SERCOM2) */ +#define ID_SERCOM3 42 /**< \brief Serial Communication Interface 3 (SERCOM3) */ +#define ID_TCC0 43 /**< \brief Timer Counter Control 0 (TCC0) */ +#define ID_TCC1 44 /**< \brief Timer Counter Control 1 (TCC1) */ +#define ID_TC2 45 /**< \brief Basic Timer Counter 2 (TC2) */ +#define ID_TC3 46 /**< \brief Basic Timer Counter 3 (TC3) */ +#define ID_RAMECC 48 /**< \brief RAM ECC (RAMECC) */ + +// Peripheral instances on HPB2 bridge +#define ID_CAN0 64 /**< \brief Control Area Network 0 (CAN0) */ +#define ID_CAN1 65 /**< \brief Control Area Network 1 (CAN1) */ +#define ID_GMAC 66 /**< \brief Ethernet MAC (GMAC) */ +#define ID_TCC2 67 /**< \brief Timer Counter Control 2 (TCC2) */ +#define ID_TCC3 68 /**< \brief Timer Counter Control 3 (TCC3) */ +#define ID_TC4 69 /**< \brief Basic Timer Counter 4 (TC4) */ +#define ID_TC5 70 /**< \brief Basic Timer Counter 5 (TC5) */ +#define ID_PDEC 71 /**< \brief Quadrature Decodeur (PDEC) */ +#define ID_AC 72 /**< \brief Analog Comparators (AC) */ +#define ID_AES 73 /**< \brief Advanced Encryption Standard (AES) */ +#define ID_TRNG 74 /**< \brief True Random Generator (TRNG) */ +#define ID_ICM 75 /**< \brief Integrity Check Monitor (ICM) */ +#define ID_PUKCC 76 /**< \brief PUblic-Key Cryptography Controller (PUKCC) */ +#define ID_QSPI 77 /**< \brief Quad SPI interface (QSPI) */ +#define ID_CCL 78 /**< \brief Configurable Custom Logic (CCL) */ + +// Peripheral instances on HPB3 bridge +#define ID_SERCOM4 96 /**< \brief Serial Communication Interface 4 (SERCOM4) */ +#define ID_SERCOM5 97 /**< \brief Serial Communication Interface 5 (SERCOM5) */ +#define ID_SERCOM6 98 /**< \brief Serial Communication Interface 6 (SERCOM6) */ +#define ID_SERCOM7 99 /**< \brief Serial Communication Interface 7 (SERCOM7) */ +#define ID_TCC4 100 /**< \brief Timer Counter Control 4 (TCC4) */ +#define ID_TC6 101 /**< \brief Basic Timer Counter 6 (TC6) */ +#define ID_TC7 102 /**< \brief Basic Timer Counter 7 (TC7) */ +#define ID_ADC0 103 /**< \brief Analog Digital Converter 0 (ADC0) */ +#define ID_ADC1 104 /**< \brief Analog Digital Converter 1 (ADC1) */ +#define ID_DAC 105 /**< \brief Digital-to-Analog Converter (DAC) */ +#define ID_I2S 106 /**< \brief Inter-IC Sound Interface (I2S) */ +#define ID_PCC 107 /**< \brief Parallel Capture Controller (PCC) */ + +// Peripheral instances on AHB (as if on bridge 4) +#define ID_SDHC0 128 /**< \brief SD/MMC Host Controller (SDHC0) */ +#define ID_SDHC1 129 /**< \brief SD/MMC Host Controller (SDHC1) */ + +#define ID_PERIPH_COUNT 130 /**< \brief Max number of peripheral IDs */ +/*@}*/ + +/* ************************************************************************** */ +/** BASE ADDRESS DEFINITIONS FOR SAME54P20A */ +/* ************************************************************************** */ +/** \defgroup SAME54P20A_base Peripheral Base Address Definitions */ +/*@{*/ + +#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) +#define AC (0x42002000) /**< \brief (AC) APB Base Address */ +#define ADC0 (0x43001C00) /**< \brief (ADC0) APB Base Address */ +#define ADC1 (0x43002000) /**< \brief (ADC1) APB Base Address */ +#define AES (0x42002400) /**< \brief (AES) APB Base Address */ +#define CAN0 (0x42000000) /**< \brief (CAN0) APB Base Address */ +#define CAN1 (0x42000400) /**< \brief (CAN1) APB Base Address */ +#define CCL (0x42003800) /**< \brief (CCL) APB Base Address */ +#define CMCC (0x41006000) /**< \brief (CMCC) APB Base Address */ +#define CMCC_AHB (0x03000000) /**< \brief (CMCC) AHB Base Address */ +#define DAC (0x43002400) /**< \brief (DAC) APB Base Address */ +#define DMAC (0x4100A000) /**< \brief (DMAC) APB Base Address */ +#define DSU (0x41002000) /**< \brief (DSU) APB Base Address */ +#define EIC (0x40002800) /**< \brief (EIC) APB Base Address */ +#define EVSYS (0x4100E000) /**< \brief (EVSYS) APB Base Address */ +#define FREQM (0x40002C00) /**< \brief (FREQM) APB Base Address */ +#define GCLK (0x40001C00) /**< \brief (GCLK) APB Base Address */ +#define GMAC (0x42000800) /**< \brief (GMAC) APB Base Address */ +#define HMATRIX (0x4100C000) /**< \brief (HMATRIX) APB Base Address */ +#define ICM (0x42002C00) /**< \brief (ICM) APB Base Address */ +#define I2S (0x43002800) /**< \brief (I2S) APB Base Address */ +#define MCLK (0x40000800) /**< \brief (MCLK) APB Base Address */ +#define NVMCTRL (0x41004000) /**< \brief (NVMCTRL) APB Base Address */ +#define NVMCTRL_SW0 (0x00800080) /**< \brief (NVMCTRL) SW0 Base Address */ +#define NVMCTRL_TEMP_LOG (0x00800100) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ +#define NVMCTRL_USER (0x00804000) /**< \brief (NVMCTRL) USER Base Address */ +#define OSCCTRL (0x40001000) /**< \brief (OSCCTRL) APB Base Address */ +#define OSC32KCTRL (0x40001400) /**< \brief (OSC32KCTRL) APB Base Address */ +#define PAC (0x40000000) /**< \brief (PAC) APB Base Address */ +#define PCC (0x43002C00) /**< \brief (PCC) APB Base Address */ +#define PDEC (0x42001C00) /**< \brief (PDEC) APB Base Address */ +#define PM (0x40000400) /**< \brief (PM) APB Base Address */ +#define PORT (0x41008000) /**< \brief (PORT) APB Base Address */ +#define PUKCC (0x42003000) /**< \brief (PUKCC) APB Base Address */ +#define PUKCC_AHB (0x02000000) /**< \brief (PUKCC) AHB Base Address */ +#define QSPI (0x42003400) /**< \brief (QSPI) APB Base Address */ +#define QSPI_AHB (0x04000000) /**< \brief (QSPI) AHB Base Address */ +#define RAMECC (0x41020000) /**< \brief (RAMECC) APB Base Address */ +#define RSTC (0x40000C00) /**< \brief (RSTC) APB Base Address */ +#define RTC (0x40002400) /**< \brief (RTC) APB Base Address */ +#define SDHC0 (0x45000000) /**< \brief (SDHC0) AHB Base Address */ +#define SDHC1 (0x46000000) /**< \brief (SDHC1) AHB Base Address */ +#define SERCOM0 (0x40003000) /**< \brief (SERCOM0) APB Base Address */ +#define SERCOM1 (0x40003400) /**< \brief (SERCOM1) APB Base Address */ +#define SERCOM2 (0x41012000) /**< \brief (SERCOM2) APB Base Address */ +#define SERCOM3 (0x41014000) /**< \brief (SERCOM3) APB Base Address */ +#define SERCOM4 (0x43000000) /**< \brief (SERCOM4) APB Base Address */ +#define SERCOM5 (0x43000400) /**< \brief (SERCOM5) APB Base Address */ +#define SERCOM6 (0x43000800) /**< \brief (SERCOM6) APB Base Address */ +#define SERCOM7 (0x43000C00) /**< \brief (SERCOM7) APB Base Address */ +#define SUPC (0x40001800) /**< \brief (SUPC) APB Base Address */ +#define TC0 (0x40003800) /**< \brief (TC0) APB Base Address */ +#define TC1 (0x40003C00) /**< \brief (TC1) APB Base Address */ +#define TC2 (0x4101A000) /**< \brief (TC2) APB Base Address */ +#define TC3 (0x4101C000) /**< \brief (TC3) APB Base Address */ +#define TC4 (0x42001400) /**< \brief (TC4) APB Base Address */ +#define TC5 (0x42001800) /**< \brief (TC5) APB Base Address */ +#define TC6 (0x43001400) /**< \brief (TC6) APB Base Address */ +#define TC7 (0x43001800) /**< \brief (TC7) APB Base Address */ +#define TCC0 (0x41016000) /**< \brief (TCC0) APB Base Address */ +#define TCC1 (0x41018000) /**< \brief (TCC1) APB Base Address */ +#define TCC2 (0x42000C00) /**< \brief (TCC2) APB Base Address */ +#define TCC3 (0x42001000) /**< \brief (TCC3) APB Base Address */ +#define TCC4 (0x43001000) /**< \brief (TCC4) APB Base Address */ +#define TRNG (0x42002800) /**< \brief (TRNG) APB Base Address */ +#define USB (0x41000000) /**< \brief (USB) APB Base Address */ +#define WDT (0x40002000) /**< \brief (WDT) APB Base Address */ +#else +#define AC ((Ac *)0x42002000UL) /**< \brief (AC) APB Base Address */ +#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ +#define AC_INSTS { AC } /**< \brief (AC) Instances List */ + +#define ADC0 ((Adc *)0x43001C00UL) /**< \brief (ADC0) APB Base Address */ +#define ADC1 ((Adc *)0x43002000UL) /**< \brief (ADC1) APB Base Address */ +#define ADC_INST_NUM 2 /**< \brief (ADC) Number of instances */ +#define ADC_INSTS { ADC0, ADC1 } /**< \brief (ADC) Instances List */ + +#define AES ((Aes *)0x42002400UL) /**< \brief (AES) APB Base Address */ +#define AES_INST_NUM 1 /**< \brief (AES) Number of instances */ +#define AES_INSTS { AES } /**< \brief (AES) Instances List */ + +#define CAN0 ((Can *)0x42000000UL) /**< \brief (CAN0) APB Base Address */ +#define CAN1 ((Can *)0x42000400UL) /**< \brief (CAN1) APB Base Address */ +#define CAN_INST_NUM 2 /**< \brief (CAN) Number of instances */ +#define CAN_INSTS { CAN0, CAN1 } /**< \brief (CAN) Instances List */ + +#define CCL ((Ccl *)0x42003800UL) /**< \brief (CCL) APB Base Address */ +#define CCL_INST_NUM 1 /**< \brief (CCL) Number of instances */ +#define CCL_INSTS { CCL } /**< \brief (CCL) Instances List */ + +#define CMCC ((Cmcc *)0x41006000UL) /**< \brief (CMCC) APB Base Address */ +#define CMCC_AHB (0x03000000UL) /**< \brief (CMCC) AHB Base Address */ +#define CMCC_INST_NUM 1 /**< \brief (CMCC) Number of instances */ +#define CMCC_INSTS { CMCC } /**< \brief (CMCC) Instances List */ + +#define DAC ((Dac *)0x43002400UL) /**< \brief (DAC) APB Base Address */ +#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */ +#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */ + +#define DMAC ((Dmac *)0x4100A000UL) /**< \brief (DMAC) APB Base Address */ +#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ +#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ + +#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ +#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ +#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ + +#define EIC ((Eic *)0x40002800UL) /**< \brief (EIC) APB Base Address */ +#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ +#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ + +#define EVSYS ((Evsys *)0x4100E000UL) /**< \brief (EVSYS) APB Base Address */ +#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ +#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ + +#define FREQM ((Freqm *)0x40002C00UL) /**< \brief (FREQM) APB Base Address */ +#define FREQM_INST_NUM 1 /**< \brief (FREQM) Number of instances */ +#define FREQM_INSTS { FREQM } /**< \brief (FREQM) Instances List */ + +#define GCLK ((Gclk *)0x40001C00UL) /**< \brief (GCLK) APB Base Address */ +#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ +#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ + +#define GMAC ((Gmac *)0x42000800UL) /**< \brief (GMAC) APB Base Address */ +#define GMAC_INST_NUM 1 /**< \brief (GMAC) Number of instances */ +#define GMAC_INSTS { GMAC } /**< \brief (GMAC) Instances List */ + +#define HMATRIX ((Hmatrixb *)0x4100C000UL) /**< \brief (HMATRIX) APB Base Address */ +#define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */ +#define HMATRIXB_INSTS { HMATRIX } /**< \brief (HMATRIXB) Instances List */ + +#define ICM ((Icm *)0x42002C00UL) /**< \brief (ICM) APB Base Address */ +#define ICM_INST_NUM 1 /**< \brief (ICM) Number of instances */ +#define ICM_INSTS { ICM } /**< \brief (ICM) Instances List */ + +#define I2S ((I2s *)0x43002800UL) /**< \brief (I2S) APB Base Address */ +#define I2S_INST_NUM 1 /**< \brief (I2S) Number of instances */ +#define I2S_INSTS { I2S } /**< \brief (I2S) Instances List */ + +#define MCLK ((Mclk *)0x40000800UL) /**< \brief (MCLK) APB Base Address */ +#define MCLK_INST_NUM 1 /**< \brief (MCLK) Number of instances */ +#define MCLK_INSTS { MCLK } /**< \brief (MCLK) Instances List */ + +#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ +#define NVMCTRL_SW0 (0x00800080UL) /**< \brief (NVMCTRL) SW0 Base Address */ +#define NVMCTRL_TEMP_LOG (0x00800100UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ +#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ +#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ +#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ + +#define OSCCTRL ((Oscctrl *)0x40001000UL) /**< \brief (OSCCTRL) APB Base Address */ +#define OSCCTRL_INST_NUM 1 /**< \brief (OSCCTRL) Number of instances */ +#define OSCCTRL_INSTS { OSCCTRL } /**< \brief (OSCCTRL) Instances List */ + +#define OSC32KCTRL ((Osc32kctrl *)0x40001400UL) /**< \brief (OSC32KCTRL) APB Base Address */ +#define OSC32KCTRL_INST_NUM 1 /**< \brief (OSC32KCTRL) Number of instances */ +#define OSC32KCTRL_INSTS { OSC32KCTRL } /**< \brief (OSC32KCTRL) Instances List */ + +#define PAC ((Pac *)0x40000000UL) /**< \brief (PAC) APB Base Address */ +#define PAC_INST_NUM 1 /**< \brief (PAC) Number of instances */ +#define PAC_INSTS { PAC } /**< \brief (PAC) Instances List */ + +#define PCC ((Pcc *)0x43002C00UL) /**< \brief (PCC) APB Base Address */ +#define PCC_INST_NUM 1 /**< \brief (PCC) Number of instances */ +#define PCC_INSTS { PCC } /**< \brief (PCC) Instances List */ + +#define PDEC ((Pdec *)0x42001C00UL) /**< \brief (PDEC) APB Base Address */ +#define PDEC_INST_NUM 1 /**< \brief (PDEC) Number of instances */ +#define PDEC_INSTS { PDEC } /**< \brief (PDEC) Instances List */ + +#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */ +#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ +#define PM_INSTS { PM } /**< \brief (PM) Instances List */ + +#define PORT ((Port *)0x41008000UL) /**< \brief (PORT) APB Base Address */ +#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ +#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ + +#define PUKCC ((void *)0x42003000UL) /**< \brief (PUKCC) APB Base Address */ +#define PUKCC_AHB ((void *)0x02000000UL) /**< \brief (PUKCC) AHB Base Address */ +#define PUKCC_INST_NUM 1 /**< \brief (PUKCC) Number of instances */ +#define PUKCC_INSTS { PUKCC } /**< \brief (PUKCC) Instances List */ + +#define QSPI ((Qspi *)0x42003400UL) /**< \brief (QSPI) APB Base Address */ +#define QSPI_AHB (0x04000000UL) /**< \brief (QSPI) AHB Base Address */ +#define QSPI_INST_NUM 1 /**< \brief (QSPI) Number of instances */ +#define QSPI_INSTS { QSPI } /**< \brief (QSPI) Instances List */ + +#define RAMECC ((Ramecc *)0x41020000UL) /**< \brief (RAMECC) APB Base Address */ +#define RAMECC_INST_NUM 1 /**< \brief (RAMECC) Number of instances */ +#define RAMECC_INSTS { RAMECC } /**< \brief (RAMECC) Instances List */ + +#define RSTC ((Rstc *)0x40000C00UL) /**< \brief (RSTC) APB Base Address */ +#define RSTC_INST_NUM 1 /**< \brief (RSTC) Number of instances */ +#define RSTC_INSTS { RSTC } /**< \brief (RSTC) Instances List */ + +#define RTC ((Rtc *)0x40002400UL) /**< \brief (RTC) APB Base Address */ +#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ +#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ + +#define SDHC0 ((Sdhc *)0x45000000UL) /**< \brief (SDHC0) AHB Base Address */ +#define SDHC1 ((Sdhc *)0x46000000UL) /**< \brief (SDHC1) AHB Base Address */ +#define SDHC_INST_NUM 2 /**< \brief (SDHC) Number of instances */ +#define SDHC_INSTS { SDHC0, SDHC1 } /**< \brief (SDHC) Instances List */ + +#define SERCOM0 ((Sercom *)0x40003000UL) /**< \brief (SERCOM0) APB Base Address */ +#define SERCOM1 ((Sercom *)0x40003400UL) /**< \brief (SERCOM1) APB Base Address */ +#define SERCOM2 ((Sercom *)0x41012000UL) /**< \brief (SERCOM2) APB Base Address */ +#define SERCOM3 ((Sercom *)0x41014000UL) /**< \brief (SERCOM3) APB Base Address */ +#define SERCOM4 ((Sercom *)0x43000000UL) /**< \brief (SERCOM4) APB Base Address */ +#define SERCOM5 ((Sercom *)0x43000400UL) /**< \brief (SERCOM5) APB Base Address */ +#define SERCOM6 ((Sercom *)0x43000800UL) /**< \brief (SERCOM6) APB Base Address */ +#define SERCOM7 ((Sercom *)0x43000C00UL) /**< \brief (SERCOM7) APB Base Address */ +#define SERCOM_INST_NUM 8 /**< \brief (SERCOM) Number of instances */ +#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5, SERCOM6, SERCOM7 } /**< \brief (SERCOM) Instances List */ + +#define SUPC ((Supc *)0x40001800UL) /**< \brief (SUPC) APB Base Address */ +#define SUPC_INST_NUM 1 /**< \brief (SUPC) Number of instances */ +#define SUPC_INSTS { SUPC } /**< \brief (SUPC) Instances List */ + +#define TC0 ((Tc *)0x40003800UL) /**< \brief (TC0) APB Base Address */ +#define TC1 ((Tc *)0x40003C00UL) /**< \brief (TC1) APB Base Address */ +#define TC2 ((Tc *)0x4101A000UL) /**< \brief (TC2) APB Base Address */ +#define TC3 ((Tc *)0x4101C000UL) /**< \brief (TC3) APB Base Address */ +#define TC4 ((Tc *)0x42001400UL) /**< \brief (TC4) APB Base Address */ +#define TC5 ((Tc *)0x42001800UL) /**< \brief (TC5) APB Base Address */ +#define TC6 ((Tc *)0x43001400UL) /**< \brief (TC6) APB Base Address */ +#define TC7 ((Tc *)0x43001800UL) /**< \brief (TC7) APB Base Address */ +#define TC_INST_NUM 8 /**< \brief (TC) Number of instances */ +#define TC_INSTS { TC0, TC1, TC2, TC3, TC4, TC5, TC6, TC7 } /**< \brief (TC) Instances List */ + +#define TCC0 ((Tcc *)0x41016000UL) /**< \brief (TCC0) APB Base Address */ +#define TCC1 ((Tcc *)0x41018000UL) /**< \brief (TCC1) APB Base Address */ +#define TCC2 ((Tcc *)0x42000C00UL) /**< \brief (TCC2) APB Base Address */ +#define TCC3 ((Tcc *)0x42001000UL) /**< \brief (TCC3) APB Base Address */ +#define TCC4 ((Tcc *)0x43001000UL) /**< \brief (TCC4) APB Base Address */ +#define TCC_INST_NUM 5 /**< \brief (TCC) Number of instances */ +#define TCC_INSTS { TCC0, TCC1, TCC2, TCC3, TCC4 } /**< \brief (TCC) Instances List */ + +#define TRNG ((Trng *)0x42002800UL) /**< \brief (TRNG) APB Base Address */ +#define TRNG_INST_NUM 1 /**< \brief (TRNG) Number of instances */ +#define TRNG_INSTS { TRNG } /**< \brief (TRNG) Instances List */ + +#define USB ((Usb *)0x41000000UL) /**< \brief (USB) APB Base Address */ +#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ +#define USB_INSTS { USB } /**< \brief (USB) Instances List */ + +#define WDT ((Wdt *)0x40002000UL) /**< \brief (WDT) APB Base Address */ +#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ +#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ + +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/*@}*/ + +/* ************************************************************************** */ +/** PORT DEFINITIONS FOR SAME54P20A */ +/* ************************************************************************** */ +/** \defgroup SAME54P20A_port PORT Definitions */ +/*@{*/ + +#include "pio/same54p20a.h" +/*@}*/ + +/* ************************************************************************** */ +/** MEMORY MAPPING DEFINITIONS FOR SAME54P20A */ +/* ************************************************************************** */ + +#define HSRAM_SIZE _UL_(0x00040000) /* 256 kB */ +#define FLASH_SIZE _UL_(0x00100000) /* 1024 kB */ +#define FLASH_PAGE_SIZE 512 +#define FLASH_NB_OF_PAGES 2048 +#define FLASH_USER_PAGE_SIZE 512 +#define BKUPRAM_SIZE _UL_(0x00002000) /* 8 kB */ +#define QSPI_SIZE _UL_(0x01000000) /* 16384 kB */ + +#define FLASH_ADDR _UL_(0x00000000) /**< FLASH base address */ +#define CMCC_DATARAM_ADDR _UL_(0x03000000) /**< CMCC_DATARAM base address */ +#define CMCC_DATARAM_SIZE _UL_(0x00001000) /**< CMCC_DATARAM size */ +#define CMCC_TAGRAM_ADDR _UL_(0x03001000) /**< CMCC_TAGRAM base address */ +#define CMCC_TAGRAM_SIZE _UL_(0x00000400) /**< CMCC_TAGRAM size */ +#define CMCC_VALIDRAM_ADDR _UL_(0x03002000) /**< CMCC_VALIDRAM base address */ +#define CMCC_VALIDRAM_SIZE _UL_(0x00000040) /**< CMCC_VALIDRAM size */ +#define HSRAM_ADDR _UL_(0x20000000) /**< HSRAM base address */ +#define HSRAM_ETB_ADDR _UL_(0x20000000) /**< HSRAM_ETB base address */ +#define HSRAM_ETB_SIZE _UL_(0x00008000) /**< HSRAM_ETB size */ +#define HSRAM_RET1_ADDR _UL_(0x20000000) /**< HSRAM_RET1 base address */ +#define HSRAM_RET1_SIZE _UL_(0x00008000) /**< HSRAM_RET1 size */ +#define HPB0_ADDR _UL_(0x40000000) /**< HPB0 base address */ +#define HPB1_ADDR _UL_(0x41000000) /**< HPB1 base address */ +#define HPB2_ADDR _UL_(0x42000000) /**< HPB2 base address */ +#define HPB3_ADDR _UL_(0x43000000) /**< HPB3 base address */ +#define SEEPROM_ADDR _UL_(0x44000000) /**< SEEPROM base address */ +#define BKUPRAM_ADDR _UL_(0x47000000) /**< BKUPRAM base address */ +#define PPB_ADDR _UL_(0xE0000000) /**< PPB base address */ + +#define DSU_DID_RESETVALUE _UL_(0x61840300) +#define ADC0_TOUCH_LINES_NUM 32 +#define PORT_GROUPS 4 + +/* ************************************************************************** */ +/** ELECTRICAL DEFINITIONS FOR SAME54P20A */ +/* ************************************************************************** */ + + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* SAME54P20A_H */ diff --git a/arch/arm/SAME54/SAME54A/mcu/inc/system_same54.h b/arch/arm/SAME54/SAME54A/mcu/inc/system_same54.h index 91261ab3..e4535de1 100644 --- a/arch/arm/SAME54/SAME54A/mcu/inc/system_same54.h +++ b/arch/arm/SAME54/SAME54A/mcu/inc/system_same54.h @@ -1,48 +1,48 @@ -/** - * \file - * - * \brief Low-level initialization functions called upon device startup - * - * Copyright (c) 2020 Microchip Technology Inc. - * - * \license_start - * - * \page License - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \license_stop - * - */ - -#ifndef _SYSTEM_SAME54_H_INCLUDED_ -#define _SYSTEM_SAME54_H_INCLUDED_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include - -extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ - -void SystemInit(void); -void SystemCoreClockUpdate(void); - -#ifdef __cplusplus -} -#endif - -#endif /* _SYSTEM_SAME54_H_INCLUDED */ +/** + * \file + * + * \brief Low-level initialization functions called upon chip startup + * + * Copyright (c) 2019 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SYSTEM_SAME54_H_INCLUDED_ +#define _SYSTEM_SAME54_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ + +void SystemInit(void); +void SystemCoreClockUpdate(void); + +#ifdef __cplusplus +} +#endif + +#endif /* SYSTEM_SAME54_H_INCLUDED */ diff --git a/arch/arm/SAME54/SAME54A/mcu/src/startup_same54.c b/arch/arm/SAME54/SAME54A/mcu/src/startup_same54.c new file mode 100644 index 00000000..527e4364 --- /dev/null +++ b/arch/arm/SAME54/SAME54A/mcu/src/startup_same54.c @@ -0,0 +1,546 @@ +/** + * \file + * + * \brief gcc starttup file for SAME54 + * + * Copyright (c) 2019 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#include "same54.h" + +/* Initialize segments */ +extern uint32_t _sfixed; +extern uint32_t _efixed; +extern uint32_t _etext; +extern uint32_t _srelocate; +extern uint32_t _erelocate; +extern uint32_t _szero; +extern uint32_t _ezero; +extern uint32_t _sstack; +extern uint32_t _estack; + +/** \cond DOXYGEN_SHOULD_SKIP_THIS */ +int main(void); +/** \endcond */ + +void __libc_init_array(void); + +/* Default empty handler */ +void Dummy_Handler(void); + +/* Cortex-M4 core handlers */ +void NonMaskableInt_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void HardFault_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void MemManagement_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void BusFault_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void UsageFault_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SVCall_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void DebugMonitor_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void PendSV_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SysTick_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); + +/* Peripherals handlers */ +void PM_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void MCLK_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void OSCCTRL_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* OSCCTRL_XOSCFAIL_0, OSCCTRL_XOSCRDY_0 */ +void OSCCTRL_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* OSCCTRL_XOSCFAIL_1, OSCCTRL_XOSCRDY_1 */ +void OSCCTRL_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* OSCCTRL_DFLLLOCKC, OSCCTRL_DFLLLOCKF, OSCCTRL_DFLLOOB, OSCCTRL_DFLLRCS, OSCCTRL_DFLLRDY */ +void OSCCTRL_3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* OSCCTRL_DPLLLCKF_0, OSCCTRL_DPLLLCKR_0, OSCCTRL_DPLLLDRTO_0, OSCCTRL_DPLLLTO_0 */ +void OSCCTRL_4_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* OSCCTRL_DPLLLCKF_1, OSCCTRL_DPLLLCKR_1, OSCCTRL_DPLLLDRTO_1, OSCCTRL_DPLLLTO_1 */ +void OSC32KCTRL_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SUPC_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SUPC_B12SRDY, SUPC_B33SRDY, SUPC_BOD12RDY, SUPC_BOD33RDY, SUPC_VCORERDY, SUPC_VREGRDY */ +void SUPC_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SUPC_BOD12DET, SUPC_BOD33DET */ +void WDT_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void RTC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EIC_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_0 */ +void EIC_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_1 */ +void EIC_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_2 */ +void EIC_3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_3 */ +void EIC_4_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_4 */ +void EIC_5_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_5 */ +void EIC_6_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_6 */ +void EIC_7_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_7 */ +void EIC_8_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_8 */ +void EIC_9_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_9 */ +void EIC_10_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_10 */ +void EIC_11_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_11 */ +void EIC_12_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_12 */ +void EIC_13_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_13 */ +void EIC_14_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_14 */ +void EIC_15_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_15 */ +void FREQM_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void NVMCTRL_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* NVMCTRL_0, NVMCTRL_1, NVMCTRL_2, NVMCTRL_3, NVMCTRL_4, NVMCTRL_5, NVMCTRL_6, NVMCTRL_7 */ +void NVMCTRL_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* NVMCTRL_10, NVMCTRL_8, NVMCTRL_9 */ +void DMAC_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* DMAC_SUSP_0, DMAC_TCMPL_0, DMAC_TERR_0 */ +void DMAC_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* DMAC_SUSP_1, DMAC_TCMPL_1, DMAC_TERR_1 */ +void DMAC_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* DMAC_SUSP_2, DMAC_TCMPL_2, DMAC_TERR_2 */ +void DMAC_3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* DMAC_SUSP_3, DMAC_TCMPL_3, DMAC_TERR_3 */ +void DMAC_4_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* DMAC_SUSP_10, DMAC_SUSP_11, DMAC_SUSP_12, DMAC_SUSP_13, DMAC_SUSP_14, DMAC_SUSP_15, DMAC_SUSP_16, DMAC_SUSP_17, DMAC_SUSP_18, DMAC_SUSP_19, DMAC_SUSP_20, DMAC_SUSP_21, DMAC_SUSP_22, DMAC_SUSP_23, DMAC_SUSP_24, DMAC_SUSP_25, DMAC_SUSP_26, DMAC_SUSP_27, DMAC_SUSP_28, DMAC_SUSP_29, DMAC_SUSP_30, DMAC_SUSP_31, DMAC_SUSP_4, DMAC_SUSP_5, DMAC_SUSP_6, DMAC_SUSP_7, DMAC_SUSP_8, DMAC_SUSP_9, DMAC_TCMPL_10, DMAC_TCMPL_11, DMAC_TCMPL_12, DMAC_TCMPL_13, DMAC_TCMPL_14, DMAC_TCMPL_15, DMAC_TCMPL_16, DMAC_TCMPL_17, DMAC_TCMPL_18, DMAC_TCMPL_19, DMAC_TCMPL_20, DMAC_TCMPL_21, DMAC_TCMPL_22, DMAC_TCMPL_23, DMAC_TCMPL_24, DMAC_TCMPL_25, DMAC_TCMPL_26, DMAC_TCMPL_27, DMAC_TCMPL_28, DMAC_TCMPL_29, DMAC_TCMPL_30, DMAC_TCMPL_31, DMAC_TCMPL_4, DMAC_TCMPL_5, DMAC_TCMPL_6, DMAC_TCMPL_7, DMAC_TCMPL_8, DMAC_TCMPL_9, DMAC_TERR_10, DMAC_TERR_11, DMAC_TERR_12, DMAC_TERR_13, DMAC_TERR_14, DMAC_TERR_15, DMAC_TERR_16, DMAC_TERR_17, DMAC_TERR_18, DMAC_TERR_19, DMAC_TERR_20, DMAC_TERR_21, DMAC_TERR_22, DMAC_TERR_23, DMAC_TERR_24, DMAC_TERR_25, DMAC_TERR_26, DMAC_TERR_27, DMAC_TERR_28, DMAC_TERR_29, DMAC_TERR_30, DMAC_TERR_31, DMAC_TERR_4, DMAC_TERR_5, DMAC_TERR_6, DMAC_TERR_7, DMAC_TERR_8, DMAC_TERR_9 */ +void EVSYS_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EVSYS_EVD_0, EVSYS_OVR_0 */ +void EVSYS_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EVSYS_EVD_1, EVSYS_OVR_1 */ +void EVSYS_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EVSYS_EVD_2, EVSYS_OVR_2 */ +void EVSYS_3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EVSYS_EVD_3, EVSYS_OVR_3 */ +void EVSYS_4_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* EVSYS_EVD_10, EVSYS_EVD_11, EVSYS_EVD_4, EVSYS_EVD_5, EVSYS_EVD_6, EVSYS_EVD_7, EVSYS_EVD_8, EVSYS_EVD_9, EVSYS_OVR_10, EVSYS_OVR_11, EVSYS_OVR_4, EVSYS_OVR_5, EVSYS_OVR_6, EVSYS_OVR_7, EVSYS_OVR_8, EVSYS_OVR_9 */ +void PAC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void RAMECC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SERCOM0_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM0_0 */ +void SERCOM0_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM0_1 */ +void SERCOM0_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM0_2 */ +void SERCOM0_3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM0_3, SERCOM0_4, SERCOM0_5, SERCOM0_6 */ +void SERCOM1_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM1_0 */ +void SERCOM1_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM1_1 */ +void SERCOM1_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM1_2 */ +void SERCOM1_3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM1_3, SERCOM1_4, SERCOM1_5, SERCOM1_6 */ +void SERCOM2_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM2_0 */ +void SERCOM2_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM2_1 */ +void SERCOM2_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM2_2 */ +void SERCOM2_3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM2_3, SERCOM2_4, SERCOM2_5, SERCOM2_6 */ +void SERCOM3_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM3_0 */ +void SERCOM3_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM3_1 */ +void SERCOM3_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM3_2 */ +void SERCOM3_3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM3_3, SERCOM3_4, SERCOM3_5, SERCOM3_6 */ +#ifdef ID_SERCOM4 +void SERCOM4_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM4_0 */ +void SERCOM4_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM4_1 */ +void SERCOM4_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM4_2 */ +void SERCOM4_3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM4_3, SERCOM4_4, SERCOM4_5, SERCOM4_6 */ +#endif +#ifdef ID_SERCOM5 +void SERCOM5_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM5_0 */ +void SERCOM5_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM5_1 */ +void SERCOM5_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM5_2 */ +void SERCOM5_3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM5_3, SERCOM5_4, SERCOM5_5, SERCOM5_6 */ +#endif +#ifdef ID_SERCOM6 +void SERCOM6_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM6_0 */ +void SERCOM6_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM6_1 */ +void SERCOM6_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM6_2 */ +void SERCOM6_3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM6_3, SERCOM6_4, SERCOM6_5, SERCOM6_6 */ +#endif +#ifdef ID_SERCOM7 +void SERCOM7_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM7_0 */ +void SERCOM7_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM7_1 */ +void SERCOM7_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM7_2 */ +void SERCOM7_3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* SERCOM7_3, SERCOM7_4, SERCOM7_5, SERCOM7_6 */ +#endif +#ifdef ID_CAN0 +void CAN0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +#endif +#ifdef ID_CAN1 +void CAN1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +#endif +#ifdef ID_USB +void USB_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* USB_EORSM_DNRSM, USB_EORST_RST, USB_LPMSUSP_DDISC, USB_LPM_DCONN, USB_MSOF, USB_RAMACER, USB_RXSTP_TXSTP_0, USB_RXSTP_TXSTP_1, USB_RXSTP_TXSTP_2, USB_RXSTP_TXSTP_3, USB_RXSTP_TXSTP_4, USB_RXSTP_TXSTP_5, USB_RXSTP_TXSTP_6, USB_RXSTP_TXSTP_7, USB_STALL0_STALL_0, USB_STALL0_STALL_1, USB_STALL0_STALL_2, USB_STALL0_STALL_3, USB_STALL0_STALL_4, USB_STALL0_STALL_5, USB_STALL0_STALL_6, USB_STALL0_STALL_7, USB_STALL1_0, USB_STALL1_1, USB_STALL1_2, USB_STALL1_3, USB_STALL1_4, USB_STALL1_5, USB_STALL1_6, USB_STALL1_7, USB_SUSPEND, USB_TRFAIL0_TRFAIL_0, USB_TRFAIL0_TRFAIL_1, USB_TRFAIL0_TRFAIL_2, USB_TRFAIL0_TRFAIL_3, USB_TRFAIL0_TRFAIL_4, USB_TRFAIL0_TRFAIL_5, USB_TRFAIL0_TRFAIL_6, USB_TRFAIL0_TRFAIL_7, USB_TRFAIL1_PERR_0, USB_TRFAIL1_PERR_1, USB_TRFAIL1_PERR_2, USB_TRFAIL1_PERR_3, USB_TRFAIL1_PERR_4, USB_TRFAIL1_PERR_5, USB_TRFAIL1_PERR_6, USB_TRFAIL1_PERR_7, USB_UPRSM, USB_WAKEUP */ +void USB_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* USB_SOF_HSOF */ +void USB_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* USB_TRCPT0_0, USB_TRCPT0_1, USB_TRCPT0_2, USB_TRCPT0_3, USB_TRCPT0_4, USB_TRCPT0_5, USB_TRCPT0_6, USB_TRCPT0_7 */ +void USB_3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* USB_TRCPT1_0, USB_TRCPT1_1, USB_TRCPT1_2, USB_TRCPT1_3, USB_TRCPT1_4, USB_TRCPT1_5, USB_TRCPT1_6, USB_TRCPT1_7 */ +#endif +#ifdef ID_GMAC +void GMAC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +#endif +void TCC0_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC0_CNT_A, TCC0_DFS_A, TCC0_ERR_A, TCC0_FAULT0_A, TCC0_FAULT1_A, TCC0_FAULTA_A, TCC0_FAULTB_A, TCC0_OVF, TCC0_TRG, TCC0_UFS_A */ +void TCC0_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC0_MC_0 */ +void TCC0_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC0_MC_1 */ +void TCC0_3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC0_MC_2 */ +void TCC0_4_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC0_MC_3 */ +void TCC0_5_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC0_MC_4 */ +void TCC0_6_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC0_MC_5 */ +void TCC1_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC1_CNT_A, TCC1_DFS_A, TCC1_ERR_A, TCC1_FAULT0_A, TCC1_FAULT1_A, TCC1_FAULTA_A, TCC1_FAULTB_A, TCC1_OVF, TCC1_TRG, TCC1_UFS_A */ +void TCC1_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC1_MC_0 */ +void TCC1_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC1_MC_1 */ +void TCC1_3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC1_MC_2 */ +void TCC1_4_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC1_MC_3 */ +void TCC2_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC2_CNT_A, TCC2_DFS_A, TCC2_ERR_A, TCC2_FAULT0_A, TCC2_FAULT1_A, TCC2_FAULTA_A, TCC2_FAULTB_A, TCC2_OVF, TCC2_TRG, TCC2_UFS_A */ +void TCC2_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC2_MC_0 */ +void TCC2_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC2_MC_1 */ +void TCC2_3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC2_MC_2 */ +#ifdef ID_TCC3 +void TCC3_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC3_CNT_A, TCC3_DFS_A, TCC3_ERR_A, TCC3_FAULT0_A, TCC3_FAULT1_A, TCC3_FAULTA_A, TCC3_FAULTB_A, TCC3_OVF, TCC3_TRG, TCC3_UFS_A */ +void TCC3_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC3_MC_0 */ +void TCC3_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC3_MC_1 */ +#endif +#ifdef ID_TCC4 +void TCC4_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC4_CNT_A, TCC4_DFS_A, TCC4_ERR_A, TCC4_FAULT0_A, TCC4_FAULT1_A, TCC4_FAULTA_A, TCC4_FAULTB_A, TCC4_OVF, TCC4_TRG, TCC4_UFS_A */ +void TCC4_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC4_MC_0 */ +void TCC4_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* TCC4_MC_1 */ +#endif +void TC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +#ifdef ID_TC4 +void TC4_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +#endif +#ifdef ID_TC5 +void TC5_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +#endif +#ifdef ID_TC6 +void TC6_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +#endif +#ifdef ID_TC7 +void TC7_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +#endif +void PDEC_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* PDEC_DIR_A, PDEC_ERR_A, PDEC_OVF, PDEC_VLC_A */ +void PDEC_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* PDEC_MC_0 */ +void PDEC_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* PDEC_MC_1 */ +void ADC0_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* ADC0_OVERRUN, ADC0_WINMON */ +void ADC0_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* ADC0_RESRDY */ +void ADC1_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* ADC1_OVERRUN, ADC1_WINMON */ +void ADC1_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* ADC1_RESRDY */ +void AC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void DAC_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* DAC_OVERRUN_A_0, DAC_OVERRUN_A_1, DAC_UNDERRUN_A_0, DAC_UNDERRUN_A_1 */ +void DAC_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* DAC_EMPTY_0 */ +void DAC_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* DAC_EMPTY_1 */ +void DAC_3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* DAC_RESRDY_0 */ +void DAC_4_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* DAC_RESRDY_1 */ +#ifdef ID_I2S +void I2S_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +#endif +void PCC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void AES_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TRNG_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +#ifdef ID_ICM +void ICM_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +#endif +#ifdef ID_PUKCC +void PUKCC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +#endif +void QSPI_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +#ifdef ID_SDHC0 +void SDHC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +#endif +#ifdef ID_SDHC1 +void SDHC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +#endif + +/* Exception Table */ +__attribute__ ((section(".vectors"))) +const DeviceVectors exception_table = { + + /* Configure Initial Stack Pointer, using linker-generated symbols */ + .pvStack = (void*) (&_estack), + + .pfnReset_Handler = (void*) Reset_Handler, + .pfnNonMaskableInt_Handler = (void*) NonMaskableInt_Handler, + .pfnHardFault_Handler = (void*) HardFault_Handler, + .pfnMemManagement_Handler = (void*) MemManagement_Handler, + .pfnBusFault_Handler = (void*) BusFault_Handler, + .pfnUsageFault_Handler = (void*) UsageFault_Handler, + .pvReservedM9 = (void*) (0UL), /* Reserved */ + .pvReservedM8 = (void*) (0UL), /* Reserved */ + .pvReservedM7 = (void*) (0UL), /* Reserved */ + .pvReservedM6 = (void*) (0UL), /* Reserved */ + .pfnSVCall_Handler = (void*) SVCall_Handler, + .pfnDebugMonitor_Handler = (void*) DebugMonitor_Handler, + .pvReservedM3 = (void*) (0UL), /* Reserved */ + .pfnPendSV_Handler = (void*) PendSV_Handler, + .pfnSysTick_Handler = (void*) SysTick_Handler, + + /* Configurable interrupts */ + .pfnPM_Handler = (void*) PM_Handler, /* 0 Power Manager */ + .pfnMCLK_Handler = (void*) MCLK_Handler, /* 1 Main Clock */ + .pfnOSCCTRL_0_Handler = (void*) OSCCTRL_0_Handler, /* 2 OSCCTRL_XOSCFAIL_0, OSCCTRL_XOSCRDY_0 */ + .pfnOSCCTRL_1_Handler = (void*) OSCCTRL_1_Handler, /* 3 OSCCTRL_XOSCFAIL_1, OSCCTRL_XOSCRDY_1 */ + .pfnOSCCTRL_2_Handler = (void*) OSCCTRL_2_Handler, /* 4 OSCCTRL_DFLLLOCKC, OSCCTRL_DFLLLOCKF, OSCCTRL_DFLLOOB, OSCCTRL_DFLLRCS, OSCCTRL_DFLLRDY */ + .pfnOSCCTRL_3_Handler = (void*) OSCCTRL_3_Handler, /* 5 OSCCTRL_DPLLLCKF_0, OSCCTRL_DPLLLCKR_0, OSCCTRL_DPLLLDRTO_0, OSCCTRL_DPLLLTO_0 */ + .pfnOSCCTRL_4_Handler = (void*) OSCCTRL_4_Handler, /* 6 OSCCTRL_DPLLLCKF_1, OSCCTRL_DPLLLCKR_1, OSCCTRL_DPLLLDRTO_1, OSCCTRL_DPLLLTO_1 */ + .pfnOSC32KCTRL_Handler = (void*) OSC32KCTRL_Handler, /* 7 32kHz Oscillators Control */ + .pfnSUPC_0_Handler = (void*) SUPC_0_Handler, /* 8 SUPC_B12SRDY, SUPC_B33SRDY, SUPC_BOD12RDY, SUPC_BOD33RDY, SUPC_VCORERDY, SUPC_VREGRDY */ + .pfnSUPC_1_Handler = (void*) SUPC_1_Handler, /* 9 SUPC_BOD12DET, SUPC_BOD33DET */ + .pfnWDT_Handler = (void*) WDT_Handler, /* 10 Watchdog Timer */ + .pfnRTC_Handler = (void*) RTC_Handler, /* 11 Real-Time Counter */ + .pfnEIC_0_Handler = (void*) EIC_0_Handler, /* 12 EIC_EXTINT_0 */ + .pfnEIC_1_Handler = (void*) EIC_1_Handler, /* 13 EIC_EXTINT_1 */ + .pfnEIC_2_Handler = (void*) EIC_2_Handler, /* 14 EIC_EXTINT_2 */ + .pfnEIC_3_Handler = (void*) EIC_3_Handler, /* 15 EIC_EXTINT_3 */ + .pfnEIC_4_Handler = (void*) EIC_4_Handler, /* 16 EIC_EXTINT_4 */ + .pfnEIC_5_Handler = (void*) EIC_5_Handler, /* 17 EIC_EXTINT_5 */ + .pfnEIC_6_Handler = (void*) EIC_6_Handler, /* 18 EIC_EXTINT_6 */ + .pfnEIC_7_Handler = (void*) EIC_7_Handler, /* 19 EIC_EXTINT_7 */ + .pfnEIC_8_Handler = (void*) EIC_8_Handler, /* 20 EIC_EXTINT_8 */ + .pfnEIC_9_Handler = (void*) EIC_9_Handler, /* 21 EIC_EXTINT_9 */ + .pfnEIC_10_Handler = (void*) EIC_10_Handler, /* 22 EIC_EXTINT_10 */ + .pfnEIC_11_Handler = (void*) EIC_11_Handler, /* 23 EIC_EXTINT_11 */ + .pfnEIC_12_Handler = (void*) EIC_12_Handler, /* 24 EIC_EXTINT_12 */ + .pfnEIC_13_Handler = (void*) EIC_13_Handler, /* 25 EIC_EXTINT_13 */ + .pfnEIC_14_Handler = (void*) EIC_14_Handler, /* 26 EIC_EXTINT_14 */ + .pfnEIC_15_Handler = (void*) EIC_15_Handler, /* 27 EIC_EXTINT_15 */ + .pfnFREQM_Handler = (void*) FREQM_Handler, /* 28 Frequency Meter */ + .pfnNVMCTRL_0_Handler = (void*) NVMCTRL_0_Handler, /* 29 NVMCTRL_0, NVMCTRL_1, NVMCTRL_2, NVMCTRL_3, NVMCTRL_4, NVMCTRL_5, NVMCTRL_6, NVMCTRL_7 */ + .pfnNVMCTRL_1_Handler = (void*) NVMCTRL_1_Handler, /* 30 NVMCTRL_10, NVMCTRL_8, NVMCTRL_9 */ + .pfnDMAC_0_Handler = (void*) DMAC_0_Handler, /* 31 DMAC_SUSP_0, DMAC_TCMPL_0, DMAC_TERR_0 */ + .pfnDMAC_1_Handler = (void*) DMAC_1_Handler, /* 32 DMAC_SUSP_1, DMAC_TCMPL_1, DMAC_TERR_1 */ + .pfnDMAC_2_Handler = (void*) DMAC_2_Handler, /* 33 DMAC_SUSP_2, DMAC_TCMPL_2, DMAC_TERR_2 */ + .pfnDMAC_3_Handler = (void*) DMAC_3_Handler, /* 34 DMAC_SUSP_3, DMAC_TCMPL_3, DMAC_TERR_3 */ + .pfnDMAC_4_Handler = (void*) DMAC_4_Handler, /* 35 DMAC_SUSP_10, DMAC_SUSP_11, DMAC_SUSP_12, DMAC_SUSP_13, DMAC_SUSP_14, DMAC_SUSP_15, DMAC_SUSP_16, DMAC_SUSP_17, DMAC_SUSP_18, DMAC_SUSP_19, DMAC_SUSP_20, DMAC_SUSP_21, DMAC_SUSP_22, DMAC_SUSP_23, DMAC_SUSP_24, DMAC_SUSP_25, DMAC_SUSP_26, DMAC_SUSP_27, DMAC_SUSP_28, DMAC_SUSP_29, DMAC_SUSP_30, DMAC_SUSP_31, DMAC_SUSP_4, DMAC_SUSP_5, DMAC_SUSP_6, DMAC_SUSP_7, DMAC_SUSP_8, DMAC_SUSP_9, DMAC_TCMPL_10, DMAC_TCMPL_11, DMAC_TCMPL_12, DMAC_TCMPL_13, DMAC_TCMPL_14, DMAC_TCMPL_15, DMAC_TCMPL_16, DMAC_TCMPL_17, DMAC_TCMPL_18, DMAC_TCMPL_19, DMAC_TCMPL_20, DMAC_TCMPL_21, DMAC_TCMPL_22, DMAC_TCMPL_23, DMAC_TCMPL_24, DMAC_TCMPL_25, DMAC_TCMPL_26, DMAC_TCMPL_27, DMAC_TCMPL_28, DMAC_TCMPL_29, DMAC_TCMPL_30, DMAC_TCMPL_31, DMAC_TCMPL_4, DMAC_TCMPL_5, DMAC_TCMPL_6, DMAC_TCMPL_7, DMAC_TCMPL_8, DMAC_TCMPL_9, DMAC_TERR_10, DMAC_TERR_11, DMAC_TERR_12, DMAC_TERR_13, DMAC_TERR_14, DMAC_TERR_15, DMAC_TERR_16, DMAC_TERR_17, DMAC_TERR_18, DMAC_TERR_19, DMAC_TERR_20, DMAC_TERR_21, DMAC_TERR_22, DMAC_TERR_23, DMAC_TERR_24, DMAC_TERR_25, DMAC_TERR_26, DMAC_TERR_27, DMAC_TERR_28, DMAC_TERR_29, DMAC_TERR_30, DMAC_TERR_31, DMAC_TERR_4, DMAC_TERR_5, DMAC_TERR_6, DMAC_TERR_7, DMAC_TERR_8, DMAC_TERR_9 */ + .pfnEVSYS_0_Handler = (void*) EVSYS_0_Handler, /* 36 EVSYS_EVD_0, EVSYS_OVR_0 */ + .pfnEVSYS_1_Handler = (void*) EVSYS_1_Handler, /* 37 EVSYS_EVD_1, EVSYS_OVR_1 */ + .pfnEVSYS_2_Handler = (void*) EVSYS_2_Handler, /* 38 EVSYS_EVD_2, EVSYS_OVR_2 */ + .pfnEVSYS_3_Handler = (void*) EVSYS_3_Handler, /* 39 EVSYS_EVD_3, EVSYS_OVR_3 */ + .pfnEVSYS_4_Handler = (void*) EVSYS_4_Handler, /* 40 EVSYS_EVD_10, EVSYS_EVD_11, EVSYS_EVD_4, EVSYS_EVD_5, EVSYS_EVD_6, EVSYS_EVD_7, EVSYS_EVD_8, EVSYS_EVD_9, EVSYS_OVR_10, EVSYS_OVR_11, EVSYS_OVR_4, EVSYS_OVR_5, EVSYS_OVR_6, EVSYS_OVR_7, EVSYS_OVR_8, EVSYS_OVR_9 */ + .pfnPAC_Handler = (void*) PAC_Handler, /* 41 Peripheral Access Controller */ + .pvReserved42 = (void*) (0UL), /* 42 Reserved */ + .pvReserved43 = (void*) (0UL), /* 43 Reserved */ + .pvReserved44 = (void*) (0UL), /* 44 Reserved */ + .pfnRAMECC_Handler = (void*) RAMECC_Handler, /* 45 RAM ECC */ + .pfnSERCOM0_0_Handler = (void*) SERCOM0_0_Handler, /* 46 SERCOM0_0 */ + .pfnSERCOM0_1_Handler = (void*) SERCOM0_1_Handler, /* 47 SERCOM0_1 */ + .pfnSERCOM0_2_Handler = (void*) SERCOM0_2_Handler, /* 48 SERCOM0_2 */ + .pfnSERCOM0_3_Handler = (void*) SERCOM0_3_Handler, /* 49 SERCOM0_3, SERCOM0_4, SERCOM0_5, SERCOM0_6 */ + .pfnSERCOM1_0_Handler = (void*) SERCOM1_0_Handler, /* 50 SERCOM1_0 */ + .pfnSERCOM1_1_Handler = (void*) SERCOM1_1_Handler, /* 51 SERCOM1_1 */ + .pfnSERCOM1_2_Handler = (void*) SERCOM1_2_Handler, /* 52 SERCOM1_2 */ + .pfnSERCOM1_3_Handler = (void*) SERCOM1_3_Handler, /* 53 SERCOM1_3, SERCOM1_4, SERCOM1_5, SERCOM1_6 */ + .pfnSERCOM2_0_Handler = (void*) SERCOM2_0_Handler, /* 54 SERCOM2_0 */ + .pfnSERCOM2_1_Handler = (void*) SERCOM2_1_Handler, /* 55 SERCOM2_1 */ + .pfnSERCOM2_2_Handler = (void*) SERCOM2_2_Handler, /* 56 SERCOM2_2 */ + .pfnSERCOM2_3_Handler = (void*) SERCOM2_3_Handler, /* 57 SERCOM2_3, SERCOM2_4, SERCOM2_5, SERCOM2_6 */ + .pfnSERCOM3_0_Handler = (void*) SERCOM3_0_Handler, /* 58 SERCOM3_0 */ + .pfnSERCOM3_1_Handler = (void*) SERCOM3_1_Handler, /* 59 SERCOM3_1 */ + .pfnSERCOM3_2_Handler = (void*) SERCOM3_2_Handler, /* 60 SERCOM3_2 */ + .pfnSERCOM3_3_Handler = (void*) SERCOM3_3_Handler, /* 61 SERCOM3_3, SERCOM3_4, SERCOM3_5, SERCOM3_6 */ +#ifdef ID_SERCOM4 + .pfnSERCOM4_0_Handler = (void*) SERCOM4_0_Handler, /* 62 SERCOM4_0 */ + .pfnSERCOM4_1_Handler = (void*) SERCOM4_1_Handler, /* 63 SERCOM4_1 */ + .pfnSERCOM4_2_Handler = (void*) SERCOM4_2_Handler, /* 64 SERCOM4_2 */ + .pfnSERCOM4_3_Handler = (void*) SERCOM4_3_Handler, /* 65 SERCOM4_3, SERCOM4_4, SERCOM4_5, SERCOM4_6 */ +#else + .pvReserved62 = (void*) (0UL), /* 62 Reserved */ + .pvReserved63 = (void*) (0UL), /* 63 Reserved */ + .pvReserved64 = (void*) (0UL), /* 64 Reserved */ + .pvReserved65 = (void*) (0UL), /* 65 Reserved */ +#endif +#ifdef ID_SERCOM5 + .pfnSERCOM5_0_Handler = (void*) SERCOM5_0_Handler, /* 66 SERCOM5_0 */ + .pfnSERCOM5_1_Handler = (void*) SERCOM5_1_Handler, /* 67 SERCOM5_1 */ + .pfnSERCOM5_2_Handler = (void*) SERCOM5_2_Handler, /* 68 SERCOM5_2 */ + .pfnSERCOM5_3_Handler = (void*) SERCOM5_3_Handler, /* 69 SERCOM5_3, SERCOM5_4, SERCOM5_5, SERCOM5_6 */ +#else + .pvReserved66 = (void*) (0UL), /* 66 Reserved */ + .pvReserved67 = (void*) (0UL), /* 67 Reserved */ + .pvReserved68 = (void*) (0UL), /* 68 Reserved */ + .pvReserved69 = (void*) (0UL), /* 69 Reserved */ +#endif +#ifdef ID_SERCOM6 + .pfnSERCOM6_0_Handler = (void*) SERCOM6_0_Handler, /* 70 SERCOM6_0 */ + .pfnSERCOM6_1_Handler = (void*) SERCOM6_1_Handler, /* 71 SERCOM6_1 */ + .pfnSERCOM6_2_Handler = (void*) SERCOM6_2_Handler, /* 72 SERCOM6_2 */ + .pfnSERCOM6_3_Handler = (void*) SERCOM6_3_Handler, /* 73 SERCOM6_3, SERCOM6_4, SERCOM6_5, SERCOM6_6 */ +#else + .pvReserved70 = (void*) (0UL), /* 70 Reserved */ + .pvReserved71 = (void*) (0UL), /* 71 Reserved */ + .pvReserved72 = (void*) (0UL), /* 72 Reserved */ + .pvReserved73 = (void*) (0UL), /* 73 Reserved */ +#endif +#ifdef ID_SERCOM7 + .pfnSERCOM7_0_Handler = (void*) SERCOM7_0_Handler, /* 74 SERCOM7_0 */ + .pfnSERCOM7_1_Handler = (void*) SERCOM7_1_Handler, /* 75 SERCOM7_1 */ + .pfnSERCOM7_2_Handler = (void*) SERCOM7_2_Handler, /* 76 SERCOM7_2 */ + .pfnSERCOM7_3_Handler = (void*) SERCOM7_3_Handler, /* 77 SERCOM7_3, SERCOM7_4, SERCOM7_5, SERCOM7_6 */ +#else + .pvReserved74 = (void*) (0UL), /* 74 Reserved */ + .pvReserved75 = (void*) (0UL), /* 75 Reserved */ + .pvReserved76 = (void*) (0UL), /* 76 Reserved */ + .pvReserved77 = (void*) (0UL), /* 77 Reserved */ +#endif +#ifdef ID_CAN0 + .pfnCAN0_Handler = (void*) CAN0_Handler, /* 78 Control Area Network 0 */ +#else + .pvReserved78 = (void*) (0UL), /* 78 Reserved */ +#endif +#ifdef ID_CAN1 + .pfnCAN1_Handler = (void*) CAN1_Handler, /* 79 Control Area Network 1 */ +#else + .pvReserved79 = (void*) (0UL), /* 79 Reserved */ +#endif +#ifdef ID_USB + .pfnUSB_0_Handler = (void*) USB_0_Handler, /* 80 USB_EORSM_DNRSM, USB_EORST_RST, USB_LPMSUSP_DDISC, USB_LPM_DCONN, USB_MSOF, USB_RAMACER, USB_RXSTP_TXSTP_0, USB_RXSTP_TXSTP_1, USB_RXSTP_TXSTP_2, USB_RXSTP_TXSTP_3, USB_RXSTP_TXSTP_4, USB_RXSTP_TXSTP_5, USB_RXSTP_TXSTP_6, USB_RXSTP_TXSTP_7, USB_STALL0_STALL_0, USB_STALL0_STALL_1, USB_STALL0_STALL_2, USB_STALL0_STALL_3, USB_STALL0_STALL_4, USB_STALL0_STALL_5, USB_STALL0_STALL_6, USB_STALL0_STALL_7, USB_STALL1_0, USB_STALL1_1, USB_STALL1_2, USB_STALL1_3, USB_STALL1_4, USB_STALL1_5, USB_STALL1_6, USB_STALL1_7, USB_SUSPEND, USB_TRFAIL0_TRFAIL_0, USB_TRFAIL0_TRFAIL_1, USB_TRFAIL0_TRFAIL_2, USB_TRFAIL0_TRFAIL_3, USB_TRFAIL0_TRFAIL_4, USB_TRFAIL0_TRFAIL_5, USB_TRFAIL0_TRFAIL_6, USB_TRFAIL0_TRFAIL_7, USB_TRFAIL1_PERR_0, USB_TRFAIL1_PERR_1, USB_TRFAIL1_PERR_2, USB_TRFAIL1_PERR_3, USB_TRFAIL1_PERR_4, USB_TRFAIL1_PERR_5, USB_TRFAIL1_PERR_6, USB_TRFAIL1_PERR_7, USB_UPRSM, USB_WAKEUP */ + .pfnUSB_1_Handler = (void*) USB_1_Handler, /* 81 USB_SOF_HSOF */ + .pfnUSB_2_Handler = (void*) USB_2_Handler, /* 82 USB_TRCPT0_0, USB_TRCPT0_1, USB_TRCPT0_2, USB_TRCPT0_3, USB_TRCPT0_4, USB_TRCPT0_5, USB_TRCPT0_6, USB_TRCPT0_7 */ + .pfnUSB_3_Handler = (void*) USB_3_Handler, /* 83 USB_TRCPT1_0, USB_TRCPT1_1, USB_TRCPT1_2, USB_TRCPT1_3, USB_TRCPT1_4, USB_TRCPT1_5, USB_TRCPT1_6, USB_TRCPT1_7 */ +#else + .pvReserved80 = (void*) (0UL), /* 80 Reserved */ + .pvReserved81 = (void*) (0UL), /* 81 Reserved */ + .pvReserved82 = (void*) (0UL), /* 82 Reserved */ + .pvReserved83 = (void*) (0UL), /* 83 Reserved */ +#endif +#ifdef ID_GMAC + .pfnGMAC_Handler = (void*) GMAC_Handler, /* 84 Ethernet MAC */ +#else + .pvReserved84 = (void*) (0UL), /* 84 Reserved */ +#endif + .pfnTCC0_0_Handler = (void*) TCC0_0_Handler, /* 85 TCC0_CNT_A, TCC0_DFS_A, TCC0_ERR_A, TCC0_FAULT0_A, TCC0_FAULT1_A, TCC0_FAULTA_A, TCC0_FAULTB_A, TCC0_OVF, TCC0_TRG, TCC0_UFS_A */ + .pfnTCC0_1_Handler = (void*) TCC0_1_Handler, /* 86 TCC0_MC_0 */ + .pfnTCC0_2_Handler = (void*) TCC0_2_Handler, /* 87 TCC0_MC_1 */ + .pfnTCC0_3_Handler = (void*) TCC0_3_Handler, /* 88 TCC0_MC_2 */ + .pfnTCC0_4_Handler = (void*) TCC0_4_Handler, /* 89 TCC0_MC_3 */ + .pfnTCC0_5_Handler = (void*) TCC0_5_Handler, /* 90 TCC0_MC_4 */ + .pfnTCC0_6_Handler = (void*) TCC0_6_Handler, /* 91 TCC0_MC_5 */ + .pfnTCC1_0_Handler = (void*) TCC1_0_Handler, /* 92 TCC1_CNT_A, TCC1_DFS_A, TCC1_ERR_A, TCC1_FAULT0_A, TCC1_FAULT1_A, TCC1_FAULTA_A, TCC1_FAULTB_A, TCC1_OVF, TCC1_TRG, TCC1_UFS_A */ + .pfnTCC1_1_Handler = (void*) TCC1_1_Handler, /* 93 TCC1_MC_0 */ + .pfnTCC1_2_Handler = (void*) TCC1_2_Handler, /* 94 TCC1_MC_1 */ + .pfnTCC1_3_Handler = (void*) TCC1_3_Handler, /* 95 TCC1_MC_2 */ + .pfnTCC1_4_Handler = (void*) TCC1_4_Handler, /* 96 TCC1_MC_3 */ + .pfnTCC2_0_Handler = (void*) TCC2_0_Handler, /* 97 TCC2_CNT_A, TCC2_DFS_A, TCC2_ERR_A, TCC2_FAULT0_A, TCC2_FAULT1_A, TCC2_FAULTA_A, TCC2_FAULTB_A, TCC2_OVF, TCC2_TRG, TCC2_UFS_A */ + .pfnTCC2_1_Handler = (void*) TCC2_1_Handler, /* 98 TCC2_MC_0 */ + .pfnTCC2_2_Handler = (void*) TCC2_2_Handler, /* 99 TCC2_MC_1 */ + .pfnTCC2_3_Handler = (void*) TCC2_3_Handler, /* 100 TCC2_MC_2 */ +#ifdef ID_TCC3 + .pfnTCC3_0_Handler = (void*) TCC3_0_Handler, /* 101 TCC3_CNT_A, TCC3_DFS_A, TCC3_ERR_A, TCC3_FAULT0_A, TCC3_FAULT1_A, TCC3_FAULTA_A, TCC3_FAULTB_A, TCC3_OVF, TCC3_TRG, TCC3_UFS_A */ + .pfnTCC3_1_Handler = (void*) TCC3_1_Handler, /* 102 TCC3_MC_0 */ + .pfnTCC3_2_Handler = (void*) TCC3_2_Handler, /* 103 TCC3_MC_1 */ +#else + .pvReserved101 = (void*) (0UL), /* 101 Reserved */ + .pvReserved102 = (void*) (0UL), /* 102 Reserved */ + .pvReserved103 = (void*) (0UL), /* 103 Reserved */ +#endif +#ifdef ID_TCC4 + .pfnTCC4_0_Handler = (void*) TCC4_0_Handler, /* 104 TCC4_CNT_A, TCC4_DFS_A, TCC4_ERR_A, TCC4_FAULT0_A, TCC4_FAULT1_A, TCC4_FAULTA_A, TCC4_FAULTB_A, TCC4_OVF, TCC4_TRG, TCC4_UFS_A */ + .pfnTCC4_1_Handler = (void*) TCC4_1_Handler, /* 105 TCC4_MC_0 */ + .pfnTCC4_2_Handler = (void*) TCC4_2_Handler, /* 106 TCC4_MC_1 */ +#else + .pvReserved104 = (void*) (0UL), /* 104 Reserved */ + .pvReserved105 = (void*) (0UL), /* 105 Reserved */ + .pvReserved106 = (void*) (0UL), /* 106 Reserved */ +#endif + .pfnTC0_Handler = (void*) TC0_Handler, /* 107 Basic Timer Counter 0 */ + .pfnTC1_Handler = (void*) TC1_Handler, /* 108 Basic Timer Counter 1 */ + .pfnTC2_Handler = (void*) TC2_Handler, /* 109 Basic Timer Counter 2 */ + .pfnTC3_Handler = (void*) TC3_Handler, /* 110 Basic Timer Counter 3 */ +#ifdef ID_TC4 + .pfnTC4_Handler = (void*) TC4_Handler, /* 111 Basic Timer Counter 4 */ +#else + .pvReserved111 = (void*) (0UL), /* 111 Reserved */ +#endif +#ifdef ID_TC5 + .pfnTC5_Handler = (void*) TC5_Handler, /* 112 Basic Timer Counter 5 */ +#else + .pvReserved112 = (void*) (0UL), /* 112 Reserved */ +#endif +#ifdef ID_TC6 + .pfnTC6_Handler = (void*) TC6_Handler, /* 113 Basic Timer Counter 6 */ +#else + .pvReserved113 = (void*) (0UL), /* 113 Reserved */ +#endif +#ifdef ID_TC7 + .pfnTC7_Handler = (void*) TC7_Handler, /* 114 Basic Timer Counter 7 */ +#else + .pvReserved114 = (void*) (0UL), /* 114 Reserved */ +#endif + .pfnPDEC_0_Handler = (void*) PDEC_0_Handler, /* 115 PDEC_DIR_A, PDEC_ERR_A, PDEC_OVF, PDEC_VLC_A */ + .pfnPDEC_1_Handler = (void*) PDEC_1_Handler, /* 116 PDEC_MC_0 */ + .pfnPDEC_2_Handler = (void*) PDEC_2_Handler, /* 117 PDEC_MC_1 */ + .pfnADC0_0_Handler = (void*) ADC0_0_Handler, /* 118 ADC0_OVERRUN, ADC0_WINMON */ + .pfnADC0_1_Handler = (void*) ADC0_1_Handler, /* 119 ADC0_RESRDY */ + .pfnADC1_0_Handler = (void*) ADC1_0_Handler, /* 120 ADC1_OVERRUN, ADC1_WINMON */ + .pfnADC1_1_Handler = (void*) ADC1_1_Handler, /* 121 ADC1_RESRDY */ + .pfnAC_Handler = (void*) AC_Handler, /* 122 Analog Comparators */ + .pfnDAC_0_Handler = (void*) DAC_0_Handler, /* 123 DAC_OVERRUN_A_0, DAC_OVERRUN_A_1, DAC_UNDERRUN_A_0, DAC_UNDERRUN_A_1 */ + .pfnDAC_1_Handler = (void*) DAC_1_Handler, /* 124 DAC_EMPTY_0 */ + .pfnDAC_2_Handler = (void*) DAC_2_Handler, /* 125 DAC_EMPTY_1 */ + .pfnDAC_3_Handler = (void*) DAC_3_Handler, /* 126 DAC_RESRDY_0 */ + .pfnDAC_4_Handler = (void*) DAC_4_Handler, /* 127 DAC_RESRDY_1 */ +#ifdef ID_I2S + .pfnI2S_Handler = (void*) I2S_Handler, /* 128 Inter-IC Sound Interface */ +#else + .pvReserved128 = (void*) (0UL), /* 128 Reserved */ +#endif + .pfnPCC_Handler = (void*) PCC_Handler, /* 129 Parallel Capture Controller */ + .pfnAES_Handler = (void*) AES_Handler, /* 130 Advanced Encryption Standard */ + .pfnTRNG_Handler = (void*) TRNG_Handler, /* 131 True Random Generator */ +#ifdef ID_ICM + .pfnICM_Handler = (void*) ICM_Handler, /* 132 Integrity Check Monitor */ +#else + .pvReserved132 = (void*) (0UL), /* 132 Reserved */ +#endif +#ifdef ID_PUKCC + .pfnPUKCC_Handler = (void*) PUKCC_Handler, /* 133 PUblic-Key Cryptography Controller */ +#else + .pvReserved133 = (void*) (0UL), /* 133 Reserved */ +#endif + .pfnQSPI_Handler = (void*) QSPI_Handler, /* 134 Quad SPI interface */ +#ifdef ID_SDHC0 + .pfnSDHC0_Handler = (void*) SDHC0_Handler, /* 135 SD/MMC Host Controller 0 */ +#else + .pvReserved135 = (void*) (0UL), /* 135 Reserved */ +#endif +#ifdef ID_SDHC1 + .pfnSDHC1_Handler = (void*) SDHC1_Handler /* 136 SD/MMC Host Controller 1 */ +#else + .pvReserved136 = (void*) (0UL) /* 136 Reserved */ +#endif +}; + +/** + * \brief This is the code that gets called on processor reset. + * To initialize the device, and call the main() routine. + */ +void Reset_Handler(void) +{ + uint32_t *pSrc, *pDest; + + /* Initialize the relocate segment */ + pSrc = &_etext; + pDest = &_srelocate; + + if (pSrc != pDest) { + for (; pDest < &_erelocate;) { + *pDest++ = *pSrc++; + } + } + + /* Clear the zero segment */ + for (pDest = &_szero; pDest < &_ezero;) { + *pDest++ = 0; + } + + /* Set the vector table base address */ + pSrc = (uint32_t *) & _sfixed; + SCB->VTOR = ((uint32_t) pSrc & SCB_VTOR_TBLOFF_Msk); + +#if __FPU_USED + /* Enable FPU */ + SCB->CPACR |= (0xFu << 20); + __DSB(); + __ISB(); +#endif + + /* Initialize the C library */ + __libc_init_array(); + + /* Branch to main function */ + main(); + + /* Infinite loop */ + while (1); +} + +/** + * \brief Default interrupt handler for unused IRQs. + */ +void Dummy_Handler(void) +{ + while (1) { + } +} diff --git a/arch/arm/SAME54/SAME54A/mcu/src/startup_same54n19a.c b/arch/arm/SAME54/SAME54A/mcu/src/startup_same54n19a.c deleted file mode 100644 index 47c8f48a..00000000 --- a/arch/arm/SAME54/SAME54A/mcu/src/startup_same54n19a.c +++ /dev/null @@ -1,409 +0,0 @@ -/** - * \file - * - * \brief GCC startup file for ATSAME54N19A - * - * Copyright (c) 2020 Microchip Technology Inc. - * - * \license_start - * - * \page License - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \license_stop - * - */ - -#include "same54n19a.h" - -/* Initialize segments */ -extern uint32_t _sfixed; -extern uint32_t _efixed; -extern uint32_t _etext; -extern uint32_t _srelocate; -extern uint32_t _erelocate; -extern uint32_t _szero; -extern uint32_t _ezero; -extern uint32_t _sstack; -extern uint32_t _estack; - -/** \cond DOXYGEN_SHOULD_SKIP_THIS */ -int main(void); -/** \endcond */ - -void __libc_init_array(void); - -/* Reset handler */ -void Reset_Handler(void); - -/* Default empty handler */ -void Dummy_Handler(void); - -/* Cortex-M4 core handlers */ -void NonMaskableInt_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void HardFault_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void MemoryManagement_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void BusFault_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void UsageFault_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void SVCall_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void DebugMonitor_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void PendSV_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void SysTick_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); - -/* Peripherals handlers */ -void PM_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void MCLK_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void OSCCTRL_XOSC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void OSCCTRL_XOSC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void OSCCTRL_DFLL_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void OSCCTRL_DPLL0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void OSCCTRL_DPLL1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void OSC32KCTRL_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void SUPC_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void SUPC_BODDET_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void WDT_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void RTC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void EIC_EXTINT_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void EIC_EXTINT_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void EIC_EXTINT_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void EIC_EXTINT_3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void EIC_EXTINT_4_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void EIC_EXTINT_5_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void EIC_EXTINT_6_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void EIC_EXTINT_7_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void EIC_EXTINT_8_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void EIC_EXTINT_9_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void EIC_EXTINT_10_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void EIC_EXTINT_11_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void EIC_EXTINT_12_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void EIC_EXTINT_13_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void EIC_EXTINT_14_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void EIC_EXTINT_15_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void FREQM_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void NVMCTRL_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void NVMCTRL_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void DMAC_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void DMAC_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void DMAC_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void DMAC_3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void DMAC_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void EVSYS_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void EVSYS_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void EVSYS_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void EVSYS_3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void EVSYS_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void PAC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void RAMECC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void SERCOM0_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void SERCOM0_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void SERCOM0_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void SERCOM0_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void SERCOM1_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void SERCOM1_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void SERCOM1_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void SERCOM1_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void SERCOM2_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void SERCOM2_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void SERCOM2_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void SERCOM2_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void SERCOM3_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void SERCOM3_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void SERCOM3_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void SERCOM3_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void SERCOM4_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void SERCOM4_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void SERCOM4_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void SERCOM4_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void SERCOM5_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void SERCOM5_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void SERCOM5_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void SERCOM5_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void SERCOM6_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void SERCOM6_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void SERCOM6_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void SERCOM6_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void SERCOM7_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void SERCOM7_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void SERCOM7_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void SERCOM7_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void CAN0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void CAN1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void USB_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void USB_SOF_HSOF_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void USB_TRCPT0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void USB_TRCPT1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void GMAC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void TCC0_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void TCC0_MC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void TCC0_MC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void TCC0_MC2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void TCC0_MC3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void TCC0_MC4_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void TCC0_MC5_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void TCC1_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void TCC1_MC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void TCC1_MC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void TCC1_MC2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void TCC1_MC3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void TCC2_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void TCC2_MC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void TCC2_MC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void TCC2_MC2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void TCC3_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void TCC3_MC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void TCC3_MC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void TCC4_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void TCC4_MC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void TCC4_MC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void TC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void TC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void TC2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void TC3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void TC4_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void TC5_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void TC6_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void TC7_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void PDEC_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void PDEC_MC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void PDEC_MC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void ADC0_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void ADC0_RESRDY_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void ADC1_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void ADC1_RESRDY_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void AC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void DAC_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void DAC_EMPTY_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void DAC_EMPTY_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void DAC_RESRDY_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void DAC_RESRDY_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void I2S_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void PCC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void AES_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void TRNG_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void ICM_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void PUKCC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void QSPI_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void SDHC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void SDHC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); - -/* Exception Table */ -__attribute__ ((section(".vectors"))) -const DeviceVectors exception_table = { - - /* Configure Initial Stack Pointer, using linker-generated symbols */ - .pvStack = (void*) (&_estack), - - .pfnReset_Handler = (void*) Reset_Handler, - .pfnNonMaskableInt_Handler = (void*) NonMaskableInt_Handler, - .pfnHardFault_Handler = (void*) HardFault_Handler, - .pfnMemoryManagement_Handler = (void*) MemoryManagement_Handler, - .pfnBusFault_Handler = (void*) BusFault_Handler, - .pfnUsageFault_Handler = (void*) UsageFault_Handler, - .pvReservedC9 = (void*) (0UL), /* Reserved */ - .pvReservedC8 = (void*) (0UL), /* Reserved */ - .pvReservedC7 = (void*) (0UL), /* Reserved */ - .pvReservedC6 = (void*) (0UL), /* Reserved */ - .pfnSVCall_Handler = (void*) SVCall_Handler, - .pfnDebugMonitor_Handler = (void*) DebugMonitor_Handler, - .pvReservedC3 = (void*) (0UL), /* Reserved */ - .pfnPendSV_Handler = (void*) PendSV_Handler, - .pfnSysTick_Handler = (void*) SysTick_Handler, - - /* Configurable interrupts */ - .pfnPM_Handler = (void*) PM_Handler, /* 0 Power Manager */ - .pfnMCLK_Handler = (void*) MCLK_Handler, /* 1 Main Clock */ - .pfnOSCCTRL_XOSC0_Handler = (void*) OSCCTRL_XOSC0_Handler, /* 2 Oscillators Control */ - .pfnOSCCTRL_XOSC1_Handler = (void*) OSCCTRL_XOSC1_Handler, /* 3 Oscillators Control */ - .pfnOSCCTRL_DFLL_Handler = (void*) OSCCTRL_DFLL_Handler, /* 4 Oscillators Control */ - .pfnOSCCTRL_DPLL0_Handler = (void*) OSCCTRL_DPLL0_Handler, /* 5 Oscillators Control */ - .pfnOSCCTRL_DPLL1_Handler = (void*) OSCCTRL_DPLL1_Handler, /* 6 Oscillators Control */ - .pfnOSC32KCTRL_Handler = (void*) OSC32KCTRL_Handler, /* 7 32kHz Oscillators Control */ - .pfnSUPC_OTHER_Handler = (void*) SUPC_OTHER_Handler, /* 8 Supply Controller */ - .pfnSUPC_BODDET_Handler = (void*) SUPC_BODDET_Handler, /* 9 Supply Controller */ - .pfnWDT_Handler = (void*) WDT_Handler, /* 10 Watchdog Timer */ - .pfnRTC_Handler = (void*) RTC_Handler, /* 11 Real-Time Counter */ - .pfnEIC_EXTINT_0_Handler = (void*) EIC_EXTINT_0_Handler, /* 12 External Interrupt Controller */ - .pfnEIC_EXTINT_1_Handler = (void*) EIC_EXTINT_1_Handler, /* 13 External Interrupt Controller */ - .pfnEIC_EXTINT_2_Handler = (void*) EIC_EXTINT_2_Handler, /* 14 External Interrupt Controller */ - .pfnEIC_EXTINT_3_Handler = (void*) EIC_EXTINT_3_Handler, /* 15 External Interrupt Controller */ - .pfnEIC_EXTINT_4_Handler = (void*) EIC_EXTINT_4_Handler, /* 16 External Interrupt Controller */ - .pfnEIC_EXTINT_5_Handler = (void*) EIC_EXTINT_5_Handler, /* 17 External Interrupt Controller */ - .pfnEIC_EXTINT_6_Handler = (void*) EIC_EXTINT_6_Handler, /* 18 External Interrupt Controller */ - .pfnEIC_EXTINT_7_Handler = (void*) EIC_EXTINT_7_Handler, /* 19 External Interrupt Controller */ - .pfnEIC_EXTINT_8_Handler = (void*) EIC_EXTINT_8_Handler, /* 20 External Interrupt Controller */ - .pfnEIC_EXTINT_9_Handler = (void*) EIC_EXTINT_9_Handler, /* 21 External Interrupt Controller */ - .pfnEIC_EXTINT_10_Handler = (void*) EIC_EXTINT_10_Handler, /* 22 External Interrupt Controller */ - .pfnEIC_EXTINT_11_Handler = (void*) EIC_EXTINT_11_Handler, /* 23 External Interrupt Controller */ - .pfnEIC_EXTINT_12_Handler = (void*) EIC_EXTINT_12_Handler, /* 24 External Interrupt Controller */ - .pfnEIC_EXTINT_13_Handler = (void*) EIC_EXTINT_13_Handler, /* 25 External Interrupt Controller */ - .pfnEIC_EXTINT_14_Handler = (void*) EIC_EXTINT_14_Handler, /* 26 External Interrupt Controller */ - .pfnEIC_EXTINT_15_Handler = (void*) EIC_EXTINT_15_Handler, /* 27 External Interrupt Controller */ - .pfnFREQM_Handler = (void*) FREQM_Handler, /* 28 Frequency Meter */ - .pfnNVMCTRL_0_Handler = (void*) NVMCTRL_0_Handler, /* 29 Non-Volatile Memory Controller */ - .pfnNVMCTRL_1_Handler = (void*) NVMCTRL_1_Handler, /* 30 Non-Volatile Memory Controller */ - .pfnDMAC_0_Handler = (void*) DMAC_0_Handler, /* 31 Direct Memory Access Controller */ - .pfnDMAC_1_Handler = (void*) DMAC_1_Handler, /* 32 Direct Memory Access Controller */ - .pfnDMAC_2_Handler = (void*) DMAC_2_Handler, /* 33 Direct Memory Access Controller */ - .pfnDMAC_3_Handler = (void*) DMAC_3_Handler, /* 34 Direct Memory Access Controller */ - .pfnDMAC_OTHER_Handler = (void*) DMAC_OTHER_Handler, /* 35 Direct Memory Access Controller */ - .pfnEVSYS_0_Handler = (void*) EVSYS_0_Handler, /* 36 Event System Interface */ - .pfnEVSYS_1_Handler = (void*) EVSYS_1_Handler, /* 37 Event System Interface */ - .pfnEVSYS_2_Handler = (void*) EVSYS_2_Handler, /* 38 Event System Interface */ - .pfnEVSYS_3_Handler = (void*) EVSYS_3_Handler, /* 39 Event System Interface */ - .pfnEVSYS_OTHER_Handler = (void*) EVSYS_OTHER_Handler, /* 40 Event System Interface */ - .pfnPAC_Handler = (void*) PAC_Handler, /* 41 Peripheral Access Controller */ - .pvReserved42 = (void*) (0UL), /* 42 Reserved */ - .pvReserved43 = (void*) (0UL), /* 43 Reserved */ - .pvReserved44 = (void*) (0UL), /* 44 Reserved */ - .pfnRAMECC_Handler = (void*) RAMECC_Handler, /* 45 RAM ECC */ - .pfnSERCOM0_0_Handler = (void*) SERCOM0_0_Handler, /* 46 Serial Communication Interface */ - .pfnSERCOM0_1_Handler = (void*) SERCOM0_1_Handler, /* 47 Serial Communication Interface */ - .pfnSERCOM0_2_Handler = (void*) SERCOM0_2_Handler, /* 48 Serial Communication Interface */ - .pfnSERCOM0_OTHER_Handler = (void*) SERCOM0_OTHER_Handler, /* 49 Serial Communication Interface */ - .pfnSERCOM1_0_Handler = (void*) SERCOM1_0_Handler, /* 50 Serial Communication Interface */ - .pfnSERCOM1_1_Handler = (void*) SERCOM1_1_Handler, /* 51 Serial Communication Interface */ - .pfnSERCOM1_2_Handler = (void*) SERCOM1_2_Handler, /* 52 Serial Communication Interface */ - .pfnSERCOM1_OTHER_Handler = (void*) SERCOM1_OTHER_Handler, /* 53 Serial Communication Interface */ - .pfnSERCOM2_0_Handler = (void*) SERCOM2_0_Handler, /* 54 Serial Communication Interface */ - .pfnSERCOM2_1_Handler = (void*) SERCOM2_1_Handler, /* 55 Serial Communication Interface */ - .pfnSERCOM2_2_Handler = (void*) SERCOM2_2_Handler, /* 56 Serial Communication Interface */ - .pfnSERCOM2_OTHER_Handler = (void*) SERCOM2_OTHER_Handler, /* 57 Serial Communication Interface */ - .pfnSERCOM3_0_Handler = (void*) SERCOM3_0_Handler, /* 58 Serial Communication Interface */ - .pfnSERCOM3_1_Handler = (void*) SERCOM3_1_Handler, /* 59 Serial Communication Interface */ - .pfnSERCOM3_2_Handler = (void*) SERCOM3_2_Handler, /* 60 Serial Communication Interface */ - .pfnSERCOM3_OTHER_Handler = (void*) SERCOM3_OTHER_Handler, /* 61 Serial Communication Interface */ - .pfnSERCOM4_0_Handler = (void*) SERCOM4_0_Handler, /* 62 Serial Communication Interface */ - .pfnSERCOM4_1_Handler = (void*) SERCOM4_1_Handler, /* 63 Serial Communication Interface */ - .pfnSERCOM4_2_Handler = (void*) SERCOM4_2_Handler, /* 64 Serial Communication Interface */ - .pfnSERCOM4_OTHER_Handler = (void*) SERCOM4_OTHER_Handler, /* 65 Serial Communication Interface */ - .pfnSERCOM5_0_Handler = (void*) SERCOM5_0_Handler, /* 66 Serial Communication Interface */ - .pfnSERCOM5_1_Handler = (void*) SERCOM5_1_Handler, /* 67 Serial Communication Interface */ - .pfnSERCOM5_2_Handler = (void*) SERCOM5_2_Handler, /* 68 Serial Communication Interface */ - .pfnSERCOM5_OTHER_Handler = (void*) SERCOM5_OTHER_Handler, /* 69 Serial Communication Interface */ - .pfnSERCOM6_0_Handler = (void*) SERCOM6_0_Handler, /* 70 Serial Communication Interface */ - .pfnSERCOM6_1_Handler = (void*) SERCOM6_1_Handler, /* 71 Serial Communication Interface */ - .pfnSERCOM6_2_Handler = (void*) SERCOM6_2_Handler, /* 72 Serial Communication Interface */ - .pfnSERCOM6_OTHER_Handler = (void*) SERCOM6_OTHER_Handler, /* 73 Serial Communication Interface */ - .pfnSERCOM7_0_Handler = (void*) SERCOM7_0_Handler, /* 74 Serial Communication Interface */ - .pfnSERCOM7_1_Handler = (void*) SERCOM7_1_Handler, /* 75 Serial Communication Interface */ - .pfnSERCOM7_2_Handler = (void*) SERCOM7_2_Handler, /* 76 Serial Communication Interface */ - .pfnSERCOM7_OTHER_Handler = (void*) SERCOM7_OTHER_Handler, /* 77 Serial Communication Interface */ - .pfnCAN0_Handler = (void*) CAN0_Handler, /* 78 Control Area Network */ - .pfnCAN1_Handler = (void*) CAN1_Handler, /* 79 Control Area Network */ - .pfnUSB_OTHER_Handler = (void*) USB_OTHER_Handler, /* 80 Universal Serial Bus */ - .pfnUSB_SOF_HSOF_Handler = (void*) USB_SOF_HSOF_Handler, /* 81 Universal Serial Bus */ - .pfnUSB_TRCPT0_Handler = (void*) USB_TRCPT0_Handler, /* 82 Universal Serial Bus */ - .pfnUSB_TRCPT1_Handler = (void*) USB_TRCPT1_Handler, /* 83 Universal Serial Bus */ - .pfnGMAC_Handler = (void*) GMAC_Handler, /* 84 Ethernet MAC */ - .pfnTCC0_OTHER_Handler = (void*) TCC0_OTHER_Handler, /* 85 Timer Counter Control */ - .pfnTCC0_MC0_Handler = (void*) TCC0_MC0_Handler, /* 86 Timer Counter Control */ - .pfnTCC0_MC1_Handler = (void*) TCC0_MC1_Handler, /* 87 Timer Counter Control */ - .pfnTCC0_MC2_Handler = (void*) TCC0_MC2_Handler, /* 88 Timer Counter Control */ - .pfnTCC0_MC3_Handler = (void*) TCC0_MC3_Handler, /* 89 Timer Counter Control */ - .pfnTCC0_MC4_Handler = (void*) TCC0_MC4_Handler, /* 90 Timer Counter Control */ - .pfnTCC0_MC5_Handler = (void*) TCC0_MC5_Handler, /* 91 Timer Counter Control */ - .pfnTCC1_OTHER_Handler = (void*) TCC1_OTHER_Handler, /* 92 Timer Counter Control */ - .pfnTCC1_MC0_Handler = (void*) TCC1_MC0_Handler, /* 93 Timer Counter Control */ - .pfnTCC1_MC1_Handler = (void*) TCC1_MC1_Handler, /* 94 Timer Counter Control */ - .pfnTCC1_MC2_Handler = (void*) TCC1_MC2_Handler, /* 95 Timer Counter Control */ - .pfnTCC1_MC3_Handler = (void*) TCC1_MC3_Handler, /* 96 Timer Counter Control */ - .pfnTCC2_OTHER_Handler = (void*) TCC2_OTHER_Handler, /* 97 Timer Counter Control */ - .pfnTCC2_MC0_Handler = (void*) TCC2_MC0_Handler, /* 98 Timer Counter Control */ - .pfnTCC2_MC1_Handler = (void*) TCC2_MC1_Handler, /* 99 Timer Counter Control */ - .pfnTCC2_MC2_Handler = (void*) TCC2_MC2_Handler, /* 100 Timer Counter Control */ - .pfnTCC3_OTHER_Handler = (void*) TCC3_OTHER_Handler, /* 101 Timer Counter Control */ - .pfnTCC3_MC0_Handler = (void*) TCC3_MC0_Handler, /* 102 Timer Counter Control */ - .pfnTCC3_MC1_Handler = (void*) TCC3_MC1_Handler, /* 103 Timer Counter Control */ - .pfnTCC4_OTHER_Handler = (void*) TCC4_OTHER_Handler, /* 104 Timer Counter Control */ - .pfnTCC4_MC0_Handler = (void*) TCC4_MC0_Handler, /* 105 Timer Counter Control */ - .pfnTCC4_MC1_Handler = (void*) TCC4_MC1_Handler, /* 106 Timer Counter Control */ - .pfnTC0_Handler = (void*) TC0_Handler, /* 107 Basic Timer Counter */ - .pfnTC1_Handler = (void*) TC1_Handler, /* 108 Basic Timer Counter */ - .pfnTC2_Handler = (void*) TC2_Handler, /* 109 Basic Timer Counter */ - .pfnTC3_Handler = (void*) TC3_Handler, /* 110 Basic Timer Counter */ - .pfnTC4_Handler = (void*) TC4_Handler, /* 111 Basic Timer Counter */ - .pfnTC5_Handler = (void*) TC5_Handler, /* 112 Basic Timer Counter */ - .pfnTC6_Handler = (void*) TC6_Handler, /* 113 Basic Timer Counter */ - .pfnTC7_Handler = (void*) TC7_Handler, /* 114 Basic Timer Counter */ - .pfnPDEC_OTHER_Handler = (void*) PDEC_OTHER_Handler, /* 115 Quadrature Decodeur */ - .pfnPDEC_MC0_Handler = (void*) PDEC_MC0_Handler, /* 116 Quadrature Decodeur */ - .pfnPDEC_MC1_Handler = (void*) PDEC_MC1_Handler, /* 117 Quadrature Decodeur */ - .pfnADC0_OTHER_Handler = (void*) ADC0_OTHER_Handler, /* 118 Analog Digital Converter */ - .pfnADC0_RESRDY_Handler = (void*) ADC0_RESRDY_Handler, /* 119 Analog Digital Converter */ - .pfnADC1_OTHER_Handler = (void*) ADC1_OTHER_Handler, /* 120 Analog Digital Converter */ - .pfnADC1_RESRDY_Handler = (void*) ADC1_RESRDY_Handler, /* 121 Analog Digital Converter */ - .pfnAC_Handler = (void*) AC_Handler, /* 122 Analog Comparators */ - .pfnDAC_OTHER_Handler = (void*) DAC_OTHER_Handler, /* 123 Digital-to-Analog Converter */ - .pfnDAC_EMPTY_0_Handler = (void*) DAC_EMPTY_0_Handler, /* 124 Digital-to-Analog Converter */ - .pfnDAC_EMPTY_1_Handler = (void*) DAC_EMPTY_1_Handler, /* 125 Digital-to-Analog Converter */ - .pfnDAC_RESRDY_0_Handler = (void*) DAC_RESRDY_0_Handler, /* 126 Digital-to-Analog Converter */ - .pfnDAC_RESRDY_1_Handler = (void*) DAC_RESRDY_1_Handler, /* 127 Digital-to-Analog Converter */ - .pfnI2S_Handler = (void*) I2S_Handler, /* 128 Inter-IC Sound Interface */ - .pfnPCC_Handler = (void*) PCC_Handler, /* 129 Parallel Capture Controller */ - .pfnAES_Handler = (void*) AES_Handler, /* 130 Advanced Encryption Standard */ - .pfnTRNG_Handler = (void*) TRNG_Handler, /* 131 True Random Generator */ - .pfnICM_Handler = (void*) ICM_Handler, /* 132 Integrity Check Monitor */ - .pfnPUKCC_Handler = (void*) PUKCC_Handler, /* 133 PUblic-Key Cryptography Controller */ - .pfnQSPI_Handler = (void*) QSPI_Handler, /* 134 Quad SPI interface */ - .pfnSDHC0_Handler = (void*) SDHC0_Handler, /* 135 SD/MMC Host Controller */ - .pfnSDHC1_Handler = (void*) SDHC1_Handler /* 136 SD/MMC Host Controller */ -}; - -/** - * \brief This is the code that gets called on processor reset. - * To initialize the device, and call the main() routine. - */ -void Reset_Handler(void) -{ - uint32_t *pSrc, *pDest; - - /* Initialize the relocate segment */ - pSrc = &_etext; - pDest = &_srelocate; - - if (pSrc != pDest) { - for (; pDest < &_erelocate;) { - *pDest++ = *pSrc++; - } - } - - /* Clear the zero segment */ - for (pDest = &_szero; pDest < &_ezero;) { - *pDest++ = 0; - } - - /* Set the vector table base address */ - pSrc = (uint32_t *) & _sfixed; - SCB->VTOR = ((uint32_t) pSrc & SCB_VTOR_TBLOFF_Msk); - - /* Initialize the C library */ - __libc_init_array(); - - /* Branch to main function */ - main(); - - /* Infinite loop */ - while (1); -} - -/** - * \brief Default interrupt handler for unused IRQs. - */ -void Dummy_Handler(void) -{ - while (1) { - } -} diff --git a/arch/arm/SAME54/SAME54A/mcu/src/startup_same54n20a.c b/arch/arm/SAME54/SAME54A/mcu/src/startup_same54n20a.c deleted file mode 100644 index b9cd7a90..00000000 --- a/arch/arm/SAME54/SAME54A/mcu/src/startup_same54n20a.c +++ /dev/null @@ -1,409 +0,0 @@ -/** - * \file - * - * \brief GCC startup file for ATSAME54N20A - * - * Copyright (c) 2020 Microchip Technology Inc. - * - * \license_start - * - * \page License - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \license_stop - * - */ - -#include "same54n20a.h" - -/* Initialize segments */ -extern uint32_t _sfixed; -extern uint32_t _efixed; -extern uint32_t _etext; -extern uint32_t _srelocate; -extern uint32_t _erelocate; -extern uint32_t _szero; -extern uint32_t _ezero; -extern uint32_t _sstack; -extern uint32_t _estack; - -/** \cond DOXYGEN_SHOULD_SKIP_THIS */ -int main(void); -/** \endcond */ - -void __libc_init_array(void); - -/* Reset handler */ -void Reset_Handler(void); - -/* Default empty handler */ -void Dummy_Handler(void); - -/* Cortex-M4 core handlers */ -void NonMaskableInt_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void HardFault_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void MemoryManagement_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void BusFault_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void UsageFault_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void SVCall_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void DebugMonitor_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void PendSV_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void SysTick_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); - -/* Peripherals handlers */ -void PM_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void MCLK_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void OSCCTRL_XOSC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void OSCCTRL_XOSC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void OSCCTRL_DFLL_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void OSCCTRL_DPLL0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void OSCCTRL_DPLL1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void OSC32KCTRL_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void SUPC_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void SUPC_BODDET_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void WDT_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void RTC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void EIC_EXTINT_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void EIC_EXTINT_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void EIC_EXTINT_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void EIC_EXTINT_3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void EIC_EXTINT_4_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void EIC_EXTINT_5_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void EIC_EXTINT_6_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void EIC_EXTINT_7_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void EIC_EXTINT_8_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void EIC_EXTINT_9_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void EIC_EXTINT_10_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void EIC_EXTINT_11_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void EIC_EXTINT_12_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void EIC_EXTINT_13_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void EIC_EXTINT_14_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void EIC_EXTINT_15_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void FREQM_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void NVMCTRL_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void NVMCTRL_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void DMAC_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void DMAC_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void DMAC_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void DMAC_3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void DMAC_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void EVSYS_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void EVSYS_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void EVSYS_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void EVSYS_3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void EVSYS_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void PAC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void RAMECC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void SERCOM0_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void SERCOM0_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void SERCOM0_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void SERCOM0_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void SERCOM1_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void SERCOM1_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void SERCOM1_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void SERCOM1_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void SERCOM2_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void SERCOM2_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void SERCOM2_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void SERCOM2_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void SERCOM3_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void SERCOM3_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void SERCOM3_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void SERCOM3_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void SERCOM4_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void SERCOM4_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void SERCOM4_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void SERCOM4_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void SERCOM5_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void SERCOM5_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void SERCOM5_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void SERCOM5_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void SERCOM6_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void SERCOM6_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void SERCOM6_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void SERCOM6_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void SERCOM7_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void SERCOM7_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void SERCOM7_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void SERCOM7_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void CAN0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void CAN1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void USB_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void USB_SOF_HSOF_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void USB_TRCPT0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void USB_TRCPT1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void GMAC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void TCC0_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void TCC0_MC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void TCC0_MC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void TCC0_MC2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void TCC0_MC3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void TCC0_MC4_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void TCC0_MC5_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void TCC1_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void TCC1_MC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void TCC1_MC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void TCC1_MC2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void TCC1_MC3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void TCC2_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void TCC2_MC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void TCC2_MC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void TCC2_MC2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void TCC3_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void TCC3_MC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void TCC3_MC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void TCC4_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void TCC4_MC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void TCC4_MC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void TC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void TC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void TC2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void TC3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void TC4_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void TC5_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void TC6_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void TC7_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void PDEC_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void PDEC_MC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void PDEC_MC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void ADC0_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void ADC0_RESRDY_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void ADC1_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void ADC1_RESRDY_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void AC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void DAC_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void DAC_EMPTY_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void DAC_EMPTY_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void DAC_RESRDY_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void DAC_RESRDY_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void I2S_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void PCC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void AES_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void TRNG_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void ICM_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void PUKCC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void QSPI_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void SDHC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void SDHC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); - -/* Exception Table */ -__attribute__ ((section(".vectors"))) -const DeviceVectors exception_table = { - - /* Configure Initial Stack Pointer, using linker-generated symbols */ - .pvStack = (void*) (&_estack), - - .pfnReset_Handler = (void*) Reset_Handler, - .pfnNonMaskableInt_Handler = (void*) NonMaskableInt_Handler, - .pfnHardFault_Handler = (void*) HardFault_Handler, - .pfnMemoryManagement_Handler = (void*) MemoryManagement_Handler, - .pfnBusFault_Handler = (void*) BusFault_Handler, - .pfnUsageFault_Handler = (void*) UsageFault_Handler, - .pvReservedC9 = (void*) (0UL), /* Reserved */ - .pvReservedC8 = (void*) (0UL), /* Reserved */ - .pvReservedC7 = (void*) (0UL), /* Reserved */ - .pvReservedC6 = (void*) (0UL), /* Reserved */ - .pfnSVCall_Handler = (void*) SVCall_Handler, - .pfnDebugMonitor_Handler = (void*) DebugMonitor_Handler, - .pvReservedC3 = (void*) (0UL), /* Reserved */ - .pfnPendSV_Handler = (void*) PendSV_Handler, - .pfnSysTick_Handler = (void*) SysTick_Handler, - - /* Configurable interrupts */ - .pfnPM_Handler = (void*) PM_Handler, /* 0 Power Manager */ - .pfnMCLK_Handler = (void*) MCLK_Handler, /* 1 Main Clock */ - .pfnOSCCTRL_XOSC0_Handler = (void*) OSCCTRL_XOSC0_Handler, /* 2 Oscillators Control */ - .pfnOSCCTRL_XOSC1_Handler = (void*) OSCCTRL_XOSC1_Handler, /* 3 Oscillators Control */ - .pfnOSCCTRL_DFLL_Handler = (void*) OSCCTRL_DFLL_Handler, /* 4 Oscillators Control */ - .pfnOSCCTRL_DPLL0_Handler = (void*) OSCCTRL_DPLL0_Handler, /* 5 Oscillators Control */ - .pfnOSCCTRL_DPLL1_Handler = (void*) OSCCTRL_DPLL1_Handler, /* 6 Oscillators Control */ - .pfnOSC32KCTRL_Handler = (void*) OSC32KCTRL_Handler, /* 7 32kHz Oscillators Control */ - .pfnSUPC_OTHER_Handler = (void*) SUPC_OTHER_Handler, /* 8 Supply Controller */ - .pfnSUPC_BODDET_Handler = (void*) SUPC_BODDET_Handler, /* 9 Supply Controller */ - .pfnWDT_Handler = (void*) WDT_Handler, /* 10 Watchdog Timer */ - .pfnRTC_Handler = (void*) RTC_Handler, /* 11 Real-Time Counter */ - .pfnEIC_EXTINT_0_Handler = (void*) EIC_EXTINT_0_Handler, /* 12 External Interrupt Controller */ - .pfnEIC_EXTINT_1_Handler = (void*) EIC_EXTINT_1_Handler, /* 13 External Interrupt Controller */ - .pfnEIC_EXTINT_2_Handler = (void*) EIC_EXTINT_2_Handler, /* 14 External Interrupt Controller */ - .pfnEIC_EXTINT_3_Handler = (void*) EIC_EXTINT_3_Handler, /* 15 External Interrupt Controller */ - .pfnEIC_EXTINT_4_Handler = (void*) EIC_EXTINT_4_Handler, /* 16 External Interrupt Controller */ - .pfnEIC_EXTINT_5_Handler = (void*) EIC_EXTINT_5_Handler, /* 17 External Interrupt Controller */ - .pfnEIC_EXTINT_6_Handler = (void*) EIC_EXTINT_6_Handler, /* 18 External Interrupt Controller */ - .pfnEIC_EXTINT_7_Handler = (void*) EIC_EXTINT_7_Handler, /* 19 External Interrupt Controller */ - .pfnEIC_EXTINT_8_Handler = (void*) EIC_EXTINT_8_Handler, /* 20 External Interrupt Controller */ - .pfnEIC_EXTINT_9_Handler = (void*) EIC_EXTINT_9_Handler, /* 21 External Interrupt Controller */ - .pfnEIC_EXTINT_10_Handler = (void*) EIC_EXTINT_10_Handler, /* 22 External Interrupt Controller */ - .pfnEIC_EXTINT_11_Handler = (void*) EIC_EXTINT_11_Handler, /* 23 External Interrupt Controller */ - .pfnEIC_EXTINT_12_Handler = (void*) EIC_EXTINT_12_Handler, /* 24 External Interrupt Controller */ - .pfnEIC_EXTINT_13_Handler = (void*) EIC_EXTINT_13_Handler, /* 25 External Interrupt Controller */ - .pfnEIC_EXTINT_14_Handler = (void*) EIC_EXTINT_14_Handler, /* 26 External Interrupt Controller */ - .pfnEIC_EXTINT_15_Handler = (void*) EIC_EXTINT_15_Handler, /* 27 External Interrupt Controller */ - .pfnFREQM_Handler = (void*) FREQM_Handler, /* 28 Frequency Meter */ - .pfnNVMCTRL_0_Handler = (void*) NVMCTRL_0_Handler, /* 29 Non-Volatile Memory Controller */ - .pfnNVMCTRL_1_Handler = (void*) NVMCTRL_1_Handler, /* 30 Non-Volatile Memory Controller */ - .pfnDMAC_0_Handler = (void*) DMAC_0_Handler, /* 31 Direct Memory Access Controller */ - .pfnDMAC_1_Handler = (void*) DMAC_1_Handler, /* 32 Direct Memory Access Controller */ - .pfnDMAC_2_Handler = (void*) DMAC_2_Handler, /* 33 Direct Memory Access Controller */ - .pfnDMAC_3_Handler = (void*) DMAC_3_Handler, /* 34 Direct Memory Access Controller */ - .pfnDMAC_OTHER_Handler = (void*) DMAC_OTHER_Handler, /* 35 Direct Memory Access Controller */ - .pfnEVSYS_0_Handler = (void*) EVSYS_0_Handler, /* 36 Event System Interface */ - .pfnEVSYS_1_Handler = (void*) EVSYS_1_Handler, /* 37 Event System Interface */ - .pfnEVSYS_2_Handler = (void*) EVSYS_2_Handler, /* 38 Event System Interface */ - .pfnEVSYS_3_Handler = (void*) EVSYS_3_Handler, /* 39 Event System Interface */ - .pfnEVSYS_OTHER_Handler = (void*) EVSYS_OTHER_Handler, /* 40 Event System Interface */ - .pfnPAC_Handler = (void*) PAC_Handler, /* 41 Peripheral Access Controller */ - .pvReserved42 = (void*) (0UL), /* 42 Reserved */ - .pvReserved43 = (void*) (0UL), /* 43 Reserved */ - .pvReserved44 = (void*) (0UL), /* 44 Reserved */ - .pfnRAMECC_Handler = (void*) RAMECC_Handler, /* 45 RAM ECC */ - .pfnSERCOM0_0_Handler = (void*) SERCOM0_0_Handler, /* 46 Serial Communication Interface */ - .pfnSERCOM0_1_Handler = (void*) SERCOM0_1_Handler, /* 47 Serial Communication Interface */ - .pfnSERCOM0_2_Handler = (void*) SERCOM0_2_Handler, /* 48 Serial Communication Interface */ - .pfnSERCOM0_OTHER_Handler = (void*) SERCOM0_OTHER_Handler, /* 49 Serial Communication Interface */ - .pfnSERCOM1_0_Handler = (void*) SERCOM1_0_Handler, /* 50 Serial Communication Interface */ - .pfnSERCOM1_1_Handler = (void*) SERCOM1_1_Handler, /* 51 Serial Communication Interface */ - .pfnSERCOM1_2_Handler = (void*) SERCOM1_2_Handler, /* 52 Serial Communication Interface */ - .pfnSERCOM1_OTHER_Handler = (void*) SERCOM1_OTHER_Handler, /* 53 Serial Communication Interface */ - .pfnSERCOM2_0_Handler = (void*) SERCOM2_0_Handler, /* 54 Serial Communication Interface */ - .pfnSERCOM2_1_Handler = (void*) SERCOM2_1_Handler, /* 55 Serial Communication Interface */ - .pfnSERCOM2_2_Handler = (void*) SERCOM2_2_Handler, /* 56 Serial Communication Interface */ - .pfnSERCOM2_OTHER_Handler = (void*) SERCOM2_OTHER_Handler, /* 57 Serial Communication Interface */ - .pfnSERCOM3_0_Handler = (void*) SERCOM3_0_Handler, /* 58 Serial Communication Interface */ - .pfnSERCOM3_1_Handler = (void*) SERCOM3_1_Handler, /* 59 Serial Communication Interface */ - .pfnSERCOM3_2_Handler = (void*) SERCOM3_2_Handler, /* 60 Serial Communication Interface */ - .pfnSERCOM3_OTHER_Handler = (void*) SERCOM3_OTHER_Handler, /* 61 Serial Communication Interface */ - .pfnSERCOM4_0_Handler = (void*) SERCOM4_0_Handler, /* 62 Serial Communication Interface */ - .pfnSERCOM4_1_Handler = (void*) SERCOM4_1_Handler, /* 63 Serial Communication Interface */ - .pfnSERCOM4_2_Handler = (void*) SERCOM4_2_Handler, /* 64 Serial Communication Interface */ - .pfnSERCOM4_OTHER_Handler = (void*) SERCOM4_OTHER_Handler, /* 65 Serial Communication Interface */ - .pfnSERCOM5_0_Handler = (void*) SERCOM5_0_Handler, /* 66 Serial Communication Interface */ - .pfnSERCOM5_1_Handler = (void*) SERCOM5_1_Handler, /* 67 Serial Communication Interface */ - .pfnSERCOM5_2_Handler = (void*) SERCOM5_2_Handler, /* 68 Serial Communication Interface */ - .pfnSERCOM5_OTHER_Handler = (void*) SERCOM5_OTHER_Handler, /* 69 Serial Communication Interface */ - .pfnSERCOM6_0_Handler = (void*) SERCOM6_0_Handler, /* 70 Serial Communication Interface */ - .pfnSERCOM6_1_Handler = (void*) SERCOM6_1_Handler, /* 71 Serial Communication Interface */ - .pfnSERCOM6_2_Handler = (void*) SERCOM6_2_Handler, /* 72 Serial Communication Interface */ - .pfnSERCOM6_OTHER_Handler = (void*) SERCOM6_OTHER_Handler, /* 73 Serial Communication Interface */ - .pfnSERCOM7_0_Handler = (void*) SERCOM7_0_Handler, /* 74 Serial Communication Interface */ - .pfnSERCOM7_1_Handler = (void*) SERCOM7_1_Handler, /* 75 Serial Communication Interface */ - .pfnSERCOM7_2_Handler = (void*) SERCOM7_2_Handler, /* 76 Serial Communication Interface */ - .pfnSERCOM7_OTHER_Handler = (void*) SERCOM7_OTHER_Handler, /* 77 Serial Communication Interface */ - .pfnCAN0_Handler = (void*) CAN0_Handler, /* 78 Control Area Network */ - .pfnCAN1_Handler = (void*) CAN1_Handler, /* 79 Control Area Network */ - .pfnUSB_OTHER_Handler = (void*) USB_OTHER_Handler, /* 80 Universal Serial Bus */ - .pfnUSB_SOF_HSOF_Handler = (void*) USB_SOF_HSOF_Handler, /* 81 Universal Serial Bus */ - .pfnUSB_TRCPT0_Handler = (void*) USB_TRCPT0_Handler, /* 82 Universal Serial Bus */ - .pfnUSB_TRCPT1_Handler = (void*) USB_TRCPT1_Handler, /* 83 Universal Serial Bus */ - .pfnGMAC_Handler = (void*) GMAC_Handler, /* 84 Ethernet MAC */ - .pfnTCC0_OTHER_Handler = (void*) TCC0_OTHER_Handler, /* 85 Timer Counter Control */ - .pfnTCC0_MC0_Handler = (void*) TCC0_MC0_Handler, /* 86 Timer Counter Control */ - .pfnTCC0_MC1_Handler = (void*) TCC0_MC1_Handler, /* 87 Timer Counter Control */ - .pfnTCC0_MC2_Handler = (void*) TCC0_MC2_Handler, /* 88 Timer Counter Control */ - .pfnTCC0_MC3_Handler = (void*) TCC0_MC3_Handler, /* 89 Timer Counter Control */ - .pfnTCC0_MC4_Handler = (void*) TCC0_MC4_Handler, /* 90 Timer Counter Control */ - .pfnTCC0_MC5_Handler = (void*) TCC0_MC5_Handler, /* 91 Timer Counter Control */ - .pfnTCC1_OTHER_Handler = (void*) TCC1_OTHER_Handler, /* 92 Timer Counter Control */ - .pfnTCC1_MC0_Handler = (void*) TCC1_MC0_Handler, /* 93 Timer Counter Control */ - .pfnTCC1_MC1_Handler = (void*) TCC1_MC1_Handler, /* 94 Timer Counter Control */ - .pfnTCC1_MC2_Handler = (void*) TCC1_MC2_Handler, /* 95 Timer Counter Control */ - .pfnTCC1_MC3_Handler = (void*) TCC1_MC3_Handler, /* 96 Timer Counter Control */ - .pfnTCC2_OTHER_Handler = (void*) TCC2_OTHER_Handler, /* 97 Timer Counter Control */ - .pfnTCC2_MC0_Handler = (void*) TCC2_MC0_Handler, /* 98 Timer Counter Control */ - .pfnTCC2_MC1_Handler = (void*) TCC2_MC1_Handler, /* 99 Timer Counter Control */ - .pfnTCC2_MC2_Handler = (void*) TCC2_MC2_Handler, /* 100 Timer Counter Control */ - .pfnTCC3_OTHER_Handler = (void*) TCC3_OTHER_Handler, /* 101 Timer Counter Control */ - .pfnTCC3_MC0_Handler = (void*) TCC3_MC0_Handler, /* 102 Timer Counter Control */ - .pfnTCC3_MC1_Handler = (void*) TCC3_MC1_Handler, /* 103 Timer Counter Control */ - .pfnTCC4_OTHER_Handler = (void*) TCC4_OTHER_Handler, /* 104 Timer Counter Control */ - .pfnTCC4_MC0_Handler = (void*) TCC4_MC0_Handler, /* 105 Timer Counter Control */ - .pfnTCC4_MC1_Handler = (void*) TCC4_MC1_Handler, /* 106 Timer Counter Control */ - .pfnTC0_Handler = (void*) TC0_Handler, /* 107 Basic Timer Counter */ - .pfnTC1_Handler = (void*) TC1_Handler, /* 108 Basic Timer Counter */ - .pfnTC2_Handler = (void*) TC2_Handler, /* 109 Basic Timer Counter */ - .pfnTC3_Handler = (void*) TC3_Handler, /* 110 Basic Timer Counter */ - .pfnTC4_Handler = (void*) TC4_Handler, /* 111 Basic Timer Counter */ - .pfnTC5_Handler = (void*) TC5_Handler, /* 112 Basic Timer Counter */ - .pfnTC6_Handler = (void*) TC6_Handler, /* 113 Basic Timer Counter */ - .pfnTC7_Handler = (void*) TC7_Handler, /* 114 Basic Timer Counter */ - .pfnPDEC_OTHER_Handler = (void*) PDEC_OTHER_Handler, /* 115 Quadrature Decodeur */ - .pfnPDEC_MC0_Handler = (void*) PDEC_MC0_Handler, /* 116 Quadrature Decodeur */ - .pfnPDEC_MC1_Handler = (void*) PDEC_MC1_Handler, /* 117 Quadrature Decodeur */ - .pfnADC0_OTHER_Handler = (void*) ADC0_OTHER_Handler, /* 118 Analog Digital Converter */ - .pfnADC0_RESRDY_Handler = (void*) ADC0_RESRDY_Handler, /* 119 Analog Digital Converter */ - .pfnADC1_OTHER_Handler = (void*) ADC1_OTHER_Handler, /* 120 Analog Digital Converter */ - .pfnADC1_RESRDY_Handler = (void*) ADC1_RESRDY_Handler, /* 121 Analog Digital Converter */ - .pfnAC_Handler = (void*) AC_Handler, /* 122 Analog Comparators */ - .pfnDAC_OTHER_Handler = (void*) DAC_OTHER_Handler, /* 123 Digital-to-Analog Converter */ - .pfnDAC_EMPTY_0_Handler = (void*) DAC_EMPTY_0_Handler, /* 124 Digital-to-Analog Converter */ - .pfnDAC_EMPTY_1_Handler = (void*) DAC_EMPTY_1_Handler, /* 125 Digital-to-Analog Converter */ - .pfnDAC_RESRDY_0_Handler = (void*) DAC_RESRDY_0_Handler, /* 126 Digital-to-Analog Converter */ - .pfnDAC_RESRDY_1_Handler = (void*) DAC_RESRDY_1_Handler, /* 127 Digital-to-Analog Converter */ - .pfnI2S_Handler = (void*) I2S_Handler, /* 128 Inter-IC Sound Interface */ - .pfnPCC_Handler = (void*) PCC_Handler, /* 129 Parallel Capture Controller */ - .pfnAES_Handler = (void*) AES_Handler, /* 130 Advanced Encryption Standard */ - .pfnTRNG_Handler = (void*) TRNG_Handler, /* 131 True Random Generator */ - .pfnICM_Handler = (void*) ICM_Handler, /* 132 Integrity Check Monitor */ - .pfnPUKCC_Handler = (void*) PUKCC_Handler, /* 133 PUblic-Key Cryptography Controller */ - .pfnQSPI_Handler = (void*) QSPI_Handler, /* 134 Quad SPI interface */ - .pfnSDHC0_Handler = (void*) SDHC0_Handler, /* 135 SD/MMC Host Controller */ - .pfnSDHC1_Handler = (void*) SDHC1_Handler /* 136 SD/MMC Host Controller */ -}; - -/** - * \brief This is the code that gets called on processor reset. - * To initialize the device, and call the main() routine. - */ -void Reset_Handler(void) -{ - uint32_t *pSrc, *pDest; - - /* Initialize the relocate segment */ - pSrc = &_etext; - pDest = &_srelocate; - - if (pSrc != pDest) { - for (; pDest < &_erelocate;) { - *pDest++ = *pSrc++; - } - } - - /* Clear the zero segment */ - for (pDest = &_szero; pDest < &_ezero;) { - *pDest++ = 0; - } - - /* Set the vector table base address */ - pSrc = (uint32_t *) & _sfixed; - SCB->VTOR = ((uint32_t) pSrc & SCB_VTOR_TBLOFF_Msk); - - /* Initialize the C library */ - __libc_init_array(); - - /* Branch to main function */ - main(); - - /* Infinite loop */ - while (1); -} - -/** - * \brief Default interrupt handler for unused IRQs. - */ -void Dummy_Handler(void) -{ - while (1) { - } -} diff --git a/arch/arm/SAME54/SAME54A/mcu/src/startup_same54p19a.c b/arch/arm/SAME54/SAME54A/mcu/src/startup_same54p19a.c deleted file mode 100644 index 544ebb82..00000000 --- a/arch/arm/SAME54/SAME54A/mcu/src/startup_same54p19a.c +++ /dev/null @@ -1,409 +0,0 @@ -/** - * \file - * - * \brief GCC startup file for ATSAME54P19A - * - * Copyright (c) 2020 Microchip Technology Inc. - * - * \license_start - * - * \page License - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \license_stop - * - */ - -#include "same54p19a.h" - -/* Initialize segments */ -extern uint32_t _sfixed; -extern uint32_t _efixed; -extern uint32_t _etext; -extern uint32_t _srelocate; -extern uint32_t _erelocate; -extern uint32_t _szero; -extern uint32_t _ezero; -extern uint32_t _sstack; -extern uint32_t _estack; - -/** \cond DOXYGEN_SHOULD_SKIP_THIS */ -int main(void); -/** \endcond */ - -void __libc_init_array(void); - -/* Reset handler */ -void Reset_Handler(void); - -/* Default empty handler */ -void Dummy_Handler(void); - -/* Cortex-M4 core handlers */ -void NonMaskableInt_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void HardFault_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void MemoryManagement_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void BusFault_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void UsageFault_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void SVCall_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void DebugMonitor_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void PendSV_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void SysTick_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); - -/* Peripherals handlers */ -void PM_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void MCLK_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void OSCCTRL_XOSC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void OSCCTRL_XOSC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void OSCCTRL_DFLL_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void OSCCTRL_DPLL0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void OSCCTRL_DPLL1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void OSC32KCTRL_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void SUPC_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void SUPC_BODDET_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void WDT_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void RTC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void EIC_EXTINT_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void EIC_EXTINT_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void EIC_EXTINT_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void EIC_EXTINT_3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void EIC_EXTINT_4_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void EIC_EXTINT_5_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void EIC_EXTINT_6_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void EIC_EXTINT_7_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void EIC_EXTINT_8_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void EIC_EXTINT_9_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void EIC_EXTINT_10_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void EIC_EXTINT_11_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void EIC_EXTINT_12_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void EIC_EXTINT_13_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void EIC_EXTINT_14_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void EIC_EXTINT_15_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void FREQM_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void NVMCTRL_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void NVMCTRL_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void DMAC_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void DMAC_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void DMAC_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void DMAC_3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void DMAC_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void EVSYS_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void EVSYS_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void EVSYS_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void EVSYS_3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void EVSYS_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void PAC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void RAMECC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void SERCOM0_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void SERCOM0_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void SERCOM0_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void SERCOM0_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void SERCOM1_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void SERCOM1_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void SERCOM1_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void SERCOM1_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void SERCOM2_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void SERCOM2_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void SERCOM2_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void SERCOM2_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void SERCOM3_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void SERCOM3_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void SERCOM3_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void SERCOM3_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void SERCOM4_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void SERCOM4_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void SERCOM4_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void SERCOM4_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void SERCOM5_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void SERCOM5_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void SERCOM5_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void SERCOM5_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void SERCOM6_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void SERCOM6_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void SERCOM6_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void SERCOM6_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void SERCOM7_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void SERCOM7_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void SERCOM7_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void SERCOM7_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void CAN0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void CAN1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void USB_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void USB_SOF_HSOF_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void USB_TRCPT0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void USB_TRCPT1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void GMAC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void TCC0_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void TCC0_MC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void TCC0_MC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void TCC0_MC2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void TCC0_MC3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void TCC0_MC4_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void TCC0_MC5_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void TCC1_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void TCC1_MC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void TCC1_MC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void TCC1_MC2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void TCC1_MC3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void TCC2_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void TCC2_MC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void TCC2_MC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void TCC2_MC2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void TCC3_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void TCC3_MC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void TCC3_MC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void TCC4_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void TCC4_MC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void TCC4_MC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void TC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void TC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void TC2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void TC3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void TC4_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void TC5_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void TC6_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void TC7_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void PDEC_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void PDEC_MC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void PDEC_MC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void ADC0_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void ADC0_RESRDY_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void ADC1_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void ADC1_RESRDY_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void AC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void DAC_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void DAC_EMPTY_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void DAC_EMPTY_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void DAC_RESRDY_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void DAC_RESRDY_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void I2S_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void PCC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void AES_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void TRNG_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void ICM_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void PUKCC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void QSPI_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void SDHC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void SDHC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); - -/* Exception Table */ -__attribute__ ((section(".vectors"))) -const DeviceVectors exception_table = { - - /* Configure Initial Stack Pointer, using linker-generated symbols */ - .pvStack = (void*) (&_estack), - - .pfnReset_Handler = (void*) Reset_Handler, - .pfnNonMaskableInt_Handler = (void*) NonMaskableInt_Handler, - .pfnHardFault_Handler = (void*) HardFault_Handler, - .pfnMemoryManagement_Handler = (void*) MemoryManagement_Handler, - .pfnBusFault_Handler = (void*) BusFault_Handler, - .pfnUsageFault_Handler = (void*) UsageFault_Handler, - .pvReservedC9 = (void*) (0UL), /* Reserved */ - .pvReservedC8 = (void*) (0UL), /* Reserved */ - .pvReservedC7 = (void*) (0UL), /* Reserved */ - .pvReservedC6 = (void*) (0UL), /* Reserved */ - .pfnSVCall_Handler = (void*) SVCall_Handler, - .pfnDebugMonitor_Handler = (void*) DebugMonitor_Handler, - .pvReservedC3 = (void*) (0UL), /* Reserved */ - .pfnPendSV_Handler = (void*) PendSV_Handler, - .pfnSysTick_Handler = (void*) SysTick_Handler, - - /* Configurable interrupts */ - .pfnPM_Handler = (void*) PM_Handler, /* 0 Power Manager */ - .pfnMCLK_Handler = (void*) MCLK_Handler, /* 1 Main Clock */ - .pfnOSCCTRL_XOSC0_Handler = (void*) OSCCTRL_XOSC0_Handler, /* 2 Oscillators Control */ - .pfnOSCCTRL_XOSC1_Handler = (void*) OSCCTRL_XOSC1_Handler, /* 3 Oscillators Control */ - .pfnOSCCTRL_DFLL_Handler = (void*) OSCCTRL_DFLL_Handler, /* 4 Oscillators Control */ - .pfnOSCCTRL_DPLL0_Handler = (void*) OSCCTRL_DPLL0_Handler, /* 5 Oscillators Control */ - .pfnOSCCTRL_DPLL1_Handler = (void*) OSCCTRL_DPLL1_Handler, /* 6 Oscillators Control */ - .pfnOSC32KCTRL_Handler = (void*) OSC32KCTRL_Handler, /* 7 32kHz Oscillators Control */ - .pfnSUPC_OTHER_Handler = (void*) SUPC_OTHER_Handler, /* 8 Supply Controller */ - .pfnSUPC_BODDET_Handler = (void*) SUPC_BODDET_Handler, /* 9 Supply Controller */ - .pfnWDT_Handler = (void*) WDT_Handler, /* 10 Watchdog Timer */ - .pfnRTC_Handler = (void*) RTC_Handler, /* 11 Real-Time Counter */ - .pfnEIC_EXTINT_0_Handler = (void*) EIC_EXTINT_0_Handler, /* 12 External Interrupt Controller */ - .pfnEIC_EXTINT_1_Handler = (void*) EIC_EXTINT_1_Handler, /* 13 External Interrupt Controller */ - .pfnEIC_EXTINT_2_Handler = (void*) EIC_EXTINT_2_Handler, /* 14 External Interrupt Controller */ - .pfnEIC_EXTINT_3_Handler = (void*) EIC_EXTINT_3_Handler, /* 15 External Interrupt Controller */ - .pfnEIC_EXTINT_4_Handler = (void*) EIC_EXTINT_4_Handler, /* 16 External Interrupt Controller */ - .pfnEIC_EXTINT_5_Handler = (void*) EIC_EXTINT_5_Handler, /* 17 External Interrupt Controller */ - .pfnEIC_EXTINT_6_Handler = (void*) EIC_EXTINT_6_Handler, /* 18 External Interrupt Controller */ - .pfnEIC_EXTINT_7_Handler = (void*) EIC_EXTINT_7_Handler, /* 19 External Interrupt Controller */ - .pfnEIC_EXTINT_8_Handler = (void*) EIC_EXTINT_8_Handler, /* 20 External Interrupt Controller */ - .pfnEIC_EXTINT_9_Handler = (void*) EIC_EXTINT_9_Handler, /* 21 External Interrupt Controller */ - .pfnEIC_EXTINT_10_Handler = (void*) EIC_EXTINT_10_Handler, /* 22 External Interrupt Controller */ - .pfnEIC_EXTINT_11_Handler = (void*) EIC_EXTINT_11_Handler, /* 23 External Interrupt Controller */ - .pfnEIC_EXTINT_12_Handler = (void*) EIC_EXTINT_12_Handler, /* 24 External Interrupt Controller */ - .pfnEIC_EXTINT_13_Handler = (void*) EIC_EXTINT_13_Handler, /* 25 External Interrupt Controller */ - .pfnEIC_EXTINT_14_Handler = (void*) EIC_EXTINT_14_Handler, /* 26 External Interrupt Controller */ - .pfnEIC_EXTINT_15_Handler = (void*) EIC_EXTINT_15_Handler, /* 27 External Interrupt Controller */ - .pfnFREQM_Handler = (void*) FREQM_Handler, /* 28 Frequency Meter */ - .pfnNVMCTRL_0_Handler = (void*) NVMCTRL_0_Handler, /* 29 Non-Volatile Memory Controller */ - .pfnNVMCTRL_1_Handler = (void*) NVMCTRL_1_Handler, /* 30 Non-Volatile Memory Controller */ - .pfnDMAC_0_Handler = (void*) DMAC_0_Handler, /* 31 Direct Memory Access Controller */ - .pfnDMAC_1_Handler = (void*) DMAC_1_Handler, /* 32 Direct Memory Access Controller */ - .pfnDMAC_2_Handler = (void*) DMAC_2_Handler, /* 33 Direct Memory Access Controller */ - .pfnDMAC_3_Handler = (void*) DMAC_3_Handler, /* 34 Direct Memory Access Controller */ - .pfnDMAC_OTHER_Handler = (void*) DMAC_OTHER_Handler, /* 35 Direct Memory Access Controller */ - .pfnEVSYS_0_Handler = (void*) EVSYS_0_Handler, /* 36 Event System Interface */ - .pfnEVSYS_1_Handler = (void*) EVSYS_1_Handler, /* 37 Event System Interface */ - .pfnEVSYS_2_Handler = (void*) EVSYS_2_Handler, /* 38 Event System Interface */ - .pfnEVSYS_3_Handler = (void*) EVSYS_3_Handler, /* 39 Event System Interface */ - .pfnEVSYS_OTHER_Handler = (void*) EVSYS_OTHER_Handler, /* 40 Event System Interface */ - .pfnPAC_Handler = (void*) PAC_Handler, /* 41 Peripheral Access Controller */ - .pvReserved42 = (void*) (0UL), /* 42 Reserved */ - .pvReserved43 = (void*) (0UL), /* 43 Reserved */ - .pvReserved44 = (void*) (0UL), /* 44 Reserved */ - .pfnRAMECC_Handler = (void*) RAMECC_Handler, /* 45 RAM ECC */ - .pfnSERCOM0_0_Handler = (void*) SERCOM0_0_Handler, /* 46 Serial Communication Interface */ - .pfnSERCOM0_1_Handler = (void*) SERCOM0_1_Handler, /* 47 Serial Communication Interface */ - .pfnSERCOM0_2_Handler = (void*) SERCOM0_2_Handler, /* 48 Serial Communication Interface */ - .pfnSERCOM0_OTHER_Handler = (void*) SERCOM0_OTHER_Handler, /* 49 Serial Communication Interface */ - .pfnSERCOM1_0_Handler = (void*) SERCOM1_0_Handler, /* 50 Serial Communication Interface */ - .pfnSERCOM1_1_Handler = (void*) SERCOM1_1_Handler, /* 51 Serial Communication Interface */ - .pfnSERCOM1_2_Handler = (void*) SERCOM1_2_Handler, /* 52 Serial Communication Interface */ - .pfnSERCOM1_OTHER_Handler = (void*) SERCOM1_OTHER_Handler, /* 53 Serial Communication Interface */ - .pfnSERCOM2_0_Handler = (void*) SERCOM2_0_Handler, /* 54 Serial Communication Interface */ - .pfnSERCOM2_1_Handler = (void*) SERCOM2_1_Handler, /* 55 Serial Communication Interface */ - .pfnSERCOM2_2_Handler = (void*) SERCOM2_2_Handler, /* 56 Serial Communication Interface */ - .pfnSERCOM2_OTHER_Handler = (void*) SERCOM2_OTHER_Handler, /* 57 Serial Communication Interface */ - .pfnSERCOM3_0_Handler = (void*) SERCOM3_0_Handler, /* 58 Serial Communication Interface */ - .pfnSERCOM3_1_Handler = (void*) SERCOM3_1_Handler, /* 59 Serial Communication Interface */ - .pfnSERCOM3_2_Handler = (void*) SERCOM3_2_Handler, /* 60 Serial Communication Interface */ - .pfnSERCOM3_OTHER_Handler = (void*) SERCOM3_OTHER_Handler, /* 61 Serial Communication Interface */ - .pfnSERCOM4_0_Handler = (void*) SERCOM4_0_Handler, /* 62 Serial Communication Interface */ - .pfnSERCOM4_1_Handler = (void*) SERCOM4_1_Handler, /* 63 Serial Communication Interface */ - .pfnSERCOM4_2_Handler = (void*) SERCOM4_2_Handler, /* 64 Serial Communication Interface */ - .pfnSERCOM4_OTHER_Handler = (void*) SERCOM4_OTHER_Handler, /* 65 Serial Communication Interface */ - .pfnSERCOM5_0_Handler = (void*) SERCOM5_0_Handler, /* 66 Serial Communication Interface */ - .pfnSERCOM5_1_Handler = (void*) SERCOM5_1_Handler, /* 67 Serial Communication Interface */ - .pfnSERCOM5_2_Handler = (void*) SERCOM5_2_Handler, /* 68 Serial Communication Interface */ - .pfnSERCOM5_OTHER_Handler = (void*) SERCOM5_OTHER_Handler, /* 69 Serial Communication Interface */ - .pfnSERCOM6_0_Handler = (void*) SERCOM6_0_Handler, /* 70 Serial Communication Interface */ - .pfnSERCOM6_1_Handler = (void*) SERCOM6_1_Handler, /* 71 Serial Communication Interface */ - .pfnSERCOM6_2_Handler = (void*) SERCOM6_2_Handler, /* 72 Serial Communication Interface */ - .pfnSERCOM6_OTHER_Handler = (void*) SERCOM6_OTHER_Handler, /* 73 Serial Communication Interface */ - .pfnSERCOM7_0_Handler = (void*) SERCOM7_0_Handler, /* 74 Serial Communication Interface */ - .pfnSERCOM7_1_Handler = (void*) SERCOM7_1_Handler, /* 75 Serial Communication Interface */ - .pfnSERCOM7_2_Handler = (void*) SERCOM7_2_Handler, /* 76 Serial Communication Interface */ - .pfnSERCOM7_OTHER_Handler = (void*) SERCOM7_OTHER_Handler, /* 77 Serial Communication Interface */ - .pfnCAN0_Handler = (void*) CAN0_Handler, /* 78 Control Area Network */ - .pfnCAN1_Handler = (void*) CAN1_Handler, /* 79 Control Area Network */ - .pfnUSB_OTHER_Handler = (void*) USB_OTHER_Handler, /* 80 Universal Serial Bus */ - .pfnUSB_SOF_HSOF_Handler = (void*) USB_SOF_HSOF_Handler, /* 81 Universal Serial Bus */ - .pfnUSB_TRCPT0_Handler = (void*) USB_TRCPT0_Handler, /* 82 Universal Serial Bus */ - .pfnUSB_TRCPT1_Handler = (void*) USB_TRCPT1_Handler, /* 83 Universal Serial Bus */ - .pfnGMAC_Handler = (void*) GMAC_Handler, /* 84 Ethernet MAC */ - .pfnTCC0_OTHER_Handler = (void*) TCC0_OTHER_Handler, /* 85 Timer Counter Control */ - .pfnTCC0_MC0_Handler = (void*) TCC0_MC0_Handler, /* 86 Timer Counter Control */ - .pfnTCC0_MC1_Handler = (void*) TCC0_MC1_Handler, /* 87 Timer Counter Control */ - .pfnTCC0_MC2_Handler = (void*) TCC0_MC2_Handler, /* 88 Timer Counter Control */ - .pfnTCC0_MC3_Handler = (void*) TCC0_MC3_Handler, /* 89 Timer Counter Control */ - .pfnTCC0_MC4_Handler = (void*) TCC0_MC4_Handler, /* 90 Timer Counter Control */ - .pfnTCC0_MC5_Handler = (void*) TCC0_MC5_Handler, /* 91 Timer Counter Control */ - .pfnTCC1_OTHER_Handler = (void*) TCC1_OTHER_Handler, /* 92 Timer Counter Control */ - .pfnTCC1_MC0_Handler = (void*) TCC1_MC0_Handler, /* 93 Timer Counter Control */ - .pfnTCC1_MC1_Handler = (void*) TCC1_MC1_Handler, /* 94 Timer Counter Control */ - .pfnTCC1_MC2_Handler = (void*) TCC1_MC2_Handler, /* 95 Timer Counter Control */ - .pfnTCC1_MC3_Handler = (void*) TCC1_MC3_Handler, /* 96 Timer Counter Control */ - .pfnTCC2_OTHER_Handler = (void*) TCC2_OTHER_Handler, /* 97 Timer Counter Control */ - .pfnTCC2_MC0_Handler = (void*) TCC2_MC0_Handler, /* 98 Timer Counter Control */ - .pfnTCC2_MC1_Handler = (void*) TCC2_MC1_Handler, /* 99 Timer Counter Control */ - .pfnTCC2_MC2_Handler = (void*) TCC2_MC2_Handler, /* 100 Timer Counter Control */ - .pfnTCC3_OTHER_Handler = (void*) TCC3_OTHER_Handler, /* 101 Timer Counter Control */ - .pfnTCC3_MC0_Handler = (void*) TCC3_MC0_Handler, /* 102 Timer Counter Control */ - .pfnTCC3_MC1_Handler = (void*) TCC3_MC1_Handler, /* 103 Timer Counter Control */ - .pfnTCC4_OTHER_Handler = (void*) TCC4_OTHER_Handler, /* 104 Timer Counter Control */ - .pfnTCC4_MC0_Handler = (void*) TCC4_MC0_Handler, /* 105 Timer Counter Control */ - .pfnTCC4_MC1_Handler = (void*) TCC4_MC1_Handler, /* 106 Timer Counter Control */ - .pfnTC0_Handler = (void*) TC0_Handler, /* 107 Basic Timer Counter */ - .pfnTC1_Handler = (void*) TC1_Handler, /* 108 Basic Timer Counter */ - .pfnTC2_Handler = (void*) TC2_Handler, /* 109 Basic Timer Counter */ - .pfnTC3_Handler = (void*) TC3_Handler, /* 110 Basic Timer Counter */ - .pfnTC4_Handler = (void*) TC4_Handler, /* 111 Basic Timer Counter */ - .pfnTC5_Handler = (void*) TC5_Handler, /* 112 Basic Timer Counter */ - .pfnTC6_Handler = (void*) TC6_Handler, /* 113 Basic Timer Counter */ - .pfnTC7_Handler = (void*) TC7_Handler, /* 114 Basic Timer Counter */ - .pfnPDEC_OTHER_Handler = (void*) PDEC_OTHER_Handler, /* 115 Quadrature Decodeur */ - .pfnPDEC_MC0_Handler = (void*) PDEC_MC0_Handler, /* 116 Quadrature Decodeur */ - .pfnPDEC_MC1_Handler = (void*) PDEC_MC1_Handler, /* 117 Quadrature Decodeur */ - .pfnADC0_OTHER_Handler = (void*) ADC0_OTHER_Handler, /* 118 Analog Digital Converter */ - .pfnADC0_RESRDY_Handler = (void*) ADC0_RESRDY_Handler, /* 119 Analog Digital Converter */ - .pfnADC1_OTHER_Handler = (void*) ADC1_OTHER_Handler, /* 120 Analog Digital Converter */ - .pfnADC1_RESRDY_Handler = (void*) ADC1_RESRDY_Handler, /* 121 Analog Digital Converter */ - .pfnAC_Handler = (void*) AC_Handler, /* 122 Analog Comparators */ - .pfnDAC_OTHER_Handler = (void*) DAC_OTHER_Handler, /* 123 Digital-to-Analog Converter */ - .pfnDAC_EMPTY_0_Handler = (void*) DAC_EMPTY_0_Handler, /* 124 Digital-to-Analog Converter */ - .pfnDAC_EMPTY_1_Handler = (void*) DAC_EMPTY_1_Handler, /* 125 Digital-to-Analog Converter */ - .pfnDAC_RESRDY_0_Handler = (void*) DAC_RESRDY_0_Handler, /* 126 Digital-to-Analog Converter */ - .pfnDAC_RESRDY_1_Handler = (void*) DAC_RESRDY_1_Handler, /* 127 Digital-to-Analog Converter */ - .pfnI2S_Handler = (void*) I2S_Handler, /* 128 Inter-IC Sound Interface */ - .pfnPCC_Handler = (void*) PCC_Handler, /* 129 Parallel Capture Controller */ - .pfnAES_Handler = (void*) AES_Handler, /* 130 Advanced Encryption Standard */ - .pfnTRNG_Handler = (void*) TRNG_Handler, /* 131 True Random Generator */ - .pfnICM_Handler = (void*) ICM_Handler, /* 132 Integrity Check Monitor */ - .pfnPUKCC_Handler = (void*) PUKCC_Handler, /* 133 PUblic-Key Cryptography Controller */ - .pfnQSPI_Handler = (void*) QSPI_Handler, /* 134 Quad SPI interface */ - .pfnSDHC0_Handler = (void*) SDHC0_Handler, /* 135 SD/MMC Host Controller */ - .pfnSDHC1_Handler = (void*) SDHC1_Handler /* 136 SD/MMC Host Controller */ -}; - -/** - * \brief This is the code that gets called on processor reset. - * To initialize the device, and call the main() routine. - */ -void Reset_Handler(void) -{ - uint32_t *pSrc, *pDest; - - /* Initialize the relocate segment */ - pSrc = &_etext; - pDest = &_srelocate; - - if (pSrc != pDest) { - for (; pDest < &_erelocate;) { - *pDest++ = *pSrc++; - } - } - - /* Clear the zero segment */ - for (pDest = &_szero; pDest < &_ezero;) { - *pDest++ = 0; - } - - /* Set the vector table base address */ - pSrc = (uint32_t *) & _sfixed; - SCB->VTOR = ((uint32_t) pSrc & SCB_VTOR_TBLOFF_Msk); - - /* Initialize the C library */ - __libc_init_array(); - - /* Branch to main function */ - main(); - - /* Infinite loop */ - while (1); -} - -/** - * \brief Default interrupt handler for unused IRQs. - */ -void Dummy_Handler(void) -{ - while (1) { - } -} diff --git a/arch/arm/SAME54/SAME54A/mcu/src/startup_same54p20a.c b/arch/arm/SAME54/SAME54A/mcu/src/startup_same54p20a.c deleted file mode 100644 index 9f29857e..00000000 --- a/arch/arm/SAME54/SAME54A/mcu/src/startup_same54p20a.c +++ /dev/null @@ -1,409 +0,0 @@ -/** - * \file - * - * \brief GCC startup file for ATSAME54P20A - * - * Copyright (c) 2020 Microchip Technology Inc. - * - * \license_start - * - * \page License - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \license_stop - * - */ - -#include "same54p20a.h" - -/* Initialize segments */ -extern uint32_t _sfixed; -extern uint32_t _efixed; -extern uint32_t _etext; -extern uint32_t _srelocate; -extern uint32_t _erelocate; -extern uint32_t _szero; -extern uint32_t _ezero; -extern uint32_t _sstack; -extern uint32_t _estack; - -/** \cond DOXYGEN_SHOULD_SKIP_THIS */ -int main(void); -/** \endcond */ - -void __libc_init_array(void); - -/* Reset handler */ -void Reset_Handler(void); - -/* Default empty handler */ -void Dummy_Handler(void); - -/* Cortex-M4 core handlers */ -void NonMaskableInt_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void HardFault_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void MemoryManagement_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void BusFault_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void UsageFault_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void SVCall_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void DebugMonitor_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void PendSV_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void SysTick_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); - -/* Peripherals handlers */ -void PM_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void MCLK_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void OSCCTRL_XOSC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void OSCCTRL_XOSC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void OSCCTRL_DFLL_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void OSCCTRL_DPLL0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void OSCCTRL_DPLL1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void OSC32KCTRL_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void SUPC_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void SUPC_BODDET_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void WDT_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void RTC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void EIC_EXTINT_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void EIC_EXTINT_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void EIC_EXTINT_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void EIC_EXTINT_3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void EIC_EXTINT_4_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void EIC_EXTINT_5_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void EIC_EXTINT_6_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void EIC_EXTINT_7_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void EIC_EXTINT_8_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void EIC_EXTINT_9_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void EIC_EXTINT_10_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void EIC_EXTINT_11_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void EIC_EXTINT_12_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void EIC_EXTINT_13_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void EIC_EXTINT_14_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void EIC_EXTINT_15_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void FREQM_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void NVMCTRL_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void NVMCTRL_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void DMAC_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void DMAC_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void DMAC_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void DMAC_3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void DMAC_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void EVSYS_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void EVSYS_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void EVSYS_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void EVSYS_3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void EVSYS_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void PAC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void RAMECC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void SERCOM0_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void SERCOM0_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void SERCOM0_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void SERCOM0_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void SERCOM1_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void SERCOM1_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void SERCOM1_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void SERCOM1_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void SERCOM2_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void SERCOM2_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void SERCOM2_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void SERCOM2_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void SERCOM3_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void SERCOM3_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void SERCOM3_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void SERCOM3_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void SERCOM4_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void SERCOM4_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void SERCOM4_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void SERCOM4_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void SERCOM5_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void SERCOM5_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void SERCOM5_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void SERCOM5_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void SERCOM6_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void SERCOM6_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void SERCOM6_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void SERCOM6_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void SERCOM7_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void SERCOM7_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void SERCOM7_2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void SERCOM7_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void CAN0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void CAN1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void USB_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void USB_SOF_HSOF_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void USB_TRCPT0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void USB_TRCPT1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void GMAC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void TCC0_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void TCC0_MC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void TCC0_MC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void TCC0_MC2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void TCC0_MC3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void TCC0_MC4_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void TCC0_MC5_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void TCC1_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void TCC1_MC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void TCC1_MC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void TCC1_MC2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void TCC1_MC3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void TCC2_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void TCC2_MC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void TCC2_MC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void TCC2_MC2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void TCC3_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void TCC3_MC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void TCC3_MC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void TCC4_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void TCC4_MC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void TCC4_MC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void TC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void TC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void TC2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void TC3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void TC4_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void TC5_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void TC6_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void TC7_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void PDEC_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void PDEC_MC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void PDEC_MC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void ADC0_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void ADC0_RESRDY_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void ADC1_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void ADC1_RESRDY_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void AC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void DAC_OTHER_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void DAC_EMPTY_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void DAC_EMPTY_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void DAC_RESRDY_0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void DAC_RESRDY_1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void I2S_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void PCC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void AES_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void TRNG_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void ICM_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void PUKCC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void QSPI_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void SDHC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void SDHC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); - -/* Exception Table */ -__attribute__ ((section(".vectors"))) -const DeviceVectors exception_table = { - - /* Configure Initial Stack Pointer, using linker-generated symbols */ - .pvStack = (void*) (&_estack), - - .pfnReset_Handler = (void*) Reset_Handler, - .pfnNonMaskableInt_Handler = (void*) NonMaskableInt_Handler, - .pfnHardFault_Handler = (void*) HardFault_Handler, - .pfnMemoryManagement_Handler = (void*) MemoryManagement_Handler, - .pfnBusFault_Handler = (void*) BusFault_Handler, - .pfnUsageFault_Handler = (void*) UsageFault_Handler, - .pvReservedC9 = (void*) (0UL), /* Reserved */ - .pvReservedC8 = (void*) (0UL), /* Reserved */ - .pvReservedC7 = (void*) (0UL), /* Reserved */ - .pvReservedC6 = (void*) (0UL), /* Reserved */ - .pfnSVCall_Handler = (void*) SVCall_Handler, - .pfnDebugMonitor_Handler = (void*) DebugMonitor_Handler, - .pvReservedC3 = (void*) (0UL), /* Reserved */ - .pfnPendSV_Handler = (void*) PendSV_Handler, - .pfnSysTick_Handler = (void*) SysTick_Handler, - - /* Configurable interrupts */ - .pfnPM_Handler = (void*) PM_Handler, /* 0 Power Manager */ - .pfnMCLK_Handler = (void*) MCLK_Handler, /* 1 Main Clock */ - .pfnOSCCTRL_XOSC0_Handler = (void*) OSCCTRL_XOSC0_Handler, /* 2 Oscillators Control */ - .pfnOSCCTRL_XOSC1_Handler = (void*) OSCCTRL_XOSC1_Handler, /* 3 Oscillators Control */ - .pfnOSCCTRL_DFLL_Handler = (void*) OSCCTRL_DFLL_Handler, /* 4 Oscillators Control */ - .pfnOSCCTRL_DPLL0_Handler = (void*) OSCCTRL_DPLL0_Handler, /* 5 Oscillators Control */ - .pfnOSCCTRL_DPLL1_Handler = (void*) OSCCTRL_DPLL1_Handler, /* 6 Oscillators Control */ - .pfnOSC32KCTRL_Handler = (void*) OSC32KCTRL_Handler, /* 7 32kHz Oscillators Control */ - .pfnSUPC_OTHER_Handler = (void*) SUPC_OTHER_Handler, /* 8 Supply Controller */ - .pfnSUPC_BODDET_Handler = (void*) SUPC_BODDET_Handler, /* 9 Supply Controller */ - .pfnWDT_Handler = (void*) WDT_Handler, /* 10 Watchdog Timer */ - .pfnRTC_Handler = (void*) RTC_Handler, /* 11 Real-Time Counter */ - .pfnEIC_EXTINT_0_Handler = (void*) EIC_EXTINT_0_Handler, /* 12 External Interrupt Controller */ - .pfnEIC_EXTINT_1_Handler = (void*) EIC_EXTINT_1_Handler, /* 13 External Interrupt Controller */ - .pfnEIC_EXTINT_2_Handler = (void*) EIC_EXTINT_2_Handler, /* 14 External Interrupt Controller */ - .pfnEIC_EXTINT_3_Handler = (void*) EIC_EXTINT_3_Handler, /* 15 External Interrupt Controller */ - .pfnEIC_EXTINT_4_Handler = (void*) EIC_EXTINT_4_Handler, /* 16 External Interrupt Controller */ - .pfnEIC_EXTINT_5_Handler = (void*) EIC_EXTINT_5_Handler, /* 17 External Interrupt Controller */ - .pfnEIC_EXTINT_6_Handler = (void*) EIC_EXTINT_6_Handler, /* 18 External Interrupt Controller */ - .pfnEIC_EXTINT_7_Handler = (void*) EIC_EXTINT_7_Handler, /* 19 External Interrupt Controller */ - .pfnEIC_EXTINT_8_Handler = (void*) EIC_EXTINT_8_Handler, /* 20 External Interrupt Controller */ - .pfnEIC_EXTINT_9_Handler = (void*) EIC_EXTINT_9_Handler, /* 21 External Interrupt Controller */ - .pfnEIC_EXTINT_10_Handler = (void*) EIC_EXTINT_10_Handler, /* 22 External Interrupt Controller */ - .pfnEIC_EXTINT_11_Handler = (void*) EIC_EXTINT_11_Handler, /* 23 External Interrupt Controller */ - .pfnEIC_EXTINT_12_Handler = (void*) EIC_EXTINT_12_Handler, /* 24 External Interrupt Controller */ - .pfnEIC_EXTINT_13_Handler = (void*) EIC_EXTINT_13_Handler, /* 25 External Interrupt Controller */ - .pfnEIC_EXTINT_14_Handler = (void*) EIC_EXTINT_14_Handler, /* 26 External Interrupt Controller */ - .pfnEIC_EXTINT_15_Handler = (void*) EIC_EXTINT_15_Handler, /* 27 External Interrupt Controller */ - .pfnFREQM_Handler = (void*) FREQM_Handler, /* 28 Frequency Meter */ - .pfnNVMCTRL_0_Handler = (void*) NVMCTRL_0_Handler, /* 29 Non-Volatile Memory Controller */ - .pfnNVMCTRL_1_Handler = (void*) NVMCTRL_1_Handler, /* 30 Non-Volatile Memory Controller */ - .pfnDMAC_0_Handler = (void*) DMAC_0_Handler, /* 31 Direct Memory Access Controller */ - .pfnDMAC_1_Handler = (void*) DMAC_1_Handler, /* 32 Direct Memory Access Controller */ - .pfnDMAC_2_Handler = (void*) DMAC_2_Handler, /* 33 Direct Memory Access Controller */ - .pfnDMAC_3_Handler = (void*) DMAC_3_Handler, /* 34 Direct Memory Access Controller */ - .pfnDMAC_OTHER_Handler = (void*) DMAC_OTHER_Handler, /* 35 Direct Memory Access Controller */ - .pfnEVSYS_0_Handler = (void*) EVSYS_0_Handler, /* 36 Event System Interface */ - .pfnEVSYS_1_Handler = (void*) EVSYS_1_Handler, /* 37 Event System Interface */ - .pfnEVSYS_2_Handler = (void*) EVSYS_2_Handler, /* 38 Event System Interface */ - .pfnEVSYS_3_Handler = (void*) EVSYS_3_Handler, /* 39 Event System Interface */ - .pfnEVSYS_OTHER_Handler = (void*) EVSYS_OTHER_Handler, /* 40 Event System Interface */ - .pfnPAC_Handler = (void*) PAC_Handler, /* 41 Peripheral Access Controller */ - .pvReserved42 = (void*) (0UL), /* 42 Reserved */ - .pvReserved43 = (void*) (0UL), /* 43 Reserved */ - .pvReserved44 = (void*) (0UL), /* 44 Reserved */ - .pfnRAMECC_Handler = (void*) RAMECC_Handler, /* 45 RAM ECC */ - .pfnSERCOM0_0_Handler = (void*) SERCOM0_0_Handler, /* 46 Serial Communication Interface */ - .pfnSERCOM0_1_Handler = (void*) SERCOM0_1_Handler, /* 47 Serial Communication Interface */ - .pfnSERCOM0_2_Handler = (void*) SERCOM0_2_Handler, /* 48 Serial Communication Interface */ - .pfnSERCOM0_OTHER_Handler = (void*) SERCOM0_OTHER_Handler, /* 49 Serial Communication Interface */ - .pfnSERCOM1_0_Handler = (void*) SERCOM1_0_Handler, /* 50 Serial Communication Interface */ - .pfnSERCOM1_1_Handler = (void*) SERCOM1_1_Handler, /* 51 Serial Communication Interface */ - .pfnSERCOM1_2_Handler = (void*) SERCOM1_2_Handler, /* 52 Serial Communication Interface */ - .pfnSERCOM1_OTHER_Handler = (void*) SERCOM1_OTHER_Handler, /* 53 Serial Communication Interface */ - .pfnSERCOM2_0_Handler = (void*) SERCOM2_0_Handler, /* 54 Serial Communication Interface */ - .pfnSERCOM2_1_Handler = (void*) SERCOM2_1_Handler, /* 55 Serial Communication Interface */ - .pfnSERCOM2_2_Handler = (void*) SERCOM2_2_Handler, /* 56 Serial Communication Interface */ - .pfnSERCOM2_OTHER_Handler = (void*) SERCOM2_OTHER_Handler, /* 57 Serial Communication Interface */ - .pfnSERCOM3_0_Handler = (void*) SERCOM3_0_Handler, /* 58 Serial Communication Interface */ - .pfnSERCOM3_1_Handler = (void*) SERCOM3_1_Handler, /* 59 Serial Communication Interface */ - .pfnSERCOM3_2_Handler = (void*) SERCOM3_2_Handler, /* 60 Serial Communication Interface */ - .pfnSERCOM3_OTHER_Handler = (void*) SERCOM3_OTHER_Handler, /* 61 Serial Communication Interface */ - .pfnSERCOM4_0_Handler = (void*) SERCOM4_0_Handler, /* 62 Serial Communication Interface */ - .pfnSERCOM4_1_Handler = (void*) SERCOM4_1_Handler, /* 63 Serial Communication Interface */ - .pfnSERCOM4_2_Handler = (void*) SERCOM4_2_Handler, /* 64 Serial Communication Interface */ - .pfnSERCOM4_OTHER_Handler = (void*) SERCOM4_OTHER_Handler, /* 65 Serial Communication Interface */ - .pfnSERCOM5_0_Handler = (void*) SERCOM5_0_Handler, /* 66 Serial Communication Interface */ - .pfnSERCOM5_1_Handler = (void*) SERCOM5_1_Handler, /* 67 Serial Communication Interface */ - .pfnSERCOM5_2_Handler = (void*) SERCOM5_2_Handler, /* 68 Serial Communication Interface */ - .pfnSERCOM5_OTHER_Handler = (void*) SERCOM5_OTHER_Handler, /* 69 Serial Communication Interface */ - .pfnSERCOM6_0_Handler = (void*) SERCOM6_0_Handler, /* 70 Serial Communication Interface */ - .pfnSERCOM6_1_Handler = (void*) SERCOM6_1_Handler, /* 71 Serial Communication Interface */ - .pfnSERCOM6_2_Handler = (void*) SERCOM6_2_Handler, /* 72 Serial Communication Interface */ - .pfnSERCOM6_OTHER_Handler = (void*) SERCOM6_OTHER_Handler, /* 73 Serial Communication Interface */ - .pfnSERCOM7_0_Handler = (void*) SERCOM7_0_Handler, /* 74 Serial Communication Interface */ - .pfnSERCOM7_1_Handler = (void*) SERCOM7_1_Handler, /* 75 Serial Communication Interface */ - .pfnSERCOM7_2_Handler = (void*) SERCOM7_2_Handler, /* 76 Serial Communication Interface */ - .pfnSERCOM7_OTHER_Handler = (void*) SERCOM7_OTHER_Handler, /* 77 Serial Communication Interface */ - .pfnCAN0_Handler = (void*) CAN0_Handler, /* 78 Control Area Network */ - .pfnCAN1_Handler = (void*) CAN1_Handler, /* 79 Control Area Network */ - .pfnUSB_OTHER_Handler = (void*) USB_OTHER_Handler, /* 80 Universal Serial Bus */ - .pfnUSB_SOF_HSOF_Handler = (void*) USB_SOF_HSOF_Handler, /* 81 Universal Serial Bus */ - .pfnUSB_TRCPT0_Handler = (void*) USB_TRCPT0_Handler, /* 82 Universal Serial Bus */ - .pfnUSB_TRCPT1_Handler = (void*) USB_TRCPT1_Handler, /* 83 Universal Serial Bus */ - .pfnGMAC_Handler = (void*) GMAC_Handler, /* 84 Ethernet MAC */ - .pfnTCC0_OTHER_Handler = (void*) TCC0_OTHER_Handler, /* 85 Timer Counter Control */ - .pfnTCC0_MC0_Handler = (void*) TCC0_MC0_Handler, /* 86 Timer Counter Control */ - .pfnTCC0_MC1_Handler = (void*) TCC0_MC1_Handler, /* 87 Timer Counter Control */ - .pfnTCC0_MC2_Handler = (void*) TCC0_MC2_Handler, /* 88 Timer Counter Control */ - .pfnTCC0_MC3_Handler = (void*) TCC0_MC3_Handler, /* 89 Timer Counter Control */ - .pfnTCC0_MC4_Handler = (void*) TCC0_MC4_Handler, /* 90 Timer Counter Control */ - .pfnTCC0_MC5_Handler = (void*) TCC0_MC5_Handler, /* 91 Timer Counter Control */ - .pfnTCC1_OTHER_Handler = (void*) TCC1_OTHER_Handler, /* 92 Timer Counter Control */ - .pfnTCC1_MC0_Handler = (void*) TCC1_MC0_Handler, /* 93 Timer Counter Control */ - .pfnTCC1_MC1_Handler = (void*) TCC1_MC1_Handler, /* 94 Timer Counter Control */ - .pfnTCC1_MC2_Handler = (void*) TCC1_MC2_Handler, /* 95 Timer Counter Control */ - .pfnTCC1_MC3_Handler = (void*) TCC1_MC3_Handler, /* 96 Timer Counter Control */ - .pfnTCC2_OTHER_Handler = (void*) TCC2_OTHER_Handler, /* 97 Timer Counter Control */ - .pfnTCC2_MC0_Handler = (void*) TCC2_MC0_Handler, /* 98 Timer Counter Control */ - .pfnTCC2_MC1_Handler = (void*) TCC2_MC1_Handler, /* 99 Timer Counter Control */ - .pfnTCC2_MC2_Handler = (void*) TCC2_MC2_Handler, /* 100 Timer Counter Control */ - .pfnTCC3_OTHER_Handler = (void*) TCC3_OTHER_Handler, /* 101 Timer Counter Control */ - .pfnTCC3_MC0_Handler = (void*) TCC3_MC0_Handler, /* 102 Timer Counter Control */ - .pfnTCC3_MC1_Handler = (void*) TCC3_MC1_Handler, /* 103 Timer Counter Control */ - .pfnTCC4_OTHER_Handler = (void*) TCC4_OTHER_Handler, /* 104 Timer Counter Control */ - .pfnTCC4_MC0_Handler = (void*) TCC4_MC0_Handler, /* 105 Timer Counter Control */ - .pfnTCC4_MC1_Handler = (void*) TCC4_MC1_Handler, /* 106 Timer Counter Control */ - .pfnTC0_Handler = (void*) TC0_Handler, /* 107 Basic Timer Counter */ - .pfnTC1_Handler = (void*) TC1_Handler, /* 108 Basic Timer Counter */ - .pfnTC2_Handler = (void*) TC2_Handler, /* 109 Basic Timer Counter */ - .pfnTC3_Handler = (void*) TC3_Handler, /* 110 Basic Timer Counter */ - .pfnTC4_Handler = (void*) TC4_Handler, /* 111 Basic Timer Counter */ - .pfnTC5_Handler = (void*) TC5_Handler, /* 112 Basic Timer Counter */ - .pfnTC6_Handler = (void*) TC6_Handler, /* 113 Basic Timer Counter */ - .pfnTC7_Handler = (void*) TC7_Handler, /* 114 Basic Timer Counter */ - .pfnPDEC_OTHER_Handler = (void*) PDEC_OTHER_Handler, /* 115 Quadrature Decodeur */ - .pfnPDEC_MC0_Handler = (void*) PDEC_MC0_Handler, /* 116 Quadrature Decodeur */ - .pfnPDEC_MC1_Handler = (void*) PDEC_MC1_Handler, /* 117 Quadrature Decodeur */ - .pfnADC0_OTHER_Handler = (void*) ADC0_OTHER_Handler, /* 118 Analog Digital Converter */ - .pfnADC0_RESRDY_Handler = (void*) ADC0_RESRDY_Handler, /* 119 Analog Digital Converter */ - .pfnADC1_OTHER_Handler = (void*) ADC1_OTHER_Handler, /* 120 Analog Digital Converter */ - .pfnADC1_RESRDY_Handler = (void*) ADC1_RESRDY_Handler, /* 121 Analog Digital Converter */ - .pfnAC_Handler = (void*) AC_Handler, /* 122 Analog Comparators */ - .pfnDAC_OTHER_Handler = (void*) DAC_OTHER_Handler, /* 123 Digital-to-Analog Converter */ - .pfnDAC_EMPTY_0_Handler = (void*) DAC_EMPTY_0_Handler, /* 124 Digital-to-Analog Converter */ - .pfnDAC_EMPTY_1_Handler = (void*) DAC_EMPTY_1_Handler, /* 125 Digital-to-Analog Converter */ - .pfnDAC_RESRDY_0_Handler = (void*) DAC_RESRDY_0_Handler, /* 126 Digital-to-Analog Converter */ - .pfnDAC_RESRDY_1_Handler = (void*) DAC_RESRDY_1_Handler, /* 127 Digital-to-Analog Converter */ - .pfnI2S_Handler = (void*) I2S_Handler, /* 128 Inter-IC Sound Interface */ - .pfnPCC_Handler = (void*) PCC_Handler, /* 129 Parallel Capture Controller */ - .pfnAES_Handler = (void*) AES_Handler, /* 130 Advanced Encryption Standard */ - .pfnTRNG_Handler = (void*) TRNG_Handler, /* 131 True Random Generator */ - .pfnICM_Handler = (void*) ICM_Handler, /* 132 Integrity Check Monitor */ - .pfnPUKCC_Handler = (void*) PUKCC_Handler, /* 133 PUblic-Key Cryptography Controller */ - .pfnQSPI_Handler = (void*) QSPI_Handler, /* 134 Quad SPI interface */ - .pfnSDHC0_Handler = (void*) SDHC0_Handler, /* 135 SD/MMC Host Controller */ - .pfnSDHC1_Handler = (void*) SDHC1_Handler /* 136 SD/MMC Host Controller */ -}; - -/** - * \brief This is the code that gets called on processor reset. - * To initialize the device, and call the main() routine. - */ -void Reset_Handler(void) -{ - uint32_t *pSrc, *pDest; - - /* Initialize the relocate segment */ - pSrc = &_etext; - pDest = &_srelocate; - - if (pSrc != pDest) { - for (; pDest < &_erelocate;) { - *pDest++ = *pSrc++; - } - } - - /* Clear the zero segment */ - for (pDest = &_szero; pDest < &_ezero;) { - *pDest++ = 0; - } - - /* Set the vector table base address */ - pSrc = (uint32_t *) & _sfixed; - SCB->VTOR = ((uint32_t) pSrc & SCB_VTOR_TBLOFF_Msk); - - /* Initialize the C library */ - __libc_init_array(); - - /* Branch to main function */ - main(); - - /* Infinite loop */ - while (1); -} - -/** - * \brief Default interrupt handler for unused IRQs. - */ -void Dummy_Handler(void) -{ - while (1) { - } -} diff --git a/arch/arm/SAME54/SAME54A/mcu/src/system_same54.c b/arch/arm/SAME54/SAME54A/mcu/src/system_same54.c new file mode 100644 index 00000000..d1d4b885 --- /dev/null +++ b/arch/arm/SAME54/SAME54A/mcu/src/system_same54.c @@ -0,0 +1,64 @@ +/** + * \file + * + * \brief Low-level initialization functions called upon chip startup. + * + * Copyright (c) 2019 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#include "same54.h" + +/** + * Initial system clock frequency. The System RC Oscillator (RCSYS) provides + * the source for the main clock at chip startup. + */ +#define __SYSTEM_CLOCK (48000000) + +uint32_t SystemCoreClock = __SYSTEM_CLOCK;/*!< System Clock Frequency (Core Clock)*/ + +/** + * Initialize the system + * + * @brief Setup the microcontroller system. + * Initialize the System and update the SystemCoreClock variable. + */ +void SystemInit(void) +{ + // Keep the default device state after reset + SystemCoreClock = __SYSTEM_CLOCK; + return; +} + +/** + * Update SystemCoreClock variable + * + * @brief Updates the SystemCoreClock with current core Clock + * retrieved from cpu registers. + */ +void SystemCoreClockUpdate(void) +{ + // Not implemented + SystemCoreClock = __SYSTEM_CLOCK; + return; +} diff --git a/arch/arm/SAME54/SAME54A/mcu/src/system_same54n19a.c b/arch/arm/SAME54/SAME54A/mcu/src/system_same54n19a.c deleted file mode 100644 index 8c074ccb..00000000 --- a/arch/arm/SAME54/SAME54A/mcu/src/system_same54n19a.c +++ /dev/null @@ -1,80 +0,0 @@ -/** - * \file - * - * \brief System configuration file for ATSAME54N19A - * - * Copyright (c) 2020 Microchip Technology Inc. - * - * \license_start - * - * \page License - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \license_stop - * - */ - -#include "same54n19a.h" - -/** \cond 0 */ -/* *INDENT-OFF* */ -#ifdef __cplusplus -extern "C" { -#endif -/* *INDENT-ON* */ -/** \endcond */ - -/** - * Initial system clock frequency. The System RC Oscillator (RCSYS) provides - * the source for the main clock at chip startup. - */ -#define __SYSTEM_CLOCK (48000000) - -uint32_t SystemCoreClock = __SYSTEM_CLOCK; /*!< System Clock Frequency (Core Clock)*/ - -/** - * Initialize the system - * - * \brief Setup the microcontroller system. - * Initialize the System and update the SystemCoreClock variable. - */ -void SystemInit(void) -{ - // Keep the default device state after reset - SystemCoreClock = __SYSTEM_CLOCK; - return; -} - -/** - * Update SystemCoreClock variable - * - * \brief Updates the SystemCoreClock with current core Clock - * retrieved from cpu registers. - */ -void SystemCoreClockUpdate(void) -{ - // Not implemented - SystemCoreClock = __SYSTEM_CLOCK; - return; -} - -/** \cond 0 */ -/* *INDENT-OFF* */ -#ifdef __cplusplus -} -#endif -/* *INDENT-ON* */ -/** \endcond */ diff --git a/arch/arm/SAME54/SAME54A/mcu/src/system_same54n20a.c b/arch/arm/SAME54/SAME54A/mcu/src/system_same54n20a.c deleted file mode 100644 index 77ddcacd..00000000 --- a/arch/arm/SAME54/SAME54A/mcu/src/system_same54n20a.c +++ /dev/null @@ -1,80 +0,0 @@ -/** - * \file - * - * \brief System configuration file for ATSAME54N20A - * - * Copyright (c) 2020 Microchip Technology Inc. - * - * \license_start - * - * \page License - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \license_stop - * - */ - -#include "same54n20a.h" - -/** \cond 0 */ -/* *INDENT-OFF* */ -#ifdef __cplusplus -extern "C" { -#endif -/* *INDENT-ON* */ -/** \endcond */ - -/** - * Initial system clock frequency. The System RC Oscillator (RCSYS) provides - * the source for the main clock at chip startup. - */ -#define __SYSTEM_CLOCK (48000000) - -uint32_t SystemCoreClock = __SYSTEM_CLOCK; /*!< System Clock Frequency (Core Clock)*/ - -/** - * Initialize the system - * - * \brief Setup the microcontroller system. - * Initialize the System and update the SystemCoreClock variable. - */ -void SystemInit(void) -{ - // Keep the default device state after reset - SystemCoreClock = __SYSTEM_CLOCK; - return; -} - -/** - * Update SystemCoreClock variable - * - * \brief Updates the SystemCoreClock with current core Clock - * retrieved from cpu registers. - */ -void SystemCoreClockUpdate(void) -{ - // Not implemented - SystemCoreClock = __SYSTEM_CLOCK; - return; -} - -/** \cond 0 */ -/* *INDENT-OFF* */ -#ifdef __cplusplus -} -#endif -/* *INDENT-ON* */ -/** \endcond */ diff --git a/arch/arm/SAME54/SAME54A/mcu/src/system_same54p19a.c b/arch/arm/SAME54/SAME54A/mcu/src/system_same54p19a.c deleted file mode 100644 index 74babf14..00000000 --- a/arch/arm/SAME54/SAME54A/mcu/src/system_same54p19a.c +++ /dev/null @@ -1,80 +0,0 @@ -/** - * \file - * - * \brief System configuration file for ATSAME54P19A - * - * Copyright (c) 2020 Microchip Technology Inc. - * - * \license_start - * - * \page License - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \license_stop - * - */ - -#include "same54p19a.h" - -/** \cond 0 */ -/* *INDENT-OFF* */ -#ifdef __cplusplus -extern "C" { -#endif -/* *INDENT-ON* */ -/** \endcond */ - -/** - * Initial system clock frequency. The System RC Oscillator (RCSYS) provides - * the source for the main clock at chip startup. - */ -#define __SYSTEM_CLOCK (48000000) - -uint32_t SystemCoreClock = __SYSTEM_CLOCK; /*!< System Clock Frequency (Core Clock)*/ - -/** - * Initialize the system - * - * \brief Setup the microcontroller system. - * Initialize the System and update the SystemCoreClock variable. - */ -void SystemInit(void) -{ - // Keep the default device state after reset - SystemCoreClock = __SYSTEM_CLOCK; - return; -} - -/** - * Update SystemCoreClock variable - * - * \brief Updates the SystemCoreClock with current core Clock - * retrieved from cpu registers. - */ -void SystemCoreClockUpdate(void) -{ - // Not implemented - SystemCoreClock = __SYSTEM_CLOCK; - return; -} - -/** \cond 0 */ -/* *INDENT-OFF* */ -#ifdef __cplusplus -} -#endif -/* *INDENT-ON* */ -/** \endcond */ diff --git a/arch/arm/SAME54/SAME54A/mcu/src/system_same54p20a.c b/arch/arm/SAME54/SAME54A/mcu/src/system_same54p20a.c deleted file mode 100644 index d9161030..00000000 --- a/arch/arm/SAME54/SAME54A/mcu/src/system_same54p20a.c +++ /dev/null @@ -1,80 +0,0 @@ -/** - * \file - * - * \brief System configuration file for ATSAME54P20A - * - * Copyright (c) 2020 Microchip Technology Inc. - * - * \license_start - * - * \page License - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \license_stop - * - */ - -#include "same54p20a.h" - -/** \cond 0 */ -/* *INDENT-OFF* */ -#ifdef __cplusplus -extern "C" { -#endif -/* *INDENT-ON* */ -/** \endcond */ - -/** - * Initial system clock frequency. The System RC Oscillator (RCSYS) provides - * the source for the main clock at chip startup. - */ -#define __SYSTEM_CLOCK (48000000) - -uint32_t SystemCoreClock = __SYSTEM_CLOCK; /*!< System Clock Frequency (Core Clock)*/ - -/** - * Initialize the system - * - * \brief Setup the microcontroller system. - * Initialize the System and update the SystemCoreClock variable. - */ -void SystemInit(void) -{ - // Keep the default device state after reset - SystemCoreClock = __SYSTEM_CLOCK; - return; -} - -/** - * Update SystemCoreClock variable - * - * \brief Updates the SystemCoreClock with current core Clock - * retrieved from cpu registers. - */ -void SystemCoreClockUpdate(void) -{ - // Not implemented - SystemCoreClock = __SYSTEM_CLOCK; - return; -} - -/** \cond 0 */ -/* *INDENT-OFF* */ -#ifdef __cplusplus -} -#endif -/* *INDENT-ON* */ -/** \endcond */ diff --git a/arch/arm/SAME54/SAME54A/scripts/same54p20a.cfg b/arch/arm/SAME54/SAME54A/scripts/same54p20a.cfg index f2d69299..d38dfa0f 100644 --- a/arch/arm/SAME54/SAME54A/scripts/same54p20a.cfg +++ b/arch/arm/SAME54/SAME54A/scripts/same54p20a.cfg @@ -4,7 +4,7 @@ # Transport Select -source [find interface/cmsis-dap.cfg] +source [find interface/jlink.cfg] transport select swd # Chip Information diff --git a/manifest/make-manifest.toml b/manifest/make-manifest.toml index 2ca5860c..ef8b93ab 100644 --- a/manifest/make-manifest.toml +++ b/manifest/make-manifest.toml @@ -275,41 +275,31 @@ OBJS_AS_ARGS = ["$(QUOTE)ESF/mcu/src/startup_samd51p20a.o$(QUOTE)", MCPU = "cortex-m4" FPU = "fpv4-sp-d16" FLOAT_ABI = "hard" +OBJS = ["ESF/mcu/src/startup_same54.o", + "ESF/mcu/src/system_same54.o"] +OBJS_AS_ARGS = ["$(QUOTE)ESF/mcu/src/startup_same54.o$(QUOTE)", + "$(QUOTE)ESF/mcu/src/system_same54.o$(QUOTE)"] +CFLAGS = ["-D$(MCU)", "-mcpu=$(MCPU)"] +ELF_FLAGS = ["-D$(MCU)", "-mcpu=$(MCPU)"] [arch.arm.same54a.same54n19a] MCU = "__SAME54N19A__" LD_SCRIPT = "$(LD_PATH)/same54n19a_flash.ld" -OBJS = ["ESF/mcu/src/startup_same54n19a.o", - "ESF/mcu/src/system_same54n19a.o"] -OBJS_AS_ARGS = ["$(QUOTE)ESF/mcu/src/startup_same54n19a.o$(QUOTE)", - "$(QUOTE)ESF/mcu/src/system_same54n19a.o$(QUOTE)"] [arch.arm.same54a.same54n20a] MCU = "__SAME54N20A__" LD_SCRIPT = "$(LD_PATH)/same54n20a_flash.ld" -OBJS = ["ESF/mcu/src/startup_same54n20a.o", - "ESF/mcu/src/system_same54n20a.o"] -OBJS_AS_ARGS = ["$(QUOTE)ESF/mcu/src/startup_same54n20a.o$(QUOTE)", - "$(QUOTE)ESF/mcu/src/system_same54n20a.o$(QUOTE)"] [arch.arm.same54a.same54p19a] MCU = "__SAME54P19A__" LD_SCRIPT = "$(LD_PATH)/same54p19a_flash.ld" -OBJS = ["ESF/mcu/src/startup_same54p19a.o", - "ESF/mcu/src/system_same54p19a.o"] -OBJS_AS_ARGS = ["$(QUOTE)ESF/mcu/src/startup_same54p19a.o$(QUOTE)", - "$(QUOTE)ESF/mcu/src/system_same54p19a.o$(QUOTE)"] [arch.arm.same54a.same54p20a] MCU = "__SAME54P20A__" LD_SCRIPT = "$(LD_PATH)/same54p20a_flash.ld" -OBJS = ["ESF/mcu/src/startup_same54p20a.o", - "ESF/mcu/src/system_same54p20a.o"] -OBJS_AS_ARGS = ["$(QUOTE)ESF/mcu/src/startup_same54p20a.o$(QUOTE)", - "$(QUOTE)ESF/mcu/src/system_same54p20a.o$(QUOTE)"] [arch.avr] -CC = "arm-none-eabi-gcc" -CXX = "arm-none-eabi-g++" -OBJCOPY = "arm-none-eabi-objcopy" -OBJDUMP = "arm-none-eabi-objdump" -SIZE = "arm-none-eabi-gdb" -AS = "arm-none-eabi-as" +CC = "avr-gcc" +CXX = "avr-g++" +OBJCOPY = "avr-objcopy" +OBJDUMP = "avr-objdump" +SIZE = "avr-size" +AS = "avr-as" [arch.riscv] TOOLCHAIN = "${ESF_DIR}/toolchains/riscv/bin/riscv64-unknown-elf" @@ -339,4 +329,4 @@ LD_SCRIPT = "$(LD_PATH)/fe310g000.ld" MCU = "__FE310G002__" LD_SCRIPT = "$(LD_PATH)/fe310g002.ld" OBJS = ["ESF/mcu/src/startup_fe310.o"] -OBJS_AS_ARGS = ["$(QUOTE)ESF/mcu/src/startup_fe310.o$(QUOTE)"] \ No newline at end of file +OBJS_AS_ARGS = ["$(QUOTE)ESF/mcu/src/startup_fe310.o$(QUOTE)"] diff --git a/scripts/debug.gdb b/scripts/debug.gdb index 0cdae3a3..909796ef 100644 --- a/scripts/debug.gdb +++ b/scripts/debug.gdb @@ -1,6 +1,7 @@ set pagination off set logging file gdb.txt set logging on +set mem inaccessible-by-default off target extended-remote localhost:3333 monitor reset halt load diff --git a/test/same54p20a_test/.dir-locals.el b/test/same54p20a_test/.dir-locals.el new file mode 100644 index 00000000..9878c284 --- /dev/null +++ b/test/same54p20a_test/.dir-locals.el @@ -0,0 +1,8 @@ +((c-mode . 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/storage/Shared/Documents/Projects/ePenguin/ePenguin-Software-Framework/toolchains/arm-none-eabi-toolchain/lib/gcc/arm-none-eabi/6.3.1/include/stdint.h \ + /storage/Shared/Documents/Projects/ePenguin/ePenguin-Software-Framework/toolchains/arm-none-eabi-toolchain/arm-none-eabi/include/stdint.h \ + /storage/Shared/Documents/Projects/ePenguin/ePenguin-Software-Framework/toolchains/arm-none-eabi-toolchain/arm-none-eabi/include/machine/_default_types.h \ + /storage/Shared/Documents/Projects/ePenguin/ePenguin-Software-Framework/toolchains/arm-none-eabi-toolchain/arm-none-eabi/include/sys/features.h \ + /storage/Shared/Documents/Projects/ePenguin/ePenguin-Software-Framework/toolchains/arm-none-eabi-toolchain/arm-none-eabi/include/_newlib_version.h \ + /storage/Shared/Documents/Projects/ePenguin/ePenguin-Software-Framework/toolchains/arm-none-eabi-toolchain/arm-none-eabi/include/sys/_intsup.h \ + /storage/Shared/Documents/Projects/ePenguin/ePenguin-Software-Framework/toolchains/arm-none-eabi-toolchain/arm-none-eabi/include/sys/_stdint.h \ + ../../../ESF/common/inc/cmsis/core_cm4.h \ + ../../../ESF/common/inc/cmsis/cmsis_version.h \ + ../../../ESF/common/inc/cmsis/cmsis_compiler.h \ + ../../../ESF/common/inc/cmsis/cmsis_gcc.h \ + ../../../ESF/common/inc/cmsis/mpu_armv7.h \ + ../../../ESF/mcu/inc/system_same54.h ../../../ESF/mcu/inc/component/ac.h \ + ../../../ESF/mcu/inc/component/adc.h \ + ../../../ESF/mcu/inc/component/aes.h \ + ../../../ESF/mcu/inc/component/can.h \ + ../../../ESF/mcu/inc/component/ccl.h \ + ../../../ESF/mcu/inc/component/cmcc.h \ + ../../../ESF/mcu/inc/component/dac.h \ + ../../../ESF/mcu/inc/component/dmac.h \ + ../../../ESF/mcu/inc/component/dsu.h \ + ../../../ESF/mcu/inc/component/eic.h \ + ../../../ESF/mcu/inc/component/evsys.h \ + ../../../ESF/mcu/inc/component/freqm.h \ + ../../../ESF/mcu/inc/component/gclk.h \ + ../../../ESF/mcu/inc/component/gmac.h \ + ../../../ESF/mcu/inc/component/hmatrixb.h \ + ../../../ESF/mcu/inc/component/icm.h \ + ../../../ESF/mcu/inc/component/i2s.h \ + ../../../ESF/mcu/inc/component/mclk.h \ + ../../../ESF/mcu/inc/component/nvmctrl.h \ + ../../../ESF/mcu/inc/component/oscctrl.h \ + ../../../ESF/mcu/inc/component/osc32kctrl.h \ + ../../../ESF/mcu/inc/component/pac.h \ + ../../../ESF/mcu/inc/component/pcc.h \ + ../../../ESF/mcu/inc/component/pdec.h \ + ../../../ESF/mcu/inc/component/pm.h \ + ../../../ESF/mcu/inc/component/port.h \ + ../../../ESF/mcu/inc/component/qspi.h \ + ../../../ESF/mcu/inc/component/ramecc.h \ + ../../../ESF/mcu/inc/component/rstc.h \ + ../../../ESF/mcu/inc/component/rtc.h \ + ../../../ESF/mcu/inc/component/sdhc.h \ + ../../../ESF/mcu/inc/component/sercom.h \ + ../../../ESF/mcu/inc/component/supc.h \ + ../../../ESF/mcu/inc/component/tc.h ../../../ESF/mcu/inc/component/tcc.h \ + ../../../ESF/mcu/inc/component/trng.h \ + ../../../ESF/mcu/inc/component/usb.h \ + ../../../ESF/mcu/inc/component/wdt.h ../../../ESF/mcu/inc/instance/ac.h \ + ../../../ESF/mcu/inc/instance/adc0.h \ + ../../../ESF/mcu/inc/instance/adc1.h ../../../ESF/mcu/inc/instance/aes.h \ + ../../../ESF/mcu/inc/instance/can0.h \ + ../../../ESF/mcu/inc/instance/can1.h ../../../ESF/mcu/inc/instance/ccl.h \ + ../../../ESF/mcu/inc/instance/cmcc.h ../../../ESF/mcu/inc/instance/dac.h \ + ../../../ESF/mcu/inc/instance/dmac.h ../../../ESF/mcu/inc/instance/dsu.h \ + ../../../ESF/mcu/inc/instance/eic.h \ + ../../../ESF/mcu/inc/instance/evsys.h \ + ../../../ESF/mcu/inc/instance/freqm.h \ + ../../../ESF/mcu/inc/instance/gclk.h \ + ../../../ESF/mcu/inc/instance/gmac.h \ + ../../../ESF/mcu/inc/instance/hmatrix.h \ + ../../../ESF/mcu/inc/instance/icm.h ../../../ESF/mcu/inc/instance/i2s.h \ + ../../../ESF/mcu/inc/instance/mclk.h \ + ../../../ESF/mcu/inc/instance/nvmctrl.h \ + ../../../ESF/mcu/inc/instance/oscctrl.h \ + ../../../ESF/mcu/inc/instance/osc32kctrl.h \ + ../../../ESF/mcu/inc/instance/pac.h ../../../ESF/mcu/inc/instance/pcc.h \ + ../../../ESF/mcu/inc/instance/pdec.h ../../../ESF/mcu/inc/instance/pm.h \ + ../../../ESF/mcu/inc/instance/port.h \ + ../../../ESF/mcu/inc/instance/pukcc.h \ + ../../../ESF/mcu/inc/instance/qspi.h \ + ../../../ESF/mcu/inc/instance/ramecc.h \ + ../../../ESF/mcu/inc/instance/rstc.h ../../../ESF/mcu/inc/instance/rtc.h \ + ../../../ESF/mcu/inc/instance/sdhc0.h \ + ../../../ESF/mcu/inc/instance/sdhc1.h \ + ../../../ESF/mcu/inc/instance/sercom0.h \ + ../../../ESF/mcu/inc/instance/sercom1.h \ + ../../../ESF/mcu/inc/instance/sercom2.h \ + ../../../ESF/mcu/inc/instance/sercom3.h \ + ../../../ESF/mcu/inc/instance/sercom4.h \ + ../../../ESF/mcu/inc/instance/sercom5.h \ + ../../../ESF/mcu/inc/instance/sercom6.h \ + ../../../ESF/mcu/inc/instance/sercom7.h \ + ../../../ESF/mcu/inc/instance/supc.h ../../../ESF/mcu/inc/instance/tc0.h \ + ../../../ESF/mcu/inc/instance/tc1.h ../../../ESF/mcu/inc/instance/tc2.h \ + ../../../ESF/mcu/inc/instance/tc3.h ../../../ESF/mcu/inc/instance/tc4.h \ + ../../../ESF/mcu/inc/instance/tc5.h ../../../ESF/mcu/inc/instance/tc6.h \ + ../../../ESF/mcu/inc/instance/tc7.h ../../../ESF/mcu/inc/instance/tcc0.h \ + ../../../ESF/mcu/inc/instance/tcc1.h \ + ../../../ESF/mcu/inc/instance/tcc2.h \ + ../../../ESF/mcu/inc/instance/tcc3.h \ + ../../../ESF/mcu/inc/instance/tcc4.h \ + ../../../ESF/mcu/inc/instance/trng.h ../../../ESF/mcu/inc/instance/usb.h \ + ../../../ESF/mcu/inc/instance/wdt.h \ + ../../../ESF/mcu/inc/pio/same54p20a.h + +../../../ESF/mcu/inc/same54.h: + +../../../ESF/mcu/inc/same54p20a.h: + +/storage/Shared/Documents/Projects/ePenguin/ePenguin-Software-Framework/toolchains/arm-none-eabi-toolchain/lib/gcc/arm-none-eabi/6.3.1/include/stdint.h: + +/storage/Shared/Documents/Projects/ePenguin/ePenguin-Software-Framework/toolchains/arm-none-eabi-toolchain/arm-none-eabi/include/stdint.h: + +/storage/Shared/Documents/Projects/ePenguin/ePenguin-Software-Framework/toolchains/arm-none-eabi-toolchain/arm-none-eabi/include/machine/_default_types.h: + +/storage/Shared/Documents/Projects/ePenguin/ePenguin-Software-Framework/toolchains/arm-none-eabi-toolchain/arm-none-eabi/include/sys/features.h: + +/storage/Shared/Documents/Projects/ePenguin/ePenguin-Software-Framework/toolchains/arm-none-eabi-toolchain/arm-none-eabi/include/_newlib_version.h: + +/storage/Shared/Documents/Projects/ePenguin/ePenguin-Software-Framework/toolchains/arm-none-eabi-toolchain/arm-none-eabi/include/sys/_intsup.h: + +/storage/Shared/Documents/Projects/ePenguin/ePenguin-Software-Framework/toolchains/arm-none-eabi-toolchain/arm-none-eabi/include/sys/_stdint.h: + +../../../ESF/common/inc/cmsis/core_cm4.h: + +../../../ESF/common/inc/cmsis/cmsis_version.h: + +../../../ESF/common/inc/cmsis/cmsis_compiler.h: + +../../../ESF/common/inc/cmsis/cmsis_gcc.h: + +../../../ESF/common/inc/cmsis/mpu_armv7.h: + +../../../ESF/mcu/inc/system_same54.h: + +../../../ESF/mcu/inc/component/ac.h: + +../../../ESF/mcu/inc/component/adc.h: + +../../../ESF/mcu/inc/component/aes.h: + +../../../ESF/mcu/inc/component/can.h: + +../../../ESF/mcu/inc/component/ccl.h: + +../../../ESF/mcu/inc/component/cmcc.h: + +../../../ESF/mcu/inc/component/dac.h: + +../../../ESF/mcu/inc/component/dmac.h: + +../../../ESF/mcu/inc/component/dsu.h: + +../../../ESF/mcu/inc/component/eic.h: + +../../../ESF/mcu/inc/component/evsys.h: + +../../../ESF/mcu/inc/component/freqm.h: + +../../../ESF/mcu/inc/component/gclk.h: + +../../../ESF/mcu/inc/component/gmac.h: + +../../../ESF/mcu/inc/component/hmatrixb.h: + +../../../ESF/mcu/inc/component/icm.h: + +../../../ESF/mcu/inc/component/i2s.h: + +../../../ESF/mcu/inc/component/mclk.h: + +../../../ESF/mcu/inc/component/nvmctrl.h: + +../../../ESF/mcu/inc/component/oscctrl.h: + +../../../ESF/mcu/inc/component/osc32kctrl.h: + +../../../ESF/mcu/inc/component/pac.h: + +../../../ESF/mcu/inc/component/pcc.h: + +../../../ESF/mcu/inc/component/pdec.h: + +../../../ESF/mcu/inc/component/pm.h: + +../../../ESF/mcu/inc/component/port.h: + +../../../ESF/mcu/inc/component/qspi.h: + +../../../ESF/mcu/inc/component/ramecc.h: + +../../../ESF/mcu/inc/component/rstc.h: + +../../../ESF/mcu/inc/component/rtc.h: + +../../../ESF/mcu/inc/component/sdhc.h: + +../../../ESF/mcu/inc/component/sercom.h: + +../../../ESF/mcu/inc/component/supc.h: + +../../../ESF/mcu/inc/component/tc.h: + +../../../ESF/mcu/inc/component/tcc.h: + +../../../ESF/mcu/inc/component/trng.h: + +../../../ESF/mcu/inc/component/usb.h: + +../../../ESF/mcu/inc/component/wdt.h: + +../../../ESF/mcu/inc/instance/ac.h: + +../../../ESF/mcu/inc/instance/adc0.h: + +../../../ESF/mcu/inc/instance/adc1.h: + +../../../ESF/mcu/inc/instance/aes.h: + +../../../ESF/mcu/inc/instance/can0.h: + +../../../ESF/mcu/inc/instance/can1.h: + +../../../ESF/mcu/inc/instance/ccl.h: + +../../../ESF/mcu/inc/instance/cmcc.h: + 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/storage/Shared/Documents/Projects/ePenguin/ePenguin-Software-Framework/toolchains/arm-none-eabi-toolchain/lib/gcc/arm-none-eabi/6.3.1/include/stdint.h \ + /storage/Shared/Documents/Projects/ePenguin/ePenguin-Software-Framework/toolchains/arm-none-eabi-toolchain/arm-none-eabi/include/stdint.h \ + /storage/Shared/Documents/Projects/ePenguin/ePenguin-Software-Framework/toolchains/arm-none-eabi-toolchain/arm-none-eabi/include/machine/_default_types.h \ + /storage/Shared/Documents/Projects/ePenguin/ePenguin-Software-Framework/toolchains/arm-none-eabi-toolchain/arm-none-eabi/include/sys/features.h \ + /storage/Shared/Documents/Projects/ePenguin/ePenguin-Software-Framework/toolchains/arm-none-eabi-toolchain/arm-none-eabi/include/_newlib_version.h \ + /storage/Shared/Documents/Projects/ePenguin/ePenguin-Software-Framework/toolchains/arm-none-eabi-toolchain/arm-none-eabi/include/sys/_intsup.h \ + /storage/Shared/Documents/Projects/ePenguin/ePenguin-Software-Framework/toolchains/arm-none-eabi-toolchain/arm-none-eabi/include/sys/_stdint.h \ + ../../../ESF/common/inc/cmsis/core_cm4.h \ + ../../../ESF/common/inc/cmsis/cmsis_version.h \ + ../../../ESF/common/inc/cmsis/cmsis_compiler.h \ + ../../../ESF/common/inc/cmsis/cmsis_gcc.h \ + ../../../ESF/common/inc/cmsis/mpu_armv7.h \ + ../../../ESF/mcu/inc/system_same54.h ../../../ESF/mcu/inc/component/ac.h \ + ../../../ESF/mcu/inc/component/adc.h \ + ../../../ESF/mcu/inc/component/aes.h \ + ../../../ESF/mcu/inc/component/can.h \ + ../../../ESF/mcu/inc/component/ccl.h \ + ../../../ESF/mcu/inc/component/cmcc.h \ + ../../../ESF/mcu/inc/component/dac.h \ + ../../../ESF/mcu/inc/component/dmac.h \ + ../../../ESF/mcu/inc/component/dsu.h \ + ../../../ESF/mcu/inc/component/eic.h \ + ../../../ESF/mcu/inc/component/evsys.h \ + ../../../ESF/mcu/inc/component/freqm.h \ + ../../../ESF/mcu/inc/component/gclk.h \ + ../../../ESF/mcu/inc/component/gmac.h \ + ../../../ESF/mcu/inc/component/hmatrixb.h \ + ../../../ESF/mcu/inc/component/icm.h \ + ../../../ESF/mcu/inc/component/i2s.h \ + ../../../ESF/mcu/inc/component/mclk.h \ + ../../../ESF/mcu/inc/component/nvmctrl.h \ + ../../../ESF/mcu/inc/component/oscctrl.h \ + ../../../ESF/mcu/inc/component/osc32kctrl.h \ + ../../../ESF/mcu/inc/component/pac.h \ + ../../../ESF/mcu/inc/component/pcc.h \ + ../../../ESF/mcu/inc/component/pdec.h \ + ../../../ESF/mcu/inc/component/pm.h \ + ../../../ESF/mcu/inc/component/port.h \ + ../../../ESF/mcu/inc/component/qspi.h \ + ../../../ESF/mcu/inc/component/ramecc.h \ + ../../../ESF/mcu/inc/component/rstc.h \ + ../../../ESF/mcu/inc/component/rtc.h \ + ../../../ESF/mcu/inc/component/sdhc.h \ + ../../../ESF/mcu/inc/component/sercom.h \ + ../../../ESF/mcu/inc/component/supc.h \ + ../../../ESF/mcu/inc/component/tc.h ../../../ESF/mcu/inc/component/tcc.h \ + ../../../ESF/mcu/inc/component/trng.h \ + ../../../ESF/mcu/inc/component/usb.h \ + ../../../ESF/mcu/inc/component/wdt.h ../../../ESF/mcu/inc/instance/ac.h \ + ../../../ESF/mcu/inc/instance/adc0.h \ + ../../../ESF/mcu/inc/instance/adc1.h ../../../ESF/mcu/inc/instance/aes.h \ + ../../../ESF/mcu/inc/instance/can0.h \ + ../../../ESF/mcu/inc/instance/can1.h ../../../ESF/mcu/inc/instance/ccl.h \ + ../../../ESF/mcu/inc/instance/cmcc.h ../../../ESF/mcu/inc/instance/dac.h \ + ../../../ESF/mcu/inc/instance/dmac.h ../../../ESF/mcu/inc/instance/dsu.h \ + ../../../ESF/mcu/inc/instance/eic.h \ + ../../../ESF/mcu/inc/instance/evsys.h \ + ../../../ESF/mcu/inc/instance/freqm.h \ + ../../../ESF/mcu/inc/instance/gclk.h \ + ../../../ESF/mcu/inc/instance/gmac.h \ + ../../../ESF/mcu/inc/instance/hmatrix.h \ + ../../../ESF/mcu/inc/instance/icm.h ../../../ESF/mcu/inc/instance/i2s.h \ + ../../../ESF/mcu/inc/instance/mclk.h \ + ../../../ESF/mcu/inc/instance/nvmctrl.h \ + ../../../ESF/mcu/inc/instance/oscctrl.h \ + ../../../ESF/mcu/inc/instance/osc32kctrl.h \ + ../../../ESF/mcu/inc/instance/pac.h ../../../ESF/mcu/inc/instance/pcc.h \ + ../../../ESF/mcu/inc/instance/pdec.h ../../../ESF/mcu/inc/instance/pm.h \ + ../../../ESF/mcu/inc/instance/port.h \ + ../../../ESF/mcu/inc/instance/pukcc.h \ + ../../../ESF/mcu/inc/instance/qspi.h \ + ../../../ESF/mcu/inc/instance/ramecc.h \ + ../../../ESF/mcu/inc/instance/rstc.h ../../../ESF/mcu/inc/instance/rtc.h \ + ../../../ESF/mcu/inc/instance/sdhc0.h \ + ../../../ESF/mcu/inc/instance/sdhc1.h \ + ../../../ESF/mcu/inc/instance/sercom0.h \ + ../../../ESF/mcu/inc/instance/sercom1.h \ + ../../../ESF/mcu/inc/instance/sercom2.h \ + ../../../ESF/mcu/inc/instance/sercom3.h \ + ../../../ESF/mcu/inc/instance/sercom4.h \ + ../../../ESF/mcu/inc/instance/sercom5.h \ + ../../../ESF/mcu/inc/instance/sercom6.h \ + ../../../ESF/mcu/inc/instance/sercom7.h \ + ../../../ESF/mcu/inc/instance/supc.h ../../../ESF/mcu/inc/instance/tc0.h \ + ../../../ESF/mcu/inc/instance/tc1.h ../../../ESF/mcu/inc/instance/tc2.h \ + ../../../ESF/mcu/inc/instance/tc3.h ../../../ESF/mcu/inc/instance/tc4.h \ + ../../../ESF/mcu/inc/instance/tc5.h ../../../ESF/mcu/inc/instance/tc6.h \ + ../../../ESF/mcu/inc/instance/tc7.h ../../../ESF/mcu/inc/instance/tcc0.h \ + ../../../ESF/mcu/inc/instance/tcc1.h \ + ../../../ESF/mcu/inc/instance/tcc2.h \ + ../../../ESF/mcu/inc/instance/tcc3.h \ + ../../../ESF/mcu/inc/instance/tcc4.h \ + ../../../ESF/mcu/inc/instance/trng.h ../../../ESF/mcu/inc/instance/usb.h \ + ../../../ESF/mcu/inc/instance/wdt.h \ + ../../../ESF/mcu/inc/pio/same54p20a.h + +../../../ESF/mcu/inc/same54.h: + +../../../ESF/mcu/inc/same54p20a.h: + +/storage/Shared/Documents/Projects/ePenguin/ePenguin-Software-Framework/toolchains/arm-none-eabi-toolchain/lib/gcc/arm-none-eabi/6.3.1/include/stdint.h: + +/storage/Shared/Documents/Projects/ePenguin/ePenguin-Software-Framework/toolchains/arm-none-eabi-toolchain/arm-none-eabi/include/stdint.h: + +/storage/Shared/Documents/Projects/ePenguin/ePenguin-Software-Framework/toolchains/arm-none-eabi-toolchain/arm-none-eabi/include/machine/_default_types.h: + +/storage/Shared/Documents/Projects/ePenguin/ePenguin-Software-Framework/toolchains/arm-none-eabi-toolchain/arm-none-eabi/include/sys/features.h: + +/storage/Shared/Documents/Projects/ePenguin/ePenguin-Software-Framework/toolchains/arm-none-eabi-toolchain/arm-none-eabi/include/_newlib_version.h: + +/storage/Shared/Documents/Projects/ePenguin/ePenguin-Software-Framework/toolchains/arm-none-eabi-toolchain/arm-none-eabi/include/sys/_intsup.h: + +/storage/Shared/Documents/Projects/ePenguin/ePenguin-Software-Framework/toolchains/arm-none-eabi-toolchain/arm-none-eabi/include/sys/_stdint.h: + +../../../ESF/common/inc/cmsis/core_cm4.h: + +../../../ESF/common/inc/cmsis/cmsis_version.h: + +../../../ESF/common/inc/cmsis/cmsis_compiler.h: + +../../../ESF/common/inc/cmsis/cmsis_gcc.h: + +../../../ESF/common/inc/cmsis/mpu_armv7.h: + +../../../ESF/mcu/inc/system_same54.h: + +../../../ESF/mcu/inc/component/ac.h: + +../../../ESF/mcu/inc/component/adc.h: + +../../../ESF/mcu/inc/component/aes.h: + +../../../ESF/mcu/inc/component/can.h: + +../../../ESF/mcu/inc/component/ccl.h: + +../../../ESF/mcu/inc/component/cmcc.h: + +../../../ESF/mcu/inc/component/dac.h: + +../../../ESF/mcu/inc/component/dmac.h: + +../../../ESF/mcu/inc/component/dsu.h: + +../../../ESF/mcu/inc/component/eic.h: + +../../../ESF/mcu/inc/component/evsys.h: + +../../../ESF/mcu/inc/component/freqm.h: + +../../../ESF/mcu/inc/component/gclk.h: + +../../../ESF/mcu/inc/component/gmac.h: + +../../../ESF/mcu/inc/component/hmatrixb.h: + +../../../ESF/mcu/inc/component/icm.h: + +../../../ESF/mcu/inc/component/i2s.h: + +../../../ESF/mcu/inc/component/mclk.h: + +../../../ESF/mcu/inc/component/nvmctrl.h: + +../../../ESF/mcu/inc/component/oscctrl.h: + +../../../ESF/mcu/inc/component/osc32kctrl.h: + +../../../ESF/mcu/inc/component/pac.h: + +../../../ESF/mcu/inc/component/pcc.h: + +../../../ESF/mcu/inc/component/pdec.h: + +../../../ESF/mcu/inc/component/pm.h: + +../../../ESF/mcu/inc/component/port.h: + +../../../ESF/mcu/inc/component/qspi.h: + +../../../ESF/mcu/inc/component/ramecc.h: + +../../../ESF/mcu/inc/component/rstc.h: + +../../../ESF/mcu/inc/component/rtc.h: + +../../../ESF/mcu/inc/component/sdhc.h: + +../../../ESF/mcu/inc/component/sercom.h: + +../../../ESF/mcu/inc/component/supc.h: + +../../../ESF/mcu/inc/component/tc.h: + +../../../ESF/mcu/inc/component/tcc.h: + +../../../ESF/mcu/inc/component/trng.h: + +../../../ESF/mcu/inc/component/usb.h: + +../../../ESF/mcu/inc/component/wdt.h: + +../../../ESF/mcu/inc/instance/ac.h: + +../../../ESF/mcu/inc/instance/adc0.h: + +../../../ESF/mcu/inc/instance/adc1.h: + +../../../ESF/mcu/inc/instance/aes.h: + +../../../ESF/mcu/inc/instance/can0.h: + +../../../ESF/mcu/inc/instance/can1.h: + +../../../ESF/mcu/inc/instance/ccl.h: + +../../../ESF/mcu/inc/instance/cmcc.h: + +../../../ESF/mcu/inc/instance/dac.h: + +../../../ESF/mcu/inc/instance/dmac.h: + +../../../ESF/mcu/inc/instance/dsu.h: + +../../../ESF/mcu/inc/instance/eic.h: + +../../../ESF/mcu/inc/instance/evsys.h: + +../../../ESF/mcu/inc/instance/freqm.h: + +../../../ESF/mcu/inc/instance/gclk.h: + +../../../ESF/mcu/inc/instance/gmac.h: + +../../../ESF/mcu/inc/instance/hmatrix.h: + +../../../ESF/mcu/inc/instance/icm.h: + +../../../ESF/mcu/inc/instance/i2s.h: + +../../../ESF/mcu/inc/instance/mclk.h: + +../../../ESF/mcu/inc/instance/nvmctrl.h: + +../../../ESF/mcu/inc/instance/oscctrl.h: + +../../../ESF/mcu/inc/instance/osc32kctrl.h: + +../../../ESF/mcu/inc/instance/pac.h: + +../../../ESF/mcu/inc/instance/pcc.h: + +../../../ESF/mcu/inc/instance/pdec.h: + +../../../ESF/mcu/inc/instance/pm.h: + +../../../ESF/mcu/inc/instance/port.h: + +../../../ESF/mcu/inc/instance/pukcc.h: + +../../../ESF/mcu/inc/instance/qspi.h: + +../../../ESF/mcu/inc/instance/ramecc.h: + +../../../ESF/mcu/inc/instance/rstc.h: + +../../../ESF/mcu/inc/instance/rtc.h: + +../../../ESF/mcu/inc/instance/sdhc0.h: + +../../../ESF/mcu/inc/instance/sdhc1.h: + +../../../ESF/mcu/inc/instance/sercom0.h: + +../../../ESF/mcu/inc/instance/sercom1.h: + +../../../ESF/mcu/inc/instance/sercom2.h: + +../../../ESF/mcu/inc/instance/sercom3.h: + +../../../ESF/mcu/inc/instance/sercom4.h: + +../../../ESF/mcu/inc/instance/sercom5.h: + +../../../ESF/mcu/inc/instance/sercom6.h: + +../../../ESF/mcu/inc/instance/sercom7.h: + +../../../ESF/mcu/inc/instance/supc.h: + +../../../ESF/mcu/inc/instance/tc0.h: + +../../../ESF/mcu/inc/instance/tc1.h: + +../../../ESF/mcu/inc/instance/tc2.h: + +../../../ESF/mcu/inc/instance/tc3.h: + +../../../ESF/mcu/inc/instance/tc4.h: + +../../../ESF/mcu/inc/instance/tc5.h: + +../../../ESF/mcu/inc/instance/tc6.h: + +../../../ESF/mcu/inc/instance/tc7.h: + +../../../ESF/mcu/inc/instance/tcc0.h: + +../../../ESF/mcu/inc/instance/tcc1.h: + +../../../ESF/mcu/inc/instance/tcc2.h: + +../../../ESF/mcu/inc/instance/tcc3.h: + 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$(QUOTE)$<$(QUOTE) + @echo Finished building: $< + +%.o: %.s + @echo Building file: $< + @echo ARM/GNU Assembler + $(QUOTE)$(AS)$(QUOTE) $(CFLAGS) -o $(QUOTE)$@$(QUOTE) $(QUOTE)$<$(QUOTE) + @echo Finished building: $< + +%.o: %.S + @echo Building file: $< + @echo ARM/GNU Preprocessing Assembler + $(QUOTE)$(CC)$(QUOTE) $(CFLAGS) -o $(QUOTE)$@$(QUOTE) $(QUOTE)$<$(QUOTE) + @echo Finished building: $< + + +$(SUB_DIRS): + $(MK_DIR) $(QUOTE)$@$(QUOTE) + +ifneq ($(MAKECMDGOALS),clean) +ifneq ($(strip $(DEPS)),) +-include $(DEPS) +endif +endif + +clean: + @rm -f $(PROJECT_NAME).a + @rm -f $(PROJECT_NAME).lss + @rm -f $(PROJECT_NAME).srec + @rm -f $(PROJECT_NAME).map + @rm -f $(PROJECT_NAME).eep + @rm -f $(OBJS_AS_ARGS) + @rm -f $(DEPS_AS_ARGS) + @rm -f $(PROJECT_NAME).bin + @rm -f $(PROJECT_NAME).elf + @rm -f $(PROJECT_NAME).hex + + +debug:\ +all + @$(GDB) $(PROJECT_NAME).elf -x $(QUOTE)scripts/bmdebug.gdb$(QUOTE) + + +push:\ +all + @echo $(QUOTE)$(QUOTE) + @echo $(QUOTE)Uploading $(PROJECT_NAME).elf...$(QUOTE) + @$(GDB) $(PROJECT_NAME).elf -x $(QUOTE)scripts/bmpush.gdb$(QUOTE) >/dev/null + @echo $(QUOTE)$(QUOTE)$(PROJECT_NAME).elf $(QUOTE) uploaded!$(QUOTE) + @$(QUOTE)$(SIZE)$(QUOTE) $(QUOTE)$(PROJECT_NAME).elf$(QUOTE) + + +QUOTE:=" diff --git a/test/same54p20a_test/.igloo/target/same54p20a/compile_commands.json b/test/same54p20a_test/.igloo/target/same54p20a/compile_commands.json new file mode 100644 index 00000000..48c9dc60 --- /dev/null +++ b/test/same54p20a_test/.igloo/target/same54p20a/compile_commands.json @@ -0,0 +1,152 @@ +[ + { + "arguments": [ + "/storage/Shared/Documents/Projects/ePenguin/ePenguin-Software-Framework/toolchains/arm-none-eabi-toolchain/bin/arm-none-eabi-gcc", + "-D__SAME54P20A__", + "-mcpu=cortex-m4", + "-x", + "c", + "-DDEBUG", + "-Os", + "-g3", + "-Wall", + "-c", + "-std=gnu99", + "-I../../../ESF/common/inc", + "-I../../../ESF/common/inc/cmsis", + "-I../../../ESF/modules", + "-I../../../ESF/modules/clocks", + "-I../../../ESF/modules/usart", + "-I../../../ESF/mcu/inc", + "-I../../../cfg", + "-I../../../inc", + "-MTESF/mcu/src/startup_same54.o", + "-o", + "ESF/mcu/src/startup_same54.o", + "../../../ESF/mcu/src/startup_same54.c" + ], + "directory": "/storage/Shared/Documents/Projects/ePenguin/ePenguin-Software-Framework/test/same54p20a_test/.igloo/target/same54p20a", + "file": "/storage/Shared/Documents/Projects/ePenguin/ePenguin-Software-Framework/test/same54p20a_test/.igloo/target/same54p20a/../../../ESF/mcu/src/startup_same54.c", + "output": "/storage/Shared/Documents/Projects/ePenguin/ePenguin-Software-Framework/test/same54p20a_test/.igloo/target/same54p20a/ESF/mcu/src/startup_same54.o" + }, + { + "arguments": [ + "/storage/Shared/Documents/Projects/ePenguin/ePenguin-Software-Framework/toolchains/arm-none-eabi-toolchain/bin/arm-none-eabi-gcc", + "-D__SAME54P20A__", + "-mcpu=cortex-m4", + "-x", + "c", + "-DDEBUG", + "-Os", + "-g3", + "-Wall", + "-c", + "-std=gnu99", + "-I../../../ESF/common/inc", + "-I../../../ESF/common/inc/cmsis", + "-I../../../ESF/modules", + "-I../../../ESF/modules/clocks", + "-I../../../ESF/modules/usart", + "-I../../../ESF/mcu/inc", + "-I../../../cfg", + "-I../../../inc", + "-MTESF/modules/core/clocks.o", + "-o", + "ESF/modules/core/clocks.o", + "../../../ESF/modules/core/clocks.c" + ], + "directory": "/storage/Shared/Documents/Projects/ePenguin/ePenguin-Software-Framework/test/same54p20a_test/.igloo/target/same54p20a", + "file": "/storage/Shared/Documents/Projects/ePenguin/ePenguin-Software-Framework/test/same54p20a_test/.igloo/target/same54p20a/../../../ESF/modules/core/clocks.c", + "output": "/storage/Shared/Documents/Projects/ePenguin/ePenguin-Software-Framework/test/same54p20a_test/.igloo/target/same54p20a/ESF/modules/core/clocks.o" + }, + { + "arguments": [ + "/storage/Shared/Documents/Projects/ePenguin/ePenguin-Software-Framework/toolchains/arm-none-eabi-toolchain/bin/arm-none-eabi-gcc", + "-D__SAME54P20A__", + "-mcpu=cortex-m4", + "-x", + "c", + "-DDEBUG", + "-Os", + "-g3", + "-Wall", + "-c", + "-std=gnu99", + "-I../../../ESF/common/inc", + "-I../../../ESF/common/inc/cmsis", + "-I../../../ESF/modules", + "-I../../../ESF/modules/clocks", + "-I../../../ESF/modules/usart", + "-I../../../ESF/mcu/inc", + "-I../../../cfg", + "-I../../../inc", + "-MTESF/mcu/src/system_same54.o", + "-o", + "ESF/mcu/src/system_same54.o", + "../../../ESF/mcu/src/system_same54.c" + ], + "directory": "/storage/Shared/Documents/Projects/ePenguin/ePenguin-Software-Framework/test/same54p20a_test/.igloo/target/same54p20a", + "file": "/storage/Shared/Documents/Projects/ePenguin/ePenguin-Software-Framework/test/same54p20a_test/.igloo/target/same54p20a/../../../ESF/mcu/src/system_same54.c", + "output": "/storage/Shared/Documents/Projects/ePenguin/ePenguin-Software-Framework/test/same54p20a_test/.igloo/target/same54p20a/ESF/mcu/src/system_same54.o" + }, + { + "arguments": [ + "/storage/Shared/Documents/Projects/ePenguin/ePenguin-Software-Framework/toolchains/arm-none-eabi-toolchain/bin/arm-none-eabi-gcc", + "-D__SAME54P20A__", + "-mcpu=cortex-m4", + "-x", + "c", + "-DDEBUG", + "-Os", + "-g3", + "-Wall", + "-c", + "-std=gnu99", + "-I../../../ESF/common/inc", + "-I../../../ESF/common/inc/cmsis", + "-I../../../ESF/modules", + "-I../../../ESF/modules/clocks", + "-I../../../ESF/modules/usart", + "-I../../../ESF/mcu/inc", + "-I../../../cfg", + "-I../../../inc", + "-MTESF/modules/usart/usart.o", + "-o", + "ESF/modules/usart/usart.o", + "../../../ESF/modules/usart/usart.c" + ], + "directory": "/storage/Shared/Documents/Projects/ePenguin/ePenguin-Software-Framework/test/same54p20a_test/.igloo/target/same54p20a", + "file": "/storage/Shared/Documents/Projects/ePenguin/ePenguin-Software-Framework/test/same54p20a_test/.igloo/target/same54p20a/../../../ESF/modules/usart/usart.c", + "output": "/storage/Shared/Documents/Projects/ePenguin/ePenguin-Software-Framework/test/same54p20a_test/.igloo/target/same54p20a/ESF/modules/usart/usart.o" + }, + { + "arguments": [ + "/storage/Shared/Documents/Projects/ePenguin/ePenguin-Software-Framework/toolchains/arm-none-eabi-toolchain/bin/arm-none-eabi-gcc", + "-D__SAME54P20A__", + "-mcpu=cortex-m4", + "-x", + "c", + "-DDEBUG", + "-Os", + "-g3", + "-Wall", + "-c", + "-std=gnu99", + "-I../../../ESF/common/inc", + "-I../../../ESF/common/inc/cmsis", + "-I../../../ESF/modules", + "-I../../../ESF/modules/clocks", + "-I../../../ESF/modules/usart", + "-I../../../ESF/mcu/inc", + "-I../../../cfg", + "-I../../../inc", + "-MTsrc/main.o", + "-o", + "src/main.o", + "../../../src/main.c" + ], + "directory": "/storage/Shared/Documents/Projects/ePenguin/ePenguin-Software-Framework/test/same54p20a_test/.igloo/target/same54p20a", + "file": "/storage/Shared/Documents/Projects/ePenguin/ePenguin-Software-Framework/test/same54p20a_test/.igloo/target/same54p20a/../../../src/main.c", + "output": "/storage/Shared/Documents/Projects/ePenguin/ePenguin-Software-Framework/test/same54p20a_test/.igloo/target/same54p20a/src/main.o" + } +] diff --git a/test/same54p20a_test/.igloo/target/same54p20a/gdb.txt b/test/same54p20a_test/.igloo/target/same54p20a/gdb.txt new file mode 100644 index 00000000..91ca98b9 --- /dev/null +++ b/test/same54p20a_test/.igloo/target/same54p20a/gdb.txt @@ -0,0 +1,2338 @@ +Target voltage: 3.3V +Available Targets: +No. Att Driver + 1 Microchip SAME54N19A (rev A) M3/M4 +Cannot write the dashboard +Traceback (most recent call last): + File "", line 511, in render + File "", line 601, in get_term_size +IOError: [Errno 25] Inappropriate ioctl for device +0x000119d6 in ?? () +Breakpoint 1 at 0x330: file ../../../src/main.c, line 7. +Loading section .text, size 0x39c lma 0x0 +Start address 0x0, load size 924 +Transfer rate: 18 KB/sec, 924 bytes/write. +Traceback (most recent call last): + File "", line 417, in on_continue + File "", line 601, in get_term_size +IOError: [Errno 25] Inappropriate ioctl for device +Note: automatically using hardware breakpoints for read-only addresses. +Cannot write the dashboard +Traceback (most recent call last): + File "", line 511, in render + File "", line 601, in get_term_size +IOError: [Errno 25] Inappropriate ioctl for device + +Breakpoint 1, main () at ../../../src/main.c:7 +7 } +Target voltage: 3.3V +Available Targets: +No. Att Driver + 1 Microchip SAME54N19A (rev A) M3/M4 +─── Assembly ──────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── + 0x000002e8 Reset_Handler+22 ldr r2, [pc, #60] ; (0x328 ) + 0x000002ea Reset_Handler+24 bic.w r3, r3, #127 ; 0x7f + 0x000002ee Reset_Handler+28 str r3, [r2, #8] + 0x000002f0 Reset_Handler+30 bl 0x334 <__libc_init_array> + 0x000002f4 Reset_Handler+34 bl 0x330

 + 0x000002f8 Reset_Handler+38 b.n 0x2f8  + 0x000002fa Reset_Handler+40 ldr r1, [pc, #48] ; (0x32c ) + 0x000002fc Reset_Handler+42 subs r2, #4 + 0x000002fe Reset_Handler+44 cmp r3, r1 + 0x00000300 Reset_Handler+46 bcs.n 0x2dc +─── Breakpoints ───────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +─── Expressions ───────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +─── History ───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +─── Memory ────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +─── Registers ─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── + r0 0x00000000 r1 0x00000000 r2 0xe000ed00 r3 0x00000000 r4 0x000119d5 r5 0x20008abc + r6 0x200059d8 r7 0x000125c1 r8 0x000125b5 r9 0x200059d8 r10 0x20005a48 r11 0x2000db94 + r12 0x00000000 sp 0x20010018 lr 0x000002f9 pc 0x000002f8 xpsr 0x61000000 fpscr 0x00000000 + msp 0x20010018 psp 0xfdff277c primask 0x00 basepri 0x00 faultmask 0x00 control 0x00 +─── Source ────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── + 523 /* Enable FPU */ + 524 SCB->CPACR |= (0xFu << 20); + 525 __DSB(); + 526 __ISB(); + 527 #endif + 528 + 529 /* Initialize the C library */ + 530 __libc_init_array(); + 531 + 532 /* Branch to main function */ + 533 main();  + 534 + 535 /* Infinite loop */ + 536 while (1); + 537 } + 538 + 539 /** + 540 * \brief Default interrupt handler for unused IRQs. + 541 */ + 542 void Dummy_Handler(void) +─── Stack ─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +[0] from 0x000002f8 in Reset_Handler+38 at ../../../ESF/mcu/src/startup_same54.c:533 +[1] from 0xfffffffe +─── Threads ───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +[1] id 0 from 0x000002f8 in Reset_Handler+38 at ../../../ESF/mcu/src/startup_same54.c:533 +─── Variables ─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +loc pDest = +───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +0x000002f8 in Reset_Handler () at ../../../ESF/mcu/src/startup_same54.c:533 +533 main(); +Breakpoint 1 at 0x330: file ../../../src/main.c, line 7. +Loading section .text, size 0x39c lma 0x0 +Start address 0x0, load size 924 +Transfer rate: 17 KB/sec, 924 bytes/write. +─── Output/messages ───────────────────────────────────────────────────────────────────────────────────────────────────────────────── +Note: automatically using hardware breakpoints for read-only addresses. +─── Assembly ──────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +~ +~ +~ +~ +~ +!0x00000330 main+0 movs r0, #0 + 0x00000332 main+2 bx lr +~ +~ +~ +─── Breakpoints ───────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +[1] break at 0x00000330 in ../../../src/main.c:7 for main hit 1 time +─── Expressions ───────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +─── History ───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +─── Memory ────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +─── Registers ─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── + r0 0x0000039c r1 0x00000000 r2 0xe000ed00 r3 0x00000000 r4 0x000119d5 r5 0x20008abc + r6 0x200059d8 r7 0x000125c1 r8 0x000125b5 r9 0x200059d8 r10 0x20005a48 r11 0x2000db94 + r12 0x00000000 sp 0x20010018 lr 0x000002f9 pc 0x00000330 xpsr 0x61000000 fpscr 0x00000000 + msp 0x20010018 psp 0xfdff277c primask 0x00 basepri 0x00 faultmask 0x00 control 0x00 +─── Source ────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +~ +~ +~ +~ + 1 #include "igloo.h" + 2 + 3 + 4 int main() + 5 { + 6 return 0; +!7 } +~ +~ +~ +~ +~ +~ +~ +~ +~ +─── Stack ─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +[0] from 0x00000330 in main+0 at ../../../src/main.c:7 +─── Threads ───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +[1] id -1 from 0x00000330 in main+0 at ../../../src/main.c:7 +─── Variables ─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── + +Breakpoint 1, main () at ../../../src/main.c:7 +7 } +Target voltage: 3.3V +Available Targets: +No. Att Driver + 1 Microchip SAME54N19A (rev A) M3/M4 +─── Assembly ──────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── + 0x000002e8 Reset_Handler+22 ldr r2, [pc, #60] ; (0x328 ) + 0x000002ea Reset_Handler+24 bic.w r3, r3, #127 ; 0x7f + 0x000002ee Reset_Handler+28 str r3, [r2, #8] + 0x000002f0 Reset_Handler+30 bl 0x334 <__libc_init_array> + 0x000002f4 Reset_Handler+34 bl 0x330
 + 0x000002f8 Reset_Handler+38 b.n 0x2f8  + 0x000002fa Reset_Handler+40 ldr r1, [pc, #48] ; (0x32c ) + 0x000002fc Reset_Handler+42 subs r2, #4 + 0x000002fe Reset_Handler+44 cmp r3, r1 + 0x00000300 Reset_Handler+46 bcs.n 0x2dc +─── Breakpoints ───────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +─── Expressions ───────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +─── History ───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +─── Memory ────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +─── Registers ─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── + r0 0x00000000 r1 0x00000000 r2 0xe000ed00 r3 0x00000000 r4 0x000119d5 r5 0x20008abc + r6 0x200059d8 r7 0x000125c1 r8 0x000125b5 r9 0x200059d8 r10 0x20005a48 r11 0x2000db94 + r12 0x00000000 sp 0x20010018 lr 0x000002f9 pc 0x000002f8 xpsr 0x61000000 fpscr 0x00000000 + msp 0x20010018 psp 0xfdff277c primask 0x00 basepri 0x00 faultmask 0x00 control 0x00 +─── Source ────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── + 523 /* Enable FPU */ + 524 SCB->CPACR |= (0xFu << 20); + 525 __DSB(); + 526 __ISB(); + 527 #endif + 528 + 529 /* Initialize the C library */ + 530 __libc_init_array(); + 531 + 532 /* Branch to main function */ + 533 main();  + 534 + 535 /* Infinite loop */ + 536 while (1); + 537 } + 538 + 539 /** + 540 * \brief Default interrupt handler for unused IRQs. + 541 */ + 542 void Dummy_Handler(void) +─── Stack ─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +[0] from 0x000002f8 in Reset_Handler+38 at ../../../ESF/mcu/src/startup_same54.c:533 +[1] from 0xfffffffe +─── Threads ───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +[1] id 0 from 0x000002f8 in Reset_Handler+38 at ../../../ESF/mcu/src/startup_same54.c:533 +─── Variables ─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +loc pDest = +───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +0x000002f8 in Reset_Handler () at ../../../ESF/mcu/src/startup_same54.c:533 +533 main(); +Breakpoint 1 at 0x332 +Loading section .text, size 0x39c lma 0x0 +Start address 0x0, load size 924 +Transfer rate: 18 KB/sec, 924 bytes/write. +─── Output/messages ───────────────────────────────────────────────────────────────────────────────────────────────────────────────── +Note: automatically using hardware breakpoints for read-only addresses. +─── Assembly ──────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +~ +~ +~ +~ +~ +!0x00000330 main+0 b.n 0x330
 +~ +~ +~ +~ +─── Breakpoints ───────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +[1] break at 0x00000330 in ../../../src/main.c:5 for main hit 1 time +─── Expressions ───────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +─── History ───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +─── Memory ────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +─── Registers ─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── + r0 0x0000039c r1 0x00000000 r2 0xe000ed00 r3 0x00000000 r4 0x000119d5 r5 0x20008abc + r6 0x200059d8 r7 0x000125c1 r8 0x000125b5 r9 0x200059d8 r10 0x20005a48 r11 0x2000db94 + r12 0x00000000 sp 0x20010018 lr 0x000002f9 pc 0x00000330 xpsr 0x61000000 fpscr 0x00000000 + msp 0x20010018 psp 0xfdff277c primask 0x00 basepri 0x00 faultmask 0x00 control 0x00 +─── Source ────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +~ +~ +~ +~ +~ +~ +  1 #include "igloo.h" +  2 +  3 +  4 int main() +! 5 { +  6 for(;;) +  7 { +  8 +  9 } + 10 return 0; + 11 } +~ +~ +~ +─── Stack ─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +[0] from 0x00000330 in main+0 at ../../../src/main.c:5 +─── Threads ───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +[1] id -1 from 0x00000330 in main+0 at ../../../src/main.c:5 +─── Variables ─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── + +Breakpoint 1, main () at ../../../src/main.c:5 +5 { +Target voltage: 3.3V +Available Targets: +No. Att Driver + 1 Microchip SAME54N19A (rev A) M3/M4 +─── Assembly ──────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +~ +~ +~ +~ +~ + 0x00000330 main+0 b.n 0x330
 + 0x00000332 main+2 movs r0, r0 + 0x00000334 main+4 push {r4, r5, r6, lr} + 0x00000336 main+6 ldr r6, [pc, #52] ; (0x36c ) + 0x00000338 main+8 ldr r4, [pc, #52] ; (0x370 <__libc_init_array>) +─── Breakpoints ───────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +─── Expressions ───────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +─── History ───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +─── Memory ────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +─── Registers ─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── + r0 0x0000039c r1 0x00000000 r2 0xe000ed00 r3 0x00000000 r4 0x000119d5 r5 0x20008abc + r6 0x200059d8 r7 0x000125c1 r8 0x000125b5 r9 0x200059d8 r10 0x20005a48 r11 0x2000db94 + r12 0x00000000 sp 0x20010018 lr 0x000002f9 pc 0x00000330 xpsr 0x61000000 fpscr 0x00000000 + msp 0x20010018 psp 0xfdff277c primask 0x00 basepri 0x00 faultmask 0x00 control 0x00 +─── Source ────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +  1 #include "igloo.h" +  2 +  3 +  4 int main() +  5 { +  6 // Run with 12mhz external crystal on XOSC0 +  7 +  8 // Automatic Loop Control +  9 // 0 - disable + 10 // 1 - enable + 11 OSCCTRL->XOSCCTRL[0].bit.ENALC = 1; + 12 // Current Multiplier + 13 // 6 - >24MHz to 48MHz + 14 // 5 - >16MHz to 24MHz + 15 // 4 - >8MHz to 16MHz + 16 // 3 - 8MHz + 17 OSCCTRL->XOSCCTRL[0].bit.IMULT = 4; + 18 // 3 - >24MHz to 48MHz + 19 // 3 - >16MHz to 24MHz + 20 // 3 - >8MHz to 16MHz +─── Stack ─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +[0] from 0x00000330 in main+0 at ../../../src/main.c:11 +─── Threads ───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +[1] id 0 from 0x00000330 in main+0 at ../../../src/main.c:11 +─── Variables ─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +main () at ../../../src/main.c:11 +11 OSCCTRL->XOSCCTRL[0].bit.ENALC = 1; +Breakpoint 1 at 0x330: file ../../../src/main.c, line 11. +Loading section .text, size 0x3d8 lma 0x0 +Start address 0x0, load size 984 +Transfer rate: 19 KB/sec, 984 bytes/write. +─── Output/messages ───────────────────────────────────────────────────────────────────────────────────────────────────────────────── +Note: automatically using hardware breakpoints for read-only addresses. +─── Assembly ──────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +~ +~ +~ +~ +~ +!0x00000330 main+0 b.n 0x330
 + 0x00000332 main+2 movs r0, r0 + 0x00000334 main+4 push {r4, r5, r6, lr} + 0x00000336 main+6 ldr r6, [pc, #52] ; (0x36c ) + 0x00000338 main+8 ldr r4, [pc, #52] ; (0x370 <__libc_init_array>) +─── Breakpoints ───────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +[1] break at 0x00000330 in ../../../src/main.c:11 for main hit 1 time +─── Expressions ───────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +─── History ───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +─── Memory ────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +─── Registers ─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── + r0 0x000003d8 r1 0x00000000 r2 0xe000ed00 r3 0x00000000 r4 0x000119d5 r5 0x20008abc + r6 0x200059d8 r7 0x000125c1 r8 0x000125b5 r9 0x200059d8 r10 0x20005a48 r11 0x2000db94 + r12 0x00000000 sp 0x20010018 lr 0x000002f9 pc 0x00000330 xpsr 0x61000000 fpscr 0x00000000 + msp 0x20010018 psp 0xfdff277c primask 0x00 basepri 0x00 faultmask 0x00 control 0x00 +─── Source ────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +  1 #include "igloo.h" +  2 +  3 +  4 int main() +  5 { +  6 // Run with 12mhz external crystal on XOSC0 +  7 +  8 // Automatic Loop Control +  9 // 0 - disable + 10 // 1 - enable +!11 OSCCTRL->XOSCCTRL[0].bit.ENALC = 1; + 12 // Current Multiplier + 13 // 6 - >24MHz to 48MHz + 14 // 5 - >16MHz to 24MHz + 15 // 4 - >8MHz to 16MHz + 16 // 3 - 8MHz + 17 OSCCTRL->XOSCCTRL[0].bit.IMULT = 4; + 18 // 3 - >24MHz to 48MHz + 19 // 3 - >16MHz to 24MHz + 20 // 3 - >8MHz to 16MHz +─── Stack ─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +[0] from 0x00000330 in main+0 at ../../../src/main.c:11 +─── Threads ───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +[1] id -1 from 0x00000330 in main+0 at ../../../src/main.c:11 +─── Variables ─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── + +Breakpoint 1, main () at ../../../src/main.c:11 +11 OSCCTRL->XOSCCTRL[0].bit.ENALC = 1; +─── Output/messages ───────────────────────────────────────────────────────────────────────────────────────────────────────────────── +─── Assembly ──────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +!0x00000330 main+0  b.n 0x330
+ 0x00000332 main+2  movs r0, r0 + 0x00000334 main+4  push {r4, r5, r6, lr} + 0x00000336 main+6  ldr r6, [pc, #52] ; (0x36c ) + 0x00000338 main+8  ldr r4, [pc, #52] ; (0x370 <__libc_init_array>) + 0x0000033a main+10 subs r4, r4, r6 + 0x0000033c main+12 asrs r4, r4, #2 + 0x0000033e main+14 movs r5, #0 + 0x00000340 main+16 cmp r5, r4 + 0x00000342 main+18 bne.n 0x358  +─── Breakpoints ───────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +[1] break at 0x00000330 in ../../../src/main.c:11 for main hit 1 time +─── Expressions ───────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +─── History ───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +─── Memory ────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +─── Registers ─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── + r0 0x000003d8 r1 0x00000000 r2 0x00008080 r3 0x40001000 r4 0x000119d5 r5 0x20008abc + r6 0x200059d8 r7 0x000125c1 r8 0x000125b5 r9 0x200059d8 r10 0x20005a48 r11 0x2000db94 + r12 0x00000000 sp 0x20010018 lr 0x000002f9 pc 0x0000033a xpsr 0x61000000 fpscr 0x00000000 + msp 0x20010018 psp 0xfdff277c primask 0x00 basepri 0x00 faultmask 0x00 control 0x00 +─── Source ────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +  7 +  8 // Automatic Loop Control +  9 // 0 - disable + 10 // 1 - enable +!11 OSCCTRL->XOSCCTRL[0].bit.ENALC = 1; + 12 // Current Multiplier + 13 // 6 - >24MHz to 48MHz + 14 // 5 - >16MHz to 24MHz + 15 // 4 - >8MHz to 16MHz + 16 // 3 - 8MHz + 17 OSCCTRL->XOSCCTRL[0].bit.IMULT = 4; + 18 // 3 - >24MHz to 48MHz + 19 // 3 - >16MHz to 24MHz + 20 // 3 - >8MHz to 16MHz + 21 // 2 - 8MHz + 22 OSCCTRL->XOSCCTRL[0].bit.IPTAT = 3; + 23 OSCCTRL->XOSCCTRL[0].bit.ONDEMAND = 0; + 24 OSCCTRL->XOSCCTRL[0].bit.XTALEN = 1; + 25 OSCCTRL->XOSCCTRL[0].bit.ENABLE = 1; + 26 +─── Stack ─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +[0] from 0x0000033a in main+10 at ../../../src/main.c:17 +─── Threads ───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +[1] id -1 from 0x0000033a in main+10 at ../../../src/main.c:17 +─── Variables ─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +17 OSCCTRL->XOSCCTRL[0].bit.IMULT = 4; +─── Output/messages ───────────────────────────────────────────────────────────────────────────────────────────────────────────────── +─── Assembly ──────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── + 0x0000033a main+10 subs r4, r4, r6 + 0x0000033c main+12 asrs r4, r4, #2 + 0x0000033e main+14 movs r5, #0 + 0x00000340 main+16 cmp r5, r4 + 0x00000342 main+18 bne.n 0x358 + 0x00000344 main+20 ldr r6, [pc, #44] ; (0x374 <__libc_init_array+4>) + 0x00000346 main+22 ldr r4, [pc, #48] ; (0x378 <__libc_init_array+8>) + 0x00000348 main+24 bl 0x37c <__libc_init_array+12> + 0x0000034c main+28 subs r4, r4, r6 + 0x0000034e main+30 asrs r4, r4, #2 +─── Breakpoints ───────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +[1] break at 0x00000330 in ../../../src/main.c:11 for main hit 1 time +─── Expressions ───────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +─── History ───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +─── Memory ────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +─── Registers ─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── + r0 0x000003d8 r1 0x00000004 r2 0x0000a080 r3 0x40001000 r4 0x000119d5 r5 0x20008abc + r6 0x200059d8 r7 0x000125c1 r8 0x000125b5 r9 0x200059d8 r10 0x20005a48 r11 0x2000db94 + r12 0x00000000 sp 0x20010018 lr 0x000002f9 pc 0x00000344 xpsr 0x21000000 fpscr 0x00000000 + msp 0x20010018 psp 0xfdff277c primask 0x00 basepri 0x00 faultmask 0x00 control 0x00 +─── Source ────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── + 12 // Current Multiplier + 13 // 6 - >24MHz to 48MHz + 14 // 5 - >16MHz to 24MHz + 15 // 4 - >8MHz to 16MHz + 16 // 3 - 8MHz + 17 OSCCTRL->XOSCCTRL[0].bit.IMULT = 4; + 18 // 3 - >24MHz to 48MHz + 19 // 3 - >16MHz to 24MHz + 20 // 3 - >8MHz to 16MHz + 21 // 2 - 8MHz + 22 OSCCTRL->XOSCCTRL[0].bit.IPTAT = 3; + 23 OSCCTRL->XOSCCTRL[0].bit.ONDEMAND = 0; + 24 OSCCTRL->XOSCCTRL[0].bit.XTALEN = 1; + 25 OSCCTRL->XOSCCTRL[0].bit.ENABLE = 1; + 26 + 27 while(0 == OSCCTRL->STATUS.bit.XOSCRDY0); + 28 + 29 + 30 asm volatile("nop"); + 31 for(;;) +─── Stack ─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +[0] from 0x00000344 in main+20 at ../../../src/main.c:22 +─── Threads ───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +[1] id -1 from 0x00000344 in main+20 at ../../../src/main.c:22 +─── Variables ─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +22 OSCCTRL->XOSCCTRL[0].bit.IPTAT = 3; +─── Output/messages ───────────────────────────────────────────────────────────────────────────────────────────────────────────────── +─── Assembly ──────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── + 0x00000340 main+16 cmp r5, r4 + 0x00000342 main+18 bne.n 0x358 + 0x00000344 main+20 ldr r6, [pc, #44] ; (0x374 <__libc_init_array+4>) + 0x00000346 main+22 ldr r4, [pc, #48] ; (0x378 <__libc_init_array+8>) + 0x00000348 main+24 bl 0x37c <__libc_init_array+12> + 0x0000034c main+28 subs r4, r4, r6 + 0x0000034e main+30 asrs r4, r4, #2 + 0x00000350 main+32 movs r5, #0 + 0x00000352 main+34 cmp r5, r4 + 0x00000354 main+36 bne.n 0x362 +─── Breakpoints ───────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +[1] break at 0x00000330 in ../../../src/main.c:11 for main hit 1 time +─── Expressions ───────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +─── History ───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +─── Memory ────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +─── Registers ─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── + r0 0x000003d8 r1 0x00000004 r2 0x0000a680 r3 0x40001000 r4 0x000119d5 r5 0x20008abc + r6 0x200059d8 r7 0x000125c1 r8 0x000125b5 r9 0x200059d8 r10 0x20005a48 r11 0x2000db94 + r12 0x00000000 sp 0x20010018 lr 0x000002f9 pc 0x0000034c xpsr 0x21000000 fpscr 0x00000000 + msp 0x20010018 psp 0xfdff277c primask 0x00 basepri 0x00 faultmask 0x00 control 0x00 +─── Source ────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── + 13 // 6 - >24MHz to 48MHz + 14 // 5 - >16MHz to 24MHz + 15 // 4 - >8MHz to 16MHz + 16 // 3 - 8MHz + 17 OSCCTRL->XOSCCTRL[0].bit.IMULT = 4; + 18 // 3 - >24MHz to 48MHz + 19 // 3 - >16MHz to 24MHz + 20 // 3 - >8MHz to 16MHz + 21 // 2 - 8MHz + 22 OSCCTRL->XOSCCTRL[0].bit.IPTAT = 3; + 23 OSCCTRL->XOSCCTRL[0].bit.ONDEMAND = 0; + 24 OSCCTRL->XOSCCTRL[0].bit.XTALEN = 1; + 25 OSCCTRL->XOSCCTRL[0].bit.ENABLE = 1; + 26 + 27 while(0 == OSCCTRL->STATUS.bit.XOSCRDY0); + 28 + 29 + 30 asm volatile("nop"); + 31 for(;;) + 32 { +─── Stack ─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +[0] from 0x0000034c in main+28 at ../../../src/main.c:23 +─── Threads ───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +[1] id -1 from 0x0000034c in main+28 at ../../../src/main.c:23 +─── Variables ─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +23 OSCCTRL->XOSCCTRL[0].bit.ONDEMAND = 0; +─── Output/messages ───────────────────────────────────────────────────────────────────────────────────────────────────────────────── +─── Assembly ──────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── + 0x00000348 main+24 bl 0x37c <__libc_init_array+12> + 0x0000034c main+28 subs r4, r4, r6 + 0x0000034e main+30 asrs r4, r4, #2 + 0x00000350 main+32 movs r5, #0 + 0x00000352 main+34 cmp r5, r4 + 0x00000354 main+36 bne.n 0x362  + 0x00000356 main+38 pop {r4, r5, r6, pc} + 0x00000358 main+40 ldr.w r3, [r6, r5, lsl #2] + 0x0000035c main+44 blx r3 + 0x0000035e main+46 adds r5, #1 +─── Breakpoints ───────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +[1] break at 0x00000330 in ../../../src/main.c:11 for main hit 1 time +─── Expressions ───────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +─── History ───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +─── Memory ────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +─── Registers ─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── + r0 0x000003d8 r1 0x00000004 r2 0x0000a600 r3 0x40001000 r4 0x000119d5 r5 0x20008abc + r6 0x200059d8 r7 0x000125c1 r8 0x000125b5 r9 0x200059d8 r10 0x20005a48 r11 0x2000db94 + r12 0x00000000 sp 0x20010018 lr 0x000002f9 pc 0x00000354 xpsr 0x21000000 fpscr 0x00000000 + msp 0x20010018 psp 0xfdff277c primask 0x00 basepri 0x00 faultmask 0x00 control 0x00 +─── Source ────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── + 14 // 5 - >16MHz to 24MHz + 15 // 4 - >8MHz to 16MHz + 16 // 3 - 8MHz + 17 OSCCTRL->XOSCCTRL[0].bit.IMULT = 4; + 18 // 3 - >24MHz to 48MHz + 19 // 3 - >16MHz to 24MHz + 20 // 3 - >8MHz to 16MHz + 21 // 2 - 8MHz + 22 OSCCTRL->XOSCCTRL[0].bit.IPTAT = 3; + 23 OSCCTRL->XOSCCTRL[0].bit.ONDEMAND = 0; + 24 OSCCTRL->XOSCCTRL[0].bit.XTALEN = 1; + 25 OSCCTRL->XOSCCTRL[0].bit.ENABLE = 1; + 26 + 27 while(0 == OSCCTRL->STATUS.bit.XOSCRDY0); + 28 + 29 + 30 asm volatile("nop"); + 31 for(;;) + 32 { + 33 +─── Stack ─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +[0] from 0x00000354 in main+36 at ../../../src/main.c:24 +─── Threads ───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +[1] id -1 from 0x00000354 in main+36 at ../../../src/main.c:24 +─── Variables ─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +24 OSCCTRL->XOSCCTRL[0].bit.XTALEN = 1; +─── Output/messages ───────────────────────────────────────────────────────────────────────────────────────────────────────────────── +─── Assembly ──────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── + 0x0000035a main+42 ldr r2, [r3, #20] + 0x0000035c main+44 orr.w r2, r2, #2 + 0x00000360 main+48 str r2, [r3, #20] + 0x00000362 main+50 ldr r2, [r3, #16] + 0x00000364 main+52 lsls r2, r2, #31 + 0x00000366 main+54 bpl.n 0x362 + 0x00000368 main+56 nop + 0x0000036a main+58 b.n 0x36a + 0x0000036c main+60 asrs r0, r0, #32 + 0x0000036e main+62 ands r0, r0 +─── Breakpoints ───────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +[1] break at 0x00000330 in ../../../src/main.c:11 for main hit 1 time +─── Expressions ───────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +─── History ───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +─── Memory ────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +─── Registers ─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── + r0 0x000003d8 r1 0x00000004 r2 0x0000a604 r3 0x40001000 r4 0x000119d5 r5 0x20008abc + r6 0x200059d8 r7 0x000125c1 r8 0x000125b5 r9 0x200059d8 r10 0x20005a48 r11 0x2000db94 + r12 0x00000000 sp 0x20010018 lr 0x000002f9 pc 0x0000035a xpsr 0x21000000 fpscr 0x00000000 + msp 0x20010018 psp 0xfdff277c primask 0x00 basepri 0x00 faultmask 0x00 control 0x00 +─── Source ────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── + 15 // 4 - >8MHz to 16MHz + 16 // 3 - 8MHz + 17 OSCCTRL->XOSCCTRL[0].bit.IMULT = 4; + 18 // 3 - >24MHz to 48MHz + 19 // 3 - >16MHz to 24MHz + 20 // 3 - >8MHz to 16MHz + 21 // 2 - 8MHz + 22 OSCCTRL->XOSCCTRL[0].bit.IPTAT = 3; + 23 OSCCTRL->XOSCCTRL[0].bit.ONDEMAND = 0; + 24 OSCCTRL->XOSCCTRL[0].bit.XTALEN = 1; + 25 OSCCTRL->XOSCCTRL[0].bit.ENABLE = 1; + 26 + 27 while(0 == OSCCTRL->STATUS.bit.XOSCRDY0); + 28 + 29 + 30 asm volatile("nop"); + 31 for(;;) + 32 { + 33 + 34 } +─── Stack ─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +[0] from 0x0000035a in main+42 at ../../../src/main.c:25 +─── Threads ───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +[1] id -1 from 0x0000035a in main+42 at ../../../src/main.c:25 +─── Variables ─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +25 OSCCTRL->XOSCCTRL[0].bit.ENABLE = 1; +─── Output/messages ───────────────────────────────────────────────────────────────────────────────────────────────────────────────── +─── Assembly ──────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── + 0x00000356 main+38 orrs r2, r1 + 0x00000358 main+40 str r2, [r3, #20] + 0x0000035a main+42 ldr r2, [r3, #20] + 0x0000035c main+44 orr.w r2, r2, #2 + 0x00000360 main+48 str r2, [r3, #20] + 0x00000362 main+50 ldr r2, [r3, #16] + 0x00000364 main+52 lsls r2, r2, #31 + 0x00000366 main+54 bpl.n 0x362  + 0x00000368 main+56 nop + 0x0000036a main+58 b.n 0x36a +─── Breakpoints ───────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +[1] break at 0x00000330 in ../../../src/main.c:11 for main hit 1 time +─── Expressions ───────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +─── History ───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +─── Memory ────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +─── Registers ─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── + r0 0x000003d8 r1 0x00000004 r2 0x0000a606 r3 0x40001000 r4 0x000119d5 r5 0x20008abc + r6 0x200059d8 r7 0x000125c1 r8 0x000125b5 r9 0x200059d8 r10 0x20005a48 r11 0x2000db94 + r12 0x00000000 sp 0x20010018 lr 0x000002f9 pc 0x00000362 xpsr 0x21000000 fpscr 0x00000000 + msp 0x20010018 psp 0xfdff277c primask 0x00 basepri 0x00 faultmask 0x00 control 0x00 +─── Source ────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── + 17 OSCCTRL->XOSCCTRL[0].bit.IMULT = 4; + 18 // 3 - >24MHz to 48MHz + 19 // 3 - >16MHz to 24MHz + 20 // 3 - >8MHz to 16MHz + 21 // 2 - 8MHz + 22 OSCCTRL->XOSCCTRL[0].bit.IPTAT = 3; + 23 OSCCTRL->XOSCCTRL[0].bit.ONDEMAND = 0; + 24 OSCCTRL->XOSCCTRL[0].bit.XTALEN = 1; + 25 OSCCTRL->XOSCCTRL[0].bit.ENABLE = 1; + 26 + 27 while(0 == OSCCTRL->STATUS.bit.XOSCRDY0); + 28 + 29 + 30 asm volatile("nop"); + 31 for(;;) + 32 { + 33 + 34 } + 35 return 0; + 36 } +─── Stack ─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +[0] from 0x00000362 in main+50 at ../../../src/main.c:27 +─── Threads ───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +[1] id -1 from 0x00000362 in main+50 at ../../../src/main.c:27 +─── Variables ─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +27 while(0 == OSCCTRL->STATUS.bit.XOSCRDY0); +─── Output/messages ───────────────────────────────────────────────────────────────────────────────────────────────────────────────── +─── Assembly ──────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── + 0x0000035c main+44 orr.w r2, r2, #2 + 0x00000360 main+48 str r2, [r3, #20] + 0x00000362 main+50 ldr r2, [r3, #16] + 0x00000364 main+52 lsls r2, r2, #31 + 0x00000366 main+54 bpl.n 0x362 + 0x00000368 main+56 nop + 0x0000036a main+58 b.n 0x36a  + 0x0000036c main+60 asrs r0, r0, #32 + 0x0000036e main+62 ands r0, r0 +~ +─── Breakpoints ───────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +[1] break at 0x00000330 in ../../../src/main.c:11 for main hit 1 time +─── Expressions ───────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +─── History ───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +─── Memory ────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +─── Registers ─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── + r0 0x000003d8 r1 0x00000004 r2 0x80000000 r3 0x40001000 r4 0x000119d5 r5 0x20008abc + r6 0x200059d8 r7 0x000125c1 r8 0x000125b5 r9 0x200059d8 r10 0x20005a48 r11 0x2000db94 + r12 0x00000000 sp 0x20010018 lr 0x000002f9 pc 0x00000368 xpsr 0x81000000 fpscr 0x00000000 + msp 0x20010018 psp 0xfdff277c primask 0x00 basepri 0x00 faultmask 0x00 control 0x00 +─── Source ────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── + 20 // 3 - >8MHz to 16MHz + 21 // 2 - 8MHz + 22 OSCCTRL->XOSCCTRL[0].bit.IPTAT = 3; + 23 OSCCTRL->XOSCCTRL[0].bit.ONDEMAND = 0; + 24 OSCCTRL->XOSCCTRL[0].bit.XTALEN = 1; + 25 OSCCTRL->XOSCCTRL[0].bit.ENABLE = 1; + 26 + 27 while(0 == OSCCTRL->STATUS.bit.XOSCRDY0); + 28 + 29 + 30 asm volatile("nop"); + 31 for(;;) + 32 { + 33 + 34 } + 35 return 0; + 36 } +~ +~ +~ +─── Stack ─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +[0] from 0x00000368 in main+56 at ../../../src/main.c:30 +─── Threads ───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +[1] id -1 from 0x00000368 in main+56 at ../../../src/main.c:30 +─── Variables ─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +30 asm volatile("nop"); +Cannot access memory at address 0x40001010 +$1 = { + bit = { + XOSCRDY0 = 1, + XOSCRDY1 = 0, + XOSCFAIL0 = 0, + XOSCFAIL1 = 0, + XOSCCKSW0 = 0, + XOSCCKSW1 = 0, + DFLLRDY = 1, + DFLLOOB = 0, + DFLLLCKF = 0, + DFLLLCKC = 0, + DFLLRCS = 0, + DPLL0LCKR = 0, + DPLL0LCKF = 0, + DPLL0TO = 0, + DPLL0LDRTO = 0, + DPLL1LCKR = 0, + DPLL1LCKF = 0, + DPLL1TO = 0, + DPLL1LDRTO = 0 + }, + vec = { + XOSCRDY = 1, + XOSCFAIL = 0, + XOSCCKSW = 0 + }, + reg = 257 +} +$2 = 1 +Target voltage: 3.3V +Available Targets: +No. Att Driver + 1 Microchip SAME54N19A (rev A) M3/M4 +─── Assembly ──────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── + 0x00000360 main+48 str r2, [r3, #20] + 0x00000362 main+50 ldr r2, [r3, #16] + 0x00000364 main+52 lsls r2, r2, #31 + 0x00000366 main+54 bpl.n 0x362 + 0x00000368 main+56 nop + 0x0000036a main+58 b.n 0x36a  + 0x0000036c main+60 asrs r0, r0, #32 + 0x0000036e main+62 ands r0, r0 +~ +~ +─── Breakpoints ───────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +─── Expressions ───────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +─── History ───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +─── Memory ────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +─── Registers ─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── + r0 0x000003d8 r1 0x00000004 r2 0x80000000 r3 0x40001000 r4 0x000119d5 r5 0x20008abc + r6 0x200059d8 r7 0x000125c1 r8 0x000125b5 r9 0x200059d8 r10 0x20005a48 r11 0x2000db94 + r12 0x00000000 sp 0x20010018 lr 0x000002f9 pc 0x0000036a xpsr 0x81000000 fpscr 0x00000000 + msp 0x20010018 psp 0xfdff277c primask 0x00 basepri 0x00 faultmask 0x00 control 0x00 +─── Source ────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── + 20 // 3 - >8MHz to 16MHz + 21 // 2 - 8MHz + 22 OSCCTRL->XOSCCTRL[0].bit.IPTAT = 3; + 23 OSCCTRL->XOSCCTRL[0].bit.ONDEMAND = 0; + 24 OSCCTRL->XOSCCTRL[0].bit.XTALEN = 1; + 25 OSCCTRL->XOSCCTRL[0].bit.ENABLE = 1; + 26 + 27 while(0 == OSCCTRL->STATUS.bit.XOSCRDY0); + 28 + 29 + 30 asm volatile("nop"); + 31 for(;;) + 32 { + 33 + 34 } + 35 return 0; + 36 } +~ +~ +~ +─── Stack ─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +[0] from 0x0000036a in main+58 at ../../../src/main.c:30 +─── Threads ───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +[1] id 0 from 0x0000036a in main+58 at ../../../src/main.c:30 +─── Variables ─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +0x0000036a in main () at ../../../src/main.c:30 +30 asm volatile("nop"); +Breakpoint 1 at 0x330: file ../../../src/main.c, line 11. +Loading section .text, size 0x3d8 lma 0x0 +Start address 0x0, load size 984 +Transfer rate: 19 KB/sec, 984 bytes/write. +─── Output/messages ───────────────────────────────────────────────────────────────────────────────────────────────────────────────── +Note: automatically using hardware breakpoints for read-only addresses. +─── Assembly ──────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +~ +~ +~ +~ +~ +!0x00000330 main+0  ldr r3, [pc, #56] ; (0x36c ) + 0x00000332 main+2  ldr r2, [r3, #20] + 0x00000334 main+4  orr.w r2, r2, #32768 ; 0x8000 + 0x00000338 main+8  str r2, [r3, #20] + 0x0000033a main+10 ldr r2, [r3, #20] +─── Breakpoints ───────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +[1] break at 0x00000330 in ../../../src/main.c:11 for main hit 1 time +─── Expressions ───────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +─── History ───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +─── Memory ────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +─── Registers ─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── + r0 0x000003d8 r1 0x00000000 r2 0xe000ed00 r3 0x00000000 r4 0x000119d5 r5 0x20008abc + r6 0x200059d8 r7 0x000125c1 r8 0x000125b5 r9 0x200059d8 r10 0x20005a48 r11 0x2000db94 + r12 0x00000000 sp 0x20010018 lr 0x000002f9 pc 0x00000330 xpsr 0x61000000 fpscr 0x00000000 + msp 0x20010018 psp 0xfdff277c primask 0x00 basepri 0x00 faultmask 0x00 control 0x00 +─── Source ────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +  1 #include "igloo.h" +  2 +  3 +  4 int main() +  5 { +  6 // Run with 12mhz external crystal on XOSC0 +  7 +  8 // Automatic Loop Control +  9 // 0 - disable + 10 // 1 - enable +!11 OSCCTRL->XOSCCTRL[0].bit.ENALC = 1; + 12 // Current Multiplier + 13 // 6 - >24MHz to 48MHz + 14 // 5 - >16MHz to 24MHz + 15 // 4 - >8MHz to 16MHz + 16 // 3 - 8MHz + 17 OSCCTRL->XOSCCTRL[0].bit.IMULT = 4; + 18 // 3 - >24MHz to 48MHz + 19 // 3 - >16MHz to 24MHz + 20 // 3 - >8MHz to 16MHz +─── Stack ─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +[0] from 0x00000330 in main+0 at ../../../src/main.c:11 +─── Threads ───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +[1] id -1 from 0x00000330 in main+0 at ../../../src/main.c:11 +─── Variables ─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── + +Breakpoint 1, main () at ../../../src/main.c:11 +11 OSCCTRL->XOSCCTRL[0].bit.ENALC = 1; +$1 = (Oscctrl *) 0x40001000 +Cannot access memory at address 0x40001014 +Target voltage: 3.3V +Available Targets: +No. Att Driver + 1 Microchip SAME54N19A (rev A) M3/M4 +─── Assembly ──────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── + 0x00000360 main+48 str r2, [r3, #20] + 0x00000362 main+50 ldr r2, [r3, #16] + 0x00000364 main+52 lsls r2, r2, #31 + 0x00000366 main+54 bpl.n 0x362 + 0x00000368 main+56 nop + 0x0000036a main+58 b.n 0x36a  + 0x0000036c main+60 asrs r0, r0, #32 + 0x0000036e main+62 ands r0, r0 +~ +~ +─── Breakpoints ───────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +─── Expressions ───────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +─── History ───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +─── Memory ────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +─── Registers ─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── + r0 0x000003d8 r1 0x00000004 r2 0x80000000 r3 0x40001000 r4 0x000119d5 r5 0x20008abc + r6 0x200059d8 r7 0x000125c1 r8 0x000125b5 r9 0x200059d8 r10 0x20005a48 r11 0x2000db94 + r12 0x00000000 sp 0x20010018 lr 0x000002f9 pc 0x0000036a xpsr 0x81000000 fpscr 0x00000000 + msp 0x20010018 psp 0xfdff277c primask 0x00 basepri 0x00 faultmask 0x00 control 0x00 +─── Source ────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── + 20 // 3 - >8MHz to 16MHz + 21 // 2 - 8MHz + 22 OSCCTRL->XOSCCTRL[0].bit.IPTAT = 3; + 23 OSCCTRL->XOSCCTRL[0].bit.ONDEMAND = 0; + 24 OSCCTRL->XOSCCTRL[0].bit.XTALEN = 1; + 25 OSCCTRL->XOSCCTRL[0].bit.ENABLE = 1; + 26 + 27 while(0 == OSCCTRL->STATUS.bit.XOSCRDY0); + 28 + 29 + 30 asm volatile("nop"); + 31 for(;;) + 32 { + 33 + 34 } + 35 return 0; + 36 } +~ +~ +~ +─── Stack ─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +[0] from 0x0000036a in main+58 at ../../../src/main.c:30 +─── Threads ───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +[1] id 0 from 0x0000036a in main+58 at ../../../src/main.c:30 +─── Variables ─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +0x0000036a in main () at ../../../src/main.c:30 +30 asm volatile("nop"); +Breakpoint 1 at 0x330: file ../../../src/main.c, line 11. +Loading section .text, size 0x3d8 lma 0x0 +Start address 0x0, load size 984 +Transfer rate: 19 KB/sec, 984 bytes/write. +─── Output/messages ───────────────────────────────────────────────────────────────────────────────────────────────────────────────── +Note: automatically using hardware breakpoints for read-only addresses. +─── Assembly ──────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +~ +~ +~ +~ +~ +!0x00000330 main+0  ldr r3, [pc, #56] ; (0x36c ) + 0x00000332 main+2  ldr r2, [r3, #20] + 0x00000334 main+4  orr.w r2, r2, #32768 ; 0x8000 + 0x00000338 main+8  str r2, [r3, #20] + 0x0000033a main+10 ldr r2, [r3, #20] +─── Breakpoints ───────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +[1] break at 0x00000330 in ../../../src/main.c:11 for main hit 1 time +─── Expressions ───────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +─── History ───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +─── Memory ────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +─── Registers ─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── + r0 0x000003d8 r1 0x00000000 r2 0xe000ed00 r3 0x00000000 r4 0x000119d5 r5 0x20008abc + r6 0x200059d8 r7 0x000125c1 r8 0x000125b5 r9 0x200059d8 r10 0x20005a48 r11 0x2000db94 + r12 0x00000000 sp 0x20010018 lr 0x000002f9 pc 0x00000330 xpsr 0x61000000 fpscr 0x00000000 + msp 0x20010018 psp 0xfdff277c primask 0x00 basepri 0x00 faultmask 0x00 control 0x00 +─── Source ────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +  1 #include "igloo.h" +  2 +  3 +  4 int main() +  5 { +  6 // Run with 12mhz external crystal on XOSC0 +  7 +  8 // Automatic Loop Control +  9 // 0 - disable + 10 // 1 - enable +!11 OSCCTRL->XOSCCTRL[0].bit.ENALC = 1; + 12 // Current Multiplier + 13 // 6 - >24MHz to 48MHz + 14 // 5 - >16MHz to 24MHz + 15 // 4 - >8MHz to 16MHz + 16 // 3 - 8MHz + 17 OSCCTRL->XOSCCTRL[0].bit.IMULT = 4; + 18 // 3 - >24MHz to 48MHz + 19 // 3 - >16MHz to 24MHz + 20 // 3 - >8MHz to 16MHz +─── Stack ─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +[0] from 0x00000330 in main+0 at ../../../src/main.c:11 +─── Threads ───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +[1] id -1 from 0x00000330 in main+0 at ../../../src/main.c:11 +─── Variables ─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── + +Breakpoint 1, main () at ../../../src/main.c:11 +11 OSCCTRL->XOSCCTRL[0].bit.ENALC = 1; +$1 = { + bit = { + ENABLE = 0, + XTALEN = 0, + RUNSTDBY = 0, + ONDEMAND = 1, + LOWBUFGAIN = 0, + IPTAT = 0, + IMULT = 0, + ENALC = 0, + CFDEN = 0, + SWBEN = 0, + STARTUP = 0, + CFDPRESC = 0 + }, + reg = 128 +} +Quit +─── Output/messages ───────────────────────────────────────────────────────────────────────────────────────────────────────────────── +─── Assembly ──────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +~ +!0x00000330 main+0  ldr r3, [pc, #56] ; (0x36c ) + 0x00000332 main+2  ldr r2, [r3, #20] + 0x00000334 main+4  orr.w r2, r2, #32768 ; 0x8000 + 0x00000338 main+8  str r2, [r3, #20] + 0x0000033a main+10 ldr r2, [r3, #20] + 0x0000033c main+12 movs r1, #4 + 0x0000033e main+14 bfi r2, r1, #11, #4 + 0x00000342 main+18 str r2, [r3, #20] + 0x00000344 main+20 ldr r2, [r3, #20] +─── Breakpoints ───────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +[1] break at 0x00000330 in ../../../src/main.c:11 for main hit 1 time +─── Expressions ───────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +─── History ───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +$$0 = {bit = {ENABLE = 0, XTALEN = 0, RUNSTDBY = 0, ONDEMAND = 1, LOWBUFGAIN = 0, IPTAT = 0, IMULT = 0, EN… +─── Memory ────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +─── Registers ─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── + r0 0x000003d8 r1 0x00000000 r2 0x00008080 r3 0x40001000 r4 0x000119d5 r5 0x20008abc + r6 0x200059d8 r7 0x000125c1 r8 0x000125b5 r9 0x200059d8 r10 0x20005a48 r11 0x2000db94 + r12 0x00000000 sp 0x20010018 lr 0x000002f9 pc 0x0000033a xpsr 0x61000000 fpscr 0x00000000 + msp 0x20010018 psp 0xfdff277c primask 0x00 basepri 0x00 faultmask 0x00 control 0x00 +─── Source ────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +  7 +  8 // Automatic Loop Control +  9 // 0 - disable + 10 // 1 - enable +!11 OSCCTRL->XOSCCTRL[0].bit.ENALC = 1; + 12 // Current Multiplier + 13 // 6 - >24MHz to 48MHz + 14 // 5 - >16MHz to 24MHz + 15 // 4 - >8MHz to 16MHz + 16 // 3 - 8MHz + 17 OSCCTRL->XOSCCTRL[0].bit.IMULT = 4; + 18 // 3 - >24MHz to 48MHz + 19 // 3 - >16MHz to 24MHz + 20 // 3 - >8MHz to 16MHz + 21 // 2 - 8MHz + 22 OSCCTRL->XOSCCTRL[0].bit.IPTAT = 3; + 23 OSCCTRL->XOSCCTRL[0].bit.ONDEMAND = 0; + 24 OSCCTRL->XOSCCTRL[0].bit.XTALEN = 1; + 25 OSCCTRL->XOSCCTRL[0].bit.ENABLE = 1; + 26 +─── Stack ─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +[0] from 0x0000033a in main+10 at ../../../src/main.c:17 +─── Threads ───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +[1] id -1 from 0x0000033a in main+10 at ../../../src/main.c:17 +─── Variables ─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +17 OSCCTRL->XOSCCTRL[0].bit.IMULT = 4; +─── Output/messages ───────────────────────────────────────────────────────────────────────────────────────────────────────────────── +─── Assembly ──────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── + 0x00000338 main+8  str r2, [r3, #20] + 0x0000033a main+10 ldr r2, [r3, #20] + 0x0000033c main+12 movs r1, #4 + 0x0000033e main+14 bfi r2, r1, #11, #4 + 0x00000342 main+18 str r2, [r3, #20] + 0x00000344 main+20 ldr r2, [r3, #20] + 0x00000346 main+22 orr.w r2, r2, #1536 ; 0x600 + 0x0000034a main+26 str r2, [r3, #20] + 0x0000034c main+28 ldr r2, [r3, #20] + 0x0000034e main+30 bfc r2, #7, #1 +─── Breakpoints ───────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +[1] break at 0x00000330 in ../../../src/main.c:11 for main hit 1 time +─── Expressions ───────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +─── History ───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +$$0 = {bit = {ENABLE = 0, XTALEN = 0, RUNSTDBY = 0, ONDEMAND = 1, LOWBUFGAIN = 0, IPTAT = 0, IMULT = 0, EN… +─── Memory ────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +─── Registers ─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── + r0 0x000003d8 r1 0x00000004 r2 0x0000a080 r3 0x40001000 r4 0x000119d5 r5 0x20008abc + r6 0x200059d8 r7 0x000125c1 r8 0x000125b5 r9 0x200059d8 r10 0x20005a48 r11 0x2000db94 + r12 0x00000000 sp 0x20010018 lr 0x000002f9 pc 0x00000344 xpsr 0x21000000 fpscr 0x00000000 + msp 0x20010018 psp 0xfdff277c primask 0x00 basepri 0x00 faultmask 0x00 control 0x00 +─── Source ────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── + 12 // Current Multiplier + 13 // 6 - >24MHz to 48MHz + 14 // 5 - >16MHz to 24MHz + 15 // 4 - >8MHz to 16MHz + 16 // 3 - 8MHz + 17 OSCCTRL->XOSCCTRL[0].bit.IMULT = 4; + 18 // 3 - >24MHz to 48MHz + 19 // 3 - >16MHz to 24MHz + 20 // 3 - >8MHz to 16MHz + 21 // 2 - 8MHz + 22 OSCCTRL->XOSCCTRL[0].bit.IPTAT = 3; + 23 OSCCTRL->XOSCCTRL[0].bit.ONDEMAND = 0; + 24 OSCCTRL->XOSCCTRL[0].bit.XTALEN = 1; + 25 OSCCTRL->XOSCCTRL[0].bit.ENABLE = 1; + 26 + 27 while(0 == OSCCTRL->STATUS.bit.XOSCRDY0); + 28 + 29 + 30 asm volatile("nop"); + 31 for(;;) +─── Stack ─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +[0] from 0x00000344 in main+20 at ../../../src/main.c:22 +─── Threads ───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +[1] id -1 from 0x00000344 in main+20 at ../../../src/main.c:22 +─── Variables ─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +22 OSCCTRL->XOSCCTRL[0].bit.IPTAT = 3; +─── Output/messages ───────────────────────────────────────────────────────────────────────────────────────────────────────────────── +─── Assembly ──────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── + 0x0000033e main+14 bfi r2, r1, #11, #4 + 0x00000342 main+18 str r2, [r3, #20] + 0x00000344 main+20 ldr r2, [r3, #20] + 0x00000346 main+22 orr.w r2, r2, #1536 ; 0x600 + 0x0000034a main+26 str r2, [r3, #20] + 0x0000034c main+28 ldr r2, [r3, #20] + 0x0000034e main+30 bfc r2, #7, #1 + 0x00000352 main+34 str r2, [r3, #20] + 0x00000354 main+36 ldr r2, [r3, #20] + 0x00000356 main+38 orrs r2, r1 +─── Breakpoints ───────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +[1] break at 0x00000330 in ../../../src/main.c:11 for main hit 1 time +─── Expressions ───────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +─── History ───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +$$0 = {bit = {ENABLE = 0, XTALEN = 0, RUNSTDBY = 0, ONDEMAND = 1, LOWBUFGAIN = 0, IPTAT = 0, IMULT = 0, EN… +─── Memory ────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +─── Registers ─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── + r0 0x000003d8 r1 0x00000004 r2 0x0000a680 r3 0x40001000 r4 0x000119d5 r5 0x20008abc + r6 0x200059d8 r7 0x000125c1 r8 0x000125b5 r9 0x200059d8 r10 0x20005a48 r11 0x2000db94 + r12 0x00000000 sp 0x20010018 lr 0x000002f9 pc 0x0000034c xpsr 0x21000000 fpscr 0x00000000 + msp 0x20010018 psp 0xfdff277c primask 0x00 basepri 0x00 faultmask 0x00 control 0x00 +─── Source ────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── + 13 // 6 - >24MHz to 48MHz + 14 // 5 - >16MHz to 24MHz + 15 // 4 - >8MHz to 16MHz + 16 // 3 - 8MHz + 17 OSCCTRL->XOSCCTRL[0].bit.IMULT = 4; + 18 // 3 - >24MHz to 48MHz + 19 // 3 - >16MHz to 24MHz + 20 // 3 - >8MHz to 16MHz + 21 // 2 - 8MHz + 22 OSCCTRL->XOSCCTRL[0].bit.IPTAT = 3; + 23 OSCCTRL->XOSCCTRL[0].bit.ONDEMAND = 0; + 24 OSCCTRL->XOSCCTRL[0].bit.XTALEN = 1; + 25 OSCCTRL->XOSCCTRL[0].bit.ENABLE = 1; + 26 + 27 while(0 == OSCCTRL->STATUS.bit.XOSCRDY0); + 28 + 29 + 30 asm volatile("nop"); + 31 for(;;) + 32 { +─── Stack ─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +[0] from 0x0000034c in main+28 at ../../../src/main.c:23 +─── Threads ───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +[1] id -1 from 0x0000034c in main+28 at ../../../src/main.c:23 +─── Variables ─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +23 OSCCTRL->XOSCCTRL[0].bit.ONDEMAND = 0; +─── Output/messages ───────────────────────────────────────────────────────────────────────────────────────────────────────────────── +─── Assembly ──────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── + 0x00000346 main+22 orr.w r2, r2, #1536 ; 0x600 + 0x0000034a main+26 str r2, [r3, #20] + 0x0000034c main+28 ldr r2, [r3, #20] + 0x0000034e main+30 bfc r2, #7, #1 + 0x00000352 main+34 str r2, [r3, #20] + 0x00000354 main+36 ldr r2, [r3, #20] + 0x00000356 main+38 orrs r2, r1 + 0x00000358 main+40 str r2, [r3, #20] + 0x0000035a main+42 ldr r2, [r3, #20] + 0x0000035c main+44 orr.w r2, r2, #2 +─── Breakpoints ───────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +[1] break at 0x00000330 in ../../../src/main.c:11 for main hit 1 time +─── Expressions ───────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +─── History ───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +$$0 = {bit = {ENABLE = 0, XTALEN = 0, RUNSTDBY = 0, ONDEMAND = 1, LOWBUFGAIN = 0, IPTAT = 0, IMULT = 0, EN… +─── Memory ────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +─── Registers ─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── + r0 0x000003d8 r1 0x00000004 r2 0x0000a600 r3 0x40001000 r4 0x000119d5 r5 0x20008abc + r6 0x200059d8 r7 0x000125c1 r8 0x000125b5 r9 0x200059d8 r10 0x20005a48 r11 0x2000db94 + r12 0x00000000 sp 0x20010018 lr 0x000002f9 pc 0x00000354 xpsr 0x21000000 fpscr 0x00000000 + msp 0x20010018 psp 0xfdff277c primask 0x00 basepri 0x00 faultmask 0x00 control 0x00 +─── Source ────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── + 14 // 5 - >16MHz to 24MHz + 15 // 4 - >8MHz to 16MHz + 16 // 3 - 8MHz + 17 OSCCTRL->XOSCCTRL[0].bit.IMULT = 4; + 18 // 3 - >24MHz to 48MHz + 19 // 3 - >16MHz to 24MHz + 20 // 3 - >8MHz to 16MHz + 21 // 2 - 8MHz + 22 OSCCTRL->XOSCCTRL[0].bit.IPTAT = 3; + 23 OSCCTRL->XOSCCTRL[0].bit.ONDEMAND = 0; + 24 OSCCTRL->XOSCCTRL[0].bit.XTALEN = 1; + 25 OSCCTRL->XOSCCTRL[0].bit.ENABLE = 1; + 26 + 27 while(0 == OSCCTRL->STATUS.bit.XOSCRDY0); + 28 + 29 + 30 asm volatile("nop"); + 31 for(;;) + 32 { + 33 +─── Stack ─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +[0] from 0x00000354 in main+36 at ../../../src/main.c:24 +─── Threads ───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +[1] id -1 from 0x00000354 in main+36 at ../../../src/main.c:24 +─── Variables ─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +24 OSCCTRL->XOSCCTRL[0].bit.XTALEN = 1; +─── Output/messages ───────────────────────────────────────────────────────────────────────────────────────────────────────────────── +─── Assembly ──────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── + 0x0000034e main+30 bfc r2, #7, #1 + 0x00000352 main+34 str r2, [r3, #20] + 0x00000354 main+36 ldr r2, [r3, #20] + 0x00000356 main+38 orrs r2, r1 + 0x00000358 main+40 str r2, [r3, #20] + 0x0000035a main+42 ldr r2, [r3, #20] + 0x0000035c main+44 orr.w r2, r2, #2 + 0x00000360 main+48 str r2, [r3, #20] + 0x00000362 main+50 ldr r2, [r3, #16] + 0x00000364 main+52 lsls r2, r2, #31 +─── Breakpoints ───────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +[1] break at 0x00000330 in ../../../src/main.c:11 for main hit 1 time +─── Expressions ───────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +─── History ───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +$$0 = {bit = {ENABLE = 0, XTALEN = 0, RUNSTDBY = 0, ONDEMAND = 1, LOWBUFGAIN = 0, IPTAT = 0, IMULT = 0, EN… +─── Memory ────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +─── Registers ─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── + r0 0x000003d8 r1 0x00000004 r2 0x0000a604 r3 0x40001000 r4 0x000119d5 r5 0x20008abc + r6 0x200059d8 r7 0x000125c1 r8 0x000125b5 r9 0x200059d8 r10 0x20005a48 r11 0x2000db94 + r12 0x00000000 sp 0x20010018 lr 0x000002f9 pc 0x0000035a xpsr 0x21000000 fpscr 0x00000000 + msp 0x20010018 psp 0xfdff277c primask 0x00 basepri 0x00 faultmask 0x00 control 0x00 +─── Source ────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── + 15 // 4 - >8MHz to 16MHz + 16 // 3 - 8MHz + 17 OSCCTRL->XOSCCTRL[0].bit.IMULT = 4; + 18 // 3 - >24MHz to 48MHz + 19 // 3 - >16MHz to 24MHz + 20 // 3 - >8MHz to 16MHz + 21 // 2 - 8MHz + 22 OSCCTRL->XOSCCTRL[0].bit.IPTAT = 3; + 23 OSCCTRL->XOSCCTRL[0].bit.ONDEMAND = 0; + 24 OSCCTRL->XOSCCTRL[0].bit.XTALEN = 1; + 25 OSCCTRL->XOSCCTRL[0].bit.ENABLE = 1; + 26 + 27 while(0 == OSCCTRL->STATUS.bit.XOSCRDY0); + 28 + 29 + 30 asm volatile("nop"); + 31 for(;;) + 32 { + 33 + 34 } +─── Stack ─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +[0] from 0x0000035a in main+42 at ../../../src/main.c:25 +─── Threads ───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +[1] id -1 from 0x0000035a in main+42 at ../../../src/main.c:25 +─── Variables ─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +25 OSCCTRL->XOSCCTRL[0].bit.ENABLE = 1; +─── Output/messages ───────────────────────────────────────────────────────────────────────────────────────────────────────────────── +─── Assembly ──────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── + 0x00000356 main+38 orrs r2, r1 + 0x00000358 main+40 str r2, [r3, #20] + 0x0000035a main+42 ldr r2, [r3, #20] + 0x0000035c main+44 orr.w r2, r2, #2 + 0x00000360 main+48 str r2, [r3, #20] + 0x00000362 main+50 ldr r2, [r3, #16] + 0x00000364 main+52 lsls r2, r2, #31 + 0x00000366 main+54 bpl.n 0x362  + 0x00000368 main+56 nop + 0x0000036a main+58 b.n 0x36a +─── Breakpoints ───────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +[1] break at 0x00000330 in ../../../src/main.c:11 for main hit 1 time +─── Expressions ───────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +─── History ───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +$$0 = {bit = {ENABLE = 0, XTALEN = 0, RUNSTDBY = 0, ONDEMAND = 1, LOWBUFGAIN = 0, IPTAT = 0, IMULT = 0, EN… +─── Memory ────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +─── Registers ─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── + r0 0x000003d8 r1 0x00000004 r2 0x0000a606 r3 0x40001000 r4 0x000119d5 r5 0x20008abc + r6 0x200059d8 r7 0x000125c1 r8 0x000125b5 r9 0x200059d8 r10 0x20005a48 r11 0x2000db94 + r12 0x00000000 sp 0x20010018 lr 0x000002f9 pc 0x00000362 xpsr 0x21000000 fpscr 0x00000000 + msp 0x20010018 psp 0xfdff277c primask 0x00 basepri 0x00 faultmask 0x00 control 0x00 +─── Source ────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── + 17 OSCCTRL->XOSCCTRL[0].bit.IMULT = 4; + 18 // 3 - >24MHz to 48MHz + 19 // 3 - >16MHz to 24MHz + 20 // 3 - >8MHz to 16MHz + 21 // 2 - 8MHz + 22 OSCCTRL->XOSCCTRL[0].bit.IPTAT = 3; + 23 OSCCTRL->XOSCCTRL[0].bit.ONDEMAND = 0; + 24 OSCCTRL->XOSCCTRL[0].bit.XTALEN = 1; + 25 OSCCTRL->XOSCCTRL[0].bit.ENABLE = 1; + 26 + 27 while(0 == OSCCTRL->STATUS.bit.XOSCRDY0); + 28 + 29 + 30 asm volatile("nop"); + 31 for(;;) + 32 { + 33 + 34 } + 35 return 0; + 36 } +─── Stack ─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +[0] from 0x00000362 in main+50 at ../../../src/main.c:27 +─── Threads ───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +[1] id -1 from 0x00000362 in main+50 at ../../../src/main.c:27 +─── Variables ─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +27 while(0 == OSCCTRL->STATUS.bit.XOSCRDY0); +─── Output/messages ───────────────────────────────────────────────────────────────────────────────────────────────────────────────── +─── Assembly ──────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── + 0x0000035c main+44 orr.w r2, r2, #2 + 0x00000360 main+48 str r2, [r3, #20] + 0x00000362 main+50 ldr r2, [r3, #16] + 0x00000364 main+52 lsls r2, r2, #31 + 0x00000366 main+54 bpl.n 0x362 + 0x00000368 main+56 nop + 0x0000036a main+58 b.n 0x36a  + 0x0000036c main+60 asrs r0, r0, #32 + 0x0000036e main+62 ands r0, r0 +~ +─── Breakpoints ───────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +[1] break at 0x00000330 in ../../../src/main.c:11 for main hit 1 time +─── Expressions ───────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +─── History ───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +$$0 = {bit = {ENABLE = 0, XTALEN = 0, RUNSTDBY = 0, ONDEMAND = 1, LOWBUFGAIN = 0, IPTAT = 0, IMULT = 0, EN… +─── Memory ────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +─── Registers ─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── + r0 0x000003d8 r1 0x00000004 r2 0x80000000 r3 0x40001000 r4 0x000119d5 r5 0x20008abc + r6 0x200059d8 r7 0x000125c1 r8 0x000125b5 r9 0x200059d8 r10 0x20005a48 r11 0x2000db94 + r12 0x00000000 sp 0x20010018 lr 0x000002f9 pc 0x00000368 xpsr 0x81000000 fpscr 0x00000000 + msp 0x20010018 psp 0xfdff277c primask 0x00 basepri 0x00 faultmask 0x00 control 0x00 +─── Source ────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── + 20 // 3 - >8MHz to 16MHz + 21 // 2 - 8MHz + 22 OSCCTRL->XOSCCTRL[0].bit.IPTAT = 3; + 23 OSCCTRL->XOSCCTRL[0].bit.ONDEMAND = 0; + 24 OSCCTRL->XOSCCTRL[0].bit.XTALEN = 1; + 25 OSCCTRL->XOSCCTRL[0].bit.ENABLE = 1; + 26 + 27 while(0 == OSCCTRL->STATUS.bit.XOSCRDY0); + 28 + 29 + 30 asm volatile("nop"); + 31 for(;;) + 32 { + 33 + 34 } + 35 return 0; + 36 } +~ +~ +~ +─── Stack ─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +[0] from 0x00000368 in main+56 at ../../../src/main.c:30 +─── Threads ───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +[1] id -1 from 0x00000368 in main+56 at ../../../src/main.c:30 +─── Variables ─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +30 asm volatile("nop"); +$2 = { + bit = { + ENABLE = 1, + XTALEN = 1, + RUNSTDBY = 0, + ONDEMAND = 0, + LOWBUFGAIN = 0, + IPTAT = 3, + IMULT = 4, + ENALC = 1, + CFDEN = 0, + SWBEN = 0, + STARTUP = 0, + CFDPRESC = 0 + }, + reg = 42502 +} +Quit +Target voltage: 3.3V +Available Targets: +No. Att Driver + 1 Microchip SAME54N19A (rev A) M3/M4 +─── Assembly ──────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── + 0x00000360 main+48 str r2, [r3, #20] + 0x00000362 main+50 ldr r2, [r3, #16] + 0x00000364 main+52 lsls r2, r2, #31 + 0x00000366 main+54 bpl.n 0x362 + 0x00000368 main+56 nop + 0x0000036a main+58 b.n 0x36a  + 0x0000036c main+60 asrs r0, r0, #32 + 0x0000036e main+62 ands r0, r0 + 0x00000370 main+64 push {r4, r5, r6, lr} + 0x00000372 main+66 ldr r6, [pc, #52] ; (0x3a8 ) +─── Breakpoints ───────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +─── Expressions ───────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +─── History ───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +─── Memory ────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +─── Registers ─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── + r0 0x000003d8 r1 0x00000004 r2 0x80000000 r3 0x40001000 r4 0x000119d5 r5 0x20008abc + r6 0x200059d8 r7 0x000125c1 r8 0x000125b5 r9 0x200059d8 r10 0x20005a48 r11 0x2000db94 + r12 0x00000000 sp 0x20010018 lr 0x000002f9 pc 0x0000036a xpsr 0x81000000 fpscr 0x00000000 + msp 0x20010018 psp 0xfdff277c primask 0x00 basepri 0x00 faultmask 0x00 control 0x00 +─── Source ────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── + 46 // 3 - >16MHz to 24MHz + 47 // 3 - >8MHz to 16MHz + 48 // 2 - 8MHz + 49 OSCCTRL->XOSCCTRL[0].bit.IPTAT = 3; + 50 OSCCTRL->XOSCCTRL[0].bit.ONDEMAND = 0; + 51 OSCCTRL->XOSCCTRL[0].bit.XTALEN = 1; + 52 OSCCTRL->XOSCCTRL[0].bit.ENABLE = 1; + 53 + 54 while(0 == OSCCTRL->STATUS.bit.XOSCRDY0); + 55 + 56 OSCCTRL->Dpll[0].DPLLRATIO.bit.LDRFRAC = 0; + 57 OSCCTRL->Dpll[0].DPLLRATIO.bit.LDR = 119; + 58 OSCCTRL->Dpll[0].DPLLCTRLB.bit.DIV = 5; + 59 // 0 - GCLK + 60 // 1 - XOSC32 + 61 // 2 - XOSC0 + 62 // 3 - XOSC1 + 63 OSCCTRL->Dpll[0].DPLLCTRLB.bit.REFCLK = 2; + 64 OSCCTRL->Dpll[0].DPLLCTRLA.bit.ONDEMAND = 0; + 65 OSCCTRL->Dpll[0].DPLLCTRLA.bit.ENABLE = 1; +─── Stack ─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +[0] from 0x0000036a in main+58 at ../../../src/main.c:56 +─── Threads ───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +[1] id 0 from 0x0000036a in main+58 at ../../../src/main.c:56 +─── Variables ─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +0x0000036a in main () at ../../../src/main.c:56 +56 OSCCTRL->Dpll[0].DPLLRATIO.bit.LDRFRAC = 0; +Breakpoint 1 at 0x330: file ../../../src/main.c, line 38. +Loading section .text, size 0x438 lma 0x0 +Start address 0x0, load size 1080 +Transfer rate: 19 KB/sec, 540 bytes/write. +─── Output/messages ───────────────────────────────────────────────────────────────────────────────────────────────────────────────── +Note: automatically using hardware breakpoints for read-only addresses. +─── Assembly ──────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +~ +~ +~ +~ +~ +!0x00000330 main+0  ldr r3, [pc, #56] ; (0x36c ) + 0x00000332 main+2  ldr r2, [r3, #20] + 0x00000334 main+4  orr.w r2, r2, #32768 ; 0x8000 + 0x00000338 main+8  str r2, [r3, #20] + 0x0000033a main+10 ldr r2, [r3, #20] +─── Breakpoints ───────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +[1] break at 0x00000330 in ../../../src/main.c:38 for main hit 1 time +─── Expressions ───────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +─── History ───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +─── Memory ────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +─── Registers ─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── + r0 0x00000438 r1 0x00000000 r2 0xe000ed00 r3 0x00000000 r4 0x000119d5 r5 0x20008abc + r6 0x200059d8 r7 0x000125c1 r8 0x000125b5 r9 0x200059d8 r10 0x20005a48 r11 0x2000db94 + r12 0x00000000 sp 0x20010018 lr 0x000002f9 pc 0x00000330 xpsr 0x61000000 fpscr 0x00000000 + msp 0x20010018 psp 0xfdff277c primask 0x00 basepri 0x00 faultmask 0x00 control 0x00 +─── Source ────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── + 28 // cache init + 29 // endif + 30 + 31 + 32 + 33 // Run with 12mhz external crystal on XOSC0 + 34 + 35 // Automatic Loop Control + 36 // 0 - disable + 37 // 1 - enable +!38 OSCCTRL->XOSCCTRL[0].bit.ENALC = 1; + 39 // Current Multiplier + 40 // 6 - >24MHz to 48MHz + 41 // 5 - >16MHz to 24MHz + 42 // 4 - >8MHz to 16MHz + 43 // 3 - 8MHz + 44 OSCCTRL->XOSCCTRL[0].bit.IMULT = 4; + 45 // 3 - >24MHz to 48MHz + 46 // 3 - >16MHz to 24MHz + 47 // 3 - >8MHz to 16MHz +─── Stack ─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +[0] from 0x00000330 in main+0 at ../../../src/main.c:38 +─── Threads ───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +[1] id -1 from 0x00000330 in main+0 at ../../../src/main.c:38 +─── Variables ─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── + +Breakpoint 1, main () at ../../../src/main.c:38 +38 OSCCTRL->XOSCCTRL[0].bit.ENALC = 1; +─── Output/messages ───────────────────────────────────────────────────────────────────────────────────────────────────────────────── +─── Assembly ──────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +~ +!0x00000330 main+0  ldr r3, [pc, #56] ; (0x36c ) + 0x00000332 main+2  ldr r2, [r3, #20] + 0x00000334 main+4  orr.w r2, r2, #32768 ; 0x8000 + 0x00000338 main+8  str r2, [r3, #20] + 0x0000033a main+10 ldr r2, [r3, #20] + 0x0000033c main+12 movs r1, #4 + 0x0000033e main+14 bfi r2, r1, #11, #4 + 0x00000342 main+18 str r2, [r3, #20] + 0x00000344 main+20 ldr r2, [r3, #20] +─── Breakpoints ───────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +[1] break at 0x00000330 in ../../../src/main.c:38 for main hit 1 time +─── Expressions ───────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +─── History ───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +─── Memory ────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +─── Registers ─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── + r0 0x00000438 r1 0x00000000 r2 0x00008080 r3 0x40001000 r4 0x000119d5 r5 0x20008abc + r6 0x200059d8 r7 0x000125c1 r8 0x000125b5 r9 0x200059d8 r10 0x20005a48 r11 0x2000db94 + r12 0x00000000 sp 0x20010018 lr 0x000002f9 pc 0x0000033a xpsr 0x61000000 fpscr 0x00000000 + msp 0x20010018 psp 0xfdff277c primask 0x00 basepri 0x00 faultmask 0x00 control 0x00 +─── Source ────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── + 34 + 35 // Automatic Loop Control + 36 // 0 - disable + 37 // 1 - enable +!38 OSCCTRL->XOSCCTRL[0].bit.ENALC = 1; + 39 // Current Multiplier + 40 // 6 - >24MHz to 48MHz + 41 // 5 - >16MHz to 24MHz + 42 // 4 - >8MHz to 16MHz + 43 // 3 - 8MHz + 44 OSCCTRL->XOSCCTRL[0].bit.IMULT = 4; + 45 // 3 - >24MHz to 48MHz + 46 // 3 - >16MHz to 24MHz + 47 // 3 - >8MHz to 16MHz + 48 // 2 - 8MHz + 49 OSCCTRL->XOSCCTRL[0].bit.IPTAT = 3; + 50 OSCCTRL->XOSCCTRL[0].bit.ONDEMAND = 0; + 51 OSCCTRL->XOSCCTRL[0].bit.XTALEN = 1; + 52 OSCCTRL->XOSCCTRL[0].bit.ENABLE = 1; + 53 +─── Stack ─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +[0] from 0x0000033a in main+10 at ../../../src/main.c:44 +─── Threads ───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +[1] id -1 from 0x0000033a in main+10 at ../../../src/main.c:44 +─── Variables ─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +44 OSCCTRL->XOSCCTRL[0].bit.IMULT = 4; +─── Output/messages ───────────────────────────────────────────────────────────────────────────────────────────────────────────────── +─── Assembly ──────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── + 0x00000338 main+8  str r2, [r3, #20] + 0x0000033a main+10 ldr r2, [r3, #20] + 0x0000033c main+12 movs r1, #4 + 0x0000033e main+14 bfi r2, r1, #11, #4 + 0x00000342 main+18 str r2, [r3, #20] + 0x00000344 main+20 ldr r2, [r3, #20] + 0x00000346 main+22 orr.w r2, r2, #1536 ; 0x600 + 0x0000034a main+26 str r2, [r3, #20] + 0x0000034c main+28 ldr r2, [r3, #20] + 0x0000034e main+30 bfc r2, #7, #1 +─── Breakpoints ───────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +[1] break at 0x00000330 in ../../../src/main.c:38 for main hit 1 time +─── Expressions ───────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +─── History ───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +─── Memory ────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +─── Registers ─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── + r0 0x00000438 r1 0x00000004 r2 0x0000a080 r3 0x40001000 r4 0x000119d5 r5 0x20008abc + r6 0x200059d8 r7 0x000125c1 r8 0x000125b5 r9 0x200059d8 r10 0x20005a48 r11 0x2000db94 + r12 0x00000000 sp 0x20010018 lr 0x000002f9 pc 0x00000344 xpsr 0x21000000 fpscr 0x00000000 + msp 0x20010018 psp 0xfdff277c primask 0x00 basepri 0x00 faultmask 0x00 control 0x00 +─── Source ────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── + 39 // Current Multiplier + 40 // 6 - >24MHz to 48MHz + 41 // 5 - >16MHz to 24MHz + 42 // 4 - >8MHz to 16MHz + 43 // 3 - 8MHz + 44 OSCCTRL->XOSCCTRL[0].bit.IMULT = 4; + 45 // 3 - >24MHz to 48MHz + 46 // 3 - >16MHz to 24MHz + 47 // 3 - >8MHz to 16MHz + 48 // 2 - 8MHz + 49 OSCCTRL->XOSCCTRL[0].bit.IPTAT = 3; + 50 OSCCTRL->XOSCCTRL[0].bit.ONDEMAND = 0; + 51 OSCCTRL->XOSCCTRL[0].bit.XTALEN = 1; + 52 OSCCTRL->XOSCCTRL[0].bit.ENABLE = 1; + 53 + 54 while(0 == OSCCTRL->STATUS.bit.XOSCRDY0); + 55 + 56 OSCCTRL->Dpll[0].DPLLRATIO.bit.LDRFRAC = 0; + 57 OSCCTRL->Dpll[0].DPLLRATIO.bit.LDR = 119; + 58 OSCCTRL->Dpll[0].DPLLCTRLB.bit.DIV = 5; +─── Stack ─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +[0] from 0x00000344 in main+20 at ../../../src/main.c:49 +─── Threads ───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +[1] id -1 from 0x00000344 in main+20 at ../../../src/main.c:49 +─── Variables ─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +49 OSCCTRL->XOSCCTRL[0].bit.IPTAT = 3; +─── Output/messages ───────────────────────────────────────────────────────────────────────────────────────────────────────────────── +─── Assembly ──────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── + 0x0000033e main+14 bfi r2, r1, #11, #4 + 0x00000342 main+18 str r2, [r3, #20] + 0x00000344 main+20 ldr r2, [r3, #20] + 0x00000346 main+22 orr.w r2, r2, #1536 ; 0x600 + 0x0000034a main+26 str r2, [r3, #20] + 0x0000034c main+28 ldr r2, [r3, #20] + 0x0000034e main+30 bfc r2, #7, #1 + 0x00000352 main+34 str r2, [r3, #20] + 0x00000354 main+36 ldr r2, [r3, #20] + 0x00000356 main+38 orrs r2, r1 +─── Breakpoints ───────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +[1] break at 0x00000330 in ../../../src/main.c:38 for main hit 1 time +─── Expressions ───────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +─── History ───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +─── Memory ────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +─── Registers ─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── + r0 0x00000438 r1 0x00000004 r2 0x0000a680 r3 0x40001000 r4 0x000119d5 r5 0x20008abc + r6 0x200059d8 r7 0x000125c1 r8 0x000125b5 r9 0x200059d8 r10 0x20005a48 r11 0x2000db94 + r12 0x00000000 sp 0x20010018 lr 0x000002f9 pc 0x0000034c xpsr 0x21000000 fpscr 0x00000000 + msp 0x20010018 psp 0xfdff277c primask 0x00 basepri 0x00 faultmask 0x00 control 0x00 +─── Source ────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── + 40 // 6 - >24MHz to 48MHz + 41 // 5 - >16MHz to 24MHz + 42 // 4 - >8MHz to 16MHz + 43 // 3 - 8MHz + 44 OSCCTRL->XOSCCTRL[0].bit.IMULT = 4; + 45 // 3 - >24MHz to 48MHz + 46 // 3 - >16MHz to 24MHz + 47 // 3 - >8MHz to 16MHz + 48 // 2 - 8MHz + 49 OSCCTRL->XOSCCTRL[0].bit.IPTAT = 3; + 50 OSCCTRL->XOSCCTRL[0].bit.ONDEMAND = 0; + 51 OSCCTRL->XOSCCTRL[0].bit.XTALEN = 1; + 52 OSCCTRL->XOSCCTRL[0].bit.ENABLE = 1; + 53 + 54 while(0 == OSCCTRL->STATUS.bit.XOSCRDY0); + 55 + 56 OSCCTRL->Dpll[0].DPLLRATIO.bit.LDRFRAC = 0; + 57 OSCCTRL->Dpll[0].DPLLRATIO.bit.LDR = 119; + 58 OSCCTRL->Dpll[0].DPLLCTRLB.bit.DIV = 5; + 59 // 0 - GCLK +─── Stack ─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +[0] from 0x0000034c in main+28 at ../../../src/main.c:50 +─── Threads ───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +[1] id -1 from 0x0000034c in main+28 at ../../../src/main.c:50 +─── Variables ─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +50 OSCCTRL->XOSCCTRL[0].bit.ONDEMAND = 0; +─── Output/messages ───────────────────────────────────────────────────────────────────────────────────────────────────────────────── +─── Assembly ──────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── + 0x00000346 main+22 orr.w r2, r2, #1536 ; 0x600 + 0x0000034a main+26 str r2, [r3, #20] + 0x0000034c main+28 ldr r2, [r3, #20] + 0x0000034e main+30 bfc r2, #7, #1 + 0x00000352 main+34 str r2, [r3, #20] + 0x00000354 main+36 ldr r2, [r3, #20] + 0x00000356 main+38 orrs r2, r1 + 0x00000358 main+40 str r2, [r3, #20] + 0x0000035a main+42 ldr r2, [r3, #20] + 0x0000035c main+44 orr.w r2, r2, #2 +─── Breakpoints ───────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +[1] break at 0x00000330 in ../../../src/main.c:38 for main hit 1 time +─── Expressions ───────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +─── History ───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +─── Memory ────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +─── Registers ─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── + r0 0x00000438 r1 0x00000004 r2 0x0000a600 r3 0x40001000 r4 0x000119d5 r5 0x20008abc + r6 0x200059d8 r7 0x000125c1 r8 0x000125b5 r9 0x200059d8 r10 0x20005a48 r11 0x2000db94 + r12 0x00000000 sp 0x20010018 lr 0x000002f9 pc 0x00000354 xpsr 0x21000000 fpscr 0x00000000 + msp 0x20010018 psp 0xfdff277c primask 0x00 basepri 0x00 faultmask 0x00 control 0x00 +─── Source ────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── + 41 // 5 - >16MHz to 24MHz + 42 // 4 - >8MHz to 16MHz + 43 // 3 - 8MHz + 44 OSCCTRL->XOSCCTRL[0].bit.IMULT = 4; + 45 // 3 - >24MHz to 48MHz + 46 // 3 - >16MHz to 24MHz + 47 // 3 - >8MHz to 16MHz + 48 // 2 - 8MHz + 49 OSCCTRL->XOSCCTRL[0].bit.IPTAT = 3; + 50 OSCCTRL->XOSCCTRL[0].bit.ONDEMAND = 0; + 51 OSCCTRL->XOSCCTRL[0].bit.XTALEN = 1; + 52 OSCCTRL->XOSCCTRL[0].bit.ENABLE = 1; + 53 + 54 while(0 == OSCCTRL->STATUS.bit.XOSCRDY0); + 55 + 56 OSCCTRL->Dpll[0].DPLLRATIO.bit.LDRFRAC = 0; + 57 OSCCTRL->Dpll[0].DPLLRATIO.bit.LDR = 119; + 58 OSCCTRL->Dpll[0].DPLLCTRLB.bit.DIV = 5; + 59 // 0 - GCLK + 60 // 1 - XOSC32 +─── Stack ─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +[0] from 0x00000354 in main+36 at ../../../src/main.c:51 +─── Threads ───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +[1] id -1 from 0x00000354 in main+36 at ../../../src/main.c:51 +─── Variables ─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +51 OSCCTRL->XOSCCTRL[0].bit.XTALEN = 1; +─── Output/messages ───────────────────────────────────────────────────────────────────────────────────────────────────────────────── +─── Assembly ──────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── + 0x0000034e main+30 bfc r2, #7, #1 + 0x00000352 main+34 str r2, [r3, #20] + 0x00000354 main+36 ldr r2, [r3, #20] + 0x00000356 main+38 orrs r2, r1 + 0x00000358 main+40 str r2, [r3, #20] + 0x0000035a main+42 ldr r2, [r3, #20] + 0x0000035c main+44 orr.w r2, r2, #2 + 0x00000360 main+48 str r2, [r3, #20] + 0x00000362 main+50 ldr r2, [r3, #16] + 0x00000364 main+52 lsls r2, r2, #31 +─── Breakpoints ───────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +[1] break at 0x00000330 in ../../../src/main.c:38 for main hit 1 time +─── Expressions ───────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +─── History ───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +─── Memory ────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +─── Registers ─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── + r0 0x00000438 r1 0x00000004 r2 0x0000a604 r3 0x40001000 r4 0x000119d5 r5 0x20008abc + r6 0x200059d8 r7 0x000125c1 r8 0x000125b5 r9 0x200059d8 r10 0x20005a48 r11 0x2000db94 + r12 0x00000000 sp 0x20010018 lr 0x000002f9 pc 0x0000035a xpsr 0x21000000 fpscr 0x00000000 + msp 0x20010018 psp 0xfdff277c primask 0x00 basepri 0x00 faultmask 0x00 control 0x00 +─── Source ────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── + 42 // 4 - >8MHz to 16MHz + 43 // 3 - 8MHz + 44 OSCCTRL->XOSCCTRL[0].bit.IMULT = 4; + 45 // 3 - >24MHz to 48MHz + 46 // 3 - >16MHz to 24MHz + 47 // 3 - >8MHz to 16MHz + 48 // 2 - 8MHz + 49 OSCCTRL->XOSCCTRL[0].bit.IPTAT = 3; + 50 OSCCTRL->XOSCCTRL[0].bit.ONDEMAND = 0; + 51 OSCCTRL->XOSCCTRL[0].bit.XTALEN = 1; + 52 OSCCTRL->XOSCCTRL[0].bit.ENABLE = 1; + 53 + 54 while(0 == OSCCTRL->STATUS.bit.XOSCRDY0); + 55 + 56 OSCCTRL->Dpll[0].DPLLRATIO.bit.LDRFRAC = 0; + 57 OSCCTRL->Dpll[0].DPLLRATIO.bit.LDR = 119; + 58 OSCCTRL->Dpll[0].DPLLCTRLB.bit.DIV = 5; + 59 // 0 - GCLK + 60 // 1 - XOSC32 + 61 // 2 - XOSC0 +─── Stack ─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +[0] from 0x0000035a in main+42 at ../../../src/main.c:52 +─── Threads ───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +[1] id -1 from 0x0000035a in main+42 at ../../../src/main.c:52 +─── Variables ─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +52 OSCCTRL->XOSCCTRL[0].bit.ENABLE = 1; +─── Output/messages ───────────────────────────────────────────────────────────────────────────────────────────────────────────────── +─── Assembly ──────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── + 0x00000356 main+38 orrs r2, r1 + 0x00000358 main+40 str r2, [r3, #20] + 0x0000035a main+42 ldr r2, [r3, #20] + 0x0000035c main+44 orr.w r2, r2, #2 + 0x00000360 main+48 str r2, [r3, #20] + 0x00000362 main+50 ldr r2, [r3, #16] + 0x00000364 main+52 lsls r2, r2, #31 + 0x00000366 main+54 bpl.n 0x362  + 0x00000368 main+56 nop + 0x0000036a main+58 b.n 0x36a +─── Breakpoints ───────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +[1] break at 0x00000330 in ../../../src/main.c:38 for main hit 1 time +─── Expressions ───────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +─── History ───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +─── Memory ────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +─── Registers ─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── + r0 0x00000438 r1 0x00000004 r2 0x0000a606 r3 0x40001000 r4 0x000119d5 r5 0x20008abc + r6 0x200059d8 r7 0x000125c1 r8 0x000125b5 r9 0x200059d8 r10 0x20005a48 r11 0x2000db94 + r12 0x00000000 sp 0x20010018 lr 0x000002f9 pc 0x00000362 xpsr 0x21000000 fpscr 0x00000000 + msp 0x20010018 psp 0xfdff277c primask 0x00 basepri 0x00 faultmask 0x00 control 0x00 +─── Source ────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── + 44 OSCCTRL->XOSCCTRL[0].bit.IMULT = 4; + 45 // 3 - >24MHz to 48MHz + 46 // 3 - >16MHz to 24MHz + 47 // 3 - >8MHz to 16MHz + 48 // 2 - 8MHz + 49 OSCCTRL->XOSCCTRL[0].bit.IPTAT = 3; + 50 OSCCTRL->XOSCCTRL[0].bit.ONDEMAND = 0; + 51 OSCCTRL->XOSCCTRL[0].bit.XTALEN = 1; + 52 OSCCTRL->XOSCCTRL[0].bit.ENABLE = 1; + 53 + 54 while(0 == OSCCTRL->STATUS.bit.XOSCRDY0); + 55 + 56 OSCCTRL->Dpll[0].DPLLRATIO.bit.LDRFRAC = 0; + 57 OSCCTRL->Dpll[0].DPLLRATIO.bit.LDR = 119; + 58 OSCCTRL->Dpll[0].DPLLCTRLB.bit.DIV = 5; + 59 // 0 - GCLK + 60 // 1 - XOSC32 + 61 // 2 - XOSC0 + 62 // 3 - XOSC1 + 63 OSCCTRL->Dpll[0].DPLLCTRLB.bit.REFCLK = 2; +─── Stack ─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +[0] from 0x00000362 in main+50 at ../../../src/main.c:54 +─── Threads ───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +[1] id -1 from 0x00000362 in main+50 at ../../../src/main.c:54 +─── Variables ─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +54 while(0 == OSCCTRL->STATUS.bit.XOSCRDY0); +─── Output/messages ───────────────────────────────────────────────────────────────────────────────────────────────────────────────── +─── Assembly ──────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── + 0x0000035c main+44 orr.w r2, r2, #2 + 0x00000360 main+48 str r2, [r3, #20] + 0x00000362 main+50 ldr r2, [r3, #16] + 0x00000364 main+52 lsls r2, r2, #31 + 0x00000366 main+54 bpl.n 0x362 + 0x00000368 main+56 nop + 0x0000036a main+58 b.n 0x36a  + 0x0000036c main+60 asrs r0, r0, #32 + 0x0000036e main+62 ands r0, r0 + 0x00000370 main+64 push {r4, r5, r6, lr} +─── Breakpoints ───────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +[1] break at 0x00000330 in ../../../src/main.c:38 for main hit 1 time +─── Expressions ───────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +─── History ───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +─── Memory ────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +─── Registers ─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── + r0 0x00000438 r1 0x00000004 r2 0x80000000 r3 0x40001000 r4 0x000119d5 r5 0x20008abc + r6 0x200059d8 r7 0x000125c1 r8 0x000125b5 r9 0x200059d8 r10 0x20005a48 r11 0x2000db94 + r12 0x00000000 sp 0x20010018 lr 0x000002f9 pc 0x00000368 xpsr 0x81000000 fpscr 0x00000000 + msp 0x20010018 psp 0xfdff277c primask 0x00 basepri 0x00 faultmask 0x00 control 0x00 +─── Source ────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── + 46 // 3 - >16MHz to 24MHz + 47 // 3 - >8MHz to 16MHz + 48 // 2 - 8MHz + 49 OSCCTRL->XOSCCTRL[0].bit.IPTAT = 3; + 50 OSCCTRL->XOSCCTRL[0].bit.ONDEMAND = 0; + 51 OSCCTRL->XOSCCTRL[0].bit.XTALEN = 1; + 52 OSCCTRL->XOSCCTRL[0].bit.ENABLE = 1; + 53 + 54 while(0 == OSCCTRL->STATUS.bit.XOSCRDY0); + 55 + 56 OSCCTRL->Dpll[0].DPLLRATIO.bit.LDRFRAC = 0; + 57 OSCCTRL->Dpll[0].DPLLRATIO.bit.LDR = 119; + 58 OSCCTRL->Dpll[0].DPLLCTRLB.bit.DIV = 5; + 59 // 0 - GCLK + 60 // 1 - XOSC32 + 61 // 2 - XOSC0 + 62 // 3 - XOSC1 + 63 OSCCTRL->Dpll[0].DPLLCTRLB.bit.REFCLK = 2; + 64 OSCCTRL->Dpll[0].DPLLCTRLA.bit.ONDEMAND = 0; + 65 OSCCTRL->Dpll[0].DPLLCTRLA.bit.ENABLE = 1; +─── Stack ─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +[0] from 0x00000368 in main+56 at ../../../src/main.c:56 +─── Threads ───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +[1] id -1 from 0x00000368 in main+56 at ../../../src/main.c:56 +─── Variables ─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +56 OSCCTRL->Dpll[0].DPLLRATIO.bit.LDRFRAC = 0; +─── Output/messages ───────────────────────────────────────────────────────────────────────────────────────────────────────────────── +─── Assembly ──────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── + 0x00000366 main+54 bpl.n 0x362 + 0x00000368 main+56 nop + 0x0000036a main+58 b.n 0x36a + 0x0000036c main+60 asrs r0, r0, #32 + 0x0000036e main+62 ands r0, r0 + 0x00000370 main+64 push {r4, r5, r6, lr} + 0x00000372 main+66 ldr r6, [pc, #52] ; (0x3a8 ) + 0x00000374 main+68 ldr r4, [pc, #52] ; (0x3ac ) + 0x00000376 main+70 subs r4, r4, r6 + 0x00000378 main+72 asrs r4, r4, #2 +─── Breakpoints ───────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +[1] break at 0x00000330 in ../../../src/main.c:38 for main hit 1 time +─── Expressions ───────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +─── History ───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +─── Memory ────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +─── Registers ─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── + r0 0x00000438 r1 0x00000004 r2 0x00000000 r3 0x40001000 r4 0x000119d5 r5 0x20008abc + r6 0x200059d8 r7 0x000125c1 r8 0x000125b5 r9 0x200059d8 r10 0x20005a48 r11 0x2000db94 + r12 0x00000000 sp 0x20010018 lr 0x000002f9 pc 0x00000370 xpsr 0x81000000 fpscr 0x00000000 + msp 0x20010018 psp 0xfdff277c primask 0x00 basepri 0x00 faultmask 0x00 control 0x00 +─── Source ────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── + 47 // 3 - >8MHz to 16MHz + 48 // 2 - 8MHz + 49 OSCCTRL->XOSCCTRL[0].bit.IPTAT = 3; + 50 OSCCTRL->XOSCCTRL[0].bit.ONDEMAND = 0; + 51 OSCCTRL->XOSCCTRL[0].bit.XTALEN = 1; + 52 OSCCTRL->XOSCCTRL[0].bit.ENABLE = 1; + 53 + 54 while(0 == OSCCTRL->STATUS.bit.XOSCRDY0); + 55 + 56 OSCCTRL->Dpll[0].DPLLRATIO.bit.LDRFRAC = 0; + 57 OSCCTRL->Dpll[0].DPLLRATIO.bit.LDR = 119; + 58 OSCCTRL->Dpll[0].DPLLCTRLB.bit.DIV = 5; + 59 // 0 - GCLK + 60 // 1 - XOSC32 + 61 // 2 - XOSC0 + 62 // 3 - XOSC1 + 63 OSCCTRL->Dpll[0].DPLLCTRLB.bit.REFCLK = 2; + 64 OSCCTRL->Dpll[0].DPLLCTRLA.bit.ONDEMAND = 0; + 65 OSCCTRL->Dpll[0].DPLLCTRLA.bit.ENABLE = 1; + 66 +─── Stack ─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +[0] from 0x00000370 in main+64 at ../../../src/main.c:57 +─── Threads ───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +[1] id -1 from 0x00000370 in main+64 at ../../../src/main.c:57 +─── Variables ─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +57 OSCCTRL->Dpll[0].DPLLRATIO.bit.LDR = 119; +─── Output/messages ───────────────────────────────────────────────────────────────────────────────────────────────────────────────── +─── Assembly ──────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── + 0x00000370 main+64 push {r4, r5, r6, lr} + 0x00000372 main+66 ldr r6, [pc, #52] ; (0x3a8 ) + 0x00000374 main+68 ldr r4, [pc, #52] ; (0x3ac ) + 0x00000376 main+70 subs r4, r4, r6 + 0x00000378 main+72 asrs r4, r4, #2 + 0x0000037a main+74 movs r5, #0 + 0x0000037c main+76 cmp r5, r4 + 0x0000037e main+78 bne.n 0x394  + 0x00000380 main+80 ldr r6, [pc, #44] ; (0x3b0 ) + 0x00000382 main+82 ldr r4, [pc, #48] ; (0x3b4 ) +─── Breakpoints ───────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +[1] break at 0x00000330 in ../../../src/main.c:38 for main hit 1 time +─── Expressions ───────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +─── History ───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +─── Memory ────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +─── Registers ─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── + r0 0x00000438 r1 0x00000077 r2 0x00000077 r3 0x40001000 r4 0x000119d5 r5 0x20008abc + r6 0x200059d8 r7 0x000125c1 r8 0x000125b5 r9 0x200059d8 r10 0x20005a48 r11 0x2000db94 + r12 0x00000000 sp 0x20010018 lr 0x000002f9 pc 0x0000037a xpsr 0x01000000 fpscr 0x00000000 + msp 0x20010018 psp 0xfdff277c primask 0x00 basepri 0x00 faultmask 0x00 control 0x00 +─── Source ────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── + 48 // 2 - 8MHz + 49 OSCCTRL->XOSCCTRL[0].bit.IPTAT = 3; + 50 OSCCTRL->XOSCCTRL[0].bit.ONDEMAND = 0; + 51 OSCCTRL->XOSCCTRL[0].bit.XTALEN = 1; + 52 OSCCTRL->XOSCCTRL[0].bit.ENABLE = 1; + 53 + 54 while(0 == OSCCTRL->STATUS.bit.XOSCRDY0); + 55 + 56 OSCCTRL->Dpll[0].DPLLRATIO.bit.LDRFRAC = 0; + 57 OSCCTRL->Dpll[0].DPLLRATIO.bit.LDR = 119; + 58 OSCCTRL->Dpll[0].DPLLCTRLB.bit.DIV = 5; + 59 // 0 - GCLK + 60 // 1 - XOSC32 + 61 // 2 - XOSC0 + 62 // 3 - XOSC1 + 63 OSCCTRL->Dpll[0].DPLLCTRLB.bit.REFCLK = 2; + 64 OSCCTRL->Dpll[0].DPLLCTRLA.bit.ONDEMAND = 0; + 65 OSCCTRL->Dpll[0].DPLLCTRLA.bit.ENABLE = 1; + 66 + 67 // wait for pll to be locked and ready +─── Stack ─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +[0] from 0x0000037a in main+74 at ../../../src/main.c:58 +─── Threads ───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +[1] id -1 from 0x0000037a in main+74 at ../../../src/main.c:58 +─── Variables ─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +58 OSCCTRL->Dpll[0].DPLLCTRLB.bit.DIV = 5; +─── Output/messages ───────────────────────────────────────────────────────────────────────────────────────────────────────────────── +─── Assembly ──────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── + 0x0000037a main+74 movs r5, #0 + 0x0000037c main+76 cmp r5, r4 + 0x0000037e main+78 bne.n 0x394 + 0x00000380 main+80 ldr r6, [pc, #44] ; (0x3b0 ) + 0x00000382 main+82 ldr r4, [pc, #48] ; (0x3b4 ) + 0x00000384 main+84 bl 0x3b8  + 0x00000388 main+88 subs r4, r4, r6 + 0x0000038a main+90 asrs r4, r4, #2 + 0x0000038c main+92 movs r5, #0 + 0x0000038e main+94 cmp r5, r4 +─── Breakpoints ───────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +[1] break at 0x00000330 in ../../../src/main.c:38 for main hit 1 time +─── Expressions ───────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +─── History ───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +─── Memory ────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +─── Registers ─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── + r0 0x00000438 r1 0x00000005 r2 0x00050020 r3 0x40001000 r4 0x000119d5 r5 0x20008abc + r6 0x200059d8 r7 0x000125c1 r8 0x000125b5 r9 0x200059d8 r10 0x20005a48 r11 0x2000db94 + r12 0x00000000 sp 0x20010018 lr 0x000002f9 pc 0x00000384 xpsr 0x01000000 fpscr 0x00000000 + msp 0x20010018 psp 0xfdff277c primask 0x00 basepri 0x00 faultmask 0x00 control 0x00 +─── Source ────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── + 53 + 54 while(0 == OSCCTRL->STATUS.bit.XOSCRDY0); + 55 + 56 OSCCTRL->Dpll[0].DPLLRATIO.bit.LDRFRAC = 0; + 57 OSCCTRL->Dpll[0].DPLLRATIO.bit.LDR = 119; + 58 OSCCTRL->Dpll[0].DPLLCTRLB.bit.DIV = 5; + 59 // 0 - GCLK + 60 // 1 - XOSC32 + 61 // 2 - XOSC0 + 62 // 3 - XOSC1 + 63 OSCCTRL->Dpll[0].DPLLCTRLB.bit.REFCLK = 2; + 64 OSCCTRL->Dpll[0].DPLLCTRLA.bit.ONDEMAND = 0; + 65 OSCCTRL->Dpll[0].DPLLCTRLA.bit.ENABLE = 1; + 66 + 67 // wait for pll to be locked and ready + 68 while(0 == OSCCTRL->Dpll[0].DPLLSTATUS.bit.LOCK + 69 || 0 == OSCCTRL->Dpll[0].DPLLSTATUS.bit.CLKRDY); + 70 + 71 // Connect DPLL0 to clock generator 0 (120mhz) - frequency used by CPU, AHB, APBA, APBB + 72 GCLK->GENCTRL[0].reg = GCLK_GENCTRL_SRC_DPLL0 | GCLK_GENCTRL_DIV(1) | GCLK_GENCTRL_GENEN; +─── Stack ─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +[0] from 0x00000384 in main+84 at ../../../src/main.c:63 +─── Threads ───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +[1] id -1 from 0x00000384 in main+84 at ../../../src/main.c:63 +─── Variables ─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +63 OSCCTRL->Dpll[0].DPLLCTRLB.bit.REFCLK = 2; +─── Output/messages ───────────────────────────────────────────────────────────────────────────────────────────────────────────────── +─── Assembly ──────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── + 0x00000382 main+82  ldr r4, [pc, #48] ; (0x3b4 ) + 0x00000384 main+84  bl 0x3b8 + 0x00000388 main+88  subs r4, r4, r6 + 0x0000038a main+90  asrs r4, r4, #2 + 0x0000038c main+92  movs r5, #0 + 0x0000038e main+94  cmp r5, r4 + 0x00000390 main+96  bne.n 0x39e  + 0x00000392 main+98  pop {r4, r5, r6, pc} + 0x00000394 main+100 ldr.w r3, [r6, r5, lsl #2] + 0x00000398 main+104 blx r3 +─── Breakpoints ───────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +[1] break at 0x00000330 in ../../../src/main.c:38 for main hit 1 time +─── Expressions ───────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +─── History ───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +─── Memory ────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +─── Registers ─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── + r0 0x00000438 r1 0x00000002 r2 0x00050040 r3 0x40001000 r4 0x000119d5 r5 0x20008abc + r6 0x200059d8 r7 0x000125c1 r8 0x000125b5 r9 0x200059d8 r10 0x20005a48 r11 0x2000db94 + r12 0x00000000 sp 0x20010018 lr 0x000002f9 pc 0x0000038e xpsr 0x01000000 fpscr 0x00000000 + msp 0x20010018 psp 0xfdff277c primask 0x00 basepri 0x00 faultmask 0x00 control 0x00 +─── Source ────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── + 54 while(0 == OSCCTRL->STATUS.bit.XOSCRDY0); + 55 + 56 OSCCTRL->Dpll[0].DPLLRATIO.bit.LDRFRAC = 0; + 57 OSCCTRL->Dpll[0].DPLLRATIO.bit.LDR = 119; + 58 OSCCTRL->Dpll[0].DPLLCTRLB.bit.DIV = 5; + 59 // 0 - GCLK + 60 // 1 - XOSC32 + 61 // 2 - XOSC0 + 62 // 3 - XOSC1 + 63 OSCCTRL->Dpll[0].DPLLCTRLB.bit.REFCLK = 2; + 64 OSCCTRL->Dpll[0].DPLLCTRLA.bit.ONDEMAND = 0; + 65 OSCCTRL->Dpll[0].DPLLCTRLA.bit.ENABLE = 1; + 66 + 67 // wait for pll to be locked and ready + 68 while(0 == OSCCTRL->Dpll[0].DPLLSTATUS.bit.LOCK + 69 || 0 == OSCCTRL->Dpll[0].DPLLSTATUS.bit.CLKRDY); + 70 + 71 // Connect DPLL0 to clock generator 0 (120mhz) - frequency used by CPU, AHB, APBA, APBB + 72 GCLK->GENCTRL[0].reg = GCLK_GENCTRL_SRC_DPLL0 | GCLK_GENCTRL_DIV(1) | GCLK_GENCTRL_GENEN; + 73 while(1 == GCLK->SYNCBUSY.bit.GENCTRL0); +─── Stack ─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +[0] from 0x0000038e in main+94 at ../../../src/main.c:64 +─── Threads ───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +[1] id -1 from 0x0000038e in main+94 at ../../../src/main.c:64 +─── Variables ─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +64 OSCCTRL->Dpll[0].DPLLCTRLA.bit.ONDEMAND = 0; +─── Output/messages ───────────────────────────────────────────────────────────────────────────────────────────────────────────────── +─── Assembly ──────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── + 0x0000038e main+94  cmp r5, r4 + 0x00000390 main+96  bne.n 0x39e + 0x00000392 main+98  pop {r4, r5, r6, pc} + 0x00000394 main+100 ldr.w r3, [r6, r5, lsl #2] + 0x00000398 main+104 blx r3 + 0x0000039a main+106 adds r5, #1 + 0x0000039c main+108 b.n 0x37c  + 0x0000039e main+110 ldr.w r3, [r6, r5, lsl #2] + 0x000003a2 main+114 blx r3 + 0x000003a4 main+116 adds r5, #1 +─── Breakpoints ───────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +[1] break at 0x00000330 in ../../../src/main.c:38 for main hit 1 time +─── Expressions ───────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +─── History ───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +─── Memory ────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +─── Registers ─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── + r0 0x00000438 r1 0x00000002 r2 0x00000000 r3 0x40001000 r4 0x000119d5 r5 0x20008abc + r6 0x200059d8 r7 0x000125c1 r8 0x000125b5 r9 0x200059d8 r10 0x20005a48 r11 0x2000db94 + r12 0x00000000 sp 0x20010018 lr 0x000002f9 pc 0x0000039a xpsr 0x01000000 fpscr 0x00000000 + msp 0x20010018 psp 0xfdff277c primask 0x00 basepri 0x00 faultmask 0x00 control 0x00 +─── Source ────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── + 55 + 56 OSCCTRL->Dpll[0].DPLLRATIO.bit.LDRFRAC = 0; + 57 OSCCTRL->Dpll[0].DPLLRATIO.bit.LDR = 119; + 58 OSCCTRL->Dpll[0].DPLLCTRLB.bit.DIV = 5; + 59 // 0 - GCLK + 60 // 1 - XOSC32 + 61 // 2 - XOSC0 + 62 // 3 - XOSC1 + 63 OSCCTRL->Dpll[0].DPLLCTRLB.bit.REFCLK = 2; + 64 OSCCTRL->Dpll[0].DPLLCTRLA.bit.ONDEMAND = 0; + 65 OSCCTRL->Dpll[0].DPLLCTRLA.bit.ENABLE = 1; + 66 + 67 // wait for pll to be locked and ready + 68 while(0 == OSCCTRL->Dpll[0].DPLLSTATUS.bit.LOCK + 69 || 0 == OSCCTRL->Dpll[0].DPLLSTATUS.bit.CLKRDY); + 70 + 71 // Connect DPLL0 to clock generator 0 (120mhz) - frequency used by CPU, AHB, APBA, APBB + 72 GCLK->GENCTRL[0].reg = GCLK_GENCTRL_SRC_DPLL0 | GCLK_GENCTRL_DIV(1) | GCLK_GENCTRL_GENEN; + 73 while(1 == GCLK->SYNCBUSY.bit.GENCTRL0); + 74 +─── Stack ─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +[0] from 0x0000039a in main+106 at ../../../src/main.c:65 +─── Threads ───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +[1] id -1 from 0x0000039a in main+106 at ../../../src/main.c:65 +─── Variables ─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +65 OSCCTRL->Dpll[0].DPLLCTRLA.bit.ENABLE = 1; +─── Output/messages ───────────────────────────────────────────────────────────────────────────────────────────────────────────────── +─── Assembly ──────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── + 0x00000398 main+104 blx r3 + 0x0000039a main+106 adds r5, #1 + 0x0000039c main+108 b.n 0x37c + 0x0000039e main+110 ldr.w r3, [r6, r5, lsl #2] + 0x000003a2 main+114 blx r3 + 0x000003a4 main+116 adds r5, #1 + 0x000003a6 main+118 b.n 0x38e  + 0x000003a8 main+120 lsls r4, r0, #15 + 0x000003aa main+122 movs r0, r0 + 0x000003ac main+124 lsls r4, r0, #15 +─── Breakpoints ───────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +[1] break at 0x00000330 in ../../../src/main.c:38 for main hit 1 time +─── Expressions ───────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +─── History ───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +─── Memory ────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +─── Registers ─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── + r0 0x00000438 r1 0x00000002 r2 0x00000002 r3 0x40001000 r4 0x000119d5 r5 0x20008abc + r6 0x200059d8 r7 0x000125c1 r8 0x000125b5 r9 0x200059d8 r10 0x20005a48 r11 0x2000db94 + r12 0x00000000 sp 0x20010018 lr 0x000002f9 pc 0x000003a4 xpsr 0x01000000 fpscr 0x00000000 + msp 0x20010018 psp 0xfdff277c primask 0x00 basepri 0x00 faultmask 0x00 control 0x00 +─── Source ────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── + 58 OSCCTRL->Dpll[0].DPLLCTRLB.bit.DIV = 5; + 59 // 0 - GCLK + 60 // 1 - XOSC32 + 61 // 2 - XOSC0 + 62 // 3 - XOSC1 + 63 OSCCTRL->Dpll[0].DPLLCTRLB.bit.REFCLK = 2; + 64 OSCCTRL->Dpll[0].DPLLCTRLA.bit.ONDEMAND = 0; + 65 OSCCTRL->Dpll[0].DPLLCTRLA.bit.ENABLE = 1; + 66 + 67 // wait for pll to be locked and ready + 68 while(0 == OSCCTRL->Dpll[0].DPLLSTATUS.bit.LOCK + 69 || 0 == OSCCTRL->Dpll[0].DPLLSTATUS.bit.CLKRDY); + 70 + 71 // Connect DPLL0 to clock generator 0 (120mhz) - frequency used by CPU, AHB, APBA, APBB + 72 GCLK->GENCTRL[0].reg = GCLK_GENCTRL_SRC_DPLL0 | GCLK_GENCTRL_DIV(1) | GCLK_GENCTRL_GENEN; + 73 while(1 == GCLK->SYNCBUSY.bit.GENCTRL0); + 74 + 75 + 76 + 77 asm volatile("nop"); +─── Stack ─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +[0] from 0x000003a4 in main+116 at ../../../src/main.c:68 +─── Threads ───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +[1] id -1 from 0x000003a4 in main+116 at ../../../src/main.c:68 +─── Variables ─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +68 while(0 == OSCCTRL->Dpll[0].DPLLSTATUS.bit.LOCK +─── Output/messages ───────────────────────────────────────────────────────────────────────────────────────────────────────────────── +─── Assembly ──────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── + 0x000003a2 main+114 blx r3 + 0x000003a4 main+116 adds r5, #1 + 0x000003a6 main+118 b.n 0x38e + 0x000003a8 main+120 lsls r4, r0, #15 + 0x000003aa main+122 movs r0, r0 + 0x000003ac main+124 lsls r4, r0, #15 + 0x000003ae main+126 movs r0, r0 + 0x000003b0 main+128 lsls r4, r0, #15 + 0x000003b2 main+130 movs r0, r0 + 0x000003b4 main+132 lsls r0, r1, #15 +─── Breakpoints ───────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +[1] break at 0x00000330 in ../../../src/main.c:38 for main hit 1 time +─── Expressions ───────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +─── History ───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +─── Memory ────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +─── Registers ─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── + r0 0x80000000 r1 0x00000002 r2 0x00000003 r3 0x40001000 r4 0x000119d5 r5 0x20008abc + r6 0x200059d8 r7 0x000125c1 r8 0x000125b5 r9 0x200059d8 r10 0x20005a48 r11 0x2000db94 + r12 0x00000000 sp 0x20010018 lr 0x000002f9 pc 0x000003ac xpsr 0xa1000000 fpscr 0x00000000 + msp 0x20010018 psp 0xfdff277c primask 0x00 basepri 0x00 faultmask 0x00 control 0x00 +─── Source ────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── + 59 // 0 - GCLK + 60 // 1 - XOSC32 + 61 // 2 - XOSC0 + 62 // 3 - XOSC1 + 63 OSCCTRL->Dpll[0].DPLLCTRLB.bit.REFCLK = 2; + 64 OSCCTRL->Dpll[0].DPLLCTRLA.bit.ONDEMAND = 0; + 65 OSCCTRL->Dpll[0].DPLLCTRLA.bit.ENABLE = 1; + 66 + 67 // wait for pll to be locked and ready + 68 while(0 == OSCCTRL->Dpll[0].DPLLSTATUS.bit.LOCK + 69 || 0 == OSCCTRL->Dpll[0].DPLLSTATUS.bit.CLKRDY); + 70 + 71 // Connect DPLL0 to clock generator 0 (120mhz) - frequency used by CPU, AHB, APBA, APBB + 72 GCLK->GENCTRL[0].reg = GCLK_GENCTRL_SRC_DPLL0 | GCLK_GENCTRL_DIV(1) | GCLK_GENCTRL_GENEN; + 73 while(1 == GCLK->SYNCBUSY.bit.GENCTRL0); + 74 + 75 + 76 + 77 asm volatile("nop"); + 78 for(;;) +─── Stack ─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +[0] from 0x000003ac in main+124 at ../../../src/main.c:69 +─── Threads ───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +[1] id -1 from 0x000003ac in main+124 at ../../../src/main.c:69 +─── Variables ─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +69 || 0 == OSCCTRL->Dpll[0].DPLLSTATUS.bit.CLKRDY); +─── Output/messages ───────────────────────────────────────────────────────────────────────────────────────────────────────────────── +─── Assembly ──────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── + 0x000003a8 main+120 lsls r4, r0, #15 + 0x000003aa main+122 movs r0, r0 + 0x000003ac main+124 lsls r4, r0, #15 + 0x000003ae main+126 movs r0, r0 + 0x000003b0 main+128 lsls r4, r0, #15 + 0x000003b2 main+130 movs r0, r0 + 0x000003b4 main+132 lsls r0, r1, #15 + 0x000003b6 main+134 movs r0, r0 + 0x000003b8 main+136 push {r3, r4, r5, r6, r7, lr} + 0x000003ba main+138 nop +─── Breakpoints ───────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +[1] break at 0x00000330 in ../../../src/main.c:38 for main hit 1 time +─── Expressions ───────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +─── History ───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +─── Memory ────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +─── Registers ─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── + r0 0x80000000 r1 0xc0000000 r2 0x00000003 r3 0x40001000 r4 0x000119d5 r5 0x20008abc + r6 0x200059d8 r7 0x000125c1 r8 0x000125b5 r9 0x200059d8 r10 0x20005a48 r11 0x2000db94 + r12 0x00000000 sp 0x20010018 lr 0x000002f9 pc 0x000003b2 xpsr 0x81000000 fpscr 0x00000000 + msp 0x20010018 psp 0xfdff277c primask 0x00 basepri 0x00 faultmask 0x00 control 0x00 +─── Source ────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── + 62 // 3 - XOSC1 + 63 OSCCTRL->Dpll[0].DPLLCTRLB.bit.REFCLK = 2; + 64 OSCCTRL->Dpll[0].DPLLCTRLA.bit.ONDEMAND = 0; + 65 OSCCTRL->Dpll[0].DPLLCTRLA.bit.ENABLE = 1; + 66 + 67 // wait for pll to be locked and ready + 68 while(0 == OSCCTRL->Dpll[0].DPLLSTATUS.bit.LOCK + 69 || 0 == OSCCTRL->Dpll[0].DPLLSTATUS.bit.CLKRDY); + 70 + 71 // Connect DPLL0 to clock generator 0 (120mhz) - frequency used by CPU, AHB, APBA, APBB + 72 GCLK->GENCTRL[0].reg = GCLK_GENCTRL_SRC_DPLL0 | GCLK_GENCTRL_DIV(1) | GCLK_GENCTRL_GENEN; + 73 while(1 == GCLK->SYNCBUSY.bit.GENCTRL0); + 74 + 75 + 76 + 77 asm volatile("nop"); + 78 for(;;) + 79 { + 80 + 81 } +─── Stack ─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +[0] from 0x000003b2 in main+130 at ../../../src/main.c:72 +─── Threads ───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +[1] id -1 from 0x000003b2 in main+130 at ../../../src/main.c:72 +─── Variables ─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +72 GCLK->GENCTRL[0].reg = GCLK_GENCTRL_SRC_DPLL0 | GCLK_GENCTRL_DIV(1) | GCLK_GENCTRL_GENEN; +─── Output/messages ───────────────────────────────────────────────────────────────────────────────────────────────────────────────── +─── Assembly ──────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── + 0x000003ae main+126 movs r0, r0 + 0x000003b0 main+128 lsls r4, r0, #15 + 0x000003b2 main+130 movs r0, r0 + 0x000003b4 main+132 lsls r0, r1, #15 + 0x000003b6 main+134 movs r0, r0 + 0x000003b8 main+136 push {r3, r4, r5, r6, r7, lr} + 0x000003ba main+138 nop + 0x000003bc main+140 pop {r3, r4, r5, r6, r7} + 0x000003be main+142 pop {r3} + 0x000003c0 main+144 mov lr, r3 +─── Breakpoints ───────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +[1] break at 0x00000330 in ../../../src/main.c:38 for main hit 1 time +─── Expressions ───────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +─── History ───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +─── Memory ────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +─── Registers ─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── + r0 0x80000000 r1 0xc0000000 r2 0x00010107 r3 0x40001c00 r4 0x000119d5 r5 0x20008abc + r6 0x200059d8 r7 0x000125c1 r8 0x000125b5 r9 0x200059d8 r10 0x20005a48 r11 0x2000db94 + r12 0x00000000 sp 0x20010018 lr 0x000002f9 pc 0x000003b8 xpsr 0x81000000 fpscr 0x00000000 + msp 0x20010018 psp 0xfdff277c primask 0x00 basepri 0x00 faultmask 0x00 control 0x00 +─── Source ────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── + 63 OSCCTRL->Dpll[0].DPLLCTRLB.bit.REFCLK = 2; + 64 OSCCTRL->Dpll[0].DPLLCTRLA.bit.ONDEMAND = 0; + 65 OSCCTRL->Dpll[0].DPLLCTRLA.bit.ENABLE = 1; + 66 + 67 // wait for pll to be locked and ready + 68 while(0 == OSCCTRL->Dpll[0].DPLLSTATUS.bit.LOCK + 69 || 0 == OSCCTRL->Dpll[0].DPLLSTATUS.bit.CLKRDY); + 70 + 71 // Connect DPLL0 to clock generator 0 (120mhz) - frequency used by CPU, AHB, APBA, APBB + 72 GCLK->GENCTRL[0].reg = GCLK_GENCTRL_SRC_DPLL0 | GCLK_GENCTRL_DIV(1) | GCLK_GENCTRL_GENEN; + 73 while(1 == GCLK->SYNCBUSY.bit.GENCTRL0); + 74 + 75 + 76 + 77 asm volatile("nop"); + 78 for(;;) + 79 { + 80 + 81 } + 82 return 0; +─── Stack ─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +[0] from 0x000003b8 in main+136 at ../../../src/main.c:73 +─── Threads ───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +[1] id -1 from 0x000003b8 in main+136 at ../../../src/main.c:73 +─── Variables ─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +73 while(1 == GCLK->SYNCBUSY.bit.GENCTRL0); +─── Output/messages ───────────────────────────────────────────────────────────────────────────────────────────────────────────────── +─── Assembly ──────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── + 0x000003b4 main+132 lsls r0, r1, #15 + 0x000003b6 main+134 movs r0, r0 + 0x000003b8 main+136 push {r3, r4, r5, r6, r7, lr} + 0x000003ba main+138 nop + 0x000003bc main+140 pop {r3, r4, r5, r6, r7} + 0x000003be main+142 pop {r3} + 0x000003c0 main+144 mov lr, r3 + 0x000003c2 main+146 bx lr + 0x000003c4 main+148 lsls r1, r1, #10 + 0x000003c6 main+150 movs r0, r0 +─── Breakpoints ───────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +[1] break at 0x00000330 in ../../../src/main.c:38 for main hit 1 time +─── Expressions ───────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +─── History ───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +─── Memory ────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +─── Registers ─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── + r0 0x80000000 r1 0xc0000000 r2 0x00000000 r3 0x40001c00 r4 0x000119d5 r5 0x20008abc + r6 0x200059d8 r7 0x000125c1 r8 0x000125b5 r9 0x200059d8 r10 0x20005a48 r11 0x2000db94 + r12 0x00000000 sp 0x20010018 lr 0x000002f9 pc 0x000003be xpsr 0x41000000 fpscr 0x00000000 + msp 0x20010018 psp 0xfdff277c primask 0x00 basepri 0x00 faultmask 0x00 control 0x00 +─── Source ────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── + 67 // wait for pll to be locked and ready + 68 while(0 == OSCCTRL->Dpll[0].DPLLSTATUS.bit.LOCK + 69 || 0 == OSCCTRL->Dpll[0].DPLLSTATUS.bit.CLKRDY); + 70 + 71 // Connect DPLL0 to clock generator 0 (120mhz) - frequency used by CPU, AHB, APBA, APBB + 72 GCLK->GENCTRL[0].reg = GCLK_GENCTRL_SRC_DPLL0 | GCLK_GENCTRL_DIV(1) | GCLK_GENCTRL_GENEN; + 73 while(1 == GCLK->SYNCBUSY.bit.GENCTRL0); + 74 + 75 + 76 + 77 asm volatile("nop"); + 78 for(;;) + 79 { + 80 + 81 } + 82 return 0; + 83 } +~ +~ +~ +─── Stack ─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +[0] from 0x000003be in main+142 at ../../../src/main.c:77 +─── Threads ───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +[1] id -1 from 0x000003be in main+142 at ../../../src/main.c:77 +─── Variables ─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +───────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────── +77 asm volatile("nop"); +$1 = { + bit = { + SWRST = 0, + GENCTRL0 = 0, + GENCTRL1 = 0, + GENCTRL2 = 0, + GENCTRL3 = 0, + GENCTRL4 = 0, + GENCTRL5 = 0, + GENCTRL6 = 0, + GENCTRL7 = 0, + GENCTRL8 = 0, + GENCTRL9 = 0, + GENCTRL10 = 0, + GENCTRL11 = 0 + }, + vec = { + GENCTRL = 0 + }, + reg = 0 +} diff --git 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+ 2f8: e7fe b.n 2f8 + for (; pDest < &_erelocate;) { + 2fa: 490c ldr r1, [pc, #48] ; (32c ) + 2fc: 3a04 subs r2, #4 + 2fe: 428b cmp r3, r1 + 300: d2ec bcs.n 2dc + *pDest++ = *pSrc++; + 302: f852 0f04 ldr.w r0, [r2, #4]! + 306: f843 0b04 str.w r0, [r3], #4 + 30a: e7f8 b.n 2fe + *pDest++ = 0; + 30c: f843 1b04 str.w r1, [r3], #4 + 310: e7e7 b.n 2e2 + 312: bf00 nop + 314: 00000438 .word 0x00000438 + 318: 20000000 .word 0x20000000 + 31c: 20000000 .word 0x20000000 + 320: 2000001c .word 0x2000001c + 324: 00000000 .word 0x00000000 + 328: e000ed00 .word 0xe000ed00 + 32c: 20000000 .word 0x20000000 + +00000330
: + // Run with 12mhz external crystal on XOSC0 + + // Automatic Loop Control + // 0 - disable + // 1 - enable + OSCCTRL->XOSCCTRL[0].bit.ENALC = 1; + 330: 4b24 ldr r3, [pc, #144] ; (3c4 ) + 332: 695a ldr r2, [r3, #20] + 334: f442 4200 orr.w r2, r2, #32768 ; 0x8000 + 338: 615a str r2, [r3, #20] + // Current Multiplier + // 6 - >24MHz to 48MHz + // 5 - >16MHz to 24MHz + // 4 - >8MHz to 16MHz + // 3 - 8MHz + OSCCTRL->XOSCCTRL[0].bit.IMULT = 4; + 33a: 695a ldr r2, [r3, #20] + 33c: 2104 movs r1, #4 + 33e: f361 22ce bfi r2, r1, #11, #4 + 342: 615a str r2, [r3, #20] + // 3 - >24MHz to 48MHz + // 3 - >16MHz to 24MHz + // 3 - >8MHz to 16MHz + // 2 - 8MHz + OSCCTRL->XOSCCTRL[0].bit.IPTAT = 3; + 344: 695a ldr r2, [r3, #20] + 346: f442 62c0 orr.w r2, r2, #1536 ; 0x600 + 34a: 615a str r2, [r3, #20] + OSCCTRL->XOSCCTRL[0].bit.ONDEMAND = 0; + 34c: 695a ldr r2, [r3, #20] + 34e: f36f 12c7 bfc r2, #7, #1 + 352: 615a str r2, [r3, #20] + OSCCTRL->XOSCCTRL[0].bit.XTALEN = 1; + 354: 695a ldr r2, [r3, #20] + 356: 430a orrs r2, r1 + 358: 615a str r2, [r3, #20] + OSCCTRL->XOSCCTRL[0].bit.ENABLE = 1; + 35a: 695a ldr r2, [r3, #20] + 35c: f042 0202 orr.w r2, r2, #2 + 360: 615a str r2, [r3, #20] + + while(0 == OSCCTRL->STATUS.bit.XOSCRDY0); + 362: 691a ldr r2, [r3, #16] + 364: 07d2 lsls r2, r2, #31 + 366: d5fc bpl.n 362 + + OSCCTRL->Dpll[0].DPLLRATIO.bit.LDRFRAC = 0; + 368: 6b5a ldr r2, [r3, #52] ; 0x34 + 36a: f36f 4214 bfc r2, #16, #5 + 36e: 635a str r2, [r3, #52] ; 0x34 + OSCCTRL->Dpll[0].DPLLRATIO.bit.LDR = 119; + 370: 6b5a ldr r2, [r3, #52] ; 0x34 + 372: 2177 movs r1, #119 ; 0x77 + 374: f361 020c bfi r2, r1, #0, #13 + 378: 635a str r2, [r3, #52] ; 0x34 + OSCCTRL->Dpll[0].DPLLCTRLB.bit.DIV = 5; + 37a: 6b9a ldr r2, [r3, #56] ; 0x38 + 37c: 2105 movs r1, #5 + 37e: f361 421a bfi r2, r1, #16, #11 + 382: 639a str r2, [r3, #56] ; 0x38 + // 0 - GCLK + // 1 - XOSC32 + // 2 - XOSC0 + // 3 - XOSC1 + OSCCTRL->Dpll[0].DPLLCTRLB.bit.REFCLK = 2; + 384: 6b9a ldr r2, [r3, #56] ; 0x38 + 386: 2102 movs r1, #2 + 388: f361 1247 bfi r2, r1, #5, #3 + 38c: 639a str r2, [r3, #56] ; 0x38 + OSCCTRL->Dpll[0].DPLLCTRLA.bit.ONDEMAND = 0; + 38e: f893 2030 ldrb.w r2, [r3, #48] ; 0x30 + 392: f36f 12c7 bfc r2, #7, #1 + 396: f883 2030 strb.w r2, [r3, #48] ; 0x30 + OSCCTRL->Dpll[0].DPLLCTRLA.bit.ENABLE = 1; + 39a: f893 2030 ldrb.w r2, [r3, #48] ; 0x30 + 39e: 430a orrs r2, r1 + 3a0: f883 2030 strb.w r2, [r3, #48] ; 0x30 + + // wait for pll to be locked and ready + while(0 == OSCCTRL->Dpll[0].DPLLSTATUS.bit.LOCK + 3a4: 4b07 ldr r3, [pc, #28] ; (3c4 ) + 3a6: 6c1a ldr r2, [r3, #64] ; 0x40 + 3a8: 07d0 lsls r0, r2, #31 + 3aa: d5fc bpl.n 3a6 + || 0 == OSCCTRL->Dpll[0].DPLLSTATUS.bit.CLKRDY); + 3ac: 6c1a ldr r2, [r3, #64] ; 0x40 + 3ae: 0791 lsls r1, r2, #30 + 3b0: d5f9 bpl.n 3a6 + + + // Connect DPLL0 to clock generator 0 (120mhz) - frequency used by CPU, AHB, APBA, APBB + GCLK->GENCTRL[0].reg = GCLK_GENCTRL_SRC_DPLL0 | GCLK_GENCTRL_DIV(1) | GCLK_GENCTRL_GENEN; + 3b2: 4b05 ldr r3, [pc, #20] ; (3c8 ) + 3b4: 4a05 ldr r2, [pc, #20] ; (3cc ) + 3b6: 621a str r2, [r3, #32] + while(1 == GCLK->SYNCBUSY.bit.GENCTRL0); + 3b8: 685a ldr r2, [r3, #4] + 3ba: 0752 lsls r2, r2, #29 + 3bc: d4fc bmi.n 3b8 + + + + asm volatile("nop"); + 3be: bf00 nop + 3c0: e7fe b.n 3c0 + 3c2: bf00 nop + 3c4: 40001000 .word 0x40001000 + 3c8: 40001c00 .word 0x40001c00 + 3cc: 00010107 .word 0x00010107 + +000003d0 <__libc_init_array>: + 3d0: b570 push {r4, r5, r6, lr} + 3d2: 4e0d ldr r6, [pc, #52] ; (408 <__libc_init_array+0x38>) + 3d4: 4c0d ldr r4, [pc, #52] ; (40c <__libc_init_array+0x3c>) + 3d6: 1ba4 subs r4, r4, r6 + 3d8: 10a4 asrs r4, r4, #2 + 3da: 2500 movs r5, #0 + 3dc: 42a5 cmp r5, r4 + 3de: d109 bne.n 3f4 <__libc_init_array+0x24> + 3e0: 4e0b ldr r6, [pc, #44] ; (410 <__libc_init_array+0x40>) + 3e2: 4c0c ldr r4, [pc, #48] ; (414 <__libc_init_array+0x44>) + 3e4: f000 f818 bl 418 <_init> + 3e8: 1ba4 subs r4, r4, r6 + 3ea: 10a4 asrs r4, r4, #2 + 3ec: 2500 movs r5, #0 + 3ee: 42a5 cmp r5, r4 + 3f0: d105 bne.n 3fe <__libc_init_array+0x2e> + 3f2: bd70 pop {r4, r5, r6, pc} + 3f4: f856 3025 ldr.w r3, [r6, r5, lsl #2] + 3f8: 4798 blx r3 + 3fa: 3501 adds r5, #1 + 3fc: e7ee b.n 3dc <__libc_init_array+0xc> + 3fe: f856 3025 ldr.w r3, [r6, r5, lsl #2] + 402: 4798 blx r3 + 404: 3501 adds r5, #1 + 406: e7f2 b.n 3ee <__libc_init_array+0x1e> + 408: 00000424 .word 0x00000424 + 40c: 00000424 .word 0x00000424 + 410: 00000424 .word 0x00000424 + 414: 00000428 .word 0x00000428 + +00000418 <_init>: + 418: b5f8 push {r3, r4, r5, r6, r7, lr} + 41a: bf00 nop + 41c: bcf8 pop {r3, r4, r5, r6, r7} + 41e: bc08 pop {r3} + 420: 469e mov lr, r3 + 422: 4770 bx lr + +00000424 <__init_array_start>: + 424: 00000289 .word 0x00000289 + +00000428 <_fini>: + 428: b5f8 push {r3, r4, r5, r6, r7, lr} + 42a: bf00 nop + 42c: bcf8 pop {r3, r4, r5, r6, r7} + 42e: bc08 pop {r3} + 430: 469e mov lr, r3 + 432: 4770 bx lr + +00000434 <__fini_array_start>: + 434: 00000265 .word 0x00000265 diff --git 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/storage/Shared/Documents/Projects/ePenguin/ePenguin-Software-Framework/toolchains/arm-none-eabi-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/libc_nano.a(lib_a-memset.o) + .bss 0x0000000000000000 0x0 /storage/Shared/Documents/Projects/ePenguin/ePenguin-Software-Framework/toolchains/arm-none-eabi-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/libc_nano.a(lib_a-memset.o) + .text.memset 0x0000000000000000 0x10 /storage/Shared/Documents/Projects/ePenguin/ePenguin-Software-Framework/toolchains/arm-none-eabi-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/libc_nano.a(lib_a-memset.o) + .debug_frame 0x0000000000000000 0x20 /storage/Shared/Documents/Projects/ePenguin/ePenguin-Software-Framework/toolchains/arm-none-eabi-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/libc_nano.a(lib_a-memset.o) + .ARM.attributes + 0x0000000000000000 0x2e /storage/Shared/Documents/Projects/ePenguin/ePenguin-Software-Framework/toolchains/arm-none-eabi-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/libc_nano.a(lib_a-memset.o) + .text 0x0000000000000000 0x0 /storage/Shared/Documents/Projects/ePenguin/ePenguin-Software-Framework/toolchains/arm-none-eabi-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v7e-m/crtend.o + .data 0x0000000000000000 0x0 /storage/Shared/Documents/Projects/ePenguin/ePenguin-Software-Framework/toolchains/arm-none-eabi-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v7e-m/crtend.o + .bss 0x0000000000000000 0x0 /storage/Shared/Documents/Projects/ePenguin/ePenguin-Software-Framework/toolchains/arm-none-eabi-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v7e-m/crtend.o + .eh_frame 0x0000000000000000 0x4 /storage/Shared/Documents/Projects/ePenguin/ePenguin-Software-Framework/toolchains/arm-none-eabi-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v7e-m/crtend.o + .jcr 0x0000000000000000 0x4 /storage/Shared/Documents/Projects/ePenguin/ePenguin-Software-Framework/toolchains/arm-none-eabi-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v7e-m/crtend.o + .ARM.attributes + 0x0000000000000000 0x2e /storage/Shared/Documents/Projects/ePenguin/ePenguin-Software-Framework/toolchains/arm-none-eabi-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v7e-m/crtend.o + .text 0x0000000000000000 0x0 /storage/Shared/Documents/Projects/ePenguin/ePenguin-Software-Framework/toolchains/arm-none-eabi-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v7e-m/crtn.o + .data 0x0000000000000000 0x0 /storage/Shared/Documents/Projects/ePenguin/ePenguin-Software-Framework/toolchains/arm-none-eabi-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v7e-m/crtn.o + .bss 0x0000000000000000 0x0 /storage/Shared/Documents/Projects/ePenguin/ePenguin-Software-Framework/toolchains/arm-none-eabi-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v7e-m/crtn.o + +Memory Configuration + +Name Origin Length Attributes +rom 0x0000000000000000 0x0000000000100000 xr +ram 0x0000000020000000 0x0000000000040000 xrw +bkupram 0x0000000047000000 0x0000000000002000 xrw +qspi 0x0000000004000000 0x0000000001000000 xrw +*default* 0x0000000000000000 0xffffffffffffffff + +Linker script and memory map + +LOAD /storage/Shared/Documents/Projects/ePenguin/ePenguin-Software-Framework/toolchains/arm-none-eabi-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v7e-m/crti.o +LOAD /storage/Shared/Documents/Projects/ePenguin/ePenguin-Software-Framework/toolchains/arm-none-eabi-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v7e-m/crtbegin.o +LOAD /storage/Shared/Documents/Projects/ePenguin/ePenguin-Software-Framework/toolchains/arm-none-eabi-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/crt0.o +LOAD ESF/mcu/src/startup_same54.o +LOAD ESF/mcu/src/system_same54.o +LOAD ESF/modules/core/clocks.o +LOAD ESF/modules/usart/usart.o +LOAD src/main.o +START GROUP +LOAD /storage/Shared/Documents/Projects/ePenguin/ePenguin-Software-Framework/toolchains/arm-none-eabi-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/libm.a +END GROUP +START GROUP +LOAD /storage/Shared/Documents/Projects/ePenguin/ePenguin-Software-Framework/toolchains/arm-none-eabi-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v7e-m/libgcc.a +LOAD /storage/Shared/Documents/Projects/ePenguin/ePenguin-Software-Framework/toolchains/arm-none-eabi-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/libc_nano.a +END GROUP +START GROUP +LOAD /storage/Shared/Documents/Projects/ePenguin/ePenguin-Software-Framework/toolchains/arm-none-eabi-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v7e-m/libgcc.a +LOAD /storage/Shared/Documents/Projects/ePenguin/ePenguin-Software-Framework/toolchains/arm-none-eabi-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/libc_nano.a +END GROUP +LOAD /storage/Shared/Documents/Projects/ePenguin/ePenguin-Software-Framework/toolchains/arm-none-eabi-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v7e-m/crtend.o +LOAD /storage/Shared/Documents/Projects/ePenguin/ePenguin-Software-Framework/toolchains/arm-none-eabi-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v7e-m/crtn.o + 0x0000000000010000 STACK_SIZE = DEFINED (STACK_SIZE)?STACK_SIZE:DEFINED (__stack_size__)?__stack_size__:0x10000 + +.text 0x0000000000000000 0x438 + 0x0000000000000000 . = ALIGN (0x4) + 0x0000000000000000 _sfixed = . + *(.vectors .vectors.*) + .vectors 0x0000000000000000 0x264 ESF/mcu/src/startup_same54.o + 0x0000000000000000 exception_table + *(.text .text.* .gnu.linkonce.t.*) + .text 0x0000000000000264 0x6c /storage/Shared/Documents/Projects/ePenguin/ePenguin-Software-Framework/toolchains/arm-none-eabi-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v7e-m/crtbegin.o + .text 0x00000000000002d0 0x60 ESF/mcu/src/startup_same54.o + 0x00000000000002d0 EIC_5_Handler + 0x00000000000002d0 SVCall_Handler + 0x00000000000002d0 SERCOM0_2_Handler + 0x00000000000002d0 EIC_13_Handler + 0x00000000000002d0 EVSYS_0_Handler + 0x00000000000002d0 TCC1_3_Handler + 0x00000000000002d0 DAC_3_Handler + 0x00000000000002d0 TRNG_Handler + 0x00000000000002d0 HardFault_Handler + 0x00000000000002d0 TC2_Handler + 0x00000000000002d0 PDEC_2_Handler + 0x00000000000002d0 EIC_4_Handler + 0x00000000000002d0 AC_Handler + 0x00000000000002d0 SERCOM3_1_Handler + 0x00000000000002d0 SysTick_Handler + 0x00000000000002d0 TCC2_3_Handler + 0x00000000000002d0 SERCOM3_2_Handler + 0x00000000000002d0 PendSV_Handler + 0x00000000000002d0 TC7_Handler + 0x00000000000002d0 ADC1_1_Handler + 0x00000000000002d0 EVSYS_3_Handler + 0x00000000000002d0 PDEC_0_Handler + 0x00000000000002d0 QSPI_Handler + 0x00000000000002d0 NonMaskableInt_Handler + 0x00000000000002d0 TCC0_0_Handler + 0x00000000000002d0 EIC_3_Handler + 0x00000000000002d0 MemManagement_Handler + 0x00000000000002d0 DAC_2_Handler + 0x00000000000002d0 SERCOM0_0_Handler + 0x00000000000002d0 RTC_Handler + 0x00000000000002d0 UsageFault_Handler + 0x00000000000002d0 SERCOM4_0_Handler + 0x00000000000002d0 EIC_10_Handler + 0x00000000000002d0 SERCOM0_3_Handler + 0x00000000000002d0 EIC_11_Handler + 0x00000000000002d0 EIC_9_Handler + 0x00000000000002d0 OSC32KCTRL_Handler + 0x00000000000002d0 TCC2_1_Handler + 0x00000000000002d0 SUPC_1_Handler + 0x00000000000002d0 TCC0_5_Handler + 0x00000000000002d0 TCC0_6_Handler + 0x00000000000002d0 SERCOM6_2_Handler + 0x00000000000002d0 EVSYS_1_Handler + 0x00000000000002d0 TCC1_4_Handler + 0x00000000000002d0 TC6_Handler + 0x00000000000002d0 DMAC_0_Handler + 0x00000000000002d0 WDT_Handler + 0x00000000000002d0 CAN0_Handler + 0x00000000000002d0 EIC_8_Handler + 0x00000000000002d0 EIC_15_Handler + 0x00000000000002d0 SERCOM6_0_Handler + 0x00000000000002d0 SERCOM5_0_Handler + 0x00000000000002d0 TC4_Handler + 0x00000000000002d0 TC1_Handler + 0x00000000000002d0 OSCCTRL_4_Handler + 0x00000000000002d0 SERCOM4_3_Handler + 0x00000000000002d0 EIC_12_Handler + 0x00000000000002d0 DMAC_4_Handler + 0x00000000000002d0 TCC4_2_Handler + 0x00000000000002d0 PAC_Handler + 0x00000000000002d0 TCC1_0_Handler + 0x00000000000002d0 USB_0_Handler + 0x00000000000002d0 OSCCTRL_0_Handler + 0x00000000000002d0 EIC_0_Handler + 0x00000000000002d0 OSCCTRL_3_Handler + 0x00000000000002d0 SERCOM4_1_Handler + 0x00000000000002d0 TC3_Handler + 0x00000000000002d0 Dummy_Handler + 0x00000000000002d0 TCC3_0_Handler + 0x00000000000002d0 TCC2_2_Handler + 0x00000000000002d0 SERCOM5_1_Handler + 0x00000000000002d0 TCC1_1_Handler + 0x00000000000002d0 DMAC_2_Handler + 0x00000000000002d0 ADC0_0_Handler + 0x00000000000002d0 SERCOM0_1_Handler + 0x00000000000002d0 OSCCTRL_2_Handler + 0x00000000000002d0 ADC1_0_Handler + 0x00000000000002d0 TCC1_2_Handler + 0x00000000000002d0 SERCOM7_1_Handler + 0x00000000000002d0 USB_1_Handler + 0x00000000000002d0 PM_Handler + 0x00000000000002d0 SERCOM6_3_Handler + 0x00000000000002d0 SERCOM2_3_Handler + 0x00000000000002d0 DAC_4_Handler + 0x00000000000002d0 TCC3_2_Handler + 0x00000000000002d0 SERCOM7_0_Handler + 0x00000000000002d0 TCC0_2_Handler + 0x00000000000002d0 DMAC_1_Handler + 0x00000000000002d0 TCC4_0_Handler + 0x00000000000002d0 SERCOM7_3_Handler + 0x00000000000002d0 GMAC_Handler + 0x00000000000002d0 SDHC1_Handler + 0x00000000000002d0 USB_3_Handler + 0x00000000000002d0 SERCOM7_2_Handler + 0x00000000000002d0 CAN1_Handler + 0x00000000000002d0 TCC2_0_Handler + 0x00000000000002d0 PDEC_1_Handler + 0x00000000000002d0 TCC4_1_Handler + 0x00000000000002d0 SERCOM5_3_Handler + 0x00000000000002d0 USB_2_Handler + 0x00000000000002d0 SERCOM6_1_Handler + 0x00000000000002d0 SDHC0_Handler + 0x00000000000002d0 SERCOM1_1_Handler + 0x00000000000002d0 I2S_Handler + 0x00000000000002d0 EIC_2_Handler + 0x00000000000002d0 PCC_Handler + 0x00000000000002d0 DAC_0_Handler + 0x00000000000002d0 TCC0_1_Handler + 0x00000000000002d0 SERCOM1_3_Handler + 0x00000000000002d0 EIC_6_Handler + 0x00000000000002d0 OSCCTRL_1_Handler + 0x00000000000002d0 SERCOM1_0_Handler + 0x00000000000002d0 PUKCC_Handler + 0x00000000000002d0 SERCOM2_1_Handler + 0x00000000000002d0 SERCOM1_2_Handler + 0x00000000000002d0 SERCOM3_0_Handler + 0x00000000000002d0 EIC_1_Handler + 0x00000000000002d0 SERCOM4_2_Handler + 0x00000000000002d0 EVSYS_4_Handler + 0x00000000000002d0 EIC_7_Handler + 0x00000000000002d0 NVMCTRL_1_Handler + 0x00000000000002d0 SERCOM5_2_Handler + 0x00000000000002d0 SERCOM3_3_Handler + 0x00000000000002d0 ADC0_1_Handler + 0x00000000000002d0 SERCOM2_2_Handler + 0x00000000000002d0 TCC3_1_Handler + 0x00000000000002d0 EIC_14_Handler + 0x00000000000002d0 DAC_1_Handler + 0x00000000000002d0 NVMCTRL_0_Handler + 0x00000000000002d0 MCLK_Handler + 0x00000000000002d0 EVSYS_2_Handler + 0x00000000000002d0 SUPC_0_Handler + 0x00000000000002d0 BusFault_Handler + 0x00000000000002d0 FREQM_Handler + 0x00000000000002d0 TC0_Handler + 0x00000000000002d0 TCC0_3_Handler + 0x00000000000002d0 DMAC_3_Handler + 0x00000000000002d0 DebugMonitor_Handler + 0x00000000000002d0 TCC0_4_Handler + 0x00000000000002d0 RAMECC_Handler + 0x00000000000002d0 TC5_Handler + 0x00000000000002d0 SERCOM2_0_Handler + 0x00000000000002d0 AES_Handler + 0x00000000000002d0 ICM_Handler + 0x00000000000002d2 Reset_Handler + .text.startup 0x0000000000000330 0xa0 src/main.o + 0x0000000000000330 main + .text.__libc_init_array + 0x00000000000003d0 0x48 /storage/Shared/Documents/Projects/ePenguin/ePenguin-Software-Framework/toolchains/arm-none-eabi-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/libc_nano.a(lib_a-init.o) + 0x00000000000003d0 __libc_init_array + *(.glue_7t) + .glue_7t 0x0000000000000418 0x0 linker stubs + *(.glue_7) + .glue_7 0x0000000000000418 0x0 linker stubs + *(.rodata .rodata* .gnu.linkonce.r.*) + *(.ARM.extab* .gnu.linkonce.armextab.*) + 0x0000000000000418 . = ALIGN (0x4) + *(.init) + .init 0x0000000000000418 0x4 /storage/Shared/Documents/Projects/ePenguin/ePenguin-Software-Framework/toolchains/arm-none-eabi-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v7e-m/crti.o + 0x0000000000000418 _init + .init 0x000000000000041c 0x8 /storage/Shared/Documents/Projects/ePenguin/ePenguin-Software-Framework/toolchains/arm-none-eabi-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v7e-m/crtn.o + 0x0000000000000424 . = ALIGN (0x4) + 0x0000000000000424 __preinit_array_start = . + *(.preinit_array) + 0x0000000000000424 __preinit_array_end = . + 0x0000000000000424 . = ALIGN (0x4) + 0x0000000000000424 __init_array_start = . + *(SORT(.init_array.*)) + *(.init_array) + .init_array 0x0000000000000424 0x4 /storage/Shared/Documents/Projects/ePenguin/ePenguin-Software-Framework/toolchains/arm-none-eabi-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v7e-m/crtbegin.o + 0x0000000000000428 __init_array_end = . + 0x0000000000000428 . = ALIGN (0x4) + *crtbegin.o(.ctors) + *(EXCLUDE_FILE(*crtend.o) .ctors) + *(SORT(.ctors.*)) + *crtend.o(.ctors) + 0x0000000000000428 . = ALIGN (0x4) + *(.fini) + .fini 0x0000000000000428 0x4 /storage/Shared/Documents/Projects/ePenguin/ePenguin-Software-Framework/toolchains/arm-none-eabi-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v7e-m/crti.o + 0x0000000000000428 _fini + .fini 0x000000000000042c 0x8 /storage/Shared/Documents/Projects/ePenguin/ePenguin-Software-Framework/toolchains/arm-none-eabi-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v7e-m/crtn.o + 0x0000000000000434 . = ALIGN (0x4) + 0x0000000000000434 __fini_array_start = . + *(.fini_array) + .fini_array 0x0000000000000434 0x4 /storage/Shared/Documents/Projects/ePenguin/ePenguin-Software-Framework/toolchains/arm-none-eabi-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v7e-m/crtbegin.o + *(SORT(.fini_array.*)) + 0x0000000000000438 __fini_array_end = . + *crtbegin.o(.dtors) + *(EXCLUDE_FILE(*crtend.o) .dtors) + *(SORT(.dtors.*)) + *crtend.o(.dtors) + 0x0000000000000438 . = ALIGN (0x4) + 0x0000000000000438 _efixed = . + [!provide] PROVIDE (__exidx_start, .) + +.vfp11_veneer 0x0000000000000438 0x0 + .vfp11_veneer 0x0000000000000438 0x0 linker stubs + +.v4_bx 0x0000000000000438 0x0 + .v4_bx 0x0000000000000438 0x0 linker stubs + +.iplt 0x0000000000000438 0x0 + .iplt 0x0000000000000438 0x0 /storage/Shared/Documents/Projects/ePenguin/ePenguin-Software-Framework/toolchains/arm-none-eabi-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v7e-m/crtbegin.o + +.eh_frame 0x0000000000000438 0x0 + .eh_frame 0x0000000000000438 0x0 /storage/Shared/Documents/Projects/ePenguin/ePenguin-Software-Framework/toolchains/arm-none-eabi-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v7e-m/crtbegin.o + +.rel.dyn 0x0000000000000438 0x0 + .rel.iplt 0x0000000000000438 0x0 /storage/Shared/Documents/Projects/ePenguin/ePenguin-Software-Framework/toolchains/arm-none-eabi-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v7e-m/crtbegin.o + +.jcr 0x0000000000000438 0x0 + .jcr 0x0000000000000438 0x0 /storage/Shared/Documents/Projects/ePenguin/ePenguin-Software-Framework/toolchains/arm-none-eabi-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v7e-m/crtbegin.o + +.igot.plt 0x0000000000000438 0x0 + .igot.plt 0x0000000000000438 0x0 /storage/Shared/Documents/Projects/ePenguin/ePenguin-Software-Framework/toolchains/arm-none-eabi-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v7e-m/crtbegin.o + +.ARM.exidx + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + [!provide] PROVIDE (__exidx_end, .) + 0x0000000000000438 . = ALIGN (0x4) + 0x0000000000000438 _etext = . + +.relocate 0x0000000020000000 0x0 load address 0x0000000000000438 + 0x0000000020000000 . = ALIGN (0x4) + 0x0000000020000000 _srelocate = . + *(.ramfunc .ramfunc.*) + *(.data .data.*) + 0x0000000020000000 . = ALIGN (0x4) + 0x0000000020000000 _erelocate = . + +.bkupram 0x0000000047000000 0x0 + 0x0000000047000000 . = ALIGN (0x8) + 0x0000000047000000 _sbkupram = . + *(.bkupram .bkupram.*) + 0x0000000047000000 . = ALIGN (0x8) + 0x0000000047000000 _ebkupram = . + +.qspi 0x0000000004000000 0x0 + 0x0000000004000000 . = ALIGN (0x8) + 0x0000000004000000 _sqspi = . + *(.qspi .qspi.*) + 0x0000000004000000 . = ALIGN (0x8) + 0x0000000004000000 _eqspi = . + +.bss 0x0000000020000000 0x1c + 0x0000000020000000 . = ALIGN (0x4) + 0x0000000020000000 _sbss = . + 0x0000000020000000 _szero = . + *(.bss .bss.*) + .bss 0x0000000020000000 0x1c /storage/Shared/Documents/Projects/ePenguin/ePenguin-Software-Framework/toolchains/arm-none-eabi-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v7e-m/crtbegin.o + *(COMMON) + 0x000000002000001c . = ALIGN (0x4) + 0x000000002000001c _ebss = . + 0x000000002000001c _ezero = . + +.stack 0x000000002000001c 0x10004 + 0x0000000020000020 . = ALIGN (0x8) + *fill* 0x000000002000001c 0x4 + 0x0000000020000020 _sstack = . + 0x0000000020010020 . = (. + STACK_SIZE) + *fill* 0x0000000020000020 0x10000 + 0x0000000020010020 . = ALIGN (0x8) + 0x0000000020010020 _estack = . + 0x0000000020010020 . = ALIGN (0x4) + 0x0000000020010020 _end = . +OUTPUT(same54p20a_test.elf elf32-littlearm) + +.ARM.attributes + 0x0000000000000000 0x2a + .ARM.attributes + 0x0000000000000000 0x1e /storage/Shared/Documents/Projects/ePenguin/ePenguin-Software-Framework/toolchains/arm-none-eabi-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v7e-m/crti.o + .ARM.attributes + 0x000000000000001e 0x2e /storage/Shared/Documents/Projects/ePenguin/ePenguin-Software-Framework/toolchains/arm-none-eabi-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v7e-m/crtbegin.o + .ARM.attributes + 0x000000000000004c 0x33 ESF/mcu/src/startup_same54.o + .ARM.attributes + 0x000000000000007f 0x33 src/main.o + .ARM.attributes + 0x00000000000000b2 0x2e /storage/Shared/Documents/Projects/ePenguin/ePenguin-Software-Framework/toolchains/arm-none-eabi-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/libc_nano.a(lib_a-init.o) + .ARM.attributes + 0x00000000000000e0 0x1e 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0x0000000000025e6d 0xd0 src/main.o + +.debug_line 0x0000000000000000 0x1022 + .debug_line 0x0000000000000000 0x7fe ESF/mcu/src/startup_same54.o + .debug_line 0x00000000000007fe 0x824 src/main.o + +.debug_str 0x0000000000000000 0xf139e + .debug_str 0x0000000000000000 0xf0925 ESF/mcu/src/startup_same54.o + 0xf0d09 (size before relaxing) + .debug_str 0x00000000000f0925 0xa79 src/main.o + 0xf0b9b (size before relaxing) + +.debug_frame 0x0000000000000000 0x84 + .debug_frame 0x0000000000000000 0x38 ESF/mcu/src/startup_same54.o + .debug_frame 0x0000000000000038 0x20 src/main.o + .debug_frame 0x0000000000000058 0x2c /storage/Shared/Documents/Projects/ePenguin/ePenguin-Software-Framework/toolchains/arm-none-eabi-toolchain/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/libc_nano.a(lib_a-init.o) + +.debug_ranges 0x0000000000000000 0x10 + .debug_ranges 0x0000000000000000 0x10 src/main.o diff --git a/test/same54p20a_test/.igloo/target/same54p20a/scripts/bmdebug.gdb b/test/same54p20a_test/.igloo/target/same54p20a/scripts/bmdebug.gdb new file mode 100644 index 00000000..736120dc --- /dev/null +++ b/test/same54p20a_test/.igloo/target/same54p20a/scripts/bmdebug.gdb @@ -0,0 +1,10 @@ +set pagination off +set logging file gdb.txt +set logging on +set mem inaccessible-by-default off +tar ext /dev/blackmagic_0 +mon s +attach 1 +b main +load +r diff --git a/test/same54p20a_test/.igloo/target/same54p20a/scripts/bmpush.gdb b/test/same54p20a_test/.igloo/target/same54p20a/scripts/bmpush.gdb new file mode 100644 index 00000000..8765ac09 --- /dev/null +++ b/test/same54p20a_test/.igloo/target/same54p20a/scripts/bmpush.gdb @@ -0,0 +1,13 @@ +set pagination off +set logging file gdb.txt +set logging redirect on +set logging on +tar ext /dev/blackmagic_0 +mon s +attach 1 +b main +load +r +detach +q +y diff --git a/test/same54p20a_test/.igloo/target/same54p20a/scripts/debug.gdb b/test/same54p20a_test/.igloo/target/same54p20a/scripts/debug.gdb new file mode 120000 index 00000000..23ad1da9 --- /dev/null +++ b/test/same54p20a_test/.igloo/target/same54p20a/scripts/debug.gdb @@ -0,0 +1 @@ +/storage/Shared/Documents/Projects/ePenguin/ePenguin-Software-Framework/scripts/debug.gdb \ No newline at end of file diff --git a/test/same54p20a_test/.igloo/target/same54p20a/scripts/push.gdb b/test/same54p20a_test/.igloo/target/same54p20a/scripts/push.gdb new file mode 120000 index 00000000..d7d76c3e --- /dev/null +++ b/test/same54p20a_test/.igloo/target/same54p20a/scripts/push.gdb @@ -0,0 +1 @@ +/storage/Shared/Documents/Projects/ePenguin/ePenguin-Software-Framework/scripts/push.gdb \ No newline at end of file diff --git a/arch/arm/SAME54/SAME54A/scripts/samd21e18a.cfg b/test/same54p20a_test/.igloo/target/same54p20a/scripts/same54p20a.cfg similarity index 70% rename from arch/arm/SAME54/SAME54A/scripts/samd21e18a.cfg rename to test/same54p20a_test/.igloo/target/same54p20a/scripts/same54p20a.cfg index ea7b1b04..d38dfa0f 100644 --- a/arch/arm/SAME54/SAME54A/scripts/samd21e18a.cfg +++ b/test/same54p20a_test/.igloo/target/same54p20a/scripts/same54p20a.cfg @@ -8,5 +8,5 @@ source [find interface/jlink.cfg] transport select swd # Chip Information -set CHIPNAME samd21e18a -source [find target/at91samdXX.cfg] +set CHIPNAME same54p20a +source [find target/atsame5x.cfg] diff --git a/test/same54p20a_test/.igloo/target/same54p20a/src/main.d b/test/same54p20a_test/.igloo/target/same54p20a/src/main.d new file mode 100644 index 00000000..a349aa9a --- /dev/null +++ b/test/same54p20a_test/.igloo/target/same54p20a/src/main.d @@ -0,0 +1,329 @@ +src/main.d src/main.o: ../../../src/main.c ../../../inc/igloo.h \ + ../../../ESF/mcu/inc/sam.h ../../../ESF/mcu/inc/same54p20a.h \ + /storage/Shared/Documents/Projects/ePenguin/ePenguin-Software-Framework/toolchains/arm-none-eabi-toolchain/lib/gcc/arm-none-eabi/6.3.1/include/stdint.h \ + /storage/Shared/Documents/Projects/ePenguin/ePenguin-Software-Framework/toolchains/arm-none-eabi-toolchain/arm-none-eabi/include/stdint.h \ + /storage/Shared/Documents/Projects/ePenguin/ePenguin-Software-Framework/toolchains/arm-none-eabi-toolchain/arm-none-eabi/include/machine/_default_types.h \ + /storage/Shared/Documents/Projects/ePenguin/ePenguin-Software-Framework/toolchains/arm-none-eabi-toolchain/arm-none-eabi/include/sys/features.h \ + /storage/Shared/Documents/Projects/ePenguin/ePenguin-Software-Framework/toolchains/arm-none-eabi-toolchain/arm-none-eabi/include/_newlib_version.h \ + /storage/Shared/Documents/Projects/ePenguin/ePenguin-Software-Framework/toolchains/arm-none-eabi-toolchain/arm-none-eabi/include/sys/_intsup.h \ + /storage/Shared/Documents/Projects/ePenguin/ePenguin-Software-Framework/toolchains/arm-none-eabi-toolchain/arm-none-eabi/include/sys/_stdint.h \ + ../../../ESF/common/inc/cmsis/core_cm4.h \ + ../../../ESF/common/inc/cmsis/cmsis_version.h \ + ../../../ESF/common/inc/cmsis/cmsis_compiler.h \ + ../../../ESF/common/inc/cmsis/cmsis_gcc.h \ + ../../../ESF/common/inc/cmsis/mpu_armv7.h \ + ../../../ESF/mcu/inc/system_same54.h ../../../ESF/mcu/inc/component/ac.h \ + ../../../ESF/mcu/inc/component/adc.h \ + ../../../ESF/mcu/inc/component/aes.h \ + ../../../ESF/mcu/inc/component/can.h \ + ../../../ESF/mcu/inc/component/ccl.h \ + ../../../ESF/mcu/inc/component/cmcc.h \ + ../../../ESF/mcu/inc/component/dac.h \ + ../../../ESF/mcu/inc/component/dmac.h \ + ../../../ESF/mcu/inc/component/dsu.h \ + ../../../ESF/mcu/inc/component/eic.h \ + ../../../ESF/mcu/inc/component/evsys.h \ + ../../../ESF/mcu/inc/component/freqm.h \ + ../../../ESF/mcu/inc/component/gclk.h \ + ../../../ESF/mcu/inc/component/gmac.h \ + ../../../ESF/mcu/inc/component/hmatrixb.h \ + ../../../ESF/mcu/inc/component/icm.h \ + ../../../ESF/mcu/inc/component/i2s.h \ + ../../../ESF/mcu/inc/component/mclk.h \ + ../../../ESF/mcu/inc/component/nvmctrl.h \ + ../../../ESF/mcu/inc/component/oscctrl.h \ + ../../../ESF/mcu/inc/component/osc32kctrl.h \ + ../../../ESF/mcu/inc/component/pac.h \ + ../../../ESF/mcu/inc/component/pcc.h \ + ../../../ESF/mcu/inc/component/pdec.h \ + ../../../ESF/mcu/inc/component/pm.h \ + ../../../ESF/mcu/inc/component/port.h \ + ../../../ESF/mcu/inc/component/qspi.h \ + ../../../ESF/mcu/inc/component/ramecc.h \ + ../../../ESF/mcu/inc/component/rstc.h \ + ../../../ESF/mcu/inc/component/rtc.h \ + ../../../ESF/mcu/inc/component/sdhc.h \ + ../../../ESF/mcu/inc/component/sercom.h \ + ../../../ESF/mcu/inc/component/supc.h \ + ../../../ESF/mcu/inc/component/tc.h ../../../ESF/mcu/inc/component/tcc.h \ + ../../../ESF/mcu/inc/component/trng.h \ + ../../../ESF/mcu/inc/component/usb.h \ + ../../../ESF/mcu/inc/component/wdt.h ../../../ESF/mcu/inc/instance/ac.h \ + ../../../ESF/mcu/inc/instance/adc0.h \ + ../../../ESF/mcu/inc/instance/adc1.h ../../../ESF/mcu/inc/instance/aes.h \ + ../../../ESF/mcu/inc/instance/can0.h \ + ../../../ESF/mcu/inc/instance/can1.h ../../../ESF/mcu/inc/instance/ccl.h \ + ../../../ESF/mcu/inc/instance/cmcc.h ../../../ESF/mcu/inc/instance/dac.h \ + ../../../ESF/mcu/inc/instance/dmac.h ../../../ESF/mcu/inc/instance/dsu.h \ + ../../../ESF/mcu/inc/instance/eic.h \ + ../../../ESF/mcu/inc/instance/evsys.h \ + ../../../ESF/mcu/inc/instance/freqm.h \ + ../../../ESF/mcu/inc/instance/gclk.h \ + ../../../ESF/mcu/inc/instance/gmac.h \ + ../../../ESF/mcu/inc/instance/hmatrix.h \ + ../../../ESF/mcu/inc/instance/icm.h ../../../ESF/mcu/inc/instance/i2s.h \ + ../../../ESF/mcu/inc/instance/mclk.h \ + ../../../ESF/mcu/inc/instance/nvmctrl.h \ + ../../../ESF/mcu/inc/instance/oscctrl.h \ + ../../../ESF/mcu/inc/instance/osc32kctrl.h \ + ../../../ESF/mcu/inc/instance/pac.h ../../../ESF/mcu/inc/instance/pcc.h \ + ../../../ESF/mcu/inc/instance/pdec.h ../../../ESF/mcu/inc/instance/pm.h \ + ../../../ESF/mcu/inc/instance/port.h \ + ../../../ESF/mcu/inc/instance/pukcc.h \ + ../../../ESF/mcu/inc/instance/qspi.h \ + ../../../ESF/mcu/inc/instance/ramecc.h \ + ../../../ESF/mcu/inc/instance/rstc.h ../../../ESF/mcu/inc/instance/rtc.h \ + ../../../ESF/mcu/inc/instance/sdhc0.h \ + ../../../ESF/mcu/inc/instance/sdhc1.h \ + ../../../ESF/mcu/inc/instance/sercom0.h \ + ../../../ESF/mcu/inc/instance/sercom1.h \ + ../../../ESF/mcu/inc/instance/sercom2.h \ + ../../../ESF/mcu/inc/instance/sercom3.h \ + ../../../ESF/mcu/inc/instance/sercom4.h \ + ../../../ESF/mcu/inc/instance/sercom5.h \ + ../../../ESF/mcu/inc/instance/sercom6.h \ + ../../../ESF/mcu/inc/instance/sercom7.h \ + ../../../ESF/mcu/inc/instance/supc.h ../../../ESF/mcu/inc/instance/tc0.h \ + ../../../ESF/mcu/inc/instance/tc1.h ../../../ESF/mcu/inc/instance/tc2.h \ + ../../../ESF/mcu/inc/instance/tc3.h ../../../ESF/mcu/inc/instance/tc4.h \ + ../../../ESF/mcu/inc/instance/tc5.h ../../../ESF/mcu/inc/instance/tc6.h \ + ../../../ESF/mcu/inc/instance/tc7.h ../../../ESF/mcu/inc/instance/tcc0.h \ + ../../../ESF/mcu/inc/instance/tcc1.h \ + ../../../ESF/mcu/inc/instance/tcc2.h \ + ../../../ESF/mcu/inc/instance/tcc3.h \ + ../../../ESF/mcu/inc/instance/tcc4.h \ + ../../../ESF/mcu/inc/instance/trng.h ../../../ESF/mcu/inc/instance/usb.h \ + ../../../ESF/mcu/inc/instance/wdt.h \ + ../../../ESF/mcu/inc/pio/same54p20a.h ../../../cfg/conf_clocks.h + +../../../inc/igloo.h: + +../../../ESF/mcu/inc/sam.h: + +../../../ESF/mcu/inc/same54p20a.h: + +/storage/Shared/Documents/Projects/ePenguin/ePenguin-Software-Framework/toolchains/arm-none-eabi-toolchain/lib/gcc/arm-none-eabi/6.3.1/include/stdint.h: + +/storage/Shared/Documents/Projects/ePenguin/ePenguin-Software-Framework/toolchains/arm-none-eabi-toolchain/arm-none-eabi/include/stdint.h: + +/storage/Shared/Documents/Projects/ePenguin/ePenguin-Software-Framework/toolchains/arm-none-eabi-toolchain/arm-none-eabi/include/machine/_default_types.h: + +/storage/Shared/Documents/Projects/ePenguin/ePenguin-Software-Framework/toolchains/arm-none-eabi-toolchain/arm-none-eabi/include/sys/features.h: + +/storage/Shared/Documents/Projects/ePenguin/ePenguin-Software-Framework/toolchains/arm-none-eabi-toolchain/arm-none-eabi/include/_newlib_version.h: + +/storage/Shared/Documents/Projects/ePenguin/ePenguin-Software-Framework/toolchains/arm-none-eabi-toolchain/arm-none-eabi/include/sys/_intsup.h: + +/storage/Shared/Documents/Projects/ePenguin/ePenguin-Software-Framework/toolchains/arm-none-eabi-toolchain/arm-none-eabi/include/sys/_stdint.h: + +../../../ESF/common/inc/cmsis/core_cm4.h: + +../../../ESF/common/inc/cmsis/cmsis_version.h: + +../../../ESF/common/inc/cmsis/cmsis_compiler.h: + +../../../ESF/common/inc/cmsis/cmsis_gcc.h: + +../../../ESF/common/inc/cmsis/mpu_armv7.h: + +../../../ESF/mcu/inc/system_same54.h: + +../../../ESF/mcu/inc/component/ac.h: + +../../../ESF/mcu/inc/component/adc.h: + +../../../ESF/mcu/inc/component/aes.h: + +../../../ESF/mcu/inc/component/can.h: + +../../../ESF/mcu/inc/component/ccl.h: + +../../../ESF/mcu/inc/component/cmcc.h: + +../../../ESF/mcu/inc/component/dac.h: + +../../../ESF/mcu/inc/component/dmac.h: + +../../../ESF/mcu/inc/component/dsu.h: + +../../../ESF/mcu/inc/component/eic.h: + +../../../ESF/mcu/inc/component/evsys.h: + +../../../ESF/mcu/inc/component/freqm.h: + +../../../ESF/mcu/inc/component/gclk.h: + +../../../ESF/mcu/inc/component/gmac.h: + +../../../ESF/mcu/inc/component/hmatrixb.h: + +../../../ESF/mcu/inc/component/icm.h: + +../../../ESF/mcu/inc/component/i2s.h: + +../../../ESF/mcu/inc/component/mclk.h: + +../../../ESF/mcu/inc/component/nvmctrl.h: + +../../../ESF/mcu/inc/component/oscctrl.h: + +../../../ESF/mcu/inc/component/osc32kctrl.h: + +../../../ESF/mcu/inc/component/pac.h: + +../../../ESF/mcu/inc/component/pcc.h: + +../../../ESF/mcu/inc/component/pdec.h: + +../../../ESF/mcu/inc/component/pm.h: + +../../../ESF/mcu/inc/component/port.h: + +../../../ESF/mcu/inc/component/qspi.h: + +../../../ESF/mcu/inc/component/ramecc.h: + +../../../ESF/mcu/inc/component/rstc.h: + +../../../ESF/mcu/inc/component/rtc.h: + +../../../ESF/mcu/inc/component/sdhc.h: + +../../../ESF/mcu/inc/component/sercom.h: + +../../../ESF/mcu/inc/component/supc.h: + +../../../ESF/mcu/inc/component/tc.h: + +../../../ESF/mcu/inc/component/tcc.h: + +../../../ESF/mcu/inc/component/trng.h: + +../../../ESF/mcu/inc/component/usb.h: + +../../../ESF/mcu/inc/component/wdt.h: + +../../../ESF/mcu/inc/instance/ac.h: + +../../../ESF/mcu/inc/instance/adc0.h: + +../../../ESF/mcu/inc/instance/adc1.h: + +../../../ESF/mcu/inc/instance/aes.h: + +../../../ESF/mcu/inc/instance/can0.h: + +../../../ESF/mcu/inc/instance/can1.h: + +../../../ESF/mcu/inc/instance/ccl.h: + +../../../ESF/mcu/inc/instance/cmcc.h: + +../../../ESF/mcu/inc/instance/dac.h: + +../../../ESF/mcu/inc/instance/dmac.h: + +../../../ESF/mcu/inc/instance/dsu.h: + +../../../ESF/mcu/inc/instance/eic.h: + +../../../ESF/mcu/inc/instance/evsys.h: + +../../../ESF/mcu/inc/instance/freqm.h: + +../../../ESF/mcu/inc/instance/gclk.h: + +../../../ESF/mcu/inc/instance/gmac.h: + +../../../ESF/mcu/inc/instance/hmatrix.h: + +../../../ESF/mcu/inc/instance/icm.h: + +../../../ESF/mcu/inc/instance/i2s.h: + +../../../ESF/mcu/inc/instance/mclk.h: + +../../../ESF/mcu/inc/instance/nvmctrl.h: + +../../../ESF/mcu/inc/instance/oscctrl.h: + +../../../ESF/mcu/inc/instance/osc32kctrl.h: + +../../../ESF/mcu/inc/instance/pac.h: + +../../../ESF/mcu/inc/instance/pcc.h: + +../../../ESF/mcu/inc/instance/pdec.h: + +../../../ESF/mcu/inc/instance/pm.h: + +../../../ESF/mcu/inc/instance/port.h: + +../../../ESF/mcu/inc/instance/pukcc.h: + +../../../ESF/mcu/inc/instance/qspi.h: + +../../../ESF/mcu/inc/instance/ramecc.h: + +../../../ESF/mcu/inc/instance/rstc.h: + +../../../ESF/mcu/inc/instance/rtc.h: + +../../../ESF/mcu/inc/instance/sdhc0.h: + +../../../ESF/mcu/inc/instance/sdhc1.h: + +../../../ESF/mcu/inc/instance/sercom0.h: + +../../../ESF/mcu/inc/instance/sercom1.h: + +../../../ESF/mcu/inc/instance/sercom2.h: + +../../../ESF/mcu/inc/instance/sercom3.h: + +../../../ESF/mcu/inc/instance/sercom4.h: + +../../../ESF/mcu/inc/instance/sercom5.h: + +../../../ESF/mcu/inc/instance/sercom6.h: + +../../../ESF/mcu/inc/instance/sercom7.h: + +../../../ESF/mcu/inc/instance/supc.h: + +../../../ESF/mcu/inc/instance/tc0.h: + +../../../ESF/mcu/inc/instance/tc1.h: + +../../../ESF/mcu/inc/instance/tc2.h: + +../../../ESF/mcu/inc/instance/tc3.h: + +../../../ESF/mcu/inc/instance/tc4.h: + +../../../ESF/mcu/inc/instance/tc5.h: + +../../../ESF/mcu/inc/instance/tc6.h: + +../../../ESF/mcu/inc/instance/tc7.h: + +../../../ESF/mcu/inc/instance/tcc0.h: + +../../../ESF/mcu/inc/instance/tcc1.h: + +../../../ESF/mcu/inc/instance/tcc2.h: + +../../../ESF/mcu/inc/instance/tcc3.h: + +../../../ESF/mcu/inc/instance/tcc4.h: + +../../../ESF/mcu/inc/instance/trng.h: + +../../../ESF/mcu/inc/instance/usb.h: + +../../../ESF/mcu/inc/instance/wdt.h: + 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zFx%|+Z`RZvBDAs5=dbBo5a1%z{cdxy8((-I4-qCqYJ4pYMuI6iDvG{2v^Zae$8CWoc!a@-`k|tH5e)XUV(bRVjhZ{@|&MX)$^)FX}K&EYh>=MydSHsWjoQQ`qgt< gZa;|r3tYwAB=Uiw~5QV$KuZWbTof3l@wIdiOK^QwSMx^s{ffj}u9yVn(Ha5dkKW zl(QfR9?6px-0Flg;Q^{zR60xFP;zdUlp=oRanRH7{|B~cihND+^lsGILFNa`o@ibZ`=s@$Bi8FwaU4==n9WcBlEmH|>VM=p*Z&!0=2EEYdNJ&oHhK_EI*jKhR+~-S@k$ G4SxVBkNuYb literal 0 HcmV?d00001 diff --git a/test/same54p20a_test/inc/igloo.h b/test/same54p20a_test/inc/igloo.h new file mode 100644 index 00000000..83fd15c4 --- /dev/null +++ b/test/same54p20a_test/inc/igloo.h @@ -0,0 +1,5 @@ +#ifdef __SAME54P20A__ + #include "sam.h" +#endif + +#include "conf_clocks.h" diff --git a/test/same54p20a_test/src/main.c b/test/same54p20a_test/src/main.c new file mode 100644 index 00000000..cbeb5eea --- /dev/null +++ b/test/same54p20a_test/src/main.c @@ -0,0 +1,82 @@ +#include "igloo.h" + +int main() +{ + // HRI_NVMCTRL_SET_CTRLA_RWS_bf + // osc32kctrl_init + // oscctrl_init + // mclk_init + // if GCLK_INIT_1ST + // gclk_init_generators_by_freq FIRST + // endif + // oscctrl_init_referenced_generators + // gclk_init_generators_by_fref LAST + // + // if dmac enable + // hri_mclk_set_AHBMASK_DMAC_bit + // dma init + // endif + + + // if CONF_PORT_EVCTRL_PORT_0 | CONF_PORT_EVCTRL_PORT_1 | 2 | 3 + // port event init + // endif + + // if CONF_CMCC_ENABLE + // cache init + // endif + + + + // Run with 12mhz external crystal on XOSC0 + + // Automatic Loop Control + // 0 - disable + // 1 - enable + OSCCTRL->XOSCCTRL[0].bit.ENALC = 1; + // Current Multiplier + // 6 - >24MHz to 48MHz + // 5 - >16MHz to 24MHz + // 4 - >8MHz to 16MHz + // 3 - 8MHz + OSCCTRL->XOSCCTRL[0].bit.IMULT = 4; + // 3 - >24MHz to 48MHz + // 3 - >16MHz to 24MHz + // 3 - >8MHz to 16MHz + // 2 - 8MHz + OSCCTRL->XOSCCTRL[0].bit.IPTAT = 3; + OSCCTRL->XOSCCTRL[0].bit.ONDEMAND = 0; + OSCCTRL->XOSCCTRL[0].bit.XTALEN = 1; + OSCCTRL->XOSCCTRL[0].bit.ENABLE = 1; + + while(0 == OSCCTRL->STATUS.bit.XOSCRDY0); + + OSCCTRL->Dpll[0].DPLLRATIO.bit.LDRFRAC = 0; + OSCCTRL->Dpll[0].DPLLRATIO.bit.LDR = 119; + OSCCTRL->Dpll[0].DPLLCTRLB.bit.DIV = 5; + // 0 - GCLK + // 1 - XOSC32 + // 2 - XOSC0 + // 3 - XOSC1 + OSCCTRL->Dpll[0].DPLLCTRLB.bit.REFCLK = 2; + OSCCTRL->Dpll[0].DPLLCTRLA.bit.ONDEMAND = 0; + OSCCTRL->Dpll[0].DPLLCTRLA.bit.ENABLE = 1; + + // wait for pll to be locked and ready + while(0 == OSCCTRL->Dpll[0].DPLLSTATUS.bit.LOCK + || 0 == OSCCTRL->Dpll[0].DPLLSTATUS.bit.CLKRDY); + + + // Connect DPLL0 to clock generator 0 (120mhz) - frequency used by CPU, AHB, APBA, APBB + GCLK->GENCTRL[0].reg = GCLK_GENCTRL_SRC_DPLL0 | GCLK_GENCTRL_DIV(1) | GCLK_GENCTRL_GENEN; + while(1 == GCLK->SYNCBUSY.bit.GENCTRL0); + + + + asm volatile("nop"); + for(;;) + { + + } + return 0; +} diff --git a/test/scripts/bmdebug.gdb b/test/scripts/bmdebug.gdb new file mode 100644 index 00000000..dac76658 --- /dev/null +++ b/test/scripts/bmdebug.gdb @@ -0,0 +1,9 @@ +set pagination off +set logging file gdb.txt +set logging on +tar ext /dev/blackmagic_0 +mon s +attach 1 +b main +load +r diff --git a/test/scripts/bmpush.gdb b/test/scripts/bmpush.gdb new file mode 100644 index 00000000..8765ac09 --- /dev/null +++ b/test/scripts/bmpush.gdb @@ -0,0 +1,13 @@ +set pagination off +set logging file gdb.txt +set logging redirect on +set logging on +tar ext /dev/blackmagic_0 +mon s +attach 1 +b main +load +r +detach +q +y diff --git a/test/scripts/debug.gdb b/test/scripts/debug.gdb new file mode 120000 index 00000000..23ad1da9 --- /dev/null +++ b/test/scripts/debug.gdb @@ -0,0 +1 @@ +/storage/Shared/Documents/Projects/ePenguin/ePenguin-Software-Framework/scripts/debug.gdb \ No newline at end of file diff --git a/test/scripts/push.gdb b/test/scripts/push.gdb new file mode 120000 index 00000000..d7d76c3e --- /dev/null +++ b/test/scripts/push.gdb @@ -0,0 +1 @@ +/storage/Shared/Documents/Projects/ePenguin/ePenguin-Software-Framework/scripts/push.gdb \ No newline at end of file diff --git a/test/scripts/same54p20a.cfg b/test/scripts/same54p20a.cfg new file mode 100644 index 00000000..d38dfa0f --- /dev/null +++ b/test/scripts/same54p20a.cfg @@ -0,0 +1,12 @@ +# +# ePenguin Generated OpenOCD Config Script +# + + +# Transport Select +source [find interface/jlink.cfg] +transport select swd + +# Chip Information +set CHIPNAME same54p20a +source [find target/atsame5x.cfg]

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... + 2c: d1 02 00 00 d1 02 00 00 00 00 00 00 d1 02 00 00 ................ + 3c: d1 02 00 00 d1 02 00 00 d1 02 00 00 d1 02 00 00 ................ + 4c: d1 02 00 00 d1 02 00 00 d1 02 00 00 d1 02 00 00 ................ + 5c: d1 02 00 00 d1 02 00 00 d1 02 00 00 d1 02 00 00 ................ + 6c: d1 02 00 00 d1 02 00 00 d1 02 00 00 d1 02 00 00 ................ + 7c: d1 02 00 00 d1 02 00 00 d1 02 00 00 d1 02 00 00 ................ + 8c: d1 02 00 00 d1 02 00 00 d1 02 00 00 d1 02 00 00 ................ + 9c: d1 02 00 00 d1 02 00 00 d1 02 00 00 d1 02 00 00 ................ + ac: d1 02 00 00 d1 02 00 00 d1 02 00 00 d1 02 00 00 ................ + bc: d1 02 00 00 d1 02 00 00 d1 02 00 00 d1 02 00 00 ................ + cc: d1 02 00 00 d1 02 00 00 d1 02 00 00 d1 02 00 00 ................ + dc: d1 02 00 00 d1 02 00 00 d1 02 00 00 00 00 00 00 ................ + ... + f4: d1 02 00 00 d1 02 00 00 d1 02 00 00 d1 02 00 00 ................ + 104: d1 02 00 00 d1 02 00 00 d1 02 00 00 d1 02 00 00 ................ + 114: d1 02 00 00 d1 02 00 00 d1 02 00 00 d1 02 00 00 ................ + 124: d1 02 00 00 d1 02 00 00 d1 02 00 00 d1 02 00 00 ................ + 134: d1 02 00 00 d1 02 00 00 d1 02 00 00 d1 02 00 00 ................ + 144: d1 02 00 00 d1 02 00 00 d1 02 00 00 d1 02 00 00 ................ + 154: d1 02 00 00 d1 02 00 00 d1 02 00 00 d1 02 00 00 ................ + 164: d1 02 00 00 d1 02 00 00 d1 02 00 00 d1 02 00 00 ................ + 174: d1 02 00 00 d1 02 00 00 d1 02 00 00 d1 02 00 00 ................ + 184: d1 02 00 00 d1 02 00 00 d1 02 00 00 d1 02 00 00 ................ + 194: d1 02 00 00 d1 02 00 00 d1 02 00 00 d1 02 00 00 ................ + 1a4: d1 02 00 00 d1 02 00 00 d1 02 00 00 d1 02 00 00 ................ + 1b4: d1 02 00 00 d1 02 00 00 d1 02 00 00 d1 02 00 00 ................ + 1c4: d1 02 00 00 d1 02 00 00 d1 02 00 00 d1 02 00 00 ................ + 1d4: d1 02 00 00 d1 02 00 00 d1 02 00 00 d1 02 00 00 ................ + 1e4: d1 02 00 00 d1 02 00 00 d1 02 00 00 d1 02 00 00 ................ + 1f4: d1 02 00 00 d1 02 00 00 d1 02 00 00 d1 02 00 00 ................ + 204: d1 02 00 00 d1 02 00 00 d1 02 00 00 d1 02 00 00 ................ + 214: d1 02 00 00 d1 02 00 00 d1 02 00 00 d1 02 00 00 ................ + 224: d1 02 00 00 d1 02 00 00 d1 02 00 00 d1 02 00 00 ................ + 234: d1 02 00 00 d1 02 00 00 d1 02 00 00 d1 02 00 00 ................ + 244: d1 02 00 00 d1 02 00 00 d1 02 00 00 d1 02 00 00 ................ + 254: d1 02 00 00 d1 02 00 00 d1 02 00 00 d1 02 00 00 ................ + +00000264 <__do_global_dtors_aux>: + 264: b510 push {r4, lr} + 266: 4c05 ldr r4, [pc, #20] ; (27c <__do_global_dtors_aux+0x18>) + 268: 7823 ldrb r3, [r4, #0] + 26a: b933 cbnz r3, 27a <__do_global_dtors_aux+0x16> + 26c: 4b04 ldr r3, [pc, #16] ; (280 <__do_global_dtors_aux+0x1c>) + 26e: b113 cbz r3, 276 <__do_global_dtors_aux+0x12> + 270: 4804 ldr r0, [pc, #16] ; (284 <__do_global_dtors_aux+0x20>) + 272: f3af 8000 nop.w + 276: 2301 movs r3, #1 + 278: 7023 strb r3, [r4, #0] + 27a: bd10 pop {r4, pc} + 27c: 20000000 .word 0x20000000 + 280: 00000000 .word 0x00000000 + 284: 00000438 .word 0x00000438 + +00000288 : + 288: 4b0c ldr r3, [pc, #48] ; (2bc ) + 28a: b143 cbz r3, 29e + 28c: 480c ldr r0, [pc, #48] ; (2c0 ) + 28e: 490d ldr r1, [pc, #52] ; (2c4 ) + 290: b510 push {r4, lr} + 292: f3af 8000 nop.w + 296: 480c ldr r0, [pc, #48] ; (2c8 ) + 298: 6803 ldr r3, [r0, #0] + 29a: b923 cbnz r3, 2a6 + 29c: bd10 pop {r4, pc} + 29e: 480a ldr r0, [pc, #40] ; (2c8 ) + 2a0: 6803 ldr r3, [r0, #0] + 2a2: b933 cbnz r3, 2b2 + 2a4: 4770 bx lr + 2a6: 4b09 ldr r3, [pc, #36] ; (2cc ) + 2a8: 2b00 cmp r3, #0 + 2aa: d0f7 beq.n 29c + 2ac: e8bd 4010 ldmia.w sp!, {r4, lr} + 2b0: 4718 bx r3 + 2b2: 4b06 ldr r3, [pc, #24] ; (2cc ) + 2b4: 2b00 cmp r3, #0 + 2b6: d0f5 beq.n 2a4 + 2b8: 4718 bx r3 + 2ba: bf00 nop + 2bc: 00000000 .word 0x00000000 + 2c0: 00000438 .word 0x00000438 + 2c4: 20000004 .word 0x20000004 + 2c8: 00000438 .word 0x00000438 + 2cc: 00000000 .word 0x00000000 + +000002d0 : + +/** + * \brief Default interrupt handler for unused IRQs. + */ +void Dummy_Handler(void) +{ + 2d0: e7fe b.n 2d0 + +000002d2 : +{ + 2d2: b508 push {r3, lr} + if (pSrc != pDest) { + 2d4: 4a0f ldr r2, [pc, #60] ; (314 ) + 2d6: 4b10 ldr r3, [pc, #64] ; (318 ) + 2d8: 429a cmp r2, r3 + 2da: d10e bne.n 2fa +{ + 2dc: 4b0f ldr r3, [pc, #60] ; (31c ) + for (pDest = &_szero; pDest < &_ezero;) { + 2de: 4a10 ldr r2, [pc, #64] ; (320 ) + *pDest++ = 0; + 2e0: 2100 movs r1, #0 + for (pDest = &_szero; pDest < &_ezero;) { + 2e2: 4293 cmp r3, r2 + 2e4: d312 bcc.n 30c + SCB->VTOR = ((uint32_t) pSrc & SCB_VTOR_TBLOFF_Msk); + 2e6: 4b0f ldr r3, [pc, #60] ; (324 ) + 2e8: 4a0f ldr r2, [pc, #60] ; (328 ) + 2ea: f023 037f bic.w r3, r3, #127 ; 0x7f + 2ee: 6093 str r3, [r2, #8] + __libc_init_array(); + 2f0: f000 f86e bl 3d0 <__libc_init_array> + main(); + 2f4: f000 f81c bl 330