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62 lines
3.1 KiB
C
62 lines
3.1 KiB
C
/**
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* \file
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*
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* \brief Instance description for MCLK
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*
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* Copyright (c) 2019 Microchip Technology Inc.
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*
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* \asf_license_start
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*
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* \page License
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed under the Apache License, Version 2.0 (the "License"); you may
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* not use this file except in compliance with the License.
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* You may obtain a copy of the Licence at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an AS IS BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*
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* \asf_license_stop
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*
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*/
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#ifndef _SAME54_MCLK_INSTANCE_
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#define _SAME54_MCLK_INSTANCE_
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/* ========== Register definition for MCLK peripheral ========== */
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#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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#define REG_MCLK_INTENCLR (0x40000801) /**< \brief (MCLK) Interrupt Enable Clear */
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#define REG_MCLK_INTENSET (0x40000802) /**< \brief (MCLK) Interrupt Enable Set */
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#define REG_MCLK_INTFLAG (0x40000803) /**< \brief (MCLK) Interrupt Flag Status and Clear */
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#define REG_MCLK_HSDIV (0x40000804) /**< \brief (MCLK) HS Clock Division */
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#define REG_MCLK_CPUDIV (0x40000805) /**< \brief (MCLK) CPU Clock Division */
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#define REG_MCLK_AHBMASK (0x40000810) /**< \brief (MCLK) AHB Mask */
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#define REG_MCLK_APBAMASK (0x40000814) /**< \brief (MCLK) APBA Mask */
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#define REG_MCLK_APBBMASK (0x40000818) /**< \brief (MCLK) APBB Mask */
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#define REG_MCLK_APBCMASK (0x4000081C) /**< \brief (MCLK) APBC Mask */
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#define REG_MCLK_APBDMASK (0x40000820) /**< \brief (MCLK) APBD Mask */
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#else
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#define REG_MCLK_INTENCLR (*(RwReg8 *)0x40000801UL) /**< \brief (MCLK) Interrupt Enable Clear */
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#define REG_MCLK_INTENSET (*(RwReg8 *)0x40000802UL) /**< \brief (MCLK) Interrupt Enable Set */
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#define REG_MCLK_INTFLAG (*(RwReg8 *)0x40000803UL) /**< \brief (MCLK) Interrupt Flag Status and Clear */
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#define REG_MCLK_HSDIV (*(RoReg8 *)0x40000804UL) /**< \brief (MCLK) HS Clock Division */
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#define REG_MCLK_CPUDIV (*(RwReg8 *)0x40000805UL) /**< \brief (MCLK) CPU Clock Division */
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#define REG_MCLK_AHBMASK (*(RwReg *)0x40000810UL) /**< \brief (MCLK) AHB Mask */
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#define REG_MCLK_APBAMASK (*(RwReg *)0x40000814UL) /**< \brief (MCLK) APBA Mask */
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#define REG_MCLK_APBBMASK (*(RwReg *)0x40000818UL) /**< \brief (MCLK) APBB Mask */
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#define REG_MCLK_APBCMASK (*(RwReg *)0x4000081CUL) /**< \brief (MCLK) APBC Mask */
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#define REG_MCLK_APBDMASK (*(RwReg *)0x40000820UL) /**< \brief (MCLK) APBD Mask */
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#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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/* ========== Instance parameters for MCLK peripheral ========== */
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#define MCLK_SYSTEM_CLOCK 48000000 // System Clock Frequency at Reset
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#endif /* _SAME54_MCLK_INSTANCE_ */
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