updated target manifest for more mcu support
penguin
4 years ago
parent
a4611500fb
commit
df71b555b0
@ -0,0 +1,160 @@
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/**
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* \file
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*
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* \brief GCC linker script (flash) for ATSAME70J19
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*
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* Copyright (c) 2020 Microchip Technology Inc.
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*
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* \license_start
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*
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* \page License
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*
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* \license_stop
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*
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*/
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/*------------------------------------------------------------------------------
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* Linker script for running in internal FLASH on the ATSAME70J19
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*----------------------------------------------------------------------------*/
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OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
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OUTPUT_ARCH(arm)
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SEARCH_DIR(.)
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/* Memory Spaces Definitions */
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MEMORY
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{
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rom (rx) : ORIGIN = 0x00400000, LENGTH = 0x00080000 /* rom, 524288K */
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ram (rwx) : ORIGIN = 0x20400000, LENGTH = 0x00040000 /* ram, 262144K */
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}
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/* The stack size used by the application. NOTE: you need to adjust according to your application. */
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STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x0400;
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/* The heapsize used by the application. NOTE: you need to adjust according to your application. */
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HEAP_SIZE = DEFINED(HEAP_SIZE) ? HEAP_SIZE : DEFINED(__heap_size__) ? __heap_size__ : 0x0200;
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/* Section Definitions */
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SECTIONS
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{
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.text :
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{
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. = ALIGN(4);
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_sfixed = .;
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KEEP(*(.vectors .vectors.*))
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*(.text .text.* .gnu.linkonce.t.*)
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*(.glue_7t) *(.glue_7)
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*(.rodata .rodata* .gnu.linkonce.r.*)
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*(.ARM.extab* .gnu.linkonce.armextab.*)
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/* Support C constructors, and C destructors in both user code
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and the C library. This also provides support for C++ code. */
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. = ALIGN(4);
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KEEP(*(.init))
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. = ALIGN(4);
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__preinit_array_start = .;
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KEEP (*(.preinit_array))
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__preinit_array_end = .;
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. = ALIGN(4);
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__init_array_start = .;
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KEEP (*(SORT(.init_array.*)))
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KEEP (*(.init_array))
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__init_array_end = .;
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. = ALIGN(4);
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KEEP (*crtbegin.o(.ctors))
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KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
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KEEP (*(SORT(.ctors.*)))
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KEEP (*crtend.o(.ctors))
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. = ALIGN(4);
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KEEP(*(.fini))
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. = ALIGN(4);
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__fini_array_start = .;
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KEEP (*(.fini_array))
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KEEP (*(SORT(.fini_array.*)))
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__fini_array_end = .;
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||||
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||||
KEEP (*crtbegin.o(.dtors))
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KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
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KEEP (*(SORT(.dtors.*)))
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KEEP (*crtend.o(.dtors))
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. = ALIGN(4);
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_efixed = .; /* End of text section */
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} > rom
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/* .ARM.exidx is sorted, so has to go in its own output section. */
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PROVIDE_HIDDEN (__exidx_start = .);
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.ARM.exidx :
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{
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*(.ARM.exidx* .gnu.linkonce.armexidx.*)
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} > rom
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PROVIDE_HIDDEN (__exidx_end = .);
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. = ALIGN(4);
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_etext = .;
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.relocate : AT (_etext)
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{
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. = ALIGN(4);
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_srelocate = .;
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*(.ramfunc .ramfunc.*);
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*(.data .data.*);
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. = ALIGN(4);
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_erelocate = .;
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} > ram
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/* .bss section which is used for uninitialized data */
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.bss (NOLOAD) :
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{
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. = ALIGN(4);
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_sbss = . ;
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_szero = .;
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*(.bss .bss.*)
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*(COMMON)
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. = ALIGN(4);
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_ebss = . ;
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_ezero = .;
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} > ram
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/* heap section */
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.heap (NOLOAD):
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{
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. = ALIGN(8);
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_sheap = .;
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. = . + HEAP_SIZE;
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. = ALIGN(8);
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_eheap = .;
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} > ram
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/* stack section */
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.stack (NOLOAD):
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{
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. = ALIGN(8);
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_sstack = .;
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. = . + STACK_SIZE;
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. = ALIGN(8);
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_estack = .;
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} > ram
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. = ALIGN(4);
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_end = . ;
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_ram_end_ = ORIGIN(ram) + LENGTH(ram) - 1 ;
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}
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@ -0,0 +1,161 @@
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/**
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* \file
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*
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* \brief GCC linker script (sram) for ATSAME70J19
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*
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* Copyright (c) 2020 Microchip Technology Inc.
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*
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* \license_start
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*
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* \page License
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
|
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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||||
* Unless required by applicable law or agreed to in writing, software
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||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*
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* \license_stop
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*
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*/
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/*------------------------------------------------------------------------------
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* Linker script for running in internal SRAM on the ATSAME70J19
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*----------------------------------------------------------------------------*/
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OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
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OUTPUT_ARCH(arm)
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SEARCH_DIR(.)
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/* Memory Spaces Definitions */
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MEMORY
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{
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||||
rom (rx) : ORIGIN = 0x00400000, LENGTH = 0x00080000 /* rom, 524288K */
|
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ram (rwx) : ORIGIN = 0x20400000, LENGTH = 0x00040000 /* ram, 262144K */
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}
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/* The stack size used by the application. NOTE: you need to adjust according to your application. */
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STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x0400;
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||||
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||||
/* The heapsize used by the application. NOTE: you need to adjust according to your application. */
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||||
HEAP_SIZE = DEFINED(HEAP_SIZE) ? HEAP_SIZE : DEFINED(__heap_size__) ? __heap_size__ : 0x0200;
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||||
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||||
/* Section Definitions */
|
||||
SECTIONS
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||||
{
|
||||
.text :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_sfixed = .;
|
||||
KEEP(*(.vectors .vectors.*))
|
||||
*(.text .text.* .gnu.linkonce.t.*)
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||||
*(.glue_7t) *(.glue_7)
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*(.rodata .rodata* .gnu.linkonce.r.*)
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*(.ARM.extab* .gnu.linkonce.armextab.*)
|
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|
||||
/* Support C constructors, and C destructors in both user code
|
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and the C library. This also provides support for C++ code. */
|
||||
. = ALIGN(4);
|
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KEEP(*(.init))
|
||||
. = ALIGN(4);
|
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__preinit_array_start = .;
|
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KEEP (*(.preinit_array))
|
||||
__preinit_array_end = .;
|
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|
||||
. = ALIGN(4);
|
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__init_array_start = .;
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KEEP (*(SORT(.init_array.*)))
|
||||
KEEP (*(.init_array))
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||||
__init_array_end = .;
|
||||
|
||||
. = ALIGN(4);
|
||||
KEEP (*crtbegin.o(.ctors))
|
||||
KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
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||||
KEEP (*(SORT(.ctors.*)))
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||||
KEEP (*crtend.o(.ctors))
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. = ALIGN(4);
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KEEP(*(.fini))
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. = ALIGN(4);
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__fini_array_start = .;
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KEEP (*(.fini_array))
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KEEP (*(SORT(.fini_array.*)))
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__fini_array_end = .;
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||||
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||||
KEEP (*crtbegin.o(.dtors))
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KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
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KEEP (*(SORT(.dtors.*)))
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||||
KEEP (*crtend.o(.dtors))
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||||
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||||
. = ALIGN(4);
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||||
_efixed = .; /* End of text section */
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||||
} > ram
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||||
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||||
. = ALIGN(4);
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_etext = .;
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||||
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||||
.relocate : AT (_etext)
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_srelocate = .;
|
||||
*(.ramfunc .ramfunc.*);
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||||
*(.data .data.*);
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||||
. = ALIGN(4);
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||||
_erelocate = .;
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||||
} > ram
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||||
/* .bss section which is used for uninitialized data */
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.bss (NOLOAD) :
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{
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. = ALIGN(4);
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||||
_sbss = . ;
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||||
_szero = .;
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*(.bss .bss.*)
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*(COMMON)
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. = ALIGN(4);
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_ebss = . ;
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||||
_ezero = .;
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} > ram
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/* heap section */
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.heap (NOLOAD):
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||||
{
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. = ALIGN(8);
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_sheap = .;
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||||
. = . + HEAP_SIZE;
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. = ALIGN(8);
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_eheap = .;
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||||
} > ram
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||||
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||||
/* stack section */
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.stack (NOLOAD):
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||||
{
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. = ALIGN(8);
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_sstack = .;
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. = . + STACK_SIZE;
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. = ALIGN(8);
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_estack = .;
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} > ram
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/* .ARM.exidx is sorted, so has to go in its own output section. */
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PROVIDE_HIDDEN (__exidx_start = .);
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.ARM.exidx :
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{
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*(.ARM.exidx* .gnu.linkonce.armexidx.*)
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} > ram
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PROVIDE_HIDDEN (__exidx_end = .);
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. = ALIGN(4);
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_end = . ;
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_ram_end_ = ORIGIN(ram) + LENGTH(ram) - 1 ;
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}
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@ -0,0 +1,160 @@
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/**
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* \file
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*
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* \brief GCC linker script (flash) for ATSAME70J20
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*
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* Copyright (c) 2020 Microchip Technology Inc.
|
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*
|
||||
* \license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
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* you may not use this file except in compliance with the License.
|
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* You may obtain a copy of the License at
|
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*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
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*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
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* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
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*
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* \license_stop
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*
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*/
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/*------------------------------------------------------------------------------
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* Linker script for running in internal FLASH on the ATSAME70J20
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*----------------------------------------------------------------------------*/
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OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
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OUTPUT_ARCH(arm)
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SEARCH_DIR(.)
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/* Memory Spaces Definitions */
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MEMORY
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{
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rom (rx) : ORIGIN = 0x00400000, LENGTH = 0x00100000 /* rom, 1048576K */
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ram (rwx) : ORIGIN = 0x20400000, LENGTH = 0x00060000 /* ram, 393216K */
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}
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/* The stack size used by the application. NOTE: you need to adjust according to your application. */
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STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x0400;
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/* The heapsize used by the application. NOTE: you need to adjust according to your application. */
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HEAP_SIZE = DEFINED(HEAP_SIZE) ? HEAP_SIZE : DEFINED(__heap_size__) ? __heap_size__ : 0x0200;
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/* Section Definitions */
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SECTIONS
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||||
{
|
||||
.text :
|
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{
|
||||
. = ALIGN(4);
|
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_sfixed = .;
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KEEP(*(.vectors .vectors.*))
|
||||
*(.text .text.* .gnu.linkonce.t.*)
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||||
*(.glue_7t) *(.glue_7)
|
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*(.rodata .rodata* .gnu.linkonce.r.*)
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*(.ARM.extab* .gnu.linkonce.armextab.*)
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/* Support C constructors, and C destructors in both user code
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and the C library. This also provides support for C++ code. */
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. = ALIGN(4);
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KEEP(*(.init))
|
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. = ALIGN(4);
|
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__preinit_array_start = .;
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KEEP (*(.preinit_array))
|
||||
__preinit_array_end = .;
|
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|
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. = ALIGN(4);
|
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__init_array_start = .;
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KEEP (*(SORT(.init_array.*)))
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KEEP (*(.init_array))
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__init_array_end = .;
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||||
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||||
. = ALIGN(4);
|
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KEEP (*crtbegin.o(.ctors))
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||||
KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
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||||
KEEP (*(SORT(.ctors.*)))
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||||
KEEP (*crtend.o(.ctors))
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. = ALIGN(4);
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KEEP(*(.fini))
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. = ALIGN(4);
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__fini_array_start = .;
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KEEP (*(.fini_array))
|
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KEEP (*(SORT(.fini_array.*)))
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__fini_array_end = .;
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|
||||
KEEP (*crtbegin.o(.dtors))
|
||||
KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
|
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KEEP (*(SORT(.dtors.*)))
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KEEP (*crtend.o(.dtors))
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. = ALIGN(4);
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_efixed = .; /* End of text section */
|
||||
} > rom
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/* .ARM.exidx is sorted, so has to go in its own output section. */
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PROVIDE_HIDDEN (__exidx_start = .);
|
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.ARM.exidx :
|
||||
{
|
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*(.ARM.exidx* .gnu.linkonce.armexidx.*)
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} > rom
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PROVIDE_HIDDEN (__exidx_end = .);
|
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|
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. = ALIGN(4);
|
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_etext = .;
|
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|
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.relocate : AT (_etext)
|
||||
{
|
||||
. = ALIGN(4);
|
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_srelocate = .;
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*(.ramfunc .ramfunc.*);
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*(.data .data.*);
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. = ALIGN(4);
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_erelocate = .;
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} > ram
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/* .bss section which is used for uninitialized data */
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.bss (NOLOAD) :
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{
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. = ALIGN(4);
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_sbss = . ;
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_szero = .;
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*(.bss .bss.*)
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*(COMMON)
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. = ALIGN(4);
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_ebss = . ;
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_ezero = .;
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} > ram
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/* heap section */
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||||
.heap (NOLOAD):
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||||
{
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. = ALIGN(8);
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_sheap = .;
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. = . + HEAP_SIZE;
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. = ALIGN(8);
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_eheap = .;
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} > ram
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/* stack section */
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.stack (NOLOAD):
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||||
{
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. = ALIGN(8);
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_sstack = .;
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. = . + STACK_SIZE;
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. = ALIGN(8);
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_estack = .;
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} > ram
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||||
. = ALIGN(4);
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||||
_end = . ;
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||||
_ram_end_ = ORIGIN(ram) + LENGTH(ram) - 1 ;
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||||
}
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@ -0,0 +1,161 @@
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/**
|
||||
* \file
|
||||
*
|
||||
* \brief GCC linker script (sram) for ATSAME70J20
|
||||
*
|
||||
* Copyright (c) 2020 Microchip Technology Inc.
|
||||
*
|
||||
* \license_start
|
||||
*
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||||
* \page License
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
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||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* \license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
/*------------------------------------------------------------------------------
|
||||
* Linker script for running in internal SRAM on the ATSAME70J20
|
||||
*----------------------------------------------------------------------------*/
|
||||
|
||||
OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
|
||||
OUTPUT_ARCH(arm)
|
||||
SEARCH_DIR(.)
|
||||
|
||||
/* Memory Spaces Definitions */
|
||||
MEMORY
|
||||
{
|
||||
rom (rx) : ORIGIN = 0x00400000, LENGTH = 0x00100000 /* rom, 1048576K */
|
||||
ram (rwx) : ORIGIN = 0x20400000, LENGTH = 0x00060000 /* ram, 393216K */
|
||||
}
|
||||
|
||||
/* The stack size used by the application. NOTE: you need to adjust according to your application. */
|
||||
STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x0400;
|
||||
|
||||
/* The heapsize used by the application. NOTE: you need to adjust according to your application. */
|
||||
HEAP_SIZE = DEFINED(HEAP_SIZE) ? HEAP_SIZE : DEFINED(__heap_size__) ? __heap_size__ : 0x0200;
|
||||
|
||||
/* Section Definitions */
|
||||
SECTIONS
|
||||
{
|
||||
.text :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_sfixed = .;
|
||||
KEEP(*(.vectors .vectors.*))
|
||||
*(.text .text.* .gnu.linkonce.t.*)
|
||||
*(.glue_7t) *(.glue_7)
|
||||
*(.rodata .rodata* .gnu.linkonce.r.*)
|
||||
*(.ARM.extab* .gnu.linkonce.armextab.*)
|
||||
|
||||
/* Support C constructors, and C destructors in both user code
|
||||
and the C library. This also provides support for C++ code. */
|
||||
. = ALIGN(4);
|
||||
KEEP(*(.init))
|
||||
. = ALIGN(4);
|
||||
__preinit_array_start = .;
|
||||
KEEP (*(.preinit_array))
|
||||
__preinit_array_end = .;
|
||||
|
||||
. = ALIGN(4);
|
||||
__init_array_start = .;
|
||||
KEEP (*(SORT(.init_array.*)))
|
||||
KEEP (*(.init_array))
|
||||
__init_array_end = .;
|
||||
|
||||
. = ALIGN(4);
|
||||
KEEP (*crtbegin.o(.ctors))
|
||||
KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
|
||||
KEEP (*(SORT(.ctors.*)))
|
||||
KEEP (*crtend.o(.ctors))
|
||||
|
||||
. = ALIGN(4);
|
||||
KEEP(*(.fini))
|
||||
|
||||
. = ALIGN(4);
|
||||
__fini_array_start = .;
|
||||
KEEP (*(.fini_array))
|
||||
KEEP (*(SORT(.fini_array.*)))
|
||||
__fini_array_end = .;
|
||||
|
||||
KEEP (*crtbegin.o(.dtors))
|
||||
KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
|
||||
KEEP (*(SORT(.dtors.*)))
|
||||
KEEP (*crtend.o(.dtors))
|
||||
|
||||
. = ALIGN(4);
|
||||
_efixed = .; /* End of text section */
|
||||
} > ram
|
||||
|
||||
. = ALIGN(4);
|
||||
_etext = .;
|
||||
|
||||
.relocate : AT (_etext)
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_srelocate = .;
|
||||
*(.ramfunc .ramfunc.*);
|
||||
*(.data .data.*);
|
||||
. = ALIGN(4);
|
||||
_erelocate = .;
|
||||
} > ram
|
||||
|
||||
/* .bss section which is used for uninitialized data */
|
||||
.bss (NOLOAD) :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_sbss = . ;
|
||||
_szero = .;
|
||||
*(.bss .bss.*)
|
||||
*(COMMON)
|
||||
. = ALIGN(4);
|
||||
_ebss = . ;
|
||||
_ezero = .;
|
||||
} > ram
|
||||
|
||||
/* heap section */
|
||||
.heap (NOLOAD):
|
||||
{
|
||||
. = ALIGN(8);
|
||||
_sheap = .;
|
||||
. = . + HEAP_SIZE;
|
||||
. = ALIGN(8);
|
||||
_eheap = .;
|
||||
} > ram
|
||||
|
||||
/* stack section */
|
||||
.stack (NOLOAD):
|
||||
{
|
||||
. = ALIGN(8);
|
||||
_sstack = .;
|
||||
. = . + STACK_SIZE;
|
||||
. = ALIGN(8);
|
||||
_estack = .;
|
||||
} > ram
|
||||
|
||||
/* .ARM.exidx is sorted, so has to go in its own output section. */
|
||||
PROVIDE_HIDDEN (__exidx_start = .);
|
||||
.ARM.exidx :
|
||||
{
|
||||
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
|
||||
} > ram
|
||||
PROVIDE_HIDDEN (__exidx_end = .);
|
||||
|
||||
. = ALIGN(4);
|
||||
_end = . ;
|
||||
_ram_end_ = ORIGIN(ram) + LENGTH(ram) - 1 ;
|
||||
}
|
||||
|
||||
@ -0,0 +1,160 @@
|
||||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief GCC linker script (flash) for ATSAME70J21
|
||||
*
|
||||
* Copyright (c) 2020 Microchip Technology Inc.
|
||||
*
|
||||
* \license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* \license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
/*------------------------------------------------------------------------------
|
||||
* Linker script for running in internal FLASH on the ATSAME70J21
|
||||
*----------------------------------------------------------------------------*/
|
||||
|
||||
OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
|
||||
OUTPUT_ARCH(arm)
|
||||
SEARCH_DIR(.)
|
||||
|
||||
/* Memory Spaces Definitions */
|
||||
MEMORY
|
||||
{
|
||||
rom (rx) : ORIGIN = 0x00400000, LENGTH = 0x00200000 /* rom, 2097152K */
|
||||
ram (rwx) : ORIGIN = 0x20400000, LENGTH = 0x00060000 /* ram, 393216K */
|
||||
}
|
||||
|
||||
/* The stack size used by the application. NOTE: you need to adjust according to your application. */
|
||||
STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x0400;
|
||||
|
||||
/* The heapsize used by the application. NOTE: you need to adjust according to your application. */
|
||||
HEAP_SIZE = DEFINED(HEAP_SIZE) ? HEAP_SIZE : DEFINED(__heap_size__) ? __heap_size__ : 0x0200;
|
||||
|
||||
/* Section Definitions */
|
||||
SECTIONS
|
||||
{
|
||||
.text :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_sfixed = .;
|
||||
KEEP(*(.vectors .vectors.*))
|
||||
*(.text .text.* .gnu.linkonce.t.*)
|
||||
*(.glue_7t) *(.glue_7)
|
||||
*(.rodata .rodata* .gnu.linkonce.r.*)
|
||||
*(.ARM.extab* .gnu.linkonce.armextab.*)
|
||||
|
||||
/* Support C constructors, and C destructors in both user code
|
||||
and the C library. This also provides support for C++ code. */
|
||||
. = ALIGN(4);
|
||||
KEEP(*(.init))
|
||||
. = ALIGN(4);
|
||||
__preinit_array_start = .;
|
||||
KEEP (*(.preinit_array))
|
||||
__preinit_array_end = .;
|
||||
|
||||
. = ALIGN(4);
|
||||
__init_array_start = .;
|
||||
KEEP (*(SORT(.init_array.*)))
|
||||
KEEP (*(.init_array))
|
||||
__init_array_end = .;
|
||||
|
||||
. = ALIGN(4);
|
||||
KEEP (*crtbegin.o(.ctors))
|
||||
KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
|
||||
KEEP (*(SORT(.ctors.*)))
|
||||
KEEP (*crtend.o(.ctors))
|
||||
|
||||
. = ALIGN(4);
|
||||
KEEP(*(.fini))
|
||||
|
||||
. = ALIGN(4);
|
||||
__fini_array_start = .;
|
||||
KEEP (*(.fini_array))
|
||||
KEEP (*(SORT(.fini_array.*)))
|
||||
__fini_array_end = .;
|
||||
|
||||
KEEP (*crtbegin.o(.dtors))
|
||||
KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
|
||||
KEEP (*(SORT(.dtors.*)))
|
||||
KEEP (*crtend.o(.dtors))
|
||||
|
||||
. = ALIGN(4);
|
||||
_efixed = .; /* End of text section */
|
||||
} > rom
|
||||
|
||||
/* .ARM.exidx is sorted, so has to go in its own output section. */
|
||||
PROVIDE_HIDDEN (__exidx_start = .);
|
||||
.ARM.exidx :
|
||||
{
|
||||
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
|
||||
} > rom
|
||||
PROVIDE_HIDDEN (__exidx_end = .);
|
||||
|
||||
. = ALIGN(4);
|
||||
_etext = .;
|
||||
|
||||
.relocate : AT (_etext)
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_srelocate = .;
|
||||
*(.ramfunc .ramfunc.*);
|
||||
*(.data .data.*);
|
||||
. = ALIGN(4);
|
||||
_erelocate = .;
|
||||
} > ram
|
||||
|
||||
/* .bss section which is used for uninitialized data */
|
||||
.bss (NOLOAD) :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_sbss = . ;
|
||||
_szero = .;
|
||||
*(.bss .bss.*)
|
||||
*(COMMON)
|
||||
. = ALIGN(4);
|
||||
_ebss = . ;
|
||||
_ezero = .;
|
||||
} > ram
|
||||
|
||||
/* heap section */
|
||||
.heap (NOLOAD):
|
||||
{
|
||||
. = ALIGN(8);
|
||||
_sheap = .;
|
||||
. = . + HEAP_SIZE;
|
||||
. = ALIGN(8);
|
||||
_eheap = .;
|
||||
} > ram
|
||||
|
||||
/* stack section */
|
||||
.stack (NOLOAD):
|
||||
{
|
||||
. = ALIGN(8);
|
||||
_sstack = .;
|
||||
. = . + STACK_SIZE;
|
||||
. = ALIGN(8);
|
||||
_estack = .;
|
||||
} > ram
|
||||
|
||||
. = ALIGN(4);
|
||||
_end = . ;
|
||||
_ram_end_ = ORIGIN(ram) + LENGTH(ram) - 1 ;
|
||||
}
|
||||
@ -0,0 +1,161 @@
|
||||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief GCC linker script (sram) for ATSAME70J21
|
||||
*
|
||||
* Copyright (c) 2020 Microchip Technology Inc.
|
||||
*
|
||||
* \license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* \license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
/*------------------------------------------------------------------------------
|
||||
* Linker script for running in internal SRAM on the ATSAME70J21
|
||||
*----------------------------------------------------------------------------*/
|
||||
|
||||
OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
|
||||
OUTPUT_ARCH(arm)
|
||||
SEARCH_DIR(.)
|
||||
|
||||
/* Memory Spaces Definitions */
|
||||
MEMORY
|
||||
{
|
||||
rom (rx) : ORIGIN = 0x00400000, LENGTH = 0x00200000 /* rom, 2097152K */
|
||||
ram (rwx) : ORIGIN = 0x20400000, LENGTH = 0x00060000 /* ram, 393216K */
|
||||
}
|
||||
|
||||
/* The stack size used by the application. NOTE: you need to adjust according to your application. */
|
||||
STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x0400;
|
||||
|
||||
/* The heapsize used by the application. NOTE: you need to adjust according to your application. */
|
||||
HEAP_SIZE = DEFINED(HEAP_SIZE) ? HEAP_SIZE : DEFINED(__heap_size__) ? __heap_size__ : 0x0200;
|
||||
|
||||
/* Section Definitions */
|
||||
SECTIONS
|
||||
{
|
||||
.text :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_sfixed = .;
|
||||
KEEP(*(.vectors .vectors.*))
|
||||
*(.text .text.* .gnu.linkonce.t.*)
|
||||
*(.glue_7t) *(.glue_7)
|
||||
*(.rodata .rodata* .gnu.linkonce.r.*)
|
||||
*(.ARM.extab* .gnu.linkonce.armextab.*)
|
||||
|
||||
/* Support C constructors, and C destructors in both user code
|
||||
and the C library. This also provides support for C++ code. */
|
||||
. = ALIGN(4);
|
||||
KEEP(*(.init))
|
||||
. = ALIGN(4);
|
||||
__preinit_array_start = .;
|
||||
KEEP (*(.preinit_array))
|
||||
__preinit_array_end = .;
|
||||
|
||||
. = ALIGN(4);
|
||||
__init_array_start = .;
|
||||
KEEP (*(SORT(.init_array.*)))
|
||||
KEEP (*(.init_array))
|
||||
__init_array_end = .;
|
||||
|
||||
. = ALIGN(4);
|
||||
KEEP (*crtbegin.o(.ctors))
|
||||
KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
|
||||
KEEP (*(SORT(.ctors.*)))
|
||||
KEEP (*crtend.o(.ctors))
|
||||
|
||||
. = ALIGN(4);
|
||||
KEEP(*(.fini))
|
||||
|
||||
. = ALIGN(4);
|
||||
__fini_array_start = .;
|
||||
KEEP (*(.fini_array))
|
||||
KEEP (*(SORT(.fini_array.*)))
|
||||
__fini_array_end = .;
|
||||
|
||||
KEEP (*crtbegin.o(.dtors))
|
||||
KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
|
||||
KEEP (*(SORT(.dtors.*)))
|
||||
KEEP (*crtend.o(.dtors))
|
||||
|
||||
. = ALIGN(4);
|
||||
_efixed = .; /* End of text section */
|
||||
} > ram
|
||||
|
||||
. = ALIGN(4);
|
||||
_etext = .;
|
||||
|
||||
.relocate : AT (_etext)
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_srelocate = .;
|
||||
*(.ramfunc .ramfunc.*);
|
||||
*(.data .data.*);
|
||||
. = ALIGN(4);
|
||||
_erelocate = .;
|
||||
} > ram
|
||||
|
||||
/* .bss section which is used for uninitialized data */
|
||||
.bss (NOLOAD) :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_sbss = . ;
|
||||
_szero = .;
|
||||
*(.bss .bss.*)
|
||||
*(COMMON)
|
||||
. = ALIGN(4);
|
||||
_ebss = . ;
|
||||
_ezero = .;
|
||||
} > ram
|
||||
|
||||
/* heap section */
|
||||
.heap (NOLOAD):
|
||||
{
|
||||
. = ALIGN(8);
|
||||
_sheap = .;
|
||||
. = . + HEAP_SIZE;
|
||||
. = ALIGN(8);
|
||||
_eheap = .;
|
||||
} > ram
|
||||
|
||||
/* stack section */
|
||||
.stack (NOLOAD):
|
||||
{
|
||||
. = ALIGN(8);
|
||||
_sstack = .;
|
||||
. = . + STACK_SIZE;
|
||||
. = ALIGN(8);
|
||||
_estack = .;
|
||||
} > ram
|
||||
|
||||
/* .ARM.exidx is sorted, so has to go in its own output section. */
|
||||
PROVIDE_HIDDEN (__exidx_start = .);
|
||||
.ARM.exidx :
|
||||
{
|
||||
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
|
||||
} > ram
|
||||
PROVIDE_HIDDEN (__exidx_end = .);
|
||||
|
||||
. = ALIGN(4);
|
||||
_end = . ;
|
||||
_ram_end_ = ORIGIN(ram) + LENGTH(ram) - 1 ;
|
||||
}
|
||||
|
||||
@ -0,0 +1,160 @@
|
||||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief GCC linker script (flash) for ATSAME70N19
|
||||
*
|
||||
* Copyright (c) 2020 Microchip Technology Inc.
|
||||
*
|
||||
* \license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* \license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
/*------------------------------------------------------------------------------
|
||||
* Linker script for running in internal FLASH on the ATSAME70N19
|
||||
*----------------------------------------------------------------------------*/
|
||||
|
||||
OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
|
||||
OUTPUT_ARCH(arm)
|
||||
SEARCH_DIR(.)
|
||||
|
||||
/* Memory Spaces Definitions */
|
||||
MEMORY
|
||||
{
|
||||
rom (rx) : ORIGIN = 0x00400000, LENGTH = 0x00080000 /* rom, 524288K */
|
||||
ram (rwx) : ORIGIN = 0x20400000, LENGTH = 0x00040000 /* ram, 262144K */
|
||||
}
|
||||
|
||||
/* The stack size used by the application. NOTE: you need to adjust according to your application. */
|
||||
STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x0400;
|
||||
|
||||
/* The heapsize used by the application. NOTE: you need to adjust according to your application. */
|
||||
HEAP_SIZE = DEFINED(HEAP_SIZE) ? HEAP_SIZE : DEFINED(__heap_size__) ? __heap_size__ : 0x0200;
|
||||
|
||||
/* Section Definitions */
|
||||
SECTIONS
|
||||
{
|
||||
.text :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_sfixed = .;
|
||||
KEEP(*(.vectors .vectors.*))
|
||||
*(.text .text.* .gnu.linkonce.t.*)
|
||||
*(.glue_7t) *(.glue_7)
|
||||
*(.rodata .rodata* .gnu.linkonce.r.*)
|
||||
*(.ARM.extab* .gnu.linkonce.armextab.*)
|
||||
|
||||
/* Support C constructors, and C destructors in both user code
|
||||
and the C library. This also provides support for C++ code. */
|
||||
. = ALIGN(4);
|
||||
KEEP(*(.init))
|
||||
. = ALIGN(4);
|
||||
__preinit_array_start = .;
|
||||
KEEP (*(.preinit_array))
|
||||
__preinit_array_end = .;
|
||||
|
||||
. = ALIGN(4);
|
||||
__init_array_start = .;
|
||||
KEEP (*(SORT(.init_array.*)))
|
||||
KEEP (*(.init_array))
|
||||
__init_array_end = .;
|
||||
|
||||
. = ALIGN(4);
|
||||
KEEP (*crtbegin.o(.ctors))
|
||||
KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
|
||||
KEEP (*(SORT(.ctors.*)))
|
||||
KEEP (*crtend.o(.ctors))
|
||||
|
||||
. = ALIGN(4);
|
||||
KEEP(*(.fini))
|
||||
|
||||
. = ALIGN(4);
|
||||
__fini_array_start = .;
|
||||
KEEP (*(.fini_array))
|
||||
KEEP (*(SORT(.fini_array.*)))
|
||||
__fini_array_end = .;
|
||||
|
||||
KEEP (*crtbegin.o(.dtors))
|
||||
KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
|
||||
KEEP (*(SORT(.dtors.*)))
|
||||
KEEP (*crtend.o(.dtors))
|
||||
|
||||
. = ALIGN(4);
|
||||
_efixed = .; /* End of text section */
|
||||
} > rom
|
||||
|
||||
/* .ARM.exidx is sorted, so has to go in its own output section. */
|
||||
PROVIDE_HIDDEN (__exidx_start = .);
|
||||
.ARM.exidx :
|
||||
{
|
||||
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
|
||||
} > rom
|
||||
PROVIDE_HIDDEN (__exidx_end = .);
|
||||
|
||||
. = ALIGN(4);
|
||||
_etext = .;
|
||||
|
||||
.relocate : AT (_etext)
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_srelocate = .;
|
||||
*(.ramfunc .ramfunc.*);
|
||||
*(.data .data.*);
|
||||
. = ALIGN(4);
|
||||
_erelocate = .;
|
||||
} > ram
|
||||
|
||||
/* .bss section which is used for uninitialized data */
|
||||
.bss (NOLOAD) :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_sbss = . ;
|
||||
_szero = .;
|
||||
*(.bss .bss.*)
|
||||
*(COMMON)
|
||||
. = ALIGN(4);
|
||||
_ebss = . ;
|
||||
_ezero = .;
|
||||
} > ram
|
||||
|
||||
/* heap section */
|
||||
.heap (NOLOAD):
|
||||
{
|
||||
. = ALIGN(8);
|
||||
_sheap = .;
|
||||
. = . + HEAP_SIZE;
|
||||
. = ALIGN(8);
|
||||
_eheap = .;
|
||||
} > ram
|
||||
|
||||
/* stack section */
|
||||
.stack (NOLOAD):
|
||||
{
|
||||
. = ALIGN(8);
|
||||
_sstack = .;
|
||||
. = . + STACK_SIZE;
|
||||
. = ALIGN(8);
|
||||
_estack = .;
|
||||
} > ram
|
||||
|
||||
. = ALIGN(4);
|
||||
_end = . ;
|
||||
_ram_end_ = ORIGIN(ram) + LENGTH(ram) - 1 ;
|
||||
}
|
||||
@ -0,0 +1,161 @@
|
||||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief GCC linker script (sram) for ATSAME70N19
|
||||
*
|
||||
* Copyright (c) 2020 Microchip Technology Inc.
|
||||
*
|
||||
* \license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* \license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
/*------------------------------------------------------------------------------
|
||||
* Linker script for running in internal SRAM on the ATSAME70N19
|
||||
*----------------------------------------------------------------------------*/
|
||||
|
||||
OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
|
||||
OUTPUT_ARCH(arm)
|
||||
SEARCH_DIR(.)
|
||||
|
||||
/* Memory Spaces Definitions */
|
||||
MEMORY
|
||||
{
|
||||
rom (rx) : ORIGIN = 0x00400000, LENGTH = 0x00080000 /* rom, 524288K */
|
||||
ram (rwx) : ORIGIN = 0x20400000, LENGTH = 0x00040000 /* ram, 262144K */
|
||||
}
|
||||
|
||||
/* The stack size used by the application. NOTE: you need to adjust according to your application. */
|
||||
STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x0400;
|
||||
|
||||
/* The heapsize used by the application. NOTE: you need to adjust according to your application. */
|
||||
HEAP_SIZE = DEFINED(HEAP_SIZE) ? HEAP_SIZE : DEFINED(__heap_size__) ? __heap_size__ : 0x0200;
|
||||
|
||||
/* Section Definitions */
|
||||
SECTIONS
|
||||
{
|
||||
.text :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_sfixed = .;
|
||||
KEEP(*(.vectors .vectors.*))
|
||||
*(.text .text.* .gnu.linkonce.t.*)
|
||||
*(.glue_7t) *(.glue_7)
|
||||
*(.rodata .rodata* .gnu.linkonce.r.*)
|
||||
*(.ARM.extab* .gnu.linkonce.armextab.*)
|
||||
|
||||
/* Support C constructors, and C destructors in both user code
|
||||
and the C library. This also provides support for C++ code. */
|
||||
. = ALIGN(4);
|
||||
KEEP(*(.init))
|
||||
. = ALIGN(4);
|
||||
__preinit_array_start = .;
|
||||
KEEP (*(.preinit_array))
|
||||
__preinit_array_end = .;
|
||||
|
||||
. = ALIGN(4);
|
||||
__init_array_start = .;
|
||||
KEEP (*(SORT(.init_array.*)))
|
||||
KEEP (*(.init_array))
|
||||
__init_array_end = .;
|
||||
|
||||
. = ALIGN(4);
|
||||
KEEP (*crtbegin.o(.ctors))
|
||||
KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
|
||||
KEEP (*(SORT(.ctors.*)))
|
||||
KEEP (*crtend.o(.ctors))
|
||||
|
||||
. = ALIGN(4);
|
||||
KEEP(*(.fini))
|
||||
|
||||
. = ALIGN(4);
|
||||
__fini_array_start = .;
|
||||
KEEP (*(.fini_array))
|
||||
KEEP (*(SORT(.fini_array.*)))
|
||||
__fini_array_end = .;
|
||||
|
||||
KEEP (*crtbegin.o(.dtors))
|
||||
KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
|
||||
KEEP (*(SORT(.dtors.*)))
|
||||
KEEP (*crtend.o(.dtors))
|
||||
|
||||
. = ALIGN(4);
|
||||
_efixed = .; /* End of text section */
|
||||
} > ram
|
||||
|
||||
. = ALIGN(4);
|
||||
_etext = .;
|
||||
|
||||
.relocate : AT (_etext)
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_srelocate = .;
|
||||
*(.ramfunc .ramfunc.*);
|
||||
*(.data .data.*);
|
||||
. = ALIGN(4);
|
||||
_erelocate = .;
|
||||
} > ram
|
||||
|
||||
/* .bss section which is used for uninitialized data */
|
||||
.bss (NOLOAD) :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_sbss = . ;
|
||||
_szero = .;
|
||||
*(.bss .bss.*)
|
||||
*(COMMON)
|
||||
. = ALIGN(4);
|
||||
_ebss = . ;
|
||||
_ezero = .;
|
||||
} > ram
|
||||
|
||||
/* heap section */
|
||||
.heap (NOLOAD):
|
||||
{
|
||||
. = ALIGN(8);
|
||||
_sheap = .;
|
||||
. = . + HEAP_SIZE;
|
||||
. = ALIGN(8);
|
||||
_eheap = .;
|
||||
} > ram
|
||||
|
||||
/* stack section */
|
||||
.stack (NOLOAD):
|
||||
{
|
||||
. = ALIGN(8);
|
||||
_sstack = .;
|
||||
. = . + STACK_SIZE;
|
||||
. = ALIGN(8);
|
||||
_estack = .;
|
||||
} > ram
|
||||
|
||||
/* .ARM.exidx is sorted, so has to go in its own output section. */
|
||||
PROVIDE_HIDDEN (__exidx_start = .);
|
||||
.ARM.exidx :
|
||||
{
|
||||
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
|
||||
} > ram
|
||||
PROVIDE_HIDDEN (__exidx_end = .);
|
||||
|
||||
. = ALIGN(4);
|
||||
_end = . ;
|
||||
_ram_end_ = ORIGIN(ram) + LENGTH(ram) - 1 ;
|
||||
}
|
||||
|
||||
@ -0,0 +1,160 @@
|
||||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief GCC linker script (flash) for ATSAME70N20
|
||||
*
|
||||
* Copyright (c) 2020 Microchip Technology Inc.
|
||||
*
|
||||
* \license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* \license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
/*------------------------------------------------------------------------------
|
||||
* Linker script for running in internal FLASH on the ATSAME70N20
|
||||
*----------------------------------------------------------------------------*/
|
||||
|
||||
OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
|
||||
OUTPUT_ARCH(arm)
|
||||
SEARCH_DIR(.)
|
||||
|
||||
/* Memory Spaces Definitions */
|
||||
MEMORY
|
||||
{
|
||||
rom (rx) : ORIGIN = 0x00400000, LENGTH = 0x00100000 /* rom, 1048576K */
|
||||
ram (rwx) : ORIGIN = 0x20400000, LENGTH = 0x00060000 /* ram, 393216K */
|
||||
}
|
||||
|
||||
/* The stack size used by the application. NOTE: you need to adjust according to your application. */
|
||||
STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x0400;
|
||||
|
||||
/* The heapsize used by the application. NOTE: you need to adjust according to your application. */
|
||||
HEAP_SIZE = DEFINED(HEAP_SIZE) ? HEAP_SIZE : DEFINED(__heap_size__) ? __heap_size__ : 0x0200;
|
||||
|
||||
/* Section Definitions */
|
||||
SECTIONS
|
||||
{
|
||||
.text :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_sfixed = .;
|
||||
KEEP(*(.vectors .vectors.*))
|
||||
*(.text .text.* .gnu.linkonce.t.*)
|
||||
*(.glue_7t) *(.glue_7)
|
||||
*(.rodata .rodata* .gnu.linkonce.r.*)
|
||||
*(.ARM.extab* .gnu.linkonce.armextab.*)
|
||||
|
||||
/* Support C constructors, and C destructors in both user code
|
||||
and the C library. This also provides support for C++ code. */
|
||||
. = ALIGN(4);
|
||||
KEEP(*(.init))
|
||||
. = ALIGN(4);
|
||||
__preinit_array_start = .;
|
||||
KEEP (*(.preinit_array))
|
||||
__preinit_array_end = .;
|
||||
|
||||
. = ALIGN(4);
|
||||
__init_array_start = .;
|
||||
KEEP (*(SORT(.init_array.*)))
|
||||
KEEP (*(.init_array))
|
||||
__init_array_end = .;
|
||||
|
||||
. = ALIGN(4);
|
||||
KEEP (*crtbegin.o(.ctors))
|
||||
KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
|
||||
KEEP (*(SORT(.ctors.*)))
|
||||
KEEP (*crtend.o(.ctors))
|
||||
|
||||
. = ALIGN(4);
|
||||
KEEP(*(.fini))
|
||||
|
||||
. = ALIGN(4);
|
||||
__fini_array_start = .;
|
||||
KEEP (*(.fini_array))
|
||||
KEEP (*(SORT(.fini_array.*)))
|
||||
__fini_array_end = .;
|
||||
|
||||
KEEP (*crtbegin.o(.dtors))
|
||||
KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
|
||||
KEEP (*(SORT(.dtors.*)))
|
||||
KEEP (*crtend.o(.dtors))
|
||||
|
||||
. = ALIGN(4);
|
||||
_efixed = .; /* End of text section */
|
||||
} > rom
|
||||
|
||||
/* .ARM.exidx is sorted, so has to go in its own output section. */
|
||||
PROVIDE_HIDDEN (__exidx_start = .);
|
||||
.ARM.exidx :
|
||||
{
|
||||
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
|
||||
} > rom
|
||||
PROVIDE_HIDDEN (__exidx_end = .);
|
||||
|
||||
. = ALIGN(4);
|
||||
_etext = .;
|
||||
|
||||
.relocate : AT (_etext)
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_srelocate = .;
|
||||
*(.ramfunc .ramfunc.*);
|
||||
*(.data .data.*);
|
||||
. = ALIGN(4);
|
||||
_erelocate = .;
|
||||
} > ram
|
||||
|
||||
/* .bss section which is used for uninitialized data */
|
||||
.bss (NOLOAD) :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_sbss = . ;
|
||||
_szero = .;
|
||||
*(.bss .bss.*)
|
||||
*(COMMON)
|
||||
. = ALIGN(4);
|
||||
_ebss = . ;
|
||||
_ezero = .;
|
||||
} > ram
|
||||
|
||||
/* heap section */
|
||||
.heap (NOLOAD):
|
||||
{
|
||||
. = ALIGN(8);
|
||||
_sheap = .;
|
||||
. = . + HEAP_SIZE;
|
||||
. = ALIGN(8);
|
||||
_eheap = .;
|
||||
} > ram
|
||||
|
||||
/* stack section */
|
||||
.stack (NOLOAD):
|
||||
{
|
||||
. = ALIGN(8);
|
||||
_sstack = .;
|
||||
. = . + STACK_SIZE;
|
||||
. = ALIGN(8);
|
||||
_estack = .;
|
||||
} > ram
|
||||
|
||||
. = ALIGN(4);
|
||||
_end = . ;
|
||||
_ram_end_ = ORIGIN(ram) + LENGTH(ram) - 1 ;
|
||||
}
|
||||
@ -0,0 +1,161 @@
|
||||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief GCC linker script (sram) for ATSAME70N20
|
||||
*
|
||||
* Copyright (c) 2020 Microchip Technology Inc.
|
||||
*
|
||||
* \license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* \license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
/*------------------------------------------------------------------------------
|
||||
* Linker script for running in internal SRAM on the ATSAME70N20
|
||||
*----------------------------------------------------------------------------*/
|
||||
|
||||
OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
|
||||
OUTPUT_ARCH(arm)
|
||||
SEARCH_DIR(.)
|
||||
|
||||
/* Memory Spaces Definitions */
|
||||
MEMORY
|
||||
{
|
||||
rom (rx) : ORIGIN = 0x00400000, LENGTH = 0x00100000 /* rom, 1048576K */
|
||||
ram (rwx) : ORIGIN = 0x20400000, LENGTH = 0x00060000 /* ram, 393216K */
|
||||
}
|
||||
|
||||
/* The stack size used by the application. NOTE: you need to adjust according to your application. */
|
||||
STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x0400;
|
||||
|
||||
/* The heapsize used by the application. NOTE: you need to adjust according to your application. */
|
||||
HEAP_SIZE = DEFINED(HEAP_SIZE) ? HEAP_SIZE : DEFINED(__heap_size__) ? __heap_size__ : 0x0200;
|
||||
|
||||
/* Section Definitions */
|
||||
SECTIONS
|
||||
{
|
||||
.text :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_sfixed = .;
|
||||
KEEP(*(.vectors .vectors.*))
|
||||
*(.text .text.* .gnu.linkonce.t.*)
|
||||
*(.glue_7t) *(.glue_7)
|
||||
*(.rodata .rodata* .gnu.linkonce.r.*)
|
||||
*(.ARM.extab* .gnu.linkonce.armextab.*)
|
||||
|
||||
/* Support C constructors, and C destructors in both user code
|
||||
and the C library. This also provides support for C++ code. */
|
||||
. = ALIGN(4);
|
||||
KEEP(*(.init))
|
||||
. = ALIGN(4);
|
||||
__preinit_array_start = .;
|
||||
KEEP (*(.preinit_array))
|
||||
__preinit_array_end = .;
|
||||
|
||||
. = ALIGN(4);
|
||||
__init_array_start = .;
|
||||
KEEP (*(SORT(.init_array.*)))
|
||||
KEEP (*(.init_array))
|
||||
__init_array_end = .;
|
||||
|
||||
. = ALIGN(4);
|
||||
KEEP (*crtbegin.o(.ctors))
|
||||
KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
|
||||
KEEP (*(SORT(.ctors.*)))
|
||||
KEEP (*crtend.o(.ctors))
|
||||
|
||||
. = ALIGN(4);
|
||||
KEEP(*(.fini))
|
||||
|
||||
. = ALIGN(4);
|
||||
__fini_array_start = .;
|
||||
KEEP (*(.fini_array))
|
||||
KEEP (*(SORT(.fini_array.*)))
|
||||
__fini_array_end = .;
|
||||
|
||||
KEEP (*crtbegin.o(.dtors))
|
||||
KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
|
||||
KEEP (*(SORT(.dtors.*)))
|
||||
KEEP (*crtend.o(.dtors))
|
||||
|
||||
. = ALIGN(4);
|
||||
_efixed = .; /* End of text section */
|
||||
} > ram
|
||||
|
||||
. = ALIGN(4);
|
||||
_etext = .;
|
||||
|
||||
.relocate : AT (_etext)
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_srelocate = .;
|
||||
*(.ramfunc .ramfunc.*);
|
||||
*(.data .data.*);
|
||||
. = ALIGN(4);
|
||||
_erelocate = .;
|
||||
} > ram
|
||||
|
||||
/* .bss section which is used for uninitialized data */
|
||||
.bss (NOLOAD) :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_sbss = . ;
|
||||
_szero = .;
|
||||
*(.bss .bss.*)
|
||||
*(COMMON)
|
||||
. = ALIGN(4);
|
||||
_ebss = . ;
|
||||
_ezero = .;
|
||||
} > ram
|
||||
|
||||
/* heap section */
|
||||
.heap (NOLOAD):
|
||||
{
|
||||
. = ALIGN(8);
|
||||
_sheap = .;
|
||||
. = . + HEAP_SIZE;
|
||||
. = ALIGN(8);
|
||||
_eheap = .;
|
||||
} > ram
|
||||
|
||||
/* stack section */
|
||||
.stack (NOLOAD):
|
||||
{
|
||||
. = ALIGN(8);
|
||||
_sstack = .;
|
||||
. = . + STACK_SIZE;
|
||||
. = ALIGN(8);
|
||||
_estack = .;
|
||||
} > ram
|
||||
|
||||
/* .ARM.exidx is sorted, so has to go in its own output section. */
|
||||
PROVIDE_HIDDEN (__exidx_start = .);
|
||||
.ARM.exidx :
|
||||
{
|
||||
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
|
||||
} > ram
|
||||
PROVIDE_HIDDEN (__exidx_end = .);
|
||||
|
||||
. = ALIGN(4);
|
||||
_end = . ;
|
||||
_ram_end_ = ORIGIN(ram) + LENGTH(ram) - 1 ;
|
||||
}
|
||||
|
||||
@ -0,0 +1,160 @@
|
||||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief GCC linker script (flash) for ATSAME70N21
|
||||
*
|
||||
* Copyright (c) 2020 Microchip Technology Inc.
|
||||
*
|
||||
* \license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* \license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
/*------------------------------------------------------------------------------
|
||||
* Linker script for running in internal FLASH on the ATSAME70N21
|
||||
*----------------------------------------------------------------------------*/
|
||||
|
||||
OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
|
||||
OUTPUT_ARCH(arm)
|
||||
SEARCH_DIR(.)
|
||||
|
||||
/* Memory Spaces Definitions */
|
||||
MEMORY
|
||||
{
|
||||
rom (rx) : ORIGIN = 0x00400000, LENGTH = 0x00200000 /* rom, 2097152K */
|
||||
ram (rwx) : ORIGIN = 0x20400000, LENGTH = 0x00060000 /* ram, 393216K */
|
||||
}
|
||||
|
||||
/* The stack size used by the application. NOTE: you need to adjust according to your application. */
|
||||
STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x0400;
|
||||
|
||||
/* The heapsize used by the application. NOTE: you need to adjust according to your application. */
|
||||
HEAP_SIZE = DEFINED(HEAP_SIZE) ? HEAP_SIZE : DEFINED(__heap_size__) ? __heap_size__ : 0x0200;
|
||||
|
||||
/* Section Definitions */
|
||||
SECTIONS
|
||||
{
|
||||
.text :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_sfixed = .;
|
||||
KEEP(*(.vectors .vectors.*))
|
||||
*(.text .text.* .gnu.linkonce.t.*)
|
||||
*(.glue_7t) *(.glue_7)
|
||||
*(.rodata .rodata* .gnu.linkonce.r.*)
|
||||
*(.ARM.extab* .gnu.linkonce.armextab.*)
|
||||
|
||||
/* Support C constructors, and C destructors in both user code
|
||||
and the C library. This also provides support for C++ code. */
|
||||
. = ALIGN(4);
|
||||
KEEP(*(.init))
|
||||
. = ALIGN(4);
|
||||
__preinit_array_start = .;
|
||||
KEEP (*(.preinit_array))
|
||||
__preinit_array_end = .;
|
||||
|
||||
. = ALIGN(4);
|
||||
__init_array_start = .;
|
||||
KEEP (*(SORT(.init_array.*)))
|
||||
KEEP (*(.init_array))
|
||||
__init_array_end = .;
|
||||
|
||||
. = ALIGN(4);
|
||||
KEEP (*crtbegin.o(.ctors))
|
||||
KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
|
||||
KEEP (*(SORT(.ctors.*)))
|
||||
KEEP (*crtend.o(.ctors))
|
||||
|
||||
. = ALIGN(4);
|
||||
KEEP(*(.fini))
|
||||
|
||||
. = ALIGN(4);
|
||||
__fini_array_start = .;
|
||||
KEEP (*(.fini_array))
|
||||
KEEP (*(SORT(.fini_array.*)))
|
||||
__fini_array_end = .;
|
||||
|
||||
KEEP (*crtbegin.o(.dtors))
|
||||
KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
|
||||
KEEP (*(SORT(.dtors.*)))
|
||||
KEEP (*crtend.o(.dtors))
|
||||
|
||||
. = ALIGN(4);
|
||||
_efixed = .; /* End of text section */
|
||||
} > rom
|
||||
|
||||
/* .ARM.exidx is sorted, so has to go in its own output section. */
|
||||
PROVIDE_HIDDEN (__exidx_start = .);
|
||||
.ARM.exidx :
|
||||
{
|
||||
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
|
||||
} > rom
|
||||
PROVIDE_HIDDEN (__exidx_end = .);
|
||||
|
||||
. = ALIGN(4);
|
||||
_etext = .;
|
||||
|
||||
.relocate : AT (_etext)
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_srelocate = .;
|
||||
*(.ramfunc .ramfunc.*);
|
||||
*(.data .data.*);
|
||||
. = ALIGN(4);
|
||||
_erelocate = .;
|
||||
} > ram
|
||||
|
||||
/* .bss section which is used for uninitialized data */
|
||||
.bss (NOLOAD) :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_sbss = . ;
|
||||
_szero = .;
|
||||
*(.bss .bss.*)
|
||||
*(COMMON)
|
||||
. = ALIGN(4);
|
||||
_ebss = . ;
|
||||
_ezero = .;
|
||||
} > ram
|
||||
|
||||
/* heap section */
|
||||
.heap (NOLOAD):
|
||||
{
|
||||
. = ALIGN(8);
|
||||
_sheap = .;
|
||||
. = . + HEAP_SIZE;
|
||||
. = ALIGN(8);
|
||||
_eheap = .;
|
||||
} > ram
|
||||
|
||||
/* stack section */
|
||||
.stack (NOLOAD):
|
||||
{
|
||||
. = ALIGN(8);
|
||||
_sstack = .;
|
||||
. = . + STACK_SIZE;
|
||||
. = ALIGN(8);
|
||||
_estack = .;
|
||||
} > ram
|
||||
|
||||
. = ALIGN(4);
|
||||
_end = . ;
|
||||
_ram_end_ = ORIGIN(ram) + LENGTH(ram) - 1 ;
|
||||
}
|
||||
@ -0,0 +1,161 @@
|
||||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief GCC linker script (sram) for ATSAME70N21
|
||||
*
|
||||
* Copyright (c) 2020 Microchip Technology Inc.
|
||||
*
|
||||
* \license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* \license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
/*------------------------------------------------------------------------------
|
||||
* Linker script for running in internal SRAM on the ATSAME70N21
|
||||
*----------------------------------------------------------------------------*/
|
||||
|
||||
OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
|
||||
OUTPUT_ARCH(arm)
|
||||
SEARCH_DIR(.)
|
||||
|
||||
/* Memory Spaces Definitions */
|
||||
MEMORY
|
||||
{
|
||||
rom (rx) : ORIGIN = 0x00400000, LENGTH = 0x00200000 /* rom, 2097152K */
|
||||
ram (rwx) : ORIGIN = 0x20400000, LENGTH = 0x00060000 /* ram, 393216K */
|
||||
}
|
||||
|
||||
/* The stack size used by the application. NOTE: you need to adjust according to your application. */
|
||||
STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x0400;
|
||||
|
||||
/* The heapsize used by the application. NOTE: you need to adjust according to your application. */
|
||||
HEAP_SIZE = DEFINED(HEAP_SIZE) ? HEAP_SIZE : DEFINED(__heap_size__) ? __heap_size__ : 0x0200;
|
||||
|
||||
/* Section Definitions */
|
||||
SECTIONS
|
||||
{
|
||||
.text :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_sfixed = .;
|
||||
KEEP(*(.vectors .vectors.*))
|
||||
*(.text .text.* .gnu.linkonce.t.*)
|
||||
*(.glue_7t) *(.glue_7)
|
||||
*(.rodata .rodata* .gnu.linkonce.r.*)
|
||||
*(.ARM.extab* .gnu.linkonce.armextab.*)
|
||||
|
||||
/* Support C constructors, and C destructors in both user code
|
||||
and the C library. This also provides support for C++ code. */
|
||||
. = ALIGN(4);
|
||||
KEEP(*(.init))
|
||||
. = ALIGN(4);
|
||||
__preinit_array_start = .;
|
||||
KEEP (*(.preinit_array))
|
||||
__preinit_array_end = .;
|
||||
|
||||
. = ALIGN(4);
|
||||
__init_array_start = .;
|
||||
KEEP (*(SORT(.init_array.*)))
|
||||
KEEP (*(.init_array))
|
||||
__init_array_end = .;
|
||||
|
||||
. = ALIGN(4);
|
||||
KEEP (*crtbegin.o(.ctors))
|
||||
KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
|
||||
KEEP (*(SORT(.ctors.*)))
|
||||
KEEP (*crtend.o(.ctors))
|
||||
|
||||
. = ALIGN(4);
|
||||
KEEP(*(.fini))
|
||||
|
||||
. = ALIGN(4);
|
||||
__fini_array_start = .;
|
||||
KEEP (*(.fini_array))
|
||||
KEEP (*(SORT(.fini_array.*)))
|
||||
__fini_array_end = .;
|
||||
|
||||
KEEP (*crtbegin.o(.dtors))
|
||||
KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
|
||||
KEEP (*(SORT(.dtors.*)))
|
||||
KEEP (*crtend.o(.dtors))
|
||||
|
||||
. = ALIGN(4);
|
||||
_efixed = .; /* End of text section */
|
||||
} > ram
|
||||
|
||||
. = ALIGN(4);
|
||||
_etext = .;
|
||||
|
||||
.relocate : AT (_etext)
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_srelocate = .;
|
||||
*(.ramfunc .ramfunc.*);
|
||||
*(.data .data.*);
|
||||
. = ALIGN(4);
|
||||
_erelocate = .;
|
||||
} > ram
|
||||
|
||||
/* .bss section which is used for uninitialized data */
|
||||
.bss (NOLOAD) :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_sbss = . ;
|
||||
_szero = .;
|
||||
*(.bss .bss.*)
|
||||
*(COMMON)
|
||||
. = ALIGN(4);
|
||||
_ebss = . ;
|
||||
_ezero = .;
|
||||
} > ram
|
||||
|
||||
/* heap section */
|
||||
.heap (NOLOAD):
|
||||
{
|
||||
. = ALIGN(8);
|
||||
_sheap = .;
|
||||
. = . + HEAP_SIZE;
|
||||
. = ALIGN(8);
|
||||
_eheap = .;
|
||||
} > ram
|
||||
|
||||
/* stack section */
|
||||
.stack (NOLOAD):
|
||||
{
|
||||
. = ALIGN(8);
|
||||
_sstack = .;
|
||||
. = . + STACK_SIZE;
|
||||
. = ALIGN(8);
|
||||
_estack = .;
|
||||
} > ram
|
||||
|
||||
/* .ARM.exidx is sorted, so has to go in its own output section. */
|
||||
PROVIDE_HIDDEN (__exidx_start = .);
|
||||
.ARM.exidx :
|
||||
{
|
||||
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
|
||||
} > ram
|
||||
PROVIDE_HIDDEN (__exidx_end = .);
|
||||
|
||||
. = ALIGN(4);
|
||||
_end = . ;
|
||||
_ram_end_ = ORIGIN(ram) + LENGTH(ram) - 1 ;
|
||||
}
|
||||
|
||||
@ -0,0 +1,160 @@
|
||||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief GCC linker script (flash) for ATSAME70Q19
|
||||
*
|
||||
* Copyright (c) 2020 Microchip Technology Inc.
|
||||
*
|
||||
* \license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* \license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
/*------------------------------------------------------------------------------
|
||||
* Linker script for running in internal FLASH on the ATSAME70Q19
|
||||
*----------------------------------------------------------------------------*/
|
||||
|
||||
OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
|
||||
OUTPUT_ARCH(arm)
|
||||
SEARCH_DIR(.)
|
||||
|
||||
/* Memory Spaces Definitions */
|
||||
MEMORY
|
||||
{
|
||||
rom (rx) : ORIGIN = 0x00400000, LENGTH = 0x00080000 /* rom, 524288K */
|
||||
ram (rwx) : ORIGIN = 0x20400000, LENGTH = 0x00040000 /* ram, 262144K */
|
||||
}
|
||||
|
||||
/* The stack size used by the application. NOTE: you need to adjust according to your application. */
|
||||
STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x0400;
|
||||
|
||||
/* The heapsize used by the application. NOTE: you need to adjust according to your application. */
|
||||
HEAP_SIZE = DEFINED(HEAP_SIZE) ? HEAP_SIZE : DEFINED(__heap_size__) ? __heap_size__ : 0x0200;
|
||||
|
||||
/* Section Definitions */
|
||||
SECTIONS
|
||||
{
|
||||
.text :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_sfixed = .;
|
||||
KEEP(*(.vectors .vectors.*))
|
||||
*(.text .text.* .gnu.linkonce.t.*)
|
||||
*(.glue_7t) *(.glue_7)
|
||||
*(.rodata .rodata* .gnu.linkonce.r.*)
|
||||
*(.ARM.extab* .gnu.linkonce.armextab.*)
|
||||
|
||||
/* Support C constructors, and C destructors in both user code
|
||||
and the C library. This also provides support for C++ code. */
|
||||
. = ALIGN(4);
|
||||
KEEP(*(.init))
|
||||
. = ALIGN(4);
|
||||
__preinit_array_start = .;
|
||||
KEEP (*(.preinit_array))
|
||||
__preinit_array_end = .;
|
||||
|
||||
. = ALIGN(4);
|
||||
__init_array_start = .;
|
||||
KEEP (*(SORT(.init_array.*)))
|
||||
KEEP (*(.init_array))
|
||||
__init_array_end = .;
|
||||
|
||||
. = ALIGN(4);
|
||||
KEEP (*crtbegin.o(.ctors))
|
||||
KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
|
||||
KEEP (*(SORT(.ctors.*)))
|
||||
KEEP (*crtend.o(.ctors))
|
||||
|
||||
. = ALIGN(4);
|
||||
KEEP(*(.fini))
|
||||
|
||||
. = ALIGN(4);
|
||||
__fini_array_start = .;
|
||||
KEEP (*(.fini_array))
|
||||
KEEP (*(SORT(.fini_array.*)))
|
||||
__fini_array_end = .;
|
||||
|
||||
KEEP (*crtbegin.o(.dtors))
|
||||
KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
|
||||
KEEP (*(SORT(.dtors.*)))
|
||||
KEEP (*crtend.o(.dtors))
|
||||
|
||||
. = ALIGN(4);
|
||||
_efixed = .; /* End of text section */
|
||||
} > rom
|
||||
|
||||
/* .ARM.exidx is sorted, so has to go in its own output section. */
|
||||
PROVIDE_HIDDEN (__exidx_start = .);
|
||||
.ARM.exidx :
|
||||
{
|
||||
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
|
||||
} > rom
|
||||
PROVIDE_HIDDEN (__exidx_end = .);
|
||||
|
||||
. = ALIGN(4);
|
||||
_etext = .;
|
||||
|
||||
.relocate : AT (_etext)
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_srelocate = .;
|
||||
*(.ramfunc .ramfunc.*);
|
||||
*(.data .data.*);
|
||||
. = ALIGN(4);
|
||||
_erelocate = .;
|
||||
} > ram
|
||||
|
||||
/* .bss section which is used for uninitialized data */
|
||||
.bss (NOLOAD) :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_sbss = . ;
|
||||
_szero = .;
|
||||
*(.bss .bss.*)
|
||||
*(COMMON)
|
||||
. = ALIGN(4);
|
||||
_ebss = . ;
|
||||
_ezero = .;
|
||||
} > ram
|
||||
|
||||
/* heap section */
|
||||
.heap (NOLOAD):
|
||||
{
|
||||
. = ALIGN(8);
|
||||
_sheap = .;
|
||||
. = . + HEAP_SIZE;
|
||||
. = ALIGN(8);
|
||||
_eheap = .;
|
||||
} > ram
|
||||
|
||||
/* stack section */
|
||||
.stack (NOLOAD):
|
||||
{
|
||||
. = ALIGN(8);
|
||||
_sstack = .;
|
||||
. = . + STACK_SIZE;
|
||||
. = ALIGN(8);
|
||||
_estack = .;
|
||||
} > ram
|
||||
|
||||
. = ALIGN(4);
|
||||
_end = . ;
|
||||
_ram_end_ = ORIGIN(ram) + LENGTH(ram) - 1 ;
|
||||
}
|
||||
@ -0,0 +1,161 @@
|
||||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief GCC linker script (sram) for ATSAME70Q19
|
||||
*
|
||||
* Copyright (c) 2020 Microchip Technology Inc.
|
||||
*
|
||||
* \license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* \license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
/*------------------------------------------------------------------------------
|
||||
* Linker script for running in internal SRAM on the ATSAME70Q19
|
||||
*----------------------------------------------------------------------------*/
|
||||
|
||||
OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
|
||||
OUTPUT_ARCH(arm)
|
||||
SEARCH_DIR(.)
|
||||
|
||||
/* Memory Spaces Definitions */
|
||||
MEMORY
|
||||
{
|
||||
rom (rx) : ORIGIN = 0x00400000, LENGTH = 0x00080000 /* rom, 524288K */
|
||||
ram (rwx) : ORIGIN = 0x20400000, LENGTH = 0x00040000 /* ram, 262144K */
|
||||
}
|
||||
|
||||
/* The stack size used by the application. NOTE: you need to adjust according to your application. */
|
||||
STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x0400;
|
||||
|
||||
/* The heapsize used by the application. NOTE: you need to adjust according to your application. */
|
||||
HEAP_SIZE = DEFINED(HEAP_SIZE) ? HEAP_SIZE : DEFINED(__heap_size__) ? __heap_size__ : 0x0200;
|
||||
|
||||
/* Section Definitions */
|
||||
SECTIONS
|
||||
{
|
||||
.text :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_sfixed = .;
|
||||
KEEP(*(.vectors .vectors.*))
|
||||
*(.text .text.* .gnu.linkonce.t.*)
|
||||
*(.glue_7t) *(.glue_7)
|
||||
*(.rodata .rodata* .gnu.linkonce.r.*)
|
||||
*(.ARM.extab* .gnu.linkonce.armextab.*)
|
||||
|
||||
/* Support C constructors, and C destructors in both user code
|
||||
and the C library. This also provides support for C++ code. */
|
||||
. = ALIGN(4);
|
||||
KEEP(*(.init))
|
||||
. = ALIGN(4);
|
||||
__preinit_array_start = .;
|
||||
KEEP (*(.preinit_array))
|
||||
__preinit_array_end = .;
|
||||
|
||||
. = ALIGN(4);
|
||||
__init_array_start = .;
|
||||
KEEP (*(SORT(.init_array.*)))
|
||||
KEEP (*(.init_array))
|
||||
__init_array_end = .;
|
||||
|
||||
. = ALIGN(4);
|
||||
KEEP (*crtbegin.o(.ctors))
|
||||
KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
|
||||
KEEP (*(SORT(.ctors.*)))
|
||||
KEEP (*crtend.o(.ctors))
|
||||
|
||||
. = ALIGN(4);
|
||||
KEEP(*(.fini))
|
||||
|
||||
. = ALIGN(4);
|
||||
__fini_array_start = .;
|
||||
KEEP (*(.fini_array))
|
||||
KEEP (*(SORT(.fini_array.*)))
|
||||
__fini_array_end = .;
|
||||
|
||||
KEEP (*crtbegin.o(.dtors))
|
||||
KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
|
||||
KEEP (*(SORT(.dtors.*)))
|
||||
KEEP (*crtend.o(.dtors))
|
||||
|
||||
. = ALIGN(4);
|
||||
_efixed = .; /* End of text section */
|
||||
} > ram
|
||||
|
||||
. = ALIGN(4);
|
||||
_etext = .;
|
||||
|
||||
.relocate : AT (_etext)
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_srelocate = .;
|
||||
*(.ramfunc .ramfunc.*);
|
||||
*(.data .data.*);
|
||||
. = ALIGN(4);
|
||||
_erelocate = .;
|
||||
} > ram
|
||||
|
||||
/* .bss section which is used for uninitialized data */
|
||||
.bss (NOLOAD) :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_sbss = . ;
|
||||
_szero = .;
|
||||
*(.bss .bss.*)
|
||||
*(COMMON)
|
||||
. = ALIGN(4);
|
||||
_ebss = . ;
|
||||
_ezero = .;
|
||||
} > ram
|
||||
|
||||
/* heap section */
|
||||
.heap (NOLOAD):
|
||||
{
|
||||
. = ALIGN(8);
|
||||
_sheap = .;
|
||||
. = . + HEAP_SIZE;
|
||||
. = ALIGN(8);
|
||||
_eheap = .;
|
||||
} > ram
|
||||
|
||||
/* stack section */
|
||||
.stack (NOLOAD):
|
||||
{
|
||||
. = ALIGN(8);
|
||||
_sstack = .;
|
||||
. = . + STACK_SIZE;
|
||||
. = ALIGN(8);
|
||||
_estack = .;
|
||||
} > ram
|
||||
|
||||
/* .ARM.exidx is sorted, so has to go in its own output section. */
|
||||
PROVIDE_HIDDEN (__exidx_start = .);
|
||||
.ARM.exidx :
|
||||
{
|
||||
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
|
||||
} > ram
|
||||
PROVIDE_HIDDEN (__exidx_end = .);
|
||||
|
||||
. = ALIGN(4);
|
||||
_end = . ;
|
||||
_ram_end_ = ORIGIN(ram) + LENGTH(ram) - 1 ;
|
||||
}
|
||||
|
||||
@ -0,0 +1,160 @@
|
||||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief GCC linker script (flash) for ATSAME70Q20
|
||||
*
|
||||
* Copyright (c) 2020 Microchip Technology Inc.
|
||||
*
|
||||
* \license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* \license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
/*------------------------------------------------------------------------------
|
||||
* Linker script for running in internal FLASH on the ATSAME70Q20
|
||||
*----------------------------------------------------------------------------*/
|
||||
|
||||
OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
|
||||
OUTPUT_ARCH(arm)
|
||||
SEARCH_DIR(.)
|
||||
|
||||
/* Memory Spaces Definitions */
|
||||
MEMORY
|
||||
{
|
||||
rom (rx) : ORIGIN = 0x00400000, LENGTH = 0x00100000 /* rom, 1048576K */
|
||||
ram (rwx) : ORIGIN = 0x20400000, LENGTH = 0x00060000 /* ram, 393216K */
|
||||
}
|
||||
|
||||
/* The stack size used by the application. NOTE: you need to adjust according to your application. */
|
||||
STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x0400;
|
||||
|
||||
/* The heapsize used by the application. NOTE: you need to adjust according to your application. */
|
||||
HEAP_SIZE = DEFINED(HEAP_SIZE) ? HEAP_SIZE : DEFINED(__heap_size__) ? __heap_size__ : 0x0200;
|
||||
|
||||
/* Section Definitions */
|
||||
SECTIONS
|
||||
{
|
||||
.text :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_sfixed = .;
|
||||
KEEP(*(.vectors .vectors.*))
|
||||
*(.text .text.* .gnu.linkonce.t.*)
|
||||
*(.glue_7t) *(.glue_7)
|
||||
*(.rodata .rodata* .gnu.linkonce.r.*)
|
||||
*(.ARM.extab* .gnu.linkonce.armextab.*)
|
||||
|
||||
/* Support C constructors, and C destructors in both user code
|
||||
and the C library. This also provides support for C++ code. */
|
||||
. = ALIGN(4);
|
||||
KEEP(*(.init))
|
||||
. = ALIGN(4);
|
||||
__preinit_array_start = .;
|
||||
KEEP (*(.preinit_array))
|
||||
__preinit_array_end = .;
|
||||
|
||||
. = ALIGN(4);
|
||||
__init_array_start = .;
|
||||
KEEP (*(SORT(.init_array.*)))
|
||||
KEEP (*(.init_array))
|
||||
__init_array_end = .;
|
||||
|
||||
. = ALIGN(4);
|
||||
KEEP (*crtbegin.o(.ctors))
|
||||
KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
|
||||
KEEP (*(SORT(.ctors.*)))
|
||||
KEEP (*crtend.o(.ctors))
|
||||
|
||||
. = ALIGN(4);
|
||||
KEEP(*(.fini))
|
||||
|
||||
. = ALIGN(4);
|
||||
__fini_array_start = .;
|
||||
KEEP (*(.fini_array))
|
||||
KEEP (*(SORT(.fini_array.*)))
|
||||
__fini_array_end = .;
|
||||
|
||||
KEEP (*crtbegin.o(.dtors))
|
||||
KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
|
||||
KEEP (*(SORT(.dtors.*)))
|
||||
KEEP (*crtend.o(.dtors))
|
||||
|
||||
. = ALIGN(4);
|
||||
_efixed = .; /* End of text section */
|
||||
} > rom
|
||||
|
||||
/* .ARM.exidx is sorted, so has to go in its own output section. */
|
||||
PROVIDE_HIDDEN (__exidx_start = .);
|
||||
.ARM.exidx :
|
||||
{
|
||||
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
|
||||
} > rom
|
||||
PROVIDE_HIDDEN (__exidx_end = .);
|
||||
|
||||
. = ALIGN(4);
|
||||
_etext = .;
|
||||
|
||||
.relocate : AT (_etext)
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_srelocate = .;
|
||||
*(.ramfunc .ramfunc.*);
|
||||
*(.data .data.*);
|
||||
. = ALIGN(4);
|
||||
_erelocate = .;
|
||||
} > ram
|
||||
|
||||
/* .bss section which is used for uninitialized data */
|
||||
.bss (NOLOAD) :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_sbss = . ;
|
||||
_szero = .;
|
||||
*(.bss .bss.*)
|
||||
*(COMMON)
|
||||
. = ALIGN(4);
|
||||
_ebss = . ;
|
||||
_ezero = .;
|
||||
} > ram
|
||||
|
||||
/* heap section */
|
||||
.heap (NOLOAD):
|
||||
{
|
||||
. = ALIGN(8);
|
||||
_sheap = .;
|
||||
. = . + HEAP_SIZE;
|
||||
. = ALIGN(8);
|
||||
_eheap = .;
|
||||
} > ram
|
||||
|
||||
/* stack section */
|
||||
.stack (NOLOAD):
|
||||
{
|
||||
. = ALIGN(8);
|
||||
_sstack = .;
|
||||
. = . + STACK_SIZE;
|
||||
. = ALIGN(8);
|
||||
_estack = .;
|
||||
} > ram
|
||||
|
||||
. = ALIGN(4);
|
||||
_end = . ;
|
||||
_ram_end_ = ORIGIN(ram) + LENGTH(ram) - 1 ;
|
||||
}
|
||||
@ -0,0 +1,161 @@
|
||||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief GCC linker script (sram) for ATSAME70Q20
|
||||
*
|
||||
* Copyright (c) 2020 Microchip Technology Inc.
|
||||
*
|
||||
* \license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* \license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
/*------------------------------------------------------------------------------
|
||||
* Linker script for running in internal SRAM on the ATSAME70Q20
|
||||
*----------------------------------------------------------------------------*/
|
||||
|
||||
OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
|
||||
OUTPUT_ARCH(arm)
|
||||
SEARCH_DIR(.)
|
||||
|
||||
/* Memory Spaces Definitions */
|
||||
MEMORY
|
||||
{
|
||||
rom (rx) : ORIGIN = 0x00400000, LENGTH = 0x00100000 /* rom, 1048576K */
|
||||
ram (rwx) : ORIGIN = 0x20400000, LENGTH = 0x00060000 /* ram, 393216K */
|
||||
}
|
||||
|
||||
/* The stack size used by the application. NOTE: you need to adjust according to your application. */
|
||||
STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x0400;
|
||||
|
||||
/* The heapsize used by the application. NOTE: you need to adjust according to your application. */
|
||||
HEAP_SIZE = DEFINED(HEAP_SIZE) ? HEAP_SIZE : DEFINED(__heap_size__) ? __heap_size__ : 0x0200;
|
||||
|
||||
/* Section Definitions */
|
||||
SECTIONS
|
||||
{
|
||||
.text :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_sfixed = .;
|
||||
KEEP(*(.vectors .vectors.*))
|
||||
*(.text .text.* .gnu.linkonce.t.*)
|
||||
*(.glue_7t) *(.glue_7)
|
||||
*(.rodata .rodata* .gnu.linkonce.r.*)
|
||||
*(.ARM.extab* .gnu.linkonce.armextab.*)
|
||||
|
||||
/* Support C constructors, and C destructors in both user code
|
||||
and the C library. This also provides support for C++ code. */
|
||||
. = ALIGN(4);
|
||||
KEEP(*(.init))
|
||||
. = ALIGN(4);
|
||||
__preinit_array_start = .;
|
||||
KEEP (*(.preinit_array))
|
||||
__preinit_array_end = .;
|
||||
|
||||
. = ALIGN(4);
|
||||
__init_array_start = .;
|
||||
KEEP (*(SORT(.init_array.*)))
|
||||
KEEP (*(.init_array))
|
||||
__init_array_end = .;
|
||||
|
||||
. = ALIGN(4);
|
||||
KEEP (*crtbegin.o(.ctors))
|
||||
KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
|
||||
KEEP (*(SORT(.ctors.*)))
|
||||
KEEP (*crtend.o(.ctors))
|
||||
|
||||
. = ALIGN(4);
|
||||
KEEP(*(.fini))
|
||||
|
||||
. = ALIGN(4);
|
||||
__fini_array_start = .;
|
||||
KEEP (*(.fini_array))
|
||||
KEEP (*(SORT(.fini_array.*)))
|
||||
__fini_array_end = .;
|
||||
|
||||
KEEP (*crtbegin.o(.dtors))
|
||||
KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
|
||||
KEEP (*(SORT(.dtors.*)))
|
||||
KEEP (*crtend.o(.dtors))
|
||||
|
||||
. = ALIGN(4);
|
||||
_efixed = .; /* End of text section */
|
||||
} > ram
|
||||
|
||||
. = ALIGN(4);
|
||||
_etext = .;
|
||||
|
||||
.relocate : AT (_etext)
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_srelocate = .;
|
||||
*(.ramfunc .ramfunc.*);
|
||||
*(.data .data.*);
|
||||
. = ALIGN(4);
|
||||
_erelocate = .;
|
||||
} > ram
|
||||
|
||||
/* .bss section which is used for uninitialized data */
|
||||
.bss (NOLOAD) :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_sbss = . ;
|
||||
_szero = .;
|
||||
*(.bss .bss.*)
|
||||
*(COMMON)
|
||||
. = ALIGN(4);
|
||||
_ebss = . ;
|
||||
_ezero = .;
|
||||
} > ram
|
||||
|
||||
/* heap section */
|
||||
.heap (NOLOAD):
|
||||
{
|
||||
. = ALIGN(8);
|
||||
_sheap = .;
|
||||
. = . + HEAP_SIZE;
|
||||
. = ALIGN(8);
|
||||
_eheap = .;
|
||||
} > ram
|
||||
|
||||
/* stack section */
|
||||
.stack (NOLOAD):
|
||||
{
|
||||
. = ALIGN(8);
|
||||
_sstack = .;
|
||||
. = . + STACK_SIZE;
|
||||
. = ALIGN(8);
|
||||
_estack = .;
|
||||
} > ram
|
||||
|
||||
/* .ARM.exidx is sorted, so has to go in its own output section. */
|
||||
PROVIDE_HIDDEN (__exidx_start = .);
|
||||
.ARM.exidx :
|
||||
{
|
||||
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
|
||||
} > ram
|
||||
PROVIDE_HIDDEN (__exidx_end = .);
|
||||
|
||||
. = ALIGN(4);
|
||||
_end = . ;
|
||||
_ram_end_ = ORIGIN(ram) + LENGTH(ram) - 1 ;
|
||||
}
|
||||
|
||||
@ -0,0 +1,160 @@
|
||||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief GCC linker script (flash) for ATSAME70Q21
|
||||
*
|
||||
* Copyright (c) 2020 Microchip Technology Inc.
|
||||
*
|
||||
* \license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* \license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
/*------------------------------------------------------------------------------
|
||||
* Linker script for running in internal FLASH on the ATSAME70Q21
|
||||
*----------------------------------------------------------------------------*/
|
||||
|
||||
OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
|
||||
OUTPUT_ARCH(arm)
|
||||
SEARCH_DIR(.)
|
||||
|
||||
/* Memory Spaces Definitions */
|
||||
MEMORY
|
||||
{
|
||||
rom (rx) : ORIGIN = 0x00400000, LENGTH = 0x00200000 /* rom, 2097152K */
|
||||
ram (rwx) : ORIGIN = 0x20400000, LENGTH = 0x00060000 /* ram, 393216K */
|
||||
}
|
||||
|
||||
/* The stack size used by the application. NOTE: you need to adjust according to your application. */
|
||||
STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x0400;
|
||||
|
||||
/* The heapsize used by the application. NOTE: you need to adjust according to your application. */
|
||||
HEAP_SIZE = DEFINED(HEAP_SIZE) ? HEAP_SIZE : DEFINED(__heap_size__) ? __heap_size__ : 0x0200;
|
||||
|
||||
/* Section Definitions */
|
||||
SECTIONS
|
||||
{
|
||||
.text :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_sfixed = .;
|
||||
KEEP(*(.vectors .vectors.*))
|
||||
*(.text .text.* .gnu.linkonce.t.*)
|
||||
*(.glue_7t) *(.glue_7)
|
||||
*(.rodata .rodata* .gnu.linkonce.r.*)
|
||||
*(.ARM.extab* .gnu.linkonce.armextab.*)
|
||||
|
||||
/* Support C constructors, and C destructors in both user code
|
||||
and the C library. This also provides support for C++ code. */
|
||||
. = ALIGN(4);
|
||||
KEEP(*(.init))
|
||||
. = ALIGN(4);
|
||||
__preinit_array_start = .;
|
||||
KEEP (*(.preinit_array))
|
||||
__preinit_array_end = .;
|
||||
|
||||
. = ALIGN(4);
|
||||
__init_array_start = .;
|
||||
KEEP (*(SORT(.init_array.*)))
|
||||
KEEP (*(.init_array))
|
||||
__init_array_end = .;
|
||||
|
||||
. = ALIGN(4);
|
||||
KEEP (*crtbegin.o(.ctors))
|
||||
KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
|
||||
KEEP (*(SORT(.ctors.*)))
|
||||
KEEP (*crtend.o(.ctors))
|
||||
|
||||
. = ALIGN(4);
|
||||
KEEP(*(.fini))
|
||||
|
||||
. = ALIGN(4);
|
||||
__fini_array_start = .;
|
||||
KEEP (*(.fini_array))
|
||||
KEEP (*(SORT(.fini_array.*)))
|
||||
__fini_array_end = .;
|
||||
|
||||
KEEP (*crtbegin.o(.dtors))
|
||||
KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
|
||||
KEEP (*(SORT(.dtors.*)))
|
||||
KEEP (*crtend.o(.dtors))
|
||||
|
||||
. = ALIGN(4);
|
||||
_efixed = .; /* End of text section */
|
||||
} > rom
|
||||
|
||||
/* .ARM.exidx is sorted, so has to go in its own output section. */
|
||||
PROVIDE_HIDDEN (__exidx_start = .);
|
||||
.ARM.exidx :
|
||||
{
|
||||
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
|
||||
} > rom
|
||||
PROVIDE_HIDDEN (__exidx_end = .);
|
||||
|
||||
. = ALIGN(4);
|
||||
_etext = .;
|
||||
|
||||
.relocate : AT (_etext)
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_srelocate = .;
|
||||
*(.ramfunc .ramfunc.*);
|
||||
*(.data .data.*);
|
||||
. = ALIGN(4);
|
||||
_erelocate = .;
|
||||
} > ram
|
||||
|
||||
/* .bss section which is used for uninitialized data */
|
||||
.bss (NOLOAD) :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_sbss = . ;
|
||||
_szero = .;
|
||||
*(.bss .bss.*)
|
||||
*(COMMON)
|
||||
. = ALIGN(4);
|
||||
_ebss = . ;
|
||||
_ezero = .;
|
||||
} > ram
|
||||
|
||||
/* heap section */
|
||||
.heap (NOLOAD):
|
||||
{
|
||||
. = ALIGN(8);
|
||||
_sheap = .;
|
||||
. = . + HEAP_SIZE;
|
||||
. = ALIGN(8);
|
||||
_eheap = .;
|
||||
} > ram
|
||||
|
||||
/* stack section */
|
||||
.stack (NOLOAD):
|
||||
{
|
||||
. = ALIGN(8);
|
||||
_sstack = .;
|
||||
. = . + STACK_SIZE;
|
||||
. = ALIGN(8);
|
||||
_estack = .;
|
||||
} > ram
|
||||
|
||||
. = ALIGN(4);
|
||||
_end = . ;
|
||||
_ram_end_ = ORIGIN(ram) + LENGTH(ram) - 1 ;
|
||||
}
|
||||
@ -0,0 +1,161 @@
|
||||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief GCC linker script (sram) for ATSAME70Q21
|
||||
*
|
||||
* Copyright (c) 2020 Microchip Technology Inc.
|
||||
*
|
||||
* \license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* \license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
/*------------------------------------------------------------------------------
|
||||
* Linker script for running in internal SRAM on the ATSAME70Q21
|
||||
*----------------------------------------------------------------------------*/
|
||||
|
||||
OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
|
||||
OUTPUT_ARCH(arm)
|
||||
SEARCH_DIR(.)
|
||||
|
||||
/* Memory Spaces Definitions */
|
||||
MEMORY
|
||||
{
|
||||
rom (rx) : ORIGIN = 0x00400000, LENGTH = 0x00200000 /* rom, 2097152K */
|
||||
ram (rwx) : ORIGIN = 0x20400000, LENGTH = 0x00060000 /* ram, 393216K */
|
||||
}
|
||||
|
||||
/* The stack size used by the application. NOTE: you need to adjust according to your application. */
|
||||
STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x0400;
|
||||
|
||||
/* The heapsize used by the application. NOTE: you need to adjust according to your application. */
|
||||
HEAP_SIZE = DEFINED(HEAP_SIZE) ? HEAP_SIZE : DEFINED(__heap_size__) ? __heap_size__ : 0x0200;
|
||||
|
||||
/* Section Definitions */
|
||||
SECTIONS
|
||||
{
|
||||
.text :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_sfixed = .;
|
||||
KEEP(*(.vectors .vectors.*))
|
||||
*(.text .text.* .gnu.linkonce.t.*)
|
||||
*(.glue_7t) *(.glue_7)
|
||||
*(.rodata .rodata* .gnu.linkonce.r.*)
|
||||
*(.ARM.extab* .gnu.linkonce.armextab.*)
|
||||
|
||||
/* Support C constructors, and C destructors in both user code
|
||||
and the C library. This also provides support for C++ code. */
|
||||
. = ALIGN(4);
|
||||
KEEP(*(.init))
|
||||
. = ALIGN(4);
|
||||
__preinit_array_start = .;
|
||||
KEEP (*(.preinit_array))
|
||||
__preinit_array_end = .;
|
||||
|
||||
. = ALIGN(4);
|
||||
__init_array_start = .;
|
||||
KEEP (*(SORT(.init_array.*)))
|
||||
KEEP (*(.init_array))
|
||||
__init_array_end = .;
|
||||
|
||||
. = ALIGN(4);
|
||||
KEEP (*crtbegin.o(.ctors))
|
||||
KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
|
||||
KEEP (*(SORT(.ctors.*)))
|
||||
KEEP (*crtend.o(.ctors))
|
||||
|
||||
. = ALIGN(4);
|
||||
KEEP(*(.fini))
|
||||
|
||||
. = ALIGN(4);
|
||||
__fini_array_start = .;
|
||||
KEEP (*(.fini_array))
|
||||
KEEP (*(SORT(.fini_array.*)))
|
||||
__fini_array_end = .;
|
||||
|
||||
KEEP (*crtbegin.o(.dtors))
|
||||
KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
|
||||
KEEP (*(SORT(.dtors.*)))
|
||||
KEEP (*crtend.o(.dtors))
|
||||
|
||||
. = ALIGN(4);
|
||||
_efixed = .; /* End of text section */
|
||||
} > ram
|
||||
|
||||
. = ALIGN(4);
|
||||
_etext = .;
|
||||
|
||||
.relocate : AT (_etext)
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_srelocate = .;
|
||||
*(.ramfunc .ramfunc.*);
|
||||
*(.data .data.*);
|
||||
. = ALIGN(4);
|
||||
_erelocate = .;
|
||||
} > ram
|
||||
|
||||
/* .bss section which is used for uninitialized data */
|
||||
.bss (NOLOAD) :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_sbss = . ;
|
||||
_szero = .;
|
||||
*(.bss .bss.*)
|
||||
*(COMMON)
|
||||
. = ALIGN(4);
|
||||
_ebss = . ;
|
||||
_ezero = .;
|
||||
} > ram
|
||||
|
||||
/* heap section */
|
||||
.heap (NOLOAD):
|
||||
{
|
||||
. = ALIGN(8);
|
||||
_sheap = .;
|
||||
. = . + HEAP_SIZE;
|
||||
. = ALIGN(8);
|
||||
_eheap = .;
|
||||
} > ram
|
||||
|
||||
/* stack section */
|
||||
.stack (NOLOAD):
|
||||
{
|
||||
. = ALIGN(8);
|
||||
_sstack = .;
|
||||
. = . + STACK_SIZE;
|
||||
. = ALIGN(8);
|
||||
_estack = .;
|
||||
} > ram
|
||||
|
||||
/* .ARM.exidx is sorted, so has to go in its own output section. */
|
||||
PROVIDE_HIDDEN (__exidx_start = .);
|
||||
.ARM.exidx :
|
||||
{
|
||||
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
|
||||
} > ram
|
||||
PROVIDE_HIDDEN (__exidx_end = .);
|
||||
|
||||
. = ALIGN(4);
|
||||
_end = . ;
|
||||
_ram_end_ = ORIGIN(ram) + LENGTH(ram) - 1 ;
|
||||
}
|
||||
|
||||
@ -0,0 +1,64 @@
|
||||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Component version header file
|
||||
*
|
||||
* Copyright (c) 2020 Atmel Corporation, a wholly owned subsidiary of Microchip Technology Inc.
|
||||
*
|
||||
* \license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* \license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _COMPONENT_VERSION_H_INCLUDED
|
||||
#define _COMPONENT_VERSION_H_INCLUDED
|
||||
|
||||
#define COMPONENT_VERSION_MAJOR 4
|
||||
#define COMPONENT_VERSION_MINOR 4
|
||||
|
||||
//
|
||||
// The COMPONENT_VERSION define is composed of the major and the minor version number.
|
||||
//
|
||||
// The last four digits of the COMPONENT_VERSION is the minor version with leading zeros.
|
||||
// The rest of the COMPONENT_VERSION is the major version.
|
||||
//
|
||||
#define COMPONENT_VERSION 40004
|
||||
|
||||
//
|
||||
// The build number does not refer to the component, but to the build number
|
||||
// of the device pack that provides the component.
|
||||
//
|
||||
#define BUILD_NUMBER 78
|
||||
|
||||
//
|
||||
// The COMPONENT_VERSION_STRING is a string (enclosed in ") that can be used for logging or embedding.
|
||||
//
|
||||
#define COMPONENT_VERSION_STRING "4.4"
|
||||
|
||||
//
|
||||
// The COMPONENT_DATE_STRING contains a timestamp of when the pack was generated.
|
||||
//
|
||||
// The COMPONENT_DATE_STRING is written out using the following strftime pattern.
|
||||
//
|
||||
// "%Y-%m-%d %H:%M:%S"
|
||||
//
|
||||
//
|
||||
#define COMPONENT_DATE_STRING "2020-09-24 08:34:52"
|
||||
|
||||
#endif/* #ifndef _COMPONENT_VERSION_H_INCLUDED */
|
||||
|
||||
@ -0,0 +1,215 @@
|
||||
/**
|
||||
* \brief Component description for ACC
|
||||
*
|
||||
* Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries.
|
||||
*
|
||||
* Subject to your compliance with these terms, you may use Microchip software and any derivatives
|
||||
* exclusively with Microchip products. It is your responsibility to comply with third party license
|
||||
* terms applicable to your use of third party software (including open source software) that may
|
||||
* accompany Microchip software.
|
||||
*
|
||||
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY,
|
||||
* APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND
|
||||
* FITNESS FOR A PARTICULAR PURPOSE.
|
||||
*
|
||||
* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
|
||||
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF
|
||||
* MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
|
||||
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT
|
||||
* EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
|
||||
*
|
||||
*/
|
||||
|
||||
/* file generated from device description version 2017-08-25T14:00:00Z */
|
||||
#ifndef _SAME70_ACC_COMPONENT_H_
|
||||
#define _SAME70_ACC_COMPONENT_H_
|
||||
|
||||
/* ************************************************************************** */
|
||||
/* SOFTWARE API DEFINITION FOR ACC */
|
||||
/* ************************************************************************** */
|
||||
|
||||
/* -------- ACC_CR : (ACC Offset: 0x00) ( /W 32) Control Register -------- */
|
||||
#define ACC_CR_SWRST_Pos _U_(0) /**< (ACC_CR) Software Reset Position */
|
||||
#define ACC_CR_SWRST_Msk (_U_(0x1) << ACC_CR_SWRST_Pos) /**< (ACC_CR) Software Reset Mask */
|
||||
#define ACC_CR_SWRST(value) (ACC_CR_SWRST_Msk & ((value) << ACC_CR_SWRST_Pos))
|
||||
#define ACC_CR_Msk _U_(0x00000001) /**< (ACC_CR) Register Mask */
|
||||
|
||||
|
||||
/* -------- ACC_MR : (ACC Offset: 0x04) (R/W 32) Mode Register -------- */
|
||||
#define ACC_MR_SELMINUS_Pos _U_(0) /**< (ACC_MR) Selection for Minus Comparator Input Position */
|
||||
#define ACC_MR_SELMINUS_Msk (_U_(0x7) << ACC_MR_SELMINUS_Pos) /**< (ACC_MR) Selection for Minus Comparator Input Mask */
|
||||
#define ACC_MR_SELMINUS(value) (ACC_MR_SELMINUS_Msk & ((value) << ACC_MR_SELMINUS_Pos))
|
||||
#define ACC_MR_SELMINUS_TS_Val _U_(0x0) /**< (ACC_MR) Select TS */
|
||||
#define ACC_MR_SELMINUS_VREFP_Val _U_(0x1) /**< (ACC_MR) Select VREFP */
|
||||
#define ACC_MR_SELMINUS_DAC0_Val _U_(0x2) /**< (ACC_MR) Select DAC0 */
|
||||
#define ACC_MR_SELMINUS_DAC1_Val _U_(0x3) /**< (ACC_MR) Select DAC1 */
|
||||
#define ACC_MR_SELMINUS_AFE0_AD0_Val _U_(0x4) /**< (ACC_MR) Select AFE0_AD0 */
|
||||
#define ACC_MR_SELMINUS_AFE0_AD1_Val _U_(0x5) /**< (ACC_MR) Select AFE0_AD1 */
|
||||
#define ACC_MR_SELMINUS_AFE0_AD2_Val _U_(0x6) /**< (ACC_MR) Select AFE0_AD2 */
|
||||
#define ACC_MR_SELMINUS_AFE0_AD3_Val _U_(0x7) /**< (ACC_MR) Select AFE0_AD3 */
|
||||
#define ACC_MR_SELMINUS_TS (ACC_MR_SELMINUS_TS_Val << ACC_MR_SELMINUS_Pos) /**< (ACC_MR) Select TS Position */
|
||||
#define ACC_MR_SELMINUS_VREFP (ACC_MR_SELMINUS_VREFP_Val << ACC_MR_SELMINUS_Pos) /**< (ACC_MR) Select VREFP Position */
|
||||
#define ACC_MR_SELMINUS_DAC0 (ACC_MR_SELMINUS_DAC0_Val << ACC_MR_SELMINUS_Pos) /**< (ACC_MR) Select DAC0 Position */
|
||||
#define ACC_MR_SELMINUS_DAC1 (ACC_MR_SELMINUS_DAC1_Val << ACC_MR_SELMINUS_Pos) /**< (ACC_MR) Select DAC1 Position */
|
||||
#define ACC_MR_SELMINUS_AFE0_AD0 (ACC_MR_SELMINUS_AFE0_AD0_Val << ACC_MR_SELMINUS_Pos) /**< (ACC_MR) Select AFE0_AD0 Position */
|
||||
#define ACC_MR_SELMINUS_AFE0_AD1 (ACC_MR_SELMINUS_AFE0_AD1_Val << ACC_MR_SELMINUS_Pos) /**< (ACC_MR) Select AFE0_AD1 Position */
|
||||
#define ACC_MR_SELMINUS_AFE0_AD2 (ACC_MR_SELMINUS_AFE0_AD2_Val << ACC_MR_SELMINUS_Pos) /**< (ACC_MR) Select AFE0_AD2 Position */
|
||||
#define ACC_MR_SELMINUS_AFE0_AD3 (ACC_MR_SELMINUS_AFE0_AD3_Val << ACC_MR_SELMINUS_Pos) /**< (ACC_MR) Select AFE0_AD3 Position */
|
||||
#define ACC_MR_SELPLUS_Pos _U_(4) /**< (ACC_MR) Selection For Plus Comparator Input Position */
|
||||
#define ACC_MR_SELPLUS_Msk (_U_(0x7) << ACC_MR_SELPLUS_Pos) /**< (ACC_MR) Selection For Plus Comparator Input Mask */
|
||||
#define ACC_MR_SELPLUS(value) (ACC_MR_SELPLUS_Msk & ((value) << ACC_MR_SELPLUS_Pos))
|
||||
#define ACC_MR_SELPLUS_AFE0_AD0_Val _U_(0x0) /**< (ACC_MR) Select AFE0_AD0 */
|
||||
#define ACC_MR_SELPLUS_AFE0_AD1_Val _U_(0x1) /**< (ACC_MR) Select AFE0_AD1 */
|
||||
#define ACC_MR_SELPLUS_AFE0_AD2_Val _U_(0x2) /**< (ACC_MR) Select AFE0_AD2 */
|
||||
#define ACC_MR_SELPLUS_AFE0_AD3_Val _U_(0x3) /**< (ACC_MR) Select AFE0_AD3 */
|
||||
#define ACC_MR_SELPLUS_AFE0_AD4_Val _U_(0x4) /**< (ACC_MR) Select AFE0_AD4 */
|
||||
#define ACC_MR_SELPLUS_AFE0_AD5_Val _U_(0x5) /**< (ACC_MR) Select AFE0_AD5 */
|
||||
#define ACC_MR_SELPLUS_AFE1_AD0_Val _U_(0x6) /**< (ACC_MR) Select AFE1_AD0 */
|
||||
#define ACC_MR_SELPLUS_AFE1_AD1_Val _U_(0x7) /**< (ACC_MR) Select AFE1_AD1 */
|
||||
#define ACC_MR_SELPLUS_AFE0_AD0 (ACC_MR_SELPLUS_AFE0_AD0_Val << ACC_MR_SELPLUS_Pos) /**< (ACC_MR) Select AFE0_AD0 Position */
|
||||
#define ACC_MR_SELPLUS_AFE0_AD1 (ACC_MR_SELPLUS_AFE0_AD1_Val << ACC_MR_SELPLUS_Pos) /**< (ACC_MR) Select AFE0_AD1 Position */
|
||||
#define ACC_MR_SELPLUS_AFE0_AD2 (ACC_MR_SELPLUS_AFE0_AD2_Val << ACC_MR_SELPLUS_Pos) /**< (ACC_MR) Select AFE0_AD2 Position */
|
||||
#define ACC_MR_SELPLUS_AFE0_AD3 (ACC_MR_SELPLUS_AFE0_AD3_Val << ACC_MR_SELPLUS_Pos) /**< (ACC_MR) Select AFE0_AD3 Position */
|
||||
#define ACC_MR_SELPLUS_AFE0_AD4 (ACC_MR_SELPLUS_AFE0_AD4_Val << ACC_MR_SELPLUS_Pos) /**< (ACC_MR) Select AFE0_AD4 Position */
|
||||
#define ACC_MR_SELPLUS_AFE0_AD5 (ACC_MR_SELPLUS_AFE0_AD5_Val << ACC_MR_SELPLUS_Pos) /**< (ACC_MR) Select AFE0_AD5 Position */
|
||||
#define ACC_MR_SELPLUS_AFE1_AD0 (ACC_MR_SELPLUS_AFE1_AD0_Val << ACC_MR_SELPLUS_Pos) /**< (ACC_MR) Select AFE1_AD0 Position */
|
||||
#define ACC_MR_SELPLUS_AFE1_AD1 (ACC_MR_SELPLUS_AFE1_AD1_Val << ACC_MR_SELPLUS_Pos) /**< (ACC_MR) Select AFE1_AD1 Position */
|
||||
#define ACC_MR_ACEN_Pos _U_(8) /**< (ACC_MR) Analog Comparator Enable Position */
|
||||
#define ACC_MR_ACEN_Msk (_U_(0x1) << ACC_MR_ACEN_Pos) /**< (ACC_MR) Analog Comparator Enable Mask */
|
||||
#define ACC_MR_ACEN(value) (ACC_MR_ACEN_Msk & ((value) << ACC_MR_ACEN_Pos))
|
||||
#define ACC_MR_ACEN_DIS_Val _U_(0x0) /**< (ACC_MR) Analog comparator disabled. */
|
||||
#define ACC_MR_ACEN_EN_Val _U_(0x1) /**< (ACC_MR) Analog comparator enabled. */
|
||||
#define ACC_MR_ACEN_DIS (ACC_MR_ACEN_DIS_Val << ACC_MR_ACEN_Pos) /**< (ACC_MR) Analog comparator disabled. Position */
|
||||
#define ACC_MR_ACEN_EN (ACC_MR_ACEN_EN_Val << ACC_MR_ACEN_Pos) /**< (ACC_MR) Analog comparator enabled. Position */
|
||||
#define ACC_MR_EDGETYP_Pos _U_(9) /**< (ACC_MR) Edge Type Position */
|
||||
#define ACC_MR_EDGETYP_Msk (_U_(0x3) << ACC_MR_EDGETYP_Pos) /**< (ACC_MR) Edge Type Mask */
|
||||
#define ACC_MR_EDGETYP(value) (ACC_MR_EDGETYP_Msk & ((value) << ACC_MR_EDGETYP_Pos))
|
||||
#define ACC_MR_EDGETYP_RISING_Val _U_(0x0) /**< (ACC_MR) Only rising edge of comparator output */
|
||||
#define ACC_MR_EDGETYP_FALLING_Val _U_(0x1) /**< (ACC_MR) Falling edge of comparator output */
|
||||
#define ACC_MR_EDGETYP_ANY_Val _U_(0x2) /**< (ACC_MR) Any edge of comparator output */
|
||||
#define ACC_MR_EDGETYP_RISING (ACC_MR_EDGETYP_RISING_Val << ACC_MR_EDGETYP_Pos) /**< (ACC_MR) Only rising edge of comparator output Position */
|
||||
#define ACC_MR_EDGETYP_FALLING (ACC_MR_EDGETYP_FALLING_Val << ACC_MR_EDGETYP_Pos) /**< (ACC_MR) Falling edge of comparator output Position */
|
||||
#define ACC_MR_EDGETYP_ANY (ACC_MR_EDGETYP_ANY_Val << ACC_MR_EDGETYP_Pos) /**< (ACC_MR) Any edge of comparator output Position */
|
||||
#define ACC_MR_INV_Pos _U_(12) /**< (ACC_MR) Invert Comparator Output Position */
|
||||
#define ACC_MR_INV_Msk (_U_(0x1) << ACC_MR_INV_Pos) /**< (ACC_MR) Invert Comparator Output Mask */
|
||||
#define ACC_MR_INV(value) (ACC_MR_INV_Msk & ((value) << ACC_MR_INV_Pos))
|
||||
#define ACC_MR_INV_DIS_Val _U_(0x0) /**< (ACC_MR) Analog comparator output is directly processed. */
|
||||
#define ACC_MR_INV_EN_Val _U_(0x1) /**< (ACC_MR) Analog comparator output is inverted prior to being processed. */
|
||||
#define ACC_MR_INV_DIS (ACC_MR_INV_DIS_Val << ACC_MR_INV_Pos) /**< (ACC_MR) Analog comparator output is directly processed. Position */
|
||||
#define ACC_MR_INV_EN (ACC_MR_INV_EN_Val << ACC_MR_INV_Pos) /**< (ACC_MR) Analog comparator output is inverted prior to being processed. Position */
|
||||
#define ACC_MR_SELFS_Pos _U_(13) /**< (ACC_MR) Selection Of Fault Source Position */
|
||||
#define ACC_MR_SELFS_Msk (_U_(0x1) << ACC_MR_SELFS_Pos) /**< (ACC_MR) Selection Of Fault Source Mask */
|
||||
#define ACC_MR_SELFS(value) (ACC_MR_SELFS_Msk & ((value) << ACC_MR_SELFS_Pos))
|
||||
#define ACC_MR_SELFS_CE_Val _U_(0x0) /**< (ACC_MR) The CE flag is used to drive the FAULT output. */
|
||||
#define ACC_MR_SELFS_OUTPUT_Val _U_(0x1) /**< (ACC_MR) The output of the analog comparator flag is used to drive the FAULT output. */
|
||||
#define ACC_MR_SELFS_CE (ACC_MR_SELFS_CE_Val << ACC_MR_SELFS_Pos) /**< (ACC_MR) The CE flag is used to drive the FAULT output. Position */
|
||||
#define ACC_MR_SELFS_OUTPUT (ACC_MR_SELFS_OUTPUT_Val << ACC_MR_SELFS_Pos) /**< (ACC_MR) The output of the analog comparator flag is used to drive the FAULT output. Position */
|
||||
#define ACC_MR_FE_Pos _U_(14) /**< (ACC_MR) Fault Enable Position */
|
||||
#define ACC_MR_FE_Msk (_U_(0x1) << ACC_MR_FE_Pos) /**< (ACC_MR) Fault Enable Mask */
|
||||
#define ACC_MR_FE(value) (ACC_MR_FE_Msk & ((value) << ACC_MR_FE_Pos))
|
||||
#define ACC_MR_FE_DIS_Val _U_(0x0) /**< (ACC_MR) The FAULT output is tied to 0. */
|
||||
#define ACC_MR_FE_EN_Val _U_(0x1) /**< (ACC_MR) The FAULT output is driven by the signal defined by SELFS. */
|
||||
#define ACC_MR_FE_DIS (ACC_MR_FE_DIS_Val << ACC_MR_FE_Pos) /**< (ACC_MR) The FAULT output is tied to 0. Position */
|
||||
#define ACC_MR_FE_EN (ACC_MR_FE_EN_Val << ACC_MR_FE_Pos) /**< (ACC_MR) The FAULT output is driven by the signal defined by SELFS. Position */
|
||||
#define ACC_MR_Msk _U_(0x00007777) /**< (ACC_MR) Register Mask */
|
||||
|
||||
|
||||
/* -------- ACC_IER : (ACC Offset: 0x24) ( /W 32) Interrupt Enable Register -------- */
|
||||
#define ACC_IER_CE_Pos _U_(0) /**< (ACC_IER) Comparison Edge Position */
|
||||
#define ACC_IER_CE_Msk (_U_(0x1) << ACC_IER_CE_Pos) /**< (ACC_IER) Comparison Edge Mask */
|
||||
#define ACC_IER_CE(value) (ACC_IER_CE_Msk & ((value) << ACC_IER_CE_Pos))
|
||||
#define ACC_IER_Msk _U_(0x00000001) /**< (ACC_IER) Register Mask */
|
||||
|
||||
|
||||
/* -------- ACC_IDR : (ACC Offset: 0x28) ( /W 32) Interrupt Disable Register -------- */
|
||||
#define ACC_IDR_CE_Pos _U_(0) /**< (ACC_IDR) Comparison Edge Position */
|
||||
#define ACC_IDR_CE_Msk (_U_(0x1) << ACC_IDR_CE_Pos) /**< (ACC_IDR) Comparison Edge Mask */
|
||||
#define ACC_IDR_CE(value) (ACC_IDR_CE_Msk & ((value) << ACC_IDR_CE_Pos))
|
||||
#define ACC_IDR_Msk _U_(0x00000001) /**< (ACC_IDR) Register Mask */
|
||||
|
||||
|
||||
/* -------- ACC_IMR : (ACC Offset: 0x2C) ( R/ 32) Interrupt Mask Register -------- */
|
||||
#define ACC_IMR_CE_Pos _U_(0) /**< (ACC_IMR) Comparison Edge Position */
|
||||
#define ACC_IMR_CE_Msk (_U_(0x1) << ACC_IMR_CE_Pos) /**< (ACC_IMR) Comparison Edge Mask */
|
||||
#define ACC_IMR_CE(value) (ACC_IMR_CE_Msk & ((value) << ACC_IMR_CE_Pos))
|
||||
#define ACC_IMR_Msk _U_(0x00000001) /**< (ACC_IMR) Register Mask */
|
||||
|
||||
|
||||
/* -------- ACC_ISR : (ACC Offset: 0x30) ( R/ 32) Interrupt Status Register -------- */
|
||||
#define ACC_ISR_CE_Pos _U_(0) /**< (ACC_ISR) Comparison Edge (cleared on read) Position */
|
||||
#define ACC_ISR_CE_Msk (_U_(0x1) << ACC_ISR_CE_Pos) /**< (ACC_ISR) Comparison Edge (cleared on read) Mask */
|
||||
#define ACC_ISR_CE(value) (ACC_ISR_CE_Msk & ((value) << ACC_ISR_CE_Pos))
|
||||
#define ACC_ISR_SCO_Pos _U_(1) /**< (ACC_ISR) Synchronized Comparator Output Position */
|
||||
#define ACC_ISR_SCO_Msk (_U_(0x1) << ACC_ISR_SCO_Pos) /**< (ACC_ISR) Synchronized Comparator Output Mask */
|
||||
#define ACC_ISR_SCO(value) (ACC_ISR_SCO_Msk & ((value) << ACC_ISR_SCO_Pos))
|
||||
#define ACC_ISR_MASK_Pos _U_(31) /**< (ACC_ISR) Flag Mask Position */
|
||||
#define ACC_ISR_MASK_Msk (_U_(0x1) << ACC_ISR_MASK_Pos) /**< (ACC_ISR) Flag Mask Mask */
|
||||
#define ACC_ISR_MASK(value) (ACC_ISR_MASK_Msk & ((value) << ACC_ISR_MASK_Pos))
|
||||
#define ACC_ISR_Msk _U_(0x80000003) /**< (ACC_ISR) Register Mask */
|
||||
|
||||
|
||||
/* -------- ACC_ACR : (ACC Offset: 0x94) (R/W 32) Analog Control Register -------- */
|
||||
#define ACC_ACR_ISEL_Pos _U_(0) /**< (ACC_ACR) Current Selection Position */
|
||||
#define ACC_ACR_ISEL_Msk (_U_(0x1) << ACC_ACR_ISEL_Pos) /**< (ACC_ACR) Current Selection Mask */
|
||||
#define ACC_ACR_ISEL(value) (ACC_ACR_ISEL_Msk & ((value) << ACC_ACR_ISEL_Pos))
|
||||
#define ACC_ACR_ISEL_LOPW_Val _U_(0x0) /**< (ACC_ACR) Low-power option. */
|
||||
#define ACC_ACR_ISEL_HISP_Val _U_(0x1) /**< (ACC_ACR) High-speed option. */
|
||||
#define ACC_ACR_ISEL_LOPW (ACC_ACR_ISEL_LOPW_Val << ACC_ACR_ISEL_Pos) /**< (ACC_ACR) Low-power option. Position */
|
||||
#define ACC_ACR_ISEL_HISP (ACC_ACR_ISEL_HISP_Val << ACC_ACR_ISEL_Pos) /**< (ACC_ACR) High-speed option. Position */
|
||||
#define ACC_ACR_HYST_Pos _U_(1) /**< (ACC_ACR) Hysteresis Selection Position */
|
||||
#define ACC_ACR_HYST_Msk (_U_(0x3) << ACC_ACR_HYST_Pos) /**< (ACC_ACR) Hysteresis Selection Mask */
|
||||
#define ACC_ACR_HYST(value) (ACC_ACR_HYST_Msk & ((value) << ACC_ACR_HYST_Pos))
|
||||
#define ACC_ACR_Msk _U_(0x00000007) /**< (ACC_ACR) Register Mask */
|
||||
|
||||
|
||||
/* -------- ACC_WPMR : (ACC Offset: 0xE4) (R/W 32) Write Protection Mode Register -------- */
|
||||
#define ACC_WPMR_WPEN_Pos _U_(0) /**< (ACC_WPMR) Write Protection Enable Position */
|
||||
#define ACC_WPMR_WPEN_Msk (_U_(0x1) << ACC_WPMR_WPEN_Pos) /**< (ACC_WPMR) Write Protection Enable Mask */
|
||||
#define ACC_WPMR_WPEN(value) (ACC_WPMR_WPEN_Msk & ((value) << ACC_WPMR_WPEN_Pos))
|
||||
#define ACC_WPMR_WPKEY_Pos _U_(8) /**< (ACC_WPMR) Write Protection Key Position */
|
||||
#define ACC_WPMR_WPKEY_Msk (_U_(0xFFFFFF) << ACC_WPMR_WPKEY_Pos) /**< (ACC_WPMR) Write Protection Key Mask */
|
||||
#define ACC_WPMR_WPKEY(value) (ACC_WPMR_WPKEY_Msk & ((value) << ACC_WPMR_WPKEY_Pos))
|
||||
#define ACC_WPMR_WPKEY_PASSWD_Val _U_(0x414343) /**< (ACC_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. */
|
||||
#define ACC_WPMR_WPKEY_PASSWD (ACC_WPMR_WPKEY_PASSWD_Val << ACC_WPMR_WPKEY_Pos) /**< (ACC_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. Position */
|
||||
#define ACC_WPMR_Msk _U_(0xFFFFFF01) /**< (ACC_WPMR) Register Mask */
|
||||
|
||||
|
||||
/* -------- ACC_WPSR : (ACC Offset: 0xE8) ( R/ 32) Write Protection Status Register -------- */
|
||||
#define ACC_WPSR_WPVS_Pos _U_(0) /**< (ACC_WPSR) Write Protection Violation Status Position */
|
||||
#define ACC_WPSR_WPVS_Msk (_U_(0x1) << ACC_WPSR_WPVS_Pos) /**< (ACC_WPSR) Write Protection Violation Status Mask */
|
||||
#define ACC_WPSR_WPVS(value) (ACC_WPSR_WPVS_Msk & ((value) << ACC_WPSR_WPVS_Pos))
|
||||
#define ACC_WPSR_Msk _U_(0x00000001) /**< (ACC_WPSR) Register Mask */
|
||||
|
||||
|
||||
/** \brief ACC register offsets definitions */
|
||||
#define ACC_CR_REG_OFST (0x00) /**< (ACC_CR) Control Register Offset */
|
||||
#define ACC_MR_REG_OFST (0x04) /**< (ACC_MR) Mode Register Offset */
|
||||
#define ACC_IER_REG_OFST (0x24) /**< (ACC_IER) Interrupt Enable Register Offset */
|
||||
#define ACC_IDR_REG_OFST (0x28) /**< (ACC_IDR) Interrupt Disable Register Offset */
|
||||
#define ACC_IMR_REG_OFST (0x2C) /**< (ACC_IMR) Interrupt Mask Register Offset */
|
||||
#define ACC_ISR_REG_OFST (0x30) /**< (ACC_ISR) Interrupt Status Register Offset */
|
||||
#define ACC_ACR_REG_OFST (0x94) /**< (ACC_ACR) Analog Control Register Offset */
|
||||
#define ACC_WPMR_REG_OFST (0xE4) /**< (ACC_WPMR) Write Protection Mode Register Offset */
|
||||
#define ACC_WPSR_REG_OFST (0xE8) /**< (ACC_WPSR) Write Protection Status Register Offset */
|
||||
|
||||
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
/** \brief ACC register API structure */
|
||||
typedef struct
|
||||
{
|
||||
__O uint32_t ACC_CR; /**< Offset: 0x00 ( /W 32) Control Register */
|
||||
__IO uint32_t ACC_MR; /**< Offset: 0x04 (R/W 32) Mode Register */
|
||||
__I uint8_t Reserved1[0x1C];
|
||||
__O uint32_t ACC_IER; /**< Offset: 0x24 ( /W 32) Interrupt Enable Register */
|
||||
__O uint32_t ACC_IDR; /**< Offset: 0x28 ( /W 32) Interrupt Disable Register */
|
||||
__I uint32_t ACC_IMR; /**< Offset: 0x2C (R/ 32) Interrupt Mask Register */
|
||||
__I uint32_t ACC_ISR; /**< Offset: 0x30 (R/ 32) Interrupt Status Register */
|
||||
__I uint8_t Reserved2[0x60];
|
||||
__IO uint32_t ACC_ACR; /**< Offset: 0x94 (R/W 32) Analog Control Register */
|
||||
__I uint8_t Reserved3[0x4C];
|
||||
__IO uint32_t ACC_WPMR; /**< Offset: 0xE4 (R/W 32) Write Protection Mode Register */
|
||||
__I uint32_t ACC_WPSR; /**< Offset: 0xE8 (R/ 32) Write Protection Status Register */
|
||||
} acc_registers_t;
|
||||
|
||||
|
||||
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
#endif /* _SAME70_ACC_COMPONENT_H_ */
|
||||
@ -0,0 +1,295 @@
|
||||
/**
|
||||
* \brief Component description for AES
|
||||
*
|
||||
* Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries.
|
||||
*
|
||||
* Subject to your compliance with these terms, you may use Microchip software and any derivatives
|
||||
* exclusively with Microchip products. It is your responsibility to comply with third party license
|
||||
* terms applicable to your use of third party software (including open source software) that may
|
||||
* accompany Microchip software.
|
||||
*
|
||||
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY,
|
||||
* APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND
|
||||
* FITNESS FOR A PARTICULAR PURPOSE.
|
||||
*
|
||||
* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
|
||||
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF
|
||||
* MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
|
||||
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT
|
||||
* EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
|
||||
*
|
||||
*/
|
||||
|
||||
/* file generated from device description version 2017-08-25T14:00:00Z */
|
||||
#ifndef _SAME70_AES_COMPONENT_H_
|
||||
#define _SAME70_AES_COMPONENT_H_
|
||||
|
||||
/* ************************************************************************** */
|
||||
/* SOFTWARE API DEFINITION FOR AES */
|
||||
/* ************************************************************************** */
|
||||
|
||||
/* -------- AES_CR : (AES Offset: 0x00) ( /W 32) Control Register -------- */
|
||||
#define AES_CR_START_Pos _U_(0) /**< (AES_CR) Start Processing Position */
|
||||
#define AES_CR_START_Msk (_U_(0x1) << AES_CR_START_Pos) /**< (AES_CR) Start Processing Mask */
|
||||
#define AES_CR_START(value) (AES_CR_START_Msk & ((value) << AES_CR_START_Pos))
|
||||
#define AES_CR_SWRST_Pos _U_(8) /**< (AES_CR) Software Reset Position */
|
||||
#define AES_CR_SWRST_Msk (_U_(0x1) << AES_CR_SWRST_Pos) /**< (AES_CR) Software Reset Mask */
|
||||
#define AES_CR_SWRST(value) (AES_CR_SWRST_Msk & ((value) << AES_CR_SWRST_Pos))
|
||||
#define AES_CR_Msk _U_(0x00000101) /**< (AES_CR) Register Mask */
|
||||
|
||||
|
||||
/* -------- AES_MR : (AES Offset: 0x04) (R/W 32) Mode Register -------- */
|
||||
#define AES_MR_CIPHER_Pos _U_(0) /**< (AES_MR) Processing Mode Position */
|
||||
#define AES_MR_CIPHER_Msk (_U_(0x1) << AES_MR_CIPHER_Pos) /**< (AES_MR) Processing Mode Mask */
|
||||
#define AES_MR_CIPHER(value) (AES_MR_CIPHER_Msk & ((value) << AES_MR_CIPHER_Pos))
|
||||
#define AES_MR_GTAGEN_Pos _U_(1) /**< (AES_MR) GCM Automatic Tag Generation Enable Position */
|
||||
#define AES_MR_GTAGEN_Msk (_U_(0x1) << AES_MR_GTAGEN_Pos) /**< (AES_MR) GCM Automatic Tag Generation Enable Mask */
|
||||
#define AES_MR_GTAGEN(value) (AES_MR_GTAGEN_Msk & ((value) << AES_MR_GTAGEN_Pos))
|
||||
#define AES_MR_DUALBUFF_Pos _U_(3) /**< (AES_MR) Dual Input Buffer Position */
|
||||
#define AES_MR_DUALBUFF_Msk (_U_(0x1) << AES_MR_DUALBUFF_Pos) /**< (AES_MR) Dual Input Buffer Mask */
|
||||
#define AES_MR_DUALBUFF(value) (AES_MR_DUALBUFF_Msk & ((value) << AES_MR_DUALBUFF_Pos))
|
||||
#define AES_MR_DUALBUFF_INACTIVE_Val _U_(0x0) /**< (AES_MR) AES_IDATARx cannot be written during processing of previous block. */
|
||||
#define AES_MR_DUALBUFF_ACTIVE_Val _U_(0x1) /**< (AES_MR) AES_IDATARx can be written during processing of previous block when SMOD = 2. It speeds up the overall runtime of large files. */
|
||||
#define AES_MR_DUALBUFF_INACTIVE (AES_MR_DUALBUFF_INACTIVE_Val << AES_MR_DUALBUFF_Pos) /**< (AES_MR) AES_IDATARx cannot be written during processing of previous block. Position */
|
||||
#define AES_MR_DUALBUFF_ACTIVE (AES_MR_DUALBUFF_ACTIVE_Val << AES_MR_DUALBUFF_Pos) /**< (AES_MR) AES_IDATARx can be written during processing of previous block when SMOD = 2. It speeds up the overall runtime of large files. Position */
|
||||
#define AES_MR_PROCDLY_Pos _U_(4) /**< (AES_MR) Processing Delay Position */
|
||||
#define AES_MR_PROCDLY_Msk (_U_(0xF) << AES_MR_PROCDLY_Pos) /**< (AES_MR) Processing Delay Mask */
|
||||
#define AES_MR_PROCDLY(value) (AES_MR_PROCDLY_Msk & ((value) << AES_MR_PROCDLY_Pos))
|
||||
#define AES_MR_SMOD_Pos _U_(8) /**< (AES_MR) Start Mode Position */
|
||||
#define AES_MR_SMOD_Msk (_U_(0x3) << AES_MR_SMOD_Pos) /**< (AES_MR) Start Mode Mask */
|
||||
#define AES_MR_SMOD(value) (AES_MR_SMOD_Msk & ((value) << AES_MR_SMOD_Pos))
|
||||
#define AES_MR_SMOD_MANUAL_START_Val _U_(0x0) /**< (AES_MR) Manual Mode */
|
||||
#define AES_MR_SMOD_AUTO_START_Val _U_(0x1) /**< (AES_MR) Auto Mode */
|
||||
#define AES_MR_SMOD_IDATAR0_START_Val _U_(0x2) /**< (AES_MR) AES_IDATAR0 access only Auto Mode (DMA) */
|
||||
#define AES_MR_SMOD_MANUAL_START (AES_MR_SMOD_MANUAL_START_Val << AES_MR_SMOD_Pos) /**< (AES_MR) Manual Mode Position */
|
||||
#define AES_MR_SMOD_AUTO_START (AES_MR_SMOD_AUTO_START_Val << AES_MR_SMOD_Pos) /**< (AES_MR) Auto Mode Position */
|
||||
#define AES_MR_SMOD_IDATAR0_START (AES_MR_SMOD_IDATAR0_START_Val << AES_MR_SMOD_Pos) /**< (AES_MR) AES_IDATAR0 access only Auto Mode (DMA) Position */
|
||||
#define AES_MR_KEYSIZE_Pos _U_(10) /**< (AES_MR) Key Size Position */
|
||||
#define AES_MR_KEYSIZE_Msk (_U_(0x3) << AES_MR_KEYSIZE_Pos) /**< (AES_MR) Key Size Mask */
|
||||
#define AES_MR_KEYSIZE(value) (AES_MR_KEYSIZE_Msk & ((value) << AES_MR_KEYSIZE_Pos))
|
||||
#define AES_MR_KEYSIZE_AES128_Val _U_(0x0) /**< (AES_MR) AES Key Size is 128 bits */
|
||||
#define AES_MR_KEYSIZE_AES192_Val _U_(0x1) /**< (AES_MR) AES Key Size is 192 bits */
|
||||
#define AES_MR_KEYSIZE_AES256_Val _U_(0x2) /**< (AES_MR) AES Key Size is 256 bits */
|
||||
#define AES_MR_KEYSIZE_AES128 (AES_MR_KEYSIZE_AES128_Val << AES_MR_KEYSIZE_Pos) /**< (AES_MR) AES Key Size is 128 bits Position */
|
||||
#define AES_MR_KEYSIZE_AES192 (AES_MR_KEYSIZE_AES192_Val << AES_MR_KEYSIZE_Pos) /**< (AES_MR) AES Key Size is 192 bits Position */
|
||||
#define AES_MR_KEYSIZE_AES256 (AES_MR_KEYSIZE_AES256_Val << AES_MR_KEYSIZE_Pos) /**< (AES_MR) AES Key Size is 256 bits Position */
|
||||
#define AES_MR_OPMOD_Pos _U_(12) /**< (AES_MR) Operating Mode Position */
|
||||
#define AES_MR_OPMOD_Msk (_U_(0x7) << AES_MR_OPMOD_Pos) /**< (AES_MR) Operating Mode Mask */
|
||||
#define AES_MR_OPMOD(value) (AES_MR_OPMOD_Msk & ((value) << AES_MR_OPMOD_Pos))
|
||||
#define AES_MR_OPMOD_ECB_Val _U_(0x0) /**< (AES_MR) ECB: Electronic Code Book mode */
|
||||
#define AES_MR_OPMOD_CBC_Val _U_(0x1) /**< (AES_MR) CBC: Cipher Block Chaining mode */
|
||||
#define AES_MR_OPMOD_OFB_Val _U_(0x2) /**< (AES_MR) OFB: Output Feedback mode */
|
||||
#define AES_MR_OPMOD_CFB_Val _U_(0x3) /**< (AES_MR) CFB: Cipher Feedback mode */
|
||||
#define AES_MR_OPMOD_CTR_Val _U_(0x4) /**< (AES_MR) CTR: Counter mode (16-bit internal counter) */
|
||||
#define AES_MR_OPMOD_GCM_Val _U_(0x5) /**< (AES_MR) GCM: Galois/Counter mode */
|
||||
#define AES_MR_OPMOD_ECB (AES_MR_OPMOD_ECB_Val << AES_MR_OPMOD_Pos) /**< (AES_MR) ECB: Electronic Code Book mode Position */
|
||||
#define AES_MR_OPMOD_CBC (AES_MR_OPMOD_CBC_Val << AES_MR_OPMOD_Pos) /**< (AES_MR) CBC: Cipher Block Chaining mode Position */
|
||||
#define AES_MR_OPMOD_OFB (AES_MR_OPMOD_OFB_Val << AES_MR_OPMOD_Pos) /**< (AES_MR) OFB: Output Feedback mode Position */
|
||||
#define AES_MR_OPMOD_CFB (AES_MR_OPMOD_CFB_Val << AES_MR_OPMOD_Pos) /**< (AES_MR) CFB: Cipher Feedback mode Position */
|
||||
#define AES_MR_OPMOD_CTR (AES_MR_OPMOD_CTR_Val << AES_MR_OPMOD_Pos) /**< (AES_MR) CTR: Counter mode (16-bit internal counter) Position */
|
||||
#define AES_MR_OPMOD_GCM (AES_MR_OPMOD_GCM_Val << AES_MR_OPMOD_Pos) /**< (AES_MR) GCM: Galois/Counter mode Position */
|
||||
#define AES_MR_LOD_Pos _U_(15) /**< (AES_MR) Last Output Data Mode Position */
|
||||
#define AES_MR_LOD_Msk (_U_(0x1) << AES_MR_LOD_Pos) /**< (AES_MR) Last Output Data Mode Mask */
|
||||
#define AES_MR_LOD(value) (AES_MR_LOD_Msk & ((value) << AES_MR_LOD_Pos))
|
||||
#define AES_MR_CFBS_Pos _U_(16) /**< (AES_MR) Cipher Feedback Data Size Position */
|
||||
#define AES_MR_CFBS_Msk (_U_(0x7) << AES_MR_CFBS_Pos) /**< (AES_MR) Cipher Feedback Data Size Mask */
|
||||
#define AES_MR_CFBS(value) (AES_MR_CFBS_Msk & ((value) << AES_MR_CFBS_Pos))
|
||||
#define AES_MR_CFBS_SIZE_128BIT_Val _U_(0x0) /**< (AES_MR) 128-bit */
|
||||
#define AES_MR_CFBS_SIZE_64BIT_Val _U_(0x1) /**< (AES_MR) 64-bit */
|
||||
#define AES_MR_CFBS_SIZE_32BIT_Val _U_(0x2) /**< (AES_MR) 32-bit */
|
||||
#define AES_MR_CFBS_SIZE_16BIT_Val _U_(0x3) /**< (AES_MR) 16-bit */
|
||||
#define AES_MR_CFBS_SIZE_8BIT_Val _U_(0x4) /**< (AES_MR) 8-bit */
|
||||
#define AES_MR_CFBS_SIZE_128BIT (AES_MR_CFBS_SIZE_128BIT_Val << AES_MR_CFBS_Pos) /**< (AES_MR) 128-bit Position */
|
||||
#define AES_MR_CFBS_SIZE_64BIT (AES_MR_CFBS_SIZE_64BIT_Val << AES_MR_CFBS_Pos) /**< (AES_MR) 64-bit Position */
|
||||
#define AES_MR_CFBS_SIZE_32BIT (AES_MR_CFBS_SIZE_32BIT_Val << AES_MR_CFBS_Pos) /**< (AES_MR) 32-bit Position */
|
||||
#define AES_MR_CFBS_SIZE_16BIT (AES_MR_CFBS_SIZE_16BIT_Val << AES_MR_CFBS_Pos) /**< (AES_MR) 16-bit Position */
|
||||
#define AES_MR_CFBS_SIZE_8BIT (AES_MR_CFBS_SIZE_8BIT_Val << AES_MR_CFBS_Pos) /**< (AES_MR) 8-bit Position */
|
||||
#define AES_MR_CKEY_Pos _U_(20) /**< (AES_MR) Countermeasure Key Position */
|
||||
#define AES_MR_CKEY_Msk (_U_(0xF) << AES_MR_CKEY_Pos) /**< (AES_MR) Countermeasure Key Mask */
|
||||
#define AES_MR_CKEY(value) (AES_MR_CKEY_Msk & ((value) << AES_MR_CKEY_Pos))
|
||||
#define AES_MR_CKEY_PASSWD_Val _U_(0xE) /**< (AES_MR) This field must be written with 0xE to allow CMTYPx bit configuration changes. Any other values will abort the write operation in CMTYPx bits.Always reads as 0. */
|
||||
#define AES_MR_CKEY_PASSWD (AES_MR_CKEY_PASSWD_Val << AES_MR_CKEY_Pos) /**< (AES_MR) This field must be written with 0xE to allow CMTYPx bit configuration changes. Any other values will abort the write operation in CMTYPx bits.Always reads as 0. Position */
|
||||
#define AES_MR_Msk _U_(0x00F7FFFB) /**< (AES_MR) Register Mask */
|
||||
|
||||
|
||||
/* -------- AES_IER : (AES Offset: 0x10) ( /W 32) Interrupt Enable Register -------- */
|
||||
#define AES_IER_DATRDY_Pos _U_(0) /**< (AES_IER) Data Ready Interrupt Enable Position */
|
||||
#define AES_IER_DATRDY_Msk (_U_(0x1) << AES_IER_DATRDY_Pos) /**< (AES_IER) Data Ready Interrupt Enable Mask */
|
||||
#define AES_IER_DATRDY(value) (AES_IER_DATRDY_Msk & ((value) << AES_IER_DATRDY_Pos))
|
||||
#define AES_IER_URAD_Pos _U_(8) /**< (AES_IER) Unspecified Register Access Detection Interrupt Enable Position */
|
||||
#define AES_IER_URAD_Msk (_U_(0x1) << AES_IER_URAD_Pos) /**< (AES_IER) Unspecified Register Access Detection Interrupt Enable Mask */
|
||||
#define AES_IER_URAD(value) (AES_IER_URAD_Msk & ((value) << AES_IER_URAD_Pos))
|
||||
#define AES_IER_TAGRDY_Pos _U_(16) /**< (AES_IER) GCM Tag Ready Interrupt Enable Position */
|
||||
#define AES_IER_TAGRDY_Msk (_U_(0x1) << AES_IER_TAGRDY_Pos) /**< (AES_IER) GCM Tag Ready Interrupt Enable Mask */
|
||||
#define AES_IER_TAGRDY(value) (AES_IER_TAGRDY_Msk & ((value) << AES_IER_TAGRDY_Pos))
|
||||
#define AES_IER_Msk _U_(0x00010101) /**< (AES_IER) Register Mask */
|
||||
|
||||
|
||||
/* -------- AES_IDR : (AES Offset: 0x14) ( /W 32) Interrupt Disable Register -------- */
|
||||
#define AES_IDR_DATRDY_Pos _U_(0) /**< (AES_IDR) Data Ready Interrupt Disable Position */
|
||||
#define AES_IDR_DATRDY_Msk (_U_(0x1) << AES_IDR_DATRDY_Pos) /**< (AES_IDR) Data Ready Interrupt Disable Mask */
|
||||
#define AES_IDR_DATRDY(value) (AES_IDR_DATRDY_Msk & ((value) << AES_IDR_DATRDY_Pos))
|
||||
#define AES_IDR_URAD_Pos _U_(8) /**< (AES_IDR) Unspecified Register Access Detection Interrupt Disable Position */
|
||||
#define AES_IDR_URAD_Msk (_U_(0x1) << AES_IDR_URAD_Pos) /**< (AES_IDR) Unspecified Register Access Detection Interrupt Disable Mask */
|
||||
#define AES_IDR_URAD(value) (AES_IDR_URAD_Msk & ((value) << AES_IDR_URAD_Pos))
|
||||
#define AES_IDR_TAGRDY_Pos _U_(16) /**< (AES_IDR) GCM Tag Ready Interrupt Disable Position */
|
||||
#define AES_IDR_TAGRDY_Msk (_U_(0x1) << AES_IDR_TAGRDY_Pos) /**< (AES_IDR) GCM Tag Ready Interrupt Disable Mask */
|
||||
#define AES_IDR_TAGRDY(value) (AES_IDR_TAGRDY_Msk & ((value) << AES_IDR_TAGRDY_Pos))
|
||||
#define AES_IDR_Msk _U_(0x00010101) /**< (AES_IDR) Register Mask */
|
||||
|
||||
|
||||
/* -------- AES_IMR : (AES Offset: 0x18) ( R/ 32) Interrupt Mask Register -------- */
|
||||
#define AES_IMR_DATRDY_Pos _U_(0) /**< (AES_IMR) Data Ready Interrupt Mask Position */
|
||||
#define AES_IMR_DATRDY_Msk (_U_(0x1) << AES_IMR_DATRDY_Pos) /**< (AES_IMR) Data Ready Interrupt Mask Mask */
|
||||
#define AES_IMR_DATRDY(value) (AES_IMR_DATRDY_Msk & ((value) << AES_IMR_DATRDY_Pos))
|
||||
#define AES_IMR_URAD_Pos _U_(8) /**< (AES_IMR) Unspecified Register Access Detection Interrupt Mask Position */
|
||||
#define AES_IMR_URAD_Msk (_U_(0x1) << AES_IMR_URAD_Pos) /**< (AES_IMR) Unspecified Register Access Detection Interrupt Mask Mask */
|
||||
#define AES_IMR_URAD(value) (AES_IMR_URAD_Msk & ((value) << AES_IMR_URAD_Pos))
|
||||
#define AES_IMR_TAGRDY_Pos _U_(16) /**< (AES_IMR) GCM Tag Ready Interrupt Mask Position */
|
||||
#define AES_IMR_TAGRDY_Msk (_U_(0x1) << AES_IMR_TAGRDY_Pos) /**< (AES_IMR) GCM Tag Ready Interrupt Mask Mask */
|
||||
#define AES_IMR_TAGRDY(value) (AES_IMR_TAGRDY_Msk & ((value) << AES_IMR_TAGRDY_Pos))
|
||||
#define AES_IMR_Msk _U_(0x00010101) /**< (AES_IMR) Register Mask */
|
||||
|
||||
|
||||
/* -------- AES_ISR : (AES Offset: 0x1C) ( R/ 32) Interrupt Status Register -------- */
|
||||
#define AES_ISR_DATRDY_Pos _U_(0) /**< (AES_ISR) Data Ready (cleared by setting bit START or bit SWRST in AES_CR or by reading AES_ODATARx) Position */
|
||||
#define AES_ISR_DATRDY_Msk (_U_(0x1) << AES_ISR_DATRDY_Pos) /**< (AES_ISR) Data Ready (cleared by setting bit START or bit SWRST in AES_CR or by reading AES_ODATARx) Mask */
|
||||
#define AES_ISR_DATRDY(value) (AES_ISR_DATRDY_Msk & ((value) << AES_ISR_DATRDY_Pos))
|
||||
#define AES_ISR_URAD_Pos _U_(8) /**< (AES_ISR) Unspecified Register Access Detection Status (cleared by writing SWRST in AES_CR) Position */
|
||||
#define AES_ISR_URAD_Msk (_U_(0x1) << AES_ISR_URAD_Pos) /**< (AES_ISR) Unspecified Register Access Detection Status (cleared by writing SWRST in AES_CR) Mask */
|
||||
#define AES_ISR_URAD(value) (AES_ISR_URAD_Msk & ((value) << AES_ISR_URAD_Pos))
|
||||
#define AES_ISR_URAT_Pos _U_(12) /**< (AES_ISR) Unspecified Register Access (cleared by writing SWRST in AES_CR) Position */
|
||||
#define AES_ISR_URAT_Msk (_U_(0xF) << AES_ISR_URAT_Pos) /**< (AES_ISR) Unspecified Register Access (cleared by writing SWRST in AES_CR) Mask */
|
||||
#define AES_ISR_URAT(value) (AES_ISR_URAT_Msk & ((value) << AES_ISR_URAT_Pos))
|
||||
#define AES_ISR_URAT_IDR_WR_PROCESSING_Val _U_(0x0) /**< (AES_ISR) Input Data Register written during the data processing when SMOD = 0x2 mode. */
|
||||
#define AES_ISR_URAT_ODR_RD_PROCESSING_Val _U_(0x1) /**< (AES_ISR) Output Data Register read during the data processing. */
|
||||
#define AES_ISR_URAT_MR_WR_PROCESSING_Val _U_(0x2) /**< (AES_ISR) Mode Register written during the data processing. */
|
||||
#define AES_ISR_URAT_ODR_RD_SUBKGEN_Val _U_(0x3) /**< (AES_ISR) Output Data Register read during the sub-keys generation. */
|
||||
#define AES_ISR_URAT_MR_WR_SUBKGEN_Val _U_(0x4) /**< (AES_ISR) Mode Register written during the sub-keys generation. */
|
||||
#define AES_ISR_URAT_WOR_RD_ACCESS_Val _U_(0x5) /**< (AES_ISR) Write-only register read access. */
|
||||
#define AES_ISR_URAT_IDR_WR_PROCESSING (AES_ISR_URAT_IDR_WR_PROCESSING_Val << AES_ISR_URAT_Pos) /**< (AES_ISR) Input Data Register written during the data processing when SMOD = 0x2 mode. Position */
|
||||
#define AES_ISR_URAT_ODR_RD_PROCESSING (AES_ISR_URAT_ODR_RD_PROCESSING_Val << AES_ISR_URAT_Pos) /**< (AES_ISR) Output Data Register read during the data processing. Position */
|
||||
#define AES_ISR_URAT_MR_WR_PROCESSING (AES_ISR_URAT_MR_WR_PROCESSING_Val << AES_ISR_URAT_Pos) /**< (AES_ISR) Mode Register written during the data processing. Position */
|
||||
#define AES_ISR_URAT_ODR_RD_SUBKGEN (AES_ISR_URAT_ODR_RD_SUBKGEN_Val << AES_ISR_URAT_Pos) /**< (AES_ISR) Output Data Register read during the sub-keys generation. Position */
|
||||
#define AES_ISR_URAT_MR_WR_SUBKGEN (AES_ISR_URAT_MR_WR_SUBKGEN_Val << AES_ISR_URAT_Pos) /**< (AES_ISR) Mode Register written during the sub-keys generation. Position */
|
||||
#define AES_ISR_URAT_WOR_RD_ACCESS (AES_ISR_URAT_WOR_RD_ACCESS_Val << AES_ISR_URAT_Pos) /**< (AES_ISR) Write-only register read access. Position */
|
||||
#define AES_ISR_TAGRDY_Pos _U_(16) /**< (AES_ISR) GCM Tag Ready Position */
|
||||
#define AES_ISR_TAGRDY_Msk (_U_(0x1) << AES_ISR_TAGRDY_Pos) /**< (AES_ISR) GCM Tag Ready Mask */
|
||||
#define AES_ISR_TAGRDY(value) (AES_ISR_TAGRDY_Msk & ((value) << AES_ISR_TAGRDY_Pos))
|
||||
#define AES_ISR_Msk _U_(0x0001F101) /**< (AES_ISR) Register Mask */
|
||||
|
||||
|
||||
/* -------- AES_KEYWR : (AES Offset: 0x20) ( /W 32) Key Word Register 0 -------- */
|
||||
#define AES_KEYWR_KEYW_Pos _U_(0) /**< (AES_KEYWR) Key Word Position */
|
||||
#define AES_KEYWR_KEYW_Msk (_U_(0xFFFFFFFF) << AES_KEYWR_KEYW_Pos) /**< (AES_KEYWR) Key Word Mask */
|
||||
#define AES_KEYWR_KEYW(value) (AES_KEYWR_KEYW_Msk & ((value) << AES_KEYWR_KEYW_Pos))
|
||||
#define AES_KEYWR_Msk _U_(0xFFFFFFFF) /**< (AES_KEYWR) Register Mask */
|
||||
|
||||
|
||||
/* -------- AES_IDATAR : (AES Offset: 0x40) ( /W 32) Input Data Register 0 -------- */
|
||||
#define AES_IDATAR_IDATA_Pos _U_(0) /**< (AES_IDATAR) Input Data Word Position */
|
||||
#define AES_IDATAR_IDATA_Msk (_U_(0xFFFFFFFF) << AES_IDATAR_IDATA_Pos) /**< (AES_IDATAR) Input Data Word Mask */
|
||||
#define AES_IDATAR_IDATA(value) (AES_IDATAR_IDATA_Msk & ((value) << AES_IDATAR_IDATA_Pos))
|
||||
#define AES_IDATAR_Msk _U_(0xFFFFFFFF) /**< (AES_IDATAR) Register Mask */
|
||||
|
||||
|
||||
/* -------- AES_ODATAR : (AES Offset: 0x50) ( R/ 32) Output Data Register 0 -------- */
|
||||
#define AES_ODATAR_ODATA_Pos _U_(0) /**< (AES_ODATAR) Output Data Position */
|
||||
#define AES_ODATAR_ODATA_Msk (_U_(0xFFFFFFFF) << AES_ODATAR_ODATA_Pos) /**< (AES_ODATAR) Output Data Mask */
|
||||
#define AES_ODATAR_ODATA(value) (AES_ODATAR_ODATA_Msk & ((value) << AES_ODATAR_ODATA_Pos))
|
||||
#define AES_ODATAR_Msk _U_(0xFFFFFFFF) /**< (AES_ODATAR) Register Mask */
|
||||
|
||||
|
||||
/* -------- AES_IVR : (AES Offset: 0x60) ( /W 32) Initialization Vector Register 0 -------- */
|
||||
#define AES_IVR_IV_Pos _U_(0) /**< (AES_IVR) Initialization Vector Position */
|
||||
#define AES_IVR_IV_Msk (_U_(0xFFFFFFFF) << AES_IVR_IV_Pos) /**< (AES_IVR) Initialization Vector Mask */
|
||||
#define AES_IVR_IV(value) (AES_IVR_IV_Msk & ((value) << AES_IVR_IV_Pos))
|
||||
#define AES_IVR_Msk _U_(0xFFFFFFFF) /**< (AES_IVR) Register Mask */
|
||||
|
||||
|
||||
/* -------- AES_AADLENR : (AES Offset: 0x70) (R/W 32) Additional Authenticated Data Length Register -------- */
|
||||
#define AES_AADLENR_AADLEN_Pos _U_(0) /**< (AES_AADLENR) Additional Authenticated Data Length Position */
|
||||
#define AES_AADLENR_AADLEN_Msk (_U_(0xFFFFFFFF) << AES_AADLENR_AADLEN_Pos) /**< (AES_AADLENR) Additional Authenticated Data Length Mask */
|
||||
#define AES_AADLENR_AADLEN(value) (AES_AADLENR_AADLEN_Msk & ((value) << AES_AADLENR_AADLEN_Pos))
|
||||
#define AES_AADLENR_Msk _U_(0xFFFFFFFF) /**< (AES_AADLENR) Register Mask */
|
||||
|
||||
|
||||
/* -------- AES_CLENR : (AES Offset: 0x74) (R/W 32) Plaintext/Ciphertext Length Register -------- */
|
||||
#define AES_CLENR_CLEN_Pos _U_(0) /**< (AES_CLENR) Plaintext/Ciphertext Length Position */
|
||||
#define AES_CLENR_CLEN_Msk (_U_(0xFFFFFFFF) << AES_CLENR_CLEN_Pos) /**< (AES_CLENR) Plaintext/Ciphertext Length Mask */
|
||||
#define AES_CLENR_CLEN(value) (AES_CLENR_CLEN_Msk & ((value) << AES_CLENR_CLEN_Pos))
|
||||
#define AES_CLENR_Msk _U_(0xFFFFFFFF) /**< (AES_CLENR) Register Mask */
|
||||
|
||||
|
||||
/* -------- AES_GHASHR : (AES Offset: 0x78) (R/W 32) GCM Intermediate Hash Word Register 0 -------- */
|
||||
#define AES_GHASHR_GHASH_Pos _U_(0) /**< (AES_GHASHR) Intermediate GCM Hash Word x Position */
|
||||
#define AES_GHASHR_GHASH_Msk (_U_(0xFFFFFFFF) << AES_GHASHR_GHASH_Pos) /**< (AES_GHASHR) Intermediate GCM Hash Word x Mask */
|
||||
#define AES_GHASHR_GHASH(value) (AES_GHASHR_GHASH_Msk & ((value) << AES_GHASHR_GHASH_Pos))
|
||||
#define AES_GHASHR_Msk _U_(0xFFFFFFFF) /**< (AES_GHASHR) Register Mask */
|
||||
|
||||
|
||||
/* -------- AES_TAGR : (AES Offset: 0x88) ( R/ 32) GCM Authentication Tag Word Register 0 -------- */
|
||||
#define AES_TAGR_TAG_Pos _U_(0) /**< (AES_TAGR) GCM Authentication Tag x Position */
|
||||
#define AES_TAGR_TAG_Msk (_U_(0xFFFFFFFF) << AES_TAGR_TAG_Pos) /**< (AES_TAGR) GCM Authentication Tag x Mask */
|
||||
#define AES_TAGR_TAG(value) (AES_TAGR_TAG_Msk & ((value) << AES_TAGR_TAG_Pos))
|
||||
#define AES_TAGR_Msk _U_(0xFFFFFFFF) /**< (AES_TAGR) Register Mask */
|
||||
|
||||
|
||||
/* -------- AES_CTRR : (AES Offset: 0x98) ( R/ 32) GCM Encryption Counter Value Register -------- */
|
||||
#define AES_CTRR_CTR_Pos _U_(0) /**< (AES_CTRR) GCM Encryption Counter Position */
|
||||
#define AES_CTRR_CTR_Msk (_U_(0xFFFFFFFF) << AES_CTRR_CTR_Pos) /**< (AES_CTRR) GCM Encryption Counter Mask */
|
||||
#define AES_CTRR_CTR(value) (AES_CTRR_CTR_Msk & ((value) << AES_CTRR_CTR_Pos))
|
||||
#define AES_CTRR_Msk _U_(0xFFFFFFFF) /**< (AES_CTRR) Register Mask */
|
||||
|
||||
|
||||
/* -------- AES_GCMHR : (AES Offset: 0x9C) (R/W 32) GCM H Word Register 0 -------- */
|
||||
#define AES_GCMHR_H_Pos _U_(0) /**< (AES_GCMHR) GCM H Word x Position */
|
||||
#define AES_GCMHR_H_Msk (_U_(0xFFFFFFFF) << AES_GCMHR_H_Pos) /**< (AES_GCMHR) GCM H Word x Mask */
|
||||
#define AES_GCMHR_H(value) (AES_GCMHR_H_Msk & ((value) << AES_GCMHR_H_Pos))
|
||||
#define AES_GCMHR_Msk _U_(0xFFFFFFFF) /**< (AES_GCMHR) Register Mask */
|
||||
|
||||
|
||||
/** \brief AES register offsets definitions */
|
||||
#define AES_CR_REG_OFST (0x00) /**< (AES_CR) Control Register Offset */
|
||||
#define AES_MR_REG_OFST (0x04) /**< (AES_MR) Mode Register Offset */
|
||||
#define AES_IER_REG_OFST (0x10) /**< (AES_IER) Interrupt Enable Register Offset */
|
||||
#define AES_IDR_REG_OFST (0x14) /**< (AES_IDR) Interrupt Disable Register Offset */
|
||||
#define AES_IMR_REG_OFST (0x18) /**< (AES_IMR) Interrupt Mask Register Offset */
|
||||
#define AES_ISR_REG_OFST (0x1C) /**< (AES_ISR) Interrupt Status Register Offset */
|
||||
#define AES_KEYWR_REG_OFST (0x20) /**< (AES_KEYWR) Key Word Register 0 Offset */
|
||||
#define AES_IDATAR_REG_OFST (0x40) /**< (AES_IDATAR) Input Data Register 0 Offset */
|
||||
#define AES_ODATAR_REG_OFST (0x50) /**< (AES_ODATAR) Output Data Register 0 Offset */
|
||||
#define AES_IVR_REG_OFST (0x60) /**< (AES_IVR) Initialization Vector Register 0 Offset */
|
||||
#define AES_AADLENR_REG_OFST (0x70) /**< (AES_AADLENR) Additional Authenticated Data Length Register Offset */
|
||||
#define AES_CLENR_REG_OFST (0x74) /**< (AES_CLENR) Plaintext/Ciphertext Length Register Offset */
|
||||
#define AES_GHASHR_REG_OFST (0x78) /**< (AES_GHASHR) GCM Intermediate Hash Word Register 0 Offset */
|
||||
#define AES_TAGR_REG_OFST (0x88) /**< (AES_TAGR) GCM Authentication Tag Word Register 0 Offset */
|
||||
#define AES_CTRR_REG_OFST (0x98) /**< (AES_CTRR) GCM Encryption Counter Value Register Offset */
|
||||
#define AES_GCMHR_REG_OFST (0x9C) /**< (AES_GCMHR) GCM H Word Register 0 Offset */
|
||||
|
||||
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
/** \brief AES register API structure */
|
||||
typedef struct
|
||||
{
|
||||
__O uint32_t AES_CR; /**< Offset: 0x00 ( /W 32) Control Register */
|
||||
__IO uint32_t AES_MR; /**< Offset: 0x04 (R/W 32) Mode Register */
|
||||
__I uint8_t Reserved1[0x08];
|
||||
__O uint32_t AES_IER; /**< Offset: 0x10 ( /W 32) Interrupt Enable Register */
|
||||
__O uint32_t AES_IDR; /**< Offset: 0x14 ( /W 32) Interrupt Disable Register */
|
||||
__I uint32_t AES_IMR; /**< Offset: 0x18 (R/ 32) Interrupt Mask Register */
|
||||
__I uint32_t AES_ISR; /**< Offset: 0x1C (R/ 32) Interrupt Status Register */
|
||||
__O uint32_t AES_KEYWR[8]; /**< Offset: 0x20 ( /W 32) Key Word Register 0 */
|
||||
__O uint32_t AES_IDATAR[4]; /**< Offset: 0x40 ( /W 32) Input Data Register 0 */
|
||||
__I uint32_t AES_ODATAR[4]; /**< Offset: 0x50 (R/ 32) Output Data Register 0 */
|
||||
__O uint32_t AES_IVR[4]; /**< Offset: 0x60 ( /W 32) Initialization Vector Register 0 */
|
||||
__IO uint32_t AES_AADLENR; /**< Offset: 0x70 (R/W 32) Additional Authenticated Data Length Register */
|
||||
__IO uint32_t AES_CLENR; /**< Offset: 0x74 (R/W 32) Plaintext/Ciphertext Length Register */
|
||||
__IO uint32_t AES_GHASHR[4]; /**< Offset: 0x78 (R/W 32) GCM Intermediate Hash Word Register 0 */
|
||||
__I uint32_t AES_TAGR[4]; /**< Offset: 0x88 (R/ 32) GCM Authentication Tag Word Register 0 */
|
||||
__I uint32_t AES_CTRR; /**< Offset: 0x98 (R/ 32) GCM Encryption Counter Value Register */
|
||||
__IO uint32_t AES_GCMHR[4]; /**< Offset: 0x9C (R/W 32) GCM H Word Register 0 */
|
||||
} aes_registers_t;
|
||||
|
||||
|
||||
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
#endif /* _SAME70_AES_COMPONENT_H_ */
|
||||
@ -0,0 +1,998 @@
|
||||
/**
|
||||
* \brief Component description for AFEC
|
||||
*
|
||||
* Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries.
|
||||
*
|
||||
* Subject to your compliance with these terms, you may use Microchip software and any derivatives
|
||||
* exclusively with Microchip products. It is your responsibility to comply with third party license
|
||||
* terms applicable to your use of third party software (including open source software) that may
|
||||
* accompany Microchip software.
|
||||
*
|
||||
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY,
|
||||
* APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND
|
||||
* FITNESS FOR A PARTICULAR PURPOSE.
|
||||
*
|
||||
* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
|
||||
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF
|
||||
* MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
|
||||
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT
|
||||
* EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
|
||||
*
|
||||
*/
|
||||
|
||||
/* file generated from device description version 2017-08-25T14:00:00Z */
|
||||
#ifndef _SAME70_AFEC_COMPONENT_H_
|
||||
#define _SAME70_AFEC_COMPONENT_H_
|
||||
|
||||
/* ************************************************************************** */
|
||||
/* SOFTWARE API DEFINITION FOR AFEC */
|
||||
/* ************************************************************************** */
|
||||
|
||||
/* -------- AFEC_CR : (AFEC Offset: 0x00) ( /W 32) AFEC Control Register -------- */
|
||||
#define AFEC_CR_SWRST_Pos _U_(0) /**< (AFEC_CR) Software Reset Position */
|
||||
#define AFEC_CR_SWRST_Msk (_U_(0x1) << AFEC_CR_SWRST_Pos) /**< (AFEC_CR) Software Reset Mask */
|
||||
#define AFEC_CR_SWRST(value) (AFEC_CR_SWRST_Msk & ((value) << AFEC_CR_SWRST_Pos))
|
||||
#define AFEC_CR_START_Pos _U_(1) /**< (AFEC_CR) Start Conversion Position */
|
||||
#define AFEC_CR_START_Msk (_U_(0x1) << AFEC_CR_START_Pos) /**< (AFEC_CR) Start Conversion Mask */
|
||||
#define AFEC_CR_START(value) (AFEC_CR_START_Msk & ((value) << AFEC_CR_START_Pos))
|
||||
#define AFEC_CR_Msk _U_(0x00000003) /**< (AFEC_CR) Register Mask */
|
||||
|
||||
|
||||
/* -------- AFEC_MR : (AFEC Offset: 0x04) (R/W 32) AFEC Mode Register -------- */
|
||||
#define AFEC_MR_TRGEN_Pos _U_(0) /**< (AFEC_MR) Trigger Enable Position */
|
||||
#define AFEC_MR_TRGEN_Msk (_U_(0x1) << AFEC_MR_TRGEN_Pos) /**< (AFEC_MR) Trigger Enable Mask */
|
||||
#define AFEC_MR_TRGEN(value) (AFEC_MR_TRGEN_Msk & ((value) << AFEC_MR_TRGEN_Pos))
|
||||
#define AFEC_MR_TRGEN_DIS_Val _U_(0x0) /**< (AFEC_MR) Hardware triggers are disabled. Starting a conversion is only possible by software. */
|
||||
#define AFEC_MR_TRGEN_EN_Val _U_(0x1) /**< (AFEC_MR) Hardware trigger selected by TRGSEL field is enabled. */
|
||||
#define AFEC_MR_TRGEN_DIS (AFEC_MR_TRGEN_DIS_Val << AFEC_MR_TRGEN_Pos) /**< (AFEC_MR) Hardware triggers are disabled. Starting a conversion is only possible by software. Position */
|
||||
#define AFEC_MR_TRGEN_EN (AFEC_MR_TRGEN_EN_Val << AFEC_MR_TRGEN_Pos) /**< (AFEC_MR) Hardware trigger selected by TRGSEL field is enabled. Position */
|
||||
#define AFEC_MR_TRGSEL_Pos _U_(1) /**< (AFEC_MR) Trigger Selection Position */
|
||||
#define AFEC_MR_TRGSEL_Msk (_U_(0x7) << AFEC_MR_TRGSEL_Pos) /**< (AFEC_MR) Trigger Selection Mask */
|
||||
#define AFEC_MR_TRGSEL(value) (AFEC_MR_TRGSEL_Msk & ((value) << AFEC_MR_TRGSEL_Pos))
|
||||
#define AFEC_MR_TRGSEL_AFEC_TRIG0_Val _U_(0x0) /**< (AFEC_MR) AFE0_ADTRG for AFEC0 / AFE1_ADTRG for AFEC1 */
|
||||
#define AFEC_MR_TRGSEL_AFEC_TRIG1_Val _U_(0x1) /**< (AFEC_MR) TIOA Output of the Timer Counter Channel 0 for AFEC0/TIOA Output of the Timer Counter Channel 3 for AFEC1 */
|
||||
#define AFEC_MR_TRGSEL_AFEC_TRIG2_Val _U_(0x2) /**< (AFEC_MR) TIOA Output of the Timer Counter Channel 1 for AFEC0/TIOA Output of the Timer Counter Channel 4 for AFEC1 */
|
||||
#define AFEC_MR_TRGSEL_AFEC_TRIG3_Val _U_(0x3) /**< (AFEC_MR) TIOA Output of the Timer Counter Channel 2 for AFEC0/TIOA Output of the Timer Counter Channel 5 for AFEC1 */
|
||||
#define AFEC_MR_TRGSEL_AFEC_TRIG4_Val _U_(0x4) /**< (AFEC_MR) PWM0 event line 0 for AFEC0 / PWM1 event line 0 for AFEC1 */
|
||||
#define AFEC_MR_TRGSEL_AFEC_TRIG5_Val _U_(0x5) /**< (AFEC_MR) PWM0 event line 1 for AFEC0 / PWM1 event line 1 for AFEC1 */
|
||||
#define AFEC_MR_TRGSEL_AFEC_TRIG6_Val _U_(0x6) /**< (AFEC_MR) Analog Comparator */
|
||||
#define AFEC_MR_TRGSEL_AFEC_TRIG0 (AFEC_MR_TRGSEL_AFEC_TRIG0_Val << AFEC_MR_TRGSEL_Pos) /**< (AFEC_MR) AFE0_ADTRG for AFEC0 / AFE1_ADTRG for AFEC1 Position */
|
||||
#define AFEC_MR_TRGSEL_AFEC_TRIG1 (AFEC_MR_TRGSEL_AFEC_TRIG1_Val << AFEC_MR_TRGSEL_Pos) /**< (AFEC_MR) TIOA Output of the Timer Counter Channel 0 for AFEC0/TIOA Output of the Timer Counter Channel 3 for AFEC1 Position */
|
||||
#define AFEC_MR_TRGSEL_AFEC_TRIG2 (AFEC_MR_TRGSEL_AFEC_TRIG2_Val << AFEC_MR_TRGSEL_Pos) /**< (AFEC_MR) TIOA Output of the Timer Counter Channel 1 for AFEC0/TIOA Output of the Timer Counter Channel 4 for AFEC1 Position */
|
||||
#define AFEC_MR_TRGSEL_AFEC_TRIG3 (AFEC_MR_TRGSEL_AFEC_TRIG3_Val << AFEC_MR_TRGSEL_Pos) /**< (AFEC_MR) TIOA Output of the Timer Counter Channel 2 for AFEC0/TIOA Output of the Timer Counter Channel 5 for AFEC1 Position */
|
||||
#define AFEC_MR_TRGSEL_AFEC_TRIG4 (AFEC_MR_TRGSEL_AFEC_TRIG4_Val << AFEC_MR_TRGSEL_Pos) /**< (AFEC_MR) PWM0 event line 0 for AFEC0 / PWM1 event line 0 for AFEC1 Position */
|
||||
#define AFEC_MR_TRGSEL_AFEC_TRIG5 (AFEC_MR_TRGSEL_AFEC_TRIG5_Val << AFEC_MR_TRGSEL_Pos) /**< (AFEC_MR) PWM0 event line 1 for AFEC0 / PWM1 event line 1 for AFEC1 Position */
|
||||
#define AFEC_MR_TRGSEL_AFEC_TRIG6 (AFEC_MR_TRGSEL_AFEC_TRIG6_Val << AFEC_MR_TRGSEL_Pos) /**< (AFEC_MR) Analog Comparator Position */
|
||||
#define AFEC_MR_SLEEP_Pos _U_(5) /**< (AFEC_MR) Sleep Mode Position */
|
||||
#define AFEC_MR_SLEEP_Msk (_U_(0x1) << AFEC_MR_SLEEP_Pos) /**< (AFEC_MR) Sleep Mode Mask */
|
||||
#define AFEC_MR_SLEEP(value) (AFEC_MR_SLEEP_Msk & ((value) << AFEC_MR_SLEEP_Pos))
|
||||
#define AFEC_MR_SLEEP_NORMAL_Val _U_(0x0) /**< (AFEC_MR) Normal mode: The AFE and reference voltage circuitry are kept ON between conversions. */
|
||||
#define AFEC_MR_SLEEP_SLEEP_Val _U_(0x1) /**< (AFEC_MR) Sleep mode: The AFE and reference voltage circuitry are OFF between conversions. */
|
||||
#define AFEC_MR_SLEEP_NORMAL (AFEC_MR_SLEEP_NORMAL_Val << AFEC_MR_SLEEP_Pos) /**< (AFEC_MR) Normal mode: The AFE and reference voltage circuitry are kept ON between conversions. Position */
|
||||
#define AFEC_MR_SLEEP_SLEEP (AFEC_MR_SLEEP_SLEEP_Val << AFEC_MR_SLEEP_Pos) /**< (AFEC_MR) Sleep mode: The AFE and reference voltage circuitry are OFF between conversions. Position */
|
||||
#define AFEC_MR_FWUP_Pos _U_(6) /**< (AFEC_MR) Fast Wake-up Position */
|
||||
#define AFEC_MR_FWUP_Msk (_U_(0x1) << AFEC_MR_FWUP_Pos) /**< (AFEC_MR) Fast Wake-up Mask */
|
||||
#define AFEC_MR_FWUP(value) (AFEC_MR_FWUP_Msk & ((value) << AFEC_MR_FWUP_Pos))
|
||||
#define AFEC_MR_FWUP_OFF_Val _U_(0x0) /**< (AFEC_MR) Normal Sleep mode: The sleep mode is defined by the SLEEP bit. */
|
||||
#define AFEC_MR_FWUP_ON_Val _U_(0x1) /**< (AFEC_MR) Fast wake-up Sleep mode: The voltage reference is ON between conversions and AFE is OFF. */
|
||||
#define AFEC_MR_FWUP_OFF (AFEC_MR_FWUP_OFF_Val << AFEC_MR_FWUP_Pos) /**< (AFEC_MR) Normal Sleep mode: The sleep mode is defined by the SLEEP bit. Position */
|
||||
#define AFEC_MR_FWUP_ON (AFEC_MR_FWUP_ON_Val << AFEC_MR_FWUP_Pos) /**< (AFEC_MR) Fast wake-up Sleep mode: The voltage reference is ON between conversions and AFE is OFF. Position */
|
||||
#define AFEC_MR_FREERUN_Pos _U_(7) /**< (AFEC_MR) Free Run Mode Position */
|
||||
#define AFEC_MR_FREERUN_Msk (_U_(0x1) << AFEC_MR_FREERUN_Pos) /**< (AFEC_MR) Free Run Mode Mask */
|
||||
#define AFEC_MR_FREERUN(value) (AFEC_MR_FREERUN_Msk & ((value) << AFEC_MR_FREERUN_Pos))
|
||||
#define AFEC_MR_FREERUN_OFF_Val _U_(0x0) /**< (AFEC_MR) Normal mode */
|
||||
#define AFEC_MR_FREERUN_ON_Val _U_(0x1) /**< (AFEC_MR) Free Run mode: Never wait for any trigger. */
|
||||
#define AFEC_MR_FREERUN_OFF (AFEC_MR_FREERUN_OFF_Val << AFEC_MR_FREERUN_Pos) /**< (AFEC_MR) Normal mode Position */
|
||||
#define AFEC_MR_FREERUN_ON (AFEC_MR_FREERUN_ON_Val << AFEC_MR_FREERUN_Pos) /**< (AFEC_MR) Free Run mode: Never wait for any trigger. Position */
|
||||
#define AFEC_MR_PRESCAL_Pos _U_(8) /**< (AFEC_MR) Prescaler Rate Selection Position */
|
||||
#define AFEC_MR_PRESCAL_Msk (_U_(0xFF) << AFEC_MR_PRESCAL_Pos) /**< (AFEC_MR) Prescaler Rate Selection Mask */
|
||||
#define AFEC_MR_PRESCAL(value) (AFEC_MR_PRESCAL_Msk & ((value) << AFEC_MR_PRESCAL_Pos))
|
||||
#define AFEC_MR_STARTUP_Pos _U_(16) /**< (AFEC_MR) Start-up Time Position */
|
||||
#define AFEC_MR_STARTUP_Msk (_U_(0xF) << AFEC_MR_STARTUP_Pos) /**< (AFEC_MR) Start-up Time Mask */
|
||||
#define AFEC_MR_STARTUP(value) (AFEC_MR_STARTUP_Msk & ((value) << AFEC_MR_STARTUP_Pos))
|
||||
#define AFEC_MR_STARTUP_SUT0_Val _U_(0x0) /**< (AFEC_MR) 0 periods of AFE clock */
|
||||
#define AFEC_MR_STARTUP_SUT8_Val _U_(0x1) /**< (AFEC_MR) 8 periods of AFE clock */
|
||||
#define AFEC_MR_STARTUP_SUT16_Val _U_(0x2) /**< (AFEC_MR) 16 periods of AFE clock */
|
||||
#define AFEC_MR_STARTUP_SUT24_Val _U_(0x3) /**< (AFEC_MR) 24 periods of AFE clock */
|
||||
#define AFEC_MR_STARTUP_SUT64_Val _U_(0x4) /**< (AFEC_MR) 64 periods of AFE clock */
|
||||
#define AFEC_MR_STARTUP_SUT80_Val _U_(0x5) /**< (AFEC_MR) 80 periods of AFE clock */
|
||||
#define AFEC_MR_STARTUP_SUT96_Val _U_(0x6) /**< (AFEC_MR) 96 periods of AFE clock */
|
||||
#define AFEC_MR_STARTUP_SUT112_Val _U_(0x7) /**< (AFEC_MR) 112 periods of AFE clock */
|
||||
#define AFEC_MR_STARTUP_SUT512_Val _U_(0x8) /**< (AFEC_MR) 512 periods of AFE clock */
|
||||
#define AFEC_MR_STARTUP_SUT576_Val _U_(0x9) /**< (AFEC_MR) 576 periods of AFE clock */
|
||||
#define AFEC_MR_STARTUP_SUT640_Val _U_(0xA) /**< (AFEC_MR) 640 periods of AFE clock */
|
||||
#define AFEC_MR_STARTUP_SUT704_Val _U_(0xB) /**< (AFEC_MR) 704 periods of AFE clock */
|
||||
#define AFEC_MR_STARTUP_SUT768_Val _U_(0xC) /**< (AFEC_MR) 768 periods of AFE clock */
|
||||
#define AFEC_MR_STARTUP_SUT832_Val _U_(0xD) /**< (AFEC_MR) 832 periods of AFE clock */
|
||||
#define AFEC_MR_STARTUP_SUT896_Val _U_(0xE) /**< (AFEC_MR) 896 periods of AFE clock */
|
||||
#define AFEC_MR_STARTUP_SUT960_Val _U_(0xF) /**< (AFEC_MR) 960 periods of AFE clock */
|
||||
#define AFEC_MR_STARTUP_SUT0 (AFEC_MR_STARTUP_SUT0_Val << AFEC_MR_STARTUP_Pos) /**< (AFEC_MR) 0 periods of AFE clock Position */
|
||||
#define AFEC_MR_STARTUP_SUT8 (AFEC_MR_STARTUP_SUT8_Val << AFEC_MR_STARTUP_Pos) /**< (AFEC_MR) 8 periods of AFE clock Position */
|
||||
#define AFEC_MR_STARTUP_SUT16 (AFEC_MR_STARTUP_SUT16_Val << AFEC_MR_STARTUP_Pos) /**< (AFEC_MR) 16 periods of AFE clock Position */
|
||||
#define AFEC_MR_STARTUP_SUT24 (AFEC_MR_STARTUP_SUT24_Val << AFEC_MR_STARTUP_Pos) /**< (AFEC_MR) 24 periods of AFE clock Position */
|
||||
#define AFEC_MR_STARTUP_SUT64 (AFEC_MR_STARTUP_SUT64_Val << AFEC_MR_STARTUP_Pos) /**< (AFEC_MR) 64 periods of AFE clock Position */
|
||||
#define AFEC_MR_STARTUP_SUT80 (AFEC_MR_STARTUP_SUT80_Val << AFEC_MR_STARTUP_Pos) /**< (AFEC_MR) 80 periods of AFE clock Position */
|
||||
#define AFEC_MR_STARTUP_SUT96 (AFEC_MR_STARTUP_SUT96_Val << AFEC_MR_STARTUP_Pos) /**< (AFEC_MR) 96 periods of AFE clock Position */
|
||||
#define AFEC_MR_STARTUP_SUT112 (AFEC_MR_STARTUP_SUT112_Val << AFEC_MR_STARTUP_Pos) /**< (AFEC_MR) 112 periods of AFE clock Position */
|
||||
#define AFEC_MR_STARTUP_SUT512 (AFEC_MR_STARTUP_SUT512_Val << AFEC_MR_STARTUP_Pos) /**< (AFEC_MR) 512 periods of AFE clock Position */
|
||||
#define AFEC_MR_STARTUP_SUT576 (AFEC_MR_STARTUP_SUT576_Val << AFEC_MR_STARTUP_Pos) /**< (AFEC_MR) 576 periods of AFE clock Position */
|
||||
#define AFEC_MR_STARTUP_SUT640 (AFEC_MR_STARTUP_SUT640_Val << AFEC_MR_STARTUP_Pos) /**< (AFEC_MR) 640 periods of AFE clock Position */
|
||||
#define AFEC_MR_STARTUP_SUT704 (AFEC_MR_STARTUP_SUT704_Val << AFEC_MR_STARTUP_Pos) /**< (AFEC_MR) 704 periods of AFE clock Position */
|
||||
#define AFEC_MR_STARTUP_SUT768 (AFEC_MR_STARTUP_SUT768_Val << AFEC_MR_STARTUP_Pos) /**< (AFEC_MR) 768 periods of AFE clock Position */
|
||||
#define AFEC_MR_STARTUP_SUT832 (AFEC_MR_STARTUP_SUT832_Val << AFEC_MR_STARTUP_Pos) /**< (AFEC_MR) 832 periods of AFE clock Position */
|
||||
#define AFEC_MR_STARTUP_SUT896 (AFEC_MR_STARTUP_SUT896_Val << AFEC_MR_STARTUP_Pos) /**< (AFEC_MR) 896 periods of AFE clock Position */
|
||||
#define AFEC_MR_STARTUP_SUT960 (AFEC_MR_STARTUP_SUT960_Val << AFEC_MR_STARTUP_Pos) /**< (AFEC_MR) 960 periods of AFE clock Position */
|
||||
#define AFEC_MR_ONE_Pos _U_(23) /**< (AFEC_MR) One Position */
|
||||
#define AFEC_MR_ONE_Msk (_U_(0x1) << AFEC_MR_ONE_Pos) /**< (AFEC_MR) One Mask */
|
||||
#define AFEC_MR_ONE(value) (AFEC_MR_ONE_Msk & ((value) << AFEC_MR_ONE_Pos))
|
||||
#define AFEC_MR_TRACKTIM_Pos _U_(24) /**< (AFEC_MR) Tracking Time Position */
|
||||
#define AFEC_MR_TRACKTIM_Msk (_U_(0xF) << AFEC_MR_TRACKTIM_Pos) /**< (AFEC_MR) Tracking Time Mask */
|
||||
#define AFEC_MR_TRACKTIM(value) (AFEC_MR_TRACKTIM_Msk & ((value) << AFEC_MR_TRACKTIM_Pos))
|
||||
#define AFEC_MR_TRANSFER_Pos _U_(28) /**< (AFEC_MR) Transfer Period Position */
|
||||
#define AFEC_MR_TRANSFER_Msk (_U_(0x3) << AFEC_MR_TRANSFER_Pos) /**< (AFEC_MR) Transfer Period Mask */
|
||||
#define AFEC_MR_TRANSFER(value) (AFEC_MR_TRANSFER_Msk & ((value) << AFEC_MR_TRANSFER_Pos))
|
||||
#define AFEC_MR_USEQ_Pos _U_(31) /**< (AFEC_MR) User Sequence Enable Position */
|
||||
#define AFEC_MR_USEQ_Msk (_U_(0x1) << AFEC_MR_USEQ_Pos) /**< (AFEC_MR) User Sequence Enable Mask */
|
||||
#define AFEC_MR_USEQ(value) (AFEC_MR_USEQ_Msk & ((value) << AFEC_MR_USEQ_Pos))
|
||||
#define AFEC_MR_USEQ_NUM_ORDER_Val _U_(0x0) /**< (AFEC_MR) Normal mode: The controller converts channels in a simple numeric order. */
|
||||
#define AFEC_MR_USEQ_REG_ORDER_Val _U_(0x1) /**< (AFEC_MR) User Sequence mode: The sequence respects what is defined in AFEC_SEQ1R and AFEC_SEQ1R. */
|
||||
#define AFEC_MR_USEQ_NUM_ORDER (AFEC_MR_USEQ_NUM_ORDER_Val << AFEC_MR_USEQ_Pos) /**< (AFEC_MR) Normal mode: The controller converts channels in a simple numeric order. Position */
|
||||
#define AFEC_MR_USEQ_REG_ORDER (AFEC_MR_USEQ_REG_ORDER_Val << AFEC_MR_USEQ_Pos) /**< (AFEC_MR) User Sequence mode: The sequence respects what is defined in AFEC_SEQ1R and AFEC_SEQ1R. Position */
|
||||
#define AFEC_MR_Msk _U_(0xBF8FFFEF) /**< (AFEC_MR) Register Mask */
|
||||
|
||||
|
||||
/* -------- AFEC_EMR : (AFEC Offset: 0x08) (R/W 32) AFEC Extended Mode Register -------- */
|
||||
#define AFEC_EMR_CMPMODE_Pos _U_(0) /**< (AFEC_EMR) Comparison Mode Position */
|
||||
#define AFEC_EMR_CMPMODE_Msk (_U_(0x3) << AFEC_EMR_CMPMODE_Pos) /**< (AFEC_EMR) Comparison Mode Mask */
|
||||
#define AFEC_EMR_CMPMODE(value) (AFEC_EMR_CMPMODE_Msk & ((value) << AFEC_EMR_CMPMODE_Pos))
|
||||
#define AFEC_EMR_CMPMODE_LOW_Val _U_(0x0) /**< (AFEC_EMR) Generates an event when the converted data is lower than the low threshold of the window. */
|
||||
#define AFEC_EMR_CMPMODE_HIGH_Val _U_(0x1) /**< (AFEC_EMR) Generates an event when the converted data is higher than the high threshold of the window. */
|
||||
#define AFEC_EMR_CMPMODE_IN_Val _U_(0x2) /**< (AFEC_EMR) Generates an event when the converted data is in the comparison window. */
|
||||
#define AFEC_EMR_CMPMODE_OUT_Val _U_(0x3) /**< (AFEC_EMR) Generates an event when the converted data is out of the comparison window. */
|
||||
#define AFEC_EMR_CMPMODE_LOW (AFEC_EMR_CMPMODE_LOW_Val << AFEC_EMR_CMPMODE_Pos) /**< (AFEC_EMR) Generates an event when the converted data is lower than the low threshold of the window. Position */
|
||||
#define AFEC_EMR_CMPMODE_HIGH (AFEC_EMR_CMPMODE_HIGH_Val << AFEC_EMR_CMPMODE_Pos) /**< (AFEC_EMR) Generates an event when the converted data is higher than the high threshold of the window. Position */
|
||||
#define AFEC_EMR_CMPMODE_IN (AFEC_EMR_CMPMODE_IN_Val << AFEC_EMR_CMPMODE_Pos) /**< (AFEC_EMR) Generates an event when the converted data is in the comparison window. Position */
|
||||
#define AFEC_EMR_CMPMODE_OUT (AFEC_EMR_CMPMODE_OUT_Val << AFEC_EMR_CMPMODE_Pos) /**< (AFEC_EMR) Generates an event when the converted data is out of the comparison window. Position */
|
||||
#define AFEC_EMR_CMPSEL_Pos _U_(3) /**< (AFEC_EMR) Comparison Selected Channel Position */
|
||||
#define AFEC_EMR_CMPSEL_Msk (_U_(0x1F) << AFEC_EMR_CMPSEL_Pos) /**< (AFEC_EMR) Comparison Selected Channel Mask */
|
||||
#define AFEC_EMR_CMPSEL(value) (AFEC_EMR_CMPSEL_Msk & ((value) << AFEC_EMR_CMPSEL_Pos))
|
||||
#define AFEC_EMR_CMPALL_Pos _U_(9) /**< (AFEC_EMR) Compare All Channels Position */
|
||||
#define AFEC_EMR_CMPALL_Msk (_U_(0x1) << AFEC_EMR_CMPALL_Pos) /**< (AFEC_EMR) Compare All Channels Mask */
|
||||
#define AFEC_EMR_CMPALL(value) (AFEC_EMR_CMPALL_Msk & ((value) << AFEC_EMR_CMPALL_Pos))
|
||||
#define AFEC_EMR_CMPFILTER_Pos _U_(12) /**< (AFEC_EMR) Compare Event Filtering Position */
|
||||
#define AFEC_EMR_CMPFILTER_Msk (_U_(0x3) << AFEC_EMR_CMPFILTER_Pos) /**< (AFEC_EMR) Compare Event Filtering Mask */
|
||||
#define AFEC_EMR_CMPFILTER(value) (AFEC_EMR_CMPFILTER_Msk & ((value) << AFEC_EMR_CMPFILTER_Pos))
|
||||
#define AFEC_EMR_RES_Pos _U_(16) /**< (AFEC_EMR) Resolution Position */
|
||||
#define AFEC_EMR_RES_Msk (_U_(0x7) << AFEC_EMR_RES_Pos) /**< (AFEC_EMR) Resolution Mask */
|
||||
#define AFEC_EMR_RES(value) (AFEC_EMR_RES_Msk & ((value) << AFEC_EMR_RES_Pos))
|
||||
#define AFEC_EMR_RES_NO_AVERAGE_Val _U_(0x0) /**< (AFEC_EMR) 12-bit resolution, AFE sample rate is maximum (no averaging). */
|
||||
#define AFEC_EMR_RES_OSR4_Val _U_(0x2) /**< (AFEC_EMR) 13-bit resolution, AFE sample rate divided by 4 (averaging). */
|
||||
#define AFEC_EMR_RES_OSR16_Val _U_(0x3) /**< (AFEC_EMR) 14-bit resolution, AFE sample rate divided by 16 (averaging). */
|
||||
#define AFEC_EMR_RES_OSR64_Val _U_(0x4) /**< (AFEC_EMR) 15-bit resolution, AFE sample rate divided by 64 (averaging). */
|
||||
#define AFEC_EMR_RES_OSR256_Val _U_(0x5) /**< (AFEC_EMR) 16-bit resolution, AFE sample rate divided by 256 (averaging). */
|
||||
#define AFEC_EMR_RES_NO_AVERAGE (AFEC_EMR_RES_NO_AVERAGE_Val << AFEC_EMR_RES_Pos) /**< (AFEC_EMR) 12-bit resolution, AFE sample rate is maximum (no averaging). Position */
|
||||
#define AFEC_EMR_RES_OSR4 (AFEC_EMR_RES_OSR4_Val << AFEC_EMR_RES_Pos) /**< (AFEC_EMR) 13-bit resolution, AFE sample rate divided by 4 (averaging). Position */
|
||||
#define AFEC_EMR_RES_OSR16 (AFEC_EMR_RES_OSR16_Val << AFEC_EMR_RES_Pos) /**< (AFEC_EMR) 14-bit resolution, AFE sample rate divided by 16 (averaging). Position */
|
||||
#define AFEC_EMR_RES_OSR64 (AFEC_EMR_RES_OSR64_Val << AFEC_EMR_RES_Pos) /**< (AFEC_EMR) 15-bit resolution, AFE sample rate divided by 64 (averaging). Position */
|
||||
#define AFEC_EMR_RES_OSR256 (AFEC_EMR_RES_OSR256_Val << AFEC_EMR_RES_Pos) /**< (AFEC_EMR) 16-bit resolution, AFE sample rate divided by 256 (averaging). Position */
|
||||
#define AFEC_EMR_TAG_Pos _U_(24) /**< (AFEC_EMR) TAG of the AFEC_LDCR Position */
|
||||
#define AFEC_EMR_TAG_Msk (_U_(0x1) << AFEC_EMR_TAG_Pos) /**< (AFEC_EMR) TAG of the AFEC_LDCR Mask */
|
||||
#define AFEC_EMR_TAG(value) (AFEC_EMR_TAG_Msk & ((value) << AFEC_EMR_TAG_Pos))
|
||||
#define AFEC_EMR_STM_Pos _U_(25) /**< (AFEC_EMR) Single Trigger Mode Position */
|
||||
#define AFEC_EMR_STM_Msk (_U_(0x1) << AFEC_EMR_STM_Pos) /**< (AFEC_EMR) Single Trigger Mode Mask */
|
||||
#define AFEC_EMR_STM(value) (AFEC_EMR_STM_Msk & ((value) << AFEC_EMR_STM_Pos))
|
||||
#define AFEC_EMR_SIGNMODE_Pos _U_(28) /**< (AFEC_EMR) Sign Mode Position */
|
||||
#define AFEC_EMR_SIGNMODE_Msk (_U_(0x3) << AFEC_EMR_SIGNMODE_Pos) /**< (AFEC_EMR) Sign Mode Mask */
|
||||
#define AFEC_EMR_SIGNMODE(value) (AFEC_EMR_SIGNMODE_Msk & ((value) << AFEC_EMR_SIGNMODE_Pos))
|
||||
#define AFEC_EMR_SIGNMODE_SE_UNSG_DF_SIGN_Val _U_(0x0) /**< (AFEC_EMR) Single-Ended channels: Unsigned conversions.Differential channels: Signed conversions. */
|
||||
#define AFEC_EMR_SIGNMODE_SE_SIGN_DF_UNSG_Val _U_(0x1) /**< (AFEC_EMR) Single-Ended channels: Signed conversions.Differential channels: Unsigned conversions. */
|
||||
#define AFEC_EMR_SIGNMODE_ALL_UNSIGNED_Val _U_(0x2) /**< (AFEC_EMR) All channels: Unsigned conversions. */
|
||||
#define AFEC_EMR_SIGNMODE_ALL_SIGNED_Val _U_(0x3) /**< (AFEC_EMR) All channels: Signed conversions. */
|
||||
#define AFEC_EMR_SIGNMODE_SE_UNSG_DF_SIGN (AFEC_EMR_SIGNMODE_SE_UNSG_DF_SIGN_Val << AFEC_EMR_SIGNMODE_Pos) /**< (AFEC_EMR) Single-Ended channels: Unsigned conversions.Differential channels: Signed conversions. Position */
|
||||
#define AFEC_EMR_SIGNMODE_SE_SIGN_DF_UNSG (AFEC_EMR_SIGNMODE_SE_SIGN_DF_UNSG_Val << AFEC_EMR_SIGNMODE_Pos) /**< (AFEC_EMR) Single-Ended channels: Signed conversions.Differential channels: Unsigned conversions. Position */
|
||||
#define AFEC_EMR_SIGNMODE_ALL_UNSIGNED (AFEC_EMR_SIGNMODE_ALL_UNSIGNED_Val << AFEC_EMR_SIGNMODE_Pos) /**< (AFEC_EMR) All channels: Unsigned conversions. Position */
|
||||
#define AFEC_EMR_SIGNMODE_ALL_SIGNED (AFEC_EMR_SIGNMODE_ALL_SIGNED_Val << AFEC_EMR_SIGNMODE_Pos) /**< (AFEC_EMR) All channels: Signed conversions. Position */
|
||||
#define AFEC_EMR_Msk _U_(0x330732FB) /**< (AFEC_EMR) Register Mask */
|
||||
|
||||
|
||||
/* -------- AFEC_SEQ1R : (AFEC Offset: 0x0C) (R/W 32) AFEC Channel Sequence 1 Register -------- */
|
||||
#define AFEC_SEQ1R_USCH0_Pos _U_(0) /**< (AFEC_SEQ1R) User Sequence Number 0 Position */
|
||||
#define AFEC_SEQ1R_USCH0_Msk (_U_(0xF) << AFEC_SEQ1R_USCH0_Pos) /**< (AFEC_SEQ1R) User Sequence Number 0 Mask */
|
||||
#define AFEC_SEQ1R_USCH0(value) (AFEC_SEQ1R_USCH0_Msk & ((value) << AFEC_SEQ1R_USCH0_Pos))
|
||||
#define AFEC_SEQ1R_USCH1_Pos _U_(4) /**< (AFEC_SEQ1R) User Sequence Number 1 Position */
|
||||
#define AFEC_SEQ1R_USCH1_Msk (_U_(0xF) << AFEC_SEQ1R_USCH1_Pos) /**< (AFEC_SEQ1R) User Sequence Number 1 Mask */
|
||||
#define AFEC_SEQ1R_USCH1(value) (AFEC_SEQ1R_USCH1_Msk & ((value) << AFEC_SEQ1R_USCH1_Pos))
|
||||
#define AFEC_SEQ1R_USCH2_Pos _U_(8) /**< (AFEC_SEQ1R) User Sequence Number 2 Position */
|
||||
#define AFEC_SEQ1R_USCH2_Msk (_U_(0xF) << AFEC_SEQ1R_USCH2_Pos) /**< (AFEC_SEQ1R) User Sequence Number 2 Mask */
|
||||
#define AFEC_SEQ1R_USCH2(value) (AFEC_SEQ1R_USCH2_Msk & ((value) << AFEC_SEQ1R_USCH2_Pos))
|
||||
#define AFEC_SEQ1R_USCH3_Pos _U_(12) /**< (AFEC_SEQ1R) User Sequence Number 3 Position */
|
||||
#define AFEC_SEQ1R_USCH3_Msk (_U_(0xF) << AFEC_SEQ1R_USCH3_Pos) /**< (AFEC_SEQ1R) User Sequence Number 3 Mask */
|
||||
#define AFEC_SEQ1R_USCH3(value) (AFEC_SEQ1R_USCH3_Msk & ((value) << AFEC_SEQ1R_USCH3_Pos))
|
||||
#define AFEC_SEQ1R_USCH4_Pos _U_(16) /**< (AFEC_SEQ1R) User Sequence Number 4 Position */
|
||||
#define AFEC_SEQ1R_USCH4_Msk (_U_(0xF) << AFEC_SEQ1R_USCH4_Pos) /**< (AFEC_SEQ1R) User Sequence Number 4 Mask */
|
||||
#define AFEC_SEQ1R_USCH4(value) (AFEC_SEQ1R_USCH4_Msk & ((value) << AFEC_SEQ1R_USCH4_Pos))
|
||||
#define AFEC_SEQ1R_USCH5_Pos _U_(20) /**< (AFEC_SEQ1R) User Sequence Number 5 Position */
|
||||
#define AFEC_SEQ1R_USCH5_Msk (_U_(0xF) << AFEC_SEQ1R_USCH5_Pos) /**< (AFEC_SEQ1R) User Sequence Number 5 Mask */
|
||||
#define AFEC_SEQ1R_USCH5(value) (AFEC_SEQ1R_USCH5_Msk & ((value) << AFEC_SEQ1R_USCH5_Pos))
|
||||
#define AFEC_SEQ1R_USCH6_Pos _U_(24) /**< (AFEC_SEQ1R) User Sequence Number 6 Position */
|
||||
#define AFEC_SEQ1R_USCH6_Msk (_U_(0xF) << AFEC_SEQ1R_USCH6_Pos) /**< (AFEC_SEQ1R) User Sequence Number 6 Mask */
|
||||
#define AFEC_SEQ1R_USCH6(value) (AFEC_SEQ1R_USCH6_Msk & ((value) << AFEC_SEQ1R_USCH6_Pos))
|
||||
#define AFEC_SEQ1R_USCH7_Pos _U_(28) /**< (AFEC_SEQ1R) User Sequence Number 7 Position */
|
||||
#define AFEC_SEQ1R_USCH7_Msk (_U_(0xF) << AFEC_SEQ1R_USCH7_Pos) /**< (AFEC_SEQ1R) User Sequence Number 7 Mask */
|
||||
#define AFEC_SEQ1R_USCH7(value) (AFEC_SEQ1R_USCH7_Msk & ((value) << AFEC_SEQ1R_USCH7_Pos))
|
||||
#define AFEC_SEQ1R_Msk _U_(0xFFFFFFFF) /**< (AFEC_SEQ1R) Register Mask */
|
||||
|
||||
|
||||
/* -------- AFEC_SEQ2R : (AFEC Offset: 0x10) (R/W 32) AFEC Channel Sequence 2 Register -------- */
|
||||
#define AFEC_SEQ2R_USCH8_Pos _U_(0) /**< (AFEC_SEQ2R) User Sequence Number 8 Position */
|
||||
#define AFEC_SEQ2R_USCH8_Msk (_U_(0xF) << AFEC_SEQ2R_USCH8_Pos) /**< (AFEC_SEQ2R) User Sequence Number 8 Mask */
|
||||
#define AFEC_SEQ2R_USCH8(value) (AFEC_SEQ2R_USCH8_Msk & ((value) << AFEC_SEQ2R_USCH8_Pos))
|
||||
#define AFEC_SEQ2R_USCH9_Pos _U_(4) /**< (AFEC_SEQ2R) User Sequence Number 9 Position */
|
||||
#define AFEC_SEQ2R_USCH9_Msk (_U_(0xF) << AFEC_SEQ2R_USCH9_Pos) /**< (AFEC_SEQ2R) User Sequence Number 9 Mask */
|
||||
#define AFEC_SEQ2R_USCH9(value) (AFEC_SEQ2R_USCH9_Msk & ((value) << AFEC_SEQ2R_USCH9_Pos))
|
||||
#define AFEC_SEQ2R_USCH10_Pos _U_(8) /**< (AFEC_SEQ2R) User Sequence Number 10 Position */
|
||||
#define AFEC_SEQ2R_USCH10_Msk (_U_(0xF) << AFEC_SEQ2R_USCH10_Pos) /**< (AFEC_SEQ2R) User Sequence Number 10 Mask */
|
||||
#define AFEC_SEQ2R_USCH10(value) (AFEC_SEQ2R_USCH10_Msk & ((value) << AFEC_SEQ2R_USCH10_Pos))
|
||||
#define AFEC_SEQ2R_USCH11_Pos _U_(12) /**< (AFEC_SEQ2R) User Sequence Number 11 Position */
|
||||
#define AFEC_SEQ2R_USCH11_Msk (_U_(0xF) << AFEC_SEQ2R_USCH11_Pos) /**< (AFEC_SEQ2R) User Sequence Number 11 Mask */
|
||||
#define AFEC_SEQ2R_USCH11(value) (AFEC_SEQ2R_USCH11_Msk & ((value) << AFEC_SEQ2R_USCH11_Pos))
|
||||
#define AFEC_SEQ2R_Msk _U_(0x0000FFFF) /**< (AFEC_SEQ2R) Register Mask */
|
||||
|
||||
|
||||
/* -------- AFEC_CHER : (AFEC Offset: 0x14) ( /W 32) AFEC Channel Enable Register -------- */
|
||||
#define AFEC_CHER_CH0_Pos _U_(0) /**< (AFEC_CHER) Channel 0 Enable Position */
|
||||
#define AFEC_CHER_CH0_Msk (_U_(0x1) << AFEC_CHER_CH0_Pos) /**< (AFEC_CHER) Channel 0 Enable Mask */
|
||||
#define AFEC_CHER_CH0(value) (AFEC_CHER_CH0_Msk & ((value) << AFEC_CHER_CH0_Pos))
|
||||
#define AFEC_CHER_CH1_Pos _U_(1) /**< (AFEC_CHER) Channel 1 Enable Position */
|
||||
#define AFEC_CHER_CH1_Msk (_U_(0x1) << AFEC_CHER_CH1_Pos) /**< (AFEC_CHER) Channel 1 Enable Mask */
|
||||
#define AFEC_CHER_CH1(value) (AFEC_CHER_CH1_Msk & ((value) << AFEC_CHER_CH1_Pos))
|
||||
#define AFEC_CHER_CH2_Pos _U_(2) /**< (AFEC_CHER) Channel 2 Enable Position */
|
||||
#define AFEC_CHER_CH2_Msk (_U_(0x1) << AFEC_CHER_CH2_Pos) /**< (AFEC_CHER) Channel 2 Enable Mask */
|
||||
#define AFEC_CHER_CH2(value) (AFEC_CHER_CH2_Msk & ((value) << AFEC_CHER_CH2_Pos))
|
||||
#define AFEC_CHER_CH3_Pos _U_(3) /**< (AFEC_CHER) Channel 3 Enable Position */
|
||||
#define AFEC_CHER_CH3_Msk (_U_(0x1) << AFEC_CHER_CH3_Pos) /**< (AFEC_CHER) Channel 3 Enable Mask */
|
||||
#define AFEC_CHER_CH3(value) (AFEC_CHER_CH3_Msk & ((value) << AFEC_CHER_CH3_Pos))
|
||||
#define AFEC_CHER_CH4_Pos _U_(4) /**< (AFEC_CHER) Channel 4 Enable Position */
|
||||
#define AFEC_CHER_CH4_Msk (_U_(0x1) << AFEC_CHER_CH4_Pos) /**< (AFEC_CHER) Channel 4 Enable Mask */
|
||||
#define AFEC_CHER_CH4(value) (AFEC_CHER_CH4_Msk & ((value) << AFEC_CHER_CH4_Pos))
|
||||
#define AFEC_CHER_CH5_Pos _U_(5) /**< (AFEC_CHER) Channel 5 Enable Position */
|
||||
#define AFEC_CHER_CH5_Msk (_U_(0x1) << AFEC_CHER_CH5_Pos) /**< (AFEC_CHER) Channel 5 Enable Mask */
|
||||
#define AFEC_CHER_CH5(value) (AFEC_CHER_CH5_Msk & ((value) << AFEC_CHER_CH5_Pos))
|
||||
#define AFEC_CHER_CH6_Pos _U_(6) /**< (AFEC_CHER) Channel 6 Enable Position */
|
||||
#define AFEC_CHER_CH6_Msk (_U_(0x1) << AFEC_CHER_CH6_Pos) /**< (AFEC_CHER) Channel 6 Enable Mask */
|
||||
#define AFEC_CHER_CH6(value) (AFEC_CHER_CH6_Msk & ((value) << AFEC_CHER_CH6_Pos))
|
||||
#define AFEC_CHER_CH7_Pos _U_(7) /**< (AFEC_CHER) Channel 7 Enable Position */
|
||||
#define AFEC_CHER_CH7_Msk (_U_(0x1) << AFEC_CHER_CH7_Pos) /**< (AFEC_CHER) Channel 7 Enable Mask */
|
||||
#define AFEC_CHER_CH7(value) (AFEC_CHER_CH7_Msk & ((value) << AFEC_CHER_CH7_Pos))
|
||||
#define AFEC_CHER_CH8_Pos _U_(8) /**< (AFEC_CHER) Channel 8 Enable Position */
|
||||
#define AFEC_CHER_CH8_Msk (_U_(0x1) << AFEC_CHER_CH8_Pos) /**< (AFEC_CHER) Channel 8 Enable Mask */
|
||||
#define AFEC_CHER_CH8(value) (AFEC_CHER_CH8_Msk & ((value) << AFEC_CHER_CH8_Pos))
|
||||
#define AFEC_CHER_CH9_Pos _U_(9) /**< (AFEC_CHER) Channel 9 Enable Position */
|
||||
#define AFEC_CHER_CH9_Msk (_U_(0x1) << AFEC_CHER_CH9_Pos) /**< (AFEC_CHER) Channel 9 Enable Mask */
|
||||
#define AFEC_CHER_CH9(value) (AFEC_CHER_CH9_Msk & ((value) << AFEC_CHER_CH9_Pos))
|
||||
#define AFEC_CHER_CH10_Pos _U_(10) /**< (AFEC_CHER) Channel 10 Enable Position */
|
||||
#define AFEC_CHER_CH10_Msk (_U_(0x1) << AFEC_CHER_CH10_Pos) /**< (AFEC_CHER) Channel 10 Enable Mask */
|
||||
#define AFEC_CHER_CH10(value) (AFEC_CHER_CH10_Msk & ((value) << AFEC_CHER_CH10_Pos))
|
||||
#define AFEC_CHER_CH11_Pos _U_(11) /**< (AFEC_CHER) Channel 11 Enable Position */
|
||||
#define AFEC_CHER_CH11_Msk (_U_(0x1) << AFEC_CHER_CH11_Pos) /**< (AFEC_CHER) Channel 11 Enable Mask */
|
||||
#define AFEC_CHER_CH11(value) (AFEC_CHER_CH11_Msk & ((value) << AFEC_CHER_CH11_Pos))
|
||||
#define AFEC_CHER_Msk _U_(0x00000FFF) /**< (AFEC_CHER) Register Mask */
|
||||
|
||||
#define AFEC_CHER_CH_Pos _U_(0) /**< (AFEC_CHER Position) Channel xx Enable */
|
||||
#define AFEC_CHER_CH_Msk (_U_(0xFFF) << AFEC_CHER_CH_Pos) /**< (AFEC_CHER Mask) CH */
|
||||
#define AFEC_CHER_CH(value) (AFEC_CHER_CH_Msk & ((value) << AFEC_CHER_CH_Pos))
|
||||
|
||||
/* -------- AFEC_CHDR : (AFEC Offset: 0x18) ( /W 32) AFEC Channel Disable Register -------- */
|
||||
#define AFEC_CHDR_CH0_Pos _U_(0) /**< (AFEC_CHDR) Channel 0 Disable Position */
|
||||
#define AFEC_CHDR_CH0_Msk (_U_(0x1) << AFEC_CHDR_CH0_Pos) /**< (AFEC_CHDR) Channel 0 Disable Mask */
|
||||
#define AFEC_CHDR_CH0(value) (AFEC_CHDR_CH0_Msk & ((value) << AFEC_CHDR_CH0_Pos))
|
||||
#define AFEC_CHDR_CH1_Pos _U_(1) /**< (AFEC_CHDR) Channel 1 Disable Position */
|
||||
#define AFEC_CHDR_CH1_Msk (_U_(0x1) << AFEC_CHDR_CH1_Pos) /**< (AFEC_CHDR) Channel 1 Disable Mask */
|
||||
#define AFEC_CHDR_CH1(value) (AFEC_CHDR_CH1_Msk & ((value) << AFEC_CHDR_CH1_Pos))
|
||||
#define AFEC_CHDR_CH2_Pos _U_(2) /**< (AFEC_CHDR) Channel 2 Disable Position */
|
||||
#define AFEC_CHDR_CH2_Msk (_U_(0x1) << AFEC_CHDR_CH2_Pos) /**< (AFEC_CHDR) Channel 2 Disable Mask */
|
||||
#define AFEC_CHDR_CH2(value) (AFEC_CHDR_CH2_Msk & ((value) << AFEC_CHDR_CH2_Pos))
|
||||
#define AFEC_CHDR_CH3_Pos _U_(3) /**< (AFEC_CHDR) Channel 3 Disable Position */
|
||||
#define AFEC_CHDR_CH3_Msk (_U_(0x1) << AFEC_CHDR_CH3_Pos) /**< (AFEC_CHDR) Channel 3 Disable Mask */
|
||||
#define AFEC_CHDR_CH3(value) (AFEC_CHDR_CH3_Msk & ((value) << AFEC_CHDR_CH3_Pos))
|
||||
#define AFEC_CHDR_CH4_Pos _U_(4) /**< (AFEC_CHDR) Channel 4 Disable Position */
|
||||
#define AFEC_CHDR_CH4_Msk (_U_(0x1) << AFEC_CHDR_CH4_Pos) /**< (AFEC_CHDR) Channel 4 Disable Mask */
|
||||
#define AFEC_CHDR_CH4(value) (AFEC_CHDR_CH4_Msk & ((value) << AFEC_CHDR_CH4_Pos))
|
||||
#define AFEC_CHDR_CH5_Pos _U_(5) /**< (AFEC_CHDR) Channel 5 Disable Position */
|
||||
#define AFEC_CHDR_CH5_Msk (_U_(0x1) << AFEC_CHDR_CH5_Pos) /**< (AFEC_CHDR) Channel 5 Disable Mask */
|
||||
#define AFEC_CHDR_CH5(value) (AFEC_CHDR_CH5_Msk & ((value) << AFEC_CHDR_CH5_Pos))
|
||||
#define AFEC_CHDR_CH6_Pos _U_(6) /**< (AFEC_CHDR) Channel 6 Disable Position */
|
||||
#define AFEC_CHDR_CH6_Msk (_U_(0x1) << AFEC_CHDR_CH6_Pos) /**< (AFEC_CHDR) Channel 6 Disable Mask */
|
||||
#define AFEC_CHDR_CH6(value) (AFEC_CHDR_CH6_Msk & ((value) << AFEC_CHDR_CH6_Pos))
|
||||
#define AFEC_CHDR_CH7_Pos _U_(7) /**< (AFEC_CHDR) Channel 7 Disable Position */
|
||||
#define AFEC_CHDR_CH7_Msk (_U_(0x1) << AFEC_CHDR_CH7_Pos) /**< (AFEC_CHDR) Channel 7 Disable Mask */
|
||||
#define AFEC_CHDR_CH7(value) (AFEC_CHDR_CH7_Msk & ((value) << AFEC_CHDR_CH7_Pos))
|
||||
#define AFEC_CHDR_CH8_Pos _U_(8) /**< (AFEC_CHDR) Channel 8 Disable Position */
|
||||
#define AFEC_CHDR_CH8_Msk (_U_(0x1) << AFEC_CHDR_CH8_Pos) /**< (AFEC_CHDR) Channel 8 Disable Mask */
|
||||
#define AFEC_CHDR_CH8(value) (AFEC_CHDR_CH8_Msk & ((value) << AFEC_CHDR_CH8_Pos))
|
||||
#define AFEC_CHDR_CH9_Pos _U_(9) /**< (AFEC_CHDR) Channel 9 Disable Position */
|
||||
#define AFEC_CHDR_CH9_Msk (_U_(0x1) << AFEC_CHDR_CH9_Pos) /**< (AFEC_CHDR) Channel 9 Disable Mask */
|
||||
#define AFEC_CHDR_CH9(value) (AFEC_CHDR_CH9_Msk & ((value) << AFEC_CHDR_CH9_Pos))
|
||||
#define AFEC_CHDR_CH10_Pos _U_(10) /**< (AFEC_CHDR) Channel 10 Disable Position */
|
||||
#define AFEC_CHDR_CH10_Msk (_U_(0x1) << AFEC_CHDR_CH10_Pos) /**< (AFEC_CHDR) Channel 10 Disable Mask */
|
||||
#define AFEC_CHDR_CH10(value) (AFEC_CHDR_CH10_Msk & ((value) << AFEC_CHDR_CH10_Pos))
|
||||
#define AFEC_CHDR_CH11_Pos _U_(11) /**< (AFEC_CHDR) Channel 11 Disable Position */
|
||||
#define AFEC_CHDR_CH11_Msk (_U_(0x1) << AFEC_CHDR_CH11_Pos) /**< (AFEC_CHDR) Channel 11 Disable Mask */
|
||||
#define AFEC_CHDR_CH11(value) (AFEC_CHDR_CH11_Msk & ((value) << AFEC_CHDR_CH11_Pos))
|
||||
#define AFEC_CHDR_Msk _U_(0x00000FFF) /**< (AFEC_CHDR) Register Mask */
|
||||
|
||||
#define AFEC_CHDR_CH_Pos _U_(0) /**< (AFEC_CHDR Position) Channel xx Disable */
|
||||
#define AFEC_CHDR_CH_Msk (_U_(0xFFF) << AFEC_CHDR_CH_Pos) /**< (AFEC_CHDR Mask) CH */
|
||||
#define AFEC_CHDR_CH(value) (AFEC_CHDR_CH_Msk & ((value) << AFEC_CHDR_CH_Pos))
|
||||
|
||||
/* -------- AFEC_CHSR : (AFEC Offset: 0x1C) ( R/ 32) AFEC Channel Status Register -------- */
|
||||
#define AFEC_CHSR_CH0_Pos _U_(0) /**< (AFEC_CHSR) Channel 0 Status Position */
|
||||
#define AFEC_CHSR_CH0_Msk (_U_(0x1) << AFEC_CHSR_CH0_Pos) /**< (AFEC_CHSR) Channel 0 Status Mask */
|
||||
#define AFEC_CHSR_CH0(value) (AFEC_CHSR_CH0_Msk & ((value) << AFEC_CHSR_CH0_Pos))
|
||||
#define AFEC_CHSR_CH1_Pos _U_(1) /**< (AFEC_CHSR) Channel 1 Status Position */
|
||||
#define AFEC_CHSR_CH1_Msk (_U_(0x1) << AFEC_CHSR_CH1_Pos) /**< (AFEC_CHSR) Channel 1 Status Mask */
|
||||
#define AFEC_CHSR_CH1(value) (AFEC_CHSR_CH1_Msk & ((value) << AFEC_CHSR_CH1_Pos))
|
||||
#define AFEC_CHSR_CH2_Pos _U_(2) /**< (AFEC_CHSR) Channel 2 Status Position */
|
||||
#define AFEC_CHSR_CH2_Msk (_U_(0x1) << AFEC_CHSR_CH2_Pos) /**< (AFEC_CHSR) Channel 2 Status Mask */
|
||||
#define AFEC_CHSR_CH2(value) (AFEC_CHSR_CH2_Msk & ((value) << AFEC_CHSR_CH2_Pos))
|
||||
#define AFEC_CHSR_CH3_Pos _U_(3) /**< (AFEC_CHSR) Channel 3 Status Position */
|
||||
#define AFEC_CHSR_CH3_Msk (_U_(0x1) << AFEC_CHSR_CH3_Pos) /**< (AFEC_CHSR) Channel 3 Status Mask */
|
||||
#define AFEC_CHSR_CH3(value) (AFEC_CHSR_CH3_Msk & ((value) << AFEC_CHSR_CH3_Pos))
|
||||
#define AFEC_CHSR_CH4_Pos _U_(4) /**< (AFEC_CHSR) Channel 4 Status Position */
|
||||
#define AFEC_CHSR_CH4_Msk (_U_(0x1) << AFEC_CHSR_CH4_Pos) /**< (AFEC_CHSR) Channel 4 Status Mask */
|
||||
#define AFEC_CHSR_CH4(value) (AFEC_CHSR_CH4_Msk & ((value) << AFEC_CHSR_CH4_Pos))
|
||||
#define AFEC_CHSR_CH5_Pos _U_(5) /**< (AFEC_CHSR) Channel 5 Status Position */
|
||||
#define AFEC_CHSR_CH5_Msk (_U_(0x1) << AFEC_CHSR_CH5_Pos) /**< (AFEC_CHSR) Channel 5 Status Mask */
|
||||
#define AFEC_CHSR_CH5(value) (AFEC_CHSR_CH5_Msk & ((value) << AFEC_CHSR_CH5_Pos))
|
||||
#define AFEC_CHSR_CH6_Pos _U_(6) /**< (AFEC_CHSR) Channel 6 Status Position */
|
||||
#define AFEC_CHSR_CH6_Msk (_U_(0x1) << AFEC_CHSR_CH6_Pos) /**< (AFEC_CHSR) Channel 6 Status Mask */
|
||||
#define AFEC_CHSR_CH6(value) (AFEC_CHSR_CH6_Msk & ((value) << AFEC_CHSR_CH6_Pos))
|
||||
#define AFEC_CHSR_CH7_Pos _U_(7) /**< (AFEC_CHSR) Channel 7 Status Position */
|
||||
#define AFEC_CHSR_CH7_Msk (_U_(0x1) << AFEC_CHSR_CH7_Pos) /**< (AFEC_CHSR) Channel 7 Status Mask */
|
||||
#define AFEC_CHSR_CH7(value) (AFEC_CHSR_CH7_Msk & ((value) << AFEC_CHSR_CH7_Pos))
|
||||
#define AFEC_CHSR_CH8_Pos _U_(8) /**< (AFEC_CHSR) Channel 8 Status Position */
|
||||
#define AFEC_CHSR_CH8_Msk (_U_(0x1) << AFEC_CHSR_CH8_Pos) /**< (AFEC_CHSR) Channel 8 Status Mask */
|
||||
#define AFEC_CHSR_CH8(value) (AFEC_CHSR_CH8_Msk & ((value) << AFEC_CHSR_CH8_Pos))
|
||||
#define AFEC_CHSR_CH9_Pos _U_(9) /**< (AFEC_CHSR) Channel 9 Status Position */
|
||||
#define AFEC_CHSR_CH9_Msk (_U_(0x1) << AFEC_CHSR_CH9_Pos) /**< (AFEC_CHSR) Channel 9 Status Mask */
|
||||
#define AFEC_CHSR_CH9(value) (AFEC_CHSR_CH9_Msk & ((value) << AFEC_CHSR_CH9_Pos))
|
||||
#define AFEC_CHSR_CH10_Pos _U_(10) /**< (AFEC_CHSR) Channel 10 Status Position */
|
||||
#define AFEC_CHSR_CH10_Msk (_U_(0x1) << AFEC_CHSR_CH10_Pos) /**< (AFEC_CHSR) Channel 10 Status Mask */
|
||||
#define AFEC_CHSR_CH10(value) (AFEC_CHSR_CH10_Msk & ((value) << AFEC_CHSR_CH10_Pos))
|
||||
#define AFEC_CHSR_CH11_Pos _U_(11) /**< (AFEC_CHSR) Channel 11 Status Position */
|
||||
#define AFEC_CHSR_CH11_Msk (_U_(0x1) << AFEC_CHSR_CH11_Pos) /**< (AFEC_CHSR) Channel 11 Status Mask */
|
||||
#define AFEC_CHSR_CH11(value) (AFEC_CHSR_CH11_Msk & ((value) << AFEC_CHSR_CH11_Pos))
|
||||
#define AFEC_CHSR_Msk _U_(0x00000FFF) /**< (AFEC_CHSR) Register Mask */
|
||||
|
||||
#define AFEC_CHSR_CH_Pos _U_(0) /**< (AFEC_CHSR Position) Channel xx Status */
|
||||
#define AFEC_CHSR_CH_Msk (_U_(0xFFF) << AFEC_CHSR_CH_Pos) /**< (AFEC_CHSR Mask) CH */
|
||||
#define AFEC_CHSR_CH(value) (AFEC_CHSR_CH_Msk & ((value) << AFEC_CHSR_CH_Pos))
|
||||
|
||||
/* -------- AFEC_LCDR : (AFEC Offset: 0x20) ( R/ 32) AFEC Last Converted Data Register -------- */
|
||||
#define AFEC_LCDR_LDATA_Pos _U_(0) /**< (AFEC_LCDR) Last Data Converted Position */
|
||||
#define AFEC_LCDR_LDATA_Msk (_U_(0xFFFF) << AFEC_LCDR_LDATA_Pos) /**< (AFEC_LCDR) Last Data Converted Mask */
|
||||
#define AFEC_LCDR_LDATA(value) (AFEC_LCDR_LDATA_Msk & ((value) << AFEC_LCDR_LDATA_Pos))
|
||||
#define AFEC_LCDR_CHNB_Pos _U_(24) /**< (AFEC_LCDR) Channel Number Position */
|
||||
#define AFEC_LCDR_CHNB_Msk (_U_(0xF) << AFEC_LCDR_CHNB_Pos) /**< (AFEC_LCDR) Channel Number Mask */
|
||||
#define AFEC_LCDR_CHNB(value) (AFEC_LCDR_CHNB_Msk & ((value) << AFEC_LCDR_CHNB_Pos))
|
||||
#define AFEC_LCDR_Msk _U_(0x0F00FFFF) /**< (AFEC_LCDR) Register Mask */
|
||||
|
||||
|
||||
/* -------- AFEC_IER : (AFEC Offset: 0x24) ( /W 32) AFEC Interrupt Enable Register -------- */
|
||||
#define AFEC_IER_EOC0_Pos _U_(0) /**< (AFEC_IER) End of Conversion Interrupt Enable 0 Position */
|
||||
#define AFEC_IER_EOC0_Msk (_U_(0x1) << AFEC_IER_EOC0_Pos) /**< (AFEC_IER) End of Conversion Interrupt Enable 0 Mask */
|
||||
#define AFEC_IER_EOC0(value) (AFEC_IER_EOC0_Msk & ((value) << AFEC_IER_EOC0_Pos))
|
||||
#define AFEC_IER_EOC1_Pos _U_(1) /**< (AFEC_IER) End of Conversion Interrupt Enable 1 Position */
|
||||
#define AFEC_IER_EOC1_Msk (_U_(0x1) << AFEC_IER_EOC1_Pos) /**< (AFEC_IER) End of Conversion Interrupt Enable 1 Mask */
|
||||
#define AFEC_IER_EOC1(value) (AFEC_IER_EOC1_Msk & ((value) << AFEC_IER_EOC1_Pos))
|
||||
#define AFEC_IER_EOC2_Pos _U_(2) /**< (AFEC_IER) End of Conversion Interrupt Enable 2 Position */
|
||||
#define AFEC_IER_EOC2_Msk (_U_(0x1) << AFEC_IER_EOC2_Pos) /**< (AFEC_IER) End of Conversion Interrupt Enable 2 Mask */
|
||||
#define AFEC_IER_EOC2(value) (AFEC_IER_EOC2_Msk & ((value) << AFEC_IER_EOC2_Pos))
|
||||
#define AFEC_IER_EOC3_Pos _U_(3) /**< (AFEC_IER) End of Conversion Interrupt Enable 3 Position */
|
||||
#define AFEC_IER_EOC3_Msk (_U_(0x1) << AFEC_IER_EOC3_Pos) /**< (AFEC_IER) End of Conversion Interrupt Enable 3 Mask */
|
||||
#define AFEC_IER_EOC3(value) (AFEC_IER_EOC3_Msk & ((value) << AFEC_IER_EOC3_Pos))
|
||||
#define AFEC_IER_EOC4_Pos _U_(4) /**< (AFEC_IER) End of Conversion Interrupt Enable 4 Position */
|
||||
#define AFEC_IER_EOC4_Msk (_U_(0x1) << AFEC_IER_EOC4_Pos) /**< (AFEC_IER) End of Conversion Interrupt Enable 4 Mask */
|
||||
#define AFEC_IER_EOC4(value) (AFEC_IER_EOC4_Msk & ((value) << AFEC_IER_EOC4_Pos))
|
||||
#define AFEC_IER_EOC5_Pos _U_(5) /**< (AFEC_IER) End of Conversion Interrupt Enable 5 Position */
|
||||
#define AFEC_IER_EOC5_Msk (_U_(0x1) << AFEC_IER_EOC5_Pos) /**< (AFEC_IER) End of Conversion Interrupt Enable 5 Mask */
|
||||
#define AFEC_IER_EOC5(value) (AFEC_IER_EOC5_Msk & ((value) << AFEC_IER_EOC5_Pos))
|
||||
#define AFEC_IER_EOC6_Pos _U_(6) /**< (AFEC_IER) End of Conversion Interrupt Enable 6 Position */
|
||||
#define AFEC_IER_EOC6_Msk (_U_(0x1) << AFEC_IER_EOC6_Pos) /**< (AFEC_IER) End of Conversion Interrupt Enable 6 Mask */
|
||||
#define AFEC_IER_EOC6(value) (AFEC_IER_EOC6_Msk & ((value) << AFEC_IER_EOC6_Pos))
|
||||
#define AFEC_IER_EOC7_Pos _U_(7) /**< (AFEC_IER) End of Conversion Interrupt Enable 7 Position */
|
||||
#define AFEC_IER_EOC7_Msk (_U_(0x1) << AFEC_IER_EOC7_Pos) /**< (AFEC_IER) End of Conversion Interrupt Enable 7 Mask */
|
||||
#define AFEC_IER_EOC7(value) (AFEC_IER_EOC7_Msk & ((value) << AFEC_IER_EOC7_Pos))
|
||||
#define AFEC_IER_EOC8_Pos _U_(8) /**< (AFEC_IER) End of Conversion Interrupt Enable 8 Position */
|
||||
#define AFEC_IER_EOC8_Msk (_U_(0x1) << AFEC_IER_EOC8_Pos) /**< (AFEC_IER) End of Conversion Interrupt Enable 8 Mask */
|
||||
#define AFEC_IER_EOC8(value) (AFEC_IER_EOC8_Msk & ((value) << AFEC_IER_EOC8_Pos))
|
||||
#define AFEC_IER_EOC9_Pos _U_(9) /**< (AFEC_IER) End of Conversion Interrupt Enable 9 Position */
|
||||
#define AFEC_IER_EOC9_Msk (_U_(0x1) << AFEC_IER_EOC9_Pos) /**< (AFEC_IER) End of Conversion Interrupt Enable 9 Mask */
|
||||
#define AFEC_IER_EOC9(value) (AFEC_IER_EOC9_Msk & ((value) << AFEC_IER_EOC9_Pos))
|
||||
#define AFEC_IER_EOC10_Pos _U_(10) /**< (AFEC_IER) End of Conversion Interrupt Enable 10 Position */
|
||||
#define AFEC_IER_EOC10_Msk (_U_(0x1) << AFEC_IER_EOC10_Pos) /**< (AFEC_IER) End of Conversion Interrupt Enable 10 Mask */
|
||||
#define AFEC_IER_EOC10(value) (AFEC_IER_EOC10_Msk & ((value) << AFEC_IER_EOC10_Pos))
|
||||
#define AFEC_IER_EOC11_Pos _U_(11) /**< (AFEC_IER) End of Conversion Interrupt Enable 11 Position */
|
||||
#define AFEC_IER_EOC11_Msk (_U_(0x1) << AFEC_IER_EOC11_Pos) /**< (AFEC_IER) End of Conversion Interrupt Enable 11 Mask */
|
||||
#define AFEC_IER_EOC11(value) (AFEC_IER_EOC11_Msk & ((value) << AFEC_IER_EOC11_Pos))
|
||||
#define AFEC_IER_DRDY_Pos _U_(24) /**< (AFEC_IER) Data Ready Interrupt Enable Position */
|
||||
#define AFEC_IER_DRDY_Msk (_U_(0x1) << AFEC_IER_DRDY_Pos) /**< (AFEC_IER) Data Ready Interrupt Enable Mask */
|
||||
#define AFEC_IER_DRDY(value) (AFEC_IER_DRDY_Msk & ((value) << AFEC_IER_DRDY_Pos))
|
||||
#define AFEC_IER_GOVRE_Pos _U_(25) /**< (AFEC_IER) General Overrun Error Interrupt Enable Position */
|
||||
#define AFEC_IER_GOVRE_Msk (_U_(0x1) << AFEC_IER_GOVRE_Pos) /**< (AFEC_IER) General Overrun Error Interrupt Enable Mask */
|
||||
#define AFEC_IER_GOVRE(value) (AFEC_IER_GOVRE_Msk & ((value) << AFEC_IER_GOVRE_Pos))
|
||||
#define AFEC_IER_COMPE_Pos _U_(26) /**< (AFEC_IER) Comparison Event Interrupt Enable Position */
|
||||
#define AFEC_IER_COMPE_Msk (_U_(0x1) << AFEC_IER_COMPE_Pos) /**< (AFEC_IER) Comparison Event Interrupt Enable Mask */
|
||||
#define AFEC_IER_COMPE(value) (AFEC_IER_COMPE_Msk & ((value) << AFEC_IER_COMPE_Pos))
|
||||
#define AFEC_IER_TEMPCHG_Pos _U_(30) /**< (AFEC_IER) Temperature Change Interrupt Enable Position */
|
||||
#define AFEC_IER_TEMPCHG_Msk (_U_(0x1) << AFEC_IER_TEMPCHG_Pos) /**< (AFEC_IER) Temperature Change Interrupt Enable Mask */
|
||||
#define AFEC_IER_TEMPCHG(value) (AFEC_IER_TEMPCHG_Msk & ((value) << AFEC_IER_TEMPCHG_Pos))
|
||||
#define AFEC_IER_Msk _U_(0x47000FFF) /**< (AFEC_IER) Register Mask */
|
||||
|
||||
#define AFEC_IER_EOC_Pos _U_(0) /**< (AFEC_IER Position) End of Conversion Interrupt Enable x */
|
||||
#define AFEC_IER_EOC_Msk (_U_(0xFFF) << AFEC_IER_EOC_Pos) /**< (AFEC_IER Mask) EOC */
|
||||
#define AFEC_IER_EOC(value) (AFEC_IER_EOC_Msk & ((value) << AFEC_IER_EOC_Pos))
|
||||
|
||||
/* -------- AFEC_IDR : (AFEC Offset: 0x28) ( /W 32) AFEC Interrupt Disable Register -------- */
|
||||
#define AFEC_IDR_EOC0_Pos _U_(0) /**< (AFEC_IDR) End of Conversion Interrupt Disable 0 Position */
|
||||
#define AFEC_IDR_EOC0_Msk (_U_(0x1) << AFEC_IDR_EOC0_Pos) /**< (AFEC_IDR) End of Conversion Interrupt Disable 0 Mask */
|
||||
#define AFEC_IDR_EOC0(value) (AFEC_IDR_EOC0_Msk & ((value) << AFEC_IDR_EOC0_Pos))
|
||||
#define AFEC_IDR_EOC1_Pos _U_(1) /**< (AFEC_IDR) End of Conversion Interrupt Disable 1 Position */
|
||||
#define AFEC_IDR_EOC1_Msk (_U_(0x1) << AFEC_IDR_EOC1_Pos) /**< (AFEC_IDR) End of Conversion Interrupt Disable 1 Mask */
|
||||
#define AFEC_IDR_EOC1(value) (AFEC_IDR_EOC1_Msk & ((value) << AFEC_IDR_EOC1_Pos))
|
||||
#define AFEC_IDR_EOC2_Pos _U_(2) /**< (AFEC_IDR) End of Conversion Interrupt Disable 2 Position */
|
||||
#define AFEC_IDR_EOC2_Msk (_U_(0x1) << AFEC_IDR_EOC2_Pos) /**< (AFEC_IDR) End of Conversion Interrupt Disable 2 Mask */
|
||||
#define AFEC_IDR_EOC2(value) (AFEC_IDR_EOC2_Msk & ((value) << AFEC_IDR_EOC2_Pos))
|
||||
#define AFEC_IDR_EOC3_Pos _U_(3) /**< (AFEC_IDR) End of Conversion Interrupt Disable 3 Position */
|
||||
#define AFEC_IDR_EOC3_Msk (_U_(0x1) << AFEC_IDR_EOC3_Pos) /**< (AFEC_IDR) End of Conversion Interrupt Disable 3 Mask */
|
||||
#define AFEC_IDR_EOC3(value) (AFEC_IDR_EOC3_Msk & ((value) << AFEC_IDR_EOC3_Pos))
|
||||
#define AFEC_IDR_EOC4_Pos _U_(4) /**< (AFEC_IDR) End of Conversion Interrupt Disable 4 Position */
|
||||
#define AFEC_IDR_EOC4_Msk (_U_(0x1) << AFEC_IDR_EOC4_Pos) /**< (AFEC_IDR) End of Conversion Interrupt Disable 4 Mask */
|
||||
#define AFEC_IDR_EOC4(value) (AFEC_IDR_EOC4_Msk & ((value) << AFEC_IDR_EOC4_Pos))
|
||||
#define AFEC_IDR_EOC5_Pos _U_(5) /**< (AFEC_IDR) End of Conversion Interrupt Disable 5 Position */
|
||||
#define AFEC_IDR_EOC5_Msk (_U_(0x1) << AFEC_IDR_EOC5_Pos) /**< (AFEC_IDR) End of Conversion Interrupt Disable 5 Mask */
|
||||
#define AFEC_IDR_EOC5(value) (AFEC_IDR_EOC5_Msk & ((value) << AFEC_IDR_EOC5_Pos))
|
||||
#define AFEC_IDR_EOC6_Pos _U_(6) /**< (AFEC_IDR) End of Conversion Interrupt Disable 6 Position */
|
||||
#define AFEC_IDR_EOC6_Msk (_U_(0x1) << AFEC_IDR_EOC6_Pos) /**< (AFEC_IDR) End of Conversion Interrupt Disable 6 Mask */
|
||||
#define AFEC_IDR_EOC6(value) (AFEC_IDR_EOC6_Msk & ((value) << AFEC_IDR_EOC6_Pos))
|
||||
#define AFEC_IDR_EOC7_Pos _U_(7) /**< (AFEC_IDR) End of Conversion Interrupt Disable 7 Position */
|
||||
#define AFEC_IDR_EOC7_Msk (_U_(0x1) << AFEC_IDR_EOC7_Pos) /**< (AFEC_IDR) End of Conversion Interrupt Disable 7 Mask */
|
||||
#define AFEC_IDR_EOC7(value) (AFEC_IDR_EOC7_Msk & ((value) << AFEC_IDR_EOC7_Pos))
|
||||
#define AFEC_IDR_EOC8_Pos _U_(8) /**< (AFEC_IDR) End of Conversion Interrupt Disable 8 Position */
|
||||
#define AFEC_IDR_EOC8_Msk (_U_(0x1) << AFEC_IDR_EOC8_Pos) /**< (AFEC_IDR) End of Conversion Interrupt Disable 8 Mask */
|
||||
#define AFEC_IDR_EOC8(value) (AFEC_IDR_EOC8_Msk & ((value) << AFEC_IDR_EOC8_Pos))
|
||||
#define AFEC_IDR_EOC9_Pos _U_(9) /**< (AFEC_IDR) End of Conversion Interrupt Disable 9 Position */
|
||||
#define AFEC_IDR_EOC9_Msk (_U_(0x1) << AFEC_IDR_EOC9_Pos) /**< (AFEC_IDR) End of Conversion Interrupt Disable 9 Mask */
|
||||
#define AFEC_IDR_EOC9(value) (AFEC_IDR_EOC9_Msk & ((value) << AFEC_IDR_EOC9_Pos))
|
||||
#define AFEC_IDR_EOC10_Pos _U_(10) /**< (AFEC_IDR) End of Conversion Interrupt Disable 10 Position */
|
||||
#define AFEC_IDR_EOC10_Msk (_U_(0x1) << AFEC_IDR_EOC10_Pos) /**< (AFEC_IDR) End of Conversion Interrupt Disable 10 Mask */
|
||||
#define AFEC_IDR_EOC10(value) (AFEC_IDR_EOC10_Msk & ((value) << AFEC_IDR_EOC10_Pos))
|
||||
#define AFEC_IDR_EOC11_Pos _U_(11) /**< (AFEC_IDR) End of Conversion Interrupt Disable 11 Position */
|
||||
#define AFEC_IDR_EOC11_Msk (_U_(0x1) << AFEC_IDR_EOC11_Pos) /**< (AFEC_IDR) End of Conversion Interrupt Disable 11 Mask */
|
||||
#define AFEC_IDR_EOC11(value) (AFEC_IDR_EOC11_Msk & ((value) << AFEC_IDR_EOC11_Pos))
|
||||
#define AFEC_IDR_DRDY_Pos _U_(24) /**< (AFEC_IDR) Data Ready Interrupt Disable Position */
|
||||
#define AFEC_IDR_DRDY_Msk (_U_(0x1) << AFEC_IDR_DRDY_Pos) /**< (AFEC_IDR) Data Ready Interrupt Disable Mask */
|
||||
#define AFEC_IDR_DRDY(value) (AFEC_IDR_DRDY_Msk & ((value) << AFEC_IDR_DRDY_Pos))
|
||||
#define AFEC_IDR_GOVRE_Pos _U_(25) /**< (AFEC_IDR) General Overrun Error Interrupt Disable Position */
|
||||
#define AFEC_IDR_GOVRE_Msk (_U_(0x1) << AFEC_IDR_GOVRE_Pos) /**< (AFEC_IDR) General Overrun Error Interrupt Disable Mask */
|
||||
#define AFEC_IDR_GOVRE(value) (AFEC_IDR_GOVRE_Msk & ((value) << AFEC_IDR_GOVRE_Pos))
|
||||
#define AFEC_IDR_COMPE_Pos _U_(26) /**< (AFEC_IDR) Comparison Event Interrupt Disable Position */
|
||||
#define AFEC_IDR_COMPE_Msk (_U_(0x1) << AFEC_IDR_COMPE_Pos) /**< (AFEC_IDR) Comparison Event Interrupt Disable Mask */
|
||||
#define AFEC_IDR_COMPE(value) (AFEC_IDR_COMPE_Msk & ((value) << AFEC_IDR_COMPE_Pos))
|
||||
#define AFEC_IDR_TEMPCHG_Pos _U_(30) /**< (AFEC_IDR) Temperature Change Interrupt Disable Position */
|
||||
#define AFEC_IDR_TEMPCHG_Msk (_U_(0x1) << AFEC_IDR_TEMPCHG_Pos) /**< (AFEC_IDR) Temperature Change Interrupt Disable Mask */
|
||||
#define AFEC_IDR_TEMPCHG(value) (AFEC_IDR_TEMPCHG_Msk & ((value) << AFEC_IDR_TEMPCHG_Pos))
|
||||
#define AFEC_IDR_Msk _U_(0x47000FFF) /**< (AFEC_IDR) Register Mask */
|
||||
|
||||
#define AFEC_IDR_EOC_Pos _U_(0) /**< (AFEC_IDR Position) End of Conversion Interrupt Disable x */
|
||||
#define AFEC_IDR_EOC_Msk (_U_(0xFFF) << AFEC_IDR_EOC_Pos) /**< (AFEC_IDR Mask) EOC */
|
||||
#define AFEC_IDR_EOC(value) (AFEC_IDR_EOC_Msk & ((value) << AFEC_IDR_EOC_Pos))
|
||||
|
||||
/* -------- AFEC_IMR : (AFEC Offset: 0x2C) ( R/ 32) AFEC Interrupt Mask Register -------- */
|
||||
#define AFEC_IMR_EOC0_Pos _U_(0) /**< (AFEC_IMR) End of Conversion Interrupt Mask 0 Position */
|
||||
#define AFEC_IMR_EOC0_Msk (_U_(0x1) << AFEC_IMR_EOC0_Pos) /**< (AFEC_IMR) End of Conversion Interrupt Mask 0 Mask */
|
||||
#define AFEC_IMR_EOC0(value) (AFEC_IMR_EOC0_Msk & ((value) << AFEC_IMR_EOC0_Pos))
|
||||
#define AFEC_IMR_EOC1_Pos _U_(1) /**< (AFEC_IMR) End of Conversion Interrupt Mask 1 Position */
|
||||
#define AFEC_IMR_EOC1_Msk (_U_(0x1) << AFEC_IMR_EOC1_Pos) /**< (AFEC_IMR) End of Conversion Interrupt Mask 1 Mask */
|
||||
#define AFEC_IMR_EOC1(value) (AFEC_IMR_EOC1_Msk & ((value) << AFEC_IMR_EOC1_Pos))
|
||||
#define AFEC_IMR_EOC2_Pos _U_(2) /**< (AFEC_IMR) End of Conversion Interrupt Mask 2 Position */
|
||||
#define AFEC_IMR_EOC2_Msk (_U_(0x1) << AFEC_IMR_EOC2_Pos) /**< (AFEC_IMR) End of Conversion Interrupt Mask 2 Mask */
|
||||
#define AFEC_IMR_EOC2(value) (AFEC_IMR_EOC2_Msk & ((value) << AFEC_IMR_EOC2_Pos))
|
||||
#define AFEC_IMR_EOC3_Pos _U_(3) /**< (AFEC_IMR) End of Conversion Interrupt Mask 3 Position */
|
||||
#define AFEC_IMR_EOC3_Msk (_U_(0x1) << AFEC_IMR_EOC3_Pos) /**< (AFEC_IMR) End of Conversion Interrupt Mask 3 Mask */
|
||||
#define AFEC_IMR_EOC3(value) (AFEC_IMR_EOC3_Msk & ((value) << AFEC_IMR_EOC3_Pos))
|
||||
#define AFEC_IMR_EOC4_Pos _U_(4) /**< (AFEC_IMR) End of Conversion Interrupt Mask 4 Position */
|
||||
#define AFEC_IMR_EOC4_Msk (_U_(0x1) << AFEC_IMR_EOC4_Pos) /**< (AFEC_IMR) End of Conversion Interrupt Mask 4 Mask */
|
||||
#define AFEC_IMR_EOC4(value) (AFEC_IMR_EOC4_Msk & ((value) << AFEC_IMR_EOC4_Pos))
|
||||
#define AFEC_IMR_EOC5_Pos _U_(5) /**< (AFEC_IMR) End of Conversion Interrupt Mask 5 Position */
|
||||
#define AFEC_IMR_EOC5_Msk (_U_(0x1) << AFEC_IMR_EOC5_Pos) /**< (AFEC_IMR) End of Conversion Interrupt Mask 5 Mask */
|
||||
#define AFEC_IMR_EOC5(value) (AFEC_IMR_EOC5_Msk & ((value) << AFEC_IMR_EOC5_Pos))
|
||||
#define AFEC_IMR_EOC6_Pos _U_(6) /**< (AFEC_IMR) End of Conversion Interrupt Mask 6 Position */
|
||||
#define AFEC_IMR_EOC6_Msk (_U_(0x1) << AFEC_IMR_EOC6_Pos) /**< (AFEC_IMR) End of Conversion Interrupt Mask 6 Mask */
|
||||
#define AFEC_IMR_EOC6(value) (AFEC_IMR_EOC6_Msk & ((value) << AFEC_IMR_EOC6_Pos))
|
||||
#define AFEC_IMR_EOC7_Pos _U_(7) /**< (AFEC_IMR) End of Conversion Interrupt Mask 7 Position */
|
||||
#define AFEC_IMR_EOC7_Msk (_U_(0x1) << AFEC_IMR_EOC7_Pos) /**< (AFEC_IMR) End of Conversion Interrupt Mask 7 Mask */
|
||||
#define AFEC_IMR_EOC7(value) (AFEC_IMR_EOC7_Msk & ((value) << AFEC_IMR_EOC7_Pos))
|
||||
#define AFEC_IMR_EOC8_Pos _U_(8) /**< (AFEC_IMR) End of Conversion Interrupt Mask 8 Position */
|
||||
#define AFEC_IMR_EOC8_Msk (_U_(0x1) << AFEC_IMR_EOC8_Pos) /**< (AFEC_IMR) End of Conversion Interrupt Mask 8 Mask */
|
||||
#define AFEC_IMR_EOC8(value) (AFEC_IMR_EOC8_Msk & ((value) << AFEC_IMR_EOC8_Pos))
|
||||
#define AFEC_IMR_EOC9_Pos _U_(9) /**< (AFEC_IMR) End of Conversion Interrupt Mask 9 Position */
|
||||
#define AFEC_IMR_EOC9_Msk (_U_(0x1) << AFEC_IMR_EOC9_Pos) /**< (AFEC_IMR) End of Conversion Interrupt Mask 9 Mask */
|
||||
#define AFEC_IMR_EOC9(value) (AFEC_IMR_EOC9_Msk & ((value) << AFEC_IMR_EOC9_Pos))
|
||||
#define AFEC_IMR_EOC10_Pos _U_(10) /**< (AFEC_IMR) End of Conversion Interrupt Mask 10 Position */
|
||||
#define AFEC_IMR_EOC10_Msk (_U_(0x1) << AFEC_IMR_EOC10_Pos) /**< (AFEC_IMR) End of Conversion Interrupt Mask 10 Mask */
|
||||
#define AFEC_IMR_EOC10(value) (AFEC_IMR_EOC10_Msk & ((value) << AFEC_IMR_EOC10_Pos))
|
||||
#define AFEC_IMR_EOC11_Pos _U_(11) /**< (AFEC_IMR) End of Conversion Interrupt Mask 11 Position */
|
||||
#define AFEC_IMR_EOC11_Msk (_U_(0x1) << AFEC_IMR_EOC11_Pos) /**< (AFEC_IMR) End of Conversion Interrupt Mask 11 Mask */
|
||||
#define AFEC_IMR_EOC11(value) (AFEC_IMR_EOC11_Msk & ((value) << AFEC_IMR_EOC11_Pos))
|
||||
#define AFEC_IMR_DRDY_Pos _U_(24) /**< (AFEC_IMR) Data Ready Interrupt Mask Position */
|
||||
#define AFEC_IMR_DRDY_Msk (_U_(0x1) << AFEC_IMR_DRDY_Pos) /**< (AFEC_IMR) Data Ready Interrupt Mask Mask */
|
||||
#define AFEC_IMR_DRDY(value) (AFEC_IMR_DRDY_Msk & ((value) << AFEC_IMR_DRDY_Pos))
|
||||
#define AFEC_IMR_GOVRE_Pos _U_(25) /**< (AFEC_IMR) General Overrun Error Interrupt Mask Position */
|
||||
#define AFEC_IMR_GOVRE_Msk (_U_(0x1) << AFEC_IMR_GOVRE_Pos) /**< (AFEC_IMR) General Overrun Error Interrupt Mask Mask */
|
||||
#define AFEC_IMR_GOVRE(value) (AFEC_IMR_GOVRE_Msk & ((value) << AFEC_IMR_GOVRE_Pos))
|
||||
#define AFEC_IMR_COMPE_Pos _U_(26) /**< (AFEC_IMR) Comparison Event Interrupt Mask Position */
|
||||
#define AFEC_IMR_COMPE_Msk (_U_(0x1) << AFEC_IMR_COMPE_Pos) /**< (AFEC_IMR) Comparison Event Interrupt Mask Mask */
|
||||
#define AFEC_IMR_COMPE(value) (AFEC_IMR_COMPE_Msk & ((value) << AFEC_IMR_COMPE_Pos))
|
||||
#define AFEC_IMR_TEMPCHG_Pos _U_(30) /**< (AFEC_IMR) Temperature Change Interrupt Mask Position */
|
||||
#define AFEC_IMR_TEMPCHG_Msk (_U_(0x1) << AFEC_IMR_TEMPCHG_Pos) /**< (AFEC_IMR) Temperature Change Interrupt Mask Mask */
|
||||
#define AFEC_IMR_TEMPCHG(value) (AFEC_IMR_TEMPCHG_Msk & ((value) << AFEC_IMR_TEMPCHG_Pos))
|
||||
#define AFEC_IMR_Msk _U_(0x47000FFF) /**< (AFEC_IMR) Register Mask */
|
||||
|
||||
#define AFEC_IMR_EOC_Pos _U_(0) /**< (AFEC_IMR Position) End of Conversion Interrupt Mask x */
|
||||
#define AFEC_IMR_EOC_Msk (_U_(0xFFF) << AFEC_IMR_EOC_Pos) /**< (AFEC_IMR Mask) EOC */
|
||||
#define AFEC_IMR_EOC(value) (AFEC_IMR_EOC_Msk & ((value) << AFEC_IMR_EOC_Pos))
|
||||
|
||||
/* -------- AFEC_ISR : (AFEC Offset: 0x30) ( R/ 32) AFEC Interrupt Status Register -------- */
|
||||
#define AFEC_ISR_EOC0_Pos _U_(0) /**< (AFEC_ISR) End of Conversion 0 (cleared by reading AFEC_CDRx) Position */
|
||||
#define AFEC_ISR_EOC0_Msk (_U_(0x1) << AFEC_ISR_EOC0_Pos) /**< (AFEC_ISR) End of Conversion 0 (cleared by reading AFEC_CDRx) Mask */
|
||||
#define AFEC_ISR_EOC0(value) (AFEC_ISR_EOC0_Msk & ((value) << AFEC_ISR_EOC0_Pos))
|
||||
#define AFEC_ISR_EOC1_Pos _U_(1) /**< (AFEC_ISR) End of Conversion 1 (cleared by reading AFEC_CDRx) Position */
|
||||
#define AFEC_ISR_EOC1_Msk (_U_(0x1) << AFEC_ISR_EOC1_Pos) /**< (AFEC_ISR) End of Conversion 1 (cleared by reading AFEC_CDRx) Mask */
|
||||
#define AFEC_ISR_EOC1(value) (AFEC_ISR_EOC1_Msk & ((value) << AFEC_ISR_EOC1_Pos))
|
||||
#define AFEC_ISR_EOC2_Pos _U_(2) /**< (AFEC_ISR) End of Conversion 2 (cleared by reading AFEC_CDRx) Position */
|
||||
#define AFEC_ISR_EOC2_Msk (_U_(0x1) << AFEC_ISR_EOC2_Pos) /**< (AFEC_ISR) End of Conversion 2 (cleared by reading AFEC_CDRx) Mask */
|
||||
#define AFEC_ISR_EOC2(value) (AFEC_ISR_EOC2_Msk & ((value) << AFEC_ISR_EOC2_Pos))
|
||||
#define AFEC_ISR_EOC3_Pos _U_(3) /**< (AFEC_ISR) End of Conversion 3 (cleared by reading AFEC_CDRx) Position */
|
||||
#define AFEC_ISR_EOC3_Msk (_U_(0x1) << AFEC_ISR_EOC3_Pos) /**< (AFEC_ISR) End of Conversion 3 (cleared by reading AFEC_CDRx) Mask */
|
||||
#define AFEC_ISR_EOC3(value) (AFEC_ISR_EOC3_Msk & ((value) << AFEC_ISR_EOC3_Pos))
|
||||
#define AFEC_ISR_EOC4_Pos _U_(4) /**< (AFEC_ISR) End of Conversion 4 (cleared by reading AFEC_CDRx) Position */
|
||||
#define AFEC_ISR_EOC4_Msk (_U_(0x1) << AFEC_ISR_EOC4_Pos) /**< (AFEC_ISR) End of Conversion 4 (cleared by reading AFEC_CDRx) Mask */
|
||||
#define AFEC_ISR_EOC4(value) (AFEC_ISR_EOC4_Msk & ((value) << AFEC_ISR_EOC4_Pos))
|
||||
#define AFEC_ISR_EOC5_Pos _U_(5) /**< (AFEC_ISR) End of Conversion 5 (cleared by reading AFEC_CDRx) Position */
|
||||
#define AFEC_ISR_EOC5_Msk (_U_(0x1) << AFEC_ISR_EOC5_Pos) /**< (AFEC_ISR) End of Conversion 5 (cleared by reading AFEC_CDRx) Mask */
|
||||
#define AFEC_ISR_EOC5(value) (AFEC_ISR_EOC5_Msk & ((value) << AFEC_ISR_EOC5_Pos))
|
||||
#define AFEC_ISR_EOC6_Pos _U_(6) /**< (AFEC_ISR) End of Conversion 6 (cleared by reading AFEC_CDRx) Position */
|
||||
#define AFEC_ISR_EOC6_Msk (_U_(0x1) << AFEC_ISR_EOC6_Pos) /**< (AFEC_ISR) End of Conversion 6 (cleared by reading AFEC_CDRx) Mask */
|
||||
#define AFEC_ISR_EOC6(value) (AFEC_ISR_EOC6_Msk & ((value) << AFEC_ISR_EOC6_Pos))
|
||||
#define AFEC_ISR_EOC7_Pos _U_(7) /**< (AFEC_ISR) End of Conversion 7 (cleared by reading AFEC_CDRx) Position */
|
||||
#define AFEC_ISR_EOC7_Msk (_U_(0x1) << AFEC_ISR_EOC7_Pos) /**< (AFEC_ISR) End of Conversion 7 (cleared by reading AFEC_CDRx) Mask */
|
||||
#define AFEC_ISR_EOC7(value) (AFEC_ISR_EOC7_Msk & ((value) << AFEC_ISR_EOC7_Pos))
|
||||
#define AFEC_ISR_EOC8_Pos _U_(8) /**< (AFEC_ISR) End of Conversion 8 (cleared by reading AFEC_CDRx) Position */
|
||||
#define AFEC_ISR_EOC8_Msk (_U_(0x1) << AFEC_ISR_EOC8_Pos) /**< (AFEC_ISR) End of Conversion 8 (cleared by reading AFEC_CDRx) Mask */
|
||||
#define AFEC_ISR_EOC8(value) (AFEC_ISR_EOC8_Msk & ((value) << AFEC_ISR_EOC8_Pos))
|
||||
#define AFEC_ISR_EOC9_Pos _U_(9) /**< (AFEC_ISR) End of Conversion 9 (cleared by reading AFEC_CDRx) Position */
|
||||
#define AFEC_ISR_EOC9_Msk (_U_(0x1) << AFEC_ISR_EOC9_Pos) /**< (AFEC_ISR) End of Conversion 9 (cleared by reading AFEC_CDRx) Mask */
|
||||
#define AFEC_ISR_EOC9(value) (AFEC_ISR_EOC9_Msk & ((value) << AFEC_ISR_EOC9_Pos))
|
||||
#define AFEC_ISR_EOC10_Pos _U_(10) /**< (AFEC_ISR) End of Conversion 10 (cleared by reading AFEC_CDRx) Position */
|
||||
#define AFEC_ISR_EOC10_Msk (_U_(0x1) << AFEC_ISR_EOC10_Pos) /**< (AFEC_ISR) End of Conversion 10 (cleared by reading AFEC_CDRx) Mask */
|
||||
#define AFEC_ISR_EOC10(value) (AFEC_ISR_EOC10_Msk & ((value) << AFEC_ISR_EOC10_Pos))
|
||||
#define AFEC_ISR_EOC11_Pos _U_(11) /**< (AFEC_ISR) End of Conversion 11 (cleared by reading AFEC_CDRx) Position */
|
||||
#define AFEC_ISR_EOC11_Msk (_U_(0x1) << AFEC_ISR_EOC11_Pos) /**< (AFEC_ISR) End of Conversion 11 (cleared by reading AFEC_CDRx) Mask */
|
||||
#define AFEC_ISR_EOC11(value) (AFEC_ISR_EOC11_Msk & ((value) << AFEC_ISR_EOC11_Pos))
|
||||
#define AFEC_ISR_DRDY_Pos _U_(24) /**< (AFEC_ISR) Data Ready (cleared by reading AFEC_LCDR) Position */
|
||||
#define AFEC_ISR_DRDY_Msk (_U_(0x1) << AFEC_ISR_DRDY_Pos) /**< (AFEC_ISR) Data Ready (cleared by reading AFEC_LCDR) Mask */
|
||||
#define AFEC_ISR_DRDY(value) (AFEC_ISR_DRDY_Msk & ((value) << AFEC_ISR_DRDY_Pos))
|
||||
#define AFEC_ISR_GOVRE_Pos _U_(25) /**< (AFEC_ISR) General Overrun Error (cleared by reading AFEC_ISR) Position */
|
||||
#define AFEC_ISR_GOVRE_Msk (_U_(0x1) << AFEC_ISR_GOVRE_Pos) /**< (AFEC_ISR) General Overrun Error (cleared by reading AFEC_ISR) Mask */
|
||||
#define AFEC_ISR_GOVRE(value) (AFEC_ISR_GOVRE_Msk & ((value) << AFEC_ISR_GOVRE_Pos))
|
||||
#define AFEC_ISR_COMPE_Pos _U_(26) /**< (AFEC_ISR) Comparison Error (cleared by reading AFEC_ISR) Position */
|
||||
#define AFEC_ISR_COMPE_Msk (_U_(0x1) << AFEC_ISR_COMPE_Pos) /**< (AFEC_ISR) Comparison Error (cleared by reading AFEC_ISR) Mask */
|
||||
#define AFEC_ISR_COMPE(value) (AFEC_ISR_COMPE_Msk & ((value) << AFEC_ISR_COMPE_Pos))
|
||||
#define AFEC_ISR_TEMPCHG_Pos _U_(30) /**< (AFEC_ISR) Temperature Change (cleared on read) Position */
|
||||
#define AFEC_ISR_TEMPCHG_Msk (_U_(0x1) << AFEC_ISR_TEMPCHG_Pos) /**< (AFEC_ISR) Temperature Change (cleared on read) Mask */
|
||||
#define AFEC_ISR_TEMPCHG(value) (AFEC_ISR_TEMPCHG_Msk & ((value) << AFEC_ISR_TEMPCHG_Pos))
|
||||
#define AFEC_ISR_Msk _U_(0x47000FFF) /**< (AFEC_ISR) Register Mask */
|
||||
|
||||
#define AFEC_ISR_EOC_Pos _U_(0) /**< (AFEC_ISR Position) End of Conversion x (cleared by reading AFEC_CDRx) */
|
||||
#define AFEC_ISR_EOC_Msk (_U_(0xFFF) << AFEC_ISR_EOC_Pos) /**< (AFEC_ISR Mask) EOC */
|
||||
#define AFEC_ISR_EOC(value) (AFEC_ISR_EOC_Msk & ((value) << AFEC_ISR_EOC_Pos))
|
||||
|
||||
/* -------- AFEC_OVER : (AFEC Offset: 0x4C) ( R/ 32) AFEC Overrun Status Register -------- */
|
||||
#define AFEC_OVER_OVRE0_Pos _U_(0) /**< (AFEC_OVER) Overrun Error 0 Position */
|
||||
#define AFEC_OVER_OVRE0_Msk (_U_(0x1) << AFEC_OVER_OVRE0_Pos) /**< (AFEC_OVER) Overrun Error 0 Mask */
|
||||
#define AFEC_OVER_OVRE0(value) (AFEC_OVER_OVRE0_Msk & ((value) << AFEC_OVER_OVRE0_Pos))
|
||||
#define AFEC_OVER_OVRE1_Pos _U_(1) /**< (AFEC_OVER) Overrun Error 1 Position */
|
||||
#define AFEC_OVER_OVRE1_Msk (_U_(0x1) << AFEC_OVER_OVRE1_Pos) /**< (AFEC_OVER) Overrun Error 1 Mask */
|
||||
#define AFEC_OVER_OVRE1(value) (AFEC_OVER_OVRE1_Msk & ((value) << AFEC_OVER_OVRE1_Pos))
|
||||
#define AFEC_OVER_OVRE2_Pos _U_(2) /**< (AFEC_OVER) Overrun Error 2 Position */
|
||||
#define AFEC_OVER_OVRE2_Msk (_U_(0x1) << AFEC_OVER_OVRE2_Pos) /**< (AFEC_OVER) Overrun Error 2 Mask */
|
||||
#define AFEC_OVER_OVRE2(value) (AFEC_OVER_OVRE2_Msk & ((value) << AFEC_OVER_OVRE2_Pos))
|
||||
#define AFEC_OVER_OVRE3_Pos _U_(3) /**< (AFEC_OVER) Overrun Error 3 Position */
|
||||
#define AFEC_OVER_OVRE3_Msk (_U_(0x1) << AFEC_OVER_OVRE3_Pos) /**< (AFEC_OVER) Overrun Error 3 Mask */
|
||||
#define AFEC_OVER_OVRE3(value) (AFEC_OVER_OVRE3_Msk & ((value) << AFEC_OVER_OVRE3_Pos))
|
||||
#define AFEC_OVER_OVRE4_Pos _U_(4) /**< (AFEC_OVER) Overrun Error 4 Position */
|
||||
#define AFEC_OVER_OVRE4_Msk (_U_(0x1) << AFEC_OVER_OVRE4_Pos) /**< (AFEC_OVER) Overrun Error 4 Mask */
|
||||
#define AFEC_OVER_OVRE4(value) (AFEC_OVER_OVRE4_Msk & ((value) << AFEC_OVER_OVRE4_Pos))
|
||||
#define AFEC_OVER_OVRE5_Pos _U_(5) /**< (AFEC_OVER) Overrun Error 5 Position */
|
||||
#define AFEC_OVER_OVRE5_Msk (_U_(0x1) << AFEC_OVER_OVRE5_Pos) /**< (AFEC_OVER) Overrun Error 5 Mask */
|
||||
#define AFEC_OVER_OVRE5(value) (AFEC_OVER_OVRE5_Msk & ((value) << AFEC_OVER_OVRE5_Pos))
|
||||
#define AFEC_OVER_OVRE6_Pos _U_(6) /**< (AFEC_OVER) Overrun Error 6 Position */
|
||||
#define AFEC_OVER_OVRE6_Msk (_U_(0x1) << AFEC_OVER_OVRE6_Pos) /**< (AFEC_OVER) Overrun Error 6 Mask */
|
||||
#define AFEC_OVER_OVRE6(value) (AFEC_OVER_OVRE6_Msk & ((value) << AFEC_OVER_OVRE6_Pos))
|
||||
#define AFEC_OVER_OVRE7_Pos _U_(7) /**< (AFEC_OVER) Overrun Error 7 Position */
|
||||
#define AFEC_OVER_OVRE7_Msk (_U_(0x1) << AFEC_OVER_OVRE7_Pos) /**< (AFEC_OVER) Overrun Error 7 Mask */
|
||||
#define AFEC_OVER_OVRE7(value) (AFEC_OVER_OVRE7_Msk & ((value) << AFEC_OVER_OVRE7_Pos))
|
||||
#define AFEC_OVER_OVRE8_Pos _U_(8) /**< (AFEC_OVER) Overrun Error 8 Position */
|
||||
#define AFEC_OVER_OVRE8_Msk (_U_(0x1) << AFEC_OVER_OVRE8_Pos) /**< (AFEC_OVER) Overrun Error 8 Mask */
|
||||
#define AFEC_OVER_OVRE8(value) (AFEC_OVER_OVRE8_Msk & ((value) << AFEC_OVER_OVRE8_Pos))
|
||||
#define AFEC_OVER_OVRE9_Pos _U_(9) /**< (AFEC_OVER) Overrun Error 9 Position */
|
||||
#define AFEC_OVER_OVRE9_Msk (_U_(0x1) << AFEC_OVER_OVRE9_Pos) /**< (AFEC_OVER) Overrun Error 9 Mask */
|
||||
#define AFEC_OVER_OVRE9(value) (AFEC_OVER_OVRE9_Msk & ((value) << AFEC_OVER_OVRE9_Pos))
|
||||
#define AFEC_OVER_OVRE10_Pos _U_(10) /**< (AFEC_OVER) Overrun Error 10 Position */
|
||||
#define AFEC_OVER_OVRE10_Msk (_U_(0x1) << AFEC_OVER_OVRE10_Pos) /**< (AFEC_OVER) Overrun Error 10 Mask */
|
||||
#define AFEC_OVER_OVRE10(value) (AFEC_OVER_OVRE10_Msk & ((value) << AFEC_OVER_OVRE10_Pos))
|
||||
#define AFEC_OVER_OVRE11_Pos _U_(11) /**< (AFEC_OVER) Overrun Error 11 Position */
|
||||
#define AFEC_OVER_OVRE11_Msk (_U_(0x1) << AFEC_OVER_OVRE11_Pos) /**< (AFEC_OVER) Overrun Error 11 Mask */
|
||||
#define AFEC_OVER_OVRE11(value) (AFEC_OVER_OVRE11_Msk & ((value) << AFEC_OVER_OVRE11_Pos))
|
||||
#define AFEC_OVER_Msk _U_(0x00000FFF) /**< (AFEC_OVER) Register Mask */
|
||||
|
||||
#define AFEC_OVER_OVRE_Pos _U_(0) /**< (AFEC_OVER Position) Overrun Error xx */
|
||||
#define AFEC_OVER_OVRE_Msk (_U_(0xFFF) << AFEC_OVER_OVRE_Pos) /**< (AFEC_OVER Mask) OVRE */
|
||||
#define AFEC_OVER_OVRE(value) (AFEC_OVER_OVRE_Msk & ((value) << AFEC_OVER_OVRE_Pos))
|
||||
|
||||
/* -------- AFEC_CWR : (AFEC Offset: 0x50) (R/W 32) AFEC Compare Window Register -------- */
|
||||
#define AFEC_CWR_LOWTHRES_Pos _U_(0) /**< (AFEC_CWR) Low Threshold Position */
|
||||
#define AFEC_CWR_LOWTHRES_Msk (_U_(0xFFFF) << AFEC_CWR_LOWTHRES_Pos) /**< (AFEC_CWR) Low Threshold Mask */
|
||||
#define AFEC_CWR_LOWTHRES(value) (AFEC_CWR_LOWTHRES_Msk & ((value) << AFEC_CWR_LOWTHRES_Pos))
|
||||
#define AFEC_CWR_HIGHTHRES_Pos _U_(16) /**< (AFEC_CWR) High Threshold Position */
|
||||
#define AFEC_CWR_HIGHTHRES_Msk (_U_(0xFFFF) << AFEC_CWR_HIGHTHRES_Pos) /**< (AFEC_CWR) High Threshold Mask */
|
||||
#define AFEC_CWR_HIGHTHRES(value) (AFEC_CWR_HIGHTHRES_Msk & ((value) << AFEC_CWR_HIGHTHRES_Pos))
|
||||
#define AFEC_CWR_Msk _U_(0xFFFFFFFF) /**< (AFEC_CWR) Register Mask */
|
||||
|
||||
|
||||
/* -------- AFEC_CGR : (AFEC Offset: 0x54) (R/W 32) AFEC Channel Gain Register -------- */
|
||||
#define AFEC_CGR_GAIN0_Pos _U_(0) /**< (AFEC_CGR) Gain for Channel 0 Position */
|
||||
#define AFEC_CGR_GAIN0_Msk (_U_(0x3) << AFEC_CGR_GAIN0_Pos) /**< (AFEC_CGR) Gain for Channel 0 Mask */
|
||||
#define AFEC_CGR_GAIN0(value) (AFEC_CGR_GAIN0_Msk & ((value) << AFEC_CGR_GAIN0_Pos))
|
||||
#define AFEC_CGR_GAIN1_Pos _U_(2) /**< (AFEC_CGR) Gain for Channel 1 Position */
|
||||
#define AFEC_CGR_GAIN1_Msk (_U_(0x3) << AFEC_CGR_GAIN1_Pos) /**< (AFEC_CGR) Gain for Channel 1 Mask */
|
||||
#define AFEC_CGR_GAIN1(value) (AFEC_CGR_GAIN1_Msk & ((value) << AFEC_CGR_GAIN1_Pos))
|
||||
#define AFEC_CGR_GAIN2_Pos _U_(4) /**< (AFEC_CGR) Gain for Channel 2 Position */
|
||||
#define AFEC_CGR_GAIN2_Msk (_U_(0x3) << AFEC_CGR_GAIN2_Pos) /**< (AFEC_CGR) Gain for Channel 2 Mask */
|
||||
#define AFEC_CGR_GAIN2(value) (AFEC_CGR_GAIN2_Msk & ((value) << AFEC_CGR_GAIN2_Pos))
|
||||
#define AFEC_CGR_GAIN3_Pos _U_(6) /**< (AFEC_CGR) Gain for Channel 3 Position */
|
||||
#define AFEC_CGR_GAIN3_Msk (_U_(0x3) << AFEC_CGR_GAIN3_Pos) /**< (AFEC_CGR) Gain for Channel 3 Mask */
|
||||
#define AFEC_CGR_GAIN3(value) (AFEC_CGR_GAIN3_Msk & ((value) << AFEC_CGR_GAIN3_Pos))
|
||||
#define AFEC_CGR_GAIN4_Pos _U_(8) /**< (AFEC_CGR) Gain for Channel 4 Position */
|
||||
#define AFEC_CGR_GAIN4_Msk (_U_(0x3) << AFEC_CGR_GAIN4_Pos) /**< (AFEC_CGR) Gain for Channel 4 Mask */
|
||||
#define AFEC_CGR_GAIN4(value) (AFEC_CGR_GAIN4_Msk & ((value) << AFEC_CGR_GAIN4_Pos))
|
||||
#define AFEC_CGR_GAIN5_Pos _U_(10) /**< (AFEC_CGR) Gain for Channel 5 Position */
|
||||
#define AFEC_CGR_GAIN5_Msk (_U_(0x3) << AFEC_CGR_GAIN5_Pos) /**< (AFEC_CGR) Gain for Channel 5 Mask */
|
||||
#define AFEC_CGR_GAIN5(value) (AFEC_CGR_GAIN5_Msk & ((value) << AFEC_CGR_GAIN5_Pos))
|
||||
#define AFEC_CGR_GAIN6_Pos _U_(12) /**< (AFEC_CGR) Gain for Channel 6 Position */
|
||||
#define AFEC_CGR_GAIN6_Msk (_U_(0x3) << AFEC_CGR_GAIN6_Pos) /**< (AFEC_CGR) Gain for Channel 6 Mask */
|
||||
#define AFEC_CGR_GAIN6(value) (AFEC_CGR_GAIN6_Msk & ((value) << AFEC_CGR_GAIN6_Pos))
|
||||
#define AFEC_CGR_GAIN7_Pos _U_(14) /**< (AFEC_CGR) Gain for Channel 7 Position */
|
||||
#define AFEC_CGR_GAIN7_Msk (_U_(0x3) << AFEC_CGR_GAIN7_Pos) /**< (AFEC_CGR) Gain for Channel 7 Mask */
|
||||
#define AFEC_CGR_GAIN7(value) (AFEC_CGR_GAIN7_Msk & ((value) << AFEC_CGR_GAIN7_Pos))
|
||||
#define AFEC_CGR_GAIN8_Pos _U_(16) /**< (AFEC_CGR) Gain for Channel 8 Position */
|
||||
#define AFEC_CGR_GAIN8_Msk (_U_(0x3) << AFEC_CGR_GAIN8_Pos) /**< (AFEC_CGR) Gain for Channel 8 Mask */
|
||||
#define AFEC_CGR_GAIN8(value) (AFEC_CGR_GAIN8_Msk & ((value) << AFEC_CGR_GAIN8_Pos))
|
||||
#define AFEC_CGR_GAIN9_Pos _U_(18) /**< (AFEC_CGR) Gain for Channel 9 Position */
|
||||
#define AFEC_CGR_GAIN9_Msk (_U_(0x3) << AFEC_CGR_GAIN9_Pos) /**< (AFEC_CGR) Gain for Channel 9 Mask */
|
||||
#define AFEC_CGR_GAIN9(value) (AFEC_CGR_GAIN9_Msk & ((value) << AFEC_CGR_GAIN9_Pos))
|
||||
#define AFEC_CGR_GAIN10_Pos _U_(20) /**< (AFEC_CGR) Gain for Channel 10 Position */
|
||||
#define AFEC_CGR_GAIN10_Msk (_U_(0x3) << AFEC_CGR_GAIN10_Pos) /**< (AFEC_CGR) Gain for Channel 10 Mask */
|
||||
#define AFEC_CGR_GAIN10(value) (AFEC_CGR_GAIN10_Msk & ((value) << AFEC_CGR_GAIN10_Pos))
|
||||
#define AFEC_CGR_GAIN11_Pos _U_(22) /**< (AFEC_CGR) Gain for Channel 11 Position */
|
||||
#define AFEC_CGR_GAIN11_Msk (_U_(0x3) << AFEC_CGR_GAIN11_Pos) /**< (AFEC_CGR) Gain for Channel 11 Mask */
|
||||
#define AFEC_CGR_GAIN11(value) (AFEC_CGR_GAIN11_Msk & ((value) << AFEC_CGR_GAIN11_Pos))
|
||||
#define AFEC_CGR_Msk _U_(0x00FFFFFF) /**< (AFEC_CGR) Register Mask */
|
||||
|
||||
|
||||
/* -------- AFEC_DIFFR : (AFEC Offset: 0x60) (R/W 32) AFEC Channel Differential Register -------- */
|
||||
#define AFEC_DIFFR_DIFF0_Pos _U_(0) /**< (AFEC_DIFFR) Differential inputs for channel 0 Position */
|
||||
#define AFEC_DIFFR_DIFF0_Msk (_U_(0x1) << AFEC_DIFFR_DIFF0_Pos) /**< (AFEC_DIFFR) Differential inputs for channel 0 Mask */
|
||||
#define AFEC_DIFFR_DIFF0(value) (AFEC_DIFFR_DIFF0_Msk & ((value) << AFEC_DIFFR_DIFF0_Pos))
|
||||
#define AFEC_DIFFR_DIFF1_Pos _U_(1) /**< (AFEC_DIFFR) Differential inputs for channel 1 Position */
|
||||
#define AFEC_DIFFR_DIFF1_Msk (_U_(0x1) << AFEC_DIFFR_DIFF1_Pos) /**< (AFEC_DIFFR) Differential inputs for channel 1 Mask */
|
||||
#define AFEC_DIFFR_DIFF1(value) (AFEC_DIFFR_DIFF1_Msk & ((value) << AFEC_DIFFR_DIFF1_Pos))
|
||||
#define AFEC_DIFFR_DIFF2_Pos _U_(2) /**< (AFEC_DIFFR) Differential inputs for channel 2 Position */
|
||||
#define AFEC_DIFFR_DIFF2_Msk (_U_(0x1) << AFEC_DIFFR_DIFF2_Pos) /**< (AFEC_DIFFR) Differential inputs for channel 2 Mask */
|
||||
#define AFEC_DIFFR_DIFF2(value) (AFEC_DIFFR_DIFF2_Msk & ((value) << AFEC_DIFFR_DIFF2_Pos))
|
||||
#define AFEC_DIFFR_DIFF3_Pos _U_(3) /**< (AFEC_DIFFR) Differential inputs for channel 3 Position */
|
||||
#define AFEC_DIFFR_DIFF3_Msk (_U_(0x1) << AFEC_DIFFR_DIFF3_Pos) /**< (AFEC_DIFFR) Differential inputs for channel 3 Mask */
|
||||
#define AFEC_DIFFR_DIFF3(value) (AFEC_DIFFR_DIFF3_Msk & ((value) << AFEC_DIFFR_DIFF3_Pos))
|
||||
#define AFEC_DIFFR_DIFF4_Pos _U_(4) /**< (AFEC_DIFFR) Differential inputs for channel 4 Position */
|
||||
#define AFEC_DIFFR_DIFF4_Msk (_U_(0x1) << AFEC_DIFFR_DIFF4_Pos) /**< (AFEC_DIFFR) Differential inputs for channel 4 Mask */
|
||||
#define AFEC_DIFFR_DIFF4(value) (AFEC_DIFFR_DIFF4_Msk & ((value) << AFEC_DIFFR_DIFF4_Pos))
|
||||
#define AFEC_DIFFR_DIFF5_Pos _U_(5) /**< (AFEC_DIFFR) Differential inputs for channel 5 Position */
|
||||
#define AFEC_DIFFR_DIFF5_Msk (_U_(0x1) << AFEC_DIFFR_DIFF5_Pos) /**< (AFEC_DIFFR) Differential inputs for channel 5 Mask */
|
||||
#define AFEC_DIFFR_DIFF5(value) (AFEC_DIFFR_DIFF5_Msk & ((value) << AFEC_DIFFR_DIFF5_Pos))
|
||||
#define AFEC_DIFFR_DIFF6_Pos _U_(6) /**< (AFEC_DIFFR) Differential inputs for channel 6 Position */
|
||||
#define AFEC_DIFFR_DIFF6_Msk (_U_(0x1) << AFEC_DIFFR_DIFF6_Pos) /**< (AFEC_DIFFR) Differential inputs for channel 6 Mask */
|
||||
#define AFEC_DIFFR_DIFF6(value) (AFEC_DIFFR_DIFF6_Msk & ((value) << AFEC_DIFFR_DIFF6_Pos))
|
||||
#define AFEC_DIFFR_DIFF7_Pos _U_(7) /**< (AFEC_DIFFR) Differential inputs for channel 7 Position */
|
||||
#define AFEC_DIFFR_DIFF7_Msk (_U_(0x1) << AFEC_DIFFR_DIFF7_Pos) /**< (AFEC_DIFFR) Differential inputs for channel 7 Mask */
|
||||
#define AFEC_DIFFR_DIFF7(value) (AFEC_DIFFR_DIFF7_Msk & ((value) << AFEC_DIFFR_DIFF7_Pos))
|
||||
#define AFEC_DIFFR_DIFF8_Pos _U_(8) /**< (AFEC_DIFFR) Differential inputs for channel 8 Position */
|
||||
#define AFEC_DIFFR_DIFF8_Msk (_U_(0x1) << AFEC_DIFFR_DIFF8_Pos) /**< (AFEC_DIFFR) Differential inputs for channel 8 Mask */
|
||||
#define AFEC_DIFFR_DIFF8(value) (AFEC_DIFFR_DIFF8_Msk & ((value) << AFEC_DIFFR_DIFF8_Pos))
|
||||
#define AFEC_DIFFR_DIFF9_Pos _U_(9) /**< (AFEC_DIFFR) Differential inputs for channel 9 Position */
|
||||
#define AFEC_DIFFR_DIFF9_Msk (_U_(0x1) << AFEC_DIFFR_DIFF9_Pos) /**< (AFEC_DIFFR) Differential inputs for channel 9 Mask */
|
||||
#define AFEC_DIFFR_DIFF9(value) (AFEC_DIFFR_DIFF9_Msk & ((value) << AFEC_DIFFR_DIFF9_Pos))
|
||||
#define AFEC_DIFFR_DIFF10_Pos _U_(10) /**< (AFEC_DIFFR) Differential inputs for channel 10 Position */
|
||||
#define AFEC_DIFFR_DIFF10_Msk (_U_(0x1) << AFEC_DIFFR_DIFF10_Pos) /**< (AFEC_DIFFR) Differential inputs for channel 10 Mask */
|
||||
#define AFEC_DIFFR_DIFF10(value) (AFEC_DIFFR_DIFF10_Msk & ((value) << AFEC_DIFFR_DIFF10_Pos))
|
||||
#define AFEC_DIFFR_DIFF11_Pos _U_(11) /**< (AFEC_DIFFR) Differential inputs for channel 11 Position */
|
||||
#define AFEC_DIFFR_DIFF11_Msk (_U_(0x1) << AFEC_DIFFR_DIFF11_Pos) /**< (AFEC_DIFFR) Differential inputs for channel 11 Mask */
|
||||
#define AFEC_DIFFR_DIFF11(value) (AFEC_DIFFR_DIFF11_Msk & ((value) << AFEC_DIFFR_DIFF11_Pos))
|
||||
#define AFEC_DIFFR_Msk _U_(0x00000FFF) /**< (AFEC_DIFFR) Register Mask */
|
||||
|
||||
#define AFEC_DIFFR_DIFF_Pos _U_(0) /**< (AFEC_DIFFR Position) Differential inputs for channel xx */
|
||||
#define AFEC_DIFFR_DIFF_Msk (_U_(0xFFF) << AFEC_DIFFR_DIFF_Pos) /**< (AFEC_DIFFR Mask) DIFF */
|
||||
#define AFEC_DIFFR_DIFF(value) (AFEC_DIFFR_DIFF_Msk & ((value) << AFEC_DIFFR_DIFF_Pos))
|
||||
|
||||
/* -------- AFEC_CSELR : (AFEC Offset: 0x64) (R/W 32) AFEC Channel Selection Register -------- */
|
||||
#define AFEC_CSELR_CSEL_Pos _U_(0) /**< (AFEC_CSELR) Channel Selection Position */
|
||||
#define AFEC_CSELR_CSEL_Msk (_U_(0xF) << AFEC_CSELR_CSEL_Pos) /**< (AFEC_CSELR) Channel Selection Mask */
|
||||
#define AFEC_CSELR_CSEL(value) (AFEC_CSELR_CSEL_Msk & ((value) << AFEC_CSELR_CSEL_Pos))
|
||||
#define AFEC_CSELR_Msk _U_(0x0000000F) /**< (AFEC_CSELR) Register Mask */
|
||||
|
||||
|
||||
/* -------- AFEC_CDR : (AFEC Offset: 0x68) ( R/ 32) AFEC Channel Data Register -------- */
|
||||
#define AFEC_CDR_DATA_Pos _U_(0) /**< (AFEC_CDR) Converted Data Position */
|
||||
#define AFEC_CDR_DATA_Msk (_U_(0xFFFF) << AFEC_CDR_DATA_Pos) /**< (AFEC_CDR) Converted Data Mask */
|
||||
#define AFEC_CDR_DATA(value) (AFEC_CDR_DATA_Msk & ((value) << AFEC_CDR_DATA_Pos))
|
||||
#define AFEC_CDR_Msk _U_(0x0000FFFF) /**< (AFEC_CDR) Register Mask */
|
||||
|
||||
|
||||
/* -------- AFEC_COCR : (AFEC Offset: 0x6C) (R/W 32) AFEC Channel Offset Compensation Register -------- */
|
||||
#define AFEC_COCR_AOFF_Pos _U_(0) /**< (AFEC_COCR) Analog Offset Position */
|
||||
#define AFEC_COCR_AOFF_Msk (_U_(0x3FF) << AFEC_COCR_AOFF_Pos) /**< (AFEC_COCR) Analog Offset Mask */
|
||||
#define AFEC_COCR_AOFF(value) (AFEC_COCR_AOFF_Msk & ((value) << AFEC_COCR_AOFF_Pos))
|
||||
#define AFEC_COCR_Msk _U_(0x000003FF) /**< (AFEC_COCR) Register Mask */
|
||||
|
||||
|
||||
/* -------- AFEC_TEMPMR : (AFEC Offset: 0x70) (R/W 32) AFEC Temperature Sensor Mode Register -------- */
|
||||
#define AFEC_TEMPMR_RTCT_Pos _U_(0) /**< (AFEC_TEMPMR) Temperature Sensor RTC Trigger Mode Position */
|
||||
#define AFEC_TEMPMR_RTCT_Msk (_U_(0x1) << AFEC_TEMPMR_RTCT_Pos) /**< (AFEC_TEMPMR) Temperature Sensor RTC Trigger Mode Mask */
|
||||
#define AFEC_TEMPMR_RTCT(value) (AFEC_TEMPMR_RTCT_Msk & ((value) << AFEC_TEMPMR_RTCT_Pos))
|
||||
#define AFEC_TEMPMR_TEMPCMPMOD_Pos _U_(4) /**< (AFEC_TEMPMR) Temperature Comparison Mode Position */
|
||||
#define AFEC_TEMPMR_TEMPCMPMOD_Msk (_U_(0x3) << AFEC_TEMPMR_TEMPCMPMOD_Pos) /**< (AFEC_TEMPMR) Temperature Comparison Mode Mask */
|
||||
#define AFEC_TEMPMR_TEMPCMPMOD(value) (AFEC_TEMPMR_TEMPCMPMOD_Msk & ((value) << AFEC_TEMPMR_TEMPCMPMOD_Pos))
|
||||
#define AFEC_TEMPMR_TEMPCMPMOD_LOW_Val _U_(0x0) /**< (AFEC_TEMPMR) Generates an event when the converted data is lower than the low threshold of the window. */
|
||||
#define AFEC_TEMPMR_TEMPCMPMOD_HIGH_Val _U_(0x1) /**< (AFEC_TEMPMR) Generates an event when the converted data is higher than the high threshold of the window. */
|
||||
#define AFEC_TEMPMR_TEMPCMPMOD_IN_Val _U_(0x2) /**< (AFEC_TEMPMR) Generates an event when the converted data is in the comparison window. */
|
||||
#define AFEC_TEMPMR_TEMPCMPMOD_OUT_Val _U_(0x3) /**< (AFEC_TEMPMR) Generates an event when the converted data is out of the comparison window. */
|
||||
#define AFEC_TEMPMR_TEMPCMPMOD_LOW (AFEC_TEMPMR_TEMPCMPMOD_LOW_Val << AFEC_TEMPMR_TEMPCMPMOD_Pos) /**< (AFEC_TEMPMR) Generates an event when the converted data is lower than the low threshold of the window. Position */
|
||||
#define AFEC_TEMPMR_TEMPCMPMOD_HIGH (AFEC_TEMPMR_TEMPCMPMOD_HIGH_Val << AFEC_TEMPMR_TEMPCMPMOD_Pos) /**< (AFEC_TEMPMR) Generates an event when the converted data is higher than the high threshold of the window. Position */
|
||||
#define AFEC_TEMPMR_TEMPCMPMOD_IN (AFEC_TEMPMR_TEMPCMPMOD_IN_Val << AFEC_TEMPMR_TEMPCMPMOD_Pos) /**< (AFEC_TEMPMR) Generates an event when the converted data is in the comparison window. Position */
|
||||
#define AFEC_TEMPMR_TEMPCMPMOD_OUT (AFEC_TEMPMR_TEMPCMPMOD_OUT_Val << AFEC_TEMPMR_TEMPCMPMOD_Pos) /**< (AFEC_TEMPMR) Generates an event when the converted data is out of the comparison window. Position */
|
||||
#define AFEC_TEMPMR_Msk _U_(0x00000031) /**< (AFEC_TEMPMR) Register Mask */
|
||||
|
||||
|
||||
/* -------- AFEC_TEMPCWR : (AFEC Offset: 0x74) (R/W 32) AFEC Temperature Compare Window Register -------- */
|
||||
#define AFEC_TEMPCWR_TLOWTHRES_Pos _U_(0) /**< (AFEC_TEMPCWR) Temperature Low Threshold Position */
|
||||
#define AFEC_TEMPCWR_TLOWTHRES_Msk (_U_(0xFFFF) << AFEC_TEMPCWR_TLOWTHRES_Pos) /**< (AFEC_TEMPCWR) Temperature Low Threshold Mask */
|
||||
#define AFEC_TEMPCWR_TLOWTHRES(value) (AFEC_TEMPCWR_TLOWTHRES_Msk & ((value) << AFEC_TEMPCWR_TLOWTHRES_Pos))
|
||||
#define AFEC_TEMPCWR_THIGHTHRES_Pos _U_(16) /**< (AFEC_TEMPCWR) Temperature High Threshold Position */
|
||||
#define AFEC_TEMPCWR_THIGHTHRES_Msk (_U_(0xFFFF) << AFEC_TEMPCWR_THIGHTHRES_Pos) /**< (AFEC_TEMPCWR) Temperature High Threshold Mask */
|
||||
#define AFEC_TEMPCWR_THIGHTHRES(value) (AFEC_TEMPCWR_THIGHTHRES_Msk & ((value) << AFEC_TEMPCWR_THIGHTHRES_Pos))
|
||||
#define AFEC_TEMPCWR_Msk _U_(0xFFFFFFFF) /**< (AFEC_TEMPCWR) Register Mask */
|
||||
|
||||
|
||||
/* -------- AFEC_ACR : (AFEC Offset: 0x94) (R/W 32) AFEC Analog Control Register -------- */
|
||||
#define AFEC_ACR_PGA0EN_Pos _U_(2) /**< (AFEC_ACR) PGA0 Enable Position */
|
||||
#define AFEC_ACR_PGA0EN_Msk (_U_(0x1) << AFEC_ACR_PGA0EN_Pos) /**< (AFEC_ACR) PGA0 Enable Mask */
|
||||
#define AFEC_ACR_PGA0EN(value) (AFEC_ACR_PGA0EN_Msk & ((value) << AFEC_ACR_PGA0EN_Pos))
|
||||
#define AFEC_ACR_PGA1EN_Pos _U_(3) /**< (AFEC_ACR) PGA1 Enable Position */
|
||||
#define AFEC_ACR_PGA1EN_Msk (_U_(0x1) << AFEC_ACR_PGA1EN_Pos) /**< (AFEC_ACR) PGA1 Enable Mask */
|
||||
#define AFEC_ACR_PGA1EN(value) (AFEC_ACR_PGA1EN_Msk & ((value) << AFEC_ACR_PGA1EN_Pos))
|
||||
#define AFEC_ACR_IBCTL_Pos _U_(8) /**< (AFEC_ACR) AFE Bias Current Control Position */
|
||||
#define AFEC_ACR_IBCTL_Msk (_U_(0x3) << AFEC_ACR_IBCTL_Pos) /**< (AFEC_ACR) AFE Bias Current Control Mask */
|
||||
#define AFEC_ACR_IBCTL(value) (AFEC_ACR_IBCTL_Msk & ((value) << AFEC_ACR_IBCTL_Pos))
|
||||
#define AFEC_ACR_Msk _U_(0x0000030C) /**< (AFEC_ACR) Register Mask */
|
||||
|
||||
|
||||
/* -------- AFEC_SHMR : (AFEC Offset: 0xA0) (R/W 32) AFEC Sample & Hold Mode Register -------- */
|
||||
#define AFEC_SHMR_DUAL0_Pos _U_(0) /**< (AFEC_SHMR) Dual Sample & Hold for channel 0 Position */
|
||||
#define AFEC_SHMR_DUAL0_Msk (_U_(0x1) << AFEC_SHMR_DUAL0_Pos) /**< (AFEC_SHMR) Dual Sample & Hold for channel 0 Mask */
|
||||
#define AFEC_SHMR_DUAL0(value) (AFEC_SHMR_DUAL0_Msk & ((value) << AFEC_SHMR_DUAL0_Pos))
|
||||
#define AFEC_SHMR_DUAL1_Pos _U_(1) /**< (AFEC_SHMR) Dual Sample & Hold for channel 1 Position */
|
||||
#define AFEC_SHMR_DUAL1_Msk (_U_(0x1) << AFEC_SHMR_DUAL1_Pos) /**< (AFEC_SHMR) Dual Sample & Hold for channel 1 Mask */
|
||||
#define AFEC_SHMR_DUAL1(value) (AFEC_SHMR_DUAL1_Msk & ((value) << AFEC_SHMR_DUAL1_Pos))
|
||||
#define AFEC_SHMR_DUAL2_Pos _U_(2) /**< (AFEC_SHMR) Dual Sample & Hold for channel 2 Position */
|
||||
#define AFEC_SHMR_DUAL2_Msk (_U_(0x1) << AFEC_SHMR_DUAL2_Pos) /**< (AFEC_SHMR) Dual Sample & Hold for channel 2 Mask */
|
||||
#define AFEC_SHMR_DUAL2(value) (AFEC_SHMR_DUAL2_Msk & ((value) << AFEC_SHMR_DUAL2_Pos))
|
||||
#define AFEC_SHMR_DUAL3_Pos _U_(3) /**< (AFEC_SHMR) Dual Sample & Hold for channel 3 Position */
|
||||
#define AFEC_SHMR_DUAL3_Msk (_U_(0x1) << AFEC_SHMR_DUAL3_Pos) /**< (AFEC_SHMR) Dual Sample & Hold for channel 3 Mask */
|
||||
#define AFEC_SHMR_DUAL3(value) (AFEC_SHMR_DUAL3_Msk & ((value) << AFEC_SHMR_DUAL3_Pos))
|
||||
#define AFEC_SHMR_DUAL4_Pos _U_(4) /**< (AFEC_SHMR) Dual Sample & Hold for channel 4 Position */
|
||||
#define AFEC_SHMR_DUAL4_Msk (_U_(0x1) << AFEC_SHMR_DUAL4_Pos) /**< (AFEC_SHMR) Dual Sample & Hold for channel 4 Mask */
|
||||
#define AFEC_SHMR_DUAL4(value) (AFEC_SHMR_DUAL4_Msk & ((value) << AFEC_SHMR_DUAL4_Pos))
|
||||
#define AFEC_SHMR_DUAL5_Pos _U_(5) /**< (AFEC_SHMR) Dual Sample & Hold for channel 5 Position */
|
||||
#define AFEC_SHMR_DUAL5_Msk (_U_(0x1) << AFEC_SHMR_DUAL5_Pos) /**< (AFEC_SHMR) Dual Sample & Hold for channel 5 Mask */
|
||||
#define AFEC_SHMR_DUAL5(value) (AFEC_SHMR_DUAL5_Msk & ((value) << AFEC_SHMR_DUAL5_Pos))
|
||||
#define AFEC_SHMR_DUAL6_Pos _U_(6) /**< (AFEC_SHMR) Dual Sample & Hold for channel 6 Position */
|
||||
#define AFEC_SHMR_DUAL6_Msk (_U_(0x1) << AFEC_SHMR_DUAL6_Pos) /**< (AFEC_SHMR) Dual Sample & Hold for channel 6 Mask */
|
||||
#define AFEC_SHMR_DUAL6(value) (AFEC_SHMR_DUAL6_Msk & ((value) << AFEC_SHMR_DUAL6_Pos))
|
||||
#define AFEC_SHMR_DUAL7_Pos _U_(7) /**< (AFEC_SHMR) Dual Sample & Hold for channel 7 Position */
|
||||
#define AFEC_SHMR_DUAL7_Msk (_U_(0x1) << AFEC_SHMR_DUAL7_Pos) /**< (AFEC_SHMR) Dual Sample & Hold for channel 7 Mask */
|
||||
#define AFEC_SHMR_DUAL7(value) (AFEC_SHMR_DUAL7_Msk & ((value) << AFEC_SHMR_DUAL7_Pos))
|
||||
#define AFEC_SHMR_DUAL8_Pos _U_(8) /**< (AFEC_SHMR) Dual Sample & Hold for channel 8 Position */
|
||||
#define AFEC_SHMR_DUAL8_Msk (_U_(0x1) << AFEC_SHMR_DUAL8_Pos) /**< (AFEC_SHMR) Dual Sample & Hold for channel 8 Mask */
|
||||
#define AFEC_SHMR_DUAL8(value) (AFEC_SHMR_DUAL8_Msk & ((value) << AFEC_SHMR_DUAL8_Pos))
|
||||
#define AFEC_SHMR_DUAL9_Pos _U_(9) /**< (AFEC_SHMR) Dual Sample & Hold for channel 9 Position */
|
||||
#define AFEC_SHMR_DUAL9_Msk (_U_(0x1) << AFEC_SHMR_DUAL9_Pos) /**< (AFEC_SHMR) Dual Sample & Hold for channel 9 Mask */
|
||||
#define AFEC_SHMR_DUAL9(value) (AFEC_SHMR_DUAL9_Msk & ((value) << AFEC_SHMR_DUAL9_Pos))
|
||||
#define AFEC_SHMR_DUAL10_Pos _U_(10) /**< (AFEC_SHMR) Dual Sample & Hold for channel 10 Position */
|
||||
#define AFEC_SHMR_DUAL10_Msk (_U_(0x1) << AFEC_SHMR_DUAL10_Pos) /**< (AFEC_SHMR) Dual Sample & Hold for channel 10 Mask */
|
||||
#define AFEC_SHMR_DUAL10(value) (AFEC_SHMR_DUAL10_Msk & ((value) << AFEC_SHMR_DUAL10_Pos))
|
||||
#define AFEC_SHMR_DUAL11_Pos _U_(11) /**< (AFEC_SHMR) Dual Sample & Hold for channel 11 Position */
|
||||
#define AFEC_SHMR_DUAL11_Msk (_U_(0x1) << AFEC_SHMR_DUAL11_Pos) /**< (AFEC_SHMR) Dual Sample & Hold for channel 11 Mask */
|
||||
#define AFEC_SHMR_DUAL11(value) (AFEC_SHMR_DUAL11_Msk & ((value) << AFEC_SHMR_DUAL11_Pos))
|
||||
#define AFEC_SHMR_Msk _U_(0x00000FFF) /**< (AFEC_SHMR) Register Mask */
|
||||
|
||||
#define AFEC_SHMR_DUAL_Pos _U_(0) /**< (AFEC_SHMR Position) Dual Sample & Hold for channel xx */
|
||||
#define AFEC_SHMR_DUAL_Msk (_U_(0xFFF) << AFEC_SHMR_DUAL_Pos) /**< (AFEC_SHMR Mask) DUAL */
|
||||
#define AFEC_SHMR_DUAL(value) (AFEC_SHMR_DUAL_Msk & ((value) << AFEC_SHMR_DUAL_Pos))
|
||||
|
||||
/* -------- AFEC_COSR : (AFEC Offset: 0xD0) (R/W 32) AFEC Correction Select Register -------- */
|
||||
#define AFEC_COSR_CSEL_Pos _U_(0) /**< (AFEC_COSR) Sample & Hold unit Correction Select Position */
|
||||
#define AFEC_COSR_CSEL_Msk (_U_(0x1) << AFEC_COSR_CSEL_Pos) /**< (AFEC_COSR) Sample & Hold unit Correction Select Mask */
|
||||
#define AFEC_COSR_CSEL(value) (AFEC_COSR_CSEL_Msk & ((value) << AFEC_COSR_CSEL_Pos))
|
||||
#define AFEC_COSR_Msk _U_(0x00000001) /**< (AFEC_COSR) Register Mask */
|
||||
|
||||
|
||||
/* -------- AFEC_CVR : (AFEC Offset: 0xD4) (R/W 32) AFEC Correction Values Register -------- */
|
||||
#define AFEC_CVR_OFFSETCORR_Pos _U_(0) /**< (AFEC_CVR) Offset Correction Position */
|
||||
#define AFEC_CVR_OFFSETCORR_Msk (_U_(0xFFFF) << AFEC_CVR_OFFSETCORR_Pos) /**< (AFEC_CVR) Offset Correction Mask */
|
||||
#define AFEC_CVR_OFFSETCORR(value) (AFEC_CVR_OFFSETCORR_Msk & ((value) << AFEC_CVR_OFFSETCORR_Pos))
|
||||
#define AFEC_CVR_GAINCORR_Pos _U_(16) /**< (AFEC_CVR) Gain Correction Position */
|
||||
#define AFEC_CVR_GAINCORR_Msk (_U_(0xFFFF) << AFEC_CVR_GAINCORR_Pos) /**< (AFEC_CVR) Gain Correction Mask */
|
||||
#define AFEC_CVR_GAINCORR(value) (AFEC_CVR_GAINCORR_Msk & ((value) << AFEC_CVR_GAINCORR_Pos))
|
||||
#define AFEC_CVR_Msk _U_(0xFFFFFFFF) /**< (AFEC_CVR) Register Mask */
|
||||
|
||||
|
||||
/* -------- AFEC_CECR : (AFEC Offset: 0xD8) (R/W 32) AFEC Channel Error Correction Register -------- */
|
||||
#define AFEC_CECR_ECORR0_Pos _U_(0) /**< (AFEC_CECR) Error Correction Enable for channel 0 Position */
|
||||
#define AFEC_CECR_ECORR0_Msk (_U_(0x1) << AFEC_CECR_ECORR0_Pos) /**< (AFEC_CECR) Error Correction Enable for channel 0 Mask */
|
||||
#define AFEC_CECR_ECORR0(value) (AFEC_CECR_ECORR0_Msk & ((value) << AFEC_CECR_ECORR0_Pos))
|
||||
#define AFEC_CECR_ECORR1_Pos _U_(1) /**< (AFEC_CECR) Error Correction Enable for channel 1 Position */
|
||||
#define AFEC_CECR_ECORR1_Msk (_U_(0x1) << AFEC_CECR_ECORR1_Pos) /**< (AFEC_CECR) Error Correction Enable for channel 1 Mask */
|
||||
#define AFEC_CECR_ECORR1(value) (AFEC_CECR_ECORR1_Msk & ((value) << AFEC_CECR_ECORR1_Pos))
|
||||
#define AFEC_CECR_ECORR2_Pos _U_(2) /**< (AFEC_CECR) Error Correction Enable for channel 2 Position */
|
||||
#define AFEC_CECR_ECORR2_Msk (_U_(0x1) << AFEC_CECR_ECORR2_Pos) /**< (AFEC_CECR) Error Correction Enable for channel 2 Mask */
|
||||
#define AFEC_CECR_ECORR2(value) (AFEC_CECR_ECORR2_Msk & ((value) << AFEC_CECR_ECORR2_Pos))
|
||||
#define AFEC_CECR_ECORR3_Pos _U_(3) /**< (AFEC_CECR) Error Correction Enable for channel 3 Position */
|
||||
#define AFEC_CECR_ECORR3_Msk (_U_(0x1) << AFEC_CECR_ECORR3_Pos) /**< (AFEC_CECR) Error Correction Enable for channel 3 Mask */
|
||||
#define AFEC_CECR_ECORR3(value) (AFEC_CECR_ECORR3_Msk & ((value) << AFEC_CECR_ECORR3_Pos))
|
||||
#define AFEC_CECR_ECORR4_Pos _U_(4) /**< (AFEC_CECR) Error Correction Enable for channel 4 Position */
|
||||
#define AFEC_CECR_ECORR4_Msk (_U_(0x1) << AFEC_CECR_ECORR4_Pos) /**< (AFEC_CECR) Error Correction Enable for channel 4 Mask */
|
||||
#define AFEC_CECR_ECORR4(value) (AFEC_CECR_ECORR4_Msk & ((value) << AFEC_CECR_ECORR4_Pos))
|
||||
#define AFEC_CECR_ECORR5_Pos _U_(5) /**< (AFEC_CECR) Error Correction Enable for channel 5 Position */
|
||||
#define AFEC_CECR_ECORR5_Msk (_U_(0x1) << AFEC_CECR_ECORR5_Pos) /**< (AFEC_CECR) Error Correction Enable for channel 5 Mask */
|
||||
#define AFEC_CECR_ECORR5(value) (AFEC_CECR_ECORR5_Msk & ((value) << AFEC_CECR_ECORR5_Pos))
|
||||
#define AFEC_CECR_ECORR6_Pos _U_(6) /**< (AFEC_CECR) Error Correction Enable for channel 6 Position */
|
||||
#define AFEC_CECR_ECORR6_Msk (_U_(0x1) << AFEC_CECR_ECORR6_Pos) /**< (AFEC_CECR) Error Correction Enable for channel 6 Mask */
|
||||
#define AFEC_CECR_ECORR6(value) (AFEC_CECR_ECORR6_Msk & ((value) << AFEC_CECR_ECORR6_Pos))
|
||||
#define AFEC_CECR_ECORR7_Pos _U_(7) /**< (AFEC_CECR) Error Correction Enable for channel 7 Position */
|
||||
#define AFEC_CECR_ECORR7_Msk (_U_(0x1) << AFEC_CECR_ECORR7_Pos) /**< (AFEC_CECR) Error Correction Enable for channel 7 Mask */
|
||||
#define AFEC_CECR_ECORR7(value) (AFEC_CECR_ECORR7_Msk & ((value) << AFEC_CECR_ECORR7_Pos))
|
||||
#define AFEC_CECR_ECORR8_Pos _U_(8) /**< (AFEC_CECR) Error Correction Enable for channel 8 Position */
|
||||
#define AFEC_CECR_ECORR8_Msk (_U_(0x1) << AFEC_CECR_ECORR8_Pos) /**< (AFEC_CECR) Error Correction Enable for channel 8 Mask */
|
||||
#define AFEC_CECR_ECORR8(value) (AFEC_CECR_ECORR8_Msk & ((value) << AFEC_CECR_ECORR8_Pos))
|
||||
#define AFEC_CECR_ECORR9_Pos _U_(9) /**< (AFEC_CECR) Error Correction Enable for channel 9 Position */
|
||||
#define AFEC_CECR_ECORR9_Msk (_U_(0x1) << AFEC_CECR_ECORR9_Pos) /**< (AFEC_CECR) Error Correction Enable for channel 9 Mask */
|
||||
#define AFEC_CECR_ECORR9(value) (AFEC_CECR_ECORR9_Msk & ((value) << AFEC_CECR_ECORR9_Pos))
|
||||
#define AFEC_CECR_ECORR10_Pos _U_(10) /**< (AFEC_CECR) Error Correction Enable for channel 10 Position */
|
||||
#define AFEC_CECR_ECORR10_Msk (_U_(0x1) << AFEC_CECR_ECORR10_Pos) /**< (AFEC_CECR) Error Correction Enable for channel 10 Mask */
|
||||
#define AFEC_CECR_ECORR10(value) (AFEC_CECR_ECORR10_Msk & ((value) << AFEC_CECR_ECORR10_Pos))
|
||||
#define AFEC_CECR_ECORR11_Pos _U_(11) /**< (AFEC_CECR) Error Correction Enable for channel 11 Position */
|
||||
#define AFEC_CECR_ECORR11_Msk (_U_(0x1) << AFEC_CECR_ECORR11_Pos) /**< (AFEC_CECR) Error Correction Enable for channel 11 Mask */
|
||||
#define AFEC_CECR_ECORR11(value) (AFEC_CECR_ECORR11_Msk & ((value) << AFEC_CECR_ECORR11_Pos))
|
||||
#define AFEC_CECR_Msk _U_(0x00000FFF) /**< (AFEC_CECR) Register Mask */
|
||||
|
||||
#define AFEC_CECR_ECORR_Pos _U_(0) /**< (AFEC_CECR Position) Error Correction Enable for channel xx */
|
||||
#define AFEC_CECR_ECORR_Msk (_U_(0xFFF) << AFEC_CECR_ECORR_Pos) /**< (AFEC_CECR Mask) ECORR */
|
||||
#define AFEC_CECR_ECORR(value) (AFEC_CECR_ECORR_Msk & ((value) << AFEC_CECR_ECORR_Pos))
|
||||
|
||||
/* -------- AFEC_WPMR : (AFEC Offset: 0xE4) (R/W 32) AFEC Write Protection Mode Register -------- */
|
||||
#define AFEC_WPMR_WPEN_Pos _U_(0) /**< (AFEC_WPMR) Write Protection Enable Position */
|
||||
#define AFEC_WPMR_WPEN_Msk (_U_(0x1) << AFEC_WPMR_WPEN_Pos) /**< (AFEC_WPMR) Write Protection Enable Mask */
|
||||
#define AFEC_WPMR_WPEN(value) (AFEC_WPMR_WPEN_Msk & ((value) << AFEC_WPMR_WPEN_Pos))
|
||||
#define AFEC_WPMR_WPKEY_Pos _U_(8) /**< (AFEC_WPMR) Write Protect KEY Position */
|
||||
#define AFEC_WPMR_WPKEY_Msk (_U_(0xFFFFFF) << AFEC_WPMR_WPKEY_Pos) /**< (AFEC_WPMR) Write Protect KEY Mask */
|
||||
#define AFEC_WPMR_WPKEY(value) (AFEC_WPMR_WPKEY_Msk & ((value) << AFEC_WPMR_WPKEY_Pos))
|
||||
#define AFEC_WPMR_WPKEY_PASSWD_Val _U_(0x414443) /**< (AFEC_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. */
|
||||
#define AFEC_WPMR_WPKEY_PASSWD (AFEC_WPMR_WPKEY_PASSWD_Val << AFEC_WPMR_WPKEY_Pos) /**< (AFEC_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. Position */
|
||||
#define AFEC_WPMR_Msk _U_(0xFFFFFF01) /**< (AFEC_WPMR) Register Mask */
|
||||
|
||||
|
||||
/* -------- AFEC_WPSR : (AFEC Offset: 0xE8) ( R/ 32) AFEC Write Protection Status Register -------- */
|
||||
#define AFEC_WPSR_WPVS_Pos _U_(0) /**< (AFEC_WPSR) Write Protect Violation Status Position */
|
||||
#define AFEC_WPSR_WPVS_Msk (_U_(0x1) << AFEC_WPSR_WPVS_Pos) /**< (AFEC_WPSR) Write Protect Violation Status Mask */
|
||||
#define AFEC_WPSR_WPVS(value) (AFEC_WPSR_WPVS_Msk & ((value) << AFEC_WPSR_WPVS_Pos))
|
||||
#define AFEC_WPSR_WPVSRC_Pos _U_(8) /**< (AFEC_WPSR) Write Protect Violation Source Position */
|
||||
#define AFEC_WPSR_WPVSRC_Msk (_U_(0xFFFF) << AFEC_WPSR_WPVSRC_Pos) /**< (AFEC_WPSR) Write Protect Violation Source Mask */
|
||||
#define AFEC_WPSR_WPVSRC(value) (AFEC_WPSR_WPVSRC_Msk & ((value) << AFEC_WPSR_WPVSRC_Pos))
|
||||
#define AFEC_WPSR_Msk _U_(0x00FFFF01) /**< (AFEC_WPSR) Register Mask */
|
||||
|
||||
|
||||
/** \brief AFEC register offsets definitions */
|
||||
#define AFEC_CR_REG_OFST (0x00) /**< (AFEC_CR) AFEC Control Register Offset */
|
||||
#define AFEC_MR_REG_OFST (0x04) /**< (AFEC_MR) AFEC Mode Register Offset */
|
||||
#define AFEC_EMR_REG_OFST (0x08) /**< (AFEC_EMR) AFEC Extended Mode Register Offset */
|
||||
#define AFEC_SEQ1R_REG_OFST (0x0C) /**< (AFEC_SEQ1R) AFEC Channel Sequence 1 Register Offset */
|
||||
#define AFEC_SEQ2R_REG_OFST (0x10) /**< (AFEC_SEQ2R) AFEC Channel Sequence 2 Register Offset */
|
||||
#define AFEC_CHER_REG_OFST (0x14) /**< (AFEC_CHER) AFEC Channel Enable Register Offset */
|
||||
#define AFEC_CHDR_REG_OFST (0x18) /**< (AFEC_CHDR) AFEC Channel Disable Register Offset */
|
||||
#define AFEC_CHSR_REG_OFST (0x1C) /**< (AFEC_CHSR) AFEC Channel Status Register Offset */
|
||||
#define AFEC_LCDR_REG_OFST (0x20) /**< (AFEC_LCDR) AFEC Last Converted Data Register Offset */
|
||||
#define AFEC_IER_REG_OFST (0x24) /**< (AFEC_IER) AFEC Interrupt Enable Register Offset */
|
||||
#define AFEC_IDR_REG_OFST (0x28) /**< (AFEC_IDR) AFEC Interrupt Disable Register Offset */
|
||||
#define AFEC_IMR_REG_OFST (0x2C) /**< (AFEC_IMR) AFEC Interrupt Mask Register Offset */
|
||||
#define AFEC_ISR_REG_OFST (0x30) /**< (AFEC_ISR) AFEC Interrupt Status Register Offset */
|
||||
#define AFEC_OVER_REG_OFST (0x4C) /**< (AFEC_OVER) AFEC Overrun Status Register Offset */
|
||||
#define AFEC_CWR_REG_OFST (0x50) /**< (AFEC_CWR) AFEC Compare Window Register Offset */
|
||||
#define AFEC_CGR_REG_OFST (0x54) /**< (AFEC_CGR) AFEC Channel Gain Register Offset */
|
||||
#define AFEC_DIFFR_REG_OFST (0x60) /**< (AFEC_DIFFR) AFEC Channel Differential Register Offset */
|
||||
#define AFEC_CSELR_REG_OFST (0x64) /**< (AFEC_CSELR) AFEC Channel Selection Register Offset */
|
||||
#define AFEC_CDR_REG_OFST (0x68) /**< (AFEC_CDR) AFEC Channel Data Register Offset */
|
||||
#define AFEC_COCR_REG_OFST (0x6C) /**< (AFEC_COCR) AFEC Channel Offset Compensation Register Offset */
|
||||
#define AFEC_TEMPMR_REG_OFST (0x70) /**< (AFEC_TEMPMR) AFEC Temperature Sensor Mode Register Offset */
|
||||
#define AFEC_TEMPCWR_REG_OFST (0x74) /**< (AFEC_TEMPCWR) AFEC Temperature Compare Window Register Offset */
|
||||
#define AFEC_ACR_REG_OFST (0x94) /**< (AFEC_ACR) AFEC Analog Control Register Offset */
|
||||
#define AFEC_SHMR_REG_OFST (0xA0) /**< (AFEC_SHMR) AFEC Sample & Hold Mode Register Offset */
|
||||
#define AFEC_COSR_REG_OFST (0xD0) /**< (AFEC_COSR) AFEC Correction Select Register Offset */
|
||||
#define AFEC_CVR_REG_OFST (0xD4) /**< (AFEC_CVR) AFEC Correction Values Register Offset */
|
||||
#define AFEC_CECR_REG_OFST (0xD8) /**< (AFEC_CECR) AFEC Channel Error Correction Register Offset */
|
||||
#define AFEC_WPMR_REG_OFST (0xE4) /**< (AFEC_WPMR) AFEC Write Protection Mode Register Offset */
|
||||
#define AFEC_WPSR_REG_OFST (0xE8) /**< (AFEC_WPSR) AFEC Write Protection Status Register Offset */
|
||||
|
||||
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
/** \brief AFEC register API structure */
|
||||
typedef struct
|
||||
{
|
||||
__O uint32_t AFEC_CR; /**< Offset: 0x00 ( /W 32) AFEC Control Register */
|
||||
__IO uint32_t AFEC_MR; /**< Offset: 0x04 (R/W 32) AFEC Mode Register */
|
||||
__IO uint32_t AFEC_EMR; /**< Offset: 0x08 (R/W 32) AFEC Extended Mode Register */
|
||||
__IO uint32_t AFEC_SEQ1R; /**< Offset: 0x0C (R/W 32) AFEC Channel Sequence 1 Register */
|
||||
__IO uint32_t AFEC_SEQ2R; /**< Offset: 0x10 (R/W 32) AFEC Channel Sequence 2 Register */
|
||||
__O uint32_t AFEC_CHER; /**< Offset: 0x14 ( /W 32) AFEC Channel Enable Register */
|
||||
__O uint32_t AFEC_CHDR; /**< Offset: 0x18 ( /W 32) AFEC Channel Disable Register */
|
||||
__I uint32_t AFEC_CHSR; /**< Offset: 0x1C (R/ 32) AFEC Channel Status Register */
|
||||
__I uint32_t AFEC_LCDR; /**< Offset: 0x20 (R/ 32) AFEC Last Converted Data Register */
|
||||
__O uint32_t AFEC_IER; /**< Offset: 0x24 ( /W 32) AFEC Interrupt Enable Register */
|
||||
__O uint32_t AFEC_IDR; /**< Offset: 0x28 ( /W 32) AFEC Interrupt Disable Register */
|
||||
__I uint32_t AFEC_IMR; /**< Offset: 0x2C (R/ 32) AFEC Interrupt Mask Register */
|
||||
__I uint32_t AFEC_ISR; /**< Offset: 0x30 (R/ 32) AFEC Interrupt Status Register */
|
||||
__I uint8_t Reserved1[0x18];
|
||||
__I uint32_t AFEC_OVER; /**< Offset: 0x4C (R/ 32) AFEC Overrun Status Register */
|
||||
__IO uint32_t AFEC_CWR; /**< Offset: 0x50 (R/W 32) AFEC Compare Window Register */
|
||||
__IO uint32_t AFEC_CGR; /**< Offset: 0x54 (R/W 32) AFEC Channel Gain Register */
|
||||
__I uint8_t Reserved2[0x08];
|
||||
__IO uint32_t AFEC_DIFFR; /**< Offset: 0x60 (R/W 32) AFEC Channel Differential Register */
|
||||
__IO uint32_t AFEC_CSELR; /**< Offset: 0x64 (R/W 32) AFEC Channel Selection Register */
|
||||
__I uint32_t AFEC_CDR; /**< Offset: 0x68 (R/ 32) AFEC Channel Data Register */
|
||||
__IO uint32_t AFEC_COCR; /**< Offset: 0x6C (R/W 32) AFEC Channel Offset Compensation Register */
|
||||
__IO uint32_t AFEC_TEMPMR; /**< Offset: 0x70 (R/W 32) AFEC Temperature Sensor Mode Register */
|
||||
__IO uint32_t AFEC_TEMPCWR; /**< Offset: 0x74 (R/W 32) AFEC Temperature Compare Window Register */
|
||||
__I uint8_t Reserved3[0x1C];
|
||||
__IO uint32_t AFEC_ACR; /**< Offset: 0x94 (R/W 32) AFEC Analog Control Register */
|
||||
__I uint8_t Reserved4[0x08];
|
||||
__IO uint32_t AFEC_SHMR; /**< Offset: 0xA0 (R/W 32) AFEC Sample & Hold Mode Register */
|
||||
__I uint8_t Reserved5[0x2C];
|
||||
__IO uint32_t AFEC_COSR; /**< Offset: 0xD0 (R/W 32) AFEC Correction Select Register */
|
||||
__IO uint32_t AFEC_CVR; /**< Offset: 0xD4 (R/W 32) AFEC Correction Values Register */
|
||||
__IO uint32_t AFEC_CECR; /**< Offset: 0xD8 (R/W 32) AFEC Channel Error Correction Register */
|
||||
__I uint8_t Reserved6[0x08];
|
||||
__IO uint32_t AFEC_WPMR; /**< Offset: 0xE4 (R/W 32) AFEC Write Protection Mode Register */
|
||||
__I uint32_t AFEC_WPSR; /**< Offset: 0xE8 (R/ 32) AFEC Write Protection Status Register */
|
||||
} afec_registers_t;
|
||||
|
||||
|
||||
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
#endif /* _SAME70_AFEC_COMPONENT_H_ */
|
||||
@ -0,0 +1,188 @@
|
||||
/**
|
||||
* \brief Component description for CHIPID
|
||||
*
|
||||
* Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries.
|
||||
*
|
||||
* Subject to your compliance with these terms, you may use Microchip software and any derivatives
|
||||
* exclusively with Microchip products. It is your responsibility to comply with third party license
|
||||
* terms applicable to your use of third party software (including open source software) that may
|
||||
* accompany Microchip software.
|
||||
*
|
||||
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY,
|
||||
* APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND
|
||||
* FITNESS FOR A PARTICULAR PURPOSE.
|
||||
*
|
||||
* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
|
||||
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF
|
||||
* MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
|
||||
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT
|
||||
* EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
|
||||
*
|
||||
*/
|
||||
|
||||
/* file generated from device description version 2017-08-25T14:00:00Z */
|
||||
#ifndef _SAME70_CHIPID_COMPONENT_H_
|
||||
#define _SAME70_CHIPID_COMPONENT_H_
|
||||
|
||||
/* ************************************************************************** */
|
||||
/* SOFTWARE API DEFINITION FOR CHIPID */
|
||||
/* ************************************************************************** */
|
||||
|
||||
/* -------- CHIPID_CIDR : (CHIPID Offset: 0x00) ( R/ 32) Chip ID Register -------- */
|
||||
#define CHIPID_CIDR_VERSION_Pos _U_(0) /**< (CHIPID_CIDR) Version of the Device Position */
|
||||
#define CHIPID_CIDR_VERSION_Msk (_U_(0x1F) << CHIPID_CIDR_VERSION_Pos) /**< (CHIPID_CIDR) Version of the Device Mask */
|
||||
#define CHIPID_CIDR_VERSION(value) (CHIPID_CIDR_VERSION_Msk & ((value) << CHIPID_CIDR_VERSION_Pos))
|
||||
#define CHIPID_CIDR_EPROC_Pos _U_(5) /**< (CHIPID_CIDR) Embedded Processor Position */
|
||||
#define CHIPID_CIDR_EPROC_Msk (_U_(0x7) << CHIPID_CIDR_EPROC_Pos) /**< (CHIPID_CIDR) Embedded Processor Mask */
|
||||
#define CHIPID_CIDR_EPROC(value) (CHIPID_CIDR_EPROC_Msk & ((value) << CHIPID_CIDR_EPROC_Pos))
|
||||
#define CHIPID_CIDR_EPROC_SAMx7_Val _U_(0x0) /**< (CHIPID_CIDR) Cortex-M7 */
|
||||
#define CHIPID_CIDR_EPROC_ARM946ES_Val _U_(0x1) /**< (CHIPID_CIDR) ARM946ES */
|
||||
#define CHIPID_CIDR_EPROC_ARM7TDMI_Val _U_(0x2) /**< (CHIPID_CIDR) ARM7TDMI */
|
||||
#define CHIPID_CIDR_EPROC_CM3_Val _U_(0x3) /**< (CHIPID_CIDR) Cortex-M3 */
|
||||
#define CHIPID_CIDR_EPROC_ARM920T_Val _U_(0x4) /**< (CHIPID_CIDR) ARM920T */
|
||||
#define CHIPID_CIDR_EPROC_ARM926EJS_Val _U_(0x5) /**< (CHIPID_CIDR) ARM926EJS */
|
||||
#define CHIPID_CIDR_EPROC_CA5_Val _U_(0x6) /**< (CHIPID_CIDR) Cortex-A5 */
|
||||
#define CHIPID_CIDR_EPROC_CM4_Val _U_(0x7) /**< (CHIPID_CIDR) Cortex-M4 */
|
||||
#define CHIPID_CIDR_EPROC_SAMx7 (CHIPID_CIDR_EPROC_SAMx7_Val << CHIPID_CIDR_EPROC_Pos) /**< (CHIPID_CIDR) Cortex-M7 Position */
|
||||
#define CHIPID_CIDR_EPROC_ARM946ES (CHIPID_CIDR_EPROC_ARM946ES_Val << CHIPID_CIDR_EPROC_Pos) /**< (CHIPID_CIDR) ARM946ES Position */
|
||||
#define CHIPID_CIDR_EPROC_ARM7TDMI (CHIPID_CIDR_EPROC_ARM7TDMI_Val << CHIPID_CIDR_EPROC_Pos) /**< (CHIPID_CIDR) ARM7TDMI Position */
|
||||
#define CHIPID_CIDR_EPROC_CM3 (CHIPID_CIDR_EPROC_CM3_Val << CHIPID_CIDR_EPROC_Pos) /**< (CHIPID_CIDR) Cortex-M3 Position */
|
||||
#define CHIPID_CIDR_EPROC_ARM920T (CHIPID_CIDR_EPROC_ARM920T_Val << CHIPID_CIDR_EPROC_Pos) /**< (CHIPID_CIDR) ARM920T Position */
|
||||
#define CHIPID_CIDR_EPROC_ARM926EJS (CHIPID_CIDR_EPROC_ARM926EJS_Val << CHIPID_CIDR_EPROC_Pos) /**< (CHIPID_CIDR) ARM926EJS Position */
|
||||
#define CHIPID_CIDR_EPROC_CA5 (CHIPID_CIDR_EPROC_CA5_Val << CHIPID_CIDR_EPROC_Pos) /**< (CHIPID_CIDR) Cortex-A5 Position */
|
||||
#define CHIPID_CIDR_EPROC_CM4 (CHIPID_CIDR_EPROC_CM4_Val << CHIPID_CIDR_EPROC_Pos) /**< (CHIPID_CIDR) Cortex-M4 Position */
|
||||
#define CHIPID_CIDR_NVPSIZ_Pos _U_(8) /**< (CHIPID_CIDR) Nonvolatile Program Memory Size Position */
|
||||
#define CHIPID_CIDR_NVPSIZ_Msk (_U_(0xF) << CHIPID_CIDR_NVPSIZ_Pos) /**< (CHIPID_CIDR) Nonvolatile Program Memory Size Mask */
|
||||
#define CHIPID_CIDR_NVPSIZ(value) (CHIPID_CIDR_NVPSIZ_Msk & ((value) << CHIPID_CIDR_NVPSIZ_Pos))
|
||||
#define CHIPID_CIDR_NVPSIZ_NONE_Val _U_(0x0) /**< (CHIPID_CIDR) None */
|
||||
#define CHIPID_CIDR_NVPSIZ_8K_Val _U_(0x1) /**< (CHIPID_CIDR) 8 Kbytes */
|
||||
#define CHIPID_CIDR_NVPSIZ_16K_Val _U_(0x2) /**< (CHIPID_CIDR) 16 Kbytes */
|
||||
#define CHIPID_CIDR_NVPSIZ_32K_Val _U_(0x3) /**< (CHIPID_CIDR) 32 Kbytes */
|
||||
#define CHIPID_CIDR_NVPSIZ_64K_Val _U_(0x5) /**< (CHIPID_CIDR) 64 Kbytes */
|
||||
#define CHIPID_CIDR_NVPSIZ_128K_Val _U_(0x7) /**< (CHIPID_CIDR) 128 Kbytes */
|
||||
#define CHIPID_CIDR_NVPSIZ_160K_Val _U_(0x8) /**< (CHIPID_CIDR) 160 Kbytes */
|
||||
#define CHIPID_CIDR_NVPSIZ_256K_Val _U_(0x9) /**< (CHIPID_CIDR) 256 Kbytes */
|
||||
#define CHIPID_CIDR_NVPSIZ_512K_Val _U_(0xA) /**< (CHIPID_CIDR) 512 Kbytes */
|
||||
#define CHIPID_CIDR_NVPSIZ_1024K_Val _U_(0xC) /**< (CHIPID_CIDR) 1024 Kbytes */
|
||||
#define CHIPID_CIDR_NVPSIZ_2048K_Val _U_(0xE) /**< (CHIPID_CIDR) 2048 Kbytes */
|
||||
#define CHIPID_CIDR_NVPSIZ_NONE (CHIPID_CIDR_NVPSIZ_NONE_Val << CHIPID_CIDR_NVPSIZ_Pos) /**< (CHIPID_CIDR) None Position */
|
||||
#define CHIPID_CIDR_NVPSIZ_8K (CHIPID_CIDR_NVPSIZ_8K_Val << CHIPID_CIDR_NVPSIZ_Pos) /**< (CHIPID_CIDR) 8 Kbytes Position */
|
||||
#define CHIPID_CIDR_NVPSIZ_16K (CHIPID_CIDR_NVPSIZ_16K_Val << CHIPID_CIDR_NVPSIZ_Pos) /**< (CHIPID_CIDR) 16 Kbytes Position */
|
||||
#define CHIPID_CIDR_NVPSIZ_32K (CHIPID_CIDR_NVPSIZ_32K_Val << CHIPID_CIDR_NVPSIZ_Pos) /**< (CHIPID_CIDR) 32 Kbytes Position */
|
||||
#define CHIPID_CIDR_NVPSIZ_64K (CHIPID_CIDR_NVPSIZ_64K_Val << CHIPID_CIDR_NVPSIZ_Pos) /**< (CHIPID_CIDR) 64 Kbytes Position */
|
||||
#define CHIPID_CIDR_NVPSIZ_128K (CHIPID_CIDR_NVPSIZ_128K_Val << CHIPID_CIDR_NVPSIZ_Pos) /**< (CHIPID_CIDR) 128 Kbytes Position */
|
||||
#define CHIPID_CIDR_NVPSIZ_160K (CHIPID_CIDR_NVPSIZ_160K_Val << CHIPID_CIDR_NVPSIZ_Pos) /**< (CHIPID_CIDR) 160 Kbytes Position */
|
||||
#define CHIPID_CIDR_NVPSIZ_256K (CHIPID_CIDR_NVPSIZ_256K_Val << CHIPID_CIDR_NVPSIZ_Pos) /**< (CHIPID_CIDR) 256 Kbytes Position */
|
||||
#define CHIPID_CIDR_NVPSIZ_512K (CHIPID_CIDR_NVPSIZ_512K_Val << CHIPID_CIDR_NVPSIZ_Pos) /**< (CHIPID_CIDR) 512 Kbytes Position */
|
||||
#define CHIPID_CIDR_NVPSIZ_1024K (CHIPID_CIDR_NVPSIZ_1024K_Val << CHIPID_CIDR_NVPSIZ_Pos) /**< (CHIPID_CIDR) 1024 Kbytes Position */
|
||||
#define CHIPID_CIDR_NVPSIZ_2048K (CHIPID_CIDR_NVPSIZ_2048K_Val << CHIPID_CIDR_NVPSIZ_Pos) /**< (CHIPID_CIDR) 2048 Kbytes Position */
|
||||
#define CHIPID_CIDR_NVPSIZ2_Pos _U_(12) /**< (CHIPID_CIDR) Second Nonvolatile Program Memory Size Position */
|
||||
#define CHIPID_CIDR_NVPSIZ2_Msk (_U_(0xF) << CHIPID_CIDR_NVPSIZ2_Pos) /**< (CHIPID_CIDR) Second Nonvolatile Program Memory Size Mask */
|
||||
#define CHIPID_CIDR_NVPSIZ2(value) (CHIPID_CIDR_NVPSIZ2_Msk & ((value) << CHIPID_CIDR_NVPSIZ2_Pos))
|
||||
#define CHIPID_CIDR_NVPSIZ2_NONE_Val _U_(0x0) /**< (CHIPID_CIDR) None */
|
||||
#define CHIPID_CIDR_NVPSIZ2_8K_Val _U_(0x1) /**< (CHIPID_CIDR) 8 Kbytes */
|
||||
#define CHIPID_CIDR_NVPSIZ2_16K_Val _U_(0x2) /**< (CHIPID_CIDR) 16 Kbytes */
|
||||
#define CHIPID_CIDR_NVPSIZ2_32K_Val _U_(0x3) /**< (CHIPID_CIDR) 32 Kbytes */
|
||||
#define CHIPID_CIDR_NVPSIZ2_64K_Val _U_(0x5) /**< (CHIPID_CIDR) 64 Kbytes */
|
||||
#define CHIPID_CIDR_NVPSIZ2_128K_Val _U_(0x7) /**< (CHIPID_CIDR) 128 Kbytes */
|
||||
#define CHIPID_CIDR_NVPSIZ2_256K_Val _U_(0x9) /**< (CHIPID_CIDR) 256 Kbytes */
|
||||
#define CHIPID_CIDR_NVPSIZ2_512K_Val _U_(0xA) /**< (CHIPID_CIDR) 512 Kbytes */
|
||||
#define CHIPID_CIDR_NVPSIZ2_1024K_Val _U_(0xC) /**< (CHIPID_CIDR) 1024 Kbytes */
|
||||
#define CHIPID_CIDR_NVPSIZ2_2048K_Val _U_(0xE) /**< (CHIPID_CIDR) 2048 Kbytes */
|
||||
#define CHIPID_CIDR_NVPSIZ2_NONE (CHIPID_CIDR_NVPSIZ2_NONE_Val << CHIPID_CIDR_NVPSIZ2_Pos) /**< (CHIPID_CIDR) None Position */
|
||||
#define CHIPID_CIDR_NVPSIZ2_8K (CHIPID_CIDR_NVPSIZ2_8K_Val << CHIPID_CIDR_NVPSIZ2_Pos) /**< (CHIPID_CIDR) 8 Kbytes Position */
|
||||
#define CHIPID_CIDR_NVPSIZ2_16K (CHIPID_CIDR_NVPSIZ2_16K_Val << CHIPID_CIDR_NVPSIZ2_Pos) /**< (CHIPID_CIDR) 16 Kbytes Position */
|
||||
#define CHIPID_CIDR_NVPSIZ2_32K (CHIPID_CIDR_NVPSIZ2_32K_Val << CHIPID_CIDR_NVPSIZ2_Pos) /**< (CHIPID_CIDR) 32 Kbytes Position */
|
||||
#define CHIPID_CIDR_NVPSIZ2_64K (CHIPID_CIDR_NVPSIZ2_64K_Val << CHIPID_CIDR_NVPSIZ2_Pos) /**< (CHIPID_CIDR) 64 Kbytes Position */
|
||||
#define CHIPID_CIDR_NVPSIZ2_128K (CHIPID_CIDR_NVPSIZ2_128K_Val << CHIPID_CIDR_NVPSIZ2_Pos) /**< (CHIPID_CIDR) 128 Kbytes Position */
|
||||
#define CHIPID_CIDR_NVPSIZ2_256K (CHIPID_CIDR_NVPSIZ2_256K_Val << CHIPID_CIDR_NVPSIZ2_Pos) /**< (CHIPID_CIDR) 256 Kbytes Position */
|
||||
#define CHIPID_CIDR_NVPSIZ2_512K (CHIPID_CIDR_NVPSIZ2_512K_Val << CHIPID_CIDR_NVPSIZ2_Pos) /**< (CHIPID_CIDR) 512 Kbytes Position */
|
||||
#define CHIPID_CIDR_NVPSIZ2_1024K (CHIPID_CIDR_NVPSIZ2_1024K_Val << CHIPID_CIDR_NVPSIZ2_Pos) /**< (CHIPID_CIDR) 1024 Kbytes Position */
|
||||
#define CHIPID_CIDR_NVPSIZ2_2048K (CHIPID_CIDR_NVPSIZ2_2048K_Val << CHIPID_CIDR_NVPSIZ2_Pos) /**< (CHIPID_CIDR) 2048 Kbytes Position */
|
||||
#define CHIPID_CIDR_SRAMSIZ_Pos _U_(16) /**< (CHIPID_CIDR) Internal SRAM Size Position */
|
||||
#define CHIPID_CIDR_SRAMSIZ_Msk (_U_(0xF) << CHIPID_CIDR_SRAMSIZ_Pos) /**< (CHIPID_CIDR) Internal SRAM Size Mask */
|
||||
#define CHIPID_CIDR_SRAMSIZ(value) (CHIPID_CIDR_SRAMSIZ_Msk & ((value) << CHIPID_CIDR_SRAMSIZ_Pos))
|
||||
#define CHIPID_CIDR_SRAMSIZ_48K_Val _U_(0x0) /**< (CHIPID_CIDR) 48 Kbytes */
|
||||
#define CHIPID_CIDR_SRAMSIZ_192K_Val _U_(0x1) /**< (CHIPID_CIDR) 192 Kbytes */
|
||||
#define CHIPID_CIDR_SRAMSIZ_384K_Val _U_(0x2) /**< (CHIPID_CIDR) 384 Kbytes */
|
||||
#define CHIPID_CIDR_SRAMSIZ_6K_Val _U_(0x3) /**< (CHIPID_CIDR) 6 Kbytes */
|
||||
#define CHIPID_CIDR_SRAMSIZ_24K_Val _U_(0x4) /**< (CHIPID_CIDR) 24 Kbytes */
|
||||
#define CHIPID_CIDR_SRAMSIZ_4K_Val _U_(0x5) /**< (CHIPID_CIDR) 4 Kbytes */
|
||||
#define CHIPID_CIDR_SRAMSIZ_80K_Val _U_(0x6) /**< (CHIPID_CIDR) 80 Kbytes */
|
||||
#define CHIPID_CIDR_SRAMSIZ_160K_Val _U_(0x7) /**< (CHIPID_CIDR) 160 Kbytes */
|
||||
#define CHIPID_CIDR_SRAMSIZ_8K_Val _U_(0x8) /**< (CHIPID_CIDR) 8 Kbytes */
|
||||
#define CHIPID_CIDR_SRAMSIZ_16K_Val _U_(0x9) /**< (CHIPID_CIDR) 16 Kbytes */
|
||||
#define CHIPID_CIDR_SRAMSIZ_32K_Val _U_(0xA) /**< (CHIPID_CIDR) 32 Kbytes */
|
||||
#define CHIPID_CIDR_SRAMSIZ_64K_Val _U_(0xB) /**< (CHIPID_CIDR) 64 Kbytes */
|
||||
#define CHIPID_CIDR_SRAMSIZ_128K_Val _U_(0xC) /**< (CHIPID_CIDR) 128 Kbytes */
|
||||
#define CHIPID_CIDR_SRAMSIZ_256K_Val _U_(0xD) /**< (CHIPID_CIDR) 256 Kbytes */
|
||||
#define CHIPID_CIDR_SRAMSIZ_96K_Val _U_(0xE) /**< (CHIPID_CIDR) 96 Kbytes */
|
||||
#define CHIPID_CIDR_SRAMSIZ_512K_Val _U_(0xF) /**< (CHIPID_CIDR) 512 Kbytes */
|
||||
#define CHIPID_CIDR_SRAMSIZ_48K (CHIPID_CIDR_SRAMSIZ_48K_Val << CHIPID_CIDR_SRAMSIZ_Pos) /**< (CHIPID_CIDR) 48 Kbytes Position */
|
||||
#define CHIPID_CIDR_SRAMSIZ_192K (CHIPID_CIDR_SRAMSIZ_192K_Val << CHIPID_CIDR_SRAMSIZ_Pos) /**< (CHIPID_CIDR) 192 Kbytes Position */
|
||||
#define CHIPID_CIDR_SRAMSIZ_384K (CHIPID_CIDR_SRAMSIZ_384K_Val << CHIPID_CIDR_SRAMSIZ_Pos) /**< (CHIPID_CIDR) 384 Kbytes Position */
|
||||
#define CHIPID_CIDR_SRAMSIZ_6K (CHIPID_CIDR_SRAMSIZ_6K_Val << CHIPID_CIDR_SRAMSIZ_Pos) /**< (CHIPID_CIDR) 6 Kbytes Position */
|
||||
#define CHIPID_CIDR_SRAMSIZ_24K (CHIPID_CIDR_SRAMSIZ_24K_Val << CHIPID_CIDR_SRAMSIZ_Pos) /**< (CHIPID_CIDR) 24 Kbytes Position */
|
||||
#define CHIPID_CIDR_SRAMSIZ_4K (CHIPID_CIDR_SRAMSIZ_4K_Val << CHIPID_CIDR_SRAMSIZ_Pos) /**< (CHIPID_CIDR) 4 Kbytes Position */
|
||||
#define CHIPID_CIDR_SRAMSIZ_80K (CHIPID_CIDR_SRAMSIZ_80K_Val << CHIPID_CIDR_SRAMSIZ_Pos) /**< (CHIPID_CIDR) 80 Kbytes Position */
|
||||
#define CHIPID_CIDR_SRAMSIZ_160K (CHIPID_CIDR_SRAMSIZ_160K_Val << CHIPID_CIDR_SRAMSIZ_Pos) /**< (CHIPID_CIDR) 160 Kbytes Position */
|
||||
#define CHIPID_CIDR_SRAMSIZ_8K (CHIPID_CIDR_SRAMSIZ_8K_Val << CHIPID_CIDR_SRAMSIZ_Pos) /**< (CHIPID_CIDR) 8 Kbytes Position */
|
||||
#define CHIPID_CIDR_SRAMSIZ_16K (CHIPID_CIDR_SRAMSIZ_16K_Val << CHIPID_CIDR_SRAMSIZ_Pos) /**< (CHIPID_CIDR) 16 Kbytes Position */
|
||||
#define CHIPID_CIDR_SRAMSIZ_32K (CHIPID_CIDR_SRAMSIZ_32K_Val << CHIPID_CIDR_SRAMSIZ_Pos) /**< (CHIPID_CIDR) 32 Kbytes Position */
|
||||
#define CHIPID_CIDR_SRAMSIZ_64K (CHIPID_CIDR_SRAMSIZ_64K_Val << CHIPID_CIDR_SRAMSIZ_Pos) /**< (CHIPID_CIDR) 64 Kbytes Position */
|
||||
#define CHIPID_CIDR_SRAMSIZ_128K (CHIPID_CIDR_SRAMSIZ_128K_Val << CHIPID_CIDR_SRAMSIZ_Pos) /**< (CHIPID_CIDR) 128 Kbytes Position */
|
||||
#define CHIPID_CIDR_SRAMSIZ_256K (CHIPID_CIDR_SRAMSIZ_256K_Val << CHIPID_CIDR_SRAMSIZ_Pos) /**< (CHIPID_CIDR) 256 Kbytes Position */
|
||||
#define CHIPID_CIDR_SRAMSIZ_96K (CHIPID_CIDR_SRAMSIZ_96K_Val << CHIPID_CIDR_SRAMSIZ_Pos) /**< (CHIPID_CIDR) 96 Kbytes Position */
|
||||
#define CHIPID_CIDR_SRAMSIZ_512K (CHIPID_CIDR_SRAMSIZ_512K_Val << CHIPID_CIDR_SRAMSIZ_Pos) /**< (CHIPID_CIDR) 512 Kbytes Position */
|
||||
#define CHIPID_CIDR_ARCH_Pos _U_(20) /**< (CHIPID_CIDR) Architecture Identifier Position */
|
||||
#define CHIPID_CIDR_ARCH_Msk (_U_(0xFF) << CHIPID_CIDR_ARCH_Pos) /**< (CHIPID_CIDR) Architecture Identifier Mask */
|
||||
#define CHIPID_CIDR_ARCH(value) (CHIPID_CIDR_ARCH_Msk & ((value) << CHIPID_CIDR_ARCH_Pos))
|
||||
#define CHIPID_CIDR_ARCH_SAME70_Val _U_(0x10) /**< (CHIPID_CIDR) SAM E70 */
|
||||
#define CHIPID_CIDR_ARCH_SAMS70_Val _U_(0x11) /**< (CHIPID_CIDR) SAM S70 */
|
||||
#define CHIPID_CIDR_ARCH_SAMV71_Val _U_(0x12) /**< (CHIPID_CIDR) SAM V71 */
|
||||
#define CHIPID_CIDR_ARCH_SAMV70_Val _U_(0x13) /**< (CHIPID_CIDR) SAM V70 */
|
||||
#define CHIPID_CIDR_ARCH_SAME70 (CHIPID_CIDR_ARCH_SAME70_Val << CHIPID_CIDR_ARCH_Pos) /**< (CHIPID_CIDR) SAM E70 Position */
|
||||
#define CHIPID_CIDR_ARCH_SAMS70 (CHIPID_CIDR_ARCH_SAMS70_Val << CHIPID_CIDR_ARCH_Pos) /**< (CHIPID_CIDR) SAM S70 Position */
|
||||
#define CHIPID_CIDR_ARCH_SAMV71 (CHIPID_CIDR_ARCH_SAMV71_Val << CHIPID_CIDR_ARCH_Pos) /**< (CHIPID_CIDR) SAM V71 Position */
|
||||
#define CHIPID_CIDR_ARCH_SAMV70 (CHIPID_CIDR_ARCH_SAMV70_Val << CHIPID_CIDR_ARCH_Pos) /**< (CHIPID_CIDR) SAM V70 Position */
|
||||
#define CHIPID_CIDR_NVPTYP_Pos _U_(28) /**< (CHIPID_CIDR) Nonvolatile Program Memory Type Position */
|
||||
#define CHIPID_CIDR_NVPTYP_Msk (_U_(0x7) << CHIPID_CIDR_NVPTYP_Pos) /**< (CHIPID_CIDR) Nonvolatile Program Memory Type Mask */
|
||||
#define CHIPID_CIDR_NVPTYP(value) (CHIPID_CIDR_NVPTYP_Msk & ((value) << CHIPID_CIDR_NVPTYP_Pos))
|
||||
#define CHIPID_CIDR_NVPTYP_ROM_Val _U_(0x0) /**< (CHIPID_CIDR) ROM */
|
||||
#define CHIPID_CIDR_NVPTYP_ROMLESS_Val _U_(0x1) /**< (CHIPID_CIDR) ROMless or on-chip Flash */
|
||||
#define CHIPID_CIDR_NVPTYP_FLASH_Val _U_(0x2) /**< (CHIPID_CIDR) Embedded Flash Memory */
|
||||
#define CHIPID_CIDR_NVPTYP_ROM_FLASH_Val _U_(0x3) /**< (CHIPID_CIDR) ROM and Embedded Flash Memory- NVPSIZ is ROM size- NVPSIZ2 is Flash size */
|
||||
#define CHIPID_CIDR_NVPTYP_SRAM_Val _U_(0x4) /**< (CHIPID_CIDR) SRAM emulating ROM */
|
||||
#define CHIPID_CIDR_NVPTYP_ROM (CHIPID_CIDR_NVPTYP_ROM_Val << CHIPID_CIDR_NVPTYP_Pos) /**< (CHIPID_CIDR) ROM Position */
|
||||
#define CHIPID_CIDR_NVPTYP_ROMLESS (CHIPID_CIDR_NVPTYP_ROMLESS_Val << CHIPID_CIDR_NVPTYP_Pos) /**< (CHIPID_CIDR) ROMless or on-chip Flash Position */
|
||||
#define CHIPID_CIDR_NVPTYP_FLASH (CHIPID_CIDR_NVPTYP_FLASH_Val << CHIPID_CIDR_NVPTYP_Pos) /**< (CHIPID_CIDR) Embedded Flash Memory Position */
|
||||
#define CHIPID_CIDR_NVPTYP_ROM_FLASH (CHIPID_CIDR_NVPTYP_ROM_FLASH_Val << CHIPID_CIDR_NVPTYP_Pos) /**< (CHIPID_CIDR) ROM and Embedded Flash Memory- NVPSIZ is ROM size- NVPSIZ2 is Flash size Position */
|
||||
#define CHIPID_CIDR_NVPTYP_SRAM (CHIPID_CIDR_NVPTYP_SRAM_Val << CHIPID_CIDR_NVPTYP_Pos) /**< (CHIPID_CIDR) SRAM emulating ROM Position */
|
||||
#define CHIPID_CIDR_EXT_Pos _U_(31) /**< (CHIPID_CIDR) Extension Flag Position */
|
||||
#define CHIPID_CIDR_EXT_Msk (_U_(0x1) << CHIPID_CIDR_EXT_Pos) /**< (CHIPID_CIDR) Extension Flag Mask */
|
||||
#define CHIPID_CIDR_EXT(value) (CHIPID_CIDR_EXT_Msk & ((value) << CHIPID_CIDR_EXT_Pos))
|
||||
#define CHIPID_CIDR_Msk _U_(0xFFFFFFFF) /**< (CHIPID_CIDR) Register Mask */
|
||||
|
||||
|
||||
/* -------- CHIPID_EXID : (CHIPID Offset: 0x04) ( R/ 32) Chip ID Extension Register -------- */
|
||||
#define CHIPID_EXID_EXID_Pos _U_(0) /**< (CHIPID_EXID) Chip ID Extension Position */
|
||||
#define CHIPID_EXID_EXID_Msk (_U_(0xFFFFFFFF) << CHIPID_EXID_EXID_Pos) /**< (CHIPID_EXID) Chip ID Extension Mask */
|
||||
#define CHIPID_EXID_EXID(value) (CHIPID_EXID_EXID_Msk & ((value) << CHIPID_EXID_EXID_Pos))
|
||||
#define CHIPID_EXID_Msk _U_(0xFFFFFFFF) /**< (CHIPID_EXID) Register Mask */
|
||||
|
||||
|
||||
/** \brief CHIPID register offsets definitions */
|
||||
#define CHIPID_CIDR_REG_OFST (0x00) /**< (CHIPID_CIDR) Chip ID Register Offset */
|
||||
#define CHIPID_EXID_REG_OFST (0x04) /**< (CHIPID_EXID) Chip ID Extension Register Offset */
|
||||
|
||||
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
/** \brief CHIPID register API structure */
|
||||
typedef struct
|
||||
{
|
||||
__I uint32_t CHIPID_CIDR; /**< Offset: 0x00 (R/ 32) Chip ID Register */
|
||||
__I uint32_t CHIPID_EXID; /**< Offset: 0x04 (R/ 32) Chip ID Extension Register */
|
||||
} chipid_registers_t;
|
||||
|
||||
|
||||
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
#endif /* _SAME70_CHIPID_COMPONENT_H_ */
|
||||
@ -0,0 +1,387 @@
|
||||
/**
|
||||
* \brief Component description for DACC
|
||||
*
|
||||
* Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries.
|
||||
*
|
||||
* Subject to your compliance with these terms, you may use Microchip software and any derivatives
|
||||
* exclusively with Microchip products. It is your responsibility to comply with third party license
|
||||
* terms applicable to your use of third party software (including open source software) that may
|
||||
* accompany Microchip software.
|
||||
*
|
||||
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY,
|
||||
* APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND
|
||||
* FITNESS FOR A PARTICULAR PURPOSE.
|
||||
*
|
||||
* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
|
||||
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF
|
||||
* MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
|
||||
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT
|
||||
* EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
|
||||
*
|
||||
*/
|
||||
|
||||
/* file generated from device description version 2017-08-25T14:00:00Z */
|
||||
#ifndef _SAME70_DACC_COMPONENT_H_
|
||||
#define _SAME70_DACC_COMPONENT_H_
|
||||
|
||||
/* ************************************************************************** */
|
||||
/* SOFTWARE API DEFINITION FOR DACC */
|
||||
/* ************************************************************************** */
|
||||
|
||||
/* -------- DACC_CR : (DACC Offset: 0x00) ( /W 32) Control Register -------- */
|
||||
#define DACC_CR_SWRST_Pos _U_(0) /**< (DACC_CR) Software Reset Position */
|
||||
#define DACC_CR_SWRST_Msk (_U_(0x1) << DACC_CR_SWRST_Pos) /**< (DACC_CR) Software Reset Mask */
|
||||
#define DACC_CR_SWRST(value) (DACC_CR_SWRST_Msk & ((value) << DACC_CR_SWRST_Pos))
|
||||
#define DACC_CR_Msk _U_(0x00000001) /**< (DACC_CR) Register Mask */
|
||||
|
||||
|
||||
/* -------- DACC_MR : (DACC Offset: 0x04) (R/W 32) Mode Register -------- */
|
||||
#define DACC_MR_MAXS0_Pos _U_(0) /**< (DACC_MR) Max Speed Mode for Channel 0 Position */
|
||||
#define DACC_MR_MAXS0_Msk (_U_(0x1) << DACC_MR_MAXS0_Pos) /**< (DACC_MR) Max Speed Mode for Channel 0 Mask */
|
||||
#define DACC_MR_MAXS0(value) (DACC_MR_MAXS0_Msk & ((value) << DACC_MR_MAXS0_Pos))
|
||||
#define DACC_MR_MAXS0_TRIG_EVENT_Val _U_(0x0) /**< (DACC_MR) External trigger mode or Free-running mode enabled. (See TRGENx.DACC_TRIGR.) */
|
||||
#define DACC_MR_MAXS0_MAXIMUM_Val _U_(0x1) /**< (DACC_MR) Max speed mode enabled. */
|
||||
#define DACC_MR_MAXS0_TRIG_EVENT (DACC_MR_MAXS0_TRIG_EVENT_Val << DACC_MR_MAXS0_Pos) /**< (DACC_MR) External trigger mode or Free-running mode enabled. (See TRGENx.DACC_TRIGR.) Position */
|
||||
#define DACC_MR_MAXS0_MAXIMUM (DACC_MR_MAXS0_MAXIMUM_Val << DACC_MR_MAXS0_Pos) /**< (DACC_MR) Max speed mode enabled. Position */
|
||||
#define DACC_MR_MAXS1_Pos _U_(1) /**< (DACC_MR) Max Speed Mode for Channel 1 Position */
|
||||
#define DACC_MR_MAXS1_Msk (_U_(0x1) << DACC_MR_MAXS1_Pos) /**< (DACC_MR) Max Speed Mode for Channel 1 Mask */
|
||||
#define DACC_MR_MAXS1(value) (DACC_MR_MAXS1_Msk & ((value) << DACC_MR_MAXS1_Pos))
|
||||
#define DACC_MR_MAXS1_TRIG_EVENT_Val _U_(0x0) /**< (DACC_MR) External trigger mode or Free-running mode enabled. (See TRGENx.DACC_TRIGR.) */
|
||||
#define DACC_MR_MAXS1_MAXIMUM_Val _U_(0x1) /**< (DACC_MR) Max speed mode enabled. */
|
||||
#define DACC_MR_MAXS1_TRIG_EVENT (DACC_MR_MAXS1_TRIG_EVENT_Val << DACC_MR_MAXS1_Pos) /**< (DACC_MR) External trigger mode or Free-running mode enabled. (See TRGENx.DACC_TRIGR.) Position */
|
||||
#define DACC_MR_MAXS1_MAXIMUM (DACC_MR_MAXS1_MAXIMUM_Val << DACC_MR_MAXS1_Pos) /**< (DACC_MR) Max speed mode enabled. Position */
|
||||
#define DACC_MR_WORD_Pos _U_(4) /**< (DACC_MR) Word Transfer Mode Position */
|
||||
#define DACC_MR_WORD_Msk (_U_(0x1) << DACC_MR_WORD_Pos) /**< (DACC_MR) Word Transfer Mode Mask */
|
||||
#define DACC_MR_WORD(value) (DACC_MR_WORD_Msk & ((value) << DACC_MR_WORD_Pos))
|
||||
#define DACC_MR_WORD_DISABLED_Val _U_(0x0) /**< (DACC_MR) One data to convert is written to the FIFO per access to DACC. */
|
||||
#define DACC_MR_WORD_ENABLED_Val _U_(0x1) /**< (DACC_MR) Two data to convert are written to the FIFO per access to DACC (reduces the number of requests to DMA and the number of system bus accesses). */
|
||||
#define DACC_MR_WORD_DISABLED (DACC_MR_WORD_DISABLED_Val << DACC_MR_WORD_Pos) /**< (DACC_MR) One data to convert is written to the FIFO per access to DACC. Position */
|
||||
#define DACC_MR_WORD_ENABLED (DACC_MR_WORD_ENABLED_Val << DACC_MR_WORD_Pos) /**< (DACC_MR) Two data to convert are written to the FIFO per access to DACC (reduces the number of requests to DMA and the number of system bus accesses). Position */
|
||||
#define DACC_MR_ZERO_Pos _U_(5) /**< (DACC_MR) Must always be written to 0. Position */
|
||||
#define DACC_MR_ZERO_Msk (_U_(0x1) << DACC_MR_ZERO_Pos) /**< (DACC_MR) Must always be written to 0. Mask */
|
||||
#define DACC_MR_ZERO(value) (DACC_MR_ZERO_Msk & ((value) << DACC_MR_ZERO_Pos))
|
||||
#define DACC_MR_DIFF_Pos _U_(23) /**< (DACC_MR) Differential Mode Position */
|
||||
#define DACC_MR_DIFF_Msk (_U_(0x1) << DACC_MR_DIFF_Pos) /**< (DACC_MR) Differential Mode Mask */
|
||||
#define DACC_MR_DIFF(value) (DACC_MR_DIFF_Msk & ((value) << DACC_MR_DIFF_Pos))
|
||||
#define DACC_MR_DIFF_DISABLED_Val _U_(0x0) /**< (DACC_MR) DAC0 and DAC1 are single-ended outputs. */
|
||||
#define DACC_MR_DIFF_ENABLED_Val _U_(0x1) /**< (DACC_MR) DACP and DACN are differential outputs. The differential level is configured by the channel 0 value. */
|
||||
#define DACC_MR_DIFF_DISABLED (DACC_MR_DIFF_DISABLED_Val << DACC_MR_DIFF_Pos) /**< (DACC_MR) DAC0 and DAC1 are single-ended outputs. Position */
|
||||
#define DACC_MR_DIFF_ENABLED (DACC_MR_DIFF_ENABLED_Val << DACC_MR_DIFF_Pos) /**< (DACC_MR) DACP and DACN are differential outputs. The differential level is configured by the channel 0 value. Position */
|
||||
#define DACC_MR_PRESCALER_Pos _U_(24) /**< (DACC_MR) Peripheral Clock to DAC Clock Ratio Position */
|
||||
#define DACC_MR_PRESCALER_Msk (_U_(0xF) << DACC_MR_PRESCALER_Pos) /**< (DACC_MR) Peripheral Clock to DAC Clock Ratio Mask */
|
||||
#define DACC_MR_PRESCALER(value) (DACC_MR_PRESCALER_Msk & ((value) << DACC_MR_PRESCALER_Pos))
|
||||
#define DACC_MR_Msk _U_(0x0F800033) /**< (DACC_MR) Register Mask */
|
||||
|
||||
#define DACC_MR_MAXS_Pos _U_(0) /**< (DACC_MR Position) Max Speed Mode for Channel x */
|
||||
#define DACC_MR_MAXS_Msk (_U_(0x3) << DACC_MR_MAXS_Pos) /**< (DACC_MR Mask) MAXS */
|
||||
#define DACC_MR_MAXS(value) (DACC_MR_MAXS_Msk & ((value) << DACC_MR_MAXS_Pos))
|
||||
|
||||
/* -------- DACC_TRIGR : (DACC Offset: 0x08) (R/W 32) Trigger Register -------- */
|
||||
#define DACC_TRIGR_TRGEN0_Pos _U_(0) /**< (DACC_TRIGR) Trigger Enable of Channel 0 Position */
|
||||
#define DACC_TRIGR_TRGEN0_Msk (_U_(0x1) << DACC_TRIGR_TRGEN0_Pos) /**< (DACC_TRIGR) Trigger Enable of Channel 0 Mask */
|
||||
#define DACC_TRIGR_TRGEN0(value) (DACC_TRIGR_TRGEN0_Msk & ((value) << DACC_TRIGR_TRGEN0_Pos))
|
||||
#define DACC_TRIGR_TRGEN0_DIS_Val _U_(0x0) /**< (DACC_TRIGR) External trigger mode disabled. DACC is in Free-running mode or Max speed mode. */
|
||||
#define DACC_TRIGR_TRGEN0_EN_Val _U_(0x1) /**< (DACC_TRIGR) External trigger mode enabled. */
|
||||
#define DACC_TRIGR_TRGEN0_DIS (DACC_TRIGR_TRGEN0_DIS_Val << DACC_TRIGR_TRGEN0_Pos) /**< (DACC_TRIGR) External trigger mode disabled. DACC is in Free-running mode or Max speed mode. Position */
|
||||
#define DACC_TRIGR_TRGEN0_EN (DACC_TRIGR_TRGEN0_EN_Val << DACC_TRIGR_TRGEN0_Pos) /**< (DACC_TRIGR) External trigger mode enabled. Position */
|
||||
#define DACC_TRIGR_TRGEN1_Pos _U_(1) /**< (DACC_TRIGR) Trigger Enable of Channel 1 Position */
|
||||
#define DACC_TRIGR_TRGEN1_Msk (_U_(0x1) << DACC_TRIGR_TRGEN1_Pos) /**< (DACC_TRIGR) Trigger Enable of Channel 1 Mask */
|
||||
#define DACC_TRIGR_TRGEN1(value) (DACC_TRIGR_TRGEN1_Msk & ((value) << DACC_TRIGR_TRGEN1_Pos))
|
||||
#define DACC_TRIGR_TRGEN1_DIS_Val _U_(0x0) /**< (DACC_TRIGR) External trigger mode disabled. DACC is in Free-running mode or Max speed mode. */
|
||||
#define DACC_TRIGR_TRGEN1_EN_Val _U_(0x1) /**< (DACC_TRIGR) External trigger mode enabled. */
|
||||
#define DACC_TRIGR_TRGEN1_DIS (DACC_TRIGR_TRGEN1_DIS_Val << DACC_TRIGR_TRGEN1_Pos) /**< (DACC_TRIGR) External trigger mode disabled. DACC is in Free-running mode or Max speed mode. Position */
|
||||
#define DACC_TRIGR_TRGEN1_EN (DACC_TRIGR_TRGEN1_EN_Val << DACC_TRIGR_TRGEN1_Pos) /**< (DACC_TRIGR) External trigger mode enabled. Position */
|
||||
#define DACC_TRIGR_TRGSEL0_Pos _U_(4) /**< (DACC_TRIGR) Trigger Selection of Channel 0 Position */
|
||||
#define DACC_TRIGR_TRGSEL0_Msk (_U_(0x7) << DACC_TRIGR_TRGSEL0_Pos) /**< (DACC_TRIGR) Trigger Selection of Channel 0 Mask */
|
||||
#define DACC_TRIGR_TRGSEL0(value) (DACC_TRIGR_TRGSEL0_Msk & ((value) << DACC_TRIGR_TRGSEL0_Pos))
|
||||
#define DACC_TRIGR_TRGSEL0_TRGSEL0_Val _U_(0x0) /**< (DACC_TRIGR) DATRG */
|
||||
#define DACC_TRIGR_TRGSEL0_TRGSEL1_Val _U_(0x1) /**< (DACC_TRIGR) TC0 output */
|
||||
#define DACC_TRIGR_TRGSEL0_TRGSEL2_Val _U_(0x2) /**< (DACC_TRIGR) TC1 output */
|
||||
#define DACC_TRIGR_TRGSEL0_TRGSEL3_Val _U_(0x3) /**< (DACC_TRIGR) TC2 output */
|
||||
#define DACC_TRIGR_TRGSEL0_TRGSEL4_Val _U_(0x4) /**< (DACC_TRIGR) PWM0 event 0 */
|
||||
#define DACC_TRIGR_TRGSEL0_TRGSEL5_Val _U_(0x5) /**< (DACC_TRIGR) PWM0 event 1 */
|
||||
#define DACC_TRIGR_TRGSEL0_TRGSEL6_Val _U_(0x6) /**< (DACC_TRIGR) PWM1 event 0 */
|
||||
#define DACC_TRIGR_TRGSEL0_TRGSEL7_Val _U_(0x7) /**< (DACC_TRIGR) PWM1 event 1 */
|
||||
#define DACC_TRIGR_TRGSEL0_TRGSEL0 (DACC_TRIGR_TRGSEL0_TRGSEL0_Val << DACC_TRIGR_TRGSEL0_Pos) /**< (DACC_TRIGR) DATRG Position */
|
||||
#define DACC_TRIGR_TRGSEL0_TRGSEL1 (DACC_TRIGR_TRGSEL0_TRGSEL1_Val << DACC_TRIGR_TRGSEL0_Pos) /**< (DACC_TRIGR) TC0 output Position */
|
||||
#define DACC_TRIGR_TRGSEL0_TRGSEL2 (DACC_TRIGR_TRGSEL0_TRGSEL2_Val << DACC_TRIGR_TRGSEL0_Pos) /**< (DACC_TRIGR) TC1 output Position */
|
||||
#define DACC_TRIGR_TRGSEL0_TRGSEL3 (DACC_TRIGR_TRGSEL0_TRGSEL3_Val << DACC_TRIGR_TRGSEL0_Pos) /**< (DACC_TRIGR) TC2 output Position */
|
||||
#define DACC_TRIGR_TRGSEL0_TRGSEL4 (DACC_TRIGR_TRGSEL0_TRGSEL4_Val << DACC_TRIGR_TRGSEL0_Pos) /**< (DACC_TRIGR) PWM0 event 0 Position */
|
||||
#define DACC_TRIGR_TRGSEL0_TRGSEL5 (DACC_TRIGR_TRGSEL0_TRGSEL5_Val << DACC_TRIGR_TRGSEL0_Pos) /**< (DACC_TRIGR) PWM0 event 1 Position */
|
||||
#define DACC_TRIGR_TRGSEL0_TRGSEL6 (DACC_TRIGR_TRGSEL0_TRGSEL6_Val << DACC_TRIGR_TRGSEL0_Pos) /**< (DACC_TRIGR) PWM1 event 0 Position */
|
||||
#define DACC_TRIGR_TRGSEL0_TRGSEL7 (DACC_TRIGR_TRGSEL0_TRGSEL7_Val << DACC_TRIGR_TRGSEL0_Pos) /**< (DACC_TRIGR) PWM1 event 1 Position */
|
||||
#define DACC_TRIGR_TRGSEL1_Pos _U_(8) /**< (DACC_TRIGR) Trigger Selection of Channel 1 Position */
|
||||
#define DACC_TRIGR_TRGSEL1_Msk (_U_(0x7) << DACC_TRIGR_TRGSEL1_Pos) /**< (DACC_TRIGR) Trigger Selection of Channel 1 Mask */
|
||||
#define DACC_TRIGR_TRGSEL1(value) (DACC_TRIGR_TRGSEL1_Msk & ((value) << DACC_TRIGR_TRGSEL1_Pos))
|
||||
#define DACC_TRIGR_TRGSEL1_TRGSEL0_Val _U_(0x0) /**< (DACC_TRIGR) DATRG */
|
||||
#define DACC_TRIGR_TRGSEL1_TRGSEL1_Val _U_(0x1) /**< (DACC_TRIGR) TC0 output */
|
||||
#define DACC_TRIGR_TRGSEL1_TRGSEL2_Val _U_(0x2) /**< (DACC_TRIGR) TC1 output */
|
||||
#define DACC_TRIGR_TRGSEL1_TRGSEL3_Val _U_(0x3) /**< (DACC_TRIGR) TC2 output */
|
||||
#define DACC_TRIGR_TRGSEL1_TRGSEL4_Val _U_(0x4) /**< (DACC_TRIGR) PWM0 event 0 */
|
||||
#define DACC_TRIGR_TRGSEL1_TRGSEL5_Val _U_(0x5) /**< (DACC_TRIGR) PWM0 event 1 */
|
||||
#define DACC_TRIGR_TRGSEL1_TRGSEL6_Val _U_(0x6) /**< (DACC_TRIGR) PWM1 event 0 */
|
||||
#define DACC_TRIGR_TRGSEL1_TRGSEL7_Val _U_(0x7) /**< (DACC_TRIGR) PWM1 event 1 */
|
||||
#define DACC_TRIGR_TRGSEL1_TRGSEL0 (DACC_TRIGR_TRGSEL1_TRGSEL0_Val << DACC_TRIGR_TRGSEL1_Pos) /**< (DACC_TRIGR) DATRG Position */
|
||||
#define DACC_TRIGR_TRGSEL1_TRGSEL1 (DACC_TRIGR_TRGSEL1_TRGSEL1_Val << DACC_TRIGR_TRGSEL1_Pos) /**< (DACC_TRIGR) TC0 output Position */
|
||||
#define DACC_TRIGR_TRGSEL1_TRGSEL2 (DACC_TRIGR_TRGSEL1_TRGSEL2_Val << DACC_TRIGR_TRGSEL1_Pos) /**< (DACC_TRIGR) TC1 output Position */
|
||||
#define DACC_TRIGR_TRGSEL1_TRGSEL3 (DACC_TRIGR_TRGSEL1_TRGSEL3_Val << DACC_TRIGR_TRGSEL1_Pos) /**< (DACC_TRIGR) TC2 output Position */
|
||||
#define DACC_TRIGR_TRGSEL1_TRGSEL4 (DACC_TRIGR_TRGSEL1_TRGSEL4_Val << DACC_TRIGR_TRGSEL1_Pos) /**< (DACC_TRIGR) PWM0 event 0 Position */
|
||||
#define DACC_TRIGR_TRGSEL1_TRGSEL5 (DACC_TRIGR_TRGSEL1_TRGSEL5_Val << DACC_TRIGR_TRGSEL1_Pos) /**< (DACC_TRIGR) PWM0 event 1 Position */
|
||||
#define DACC_TRIGR_TRGSEL1_TRGSEL6 (DACC_TRIGR_TRGSEL1_TRGSEL6_Val << DACC_TRIGR_TRGSEL1_Pos) /**< (DACC_TRIGR) PWM1 event 0 Position */
|
||||
#define DACC_TRIGR_TRGSEL1_TRGSEL7 (DACC_TRIGR_TRGSEL1_TRGSEL7_Val << DACC_TRIGR_TRGSEL1_Pos) /**< (DACC_TRIGR) PWM1 event 1 Position */
|
||||
#define DACC_TRIGR_OSR0_Pos _U_(16) /**< (DACC_TRIGR) Over Sampling Ratio of Channel 0 Position */
|
||||
#define DACC_TRIGR_OSR0_Msk (_U_(0x7) << DACC_TRIGR_OSR0_Pos) /**< (DACC_TRIGR) Over Sampling Ratio of Channel 0 Mask */
|
||||
#define DACC_TRIGR_OSR0(value) (DACC_TRIGR_OSR0_Msk & ((value) << DACC_TRIGR_OSR0_Pos))
|
||||
#define DACC_TRIGR_OSR0_OSR_1_Val _U_(0x0) /**< (DACC_TRIGR) OSR = 1 */
|
||||
#define DACC_TRIGR_OSR0_OSR_2_Val _U_(0x1) /**< (DACC_TRIGR) OSR = 2 */
|
||||
#define DACC_TRIGR_OSR0_OSR_4_Val _U_(0x2) /**< (DACC_TRIGR) OSR = 4 */
|
||||
#define DACC_TRIGR_OSR0_OSR_8_Val _U_(0x3) /**< (DACC_TRIGR) OSR = 8 */
|
||||
#define DACC_TRIGR_OSR0_OSR_16_Val _U_(0x4) /**< (DACC_TRIGR) OSR = 16 */
|
||||
#define DACC_TRIGR_OSR0_OSR_32_Val _U_(0x5) /**< (DACC_TRIGR) OSR = 32 */
|
||||
#define DACC_TRIGR_OSR0_OSR_1 (DACC_TRIGR_OSR0_OSR_1_Val << DACC_TRIGR_OSR0_Pos) /**< (DACC_TRIGR) OSR = 1 Position */
|
||||
#define DACC_TRIGR_OSR0_OSR_2 (DACC_TRIGR_OSR0_OSR_2_Val << DACC_TRIGR_OSR0_Pos) /**< (DACC_TRIGR) OSR = 2 Position */
|
||||
#define DACC_TRIGR_OSR0_OSR_4 (DACC_TRIGR_OSR0_OSR_4_Val << DACC_TRIGR_OSR0_Pos) /**< (DACC_TRIGR) OSR = 4 Position */
|
||||
#define DACC_TRIGR_OSR0_OSR_8 (DACC_TRIGR_OSR0_OSR_8_Val << DACC_TRIGR_OSR0_Pos) /**< (DACC_TRIGR) OSR = 8 Position */
|
||||
#define DACC_TRIGR_OSR0_OSR_16 (DACC_TRIGR_OSR0_OSR_16_Val << DACC_TRIGR_OSR0_Pos) /**< (DACC_TRIGR) OSR = 16 Position */
|
||||
#define DACC_TRIGR_OSR0_OSR_32 (DACC_TRIGR_OSR0_OSR_32_Val << DACC_TRIGR_OSR0_Pos) /**< (DACC_TRIGR) OSR = 32 Position */
|
||||
#define DACC_TRIGR_OSR1_Pos _U_(20) /**< (DACC_TRIGR) Over Sampling Ratio of Channel 1 Position */
|
||||
#define DACC_TRIGR_OSR1_Msk (_U_(0x7) << DACC_TRIGR_OSR1_Pos) /**< (DACC_TRIGR) Over Sampling Ratio of Channel 1 Mask */
|
||||
#define DACC_TRIGR_OSR1(value) (DACC_TRIGR_OSR1_Msk & ((value) << DACC_TRIGR_OSR1_Pos))
|
||||
#define DACC_TRIGR_OSR1_OSR_1_Val _U_(0x0) /**< (DACC_TRIGR) OSR = 1 */
|
||||
#define DACC_TRIGR_OSR1_OSR_2_Val _U_(0x1) /**< (DACC_TRIGR) OSR = 2 */
|
||||
#define DACC_TRIGR_OSR1_OSR_4_Val _U_(0x2) /**< (DACC_TRIGR) OSR = 4 */
|
||||
#define DACC_TRIGR_OSR1_OSR_8_Val _U_(0x3) /**< (DACC_TRIGR) OSR = 8 */
|
||||
#define DACC_TRIGR_OSR1_OSR_16_Val _U_(0x4) /**< (DACC_TRIGR) OSR = 16 */
|
||||
#define DACC_TRIGR_OSR1_OSR_32_Val _U_(0x5) /**< (DACC_TRIGR) OSR = 32 */
|
||||
#define DACC_TRIGR_OSR1_OSR_1 (DACC_TRIGR_OSR1_OSR_1_Val << DACC_TRIGR_OSR1_Pos) /**< (DACC_TRIGR) OSR = 1 Position */
|
||||
#define DACC_TRIGR_OSR1_OSR_2 (DACC_TRIGR_OSR1_OSR_2_Val << DACC_TRIGR_OSR1_Pos) /**< (DACC_TRIGR) OSR = 2 Position */
|
||||
#define DACC_TRIGR_OSR1_OSR_4 (DACC_TRIGR_OSR1_OSR_4_Val << DACC_TRIGR_OSR1_Pos) /**< (DACC_TRIGR) OSR = 4 Position */
|
||||
#define DACC_TRIGR_OSR1_OSR_8 (DACC_TRIGR_OSR1_OSR_8_Val << DACC_TRIGR_OSR1_Pos) /**< (DACC_TRIGR) OSR = 8 Position */
|
||||
#define DACC_TRIGR_OSR1_OSR_16 (DACC_TRIGR_OSR1_OSR_16_Val << DACC_TRIGR_OSR1_Pos) /**< (DACC_TRIGR) OSR = 16 Position */
|
||||
#define DACC_TRIGR_OSR1_OSR_32 (DACC_TRIGR_OSR1_OSR_32_Val << DACC_TRIGR_OSR1_Pos) /**< (DACC_TRIGR) OSR = 32 Position */
|
||||
#define DACC_TRIGR_Msk _U_(0x00770773) /**< (DACC_TRIGR) Register Mask */
|
||||
|
||||
#define DACC_TRIGR_TRGEN_Pos _U_(0) /**< (DACC_TRIGR Position) Trigger Enable of Channel x */
|
||||
#define DACC_TRIGR_TRGEN_Msk (_U_(0x3) << DACC_TRIGR_TRGEN_Pos) /**< (DACC_TRIGR Mask) TRGEN */
|
||||
#define DACC_TRIGR_TRGEN(value) (DACC_TRIGR_TRGEN_Msk & ((value) << DACC_TRIGR_TRGEN_Pos))
|
||||
|
||||
/* -------- DACC_CHER : (DACC Offset: 0x10) ( /W 32) Channel Enable Register -------- */
|
||||
#define DACC_CHER_CH0_Pos _U_(0) /**< (DACC_CHER) Channel 0 Enable Position */
|
||||
#define DACC_CHER_CH0_Msk (_U_(0x1) << DACC_CHER_CH0_Pos) /**< (DACC_CHER) Channel 0 Enable Mask */
|
||||
#define DACC_CHER_CH0(value) (DACC_CHER_CH0_Msk & ((value) << DACC_CHER_CH0_Pos))
|
||||
#define DACC_CHER_CH1_Pos _U_(1) /**< (DACC_CHER) Channel 1 Enable Position */
|
||||
#define DACC_CHER_CH1_Msk (_U_(0x1) << DACC_CHER_CH1_Pos) /**< (DACC_CHER) Channel 1 Enable Mask */
|
||||
#define DACC_CHER_CH1(value) (DACC_CHER_CH1_Msk & ((value) << DACC_CHER_CH1_Pos))
|
||||
#define DACC_CHER_Msk _U_(0x00000003) /**< (DACC_CHER) Register Mask */
|
||||
|
||||
#define DACC_CHER_CH_Pos _U_(0) /**< (DACC_CHER Position) Channel x Enable */
|
||||
#define DACC_CHER_CH_Msk (_U_(0x3) << DACC_CHER_CH_Pos) /**< (DACC_CHER Mask) CH */
|
||||
#define DACC_CHER_CH(value) (DACC_CHER_CH_Msk & ((value) << DACC_CHER_CH_Pos))
|
||||
|
||||
/* -------- DACC_CHDR : (DACC Offset: 0x14) ( /W 32) Channel Disable Register -------- */
|
||||
#define DACC_CHDR_CH0_Pos _U_(0) /**< (DACC_CHDR) Channel 0 Disable Position */
|
||||
#define DACC_CHDR_CH0_Msk (_U_(0x1) << DACC_CHDR_CH0_Pos) /**< (DACC_CHDR) Channel 0 Disable Mask */
|
||||
#define DACC_CHDR_CH0(value) (DACC_CHDR_CH0_Msk & ((value) << DACC_CHDR_CH0_Pos))
|
||||
#define DACC_CHDR_CH1_Pos _U_(1) /**< (DACC_CHDR) Channel 1 Disable Position */
|
||||
#define DACC_CHDR_CH1_Msk (_U_(0x1) << DACC_CHDR_CH1_Pos) /**< (DACC_CHDR) Channel 1 Disable Mask */
|
||||
#define DACC_CHDR_CH1(value) (DACC_CHDR_CH1_Msk & ((value) << DACC_CHDR_CH1_Pos))
|
||||
#define DACC_CHDR_Msk _U_(0x00000003) /**< (DACC_CHDR) Register Mask */
|
||||
|
||||
#define DACC_CHDR_CH_Pos _U_(0) /**< (DACC_CHDR Position) Channel x Disable */
|
||||
#define DACC_CHDR_CH_Msk (_U_(0x3) << DACC_CHDR_CH_Pos) /**< (DACC_CHDR Mask) CH */
|
||||
#define DACC_CHDR_CH(value) (DACC_CHDR_CH_Msk & ((value) << DACC_CHDR_CH_Pos))
|
||||
|
||||
/* -------- DACC_CHSR : (DACC Offset: 0x18) ( R/ 32) Channel Status Register -------- */
|
||||
#define DACC_CHSR_CH0_Pos _U_(0) /**< (DACC_CHSR) Channel 0 Status Position */
|
||||
#define DACC_CHSR_CH0_Msk (_U_(0x1) << DACC_CHSR_CH0_Pos) /**< (DACC_CHSR) Channel 0 Status Mask */
|
||||
#define DACC_CHSR_CH0(value) (DACC_CHSR_CH0_Msk & ((value) << DACC_CHSR_CH0_Pos))
|
||||
#define DACC_CHSR_CH1_Pos _U_(1) /**< (DACC_CHSR) Channel 1 Status Position */
|
||||
#define DACC_CHSR_CH1_Msk (_U_(0x1) << DACC_CHSR_CH1_Pos) /**< (DACC_CHSR) Channel 1 Status Mask */
|
||||
#define DACC_CHSR_CH1(value) (DACC_CHSR_CH1_Msk & ((value) << DACC_CHSR_CH1_Pos))
|
||||
#define DACC_CHSR_DACRDY0_Pos _U_(8) /**< (DACC_CHSR) DAC Ready Flag Position */
|
||||
#define DACC_CHSR_DACRDY0_Msk (_U_(0x1) << DACC_CHSR_DACRDY0_Pos) /**< (DACC_CHSR) DAC Ready Flag Mask */
|
||||
#define DACC_CHSR_DACRDY0(value) (DACC_CHSR_DACRDY0_Msk & ((value) << DACC_CHSR_DACRDY0_Pos))
|
||||
#define DACC_CHSR_DACRDY1_Pos _U_(9) /**< (DACC_CHSR) DAC Ready Flag Position */
|
||||
#define DACC_CHSR_DACRDY1_Msk (_U_(0x1) << DACC_CHSR_DACRDY1_Pos) /**< (DACC_CHSR) DAC Ready Flag Mask */
|
||||
#define DACC_CHSR_DACRDY1(value) (DACC_CHSR_DACRDY1_Msk & ((value) << DACC_CHSR_DACRDY1_Pos))
|
||||
#define DACC_CHSR_Msk _U_(0x00000303) /**< (DACC_CHSR) Register Mask */
|
||||
|
||||
#define DACC_CHSR_CH_Pos _U_(0) /**< (DACC_CHSR Position) Channel x Status */
|
||||
#define DACC_CHSR_CH_Msk (_U_(0x3) << DACC_CHSR_CH_Pos) /**< (DACC_CHSR Mask) CH */
|
||||
#define DACC_CHSR_CH(value) (DACC_CHSR_CH_Msk & ((value) << DACC_CHSR_CH_Pos))
|
||||
#define DACC_CHSR_DACRDY_Pos _U_(8) /**< (DACC_CHSR Position) DAC Ready Flag */
|
||||
#define DACC_CHSR_DACRDY_Msk (_U_(0x3) << DACC_CHSR_DACRDY_Pos) /**< (DACC_CHSR Mask) DACRDY */
|
||||
#define DACC_CHSR_DACRDY(value) (DACC_CHSR_DACRDY_Msk & ((value) << DACC_CHSR_DACRDY_Pos))
|
||||
|
||||
/* -------- DACC_CDR : (DACC Offset: 0x1C) ( /W 32) Conversion Data Register 0 -------- */
|
||||
#define DACC_CDR_DATA0_Pos _U_(0) /**< (DACC_CDR) Data to Convert for channel 0 Position */
|
||||
#define DACC_CDR_DATA0_Msk (_U_(0xFFFF) << DACC_CDR_DATA0_Pos) /**< (DACC_CDR) Data to Convert for channel 0 Mask */
|
||||
#define DACC_CDR_DATA0(value) (DACC_CDR_DATA0_Msk & ((value) << DACC_CDR_DATA0_Pos))
|
||||
#define DACC_CDR_DATA1_Pos _U_(16) /**< (DACC_CDR) Data to Convert for channel 1 Position */
|
||||
#define DACC_CDR_DATA1_Msk (_U_(0xFFFF) << DACC_CDR_DATA1_Pos) /**< (DACC_CDR) Data to Convert for channel 1 Mask */
|
||||
#define DACC_CDR_DATA1(value) (DACC_CDR_DATA1_Msk & ((value) << DACC_CDR_DATA1_Pos))
|
||||
#define DACC_CDR_Msk _U_(0xFFFFFFFF) /**< (DACC_CDR) Register Mask */
|
||||
|
||||
|
||||
/* -------- DACC_IER : (DACC Offset: 0x24) ( /W 32) Interrupt Enable Register -------- */
|
||||
#define DACC_IER_TXRDY0_Pos _U_(0) /**< (DACC_IER) Transmit Ready Interrupt Enable of channel 0 Position */
|
||||
#define DACC_IER_TXRDY0_Msk (_U_(0x1) << DACC_IER_TXRDY0_Pos) /**< (DACC_IER) Transmit Ready Interrupt Enable of channel 0 Mask */
|
||||
#define DACC_IER_TXRDY0(value) (DACC_IER_TXRDY0_Msk & ((value) << DACC_IER_TXRDY0_Pos))
|
||||
#define DACC_IER_TXRDY1_Pos _U_(1) /**< (DACC_IER) Transmit Ready Interrupt Enable of channel 1 Position */
|
||||
#define DACC_IER_TXRDY1_Msk (_U_(0x1) << DACC_IER_TXRDY1_Pos) /**< (DACC_IER) Transmit Ready Interrupt Enable of channel 1 Mask */
|
||||
#define DACC_IER_TXRDY1(value) (DACC_IER_TXRDY1_Msk & ((value) << DACC_IER_TXRDY1_Pos))
|
||||
#define DACC_IER_EOC0_Pos _U_(4) /**< (DACC_IER) End of Conversion Interrupt Enable of channel 0 Position */
|
||||
#define DACC_IER_EOC0_Msk (_U_(0x1) << DACC_IER_EOC0_Pos) /**< (DACC_IER) End of Conversion Interrupt Enable of channel 0 Mask */
|
||||
#define DACC_IER_EOC0(value) (DACC_IER_EOC0_Msk & ((value) << DACC_IER_EOC0_Pos))
|
||||
#define DACC_IER_EOC1_Pos _U_(5) /**< (DACC_IER) End of Conversion Interrupt Enable of channel 1 Position */
|
||||
#define DACC_IER_EOC1_Msk (_U_(0x1) << DACC_IER_EOC1_Pos) /**< (DACC_IER) End of Conversion Interrupt Enable of channel 1 Mask */
|
||||
#define DACC_IER_EOC1(value) (DACC_IER_EOC1_Msk & ((value) << DACC_IER_EOC1_Pos))
|
||||
#define DACC_IER_Msk _U_(0x00000033) /**< (DACC_IER) Register Mask */
|
||||
|
||||
#define DACC_IER_TXRDY_Pos _U_(0) /**< (DACC_IER Position) Transmit Ready Interrupt Enable of channel x */
|
||||
#define DACC_IER_TXRDY_Msk (_U_(0x3) << DACC_IER_TXRDY_Pos) /**< (DACC_IER Mask) TXRDY */
|
||||
#define DACC_IER_TXRDY(value) (DACC_IER_TXRDY_Msk & ((value) << DACC_IER_TXRDY_Pos))
|
||||
#define DACC_IER_EOC_Pos _U_(4) /**< (DACC_IER Position) End of Conversion Interrupt Enable of channel x */
|
||||
#define DACC_IER_EOC_Msk (_U_(0x3) << DACC_IER_EOC_Pos) /**< (DACC_IER Mask) EOC */
|
||||
#define DACC_IER_EOC(value) (DACC_IER_EOC_Msk & ((value) << DACC_IER_EOC_Pos))
|
||||
|
||||
/* -------- DACC_IDR : (DACC Offset: 0x28) ( /W 32) Interrupt Disable Register -------- */
|
||||
#define DACC_IDR_TXRDY0_Pos _U_(0) /**< (DACC_IDR) Transmit Ready Interrupt Disable of channel 0 Position */
|
||||
#define DACC_IDR_TXRDY0_Msk (_U_(0x1) << DACC_IDR_TXRDY0_Pos) /**< (DACC_IDR) Transmit Ready Interrupt Disable of channel 0 Mask */
|
||||
#define DACC_IDR_TXRDY0(value) (DACC_IDR_TXRDY0_Msk & ((value) << DACC_IDR_TXRDY0_Pos))
|
||||
#define DACC_IDR_TXRDY1_Pos _U_(1) /**< (DACC_IDR) Transmit Ready Interrupt Disable of channel 1 Position */
|
||||
#define DACC_IDR_TXRDY1_Msk (_U_(0x1) << DACC_IDR_TXRDY1_Pos) /**< (DACC_IDR) Transmit Ready Interrupt Disable of channel 1 Mask */
|
||||
#define DACC_IDR_TXRDY1(value) (DACC_IDR_TXRDY1_Msk & ((value) << DACC_IDR_TXRDY1_Pos))
|
||||
#define DACC_IDR_EOC0_Pos _U_(4) /**< (DACC_IDR) End of Conversion Interrupt Disable of channel 0 Position */
|
||||
#define DACC_IDR_EOC0_Msk (_U_(0x1) << DACC_IDR_EOC0_Pos) /**< (DACC_IDR) End of Conversion Interrupt Disable of channel 0 Mask */
|
||||
#define DACC_IDR_EOC0(value) (DACC_IDR_EOC0_Msk & ((value) << DACC_IDR_EOC0_Pos))
|
||||
#define DACC_IDR_EOC1_Pos _U_(5) /**< (DACC_IDR) End of Conversion Interrupt Disable of channel 1 Position */
|
||||
#define DACC_IDR_EOC1_Msk (_U_(0x1) << DACC_IDR_EOC1_Pos) /**< (DACC_IDR) End of Conversion Interrupt Disable of channel 1 Mask */
|
||||
#define DACC_IDR_EOC1(value) (DACC_IDR_EOC1_Msk & ((value) << DACC_IDR_EOC1_Pos))
|
||||
#define DACC_IDR_Msk _U_(0x00000033) /**< (DACC_IDR) Register Mask */
|
||||
|
||||
#define DACC_IDR_TXRDY_Pos _U_(0) /**< (DACC_IDR Position) Transmit Ready Interrupt Disable of channel x */
|
||||
#define DACC_IDR_TXRDY_Msk (_U_(0x3) << DACC_IDR_TXRDY_Pos) /**< (DACC_IDR Mask) TXRDY */
|
||||
#define DACC_IDR_TXRDY(value) (DACC_IDR_TXRDY_Msk & ((value) << DACC_IDR_TXRDY_Pos))
|
||||
#define DACC_IDR_EOC_Pos _U_(4) /**< (DACC_IDR Position) End of Conversion Interrupt Disable of channel x */
|
||||
#define DACC_IDR_EOC_Msk (_U_(0x3) << DACC_IDR_EOC_Pos) /**< (DACC_IDR Mask) EOC */
|
||||
#define DACC_IDR_EOC(value) (DACC_IDR_EOC_Msk & ((value) << DACC_IDR_EOC_Pos))
|
||||
|
||||
/* -------- DACC_IMR : (DACC Offset: 0x2C) ( R/ 32) Interrupt Mask Register -------- */
|
||||
#define DACC_IMR_TXRDY0_Pos _U_(0) /**< (DACC_IMR) Transmit Ready Interrupt Mask of channel 0 Position */
|
||||
#define DACC_IMR_TXRDY0_Msk (_U_(0x1) << DACC_IMR_TXRDY0_Pos) /**< (DACC_IMR) Transmit Ready Interrupt Mask of channel 0 Mask */
|
||||
#define DACC_IMR_TXRDY0(value) (DACC_IMR_TXRDY0_Msk & ((value) << DACC_IMR_TXRDY0_Pos))
|
||||
#define DACC_IMR_TXRDY1_Pos _U_(1) /**< (DACC_IMR) Transmit Ready Interrupt Mask of channel 1 Position */
|
||||
#define DACC_IMR_TXRDY1_Msk (_U_(0x1) << DACC_IMR_TXRDY1_Pos) /**< (DACC_IMR) Transmit Ready Interrupt Mask of channel 1 Mask */
|
||||
#define DACC_IMR_TXRDY1(value) (DACC_IMR_TXRDY1_Msk & ((value) << DACC_IMR_TXRDY1_Pos))
|
||||
#define DACC_IMR_EOC0_Pos _U_(4) /**< (DACC_IMR) End of Conversion Interrupt Mask of channel 0 Position */
|
||||
#define DACC_IMR_EOC0_Msk (_U_(0x1) << DACC_IMR_EOC0_Pos) /**< (DACC_IMR) End of Conversion Interrupt Mask of channel 0 Mask */
|
||||
#define DACC_IMR_EOC0(value) (DACC_IMR_EOC0_Msk & ((value) << DACC_IMR_EOC0_Pos))
|
||||
#define DACC_IMR_EOC1_Pos _U_(5) /**< (DACC_IMR) End of Conversion Interrupt Mask of channel 1 Position */
|
||||
#define DACC_IMR_EOC1_Msk (_U_(0x1) << DACC_IMR_EOC1_Pos) /**< (DACC_IMR) End of Conversion Interrupt Mask of channel 1 Mask */
|
||||
#define DACC_IMR_EOC1(value) (DACC_IMR_EOC1_Msk & ((value) << DACC_IMR_EOC1_Pos))
|
||||
#define DACC_IMR_Msk _U_(0x00000033) /**< (DACC_IMR) Register Mask */
|
||||
|
||||
#define DACC_IMR_TXRDY_Pos _U_(0) /**< (DACC_IMR Position) Transmit Ready Interrupt Mask of channel x */
|
||||
#define DACC_IMR_TXRDY_Msk (_U_(0x3) << DACC_IMR_TXRDY_Pos) /**< (DACC_IMR Mask) TXRDY */
|
||||
#define DACC_IMR_TXRDY(value) (DACC_IMR_TXRDY_Msk & ((value) << DACC_IMR_TXRDY_Pos))
|
||||
#define DACC_IMR_EOC_Pos _U_(4) /**< (DACC_IMR Position) End of Conversion Interrupt Mask of channel x */
|
||||
#define DACC_IMR_EOC_Msk (_U_(0x3) << DACC_IMR_EOC_Pos) /**< (DACC_IMR Mask) EOC */
|
||||
#define DACC_IMR_EOC(value) (DACC_IMR_EOC_Msk & ((value) << DACC_IMR_EOC_Pos))
|
||||
|
||||
/* -------- DACC_ISR : (DACC Offset: 0x30) ( R/ 32) Interrupt Status Register -------- */
|
||||
#define DACC_ISR_TXRDY0_Pos _U_(0) /**< (DACC_ISR) Transmit Ready Interrupt Flag of channel 0 Position */
|
||||
#define DACC_ISR_TXRDY0_Msk (_U_(0x1) << DACC_ISR_TXRDY0_Pos) /**< (DACC_ISR) Transmit Ready Interrupt Flag of channel 0 Mask */
|
||||
#define DACC_ISR_TXRDY0(value) (DACC_ISR_TXRDY0_Msk & ((value) << DACC_ISR_TXRDY0_Pos))
|
||||
#define DACC_ISR_TXRDY1_Pos _U_(1) /**< (DACC_ISR) Transmit Ready Interrupt Flag of channel 1 Position */
|
||||
#define DACC_ISR_TXRDY1_Msk (_U_(0x1) << DACC_ISR_TXRDY1_Pos) /**< (DACC_ISR) Transmit Ready Interrupt Flag of channel 1 Mask */
|
||||
#define DACC_ISR_TXRDY1(value) (DACC_ISR_TXRDY1_Msk & ((value) << DACC_ISR_TXRDY1_Pos))
|
||||
#define DACC_ISR_EOC0_Pos _U_(4) /**< (DACC_ISR) End of Conversion Interrupt Flag of channel 0 Position */
|
||||
#define DACC_ISR_EOC0_Msk (_U_(0x1) << DACC_ISR_EOC0_Pos) /**< (DACC_ISR) End of Conversion Interrupt Flag of channel 0 Mask */
|
||||
#define DACC_ISR_EOC0(value) (DACC_ISR_EOC0_Msk & ((value) << DACC_ISR_EOC0_Pos))
|
||||
#define DACC_ISR_EOC1_Pos _U_(5) /**< (DACC_ISR) End of Conversion Interrupt Flag of channel 1 Position */
|
||||
#define DACC_ISR_EOC1_Msk (_U_(0x1) << DACC_ISR_EOC1_Pos) /**< (DACC_ISR) End of Conversion Interrupt Flag of channel 1 Mask */
|
||||
#define DACC_ISR_EOC1(value) (DACC_ISR_EOC1_Msk & ((value) << DACC_ISR_EOC1_Pos))
|
||||
#define DACC_ISR_Msk _U_(0x00000033) /**< (DACC_ISR) Register Mask */
|
||||
|
||||
#define DACC_ISR_TXRDY_Pos _U_(0) /**< (DACC_ISR Position) Transmit Ready Interrupt Flag of channel x */
|
||||
#define DACC_ISR_TXRDY_Msk (_U_(0x3) << DACC_ISR_TXRDY_Pos) /**< (DACC_ISR Mask) TXRDY */
|
||||
#define DACC_ISR_TXRDY(value) (DACC_ISR_TXRDY_Msk & ((value) << DACC_ISR_TXRDY_Pos))
|
||||
#define DACC_ISR_EOC_Pos _U_(4) /**< (DACC_ISR Position) End of Conversion Interrupt Flag of channel x */
|
||||
#define DACC_ISR_EOC_Msk (_U_(0x3) << DACC_ISR_EOC_Pos) /**< (DACC_ISR Mask) EOC */
|
||||
#define DACC_ISR_EOC(value) (DACC_ISR_EOC_Msk & ((value) << DACC_ISR_EOC_Pos))
|
||||
|
||||
/* -------- DACC_ACR : (DACC Offset: 0x94) (R/W 32) Analog Current Register -------- */
|
||||
#define DACC_ACR_IBCTLCH0_Pos _U_(0) /**< (DACC_ACR) Analog Output Current Control Position */
|
||||
#define DACC_ACR_IBCTLCH0_Msk (_U_(0x3) << DACC_ACR_IBCTLCH0_Pos) /**< (DACC_ACR) Analog Output Current Control Mask */
|
||||
#define DACC_ACR_IBCTLCH0(value) (DACC_ACR_IBCTLCH0_Msk & ((value) << DACC_ACR_IBCTLCH0_Pos))
|
||||
#define DACC_ACR_IBCTLCH1_Pos _U_(2) /**< (DACC_ACR) Analog Output Current Control Position */
|
||||
#define DACC_ACR_IBCTLCH1_Msk (_U_(0x3) << DACC_ACR_IBCTLCH1_Pos) /**< (DACC_ACR) Analog Output Current Control Mask */
|
||||
#define DACC_ACR_IBCTLCH1(value) (DACC_ACR_IBCTLCH1_Msk & ((value) << DACC_ACR_IBCTLCH1_Pos))
|
||||
#define DACC_ACR_Msk _U_(0x0000000F) /**< (DACC_ACR) Register Mask */
|
||||
|
||||
|
||||
/* -------- DACC_WPMR : (DACC Offset: 0xE4) (R/W 32) Write Protection Mode Register -------- */
|
||||
#define DACC_WPMR_WPEN_Pos _U_(0) /**< (DACC_WPMR) Write Protection Enable Position */
|
||||
#define DACC_WPMR_WPEN_Msk (_U_(0x1) << DACC_WPMR_WPEN_Pos) /**< (DACC_WPMR) Write Protection Enable Mask */
|
||||
#define DACC_WPMR_WPEN(value) (DACC_WPMR_WPEN_Msk & ((value) << DACC_WPMR_WPEN_Pos))
|
||||
#define DACC_WPMR_WPKEY_Pos _U_(8) /**< (DACC_WPMR) Write Protect Key Position */
|
||||
#define DACC_WPMR_WPKEY_Msk (_U_(0xFFFFFF) << DACC_WPMR_WPKEY_Pos) /**< (DACC_WPMR) Write Protect Key Mask */
|
||||
#define DACC_WPMR_WPKEY(value) (DACC_WPMR_WPKEY_Msk & ((value) << DACC_WPMR_WPKEY_Pos))
|
||||
#define DACC_WPMR_WPKEY_PASSWD_Val _U_(0x444143) /**< (DACC_WPMR) Writing any other value in this field aborts the write operation of bit WPEN.Always reads as 0. */
|
||||
#define DACC_WPMR_WPKEY_PASSWD (DACC_WPMR_WPKEY_PASSWD_Val << DACC_WPMR_WPKEY_Pos) /**< (DACC_WPMR) Writing any other value in this field aborts the write operation of bit WPEN.Always reads as 0. Position */
|
||||
#define DACC_WPMR_Msk _U_(0xFFFFFF01) /**< (DACC_WPMR) Register Mask */
|
||||
|
||||
|
||||
/* -------- DACC_WPSR : (DACC Offset: 0xE8) ( R/ 32) Write Protection Status Register -------- */
|
||||
#define DACC_WPSR_WPVS_Pos _U_(0) /**< (DACC_WPSR) Write Protection Violation Status Position */
|
||||
#define DACC_WPSR_WPVS_Msk (_U_(0x1) << DACC_WPSR_WPVS_Pos) /**< (DACC_WPSR) Write Protection Violation Status Mask */
|
||||
#define DACC_WPSR_WPVS(value) (DACC_WPSR_WPVS_Msk & ((value) << DACC_WPSR_WPVS_Pos))
|
||||
#define DACC_WPSR_WPVSRC_Pos _U_(8) /**< (DACC_WPSR) Write Protection Violation Source Position */
|
||||
#define DACC_WPSR_WPVSRC_Msk (_U_(0xFF) << DACC_WPSR_WPVSRC_Pos) /**< (DACC_WPSR) Write Protection Violation Source Mask */
|
||||
#define DACC_WPSR_WPVSRC(value) (DACC_WPSR_WPVSRC_Msk & ((value) << DACC_WPSR_WPVSRC_Pos))
|
||||
#define DACC_WPSR_Msk _U_(0x0000FF01) /**< (DACC_WPSR) Register Mask */
|
||||
|
||||
|
||||
/** \brief DACC register offsets definitions */
|
||||
#define DACC_CR_REG_OFST (0x00) /**< (DACC_CR) Control Register Offset */
|
||||
#define DACC_MR_REG_OFST (0x04) /**< (DACC_MR) Mode Register Offset */
|
||||
#define DACC_TRIGR_REG_OFST (0x08) /**< (DACC_TRIGR) Trigger Register Offset */
|
||||
#define DACC_CHER_REG_OFST (0x10) /**< (DACC_CHER) Channel Enable Register Offset */
|
||||
#define DACC_CHDR_REG_OFST (0x14) /**< (DACC_CHDR) Channel Disable Register Offset */
|
||||
#define DACC_CHSR_REG_OFST (0x18) /**< (DACC_CHSR) Channel Status Register Offset */
|
||||
#define DACC_CDR_REG_OFST (0x1C) /**< (DACC_CDR) Conversion Data Register 0 Offset */
|
||||
#define DACC_IER_REG_OFST (0x24) /**< (DACC_IER) Interrupt Enable Register Offset */
|
||||
#define DACC_IDR_REG_OFST (0x28) /**< (DACC_IDR) Interrupt Disable Register Offset */
|
||||
#define DACC_IMR_REG_OFST (0x2C) /**< (DACC_IMR) Interrupt Mask Register Offset */
|
||||
#define DACC_ISR_REG_OFST (0x30) /**< (DACC_ISR) Interrupt Status Register Offset */
|
||||
#define DACC_ACR_REG_OFST (0x94) /**< (DACC_ACR) Analog Current Register Offset */
|
||||
#define DACC_WPMR_REG_OFST (0xE4) /**< (DACC_WPMR) Write Protection Mode Register Offset */
|
||||
#define DACC_WPSR_REG_OFST (0xE8) /**< (DACC_WPSR) Write Protection Status Register Offset */
|
||||
|
||||
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
/** \brief DACC register API structure */
|
||||
typedef struct
|
||||
{
|
||||
__O uint32_t DACC_CR; /**< Offset: 0x00 ( /W 32) Control Register */
|
||||
__IO uint32_t DACC_MR; /**< Offset: 0x04 (R/W 32) Mode Register */
|
||||
__IO uint32_t DACC_TRIGR; /**< Offset: 0x08 (R/W 32) Trigger Register */
|
||||
__I uint8_t Reserved1[0x04];
|
||||
__O uint32_t DACC_CHER; /**< Offset: 0x10 ( /W 32) Channel Enable Register */
|
||||
__O uint32_t DACC_CHDR; /**< Offset: 0x14 ( /W 32) Channel Disable Register */
|
||||
__I uint32_t DACC_CHSR; /**< Offset: 0x18 (R/ 32) Channel Status Register */
|
||||
__O uint32_t DACC_CDR[2]; /**< Offset: 0x1C ( /W 32) Conversion Data Register 0 */
|
||||
__O uint32_t DACC_IER; /**< Offset: 0x24 ( /W 32) Interrupt Enable Register */
|
||||
__O uint32_t DACC_IDR; /**< Offset: 0x28 ( /W 32) Interrupt Disable Register */
|
||||
__I uint32_t DACC_IMR; /**< Offset: 0x2C (R/ 32) Interrupt Mask Register */
|
||||
__I uint32_t DACC_ISR; /**< Offset: 0x30 (R/ 32) Interrupt Status Register */
|
||||
__I uint8_t Reserved2[0x60];
|
||||
__IO uint32_t DACC_ACR; /**< Offset: 0x94 (R/W 32) Analog Current Register */
|
||||
__I uint8_t Reserved3[0x4C];
|
||||
__IO uint32_t DACC_WPMR; /**< Offset: 0xE4 (R/W 32) Write Protection Mode Register */
|
||||
__I uint32_t DACC_WPSR; /**< Offset: 0xE8 (R/ 32) Write Protection Status Register */
|
||||
} dacc_registers_t;
|
||||
|
||||
|
||||
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
#endif /* _SAME70_DACC_COMPONENT_H_ */
|
||||
@ -0,0 +1,172 @@
|
||||
/**
|
||||
* \brief Component description for EFC
|
||||
*
|
||||
* Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries.
|
||||
*
|
||||
* Subject to your compliance with these terms, you may use Microchip software and any derivatives
|
||||
* exclusively with Microchip products. It is your responsibility to comply with third party license
|
||||
* terms applicable to your use of third party software (including open source software) that may
|
||||
* accompany Microchip software.
|
||||
*
|
||||
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY,
|
||||
* APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND
|
||||
* FITNESS FOR A PARTICULAR PURPOSE.
|
||||
*
|
||||
* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
|
||||
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF
|
||||
* MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
|
||||
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT
|
||||
* EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
|
||||
*
|
||||
*/
|
||||
|
||||
/* file generated from device description version 2017-08-25T14:00:00Z */
|
||||
#ifndef _SAME70_EFC_COMPONENT_H_
|
||||
#define _SAME70_EFC_COMPONENT_H_
|
||||
|
||||
/* ************************************************************************** */
|
||||
/* SOFTWARE API DEFINITION FOR EFC */
|
||||
/* ************************************************************************** */
|
||||
|
||||
/* -------- EEFC_FMR : (EFC Offset: 0x00) (R/W 32) EEFC Flash Mode Register -------- */
|
||||
#define EEFC_FMR_FRDY_Pos _U_(0) /**< (EEFC_FMR) Flash Ready Interrupt Enable Position */
|
||||
#define EEFC_FMR_FRDY_Msk (_U_(0x1) << EEFC_FMR_FRDY_Pos) /**< (EEFC_FMR) Flash Ready Interrupt Enable Mask */
|
||||
#define EEFC_FMR_FRDY(value) (EEFC_FMR_FRDY_Msk & ((value) << EEFC_FMR_FRDY_Pos))
|
||||
#define EEFC_FMR_FWS_Pos _U_(8) /**< (EEFC_FMR) Flash Wait State Position */
|
||||
#define EEFC_FMR_FWS_Msk (_U_(0xF) << EEFC_FMR_FWS_Pos) /**< (EEFC_FMR) Flash Wait State Mask */
|
||||
#define EEFC_FMR_FWS(value) (EEFC_FMR_FWS_Msk & ((value) << EEFC_FMR_FWS_Pos))
|
||||
#define EEFC_FMR_SCOD_Pos _U_(16) /**< (EEFC_FMR) Sequential Code Optimization Disable Position */
|
||||
#define EEFC_FMR_SCOD_Msk (_U_(0x1) << EEFC_FMR_SCOD_Pos) /**< (EEFC_FMR) Sequential Code Optimization Disable Mask */
|
||||
#define EEFC_FMR_SCOD(value) (EEFC_FMR_SCOD_Msk & ((value) << EEFC_FMR_SCOD_Pos))
|
||||
#define EEFC_FMR_CLOE_Pos _U_(26) /**< (EEFC_FMR) Code Loop Optimization Enable Position */
|
||||
#define EEFC_FMR_CLOE_Msk (_U_(0x1) << EEFC_FMR_CLOE_Pos) /**< (EEFC_FMR) Code Loop Optimization Enable Mask */
|
||||
#define EEFC_FMR_CLOE(value) (EEFC_FMR_CLOE_Msk & ((value) << EEFC_FMR_CLOE_Pos))
|
||||
#define EEFC_FMR_Msk _U_(0x04010F01) /**< (EEFC_FMR) Register Mask */
|
||||
|
||||
|
||||
/* -------- EEFC_FCR : (EFC Offset: 0x04) ( /W 32) EEFC Flash Command Register -------- */
|
||||
#define EEFC_FCR_FCMD_Pos _U_(0) /**< (EEFC_FCR) Flash Command Position */
|
||||
#define EEFC_FCR_FCMD_Msk (_U_(0xFF) << EEFC_FCR_FCMD_Pos) /**< (EEFC_FCR) Flash Command Mask */
|
||||
#define EEFC_FCR_FCMD(value) (EEFC_FCR_FCMD_Msk & ((value) << EEFC_FCR_FCMD_Pos))
|
||||
#define EEFC_FCR_FCMD_GETD_Val _U_(0x0) /**< (EEFC_FCR) Get Flash descriptor */
|
||||
#define EEFC_FCR_FCMD_WP_Val _U_(0x1) /**< (EEFC_FCR) Write page */
|
||||
#define EEFC_FCR_FCMD_WPL_Val _U_(0x2) /**< (EEFC_FCR) Write page and lock */
|
||||
#define EEFC_FCR_FCMD_EWP_Val _U_(0x3) /**< (EEFC_FCR) Erase page and write page */
|
||||
#define EEFC_FCR_FCMD_EWPL_Val _U_(0x4) /**< (EEFC_FCR) Erase page and write page then lock */
|
||||
#define EEFC_FCR_FCMD_EA_Val _U_(0x5) /**< (EEFC_FCR) Erase all */
|
||||
#define EEFC_FCR_FCMD_EPA_Val _U_(0x7) /**< (EEFC_FCR) Erase pages */
|
||||
#define EEFC_FCR_FCMD_SLB_Val _U_(0x8) /**< (EEFC_FCR) Set lock bit */
|
||||
#define EEFC_FCR_FCMD_CLB_Val _U_(0x9) /**< (EEFC_FCR) Clear lock bit */
|
||||
#define EEFC_FCR_FCMD_GLB_Val _U_(0xA) /**< (EEFC_FCR) Get lock bit */
|
||||
#define EEFC_FCR_FCMD_SGPB_Val _U_(0xB) /**< (EEFC_FCR) Set GPNVM bit */
|
||||
#define EEFC_FCR_FCMD_CGPB_Val _U_(0xC) /**< (EEFC_FCR) Clear GPNVM bit */
|
||||
#define EEFC_FCR_FCMD_GGPB_Val _U_(0xD) /**< (EEFC_FCR) Get GPNVM bit */
|
||||
#define EEFC_FCR_FCMD_STUI_Val _U_(0xE) /**< (EEFC_FCR) Start read unique identifier */
|
||||
#define EEFC_FCR_FCMD_SPUI_Val _U_(0xF) /**< (EEFC_FCR) Stop read unique identifier */
|
||||
#define EEFC_FCR_FCMD_GCALB_Val _U_(0x10) /**< (EEFC_FCR) Get CALIB bit */
|
||||
#define EEFC_FCR_FCMD_ES_Val _U_(0x11) /**< (EEFC_FCR) Erase sector */
|
||||
#define EEFC_FCR_FCMD_WUS_Val _U_(0x12) /**< (EEFC_FCR) Write user signature */
|
||||
#define EEFC_FCR_FCMD_EUS_Val _U_(0x13) /**< (EEFC_FCR) Erase user signature */
|
||||
#define EEFC_FCR_FCMD_STUS_Val _U_(0x14) /**< (EEFC_FCR) Start read user signature */
|
||||
#define EEFC_FCR_FCMD_SPUS_Val _U_(0x15) /**< (EEFC_FCR) Stop read user signature */
|
||||
#define EEFC_FCR_FCMD_GETD (EEFC_FCR_FCMD_GETD_Val << EEFC_FCR_FCMD_Pos) /**< (EEFC_FCR) Get Flash descriptor Position */
|
||||
#define EEFC_FCR_FCMD_WP (EEFC_FCR_FCMD_WP_Val << EEFC_FCR_FCMD_Pos) /**< (EEFC_FCR) Write page Position */
|
||||
#define EEFC_FCR_FCMD_WPL (EEFC_FCR_FCMD_WPL_Val << EEFC_FCR_FCMD_Pos) /**< (EEFC_FCR) Write page and lock Position */
|
||||
#define EEFC_FCR_FCMD_EWP (EEFC_FCR_FCMD_EWP_Val << EEFC_FCR_FCMD_Pos) /**< (EEFC_FCR) Erase page and write page Position */
|
||||
#define EEFC_FCR_FCMD_EWPL (EEFC_FCR_FCMD_EWPL_Val << EEFC_FCR_FCMD_Pos) /**< (EEFC_FCR) Erase page and write page then lock Position */
|
||||
#define EEFC_FCR_FCMD_EA (EEFC_FCR_FCMD_EA_Val << EEFC_FCR_FCMD_Pos) /**< (EEFC_FCR) Erase all Position */
|
||||
#define EEFC_FCR_FCMD_EPA (EEFC_FCR_FCMD_EPA_Val << EEFC_FCR_FCMD_Pos) /**< (EEFC_FCR) Erase pages Position */
|
||||
#define EEFC_FCR_FCMD_SLB (EEFC_FCR_FCMD_SLB_Val << EEFC_FCR_FCMD_Pos) /**< (EEFC_FCR) Set lock bit Position */
|
||||
#define EEFC_FCR_FCMD_CLB (EEFC_FCR_FCMD_CLB_Val << EEFC_FCR_FCMD_Pos) /**< (EEFC_FCR) Clear lock bit Position */
|
||||
#define EEFC_FCR_FCMD_GLB (EEFC_FCR_FCMD_GLB_Val << EEFC_FCR_FCMD_Pos) /**< (EEFC_FCR) Get lock bit Position */
|
||||
#define EEFC_FCR_FCMD_SGPB (EEFC_FCR_FCMD_SGPB_Val << EEFC_FCR_FCMD_Pos) /**< (EEFC_FCR) Set GPNVM bit Position */
|
||||
#define EEFC_FCR_FCMD_CGPB (EEFC_FCR_FCMD_CGPB_Val << EEFC_FCR_FCMD_Pos) /**< (EEFC_FCR) Clear GPNVM bit Position */
|
||||
#define EEFC_FCR_FCMD_GGPB (EEFC_FCR_FCMD_GGPB_Val << EEFC_FCR_FCMD_Pos) /**< (EEFC_FCR) Get GPNVM bit Position */
|
||||
#define EEFC_FCR_FCMD_STUI (EEFC_FCR_FCMD_STUI_Val << EEFC_FCR_FCMD_Pos) /**< (EEFC_FCR) Start read unique identifier Position */
|
||||
#define EEFC_FCR_FCMD_SPUI (EEFC_FCR_FCMD_SPUI_Val << EEFC_FCR_FCMD_Pos) /**< (EEFC_FCR) Stop read unique identifier Position */
|
||||
#define EEFC_FCR_FCMD_GCALB (EEFC_FCR_FCMD_GCALB_Val << EEFC_FCR_FCMD_Pos) /**< (EEFC_FCR) Get CALIB bit Position */
|
||||
#define EEFC_FCR_FCMD_ES (EEFC_FCR_FCMD_ES_Val << EEFC_FCR_FCMD_Pos) /**< (EEFC_FCR) Erase sector Position */
|
||||
#define EEFC_FCR_FCMD_WUS (EEFC_FCR_FCMD_WUS_Val << EEFC_FCR_FCMD_Pos) /**< (EEFC_FCR) Write user signature Position */
|
||||
#define EEFC_FCR_FCMD_EUS (EEFC_FCR_FCMD_EUS_Val << EEFC_FCR_FCMD_Pos) /**< (EEFC_FCR) Erase user signature Position */
|
||||
#define EEFC_FCR_FCMD_STUS (EEFC_FCR_FCMD_STUS_Val << EEFC_FCR_FCMD_Pos) /**< (EEFC_FCR) Start read user signature Position */
|
||||
#define EEFC_FCR_FCMD_SPUS (EEFC_FCR_FCMD_SPUS_Val << EEFC_FCR_FCMD_Pos) /**< (EEFC_FCR) Stop read user signature Position */
|
||||
#define EEFC_FCR_FARG_Pos _U_(8) /**< (EEFC_FCR) Flash Command Argument Position */
|
||||
#define EEFC_FCR_FARG_Msk (_U_(0xFFFF) << EEFC_FCR_FARG_Pos) /**< (EEFC_FCR) Flash Command Argument Mask */
|
||||
#define EEFC_FCR_FARG(value) (EEFC_FCR_FARG_Msk & ((value) << EEFC_FCR_FARG_Pos))
|
||||
#define EEFC_FCR_FKEY_Pos _U_(24) /**< (EEFC_FCR) Flash Writing Protection Key Position */
|
||||
#define EEFC_FCR_FKEY_Msk (_U_(0xFF) << EEFC_FCR_FKEY_Pos) /**< (EEFC_FCR) Flash Writing Protection Key Mask */
|
||||
#define EEFC_FCR_FKEY(value) (EEFC_FCR_FKEY_Msk & ((value) << EEFC_FCR_FKEY_Pos))
|
||||
#define EEFC_FCR_FKEY_PASSWD_Val _U_(0x5A) /**< (EEFC_FCR) The 0x5A value enables the command defined by the bits of the register. If the field is written with a different value, the write is not performed and no action is started. */
|
||||
#define EEFC_FCR_FKEY_PASSWD (EEFC_FCR_FKEY_PASSWD_Val << EEFC_FCR_FKEY_Pos) /**< (EEFC_FCR) The 0x5A value enables the command defined by the bits of the register. If the field is written with a different value, the write is not performed and no action is started. Position */
|
||||
#define EEFC_FCR_Msk _U_(0xFFFFFFFF) /**< (EEFC_FCR) Register Mask */
|
||||
|
||||
|
||||
/* -------- EEFC_FSR : (EFC Offset: 0x08) ( R/ 32) EEFC Flash Status Register -------- */
|
||||
#define EEFC_FSR_FRDY_Pos _U_(0) /**< (EEFC_FSR) Flash Ready Status (cleared when Flash is busy) Position */
|
||||
#define EEFC_FSR_FRDY_Msk (_U_(0x1) << EEFC_FSR_FRDY_Pos) /**< (EEFC_FSR) Flash Ready Status (cleared when Flash is busy) Mask */
|
||||
#define EEFC_FSR_FRDY(value) (EEFC_FSR_FRDY_Msk & ((value) << EEFC_FSR_FRDY_Pos))
|
||||
#define EEFC_FSR_FCMDE_Pos _U_(1) /**< (EEFC_FSR) Flash Command Error Status (cleared on read or by writing EEFC_FCR) Position */
|
||||
#define EEFC_FSR_FCMDE_Msk (_U_(0x1) << EEFC_FSR_FCMDE_Pos) /**< (EEFC_FSR) Flash Command Error Status (cleared on read or by writing EEFC_FCR) Mask */
|
||||
#define EEFC_FSR_FCMDE(value) (EEFC_FSR_FCMDE_Msk & ((value) << EEFC_FSR_FCMDE_Pos))
|
||||
#define EEFC_FSR_FLOCKE_Pos _U_(2) /**< (EEFC_FSR) Flash Lock Error Status (cleared on read) Position */
|
||||
#define EEFC_FSR_FLOCKE_Msk (_U_(0x1) << EEFC_FSR_FLOCKE_Pos) /**< (EEFC_FSR) Flash Lock Error Status (cleared on read) Mask */
|
||||
#define EEFC_FSR_FLOCKE(value) (EEFC_FSR_FLOCKE_Msk & ((value) << EEFC_FSR_FLOCKE_Pos))
|
||||
#define EEFC_FSR_FLERR_Pos _U_(3) /**< (EEFC_FSR) Flash Error Status (cleared when a programming operation starts) Position */
|
||||
#define EEFC_FSR_FLERR_Msk (_U_(0x1) << EEFC_FSR_FLERR_Pos) /**< (EEFC_FSR) Flash Error Status (cleared when a programming operation starts) Mask */
|
||||
#define EEFC_FSR_FLERR(value) (EEFC_FSR_FLERR_Msk & ((value) << EEFC_FSR_FLERR_Pos))
|
||||
#define EEFC_FSR_UECCELSB_Pos _U_(16) /**< (EEFC_FSR) Unique ECC Error on LSB Part of the Memory Flash Data Bus (cleared on read) Position */
|
||||
#define EEFC_FSR_UECCELSB_Msk (_U_(0x1) << EEFC_FSR_UECCELSB_Pos) /**< (EEFC_FSR) Unique ECC Error on LSB Part of the Memory Flash Data Bus (cleared on read) Mask */
|
||||
#define EEFC_FSR_UECCELSB(value) (EEFC_FSR_UECCELSB_Msk & ((value) << EEFC_FSR_UECCELSB_Pos))
|
||||
#define EEFC_FSR_MECCELSB_Pos _U_(17) /**< (EEFC_FSR) Multiple ECC Error on LSB Part of the Memory Flash Data Bus (cleared on read) Position */
|
||||
#define EEFC_FSR_MECCELSB_Msk (_U_(0x1) << EEFC_FSR_MECCELSB_Pos) /**< (EEFC_FSR) Multiple ECC Error on LSB Part of the Memory Flash Data Bus (cleared on read) Mask */
|
||||
#define EEFC_FSR_MECCELSB(value) (EEFC_FSR_MECCELSB_Msk & ((value) << EEFC_FSR_MECCELSB_Pos))
|
||||
#define EEFC_FSR_UECCEMSB_Pos _U_(18) /**< (EEFC_FSR) Unique ECC Error on MSB Part of the Memory Flash Data Bus (cleared on read) Position */
|
||||
#define EEFC_FSR_UECCEMSB_Msk (_U_(0x1) << EEFC_FSR_UECCEMSB_Pos) /**< (EEFC_FSR) Unique ECC Error on MSB Part of the Memory Flash Data Bus (cleared on read) Mask */
|
||||
#define EEFC_FSR_UECCEMSB(value) (EEFC_FSR_UECCEMSB_Msk & ((value) << EEFC_FSR_UECCEMSB_Pos))
|
||||
#define EEFC_FSR_MECCEMSB_Pos _U_(19) /**< (EEFC_FSR) Multiple ECC Error on MSB Part of the Memory Flash Data Bus (cleared on read) Position */
|
||||
#define EEFC_FSR_MECCEMSB_Msk (_U_(0x1) << EEFC_FSR_MECCEMSB_Pos) /**< (EEFC_FSR) Multiple ECC Error on MSB Part of the Memory Flash Data Bus (cleared on read) Mask */
|
||||
#define EEFC_FSR_MECCEMSB(value) (EEFC_FSR_MECCEMSB_Msk & ((value) << EEFC_FSR_MECCEMSB_Pos))
|
||||
#define EEFC_FSR_Msk _U_(0x000F000F) /**< (EEFC_FSR) Register Mask */
|
||||
|
||||
|
||||
/* -------- EEFC_FRR : (EFC Offset: 0x0C) ( R/ 32) EEFC Flash Result Register -------- */
|
||||
#define EEFC_FRR_FVALUE_Pos _U_(0) /**< (EEFC_FRR) Flash Result Value Position */
|
||||
#define EEFC_FRR_FVALUE_Msk (_U_(0xFFFFFFFF) << EEFC_FRR_FVALUE_Pos) /**< (EEFC_FRR) Flash Result Value Mask */
|
||||
#define EEFC_FRR_FVALUE(value) (EEFC_FRR_FVALUE_Msk & ((value) << EEFC_FRR_FVALUE_Pos))
|
||||
#define EEFC_FRR_Msk _U_(0xFFFFFFFF) /**< (EEFC_FRR) Register Mask */
|
||||
|
||||
|
||||
/* -------- EEFC_WPMR : (EFC Offset: 0xE4) (R/W 32) Write Protection Mode Register -------- */
|
||||
#define EEFC_WPMR_WPEN_Pos _U_(0) /**< (EEFC_WPMR) Write Protection Enable Position */
|
||||
#define EEFC_WPMR_WPEN_Msk (_U_(0x1) << EEFC_WPMR_WPEN_Pos) /**< (EEFC_WPMR) Write Protection Enable Mask */
|
||||
#define EEFC_WPMR_WPEN(value) (EEFC_WPMR_WPEN_Msk & ((value) << EEFC_WPMR_WPEN_Pos))
|
||||
#define EEFC_WPMR_WPKEY_Pos _U_(8) /**< (EEFC_WPMR) Write Protection Key Position */
|
||||
#define EEFC_WPMR_WPKEY_Msk (_U_(0xFFFFFF) << EEFC_WPMR_WPKEY_Pos) /**< (EEFC_WPMR) Write Protection Key Mask */
|
||||
#define EEFC_WPMR_WPKEY(value) (EEFC_WPMR_WPKEY_Msk & ((value) << EEFC_WPMR_WPKEY_Pos))
|
||||
#define EEFC_WPMR_WPKEY_PASSWD_Val _U_(0x454643) /**< (EEFC_WPMR) Writing any other value in this field aborts the write operation.Always reads as 0. */
|
||||
#define EEFC_WPMR_WPKEY_PASSWD (EEFC_WPMR_WPKEY_PASSWD_Val << EEFC_WPMR_WPKEY_Pos) /**< (EEFC_WPMR) Writing any other value in this field aborts the write operation.Always reads as 0. Position */
|
||||
#define EEFC_WPMR_Msk _U_(0xFFFFFF01) /**< (EEFC_WPMR) Register Mask */
|
||||
|
||||
|
||||
/** \brief EFC register offsets definitions */
|
||||
#define EEFC_FMR_REG_OFST (0x00) /**< (EEFC_FMR) EEFC Flash Mode Register Offset */
|
||||
#define EEFC_FCR_REG_OFST (0x04) /**< (EEFC_FCR) EEFC Flash Command Register Offset */
|
||||
#define EEFC_FSR_REG_OFST (0x08) /**< (EEFC_FSR) EEFC Flash Status Register Offset */
|
||||
#define EEFC_FRR_REG_OFST (0x0C) /**< (EEFC_FRR) EEFC Flash Result Register Offset */
|
||||
#define EEFC_WPMR_REG_OFST (0xE4) /**< (EEFC_WPMR) Write Protection Mode Register Offset */
|
||||
|
||||
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
/** \brief EFC register API structure */
|
||||
typedef struct
|
||||
{
|
||||
__IO uint32_t EEFC_FMR; /**< Offset: 0x00 (R/W 32) EEFC Flash Mode Register */
|
||||
__O uint32_t EEFC_FCR; /**< Offset: 0x04 ( /W 32) EEFC Flash Command Register */
|
||||
__I uint32_t EEFC_FSR; /**< Offset: 0x08 (R/ 32) EEFC Flash Status Register */
|
||||
__I uint32_t EEFC_FRR; /**< Offset: 0x0C (R/ 32) EEFC Flash Result Register */
|
||||
__I uint8_t Reserved1[0xD4];
|
||||
__IO uint32_t EEFC_WPMR; /**< Offset: 0xE4 (R/W 32) Write Protection Mode Register */
|
||||
} efc_registers_t;
|
||||
|
||||
|
||||
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
#endif /* _SAME70_EFC_COMPONENT_H_ */
|
||||
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,50 @@
|
||||
/**
|
||||
* \brief Component description for GPBR
|
||||
*
|
||||
* Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries.
|
||||
*
|
||||
* Subject to your compliance with these terms, you may use Microchip software and any derivatives
|
||||
* exclusively with Microchip products. It is your responsibility to comply with third party license
|
||||
* terms applicable to your use of third party software (including open source software) that may
|
||||
* accompany Microchip software.
|
||||
*
|
||||
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY,
|
||||
* APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND
|
||||
* FITNESS FOR A PARTICULAR PURPOSE.
|
||||
*
|
||||
* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
|
||||
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF
|
||||
* MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
|
||||
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT
|
||||
* EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
|
||||
*
|
||||
*/
|
||||
|
||||
/* file generated from device description version 2017-08-25T14:00:00Z */
|
||||
#ifndef _SAME70_GPBR_COMPONENT_H_
|
||||
#define _SAME70_GPBR_COMPONENT_H_
|
||||
|
||||
/* ************************************************************************** */
|
||||
/* SOFTWARE API DEFINITION FOR GPBR */
|
||||
/* ************************************************************************** */
|
||||
|
||||
/* -------- SYS_GPBR : (GPBR Offset: 0x00) (R/W 32) General Purpose Backup Register 0 -------- */
|
||||
#define SYS_GPBR_GPBR_VALUE_Pos _U_(0) /**< (SYS_GPBR) Value of GPBR x Position */
|
||||
#define SYS_GPBR_GPBR_VALUE_Msk (_U_(0xFFFFFFFF) << SYS_GPBR_GPBR_VALUE_Pos) /**< (SYS_GPBR) Value of GPBR x Mask */
|
||||
#define SYS_GPBR_GPBR_VALUE(value) (SYS_GPBR_GPBR_VALUE_Msk & ((value) << SYS_GPBR_GPBR_VALUE_Pos))
|
||||
#define SYS_GPBR_Msk _U_(0xFFFFFFFF) /**< (SYS_GPBR) Register Mask */
|
||||
|
||||
|
||||
/** \brief GPBR register offsets definitions */
|
||||
#define SYS_GPBR_REG_OFST (0x00) /**< (SYS_GPBR) General Purpose Backup Register 0 Offset */
|
||||
|
||||
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
/** \brief GPBR register API structure */
|
||||
typedef struct
|
||||
{
|
||||
__IO uint32_t SYS_GPBR[8]; /**< Offset: 0x00 (R/W 32) General Purpose Backup Register 0 */
|
||||
} gpbr_registers_t;
|
||||
|
||||
|
||||
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
#endif /* _SAME70_GPBR_COMPONENT_H_ */
|
||||
@ -0,0 +1,704 @@
|
||||
/**
|
||||
* \brief Component description for HSMCI
|
||||
*
|
||||
* Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries.
|
||||
*
|
||||
* Subject to your compliance with these terms, you may use Microchip software and any derivatives
|
||||
* exclusively with Microchip products. It is your responsibility to comply with third party license
|
||||
* terms applicable to your use of third party software (including open source software) that may
|
||||
* accompany Microchip software.
|
||||
*
|
||||
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY,
|
||||
* APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND
|
||||
* FITNESS FOR A PARTICULAR PURPOSE.
|
||||
*
|
||||
* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
|
||||
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF
|
||||
* MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
|
||||
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT
|
||||
* EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
|
||||
*
|
||||
*/
|
||||
|
||||
/* file generated from device description version 2017-08-25T14:00:00Z */
|
||||
#ifndef _SAME70_HSMCI_COMPONENT_H_
|
||||
#define _SAME70_HSMCI_COMPONENT_H_
|
||||
|
||||
/* ************************************************************************** */
|
||||
/* SOFTWARE API DEFINITION FOR HSMCI */
|
||||
/* ************************************************************************** */
|
||||
|
||||
/* -------- HSMCI_CR : (HSMCI Offset: 0x00) ( /W 32) Control Register -------- */
|
||||
#define HSMCI_CR_MCIEN_Pos _U_(0) /**< (HSMCI_CR) Multi-Media Interface Enable Position */
|
||||
#define HSMCI_CR_MCIEN_Msk (_U_(0x1) << HSMCI_CR_MCIEN_Pos) /**< (HSMCI_CR) Multi-Media Interface Enable Mask */
|
||||
#define HSMCI_CR_MCIEN(value) (HSMCI_CR_MCIEN_Msk & ((value) << HSMCI_CR_MCIEN_Pos))
|
||||
#define HSMCI_CR_MCIDIS_Pos _U_(1) /**< (HSMCI_CR) Multi-Media Interface Disable Position */
|
||||
#define HSMCI_CR_MCIDIS_Msk (_U_(0x1) << HSMCI_CR_MCIDIS_Pos) /**< (HSMCI_CR) Multi-Media Interface Disable Mask */
|
||||
#define HSMCI_CR_MCIDIS(value) (HSMCI_CR_MCIDIS_Msk & ((value) << HSMCI_CR_MCIDIS_Pos))
|
||||
#define HSMCI_CR_PWSEN_Pos _U_(2) /**< (HSMCI_CR) Power Save Mode Enable Position */
|
||||
#define HSMCI_CR_PWSEN_Msk (_U_(0x1) << HSMCI_CR_PWSEN_Pos) /**< (HSMCI_CR) Power Save Mode Enable Mask */
|
||||
#define HSMCI_CR_PWSEN(value) (HSMCI_CR_PWSEN_Msk & ((value) << HSMCI_CR_PWSEN_Pos))
|
||||
#define HSMCI_CR_PWSDIS_Pos _U_(3) /**< (HSMCI_CR) Power Save Mode Disable Position */
|
||||
#define HSMCI_CR_PWSDIS_Msk (_U_(0x1) << HSMCI_CR_PWSDIS_Pos) /**< (HSMCI_CR) Power Save Mode Disable Mask */
|
||||
#define HSMCI_CR_PWSDIS(value) (HSMCI_CR_PWSDIS_Msk & ((value) << HSMCI_CR_PWSDIS_Pos))
|
||||
#define HSMCI_CR_SWRST_Pos _U_(7) /**< (HSMCI_CR) Software Reset Position */
|
||||
#define HSMCI_CR_SWRST_Msk (_U_(0x1) << HSMCI_CR_SWRST_Pos) /**< (HSMCI_CR) Software Reset Mask */
|
||||
#define HSMCI_CR_SWRST(value) (HSMCI_CR_SWRST_Msk & ((value) << HSMCI_CR_SWRST_Pos))
|
||||
#define HSMCI_CR_Msk _U_(0x0000008F) /**< (HSMCI_CR) Register Mask */
|
||||
|
||||
|
||||
/* -------- HSMCI_MR : (HSMCI Offset: 0x04) (R/W 32) Mode Register -------- */
|
||||
#define HSMCI_MR_CLKDIV_Pos _U_(0) /**< (HSMCI_MR) Clock Divider Position */
|
||||
#define HSMCI_MR_CLKDIV_Msk (_U_(0xFF) << HSMCI_MR_CLKDIV_Pos) /**< (HSMCI_MR) Clock Divider Mask */
|
||||
#define HSMCI_MR_CLKDIV(value) (HSMCI_MR_CLKDIV_Msk & ((value) << HSMCI_MR_CLKDIV_Pos))
|
||||
#define HSMCI_MR_PWSDIV_Pos _U_(8) /**< (HSMCI_MR) Power Saving Divider Position */
|
||||
#define HSMCI_MR_PWSDIV_Msk (_U_(0x7) << HSMCI_MR_PWSDIV_Pos) /**< (HSMCI_MR) Power Saving Divider Mask */
|
||||
#define HSMCI_MR_PWSDIV(value) (HSMCI_MR_PWSDIV_Msk & ((value) << HSMCI_MR_PWSDIV_Pos))
|
||||
#define HSMCI_MR_RDPROOF_Pos _U_(11) /**< (HSMCI_MR) Read Proof Enable Position */
|
||||
#define HSMCI_MR_RDPROOF_Msk (_U_(0x1) << HSMCI_MR_RDPROOF_Pos) /**< (HSMCI_MR) Read Proof Enable Mask */
|
||||
#define HSMCI_MR_RDPROOF(value) (HSMCI_MR_RDPROOF_Msk & ((value) << HSMCI_MR_RDPROOF_Pos))
|
||||
#define HSMCI_MR_WRPROOF_Pos _U_(12) /**< (HSMCI_MR) Write Proof Enable Position */
|
||||
#define HSMCI_MR_WRPROOF_Msk (_U_(0x1) << HSMCI_MR_WRPROOF_Pos) /**< (HSMCI_MR) Write Proof Enable Mask */
|
||||
#define HSMCI_MR_WRPROOF(value) (HSMCI_MR_WRPROOF_Msk & ((value) << HSMCI_MR_WRPROOF_Pos))
|
||||
#define HSMCI_MR_FBYTE_Pos _U_(13) /**< (HSMCI_MR) Force Byte Transfer Position */
|
||||
#define HSMCI_MR_FBYTE_Msk (_U_(0x1) << HSMCI_MR_FBYTE_Pos) /**< (HSMCI_MR) Force Byte Transfer Mask */
|
||||
#define HSMCI_MR_FBYTE(value) (HSMCI_MR_FBYTE_Msk & ((value) << HSMCI_MR_FBYTE_Pos))
|
||||
#define HSMCI_MR_PADV_Pos _U_(14) /**< (HSMCI_MR) Padding Value Position */
|
||||
#define HSMCI_MR_PADV_Msk (_U_(0x1) << HSMCI_MR_PADV_Pos) /**< (HSMCI_MR) Padding Value Mask */
|
||||
#define HSMCI_MR_PADV(value) (HSMCI_MR_PADV_Msk & ((value) << HSMCI_MR_PADV_Pos))
|
||||
#define HSMCI_MR_CLKODD_Pos _U_(16) /**< (HSMCI_MR) Clock divider is odd Position */
|
||||
#define HSMCI_MR_CLKODD_Msk (_U_(0x1) << HSMCI_MR_CLKODD_Pos) /**< (HSMCI_MR) Clock divider is odd Mask */
|
||||
#define HSMCI_MR_CLKODD(value) (HSMCI_MR_CLKODD_Msk & ((value) << HSMCI_MR_CLKODD_Pos))
|
||||
#define HSMCI_MR_Msk _U_(0x00017FFF) /**< (HSMCI_MR) Register Mask */
|
||||
|
||||
|
||||
/* -------- HSMCI_DTOR : (HSMCI Offset: 0x08) (R/W 32) Data Timeout Register -------- */
|
||||
#define HSMCI_DTOR_DTOCYC_Pos _U_(0) /**< (HSMCI_DTOR) Data Timeout Cycle Number Position */
|
||||
#define HSMCI_DTOR_DTOCYC_Msk (_U_(0xF) << HSMCI_DTOR_DTOCYC_Pos) /**< (HSMCI_DTOR) Data Timeout Cycle Number Mask */
|
||||
#define HSMCI_DTOR_DTOCYC(value) (HSMCI_DTOR_DTOCYC_Msk & ((value) << HSMCI_DTOR_DTOCYC_Pos))
|
||||
#define HSMCI_DTOR_DTOMUL_Pos _U_(4) /**< (HSMCI_DTOR) Data Timeout Multiplier Position */
|
||||
#define HSMCI_DTOR_DTOMUL_Msk (_U_(0x7) << HSMCI_DTOR_DTOMUL_Pos) /**< (HSMCI_DTOR) Data Timeout Multiplier Mask */
|
||||
#define HSMCI_DTOR_DTOMUL(value) (HSMCI_DTOR_DTOMUL_Msk & ((value) << HSMCI_DTOR_DTOMUL_Pos))
|
||||
#define HSMCI_DTOR_DTOMUL_1_Val _U_(0x0) /**< (HSMCI_DTOR) DTOCYC */
|
||||
#define HSMCI_DTOR_DTOMUL_16_Val _U_(0x1) /**< (HSMCI_DTOR) DTOCYC x 16 */
|
||||
#define HSMCI_DTOR_DTOMUL_128_Val _U_(0x2) /**< (HSMCI_DTOR) DTOCYC x 128 */
|
||||
#define HSMCI_DTOR_DTOMUL_256_Val _U_(0x3) /**< (HSMCI_DTOR) DTOCYC x 256 */
|
||||
#define HSMCI_DTOR_DTOMUL_1024_Val _U_(0x4) /**< (HSMCI_DTOR) DTOCYC x 1024 */
|
||||
#define HSMCI_DTOR_DTOMUL_4096_Val _U_(0x5) /**< (HSMCI_DTOR) DTOCYC x 4096 */
|
||||
#define HSMCI_DTOR_DTOMUL_65536_Val _U_(0x6) /**< (HSMCI_DTOR) DTOCYC x 65536 */
|
||||
#define HSMCI_DTOR_DTOMUL_1048576_Val _U_(0x7) /**< (HSMCI_DTOR) DTOCYC x 1048576 */
|
||||
#define HSMCI_DTOR_DTOMUL_1 (HSMCI_DTOR_DTOMUL_1_Val << HSMCI_DTOR_DTOMUL_Pos) /**< (HSMCI_DTOR) DTOCYC Position */
|
||||
#define HSMCI_DTOR_DTOMUL_16 (HSMCI_DTOR_DTOMUL_16_Val << HSMCI_DTOR_DTOMUL_Pos) /**< (HSMCI_DTOR) DTOCYC x 16 Position */
|
||||
#define HSMCI_DTOR_DTOMUL_128 (HSMCI_DTOR_DTOMUL_128_Val << HSMCI_DTOR_DTOMUL_Pos) /**< (HSMCI_DTOR) DTOCYC x 128 Position */
|
||||
#define HSMCI_DTOR_DTOMUL_256 (HSMCI_DTOR_DTOMUL_256_Val << HSMCI_DTOR_DTOMUL_Pos) /**< (HSMCI_DTOR) DTOCYC x 256 Position */
|
||||
#define HSMCI_DTOR_DTOMUL_1024 (HSMCI_DTOR_DTOMUL_1024_Val << HSMCI_DTOR_DTOMUL_Pos) /**< (HSMCI_DTOR) DTOCYC x 1024 Position */
|
||||
#define HSMCI_DTOR_DTOMUL_4096 (HSMCI_DTOR_DTOMUL_4096_Val << HSMCI_DTOR_DTOMUL_Pos) /**< (HSMCI_DTOR) DTOCYC x 4096 Position */
|
||||
#define HSMCI_DTOR_DTOMUL_65536 (HSMCI_DTOR_DTOMUL_65536_Val << HSMCI_DTOR_DTOMUL_Pos) /**< (HSMCI_DTOR) DTOCYC x 65536 Position */
|
||||
#define HSMCI_DTOR_DTOMUL_1048576 (HSMCI_DTOR_DTOMUL_1048576_Val << HSMCI_DTOR_DTOMUL_Pos) /**< (HSMCI_DTOR) DTOCYC x 1048576 Position */
|
||||
#define HSMCI_DTOR_Msk _U_(0x0000007F) /**< (HSMCI_DTOR) Register Mask */
|
||||
|
||||
|
||||
/* -------- HSMCI_SDCR : (HSMCI Offset: 0x0C) (R/W 32) SD/SDIO Card Register -------- */
|
||||
#define HSMCI_SDCR_SDCSEL_Pos _U_(0) /**< (HSMCI_SDCR) SDCard/SDIO Slot Position */
|
||||
#define HSMCI_SDCR_SDCSEL_Msk (_U_(0x3) << HSMCI_SDCR_SDCSEL_Pos) /**< (HSMCI_SDCR) SDCard/SDIO Slot Mask */
|
||||
#define HSMCI_SDCR_SDCSEL(value) (HSMCI_SDCR_SDCSEL_Msk & ((value) << HSMCI_SDCR_SDCSEL_Pos))
|
||||
#define HSMCI_SDCR_SDCSEL_SLOTA_Val _U_(0x0) /**< (HSMCI_SDCR) Slot A is selected. */
|
||||
#define HSMCI_SDCR_SDCSEL_SLOTA (HSMCI_SDCR_SDCSEL_SLOTA_Val << HSMCI_SDCR_SDCSEL_Pos) /**< (HSMCI_SDCR) Slot A is selected. Position */
|
||||
#define HSMCI_SDCR_SDCBUS_Pos _U_(6) /**< (HSMCI_SDCR) SDCard/SDIO Bus Width Position */
|
||||
#define HSMCI_SDCR_SDCBUS_Msk (_U_(0x3) << HSMCI_SDCR_SDCBUS_Pos) /**< (HSMCI_SDCR) SDCard/SDIO Bus Width Mask */
|
||||
#define HSMCI_SDCR_SDCBUS(value) (HSMCI_SDCR_SDCBUS_Msk & ((value) << HSMCI_SDCR_SDCBUS_Pos))
|
||||
#define HSMCI_SDCR_SDCBUS_1_Val _U_(0x0) /**< (HSMCI_SDCR) 1 bit */
|
||||
#define HSMCI_SDCR_SDCBUS_4_Val _U_(0x2) /**< (HSMCI_SDCR) 4 bits */
|
||||
#define HSMCI_SDCR_SDCBUS_8_Val _U_(0x3) /**< (HSMCI_SDCR) 8 bits */
|
||||
#define HSMCI_SDCR_SDCBUS_1 (HSMCI_SDCR_SDCBUS_1_Val << HSMCI_SDCR_SDCBUS_Pos) /**< (HSMCI_SDCR) 1 bit Position */
|
||||
#define HSMCI_SDCR_SDCBUS_4 (HSMCI_SDCR_SDCBUS_4_Val << HSMCI_SDCR_SDCBUS_Pos) /**< (HSMCI_SDCR) 4 bits Position */
|
||||
#define HSMCI_SDCR_SDCBUS_8 (HSMCI_SDCR_SDCBUS_8_Val << HSMCI_SDCR_SDCBUS_Pos) /**< (HSMCI_SDCR) 8 bits Position */
|
||||
#define HSMCI_SDCR_Msk _U_(0x000000C3) /**< (HSMCI_SDCR) Register Mask */
|
||||
|
||||
|
||||
/* -------- HSMCI_ARGR : (HSMCI Offset: 0x10) (R/W 32) Argument Register -------- */
|
||||
#define HSMCI_ARGR_ARG_Pos _U_(0) /**< (HSMCI_ARGR) Command Argument Position */
|
||||
#define HSMCI_ARGR_ARG_Msk (_U_(0xFFFFFFFF) << HSMCI_ARGR_ARG_Pos) /**< (HSMCI_ARGR) Command Argument Mask */
|
||||
#define HSMCI_ARGR_ARG(value) (HSMCI_ARGR_ARG_Msk & ((value) << HSMCI_ARGR_ARG_Pos))
|
||||
#define HSMCI_ARGR_Msk _U_(0xFFFFFFFF) /**< (HSMCI_ARGR) Register Mask */
|
||||
|
||||
|
||||
/* -------- HSMCI_CMDR : (HSMCI Offset: 0x14) ( /W 32) Command Register -------- */
|
||||
#define HSMCI_CMDR_CMDNB_Pos _U_(0) /**< (HSMCI_CMDR) Command Number Position */
|
||||
#define HSMCI_CMDR_CMDNB_Msk (_U_(0x3F) << HSMCI_CMDR_CMDNB_Pos) /**< (HSMCI_CMDR) Command Number Mask */
|
||||
#define HSMCI_CMDR_CMDNB(value) (HSMCI_CMDR_CMDNB_Msk & ((value) << HSMCI_CMDR_CMDNB_Pos))
|
||||
#define HSMCI_CMDR_RSPTYP_Pos _U_(6) /**< (HSMCI_CMDR) Response Type Position */
|
||||
#define HSMCI_CMDR_RSPTYP_Msk (_U_(0x3) << HSMCI_CMDR_RSPTYP_Pos) /**< (HSMCI_CMDR) Response Type Mask */
|
||||
#define HSMCI_CMDR_RSPTYP(value) (HSMCI_CMDR_RSPTYP_Msk & ((value) << HSMCI_CMDR_RSPTYP_Pos))
|
||||
#define HSMCI_CMDR_RSPTYP_NORESP_Val _U_(0x0) /**< (HSMCI_CMDR) No response */
|
||||
#define HSMCI_CMDR_RSPTYP_48_BIT_Val _U_(0x1) /**< (HSMCI_CMDR) 48-bit response */
|
||||
#define HSMCI_CMDR_RSPTYP_136_BIT_Val _U_(0x2) /**< (HSMCI_CMDR) 136-bit response */
|
||||
#define HSMCI_CMDR_RSPTYP_R1B_Val _U_(0x3) /**< (HSMCI_CMDR) R1b response type */
|
||||
#define HSMCI_CMDR_RSPTYP_NORESP (HSMCI_CMDR_RSPTYP_NORESP_Val << HSMCI_CMDR_RSPTYP_Pos) /**< (HSMCI_CMDR) No response Position */
|
||||
#define HSMCI_CMDR_RSPTYP_48_BIT (HSMCI_CMDR_RSPTYP_48_BIT_Val << HSMCI_CMDR_RSPTYP_Pos) /**< (HSMCI_CMDR) 48-bit response Position */
|
||||
#define HSMCI_CMDR_RSPTYP_136_BIT (HSMCI_CMDR_RSPTYP_136_BIT_Val << HSMCI_CMDR_RSPTYP_Pos) /**< (HSMCI_CMDR) 136-bit response Position */
|
||||
#define HSMCI_CMDR_RSPTYP_R1B (HSMCI_CMDR_RSPTYP_R1B_Val << HSMCI_CMDR_RSPTYP_Pos) /**< (HSMCI_CMDR) R1b response type Position */
|
||||
#define HSMCI_CMDR_SPCMD_Pos _U_(8) /**< (HSMCI_CMDR) Special Command Position */
|
||||
#define HSMCI_CMDR_SPCMD_Msk (_U_(0x7) << HSMCI_CMDR_SPCMD_Pos) /**< (HSMCI_CMDR) Special Command Mask */
|
||||
#define HSMCI_CMDR_SPCMD(value) (HSMCI_CMDR_SPCMD_Msk & ((value) << HSMCI_CMDR_SPCMD_Pos))
|
||||
#define HSMCI_CMDR_SPCMD_STD_Val _U_(0x0) /**< (HSMCI_CMDR) Not a special CMD. */
|
||||
#define HSMCI_CMDR_SPCMD_INIT_Val _U_(0x1) /**< (HSMCI_CMDR) Initialization CMD: 74 clock cycles for initialization sequence. */
|
||||
#define HSMCI_CMDR_SPCMD_SYNC_Val _U_(0x2) /**< (HSMCI_CMDR) Synchronized CMD: Wait for the end of the current data block transfer before sending the pending command. */
|
||||
#define HSMCI_CMDR_SPCMD_CE_ATA_Val _U_(0x3) /**< (HSMCI_CMDR) CE-ATA Completion Signal disable Command. The host cancels the ability for the device to return a command completion signal on the command line. */
|
||||
#define HSMCI_CMDR_SPCMD_IT_CMD_Val _U_(0x4) /**< (HSMCI_CMDR) Interrupt command: Corresponds to the Interrupt Mode (CMD40). */
|
||||
#define HSMCI_CMDR_SPCMD_IT_RESP_Val _U_(0x5) /**< (HSMCI_CMDR) Interrupt response: Corresponds to the Interrupt Mode (CMD40). */
|
||||
#define HSMCI_CMDR_SPCMD_BOR_Val _U_(0x6) /**< (HSMCI_CMDR) Boot Operation Request. Start a boot operation mode, the host processor can read boot data from the MMC device directly. */
|
||||
#define HSMCI_CMDR_SPCMD_EBO_Val _U_(0x7) /**< (HSMCI_CMDR) End Boot Operation. This command allows the host processor to terminate the boot operation mode. */
|
||||
#define HSMCI_CMDR_SPCMD_STD (HSMCI_CMDR_SPCMD_STD_Val << HSMCI_CMDR_SPCMD_Pos) /**< (HSMCI_CMDR) Not a special CMD. Position */
|
||||
#define HSMCI_CMDR_SPCMD_INIT (HSMCI_CMDR_SPCMD_INIT_Val << HSMCI_CMDR_SPCMD_Pos) /**< (HSMCI_CMDR) Initialization CMD: 74 clock cycles for initialization sequence. Position */
|
||||
#define HSMCI_CMDR_SPCMD_SYNC (HSMCI_CMDR_SPCMD_SYNC_Val << HSMCI_CMDR_SPCMD_Pos) /**< (HSMCI_CMDR) Synchronized CMD: Wait for the end of the current data block transfer before sending the pending command. Position */
|
||||
#define HSMCI_CMDR_SPCMD_CE_ATA (HSMCI_CMDR_SPCMD_CE_ATA_Val << HSMCI_CMDR_SPCMD_Pos) /**< (HSMCI_CMDR) CE-ATA Completion Signal disable Command. The host cancels the ability for the device to return a command completion signal on the command line. Position */
|
||||
#define HSMCI_CMDR_SPCMD_IT_CMD (HSMCI_CMDR_SPCMD_IT_CMD_Val << HSMCI_CMDR_SPCMD_Pos) /**< (HSMCI_CMDR) Interrupt command: Corresponds to the Interrupt Mode (CMD40). Position */
|
||||
#define HSMCI_CMDR_SPCMD_IT_RESP (HSMCI_CMDR_SPCMD_IT_RESP_Val << HSMCI_CMDR_SPCMD_Pos) /**< (HSMCI_CMDR) Interrupt response: Corresponds to the Interrupt Mode (CMD40). Position */
|
||||
#define HSMCI_CMDR_SPCMD_BOR (HSMCI_CMDR_SPCMD_BOR_Val << HSMCI_CMDR_SPCMD_Pos) /**< (HSMCI_CMDR) Boot Operation Request. Start a boot operation mode, the host processor can read boot data from the MMC device directly. Position */
|
||||
#define HSMCI_CMDR_SPCMD_EBO (HSMCI_CMDR_SPCMD_EBO_Val << HSMCI_CMDR_SPCMD_Pos) /**< (HSMCI_CMDR) End Boot Operation. This command allows the host processor to terminate the boot operation mode. Position */
|
||||
#define HSMCI_CMDR_OPDCMD_Pos _U_(11) /**< (HSMCI_CMDR) Open Drain Command Position */
|
||||
#define HSMCI_CMDR_OPDCMD_Msk (_U_(0x1) << HSMCI_CMDR_OPDCMD_Pos) /**< (HSMCI_CMDR) Open Drain Command Mask */
|
||||
#define HSMCI_CMDR_OPDCMD(value) (HSMCI_CMDR_OPDCMD_Msk & ((value) << HSMCI_CMDR_OPDCMD_Pos))
|
||||
#define HSMCI_CMDR_OPDCMD_PUSHPULL_Val _U_(0x0) /**< (HSMCI_CMDR) Push pull command. */
|
||||
#define HSMCI_CMDR_OPDCMD_OPENDRAIN_Val _U_(0x1) /**< (HSMCI_CMDR) Open drain command. */
|
||||
#define HSMCI_CMDR_OPDCMD_PUSHPULL (HSMCI_CMDR_OPDCMD_PUSHPULL_Val << HSMCI_CMDR_OPDCMD_Pos) /**< (HSMCI_CMDR) Push pull command. Position */
|
||||
#define HSMCI_CMDR_OPDCMD_OPENDRAIN (HSMCI_CMDR_OPDCMD_OPENDRAIN_Val << HSMCI_CMDR_OPDCMD_Pos) /**< (HSMCI_CMDR) Open drain command. Position */
|
||||
#define HSMCI_CMDR_MAXLAT_Pos _U_(12) /**< (HSMCI_CMDR) Max Latency for Command to Response Position */
|
||||
#define HSMCI_CMDR_MAXLAT_Msk (_U_(0x1) << HSMCI_CMDR_MAXLAT_Pos) /**< (HSMCI_CMDR) Max Latency for Command to Response Mask */
|
||||
#define HSMCI_CMDR_MAXLAT(value) (HSMCI_CMDR_MAXLAT_Msk & ((value) << HSMCI_CMDR_MAXLAT_Pos))
|
||||
#define HSMCI_CMDR_MAXLAT_5_Val _U_(0x0) /**< (HSMCI_CMDR) 5-cycle max latency. */
|
||||
#define HSMCI_CMDR_MAXLAT_64_Val _U_(0x1) /**< (HSMCI_CMDR) 64-cycle max latency. */
|
||||
#define HSMCI_CMDR_MAXLAT_5 (HSMCI_CMDR_MAXLAT_5_Val << HSMCI_CMDR_MAXLAT_Pos) /**< (HSMCI_CMDR) 5-cycle max latency. Position */
|
||||
#define HSMCI_CMDR_MAXLAT_64 (HSMCI_CMDR_MAXLAT_64_Val << HSMCI_CMDR_MAXLAT_Pos) /**< (HSMCI_CMDR) 64-cycle max latency. Position */
|
||||
#define HSMCI_CMDR_TRCMD_Pos _U_(16) /**< (HSMCI_CMDR) Transfer Command Position */
|
||||
#define HSMCI_CMDR_TRCMD_Msk (_U_(0x3) << HSMCI_CMDR_TRCMD_Pos) /**< (HSMCI_CMDR) Transfer Command Mask */
|
||||
#define HSMCI_CMDR_TRCMD(value) (HSMCI_CMDR_TRCMD_Msk & ((value) << HSMCI_CMDR_TRCMD_Pos))
|
||||
#define HSMCI_CMDR_TRCMD_NO_DATA_Val _U_(0x0) /**< (HSMCI_CMDR) No data transfer */
|
||||
#define HSMCI_CMDR_TRCMD_START_DATA_Val _U_(0x1) /**< (HSMCI_CMDR) Start data transfer */
|
||||
#define HSMCI_CMDR_TRCMD_STOP_DATA_Val _U_(0x2) /**< (HSMCI_CMDR) Stop data transfer */
|
||||
#define HSMCI_CMDR_TRCMD_NO_DATA (HSMCI_CMDR_TRCMD_NO_DATA_Val << HSMCI_CMDR_TRCMD_Pos) /**< (HSMCI_CMDR) No data transfer Position */
|
||||
#define HSMCI_CMDR_TRCMD_START_DATA (HSMCI_CMDR_TRCMD_START_DATA_Val << HSMCI_CMDR_TRCMD_Pos) /**< (HSMCI_CMDR) Start data transfer Position */
|
||||
#define HSMCI_CMDR_TRCMD_STOP_DATA (HSMCI_CMDR_TRCMD_STOP_DATA_Val << HSMCI_CMDR_TRCMD_Pos) /**< (HSMCI_CMDR) Stop data transfer Position */
|
||||
#define HSMCI_CMDR_TRDIR_Pos _U_(18) /**< (HSMCI_CMDR) Transfer Direction Position */
|
||||
#define HSMCI_CMDR_TRDIR_Msk (_U_(0x1) << HSMCI_CMDR_TRDIR_Pos) /**< (HSMCI_CMDR) Transfer Direction Mask */
|
||||
#define HSMCI_CMDR_TRDIR(value) (HSMCI_CMDR_TRDIR_Msk & ((value) << HSMCI_CMDR_TRDIR_Pos))
|
||||
#define HSMCI_CMDR_TRDIR_WRITE_Val _U_(0x0) /**< (HSMCI_CMDR) Write. */
|
||||
#define HSMCI_CMDR_TRDIR_READ_Val _U_(0x1) /**< (HSMCI_CMDR) Read. */
|
||||
#define HSMCI_CMDR_TRDIR_WRITE (HSMCI_CMDR_TRDIR_WRITE_Val << HSMCI_CMDR_TRDIR_Pos) /**< (HSMCI_CMDR) Write. Position */
|
||||
#define HSMCI_CMDR_TRDIR_READ (HSMCI_CMDR_TRDIR_READ_Val << HSMCI_CMDR_TRDIR_Pos) /**< (HSMCI_CMDR) Read. Position */
|
||||
#define HSMCI_CMDR_TRTYP_Pos _U_(19) /**< (HSMCI_CMDR) Transfer Type Position */
|
||||
#define HSMCI_CMDR_TRTYP_Msk (_U_(0x7) << HSMCI_CMDR_TRTYP_Pos) /**< (HSMCI_CMDR) Transfer Type Mask */
|
||||
#define HSMCI_CMDR_TRTYP(value) (HSMCI_CMDR_TRTYP_Msk & ((value) << HSMCI_CMDR_TRTYP_Pos))
|
||||
#define HSMCI_CMDR_TRTYP_SINGLE_Val _U_(0x0) /**< (HSMCI_CMDR) MMC/SD Card Single Block */
|
||||
#define HSMCI_CMDR_TRTYP_MULTIPLE_Val _U_(0x1) /**< (HSMCI_CMDR) MMC/SD Card Multiple Block */
|
||||
#define HSMCI_CMDR_TRTYP_STREAM_Val _U_(0x2) /**< (HSMCI_CMDR) MMC Stream */
|
||||
#define HSMCI_CMDR_TRTYP_BYTE_Val _U_(0x4) /**< (HSMCI_CMDR) SDIO Byte */
|
||||
#define HSMCI_CMDR_TRTYP_BLOCK_Val _U_(0x5) /**< (HSMCI_CMDR) SDIO Block */
|
||||
#define HSMCI_CMDR_TRTYP_SINGLE (HSMCI_CMDR_TRTYP_SINGLE_Val << HSMCI_CMDR_TRTYP_Pos) /**< (HSMCI_CMDR) MMC/SD Card Single Block Position */
|
||||
#define HSMCI_CMDR_TRTYP_MULTIPLE (HSMCI_CMDR_TRTYP_MULTIPLE_Val << HSMCI_CMDR_TRTYP_Pos) /**< (HSMCI_CMDR) MMC/SD Card Multiple Block Position */
|
||||
#define HSMCI_CMDR_TRTYP_STREAM (HSMCI_CMDR_TRTYP_STREAM_Val << HSMCI_CMDR_TRTYP_Pos) /**< (HSMCI_CMDR) MMC Stream Position */
|
||||
#define HSMCI_CMDR_TRTYP_BYTE (HSMCI_CMDR_TRTYP_BYTE_Val << HSMCI_CMDR_TRTYP_Pos) /**< (HSMCI_CMDR) SDIO Byte Position */
|
||||
#define HSMCI_CMDR_TRTYP_BLOCK (HSMCI_CMDR_TRTYP_BLOCK_Val << HSMCI_CMDR_TRTYP_Pos) /**< (HSMCI_CMDR) SDIO Block Position */
|
||||
#define HSMCI_CMDR_IOSPCMD_Pos _U_(24) /**< (HSMCI_CMDR) SDIO Special Command Position */
|
||||
#define HSMCI_CMDR_IOSPCMD_Msk (_U_(0x3) << HSMCI_CMDR_IOSPCMD_Pos) /**< (HSMCI_CMDR) SDIO Special Command Mask */
|
||||
#define HSMCI_CMDR_IOSPCMD(value) (HSMCI_CMDR_IOSPCMD_Msk & ((value) << HSMCI_CMDR_IOSPCMD_Pos))
|
||||
#define HSMCI_CMDR_IOSPCMD_STD_Val _U_(0x0) /**< (HSMCI_CMDR) Not an SDIO Special Command */
|
||||
#define HSMCI_CMDR_IOSPCMD_SUSPEND_Val _U_(0x1) /**< (HSMCI_CMDR) SDIO Suspend Command */
|
||||
#define HSMCI_CMDR_IOSPCMD_RESUME_Val _U_(0x2) /**< (HSMCI_CMDR) SDIO Resume Command */
|
||||
#define HSMCI_CMDR_IOSPCMD_STD (HSMCI_CMDR_IOSPCMD_STD_Val << HSMCI_CMDR_IOSPCMD_Pos) /**< (HSMCI_CMDR) Not an SDIO Special Command Position */
|
||||
#define HSMCI_CMDR_IOSPCMD_SUSPEND (HSMCI_CMDR_IOSPCMD_SUSPEND_Val << HSMCI_CMDR_IOSPCMD_Pos) /**< (HSMCI_CMDR) SDIO Suspend Command Position */
|
||||
#define HSMCI_CMDR_IOSPCMD_RESUME (HSMCI_CMDR_IOSPCMD_RESUME_Val << HSMCI_CMDR_IOSPCMD_Pos) /**< (HSMCI_CMDR) SDIO Resume Command Position */
|
||||
#define HSMCI_CMDR_ATACS_Pos _U_(26) /**< (HSMCI_CMDR) ATA with Command Completion Signal Position */
|
||||
#define HSMCI_CMDR_ATACS_Msk (_U_(0x1) << HSMCI_CMDR_ATACS_Pos) /**< (HSMCI_CMDR) ATA with Command Completion Signal Mask */
|
||||
#define HSMCI_CMDR_ATACS(value) (HSMCI_CMDR_ATACS_Msk & ((value) << HSMCI_CMDR_ATACS_Pos))
|
||||
#define HSMCI_CMDR_ATACS_NORMAL_Val _U_(0x0) /**< (HSMCI_CMDR) Normal operation mode. */
|
||||
#define HSMCI_CMDR_ATACS_COMPLETION_Val _U_(0x1) /**< (HSMCI_CMDR) This bit indicates that a completion signal is expected within a programmed amount of time (HSMCI_CSTOR). */
|
||||
#define HSMCI_CMDR_ATACS_NORMAL (HSMCI_CMDR_ATACS_NORMAL_Val << HSMCI_CMDR_ATACS_Pos) /**< (HSMCI_CMDR) Normal operation mode. Position */
|
||||
#define HSMCI_CMDR_ATACS_COMPLETION (HSMCI_CMDR_ATACS_COMPLETION_Val << HSMCI_CMDR_ATACS_Pos) /**< (HSMCI_CMDR) This bit indicates that a completion signal is expected within a programmed amount of time (HSMCI_CSTOR). Position */
|
||||
#define HSMCI_CMDR_BOOT_ACK_Pos _U_(27) /**< (HSMCI_CMDR) Boot Operation Acknowledge Position */
|
||||
#define HSMCI_CMDR_BOOT_ACK_Msk (_U_(0x1) << HSMCI_CMDR_BOOT_ACK_Pos) /**< (HSMCI_CMDR) Boot Operation Acknowledge Mask */
|
||||
#define HSMCI_CMDR_BOOT_ACK(value) (HSMCI_CMDR_BOOT_ACK_Msk & ((value) << HSMCI_CMDR_BOOT_ACK_Pos))
|
||||
#define HSMCI_CMDR_Msk _U_(0x0F3F1FFF) /**< (HSMCI_CMDR) Register Mask */
|
||||
|
||||
|
||||
/* -------- HSMCI_BLKR : (HSMCI Offset: 0x18) (R/W 32) Block Register -------- */
|
||||
#define HSMCI_BLKR_BCNT_Pos _U_(0) /**< (HSMCI_BLKR) MMC/SDIO Block Count - SDIO Byte Count Position */
|
||||
#define HSMCI_BLKR_BCNT_Msk (_U_(0xFFFF) << HSMCI_BLKR_BCNT_Pos) /**< (HSMCI_BLKR) MMC/SDIO Block Count - SDIO Byte Count Mask */
|
||||
#define HSMCI_BLKR_BCNT(value) (HSMCI_BLKR_BCNT_Msk & ((value) << HSMCI_BLKR_BCNT_Pos))
|
||||
#define HSMCI_BLKR_BLKLEN_Pos _U_(16) /**< (HSMCI_BLKR) Data Block Length Position */
|
||||
#define HSMCI_BLKR_BLKLEN_Msk (_U_(0xFFFF) << HSMCI_BLKR_BLKLEN_Pos) /**< (HSMCI_BLKR) Data Block Length Mask */
|
||||
#define HSMCI_BLKR_BLKLEN(value) (HSMCI_BLKR_BLKLEN_Msk & ((value) << HSMCI_BLKR_BLKLEN_Pos))
|
||||
#define HSMCI_BLKR_Msk _U_(0xFFFFFFFF) /**< (HSMCI_BLKR) Register Mask */
|
||||
|
||||
|
||||
/* -------- HSMCI_CSTOR : (HSMCI Offset: 0x1C) (R/W 32) Completion Signal Timeout Register -------- */
|
||||
#define HSMCI_CSTOR_CSTOCYC_Pos _U_(0) /**< (HSMCI_CSTOR) Completion Signal Timeout Cycle Number Position */
|
||||
#define HSMCI_CSTOR_CSTOCYC_Msk (_U_(0xF) << HSMCI_CSTOR_CSTOCYC_Pos) /**< (HSMCI_CSTOR) Completion Signal Timeout Cycle Number Mask */
|
||||
#define HSMCI_CSTOR_CSTOCYC(value) (HSMCI_CSTOR_CSTOCYC_Msk & ((value) << HSMCI_CSTOR_CSTOCYC_Pos))
|
||||
#define HSMCI_CSTOR_CSTOMUL_Pos _U_(4) /**< (HSMCI_CSTOR) Completion Signal Timeout Multiplier Position */
|
||||
#define HSMCI_CSTOR_CSTOMUL_Msk (_U_(0x7) << HSMCI_CSTOR_CSTOMUL_Pos) /**< (HSMCI_CSTOR) Completion Signal Timeout Multiplier Mask */
|
||||
#define HSMCI_CSTOR_CSTOMUL(value) (HSMCI_CSTOR_CSTOMUL_Msk & ((value) << HSMCI_CSTOR_CSTOMUL_Pos))
|
||||
#define HSMCI_CSTOR_CSTOMUL_1_Val _U_(0x0) /**< (HSMCI_CSTOR) CSTOCYC x 1 */
|
||||
#define HSMCI_CSTOR_CSTOMUL_16_Val _U_(0x1) /**< (HSMCI_CSTOR) CSTOCYC x 16 */
|
||||
#define HSMCI_CSTOR_CSTOMUL_128_Val _U_(0x2) /**< (HSMCI_CSTOR) CSTOCYC x 128 */
|
||||
#define HSMCI_CSTOR_CSTOMUL_256_Val _U_(0x3) /**< (HSMCI_CSTOR) CSTOCYC x 256 */
|
||||
#define HSMCI_CSTOR_CSTOMUL_1024_Val _U_(0x4) /**< (HSMCI_CSTOR) CSTOCYC x 1024 */
|
||||
#define HSMCI_CSTOR_CSTOMUL_4096_Val _U_(0x5) /**< (HSMCI_CSTOR) CSTOCYC x 4096 */
|
||||
#define HSMCI_CSTOR_CSTOMUL_65536_Val _U_(0x6) /**< (HSMCI_CSTOR) CSTOCYC x 65536 */
|
||||
#define HSMCI_CSTOR_CSTOMUL_1048576_Val _U_(0x7) /**< (HSMCI_CSTOR) CSTOCYC x 1048576 */
|
||||
#define HSMCI_CSTOR_CSTOMUL_1 (HSMCI_CSTOR_CSTOMUL_1_Val << HSMCI_CSTOR_CSTOMUL_Pos) /**< (HSMCI_CSTOR) CSTOCYC x 1 Position */
|
||||
#define HSMCI_CSTOR_CSTOMUL_16 (HSMCI_CSTOR_CSTOMUL_16_Val << HSMCI_CSTOR_CSTOMUL_Pos) /**< (HSMCI_CSTOR) CSTOCYC x 16 Position */
|
||||
#define HSMCI_CSTOR_CSTOMUL_128 (HSMCI_CSTOR_CSTOMUL_128_Val << HSMCI_CSTOR_CSTOMUL_Pos) /**< (HSMCI_CSTOR) CSTOCYC x 128 Position */
|
||||
#define HSMCI_CSTOR_CSTOMUL_256 (HSMCI_CSTOR_CSTOMUL_256_Val << HSMCI_CSTOR_CSTOMUL_Pos) /**< (HSMCI_CSTOR) CSTOCYC x 256 Position */
|
||||
#define HSMCI_CSTOR_CSTOMUL_1024 (HSMCI_CSTOR_CSTOMUL_1024_Val << HSMCI_CSTOR_CSTOMUL_Pos) /**< (HSMCI_CSTOR) CSTOCYC x 1024 Position */
|
||||
#define HSMCI_CSTOR_CSTOMUL_4096 (HSMCI_CSTOR_CSTOMUL_4096_Val << HSMCI_CSTOR_CSTOMUL_Pos) /**< (HSMCI_CSTOR) CSTOCYC x 4096 Position */
|
||||
#define HSMCI_CSTOR_CSTOMUL_65536 (HSMCI_CSTOR_CSTOMUL_65536_Val << HSMCI_CSTOR_CSTOMUL_Pos) /**< (HSMCI_CSTOR) CSTOCYC x 65536 Position */
|
||||
#define HSMCI_CSTOR_CSTOMUL_1048576 (HSMCI_CSTOR_CSTOMUL_1048576_Val << HSMCI_CSTOR_CSTOMUL_Pos) /**< (HSMCI_CSTOR) CSTOCYC x 1048576 Position */
|
||||
#define HSMCI_CSTOR_Msk _U_(0x0000007F) /**< (HSMCI_CSTOR) Register Mask */
|
||||
|
||||
|
||||
/* -------- HSMCI_RSPR : (HSMCI Offset: 0x20) ( R/ 32) Response Register 0 -------- */
|
||||
#define HSMCI_RSPR_RSP_Pos _U_(0) /**< (HSMCI_RSPR) Response Position */
|
||||
#define HSMCI_RSPR_RSP_Msk (_U_(0xFFFFFFFF) << HSMCI_RSPR_RSP_Pos) /**< (HSMCI_RSPR) Response Mask */
|
||||
#define HSMCI_RSPR_RSP(value) (HSMCI_RSPR_RSP_Msk & ((value) << HSMCI_RSPR_RSP_Pos))
|
||||
#define HSMCI_RSPR_Msk _U_(0xFFFFFFFF) /**< (HSMCI_RSPR) Register Mask */
|
||||
|
||||
|
||||
/* -------- HSMCI_RDR : (HSMCI Offset: 0x30) ( R/ 32) Receive Data Register -------- */
|
||||
#define HSMCI_RDR_DATA_Pos _U_(0) /**< (HSMCI_RDR) Data to Read Position */
|
||||
#define HSMCI_RDR_DATA_Msk (_U_(0xFFFFFFFF) << HSMCI_RDR_DATA_Pos) /**< (HSMCI_RDR) Data to Read Mask */
|
||||
#define HSMCI_RDR_DATA(value) (HSMCI_RDR_DATA_Msk & ((value) << HSMCI_RDR_DATA_Pos))
|
||||
#define HSMCI_RDR_Msk _U_(0xFFFFFFFF) /**< (HSMCI_RDR) Register Mask */
|
||||
|
||||
|
||||
/* -------- HSMCI_TDR : (HSMCI Offset: 0x34) ( /W 32) Transmit Data Register -------- */
|
||||
#define HSMCI_TDR_DATA_Pos _U_(0) /**< (HSMCI_TDR) Data to Write Position */
|
||||
#define HSMCI_TDR_DATA_Msk (_U_(0xFFFFFFFF) << HSMCI_TDR_DATA_Pos) /**< (HSMCI_TDR) Data to Write Mask */
|
||||
#define HSMCI_TDR_DATA(value) (HSMCI_TDR_DATA_Msk & ((value) << HSMCI_TDR_DATA_Pos))
|
||||
#define HSMCI_TDR_Msk _U_(0xFFFFFFFF) /**< (HSMCI_TDR) Register Mask */
|
||||
|
||||
|
||||
/* -------- HSMCI_SR : (HSMCI Offset: 0x40) ( R/ 32) Status Register -------- */
|
||||
#define HSMCI_SR_CMDRDY_Pos _U_(0) /**< (HSMCI_SR) Command Ready (cleared by writing in HSMCI_CMDR) Position */
|
||||
#define HSMCI_SR_CMDRDY_Msk (_U_(0x1) << HSMCI_SR_CMDRDY_Pos) /**< (HSMCI_SR) Command Ready (cleared by writing in HSMCI_CMDR) Mask */
|
||||
#define HSMCI_SR_CMDRDY(value) (HSMCI_SR_CMDRDY_Msk & ((value) << HSMCI_SR_CMDRDY_Pos))
|
||||
#define HSMCI_SR_RXRDY_Pos _U_(1) /**< (HSMCI_SR) Receiver Ready (cleared by reading HSMCI_RDR) Position */
|
||||
#define HSMCI_SR_RXRDY_Msk (_U_(0x1) << HSMCI_SR_RXRDY_Pos) /**< (HSMCI_SR) Receiver Ready (cleared by reading HSMCI_RDR) Mask */
|
||||
#define HSMCI_SR_RXRDY(value) (HSMCI_SR_RXRDY_Msk & ((value) << HSMCI_SR_RXRDY_Pos))
|
||||
#define HSMCI_SR_TXRDY_Pos _U_(2) /**< (HSMCI_SR) Transmit Ready (cleared by writing in HSMCI_TDR) Position */
|
||||
#define HSMCI_SR_TXRDY_Msk (_U_(0x1) << HSMCI_SR_TXRDY_Pos) /**< (HSMCI_SR) Transmit Ready (cleared by writing in HSMCI_TDR) Mask */
|
||||
#define HSMCI_SR_TXRDY(value) (HSMCI_SR_TXRDY_Msk & ((value) << HSMCI_SR_TXRDY_Pos))
|
||||
#define HSMCI_SR_BLKE_Pos _U_(3) /**< (HSMCI_SR) Data Block Ended (cleared on read) Position */
|
||||
#define HSMCI_SR_BLKE_Msk (_U_(0x1) << HSMCI_SR_BLKE_Pos) /**< (HSMCI_SR) Data Block Ended (cleared on read) Mask */
|
||||
#define HSMCI_SR_BLKE(value) (HSMCI_SR_BLKE_Msk & ((value) << HSMCI_SR_BLKE_Pos))
|
||||
#define HSMCI_SR_DTIP_Pos _U_(4) /**< (HSMCI_SR) Data Transfer in Progress (cleared at the end of CRC16 calculation) Position */
|
||||
#define HSMCI_SR_DTIP_Msk (_U_(0x1) << HSMCI_SR_DTIP_Pos) /**< (HSMCI_SR) Data Transfer in Progress (cleared at the end of CRC16 calculation) Mask */
|
||||
#define HSMCI_SR_DTIP(value) (HSMCI_SR_DTIP_Msk & ((value) << HSMCI_SR_DTIP_Pos))
|
||||
#define HSMCI_SR_NOTBUSY_Pos _U_(5) /**< (HSMCI_SR) HSMCI Not Busy Position */
|
||||
#define HSMCI_SR_NOTBUSY_Msk (_U_(0x1) << HSMCI_SR_NOTBUSY_Pos) /**< (HSMCI_SR) HSMCI Not Busy Mask */
|
||||
#define HSMCI_SR_NOTBUSY(value) (HSMCI_SR_NOTBUSY_Msk & ((value) << HSMCI_SR_NOTBUSY_Pos))
|
||||
#define HSMCI_SR_SDIOIRQA_Pos _U_(8) /**< (HSMCI_SR) SDIO Interrupt for Slot A (cleared on read) Position */
|
||||
#define HSMCI_SR_SDIOIRQA_Msk (_U_(0x1) << HSMCI_SR_SDIOIRQA_Pos) /**< (HSMCI_SR) SDIO Interrupt for Slot A (cleared on read) Mask */
|
||||
#define HSMCI_SR_SDIOIRQA(value) (HSMCI_SR_SDIOIRQA_Msk & ((value) << HSMCI_SR_SDIOIRQA_Pos))
|
||||
#define HSMCI_SR_SDIOWAIT_Pos _U_(12) /**< (HSMCI_SR) SDIO Read Wait Operation Status Position */
|
||||
#define HSMCI_SR_SDIOWAIT_Msk (_U_(0x1) << HSMCI_SR_SDIOWAIT_Pos) /**< (HSMCI_SR) SDIO Read Wait Operation Status Mask */
|
||||
#define HSMCI_SR_SDIOWAIT(value) (HSMCI_SR_SDIOWAIT_Msk & ((value) << HSMCI_SR_SDIOWAIT_Pos))
|
||||
#define HSMCI_SR_CSRCV_Pos _U_(13) /**< (HSMCI_SR) CE-ATA Completion Signal Received (cleared on read) Position */
|
||||
#define HSMCI_SR_CSRCV_Msk (_U_(0x1) << HSMCI_SR_CSRCV_Pos) /**< (HSMCI_SR) CE-ATA Completion Signal Received (cleared on read) Mask */
|
||||
#define HSMCI_SR_CSRCV(value) (HSMCI_SR_CSRCV_Msk & ((value) << HSMCI_SR_CSRCV_Pos))
|
||||
#define HSMCI_SR_RINDE_Pos _U_(16) /**< (HSMCI_SR) Response Index Error (cleared by writing in HSMCI_CMDR) Position */
|
||||
#define HSMCI_SR_RINDE_Msk (_U_(0x1) << HSMCI_SR_RINDE_Pos) /**< (HSMCI_SR) Response Index Error (cleared by writing in HSMCI_CMDR) Mask */
|
||||
#define HSMCI_SR_RINDE(value) (HSMCI_SR_RINDE_Msk & ((value) << HSMCI_SR_RINDE_Pos))
|
||||
#define HSMCI_SR_RDIRE_Pos _U_(17) /**< (HSMCI_SR) Response Direction Error (cleared by writing in HSMCI_CMDR) Position */
|
||||
#define HSMCI_SR_RDIRE_Msk (_U_(0x1) << HSMCI_SR_RDIRE_Pos) /**< (HSMCI_SR) Response Direction Error (cleared by writing in HSMCI_CMDR) Mask */
|
||||
#define HSMCI_SR_RDIRE(value) (HSMCI_SR_RDIRE_Msk & ((value) << HSMCI_SR_RDIRE_Pos))
|
||||
#define HSMCI_SR_RCRCE_Pos _U_(18) /**< (HSMCI_SR) Response CRC Error (cleared by writing in HSMCI_CMDR) Position */
|
||||
#define HSMCI_SR_RCRCE_Msk (_U_(0x1) << HSMCI_SR_RCRCE_Pos) /**< (HSMCI_SR) Response CRC Error (cleared by writing in HSMCI_CMDR) Mask */
|
||||
#define HSMCI_SR_RCRCE(value) (HSMCI_SR_RCRCE_Msk & ((value) << HSMCI_SR_RCRCE_Pos))
|
||||
#define HSMCI_SR_RENDE_Pos _U_(19) /**< (HSMCI_SR) Response End Bit Error (cleared by writing in HSMCI_CMDR) Position */
|
||||
#define HSMCI_SR_RENDE_Msk (_U_(0x1) << HSMCI_SR_RENDE_Pos) /**< (HSMCI_SR) Response End Bit Error (cleared by writing in HSMCI_CMDR) Mask */
|
||||
#define HSMCI_SR_RENDE(value) (HSMCI_SR_RENDE_Msk & ((value) << HSMCI_SR_RENDE_Pos))
|
||||
#define HSMCI_SR_RTOE_Pos _U_(20) /**< (HSMCI_SR) Response Time-out Error (cleared by writing in HSMCI_CMDR) Position */
|
||||
#define HSMCI_SR_RTOE_Msk (_U_(0x1) << HSMCI_SR_RTOE_Pos) /**< (HSMCI_SR) Response Time-out Error (cleared by writing in HSMCI_CMDR) Mask */
|
||||
#define HSMCI_SR_RTOE(value) (HSMCI_SR_RTOE_Msk & ((value) << HSMCI_SR_RTOE_Pos))
|
||||
#define HSMCI_SR_DCRCE_Pos _U_(21) /**< (HSMCI_SR) Data CRC Error (cleared on read) Position */
|
||||
#define HSMCI_SR_DCRCE_Msk (_U_(0x1) << HSMCI_SR_DCRCE_Pos) /**< (HSMCI_SR) Data CRC Error (cleared on read) Mask */
|
||||
#define HSMCI_SR_DCRCE(value) (HSMCI_SR_DCRCE_Msk & ((value) << HSMCI_SR_DCRCE_Pos))
|
||||
#define HSMCI_SR_DTOE_Pos _U_(22) /**< (HSMCI_SR) Data Time-out Error (cleared on read) Position */
|
||||
#define HSMCI_SR_DTOE_Msk (_U_(0x1) << HSMCI_SR_DTOE_Pos) /**< (HSMCI_SR) Data Time-out Error (cleared on read) Mask */
|
||||
#define HSMCI_SR_DTOE(value) (HSMCI_SR_DTOE_Msk & ((value) << HSMCI_SR_DTOE_Pos))
|
||||
#define HSMCI_SR_CSTOE_Pos _U_(23) /**< (HSMCI_SR) Completion Signal Time-out Error (cleared on read) Position */
|
||||
#define HSMCI_SR_CSTOE_Msk (_U_(0x1) << HSMCI_SR_CSTOE_Pos) /**< (HSMCI_SR) Completion Signal Time-out Error (cleared on read) Mask */
|
||||
#define HSMCI_SR_CSTOE(value) (HSMCI_SR_CSTOE_Msk & ((value) << HSMCI_SR_CSTOE_Pos))
|
||||
#define HSMCI_SR_BLKOVRE_Pos _U_(24) /**< (HSMCI_SR) DMA Block Overrun Error (cleared on read) Position */
|
||||
#define HSMCI_SR_BLKOVRE_Msk (_U_(0x1) << HSMCI_SR_BLKOVRE_Pos) /**< (HSMCI_SR) DMA Block Overrun Error (cleared on read) Mask */
|
||||
#define HSMCI_SR_BLKOVRE(value) (HSMCI_SR_BLKOVRE_Msk & ((value) << HSMCI_SR_BLKOVRE_Pos))
|
||||
#define HSMCI_SR_FIFOEMPTY_Pos _U_(26) /**< (HSMCI_SR) FIFO empty flag Position */
|
||||
#define HSMCI_SR_FIFOEMPTY_Msk (_U_(0x1) << HSMCI_SR_FIFOEMPTY_Pos) /**< (HSMCI_SR) FIFO empty flag Mask */
|
||||
#define HSMCI_SR_FIFOEMPTY(value) (HSMCI_SR_FIFOEMPTY_Msk & ((value) << HSMCI_SR_FIFOEMPTY_Pos))
|
||||
#define HSMCI_SR_XFRDONE_Pos _U_(27) /**< (HSMCI_SR) Transfer Done flag Position */
|
||||
#define HSMCI_SR_XFRDONE_Msk (_U_(0x1) << HSMCI_SR_XFRDONE_Pos) /**< (HSMCI_SR) Transfer Done flag Mask */
|
||||
#define HSMCI_SR_XFRDONE(value) (HSMCI_SR_XFRDONE_Msk & ((value) << HSMCI_SR_XFRDONE_Pos))
|
||||
#define HSMCI_SR_ACKRCV_Pos _U_(28) /**< (HSMCI_SR) Boot Operation Acknowledge Received (cleared on read) Position */
|
||||
#define HSMCI_SR_ACKRCV_Msk (_U_(0x1) << HSMCI_SR_ACKRCV_Pos) /**< (HSMCI_SR) Boot Operation Acknowledge Received (cleared on read) Mask */
|
||||
#define HSMCI_SR_ACKRCV(value) (HSMCI_SR_ACKRCV_Msk & ((value) << HSMCI_SR_ACKRCV_Pos))
|
||||
#define HSMCI_SR_ACKRCVE_Pos _U_(29) /**< (HSMCI_SR) Boot Operation Acknowledge Error (cleared on read) Position */
|
||||
#define HSMCI_SR_ACKRCVE_Msk (_U_(0x1) << HSMCI_SR_ACKRCVE_Pos) /**< (HSMCI_SR) Boot Operation Acknowledge Error (cleared on read) Mask */
|
||||
#define HSMCI_SR_ACKRCVE(value) (HSMCI_SR_ACKRCVE_Msk & ((value) << HSMCI_SR_ACKRCVE_Pos))
|
||||
#define HSMCI_SR_OVRE_Pos _U_(30) /**< (HSMCI_SR) Overrun (if FERRCTRL = 1, cleared by writing in HSMCI_CMDR or cleared on read if FERRCTRL = 0) Position */
|
||||
#define HSMCI_SR_OVRE_Msk (_U_(0x1) << HSMCI_SR_OVRE_Pos) /**< (HSMCI_SR) Overrun (if FERRCTRL = 1, cleared by writing in HSMCI_CMDR or cleared on read if FERRCTRL = 0) Mask */
|
||||
#define HSMCI_SR_OVRE(value) (HSMCI_SR_OVRE_Msk & ((value) << HSMCI_SR_OVRE_Pos))
|
||||
#define HSMCI_SR_UNRE_Pos _U_(31) /**< (HSMCI_SR) Underrun (if FERRCTRL = 1, cleared by writing in HSMCI_CMDR or cleared on read if FERRCTRL = 0) Position */
|
||||
#define HSMCI_SR_UNRE_Msk (_U_(0x1) << HSMCI_SR_UNRE_Pos) /**< (HSMCI_SR) Underrun (if FERRCTRL = 1, cleared by writing in HSMCI_CMDR or cleared on read if FERRCTRL = 0) Mask */
|
||||
#define HSMCI_SR_UNRE(value) (HSMCI_SR_UNRE_Msk & ((value) << HSMCI_SR_UNRE_Pos))
|
||||
#define HSMCI_SR_Msk _U_(0xFDFF313F) /**< (HSMCI_SR) Register Mask */
|
||||
|
||||
|
||||
/* -------- HSMCI_IER : (HSMCI Offset: 0x44) ( /W 32) Interrupt Enable Register -------- */
|
||||
#define HSMCI_IER_CMDRDY_Pos _U_(0) /**< (HSMCI_IER) Command Ready Interrupt Enable Position */
|
||||
#define HSMCI_IER_CMDRDY_Msk (_U_(0x1) << HSMCI_IER_CMDRDY_Pos) /**< (HSMCI_IER) Command Ready Interrupt Enable Mask */
|
||||
#define HSMCI_IER_CMDRDY(value) (HSMCI_IER_CMDRDY_Msk & ((value) << HSMCI_IER_CMDRDY_Pos))
|
||||
#define HSMCI_IER_RXRDY_Pos _U_(1) /**< (HSMCI_IER) Receiver Ready Interrupt Enable Position */
|
||||
#define HSMCI_IER_RXRDY_Msk (_U_(0x1) << HSMCI_IER_RXRDY_Pos) /**< (HSMCI_IER) Receiver Ready Interrupt Enable Mask */
|
||||
#define HSMCI_IER_RXRDY(value) (HSMCI_IER_RXRDY_Msk & ((value) << HSMCI_IER_RXRDY_Pos))
|
||||
#define HSMCI_IER_TXRDY_Pos _U_(2) /**< (HSMCI_IER) Transmit Ready Interrupt Enable Position */
|
||||
#define HSMCI_IER_TXRDY_Msk (_U_(0x1) << HSMCI_IER_TXRDY_Pos) /**< (HSMCI_IER) Transmit Ready Interrupt Enable Mask */
|
||||
#define HSMCI_IER_TXRDY(value) (HSMCI_IER_TXRDY_Msk & ((value) << HSMCI_IER_TXRDY_Pos))
|
||||
#define HSMCI_IER_BLKE_Pos _U_(3) /**< (HSMCI_IER) Data Block Ended Interrupt Enable Position */
|
||||
#define HSMCI_IER_BLKE_Msk (_U_(0x1) << HSMCI_IER_BLKE_Pos) /**< (HSMCI_IER) Data Block Ended Interrupt Enable Mask */
|
||||
#define HSMCI_IER_BLKE(value) (HSMCI_IER_BLKE_Msk & ((value) << HSMCI_IER_BLKE_Pos))
|
||||
#define HSMCI_IER_DTIP_Pos _U_(4) /**< (HSMCI_IER) Data Transfer in Progress Interrupt Enable Position */
|
||||
#define HSMCI_IER_DTIP_Msk (_U_(0x1) << HSMCI_IER_DTIP_Pos) /**< (HSMCI_IER) Data Transfer in Progress Interrupt Enable Mask */
|
||||
#define HSMCI_IER_DTIP(value) (HSMCI_IER_DTIP_Msk & ((value) << HSMCI_IER_DTIP_Pos))
|
||||
#define HSMCI_IER_NOTBUSY_Pos _U_(5) /**< (HSMCI_IER) Data Not Busy Interrupt Enable Position */
|
||||
#define HSMCI_IER_NOTBUSY_Msk (_U_(0x1) << HSMCI_IER_NOTBUSY_Pos) /**< (HSMCI_IER) Data Not Busy Interrupt Enable Mask */
|
||||
#define HSMCI_IER_NOTBUSY(value) (HSMCI_IER_NOTBUSY_Msk & ((value) << HSMCI_IER_NOTBUSY_Pos))
|
||||
#define HSMCI_IER_SDIOIRQA_Pos _U_(8) /**< (HSMCI_IER) SDIO Interrupt for Slot A Interrupt Enable Position */
|
||||
#define HSMCI_IER_SDIOIRQA_Msk (_U_(0x1) << HSMCI_IER_SDIOIRQA_Pos) /**< (HSMCI_IER) SDIO Interrupt for Slot A Interrupt Enable Mask */
|
||||
#define HSMCI_IER_SDIOIRQA(value) (HSMCI_IER_SDIOIRQA_Msk & ((value) << HSMCI_IER_SDIOIRQA_Pos))
|
||||
#define HSMCI_IER_SDIOWAIT_Pos _U_(12) /**< (HSMCI_IER) SDIO Read Wait Operation Status Interrupt Enable Position */
|
||||
#define HSMCI_IER_SDIOWAIT_Msk (_U_(0x1) << HSMCI_IER_SDIOWAIT_Pos) /**< (HSMCI_IER) SDIO Read Wait Operation Status Interrupt Enable Mask */
|
||||
#define HSMCI_IER_SDIOWAIT(value) (HSMCI_IER_SDIOWAIT_Msk & ((value) << HSMCI_IER_SDIOWAIT_Pos))
|
||||
#define HSMCI_IER_CSRCV_Pos _U_(13) /**< (HSMCI_IER) Completion Signal Received Interrupt Enable Position */
|
||||
#define HSMCI_IER_CSRCV_Msk (_U_(0x1) << HSMCI_IER_CSRCV_Pos) /**< (HSMCI_IER) Completion Signal Received Interrupt Enable Mask */
|
||||
#define HSMCI_IER_CSRCV(value) (HSMCI_IER_CSRCV_Msk & ((value) << HSMCI_IER_CSRCV_Pos))
|
||||
#define HSMCI_IER_RINDE_Pos _U_(16) /**< (HSMCI_IER) Response Index Error Interrupt Enable Position */
|
||||
#define HSMCI_IER_RINDE_Msk (_U_(0x1) << HSMCI_IER_RINDE_Pos) /**< (HSMCI_IER) Response Index Error Interrupt Enable Mask */
|
||||
#define HSMCI_IER_RINDE(value) (HSMCI_IER_RINDE_Msk & ((value) << HSMCI_IER_RINDE_Pos))
|
||||
#define HSMCI_IER_RDIRE_Pos _U_(17) /**< (HSMCI_IER) Response Direction Error Interrupt Enable Position */
|
||||
#define HSMCI_IER_RDIRE_Msk (_U_(0x1) << HSMCI_IER_RDIRE_Pos) /**< (HSMCI_IER) Response Direction Error Interrupt Enable Mask */
|
||||
#define HSMCI_IER_RDIRE(value) (HSMCI_IER_RDIRE_Msk & ((value) << HSMCI_IER_RDIRE_Pos))
|
||||
#define HSMCI_IER_RCRCE_Pos _U_(18) /**< (HSMCI_IER) Response CRC Error Interrupt Enable Position */
|
||||
#define HSMCI_IER_RCRCE_Msk (_U_(0x1) << HSMCI_IER_RCRCE_Pos) /**< (HSMCI_IER) Response CRC Error Interrupt Enable Mask */
|
||||
#define HSMCI_IER_RCRCE(value) (HSMCI_IER_RCRCE_Msk & ((value) << HSMCI_IER_RCRCE_Pos))
|
||||
#define HSMCI_IER_RENDE_Pos _U_(19) /**< (HSMCI_IER) Response End Bit Error Interrupt Enable Position */
|
||||
#define HSMCI_IER_RENDE_Msk (_U_(0x1) << HSMCI_IER_RENDE_Pos) /**< (HSMCI_IER) Response End Bit Error Interrupt Enable Mask */
|
||||
#define HSMCI_IER_RENDE(value) (HSMCI_IER_RENDE_Msk & ((value) << HSMCI_IER_RENDE_Pos))
|
||||
#define HSMCI_IER_RTOE_Pos _U_(20) /**< (HSMCI_IER) Response Time-out Error Interrupt Enable Position */
|
||||
#define HSMCI_IER_RTOE_Msk (_U_(0x1) << HSMCI_IER_RTOE_Pos) /**< (HSMCI_IER) Response Time-out Error Interrupt Enable Mask */
|
||||
#define HSMCI_IER_RTOE(value) (HSMCI_IER_RTOE_Msk & ((value) << HSMCI_IER_RTOE_Pos))
|
||||
#define HSMCI_IER_DCRCE_Pos _U_(21) /**< (HSMCI_IER) Data CRC Error Interrupt Enable Position */
|
||||
#define HSMCI_IER_DCRCE_Msk (_U_(0x1) << HSMCI_IER_DCRCE_Pos) /**< (HSMCI_IER) Data CRC Error Interrupt Enable Mask */
|
||||
#define HSMCI_IER_DCRCE(value) (HSMCI_IER_DCRCE_Msk & ((value) << HSMCI_IER_DCRCE_Pos))
|
||||
#define HSMCI_IER_DTOE_Pos _U_(22) /**< (HSMCI_IER) Data Time-out Error Interrupt Enable Position */
|
||||
#define HSMCI_IER_DTOE_Msk (_U_(0x1) << HSMCI_IER_DTOE_Pos) /**< (HSMCI_IER) Data Time-out Error Interrupt Enable Mask */
|
||||
#define HSMCI_IER_DTOE(value) (HSMCI_IER_DTOE_Msk & ((value) << HSMCI_IER_DTOE_Pos))
|
||||
#define HSMCI_IER_CSTOE_Pos _U_(23) /**< (HSMCI_IER) Completion Signal Timeout Error Interrupt Enable Position */
|
||||
#define HSMCI_IER_CSTOE_Msk (_U_(0x1) << HSMCI_IER_CSTOE_Pos) /**< (HSMCI_IER) Completion Signal Timeout Error Interrupt Enable Mask */
|
||||
#define HSMCI_IER_CSTOE(value) (HSMCI_IER_CSTOE_Msk & ((value) << HSMCI_IER_CSTOE_Pos))
|
||||
#define HSMCI_IER_BLKOVRE_Pos _U_(24) /**< (HSMCI_IER) DMA Block Overrun Error Interrupt Enable Position */
|
||||
#define HSMCI_IER_BLKOVRE_Msk (_U_(0x1) << HSMCI_IER_BLKOVRE_Pos) /**< (HSMCI_IER) DMA Block Overrun Error Interrupt Enable Mask */
|
||||
#define HSMCI_IER_BLKOVRE(value) (HSMCI_IER_BLKOVRE_Msk & ((value) << HSMCI_IER_BLKOVRE_Pos))
|
||||
#define HSMCI_IER_FIFOEMPTY_Pos _U_(26) /**< (HSMCI_IER) FIFO empty Interrupt enable Position */
|
||||
#define HSMCI_IER_FIFOEMPTY_Msk (_U_(0x1) << HSMCI_IER_FIFOEMPTY_Pos) /**< (HSMCI_IER) FIFO empty Interrupt enable Mask */
|
||||
#define HSMCI_IER_FIFOEMPTY(value) (HSMCI_IER_FIFOEMPTY_Msk & ((value) << HSMCI_IER_FIFOEMPTY_Pos))
|
||||
#define HSMCI_IER_XFRDONE_Pos _U_(27) /**< (HSMCI_IER) Transfer Done Interrupt enable Position */
|
||||
#define HSMCI_IER_XFRDONE_Msk (_U_(0x1) << HSMCI_IER_XFRDONE_Pos) /**< (HSMCI_IER) Transfer Done Interrupt enable Mask */
|
||||
#define HSMCI_IER_XFRDONE(value) (HSMCI_IER_XFRDONE_Msk & ((value) << HSMCI_IER_XFRDONE_Pos))
|
||||
#define HSMCI_IER_ACKRCV_Pos _U_(28) /**< (HSMCI_IER) Boot Acknowledge Interrupt Enable Position */
|
||||
#define HSMCI_IER_ACKRCV_Msk (_U_(0x1) << HSMCI_IER_ACKRCV_Pos) /**< (HSMCI_IER) Boot Acknowledge Interrupt Enable Mask */
|
||||
#define HSMCI_IER_ACKRCV(value) (HSMCI_IER_ACKRCV_Msk & ((value) << HSMCI_IER_ACKRCV_Pos))
|
||||
#define HSMCI_IER_ACKRCVE_Pos _U_(29) /**< (HSMCI_IER) Boot Acknowledge Error Interrupt Enable Position */
|
||||
#define HSMCI_IER_ACKRCVE_Msk (_U_(0x1) << HSMCI_IER_ACKRCVE_Pos) /**< (HSMCI_IER) Boot Acknowledge Error Interrupt Enable Mask */
|
||||
#define HSMCI_IER_ACKRCVE(value) (HSMCI_IER_ACKRCVE_Msk & ((value) << HSMCI_IER_ACKRCVE_Pos))
|
||||
#define HSMCI_IER_OVRE_Pos _U_(30) /**< (HSMCI_IER) Overrun Interrupt Enable Position */
|
||||
#define HSMCI_IER_OVRE_Msk (_U_(0x1) << HSMCI_IER_OVRE_Pos) /**< (HSMCI_IER) Overrun Interrupt Enable Mask */
|
||||
#define HSMCI_IER_OVRE(value) (HSMCI_IER_OVRE_Msk & ((value) << HSMCI_IER_OVRE_Pos))
|
||||
#define HSMCI_IER_UNRE_Pos _U_(31) /**< (HSMCI_IER) Underrun Interrupt Enable Position */
|
||||
#define HSMCI_IER_UNRE_Msk (_U_(0x1) << HSMCI_IER_UNRE_Pos) /**< (HSMCI_IER) Underrun Interrupt Enable Mask */
|
||||
#define HSMCI_IER_UNRE(value) (HSMCI_IER_UNRE_Msk & ((value) << HSMCI_IER_UNRE_Pos))
|
||||
#define HSMCI_IER_Msk _U_(0xFDFF313F) /**< (HSMCI_IER) Register Mask */
|
||||
|
||||
|
||||
/* -------- HSMCI_IDR : (HSMCI Offset: 0x48) ( /W 32) Interrupt Disable Register -------- */
|
||||
#define HSMCI_IDR_CMDRDY_Pos _U_(0) /**< (HSMCI_IDR) Command Ready Interrupt Disable Position */
|
||||
#define HSMCI_IDR_CMDRDY_Msk (_U_(0x1) << HSMCI_IDR_CMDRDY_Pos) /**< (HSMCI_IDR) Command Ready Interrupt Disable Mask */
|
||||
#define HSMCI_IDR_CMDRDY(value) (HSMCI_IDR_CMDRDY_Msk & ((value) << HSMCI_IDR_CMDRDY_Pos))
|
||||
#define HSMCI_IDR_RXRDY_Pos _U_(1) /**< (HSMCI_IDR) Receiver Ready Interrupt Disable Position */
|
||||
#define HSMCI_IDR_RXRDY_Msk (_U_(0x1) << HSMCI_IDR_RXRDY_Pos) /**< (HSMCI_IDR) Receiver Ready Interrupt Disable Mask */
|
||||
#define HSMCI_IDR_RXRDY(value) (HSMCI_IDR_RXRDY_Msk & ((value) << HSMCI_IDR_RXRDY_Pos))
|
||||
#define HSMCI_IDR_TXRDY_Pos _U_(2) /**< (HSMCI_IDR) Transmit Ready Interrupt Disable Position */
|
||||
#define HSMCI_IDR_TXRDY_Msk (_U_(0x1) << HSMCI_IDR_TXRDY_Pos) /**< (HSMCI_IDR) Transmit Ready Interrupt Disable Mask */
|
||||
#define HSMCI_IDR_TXRDY(value) (HSMCI_IDR_TXRDY_Msk & ((value) << HSMCI_IDR_TXRDY_Pos))
|
||||
#define HSMCI_IDR_BLKE_Pos _U_(3) /**< (HSMCI_IDR) Data Block Ended Interrupt Disable Position */
|
||||
#define HSMCI_IDR_BLKE_Msk (_U_(0x1) << HSMCI_IDR_BLKE_Pos) /**< (HSMCI_IDR) Data Block Ended Interrupt Disable Mask */
|
||||
#define HSMCI_IDR_BLKE(value) (HSMCI_IDR_BLKE_Msk & ((value) << HSMCI_IDR_BLKE_Pos))
|
||||
#define HSMCI_IDR_DTIP_Pos _U_(4) /**< (HSMCI_IDR) Data Transfer in Progress Interrupt Disable Position */
|
||||
#define HSMCI_IDR_DTIP_Msk (_U_(0x1) << HSMCI_IDR_DTIP_Pos) /**< (HSMCI_IDR) Data Transfer in Progress Interrupt Disable Mask */
|
||||
#define HSMCI_IDR_DTIP(value) (HSMCI_IDR_DTIP_Msk & ((value) << HSMCI_IDR_DTIP_Pos))
|
||||
#define HSMCI_IDR_NOTBUSY_Pos _U_(5) /**< (HSMCI_IDR) Data Not Busy Interrupt Disable Position */
|
||||
#define HSMCI_IDR_NOTBUSY_Msk (_U_(0x1) << HSMCI_IDR_NOTBUSY_Pos) /**< (HSMCI_IDR) Data Not Busy Interrupt Disable Mask */
|
||||
#define HSMCI_IDR_NOTBUSY(value) (HSMCI_IDR_NOTBUSY_Msk & ((value) << HSMCI_IDR_NOTBUSY_Pos))
|
||||
#define HSMCI_IDR_SDIOIRQA_Pos _U_(8) /**< (HSMCI_IDR) SDIO Interrupt for Slot A Interrupt Disable Position */
|
||||
#define HSMCI_IDR_SDIOIRQA_Msk (_U_(0x1) << HSMCI_IDR_SDIOIRQA_Pos) /**< (HSMCI_IDR) SDIO Interrupt for Slot A Interrupt Disable Mask */
|
||||
#define HSMCI_IDR_SDIOIRQA(value) (HSMCI_IDR_SDIOIRQA_Msk & ((value) << HSMCI_IDR_SDIOIRQA_Pos))
|
||||
#define HSMCI_IDR_SDIOWAIT_Pos _U_(12) /**< (HSMCI_IDR) SDIO Read Wait Operation Status Interrupt Disable Position */
|
||||
#define HSMCI_IDR_SDIOWAIT_Msk (_U_(0x1) << HSMCI_IDR_SDIOWAIT_Pos) /**< (HSMCI_IDR) SDIO Read Wait Operation Status Interrupt Disable Mask */
|
||||
#define HSMCI_IDR_SDIOWAIT(value) (HSMCI_IDR_SDIOWAIT_Msk & ((value) << HSMCI_IDR_SDIOWAIT_Pos))
|
||||
#define HSMCI_IDR_CSRCV_Pos _U_(13) /**< (HSMCI_IDR) Completion Signal received interrupt Disable Position */
|
||||
#define HSMCI_IDR_CSRCV_Msk (_U_(0x1) << HSMCI_IDR_CSRCV_Pos) /**< (HSMCI_IDR) Completion Signal received interrupt Disable Mask */
|
||||
#define HSMCI_IDR_CSRCV(value) (HSMCI_IDR_CSRCV_Msk & ((value) << HSMCI_IDR_CSRCV_Pos))
|
||||
#define HSMCI_IDR_RINDE_Pos _U_(16) /**< (HSMCI_IDR) Response Index Error Interrupt Disable Position */
|
||||
#define HSMCI_IDR_RINDE_Msk (_U_(0x1) << HSMCI_IDR_RINDE_Pos) /**< (HSMCI_IDR) Response Index Error Interrupt Disable Mask */
|
||||
#define HSMCI_IDR_RINDE(value) (HSMCI_IDR_RINDE_Msk & ((value) << HSMCI_IDR_RINDE_Pos))
|
||||
#define HSMCI_IDR_RDIRE_Pos _U_(17) /**< (HSMCI_IDR) Response Direction Error Interrupt Disable Position */
|
||||
#define HSMCI_IDR_RDIRE_Msk (_U_(0x1) << HSMCI_IDR_RDIRE_Pos) /**< (HSMCI_IDR) Response Direction Error Interrupt Disable Mask */
|
||||
#define HSMCI_IDR_RDIRE(value) (HSMCI_IDR_RDIRE_Msk & ((value) << HSMCI_IDR_RDIRE_Pos))
|
||||
#define HSMCI_IDR_RCRCE_Pos _U_(18) /**< (HSMCI_IDR) Response CRC Error Interrupt Disable Position */
|
||||
#define HSMCI_IDR_RCRCE_Msk (_U_(0x1) << HSMCI_IDR_RCRCE_Pos) /**< (HSMCI_IDR) Response CRC Error Interrupt Disable Mask */
|
||||
#define HSMCI_IDR_RCRCE(value) (HSMCI_IDR_RCRCE_Msk & ((value) << HSMCI_IDR_RCRCE_Pos))
|
||||
#define HSMCI_IDR_RENDE_Pos _U_(19) /**< (HSMCI_IDR) Response End Bit Error Interrupt Disable Position */
|
||||
#define HSMCI_IDR_RENDE_Msk (_U_(0x1) << HSMCI_IDR_RENDE_Pos) /**< (HSMCI_IDR) Response End Bit Error Interrupt Disable Mask */
|
||||
#define HSMCI_IDR_RENDE(value) (HSMCI_IDR_RENDE_Msk & ((value) << HSMCI_IDR_RENDE_Pos))
|
||||
#define HSMCI_IDR_RTOE_Pos _U_(20) /**< (HSMCI_IDR) Response Time-out Error Interrupt Disable Position */
|
||||
#define HSMCI_IDR_RTOE_Msk (_U_(0x1) << HSMCI_IDR_RTOE_Pos) /**< (HSMCI_IDR) Response Time-out Error Interrupt Disable Mask */
|
||||
#define HSMCI_IDR_RTOE(value) (HSMCI_IDR_RTOE_Msk & ((value) << HSMCI_IDR_RTOE_Pos))
|
||||
#define HSMCI_IDR_DCRCE_Pos _U_(21) /**< (HSMCI_IDR) Data CRC Error Interrupt Disable Position */
|
||||
#define HSMCI_IDR_DCRCE_Msk (_U_(0x1) << HSMCI_IDR_DCRCE_Pos) /**< (HSMCI_IDR) Data CRC Error Interrupt Disable Mask */
|
||||
#define HSMCI_IDR_DCRCE(value) (HSMCI_IDR_DCRCE_Msk & ((value) << HSMCI_IDR_DCRCE_Pos))
|
||||
#define HSMCI_IDR_DTOE_Pos _U_(22) /**< (HSMCI_IDR) Data Time-out Error Interrupt Disable Position */
|
||||
#define HSMCI_IDR_DTOE_Msk (_U_(0x1) << HSMCI_IDR_DTOE_Pos) /**< (HSMCI_IDR) Data Time-out Error Interrupt Disable Mask */
|
||||
#define HSMCI_IDR_DTOE(value) (HSMCI_IDR_DTOE_Msk & ((value) << HSMCI_IDR_DTOE_Pos))
|
||||
#define HSMCI_IDR_CSTOE_Pos _U_(23) /**< (HSMCI_IDR) Completion Signal Time out Error Interrupt Disable Position */
|
||||
#define HSMCI_IDR_CSTOE_Msk (_U_(0x1) << HSMCI_IDR_CSTOE_Pos) /**< (HSMCI_IDR) Completion Signal Time out Error Interrupt Disable Mask */
|
||||
#define HSMCI_IDR_CSTOE(value) (HSMCI_IDR_CSTOE_Msk & ((value) << HSMCI_IDR_CSTOE_Pos))
|
||||
#define HSMCI_IDR_BLKOVRE_Pos _U_(24) /**< (HSMCI_IDR) DMA Block Overrun Error Interrupt Disable Position */
|
||||
#define HSMCI_IDR_BLKOVRE_Msk (_U_(0x1) << HSMCI_IDR_BLKOVRE_Pos) /**< (HSMCI_IDR) DMA Block Overrun Error Interrupt Disable Mask */
|
||||
#define HSMCI_IDR_BLKOVRE(value) (HSMCI_IDR_BLKOVRE_Msk & ((value) << HSMCI_IDR_BLKOVRE_Pos))
|
||||
#define HSMCI_IDR_FIFOEMPTY_Pos _U_(26) /**< (HSMCI_IDR) FIFO empty Interrupt Disable Position */
|
||||
#define HSMCI_IDR_FIFOEMPTY_Msk (_U_(0x1) << HSMCI_IDR_FIFOEMPTY_Pos) /**< (HSMCI_IDR) FIFO empty Interrupt Disable Mask */
|
||||
#define HSMCI_IDR_FIFOEMPTY(value) (HSMCI_IDR_FIFOEMPTY_Msk & ((value) << HSMCI_IDR_FIFOEMPTY_Pos))
|
||||
#define HSMCI_IDR_XFRDONE_Pos _U_(27) /**< (HSMCI_IDR) Transfer Done Interrupt Disable Position */
|
||||
#define HSMCI_IDR_XFRDONE_Msk (_U_(0x1) << HSMCI_IDR_XFRDONE_Pos) /**< (HSMCI_IDR) Transfer Done Interrupt Disable Mask */
|
||||
#define HSMCI_IDR_XFRDONE(value) (HSMCI_IDR_XFRDONE_Msk & ((value) << HSMCI_IDR_XFRDONE_Pos))
|
||||
#define HSMCI_IDR_ACKRCV_Pos _U_(28) /**< (HSMCI_IDR) Boot Acknowledge Interrupt Disable Position */
|
||||
#define HSMCI_IDR_ACKRCV_Msk (_U_(0x1) << HSMCI_IDR_ACKRCV_Pos) /**< (HSMCI_IDR) Boot Acknowledge Interrupt Disable Mask */
|
||||
#define HSMCI_IDR_ACKRCV(value) (HSMCI_IDR_ACKRCV_Msk & ((value) << HSMCI_IDR_ACKRCV_Pos))
|
||||
#define HSMCI_IDR_ACKRCVE_Pos _U_(29) /**< (HSMCI_IDR) Boot Acknowledge Error Interrupt Disable Position */
|
||||
#define HSMCI_IDR_ACKRCVE_Msk (_U_(0x1) << HSMCI_IDR_ACKRCVE_Pos) /**< (HSMCI_IDR) Boot Acknowledge Error Interrupt Disable Mask */
|
||||
#define HSMCI_IDR_ACKRCVE(value) (HSMCI_IDR_ACKRCVE_Msk & ((value) << HSMCI_IDR_ACKRCVE_Pos))
|
||||
#define HSMCI_IDR_OVRE_Pos _U_(30) /**< (HSMCI_IDR) Overrun Interrupt Disable Position */
|
||||
#define HSMCI_IDR_OVRE_Msk (_U_(0x1) << HSMCI_IDR_OVRE_Pos) /**< (HSMCI_IDR) Overrun Interrupt Disable Mask */
|
||||
#define HSMCI_IDR_OVRE(value) (HSMCI_IDR_OVRE_Msk & ((value) << HSMCI_IDR_OVRE_Pos))
|
||||
#define HSMCI_IDR_UNRE_Pos _U_(31) /**< (HSMCI_IDR) Underrun Interrupt Disable Position */
|
||||
#define HSMCI_IDR_UNRE_Msk (_U_(0x1) << HSMCI_IDR_UNRE_Pos) /**< (HSMCI_IDR) Underrun Interrupt Disable Mask */
|
||||
#define HSMCI_IDR_UNRE(value) (HSMCI_IDR_UNRE_Msk & ((value) << HSMCI_IDR_UNRE_Pos))
|
||||
#define HSMCI_IDR_Msk _U_(0xFDFF313F) /**< (HSMCI_IDR) Register Mask */
|
||||
|
||||
|
||||
/* -------- HSMCI_IMR : (HSMCI Offset: 0x4C) ( R/ 32) Interrupt Mask Register -------- */
|
||||
#define HSMCI_IMR_CMDRDY_Pos _U_(0) /**< (HSMCI_IMR) Command Ready Interrupt Mask Position */
|
||||
#define HSMCI_IMR_CMDRDY_Msk (_U_(0x1) << HSMCI_IMR_CMDRDY_Pos) /**< (HSMCI_IMR) Command Ready Interrupt Mask Mask */
|
||||
#define HSMCI_IMR_CMDRDY(value) (HSMCI_IMR_CMDRDY_Msk & ((value) << HSMCI_IMR_CMDRDY_Pos))
|
||||
#define HSMCI_IMR_RXRDY_Pos _U_(1) /**< (HSMCI_IMR) Receiver Ready Interrupt Mask Position */
|
||||
#define HSMCI_IMR_RXRDY_Msk (_U_(0x1) << HSMCI_IMR_RXRDY_Pos) /**< (HSMCI_IMR) Receiver Ready Interrupt Mask Mask */
|
||||
#define HSMCI_IMR_RXRDY(value) (HSMCI_IMR_RXRDY_Msk & ((value) << HSMCI_IMR_RXRDY_Pos))
|
||||
#define HSMCI_IMR_TXRDY_Pos _U_(2) /**< (HSMCI_IMR) Transmit Ready Interrupt Mask Position */
|
||||
#define HSMCI_IMR_TXRDY_Msk (_U_(0x1) << HSMCI_IMR_TXRDY_Pos) /**< (HSMCI_IMR) Transmit Ready Interrupt Mask Mask */
|
||||
#define HSMCI_IMR_TXRDY(value) (HSMCI_IMR_TXRDY_Msk & ((value) << HSMCI_IMR_TXRDY_Pos))
|
||||
#define HSMCI_IMR_BLKE_Pos _U_(3) /**< (HSMCI_IMR) Data Block Ended Interrupt Mask Position */
|
||||
#define HSMCI_IMR_BLKE_Msk (_U_(0x1) << HSMCI_IMR_BLKE_Pos) /**< (HSMCI_IMR) Data Block Ended Interrupt Mask Mask */
|
||||
#define HSMCI_IMR_BLKE(value) (HSMCI_IMR_BLKE_Msk & ((value) << HSMCI_IMR_BLKE_Pos))
|
||||
#define HSMCI_IMR_DTIP_Pos _U_(4) /**< (HSMCI_IMR) Data Transfer in Progress Interrupt Mask Position */
|
||||
#define HSMCI_IMR_DTIP_Msk (_U_(0x1) << HSMCI_IMR_DTIP_Pos) /**< (HSMCI_IMR) Data Transfer in Progress Interrupt Mask Mask */
|
||||
#define HSMCI_IMR_DTIP(value) (HSMCI_IMR_DTIP_Msk & ((value) << HSMCI_IMR_DTIP_Pos))
|
||||
#define HSMCI_IMR_NOTBUSY_Pos _U_(5) /**< (HSMCI_IMR) Data Not Busy Interrupt Mask Position */
|
||||
#define HSMCI_IMR_NOTBUSY_Msk (_U_(0x1) << HSMCI_IMR_NOTBUSY_Pos) /**< (HSMCI_IMR) Data Not Busy Interrupt Mask Mask */
|
||||
#define HSMCI_IMR_NOTBUSY(value) (HSMCI_IMR_NOTBUSY_Msk & ((value) << HSMCI_IMR_NOTBUSY_Pos))
|
||||
#define HSMCI_IMR_SDIOIRQA_Pos _U_(8) /**< (HSMCI_IMR) SDIO Interrupt for Slot A Interrupt Mask Position */
|
||||
#define HSMCI_IMR_SDIOIRQA_Msk (_U_(0x1) << HSMCI_IMR_SDIOIRQA_Pos) /**< (HSMCI_IMR) SDIO Interrupt for Slot A Interrupt Mask Mask */
|
||||
#define HSMCI_IMR_SDIOIRQA(value) (HSMCI_IMR_SDIOIRQA_Msk & ((value) << HSMCI_IMR_SDIOIRQA_Pos))
|
||||
#define HSMCI_IMR_SDIOWAIT_Pos _U_(12) /**< (HSMCI_IMR) SDIO Read Wait Operation Status Interrupt Mask Position */
|
||||
#define HSMCI_IMR_SDIOWAIT_Msk (_U_(0x1) << HSMCI_IMR_SDIOWAIT_Pos) /**< (HSMCI_IMR) SDIO Read Wait Operation Status Interrupt Mask Mask */
|
||||
#define HSMCI_IMR_SDIOWAIT(value) (HSMCI_IMR_SDIOWAIT_Msk & ((value) << HSMCI_IMR_SDIOWAIT_Pos))
|
||||
#define HSMCI_IMR_CSRCV_Pos _U_(13) /**< (HSMCI_IMR) Completion Signal Received Interrupt Mask Position */
|
||||
#define HSMCI_IMR_CSRCV_Msk (_U_(0x1) << HSMCI_IMR_CSRCV_Pos) /**< (HSMCI_IMR) Completion Signal Received Interrupt Mask Mask */
|
||||
#define HSMCI_IMR_CSRCV(value) (HSMCI_IMR_CSRCV_Msk & ((value) << HSMCI_IMR_CSRCV_Pos))
|
||||
#define HSMCI_IMR_RINDE_Pos _U_(16) /**< (HSMCI_IMR) Response Index Error Interrupt Mask Position */
|
||||
#define HSMCI_IMR_RINDE_Msk (_U_(0x1) << HSMCI_IMR_RINDE_Pos) /**< (HSMCI_IMR) Response Index Error Interrupt Mask Mask */
|
||||
#define HSMCI_IMR_RINDE(value) (HSMCI_IMR_RINDE_Msk & ((value) << HSMCI_IMR_RINDE_Pos))
|
||||
#define HSMCI_IMR_RDIRE_Pos _U_(17) /**< (HSMCI_IMR) Response Direction Error Interrupt Mask Position */
|
||||
#define HSMCI_IMR_RDIRE_Msk (_U_(0x1) << HSMCI_IMR_RDIRE_Pos) /**< (HSMCI_IMR) Response Direction Error Interrupt Mask Mask */
|
||||
#define HSMCI_IMR_RDIRE(value) (HSMCI_IMR_RDIRE_Msk & ((value) << HSMCI_IMR_RDIRE_Pos))
|
||||
#define HSMCI_IMR_RCRCE_Pos _U_(18) /**< (HSMCI_IMR) Response CRC Error Interrupt Mask Position */
|
||||
#define HSMCI_IMR_RCRCE_Msk (_U_(0x1) << HSMCI_IMR_RCRCE_Pos) /**< (HSMCI_IMR) Response CRC Error Interrupt Mask Mask */
|
||||
#define HSMCI_IMR_RCRCE(value) (HSMCI_IMR_RCRCE_Msk & ((value) << HSMCI_IMR_RCRCE_Pos))
|
||||
#define HSMCI_IMR_RENDE_Pos _U_(19) /**< (HSMCI_IMR) Response End Bit Error Interrupt Mask Position */
|
||||
#define HSMCI_IMR_RENDE_Msk (_U_(0x1) << HSMCI_IMR_RENDE_Pos) /**< (HSMCI_IMR) Response End Bit Error Interrupt Mask Mask */
|
||||
#define HSMCI_IMR_RENDE(value) (HSMCI_IMR_RENDE_Msk & ((value) << HSMCI_IMR_RENDE_Pos))
|
||||
#define HSMCI_IMR_RTOE_Pos _U_(20) /**< (HSMCI_IMR) Response Time-out Error Interrupt Mask Position */
|
||||
#define HSMCI_IMR_RTOE_Msk (_U_(0x1) << HSMCI_IMR_RTOE_Pos) /**< (HSMCI_IMR) Response Time-out Error Interrupt Mask Mask */
|
||||
#define HSMCI_IMR_RTOE(value) (HSMCI_IMR_RTOE_Msk & ((value) << HSMCI_IMR_RTOE_Pos))
|
||||
#define HSMCI_IMR_DCRCE_Pos _U_(21) /**< (HSMCI_IMR) Data CRC Error Interrupt Mask Position */
|
||||
#define HSMCI_IMR_DCRCE_Msk (_U_(0x1) << HSMCI_IMR_DCRCE_Pos) /**< (HSMCI_IMR) Data CRC Error Interrupt Mask Mask */
|
||||
#define HSMCI_IMR_DCRCE(value) (HSMCI_IMR_DCRCE_Msk & ((value) << HSMCI_IMR_DCRCE_Pos))
|
||||
#define HSMCI_IMR_DTOE_Pos _U_(22) /**< (HSMCI_IMR) Data Time-out Error Interrupt Mask Position */
|
||||
#define HSMCI_IMR_DTOE_Msk (_U_(0x1) << HSMCI_IMR_DTOE_Pos) /**< (HSMCI_IMR) Data Time-out Error Interrupt Mask Mask */
|
||||
#define HSMCI_IMR_DTOE(value) (HSMCI_IMR_DTOE_Msk & ((value) << HSMCI_IMR_DTOE_Pos))
|
||||
#define HSMCI_IMR_CSTOE_Pos _U_(23) /**< (HSMCI_IMR) Completion Signal Time-out Error Interrupt Mask Position */
|
||||
#define HSMCI_IMR_CSTOE_Msk (_U_(0x1) << HSMCI_IMR_CSTOE_Pos) /**< (HSMCI_IMR) Completion Signal Time-out Error Interrupt Mask Mask */
|
||||
#define HSMCI_IMR_CSTOE(value) (HSMCI_IMR_CSTOE_Msk & ((value) << HSMCI_IMR_CSTOE_Pos))
|
||||
#define HSMCI_IMR_BLKOVRE_Pos _U_(24) /**< (HSMCI_IMR) DMA Block Overrun Error Interrupt Mask Position */
|
||||
#define HSMCI_IMR_BLKOVRE_Msk (_U_(0x1) << HSMCI_IMR_BLKOVRE_Pos) /**< (HSMCI_IMR) DMA Block Overrun Error Interrupt Mask Mask */
|
||||
#define HSMCI_IMR_BLKOVRE(value) (HSMCI_IMR_BLKOVRE_Msk & ((value) << HSMCI_IMR_BLKOVRE_Pos))
|
||||
#define HSMCI_IMR_FIFOEMPTY_Pos _U_(26) /**< (HSMCI_IMR) FIFO Empty Interrupt Mask Position */
|
||||
#define HSMCI_IMR_FIFOEMPTY_Msk (_U_(0x1) << HSMCI_IMR_FIFOEMPTY_Pos) /**< (HSMCI_IMR) FIFO Empty Interrupt Mask Mask */
|
||||
#define HSMCI_IMR_FIFOEMPTY(value) (HSMCI_IMR_FIFOEMPTY_Msk & ((value) << HSMCI_IMR_FIFOEMPTY_Pos))
|
||||
#define HSMCI_IMR_XFRDONE_Pos _U_(27) /**< (HSMCI_IMR) Transfer Done Interrupt Mask Position */
|
||||
#define HSMCI_IMR_XFRDONE_Msk (_U_(0x1) << HSMCI_IMR_XFRDONE_Pos) /**< (HSMCI_IMR) Transfer Done Interrupt Mask Mask */
|
||||
#define HSMCI_IMR_XFRDONE(value) (HSMCI_IMR_XFRDONE_Msk & ((value) << HSMCI_IMR_XFRDONE_Pos))
|
||||
#define HSMCI_IMR_ACKRCV_Pos _U_(28) /**< (HSMCI_IMR) Boot Operation Acknowledge Received Interrupt Mask Position */
|
||||
#define HSMCI_IMR_ACKRCV_Msk (_U_(0x1) << HSMCI_IMR_ACKRCV_Pos) /**< (HSMCI_IMR) Boot Operation Acknowledge Received Interrupt Mask Mask */
|
||||
#define HSMCI_IMR_ACKRCV(value) (HSMCI_IMR_ACKRCV_Msk & ((value) << HSMCI_IMR_ACKRCV_Pos))
|
||||
#define HSMCI_IMR_ACKRCVE_Pos _U_(29) /**< (HSMCI_IMR) Boot Operation Acknowledge Error Interrupt Mask Position */
|
||||
#define HSMCI_IMR_ACKRCVE_Msk (_U_(0x1) << HSMCI_IMR_ACKRCVE_Pos) /**< (HSMCI_IMR) Boot Operation Acknowledge Error Interrupt Mask Mask */
|
||||
#define HSMCI_IMR_ACKRCVE(value) (HSMCI_IMR_ACKRCVE_Msk & ((value) << HSMCI_IMR_ACKRCVE_Pos))
|
||||
#define HSMCI_IMR_OVRE_Pos _U_(30) /**< (HSMCI_IMR) Overrun Interrupt Mask Position */
|
||||
#define HSMCI_IMR_OVRE_Msk (_U_(0x1) << HSMCI_IMR_OVRE_Pos) /**< (HSMCI_IMR) Overrun Interrupt Mask Mask */
|
||||
#define HSMCI_IMR_OVRE(value) (HSMCI_IMR_OVRE_Msk & ((value) << HSMCI_IMR_OVRE_Pos))
|
||||
#define HSMCI_IMR_UNRE_Pos _U_(31) /**< (HSMCI_IMR) Underrun Interrupt Mask Position */
|
||||
#define HSMCI_IMR_UNRE_Msk (_U_(0x1) << HSMCI_IMR_UNRE_Pos) /**< (HSMCI_IMR) Underrun Interrupt Mask Mask */
|
||||
#define HSMCI_IMR_UNRE(value) (HSMCI_IMR_UNRE_Msk & ((value) << HSMCI_IMR_UNRE_Pos))
|
||||
#define HSMCI_IMR_Msk _U_(0xFDFF313F) /**< (HSMCI_IMR) Register Mask */
|
||||
|
||||
|
||||
/* -------- HSMCI_DMA : (HSMCI Offset: 0x50) (R/W 32) DMA Configuration Register -------- */
|
||||
#define HSMCI_DMA_CHKSIZE_Pos _U_(4) /**< (HSMCI_DMA) DMA Channel Read and Write Chunk Size Position */
|
||||
#define HSMCI_DMA_CHKSIZE_Msk (_U_(0x7) << HSMCI_DMA_CHKSIZE_Pos) /**< (HSMCI_DMA) DMA Channel Read and Write Chunk Size Mask */
|
||||
#define HSMCI_DMA_CHKSIZE(value) (HSMCI_DMA_CHKSIZE_Msk & ((value) << HSMCI_DMA_CHKSIZE_Pos))
|
||||
#define HSMCI_DMA_CHKSIZE_1_Val _U_(0x0) /**< (HSMCI_DMA) 1 data available */
|
||||
#define HSMCI_DMA_CHKSIZE_2_Val _U_(0x1) /**< (HSMCI_DMA) 2 data available */
|
||||
#define HSMCI_DMA_CHKSIZE_4_Val _U_(0x2) /**< (HSMCI_DMA) 4 data available */
|
||||
#define HSMCI_DMA_CHKSIZE_8_Val _U_(0x3) /**< (HSMCI_DMA) 8 data available */
|
||||
#define HSMCI_DMA_CHKSIZE_16_Val _U_(0x4) /**< (HSMCI_DMA) 16 data available */
|
||||
#define HSMCI_DMA_CHKSIZE_1 (HSMCI_DMA_CHKSIZE_1_Val << HSMCI_DMA_CHKSIZE_Pos) /**< (HSMCI_DMA) 1 data available Position */
|
||||
#define HSMCI_DMA_CHKSIZE_2 (HSMCI_DMA_CHKSIZE_2_Val << HSMCI_DMA_CHKSIZE_Pos) /**< (HSMCI_DMA) 2 data available Position */
|
||||
#define HSMCI_DMA_CHKSIZE_4 (HSMCI_DMA_CHKSIZE_4_Val << HSMCI_DMA_CHKSIZE_Pos) /**< (HSMCI_DMA) 4 data available Position */
|
||||
#define HSMCI_DMA_CHKSIZE_8 (HSMCI_DMA_CHKSIZE_8_Val << HSMCI_DMA_CHKSIZE_Pos) /**< (HSMCI_DMA) 8 data available Position */
|
||||
#define HSMCI_DMA_CHKSIZE_16 (HSMCI_DMA_CHKSIZE_16_Val << HSMCI_DMA_CHKSIZE_Pos) /**< (HSMCI_DMA) 16 data available Position */
|
||||
#define HSMCI_DMA_DMAEN_Pos _U_(8) /**< (HSMCI_DMA) DMA Hardware Handshaking Enable Position */
|
||||
#define HSMCI_DMA_DMAEN_Msk (_U_(0x1) << HSMCI_DMA_DMAEN_Pos) /**< (HSMCI_DMA) DMA Hardware Handshaking Enable Mask */
|
||||
#define HSMCI_DMA_DMAEN(value) (HSMCI_DMA_DMAEN_Msk & ((value) << HSMCI_DMA_DMAEN_Pos))
|
||||
#define HSMCI_DMA_Msk _U_(0x00000170) /**< (HSMCI_DMA) Register Mask */
|
||||
|
||||
|
||||
/* -------- HSMCI_CFG : (HSMCI Offset: 0x54) (R/W 32) Configuration Register -------- */
|
||||
#define HSMCI_CFG_FIFOMODE_Pos _U_(0) /**< (HSMCI_CFG) HSMCI Internal FIFO control mode Position */
|
||||
#define HSMCI_CFG_FIFOMODE_Msk (_U_(0x1) << HSMCI_CFG_FIFOMODE_Pos) /**< (HSMCI_CFG) HSMCI Internal FIFO control mode Mask */
|
||||
#define HSMCI_CFG_FIFOMODE(value) (HSMCI_CFG_FIFOMODE_Msk & ((value) << HSMCI_CFG_FIFOMODE_Pos))
|
||||
#define HSMCI_CFG_FERRCTRL_Pos _U_(4) /**< (HSMCI_CFG) Flow Error flag reset control mode Position */
|
||||
#define HSMCI_CFG_FERRCTRL_Msk (_U_(0x1) << HSMCI_CFG_FERRCTRL_Pos) /**< (HSMCI_CFG) Flow Error flag reset control mode Mask */
|
||||
#define HSMCI_CFG_FERRCTRL(value) (HSMCI_CFG_FERRCTRL_Msk & ((value) << HSMCI_CFG_FERRCTRL_Pos))
|
||||
#define HSMCI_CFG_HSMODE_Pos _U_(8) /**< (HSMCI_CFG) High Speed Mode Position */
|
||||
#define HSMCI_CFG_HSMODE_Msk (_U_(0x1) << HSMCI_CFG_HSMODE_Pos) /**< (HSMCI_CFG) High Speed Mode Mask */
|
||||
#define HSMCI_CFG_HSMODE(value) (HSMCI_CFG_HSMODE_Msk & ((value) << HSMCI_CFG_HSMODE_Pos))
|
||||
#define HSMCI_CFG_LSYNC_Pos _U_(12) /**< (HSMCI_CFG) Synchronize on the last block Position */
|
||||
#define HSMCI_CFG_LSYNC_Msk (_U_(0x1) << HSMCI_CFG_LSYNC_Pos) /**< (HSMCI_CFG) Synchronize on the last block Mask */
|
||||
#define HSMCI_CFG_LSYNC(value) (HSMCI_CFG_LSYNC_Msk & ((value) << HSMCI_CFG_LSYNC_Pos))
|
||||
#define HSMCI_CFG_Msk _U_(0x00001111) /**< (HSMCI_CFG) Register Mask */
|
||||
|
||||
|
||||
/* -------- HSMCI_WPMR : (HSMCI Offset: 0xE4) (R/W 32) Write Protection Mode Register -------- */
|
||||
#define HSMCI_WPMR_WPEN_Pos _U_(0) /**< (HSMCI_WPMR) Write Protect Enable Position */
|
||||
#define HSMCI_WPMR_WPEN_Msk (_U_(0x1) << HSMCI_WPMR_WPEN_Pos) /**< (HSMCI_WPMR) Write Protect Enable Mask */
|
||||
#define HSMCI_WPMR_WPEN(value) (HSMCI_WPMR_WPEN_Msk & ((value) << HSMCI_WPMR_WPEN_Pos))
|
||||
#define HSMCI_WPMR_WPKEY_Pos _U_(8) /**< (HSMCI_WPMR) Write Protect Key Position */
|
||||
#define HSMCI_WPMR_WPKEY_Msk (_U_(0xFFFFFF) << HSMCI_WPMR_WPKEY_Pos) /**< (HSMCI_WPMR) Write Protect Key Mask */
|
||||
#define HSMCI_WPMR_WPKEY(value) (HSMCI_WPMR_WPKEY_Msk & ((value) << HSMCI_WPMR_WPKEY_Pos))
|
||||
#define HSMCI_WPMR_WPKEY_PASSWD_Val _U_(0x4D4349) /**< (HSMCI_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. */
|
||||
#define HSMCI_WPMR_WPKEY_PASSWD (HSMCI_WPMR_WPKEY_PASSWD_Val << HSMCI_WPMR_WPKEY_Pos) /**< (HSMCI_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. Position */
|
||||
#define HSMCI_WPMR_Msk _U_(0xFFFFFF01) /**< (HSMCI_WPMR) Register Mask */
|
||||
|
||||
|
||||
/* -------- HSMCI_WPSR : (HSMCI Offset: 0xE8) ( R/ 32) Write Protection Status Register -------- */
|
||||
#define HSMCI_WPSR_WPVS_Pos _U_(0) /**< (HSMCI_WPSR) Write Protection Violation Status Position */
|
||||
#define HSMCI_WPSR_WPVS_Msk (_U_(0x1) << HSMCI_WPSR_WPVS_Pos) /**< (HSMCI_WPSR) Write Protection Violation Status Mask */
|
||||
#define HSMCI_WPSR_WPVS(value) (HSMCI_WPSR_WPVS_Msk & ((value) << HSMCI_WPSR_WPVS_Pos))
|
||||
#define HSMCI_WPSR_WPVSRC_Pos _U_(8) /**< (HSMCI_WPSR) Write Protection Violation Source Position */
|
||||
#define HSMCI_WPSR_WPVSRC_Msk (_U_(0xFFFF) << HSMCI_WPSR_WPVSRC_Pos) /**< (HSMCI_WPSR) Write Protection Violation Source Mask */
|
||||
#define HSMCI_WPSR_WPVSRC(value) (HSMCI_WPSR_WPVSRC_Msk & ((value) << HSMCI_WPSR_WPVSRC_Pos))
|
||||
#define HSMCI_WPSR_Msk _U_(0x00FFFF01) /**< (HSMCI_WPSR) Register Mask */
|
||||
|
||||
|
||||
/* -------- HSMCI_FIFO : (HSMCI Offset: 0x200) (R/W 32) FIFO Memory Aperture0 0 -------- */
|
||||
#define HSMCI_FIFO_DATA_Pos _U_(0) /**< (HSMCI_FIFO) Data to Read or Data to Write Position */
|
||||
#define HSMCI_FIFO_DATA_Msk (_U_(0xFFFFFFFF) << HSMCI_FIFO_DATA_Pos) /**< (HSMCI_FIFO) Data to Read or Data to Write Mask */
|
||||
#define HSMCI_FIFO_DATA(value) (HSMCI_FIFO_DATA_Msk & ((value) << HSMCI_FIFO_DATA_Pos))
|
||||
#define HSMCI_FIFO_Msk _U_(0xFFFFFFFF) /**< (HSMCI_FIFO) Register Mask */
|
||||
|
||||
|
||||
/** \brief HSMCI register offsets definitions */
|
||||
#define HSMCI_CR_REG_OFST (0x00) /**< (HSMCI_CR) Control Register Offset */
|
||||
#define HSMCI_MR_REG_OFST (0x04) /**< (HSMCI_MR) Mode Register Offset */
|
||||
#define HSMCI_DTOR_REG_OFST (0x08) /**< (HSMCI_DTOR) Data Timeout Register Offset */
|
||||
#define HSMCI_SDCR_REG_OFST (0x0C) /**< (HSMCI_SDCR) SD/SDIO Card Register Offset */
|
||||
#define HSMCI_ARGR_REG_OFST (0x10) /**< (HSMCI_ARGR) Argument Register Offset */
|
||||
#define HSMCI_CMDR_REG_OFST (0x14) /**< (HSMCI_CMDR) Command Register Offset */
|
||||
#define HSMCI_BLKR_REG_OFST (0x18) /**< (HSMCI_BLKR) Block Register Offset */
|
||||
#define HSMCI_CSTOR_REG_OFST (0x1C) /**< (HSMCI_CSTOR) Completion Signal Timeout Register Offset */
|
||||
#define HSMCI_RSPR_REG_OFST (0x20) /**< (HSMCI_RSPR) Response Register 0 Offset */
|
||||
#define HSMCI_RDR_REG_OFST (0x30) /**< (HSMCI_RDR) Receive Data Register Offset */
|
||||
#define HSMCI_TDR_REG_OFST (0x34) /**< (HSMCI_TDR) Transmit Data Register Offset */
|
||||
#define HSMCI_SR_REG_OFST (0x40) /**< (HSMCI_SR) Status Register Offset */
|
||||
#define HSMCI_IER_REG_OFST (0x44) /**< (HSMCI_IER) Interrupt Enable Register Offset */
|
||||
#define HSMCI_IDR_REG_OFST (0x48) /**< (HSMCI_IDR) Interrupt Disable Register Offset */
|
||||
#define HSMCI_IMR_REG_OFST (0x4C) /**< (HSMCI_IMR) Interrupt Mask Register Offset */
|
||||
#define HSMCI_DMA_REG_OFST (0x50) /**< (HSMCI_DMA) DMA Configuration Register Offset */
|
||||
#define HSMCI_CFG_REG_OFST (0x54) /**< (HSMCI_CFG) Configuration Register Offset */
|
||||
#define HSMCI_WPMR_REG_OFST (0xE4) /**< (HSMCI_WPMR) Write Protection Mode Register Offset */
|
||||
#define HSMCI_WPSR_REG_OFST (0xE8) /**< (HSMCI_WPSR) Write Protection Status Register Offset */
|
||||
#define HSMCI_FIFO_REG_OFST (0x200) /**< (HSMCI_FIFO) FIFO Memory Aperture0 0 Offset */
|
||||
|
||||
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
/** \brief HSMCI register API structure */
|
||||
typedef struct
|
||||
{
|
||||
__O uint32_t HSMCI_CR; /**< Offset: 0x00 ( /W 32) Control Register */
|
||||
__IO uint32_t HSMCI_MR; /**< Offset: 0x04 (R/W 32) Mode Register */
|
||||
__IO uint32_t HSMCI_DTOR; /**< Offset: 0x08 (R/W 32) Data Timeout Register */
|
||||
__IO uint32_t HSMCI_SDCR; /**< Offset: 0x0C (R/W 32) SD/SDIO Card Register */
|
||||
__IO uint32_t HSMCI_ARGR; /**< Offset: 0x10 (R/W 32) Argument Register */
|
||||
__O uint32_t HSMCI_CMDR; /**< Offset: 0x14 ( /W 32) Command Register */
|
||||
__IO uint32_t HSMCI_BLKR; /**< Offset: 0x18 (R/W 32) Block Register */
|
||||
__IO uint32_t HSMCI_CSTOR; /**< Offset: 0x1C (R/W 32) Completion Signal Timeout Register */
|
||||
__I uint32_t HSMCI_RSPR[4]; /**< Offset: 0x20 (R/ 32) Response Register 0 */
|
||||
__I uint32_t HSMCI_RDR; /**< Offset: 0x30 (R/ 32) Receive Data Register */
|
||||
__O uint32_t HSMCI_TDR; /**< Offset: 0x34 ( /W 32) Transmit Data Register */
|
||||
__I uint8_t Reserved1[0x08];
|
||||
__I uint32_t HSMCI_SR; /**< Offset: 0x40 (R/ 32) Status Register */
|
||||
__O uint32_t HSMCI_IER; /**< Offset: 0x44 ( /W 32) Interrupt Enable Register */
|
||||
__O uint32_t HSMCI_IDR; /**< Offset: 0x48 ( /W 32) Interrupt Disable Register */
|
||||
__I uint32_t HSMCI_IMR; /**< Offset: 0x4C (R/ 32) Interrupt Mask Register */
|
||||
__IO uint32_t HSMCI_DMA; /**< Offset: 0x50 (R/W 32) DMA Configuration Register */
|
||||
__IO uint32_t HSMCI_CFG; /**< Offset: 0x54 (R/W 32) Configuration Register */
|
||||
__I uint8_t Reserved2[0x8C];
|
||||
__IO uint32_t HSMCI_WPMR; /**< Offset: 0xE4 (R/W 32) Write Protection Mode Register */
|
||||
__I uint32_t HSMCI_WPSR; /**< Offset: 0xE8 (R/ 32) Write Protection Status Register */
|
||||
__I uint8_t Reserved3[0x114];
|
||||
__IO uint32_t HSMCI_FIFO[256]; /**< Offset: 0x200 (R/W 32) FIFO Memory Aperture0 0 */
|
||||
} hsmci_registers_t;
|
||||
|
||||
|
||||
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
#endif /* _SAME70_HSMCI_COMPONENT_H_ */
|
||||
@ -0,0 +1,272 @@
|
||||
/**
|
||||
* \brief Component description for ICM
|
||||
*
|
||||
* Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries.
|
||||
*
|
||||
* Subject to your compliance with these terms, you may use Microchip software and any derivatives
|
||||
* exclusively with Microchip products. It is your responsibility to comply with third party license
|
||||
* terms applicable to your use of third party software (including open source software) that may
|
||||
* accompany Microchip software.
|
||||
*
|
||||
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY,
|
||||
* APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND
|
||||
* FITNESS FOR A PARTICULAR PURPOSE.
|
||||
*
|
||||
* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
|
||||
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF
|
||||
* MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
|
||||
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT
|
||||
* EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
|
||||
*
|
||||
*/
|
||||
|
||||
/* file generated from device description version 2017-08-25T14:00:00Z */
|
||||
#ifndef _SAME70_ICM_COMPONENT_H_
|
||||
#define _SAME70_ICM_COMPONENT_H_
|
||||
|
||||
/* ************************************************************************** */
|
||||
/* SOFTWARE API DEFINITION FOR ICM */
|
||||
/* ************************************************************************** */
|
||||
|
||||
/* -------- ICM_CFG : (ICM Offset: 0x00) (R/W 32) Configuration Register -------- */
|
||||
#define ICM_CFG_WBDIS_Pos _U_(0) /**< (ICM_CFG) Write Back Disable Position */
|
||||
#define ICM_CFG_WBDIS_Msk (_U_(0x1) << ICM_CFG_WBDIS_Pos) /**< (ICM_CFG) Write Back Disable Mask */
|
||||
#define ICM_CFG_WBDIS(value) (ICM_CFG_WBDIS_Msk & ((value) << ICM_CFG_WBDIS_Pos))
|
||||
#define ICM_CFG_EOMDIS_Pos _U_(1) /**< (ICM_CFG) End of Monitoring Disable Position */
|
||||
#define ICM_CFG_EOMDIS_Msk (_U_(0x1) << ICM_CFG_EOMDIS_Pos) /**< (ICM_CFG) End of Monitoring Disable Mask */
|
||||
#define ICM_CFG_EOMDIS(value) (ICM_CFG_EOMDIS_Msk & ((value) << ICM_CFG_EOMDIS_Pos))
|
||||
#define ICM_CFG_SLBDIS_Pos _U_(2) /**< (ICM_CFG) Secondary List Branching Disable Position */
|
||||
#define ICM_CFG_SLBDIS_Msk (_U_(0x1) << ICM_CFG_SLBDIS_Pos) /**< (ICM_CFG) Secondary List Branching Disable Mask */
|
||||
#define ICM_CFG_SLBDIS(value) (ICM_CFG_SLBDIS_Msk & ((value) << ICM_CFG_SLBDIS_Pos))
|
||||
#define ICM_CFG_BBC_Pos _U_(4) /**< (ICM_CFG) Bus Burden Control Position */
|
||||
#define ICM_CFG_BBC_Msk (_U_(0xF) << ICM_CFG_BBC_Pos) /**< (ICM_CFG) Bus Burden Control Mask */
|
||||
#define ICM_CFG_BBC(value) (ICM_CFG_BBC_Msk & ((value) << ICM_CFG_BBC_Pos))
|
||||
#define ICM_CFG_ASCD_Pos _U_(8) /**< (ICM_CFG) Automatic Switch To Compare Digest Position */
|
||||
#define ICM_CFG_ASCD_Msk (_U_(0x1) << ICM_CFG_ASCD_Pos) /**< (ICM_CFG) Automatic Switch To Compare Digest Mask */
|
||||
#define ICM_CFG_ASCD(value) (ICM_CFG_ASCD_Msk & ((value) << ICM_CFG_ASCD_Pos))
|
||||
#define ICM_CFG_DUALBUFF_Pos _U_(9) /**< (ICM_CFG) Dual Input Buffer Position */
|
||||
#define ICM_CFG_DUALBUFF_Msk (_U_(0x1) << ICM_CFG_DUALBUFF_Pos) /**< (ICM_CFG) Dual Input Buffer Mask */
|
||||
#define ICM_CFG_DUALBUFF(value) (ICM_CFG_DUALBUFF_Msk & ((value) << ICM_CFG_DUALBUFF_Pos))
|
||||
#define ICM_CFG_UIHASH_Pos _U_(12) /**< (ICM_CFG) User Initial Hash Value Position */
|
||||
#define ICM_CFG_UIHASH_Msk (_U_(0x1) << ICM_CFG_UIHASH_Pos) /**< (ICM_CFG) User Initial Hash Value Mask */
|
||||
#define ICM_CFG_UIHASH(value) (ICM_CFG_UIHASH_Msk & ((value) << ICM_CFG_UIHASH_Pos))
|
||||
#define ICM_CFG_UALGO_Pos _U_(13) /**< (ICM_CFG) User SHA Algorithm Position */
|
||||
#define ICM_CFG_UALGO_Msk (_U_(0x7) << ICM_CFG_UALGO_Pos) /**< (ICM_CFG) User SHA Algorithm Mask */
|
||||
#define ICM_CFG_UALGO(value) (ICM_CFG_UALGO_Msk & ((value) << ICM_CFG_UALGO_Pos))
|
||||
#define ICM_CFG_UALGO_SHA1_Val _U_(0x0) /**< (ICM_CFG) SHA1 algorithm processed */
|
||||
#define ICM_CFG_UALGO_SHA256_Val _U_(0x1) /**< (ICM_CFG) SHA256 algorithm processed */
|
||||
#define ICM_CFG_UALGO_SHA224_Val _U_(0x4) /**< (ICM_CFG) SHA224 algorithm processed */
|
||||
#define ICM_CFG_UALGO_SHA1 (ICM_CFG_UALGO_SHA1_Val << ICM_CFG_UALGO_Pos) /**< (ICM_CFG) SHA1 algorithm processed Position */
|
||||
#define ICM_CFG_UALGO_SHA256 (ICM_CFG_UALGO_SHA256_Val << ICM_CFG_UALGO_Pos) /**< (ICM_CFG) SHA256 algorithm processed Position */
|
||||
#define ICM_CFG_UALGO_SHA224 (ICM_CFG_UALGO_SHA224_Val << ICM_CFG_UALGO_Pos) /**< (ICM_CFG) SHA224 algorithm processed Position */
|
||||
#define ICM_CFG_Msk _U_(0x0000F3F7) /**< (ICM_CFG) Register Mask */
|
||||
|
||||
|
||||
/* -------- ICM_CTRL : (ICM Offset: 0x04) ( /W 32) Control Register -------- */
|
||||
#define ICM_CTRL_ENABLE_Pos _U_(0) /**< (ICM_CTRL) ICM Enable Position */
|
||||
#define ICM_CTRL_ENABLE_Msk (_U_(0x1) << ICM_CTRL_ENABLE_Pos) /**< (ICM_CTRL) ICM Enable Mask */
|
||||
#define ICM_CTRL_ENABLE(value) (ICM_CTRL_ENABLE_Msk & ((value) << ICM_CTRL_ENABLE_Pos))
|
||||
#define ICM_CTRL_DISABLE_Pos _U_(1) /**< (ICM_CTRL) ICM Disable Register Position */
|
||||
#define ICM_CTRL_DISABLE_Msk (_U_(0x1) << ICM_CTRL_DISABLE_Pos) /**< (ICM_CTRL) ICM Disable Register Mask */
|
||||
#define ICM_CTRL_DISABLE(value) (ICM_CTRL_DISABLE_Msk & ((value) << ICM_CTRL_DISABLE_Pos))
|
||||
#define ICM_CTRL_SWRST_Pos _U_(2) /**< (ICM_CTRL) Software Reset Position */
|
||||
#define ICM_CTRL_SWRST_Msk (_U_(0x1) << ICM_CTRL_SWRST_Pos) /**< (ICM_CTRL) Software Reset Mask */
|
||||
#define ICM_CTRL_SWRST(value) (ICM_CTRL_SWRST_Msk & ((value) << ICM_CTRL_SWRST_Pos))
|
||||
#define ICM_CTRL_REHASH_Pos _U_(4) /**< (ICM_CTRL) Recompute Internal Hash Position */
|
||||
#define ICM_CTRL_REHASH_Msk (_U_(0xF) << ICM_CTRL_REHASH_Pos) /**< (ICM_CTRL) Recompute Internal Hash Mask */
|
||||
#define ICM_CTRL_REHASH(value) (ICM_CTRL_REHASH_Msk & ((value) << ICM_CTRL_REHASH_Pos))
|
||||
#define ICM_CTRL_RMDIS_Pos _U_(8) /**< (ICM_CTRL) Region Monitoring Disable Position */
|
||||
#define ICM_CTRL_RMDIS_Msk (_U_(0xF) << ICM_CTRL_RMDIS_Pos) /**< (ICM_CTRL) Region Monitoring Disable Mask */
|
||||
#define ICM_CTRL_RMDIS(value) (ICM_CTRL_RMDIS_Msk & ((value) << ICM_CTRL_RMDIS_Pos))
|
||||
#define ICM_CTRL_RMEN_Pos _U_(12) /**< (ICM_CTRL) Region Monitoring Enable Position */
|
||||
#define ICM_CTRL_RMEN_Msk (_U_(0xF) << ICM_CTRL_RMEN_Pos) /**< (ICM_CTRL) Region Monitoring Enable Mask */
|
||||
#define ICM_CTRL_RMEN(value) (ICM_CTRL_RMEN_Msk & ((value) << ICM_CTRL_RMEN_Pos))
|
||||
#define ICM_CTRL_Msk _U_(0x0000FFF7) /**< (ICM_CTRL) Register Mask */
|
||||
|
||||
|
||||
/* -------- ICM_SR : (ICM Offset: 0x08) ( R/ 32) Status Register -------- */
|
||||
#define ICM_SR_ENABLE_Pos _U_(0) /**< (ICM_SR) ICM Controller Enable Register Position */
|
||||
#define ICM_SR_ENABLE_Msk (_U_(0x1) << ICM_SR_ENABLE_Pos) /**< (ICM_SR) ICM Controller Enable Register Mask */
|
||||
#define ICM_SR_ENABLE(value) (ICM_SR_ENABLE_Msk & ((value) << ICM_SR_ENABLE_Pos))
|
||||
#define ICM_SR_RAWRMDIS_Pos _U_(8) /**< (ICM_SR) Region Monitoring Disabled Raw Status Position */
|
||||
#define ICM_SR_RAWRMDIS_Msk (_U_(0xF) << ICM_SR_RAWRMDIS_Pos) /**< (ICM_SR) Region Monitoring Disabled Raw Status Mask */
|
||||
#define ICM_SR_RAWRMDIS(value) (ICM_SR_RAWRMDIS_Msk & ((value) << ICM_SR_RAWRMDIS_Pos))
|
||||
#define ICM_SR_RMDIS_Pos _U_(12) /**< (ICM_SR) Region Monitoring Disabled Status Position */
|
||||
#define ICM_SR_RMDIS_Msk (_U_(0xF) << ICM_SR_RMDIS_Pos) /**< (ICM_SR) Region Monitoring Disabled Status Mask */
|
||||
#define ICM_SR_RMDIS(value) (ICM_SR_RMDIS_Msk & ((value) << ICM_SR_RMDIS_Pos))
|
||||
#define ICM_SR_Msk _U_(0x0000FF01) /**< (ICM_SR) Register Mask */
|
||||
|
||||
|
||||
/* -------- ICM_IER : (ICM Offset: 0x10) ( /W 32) Interrupt Enable Register -------- */
|
||||
#define ICM_IER_RHC_Pos _U_(0) /**< (ICM_IER) Region Hash Completed Interrupt Enable Position */
|
||||
#define ICM_IER_RHC_Msk (_U_(0xF) << ICM_IER_RHC_Pos) /**< (ICM_IER) Region Hash Completed Interrupt Enable Mask */
|
||||
#define ICM_IER_RHC(value) (ICM_IER_RHC_Msk & ((value) << ICM_IER_RHC_Pos))
|
||||
#define ICM_IER_RDM_Pos _U_(4) /**< (ICM_IER) Region Digest Mismatch Interrupt Enable Position */
|
||||
#define ICM_IER_RDM_Msk (_U_(0xF) << ICM_IER_RDM_Pos) /**< (ICM_IER) Region Digest Mismatch Interrupt Enable Mask */
|
||||
#define ICM_IER_RDM(value) (ICM_IER_RDM_Msk & ((value) << ICM_IER_RDM_Pos))
|
||||
#define ICM_IER_RBE_Pos _U_(8) /**< (ICM_IER) Region Bus Error Interrupt Enable Position */
|
||||
#define ICM_IER_RBE_Msk (_U_(0xF) << ICM_IER_RBE_Pos) /**< (ICM_IER) Region Bus Error Interrupt Enable Mask */
|
||||
#define ICM_IER_RBE(value) (ICM_IER_RBE_Msk & ((value) << ICM_IER_RBE_Pos))
|
||||
#define ICM_IER_RWC_Pos _U_(12) /**< (ICM_IER) Region Wrap Condition detected Interrupt Enable Position */
|
||||
#define ICM_IER_RWC_Msk (_U_(0xF) << ICM_IER_RWC_Pos) /**< (ICM_IER) Region Wrap Condition detected Interrupt Enable Mask */
|
||||
#define ICM_IER_RWC(value) (ICM_IER_RWC_Msk & ((value) << ICM_IER_RWC_Pos))
|
||||
#define ICM_IER_REC_Pos _U_(16) /**< (ICM_IER) Region End bit Condition Detected Interrupt Enable Position */
|
||||
#define ICM_IER_REC_Msk (_U_(0xF) << ICM_IER_REC_Pos) /**< (ICM_IER) Region End bit Condition Detected Interrupt Enable Mask */
|
||||
#define ICM_IER_REC(value) (ICM_IER_REC_Msk & ((value) << ICM_IER_REC_Pos))
|
||||
#define ICM_IER_RSU_Pos _U_(20) /**< (ICM_IER) Region Status Updated Interrupt Disable Position */
|
||||
#define ICM_IER_RSU_Msk (_U_(0xF) << ICM_IER_RSU_Pos) /**< (ICM_IER) Region Status Updated Interrupt Disable Mask */
|
||||
#define ICM_IER_RSU(value) (ICM_IER_RSU_Msk & ((value) << ICM_IER_RSU_Pos))
|
||||
#define ICM_IER_URAD_Pos _U_(24) /**< (ICM_IER) Undefined Register Access Detection Interrupt Enable Position */
|
||||
#define ICM_IER_URAD_Msk (_U_(0x1) << ICM_IER_URAD_Pos) /**< (ICM_IER) Undefined Register Access Detection Interrupt Enable Mask */
|
||||
#define ICM_IER_URAD(value) (ICM_IER_URAD_Msk & ((value) << ICM_IER_URAD_Pos))
|
||||
#define ICM_IER_Msk _U_(0x01FFFFFF) /**< (ICM_IER) Register Mask */
|
||||
|
||||
|
||||
/* -------- ICM_IDR : (ICM Offset: 0x14) ( /W 32) Interrupt Disable Register -------- */
|
||||
#define ICM_IDR_RHC_Pos _U_(0) /**< (ICM_IDR) Region Hash Completed Interrupt Disable Position */
|
||||
#define ICM_IDR_RHC_Msk (_U_(0xF) << ICM_IDR_RHC_Pos) /**< (ICM_IDR) Region Hash Completed Interrupt Disable Mask */
|
||||
#define ICM_IDR_RHC(value) (ICM_IDR_RHC_Msk & ((value) << ICM_IDR_RHC_Pos))
|
||||
#define ICM_IDR_RDM_Pos _U_(4) /**< (ICM_IDR) Region Digest Mismatch Interrupt Disable Position */
|
||||
#define ICM_IDR_RDM_Msk (_U_(0xF) << ICM_IDR_RDM_Pos) /**< (ICM_IDR) Region Digest Mismatch Interrupt Disable Mask */
|
||||
#define ICM_IDR_RDM(value) (ICM_IDR_RDM_Msk & ((value) << ICM_IDR_RDM_Pos))
|
||||
#define ICM_IDR_RBE_Pos _U_(8) /**< (ICM_IDR) Region Bus Error Interrupt Disable Position */
|
||||
#define ICM_IDR_RBE_Msk (_U_(0xF) << ICM_IDR_RBE_Pos) /**< (ICM_IDR) Region Bus Error Interrupt Disable Mask */
|
||||
#define ICM_IDR_RBE(value) (ICM_IDR_RBE_Msk & ((value) << ICM_IDR_RBE_Pos))
|
||||
#define ICM_IDR_RWC_Pos _U_(12) /**< (ICM_IDR) Region Wrap Condition Detected Interrupt Disable Position */
|
||||
#define ICM_IDR_RWC_Msk (_U_(0xF) << ICM_IDR_RWC_Pos) /**< (ICM_IDR) Region Wrap Condition Detected Interrupt Disable Mask */
|
||||
#define ICM_IDR_RWC(value) (ICM_IDR_RWC_Msk & ((value) << ICM_IDR_RWC_Pos))
|
||||
#define ICM_IDR_REC_Pos _U_(16) /**< (ICM_IDR) Region End bit Condition detected Interrupt Disable Position */
|
||||
#define ICM_IDR_REC_Msk (_U_(0xF) << ICM_IDR_REC_Pos) /**< (ICM_IDR) Region End bit Condition detected Interrupt Disable Mask */
|
||||
#define ICM_IDR_REC(value) (ICM_IDR_REC_Msk & ((value) << ICM_IDR_REC_Pos))
|
||||
#define ICM_IDR_RSU_Pos _U_(20) /**< (ICM_IDR) Region Status Updated Interrupt Disable Position */
|
||||
#define ICM_IDR_RSU_Msk (_U_(0xF) << ICM_IDR_RSU_Pos) /**< (ICM_IDR) Region Status Updated Interrupt Disable Mask */
|
||||
#define ICM_IDR_RSU(value) (ICM_IDR_RSU_Msk & ((value) << ICM_IDR_RSU_Pos))
|
||||
#define ICM_IDR_URAD_Pos _U_(24) /**< (ICM_IDR) Undefined Register Access Detection Interrupt Disable Position */
|
||||
#define ICM_IDR_URAD_Msk (_U_(0x1) << ICM_IDR_URAD_Pos) /**< (ICM_IDR) Undefined Register Access Detection Interrupt Disable Mask */
|
||||
#define ICM_IDR_URAD(value) (ICM_IDR_URAD_Msk & ((value) << ICM_IDR_URAD_Pos))
|
||||
#define ICM_IDR_Msk _U_(0x01FFFFFF) /**< (ICM_IDR) Register Mask */
|
||||
|
||||
|
||||
/* -------- ICM_IMR : (ICM Offset: 0x18) ( R/ 32) Interrupt Mask Register -------- */
|
||||
#define ICM_IMR_RHC_Pos _U_(0) /**< (ICM_IMR) Region Hash Completed Interrupt Mask Position */
|
||||
#define ICM_IMR_RHC_Msk (_U_(0xF) << ICM_IMR_RHC_Pos) /**< (ICM_IMR) Region Hash Completed Interrupt Mask Mask */
|
||||
#define ICM_IMR_RHC(value) (ICM_IMR_RHC_Msk & ((value) << ICM_IMR_RHC_Pos))
|
||||
#define ICM_IMR_RDM_Pos _U_(4) /**< (ICM_IMR) Region Digest Mismatch Interrupt Mask Position */
|
||||
#define ICM_IMR_RDM_Msk (_U_(0xF) << ICM_IMR_RDM_Pos) /**< (ICM_IMR) Region Digest Mismatch Interrupt Mask Mask */
|
||||
#define ICM_IMR_RDM(value) (ICM_IMR_RDM_Msk & ((value) << ICM_IMR_RDM_Pos))
|
||||
#define ICM_IMR_RBE_Pos _U_(8) /**< (ICM_IMR) Region Bus Error Interrupt Mask Position */
|
||||
#define ICM_IMR_RBE_Msk (_U_(0xF) << ICM_IMR_RBE_Pos) /**< (ICM_IMR) Region Bus Error Interrupt Mask Mask */
|
||||
#define ICM_IMR_RBE(value) (ICM_IMR_RBE_Msk & ((value) << ICM_IMR_RBE_Pos))
|
||||
#define ICM_IMR_RWC_Pos _U_(12) /**< (ICM_IMR) Region Wrap Condition Detected Interrupt Mask Position */
|
||||
#define ICM_IMR_RWC_Msk (_U_(0xF) << ICM_IMR_RWC_Pos) /**< (ICM_IMR) Region Wrap Condition Detected Interrupt Mask Mask */
|
||||
#define ICM_IMR_RWC(value) (ICM_IMR_RWC_Msk & ((value) << ICM_IMR_RWC_Pos))
|
||||
#define ICM_IMR_REC_Pos _U_(16) /**< (ICM_IMR) Region End bit Condition Detected Interrupt Mask Position */
|
||||
#define ICM_IMR_REC_Msk (_U_(0xF) << ICM_IMR_REC_Pos) /**< (ICM_IMR) Region End bit Condition Detected Interrupt Mask Mask */
|
||||
#define ICM_IMR_REC(value) (ICM_IMR_REC_Msk & ((value) << ICM_IMR_REC_Pos))
|
||||
#define ICM_IMR_RSU_Pos _U_(20) /**< (ICM_IMR) Region Status Updated Interrupt Mask Position */
|
||||
#define ICM_IMR_RSU_Msk (_U_(0xF) << ICM_IMR_RSU_Pos) /**< (ICM_IMR) Region Status Updated Interrupt Mask Mask */
|
||||
#define ICM_IMR_RSU(value) (ICM_IMR_RSU_Msk & ((value) << ICM_IMR_RSU_Pos))
|
||||
#define ICM_IMR_URAD_Pos _U_(24) /**< (ICM_IMR) Undefined Register Access Detection Interrupt Mask Position */
|
||||
#define ICM_IMR_URAD_Msk (_U_(0x1) << ICM_IMR_URAD_Pos) /**< (ICM_IMR) Undefined Register Access Detection Interrupt Mask Mask */
|
||||
#define ICM_IMR_URAD(value) (ICM_IMR_URAD_Msk & ((value) << ICM_IMR_URAD_Pos))
|
||||
#define ICM_IMR_Msk _U_(0x01FFFFFF) /**< (ICM_IMR) Register Mask */
|
||||
|
||||
|
||||
/* -------- ICM_ISR : (ICM Offset: 0x1C) ( R/ 32) Interrupt Status Register -------- */
|
||||
#define ICM_ISR_RHC_Pos _U_(0) /**< (ICM_ISR) Region Hash Completed Position */
|
||||
#define ICM_ISR_RHC_Msk (_U_(0xF) << ICM_ISR_RHC_Pos) /**< (ICM_ISR) Region Hash Completed Mask */
|
||||
#define ICM_ISR_RHC(value) (ICM_ISR_RHC_Msk & ((value) << ICM_ISR_RHC_Pos))
|
||||
#define ICM_ISR_RDM_Pos _U_(4) /**< (ICM_ISR) Region Digest Mismatch Position */
|
||||
#define ICM_ISR_RDM_Msk (_U_(0xF) << ICM_ISR_RDM_Pos) /**< (ICM_ISR) Region Digest Mismatch Mask */
|
||||
#define ICM_ISR_RDM(value) (ICM_ISR_RDM_Msk & ((value) << ICM_ISR_RDM_Pos))
|
||||
#define ICM_ISR_RBE_Pos _U_(8) /**< (ICM_ISR) Region Bus Error Position */
|
||||
#define ICM_ISR_RBE_Msk (_U_(0xF) << ICM_ISR_RBE_Pos) /**< (ICM_ISR) Region Bus Error Mask */
|
||||
#define ICM_ISR_RBE(value) (ICM_ISR_RBE_Msk & ((value) << ICM_ISR_RBE_Pos))
|
||||
#define ICM_ISR_RWC_Pos _U_(12) /**< (ICM_ISR) Region Wrap Condition Detected Position */
|
||||
#define ICM_ISR_RWC_Msk (_U_(0xF) << ICM_ISR_RWC_Pos) /**< (ICM_ISR) Region Wrap Condition Detected Mask */
|
||||
#define ICM_ISR_RWC(value) (ICM_ISR_RWC_Msk & ((value) << ICM_ISR_RWC_Pos))
|
||||
#define ICM_ISR_REC_Pos _U_(16) /**< (ICM_ISR) Region End bit Condition Detected Position */
|
||||
#define ICM_ISR_REC_Msk (_U_(0xF) << ICM_ISR_REC_Pos) /**< (ICM_ISR) Region End bit Condition Detected Mask */
|
||||
#define ICM_ISR_REC(value) (ICM_ISR_REC_Msk & ((value) << ICM_ISR_REC_Pos))
|
||||
#define ICM_ISR_RSU_Pos _U_(20) /**< (ICM_ISR) Region Status Updated Detected Position */
|
||||
#define ICM_ISR_RSU_Msk (_U_(0xF) << ICM_ISR_RSU_Pos) /**< (ICM_ISR) Region Status Updated Detected Mask */
|
||||
#define ICM_ISR_RSU(value) (ICM_ISR_RSU_Msk & ((value) << ICM_ISR_RSU_Pos))
|
||||
#define ICM_ISR_URAD_Pos _U_(24) /**< (ICM_ISR) Undefined Register Access Detection Status Position */
|
||||
#define ICM_ISR_URAD_Msk (_U_(0x1) << ICM_ISR_URAD_Pos) /**< (ICM_ISR) Undefined Register Access Detection Status Mask */
|
||||
#define ICM_ISR_URAD(value) (ICM_ISR_URAD_Msk & ((value) << ICM_ISR_URAD_Pos))
|
||||
#define ICM_ISR_Msk _U_(0x01FFFFFF) /**< (ICM_ISR) Register Mask */
|
||||
|
||||
|
||||
/* -------- ICM_UASR : (ICM Offset: 0x20) ( R/ 32) Undefined Access Status Register -------- */
|
||||
#define ICM_UASR_URAT_Pos _U_(0) /**< (ICM_UASR) Undefined Register Access Trace Position */
|
||||
#define ICM_UASR_URAT_Msk (_U_(0x7) << ICM_UASR_URAT_Pos) /**< (ICM_UASR) Undefined Register Access Trace Mask */
|
||||
#define ICM_UASR_URAT(value) (ICM_UASR_URAT_Msk & ((value) << ICM_UASR_URAT_Pos))
|
||||
#define ICM_UASR_URAT_UNSPEC_STRUCT_MEMBER_Val _U_(0x0) /**< (ICM_UASR) Unspecified structure member set to one detected when the descriptor is loaded. */
|
||||
#define ICM_UASR_URAT_ICM_CFG_MODIFIED_Val _U_(0x1) /**< (ICM_UASR) ICM_CFG modified during active monitoring. */
|
||||
#define ICM_UASR_URAT_ICM_DSCR_MODIFIED_Val _U_(0x2) /**< (ICM_UASR) ICM_DSCR modified during active monitoring. */
|
||||
#define ICM_UASR_URAT_ICM_HASH_MODIFIED_Val _U_(0x3) /**< (ICM_UASR) ICM_HASH modified during active monitoring */
|
||||
#define ICM_UASR_URAT_READ_ACCESS_Val _U_(0x4) /**< (ICM_UASR) Write-only register read access */
|
||||
#define ICM_UASR_URAT_UNSPEC_STRUCT_MEMBER (ICM_UASR_URAT_UNSPEC_STRUCT_MEMBER_Val << ICM_UASR_URAT_Pos) /**< (ICM_UASR) Unspecified structure member set to one detected when the descriptor is loaded. Position */
|
||||
#define ICM_UASR_URAT_ICM_CFG_MODIFIED (ICM_UASR_URAT_ICM_CFG_MODIFIED_Val << ICM_UASR_URAT_Pos) /**< (ICM_UASR) ICM_CFG modified during active monitoring. Position */
|
||||
#define ICM_UASR_URAT_ICM_DSCR_MODIFIED (ICM_UASR_URAT_ICM_DSCR_MODIFIED_Val << ICM_UASR_URAT_Pos) /**< (ICM_UASR) ICM_DSCR modified during active monitoring. Position */
|
||||
#define ICM_UASR_URAT_ICM_HASH_MODIFIED (ICM_UASR_URAT_ICM_HASH_MODIFIED_Val << ICM_UASR_URAT_Pos) /**< (ICM_UASR) ICM_HASH modified during active monitoring Position */
|
||||
#define ICM_UASR_URAT_READ_ACCESS (ICM_UASR_URAT_READ_ACCESS_Val << ICM_UASR_URAT_Pos) /**< (ICM_UASR) Write-only register read access Position */
|
||||
#define ICM_UASR_Msk _U_(0x00000007) /**< (ICM_UASR) Register Mask */
|
||||
|
||||
|
||||
/* -------- ICM_DSCR : (ICM Offset: 0x30) (R/W 32) Region Descriptor Area Start Address Register -------- */
|
||||
#define ICM_DSCR_DASA_Pos _U_(6) /**< (ICM_DSCR) Descriptor Area Start Address Position */
|
||||
#define ICM_DSCR_DASA_Msk (_U_(0x3FFFFFF) << ICM_DSCR_DASA_Pos) /**< (ICM_DSCR) Descriptor Area Start Address Mask */
|
||||
#define ICM_DSCR_DASA(value) (ICM_DSCR_DASA_Msk & ((value) << ICM_DSCR_DASA_Pos))
|
||||
#define ICM_DSCR_Msk _U_(0xFFFFFFC0) /**< (ICM_DSCR) Register Mask */
|
||||
|
||||
|
||||
/* -------- ICM_HASH : (ICM Offset: 0x34) (R/W 32) Region Hash Area Start Address Register -------- */
|
||||
#define ICM_HASH_HASA_Pos _U_(7) /**< (ICM_HASH) Hash Area Start Address Position */
|
||||
#define ICM_HASH_HASA_Msk (_U_(0x1FFFFFF) << ICM_HASH_HASA_Pos) /**< (ICM_HASH) Hash Area Start Address Mask */
|
||||
#define ICM_HASH_HASA(value) (ICM_HASH_HASA_Msk & ((value) << ICM_HASH_HASA_Pos))
|
||||
#define ICM_HASH_Msk _U_(0xFFFFFF80) /**< (ICM_HASH) Register Mask */
|
||||
|
||||
|
||||
/* -------- ICM_UIHVAL : (ICM Offset: 0x38) ( /W 32) User Initial Hash Value 0 Register 0 -------- */
|
||||
#define ICM_UIHVAL_VAL_Pos _U_(0) /**< (ICM_UIHVAL) Initial Hash Value Position */
|
||||
#define ICM_UIHVAL_VAL_Msk (_U_(0xFFFFFFFF) << ICM_UIHVAL_VAL_Pos) /**< (ICM_UIHVAL) Initial Hash Value Mask */
|
||||
#define ICM_UIHVAL_VAL(value) (ICM_UIHVAL_VAL_Msk & ((value) << ICM_UIHVAL_VAL_Pos))
|
||||
#define ICM_UIHVAL_Msk _U_(0xFFFFFFFF) /**< (ICM_UIHVAL) Register Mask */
|
||||
|
||||
|
||||
/** \brief ICM register offsets definitions */
|
||||
#define ICM_CFG_REG_OFST (0x00) /**< (ICM_CFG) Configuration Register Offset */
|
||||
#define ICM_CTRL_REG_OFST (0x04) /**< (ICM_CTRL) Control Register Offset */
|
||||
#define ICM_SR_REG_OFST (0x08) /**< (ICM_SR) Status Register Offset */
|
||||
#define ICM_IER_REG_OFST (0x10) /**< (ICM_IER) Interrupt Enable Register Offset */
|
||||
#define ICM_IDR_REG_OFST (0x14) /**< (ICM_IDR) Interrupt Disable Register Offset */
|
||||
#define ICM_IMR_REG_OFST (0x18) /**< (ICM_IMR) Interrupt Mask Register Offset */
|
||||
#define ICM_ISR_REG_OFST (0x1C) /**< (ICM_ISR) Interrupt Status Register Offset */
|
||||
#define ICM_UASR_REG_OFST (0x20) /**< (ICM_UASR) Undefined Access Status Register Offset */
|
||||
#define ICM_DSCR_REG_OFST (0x30) /**< (ICM_DSCR) Region Descriptor Area Start Address Register Offset */
|
||||
#define ICM_HASH_REG_OFST (0x34) /**< (ICM_HASH) Region Hash Area Start Address Register Offset */
|
||||
#define ICM_UIHVAL_REG_OFST (0x38) /**< (ICM_UIHVAL) User Initial Hash Value 0 Register 0 Offset */
|
||||
|
||||
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
/** \brief ICM register API structure */
|
||||
typedef struct
|
||||
{
|
||||
__IO uint32_t ICM_CFG; /**< Offset: 0x00 (R/W 32) Configuration Register */
|
||||
__O uint32_t ICM_CTRL; /**< Offset: 0x04 ( /W 32) Control Register */
|
||||
__I uint32_t ICM_SR; /**< Offset: 0x08 (R/ 32) Status Register */
|
||||
__I uint8_t Reserved1[0x04];
|
||||
__O uint32_t ICM_IER; /**< Offset: 0x10 ( /W 32) Interrupt Enable Register */
|
||||
__O uint32_t ICM_IDR; /**< Offset: 0x14 ( /W 32) Interrupt Disable Register */
|
||||
__I uint32_t ICM_IMR; /**< Offset: 0x18 (R/ 32) Interrupt Mask Register */
|
||||
__I uint32_t ICM_ISR; /**< Offset: 0x1C (R/ 32) Interrupt Status Register */
|
||||
__I uint32_t ICM_UASR; /**< Offset: 0x20 (R/ 32) Undefined Access Status Register */
|
||||
__I uint8_t Reserved2[0x0C];
|
||||
__IO uint32_t ICM_DSCR; /**< Offset: 0x30 (R/W 32) Region Descriptor Area Start Address Register */
|
||||
__IO uint32_t ICM_HASH; /**< Offset: 0x34 (R/W 32) Region Hash Area Start Address Register */
|
||||
__O uint32_t ICM_UIHVAL[8]; /**< Offset: 0x38 ( /W 32) User Initial Hash Value 0 Register 0 */
|
||||
} icm_registers_t;
|
||||
|
||||
|
||||
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
#endif /* _SAME70_ICM_COMPONENT_H_ */
|
||||
@ -0,0 +1,543 @@
|
||||
/**
|
||||
* \brief Component description for ISI
|
||||
*
|
||||
* Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries.
|
||||
*
|
||||
* Subject to your compliance with these terms, you may use Microchip software and any derivatives
|
||||
* exclusively with Microchip products. It is your responsibility to comply with third party license
|
||||
* terms applicable to your use of third party software (including open source software) that may
|
||||
* accompany Microchip software.
|
||||
*
|
||||
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY,
|
||||
* APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND
|
||||
* FITNESS FOR A PARTICULAR PURPOSE.
|
||||
*
|
||||
* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
|
||||
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF
|
||||
* MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
|
||||
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT
|
||||
* EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
|
||||
*
|
||||
*/
|
||||
|
||||
/* file generated from device description version 2017-08-25T14:00:00Z */
|
||||
#ifndef _SAME70_ISI_COMPONENT_H_
|
||||
#define _SAME70_ISI_COMPONENT_H_
|
||||
|
||||
/* ************************************************************************** */
|
||||
/* SOFTWARE API DEFINITION FOR ISI */
|
||||
/* ************************************************************************** */
|
||||
|
||||
/* -------- ISI_CFG1 : (ISI Offset: 0x00) (R/W 32) ISI Configuration 1 Register -------- */
|
||||
#define ISI_CFG1_HSYNC_POL_Pos _U_(2) /**< (ISI_CFG1) Horizontal Synchronization Polarity Position */
|
||||
#define ISI_CFG1_HSYNC_POL_Msk (_U_(0x1) << ISI_CFG1_HSYNC_POL_Pos) /**< (ISI_CFG1) Horizontal Synchronization Polarity Mask */
|
||||
#define ISI_CFG1_HSYNC_POL(value) (ISI_CFG1_HSYNC_POL_Msk & ((value) << ISI_CFG1_HSYNC_POL_Pos))
|
||||
#define ISI_CFG1_VSYNC_POL_Pos _U_(3) /**< (ISI_CFG1) Vertical Synchronization Polarity Position */
|
||||
#define ISI_CFG1_VSYNC_POL_Msk (_U_(0x1) << ISI_CFG1_VSYNC_POL_Pos) /**< (ISI_CFG1) Vertical Synchronization Polarity Mask */
|
||||
#define ISI_CFG1_VSYNC_POL(value) (ISI_CFG1_VSYNC_POL_Msk & ((value) << ISI_CFG1_VSYNC_POL_Pos))
|
||||
#define ISI_CFG1_PIXCLK_POL_Pos _U_(4) /**< (ISI_CFG1) Pixel Clock Polarity Position */
|
||||
#define ISI_CFG1_PIXCLK_POL_Msk (_U_(0x1) << ISI_CFG1_PIXCLK_POL_Pos) /**< (ISI_CFG1) Pixel Clock Polarity Mask */
|
||||
#define ISI_CFG1_PIXCLK_POL(value) (ISI_CFG1_PIXCLK_POL_Msk & ((value) << ISI_CFG1_PIXCLK_POL_Pos))
|
||||
#define ISI_CFG1_GRAYLE_Pos _U_(5) /**< (ISI_CFG1) Grayscale Little Endian Position */
|
||||
#define ISI_CFG1_GRAYLE_Msk (_U_(0x1) << ISI_CFG1_GRAYLE_Pos) /**< (ISI_CFG1) Grayscale Little Endian Mask */
|
||||
#define ISI_CFG1_GRAYLE(value) (ISI_CFG1_GRAYLE_Msk & ((value) << ISI_CFG1_GRAYLE_Pos))
|
||||
#define ISI_CFG1_EMB_SYNC_Pos _U_(6) /**< (ISI_CFG1) Embedded Synchronization Position */
|
||||
#define ISI_CFG1_EMB_SYNC_Msk (_U_(0x1) << ISI_CFG1_EMB_SYNC_Pos) /**< (ISI_CFG1) Embedded Synchronization Mask */
|
||||
#define ISI_CFG1_EMB_SYNC(value) (ISI_CFG1_EMB_SYNC_Msk & ((value) << ISI_CFG1_EMB_SYNC_Pos))
|
||||
#define ISI_CFG1_CRC_SYNC_Pos _U_(7) /**< (ISI_CFG1) Embedded Synchronization Correction Position */
|
||||
#define ISI_CFG1_CRC_SYNC_Msk (_U_(0x1) << ISI_CFG1_CRC_SYNC_Pos) /**< (ISI_CFG1) Embedded Synchronization Correction Mask */
|
||||
#define ISI_CFG1_CRC_SYNC(value) (ISI_CFG1_CRC_SYNC_Msk & ((value) << ISI_CFG1_CRC_SYNC_Pos))
|
||||
#define ISI_CFG1_FRATE_Pos _U_(8) /**< (ISI_CFG1) Frame Rate [0..7] Position */
|
||||
#define ISI_CFG1_FRATE_Msk (_U_(0x7) << ISI_CFG1_FRATE_Pos) /**< (ISI_CFG1) Frame Rate [0..7] Mask */
|
||||
#define ISI_CFG1_FRATE(value) (ISI_CFG1_FRATE_Msk & ((value) << ISI_CFG1_FRATE_Pos))
|
||||
#define ISI_CFG1_DISCR_Pos _U_(11) /**< (ISI_CFG1) Disable Codec Request Position */
|
||||
#define ISI_CFG1_DISCR_Msk (_U_(0x1) << ISI_CFG1_DISCR_Pos) /**< (ISI_CFG1) Disable Codec Request Mask */
|
||||
#define ISI_CFG1_DISCR(value) (ISI_CFG1_DISCR_Msk & ((value) << ISI_CFG1_DISCR_Pos))
|
||||
#define ISI_CFG1_FULL_Pos _U_(12) /**< (ISI_CFG1) Full Mode is Allowed Position */
|
||||
#define ISI_CFG1_FULL_Msk (_U_(0x1) << ISI_CFG1_FULL_Pos) /**< (ISI_CFG1) Full Mode is Allowed Mask */
|
||||
#define ISI_CFG1_FULL(value) (ISI_CFG1_FULL_Msk & ((value) << ISI_CFG1_FULL_Pos))
|
||||
#define ISI_CFG1_THMASK_Pos _U_(13) /**< (ISI_CFG1) Threshold Mask Position */
|
||||
#define ISI_CFG1_THMASK_Msk (_U_(0x3) << ISI_CFG1_THMASK_Pos) /**< (ISI_CFG1) Threshold Mask Mask */
|
||||
#define ISI_CFG1_THMASK(value) (ISI_CFG1_THMASK_Msk & ((value) << ISI_CFG1_THMASK_Pos))
|
||||
#define ISI_CFG1_THMASK_BEATS_4_Val _U_(0x0) /**< (ISI_CFG1) Only 4 beats AHB burst allowed */
|
||||
#define ISI_CFG1_THMASK_BEATS_8_Val _U_(0x1) /**< (ISI_CFG1) Only 4 and 8 beats AHB burst allowed */
|
||||
#define ISI_CFG1_THMASK_BEATS_16_Val _U_(0x2) /**< (ISI_CFG1) 4, 8 and 16 beats AHB burst allowed */
|
||||
#define ISI_CFG1_THMASK_BEATS_4 (ISI_CFG1_THMASK_BEATS_4_Val << ISI_CFG1_THMASK_Pos) /**< (ISI_CFG1) Only 4 beats AHB burst allowed Position */
|
||||
#define ISI_CFG1_THMASK_BEATS_8 (ISI_CFG1_THMASK_BEATS_8_Val << ISI_CFG1_THMASK_Pos) /**< (ISI_CFG1) Only 4 and 8 beats AHB burst allowed Position */
|
||||
#define ISI_CFG1_THMASK_BEATS_16 (ISI_CFG1_THMASK_BEATS_16_Val << ISI_CFG1_THMASK_Pos) /**< (ISI_CFG1) 4, 8 and 16 beats AHB burst allowed Position */
|
||||
#define ISI_CFG1_SLD_Pos _U_(16) /**< (ISI_CFG1) Start of Line Delay Position */
|
||||
#define ISI_CFG1_SLD_Msk (_U_(0xFF) << ISI_CFG1_SLD_Pos) /**< (ISI_CFG1) Start of Line Delay Mask */
|
||||
#define ISI_CFG1_SLD(value) (ISI_CFG1_SLD_Msk & ((value) << ISI_CFG1_SLD_Pos))
|
||||
#define ISI_CFG1_SFD_Pos _U_(24) /**< (ISI_CFG1) Start of Frame Delay Position */
|
||||
#define ISI_CFG1_SFD_Msk (_U_(0xFF) << ISI_CFG1_SFD_Pos) /**< (ISI_CFG1) Start of Frame Delay Mask */
|
||||
#define ISI_CFG1_SFD(value) (ISI_CFG1_SFD_Msk & ((value) << ISI_CFG1_SFD_Pos))
|
||||
#define ISI_CFG1_Msk _U_(0xFFFF7FFC) /**< (ISI_CFG1) Register Mask */
|
||||
|
||||
|
||||
/* -------- ISI_CFG2 : (ISI Offset: 0x04) (R/W 32) ISI Configuration 2 Register -------- */
|
||||
#define ISI_CFG2_IM_VSIZE_Pos _U_(0) /**< (ISI_CFG2) Vertical Size of the Image Sensor [0..2047] Position */
|
||||
#define ISI_CFG2_IM_VSIZE_Msk (_U_(0x7FF) << ISI_CFG2_IM_VSIZE_Pos) /**< (ISI_CFG2) Vertical Size of the Image Sensor [0..2047] Mask */
|
||||
#define ISI_CFG2_IM_VSIZE(value) (ISI_CFG2_IM_VSIZE_Msk & ((value) << ISI_CFG2_IM_VSIZE_Pos))
|
||||
#define ISI_CFG2_GS_MODE_Pos _U_(11) /**< (ISI_CFG2) Grayscale Pixel Format Mode Position */
|
||||
#define ISI_CFG2_GS_MODE_Msk (_U_(0x1) << ISI_CFG2_GS_MODE_Pos) /**< (ISI_CFG2) Grayscale Pixel Format Mode Mask */
|
||||
#define ISI_CFG2_GS_MODE(value) (ISI_CFG2_GS_MODE_Msk & ((value) << ISI_CFG2_GS_MODE_Pos))
|
||||
#define ISI_CFG2_RGB_MODE_Pos _U_(12) /**< (ISI_CFG2) RGB Input Mode Position */
|
||||
#define ISI_CFG2_RGB_MODE_Msk (_U_(0x1) << ISI_CFG2_RGB_MODE_Pos) /**< (ISI_CFG2) RGB Input Mode Mask */
|
||||
#define ISI_CFG2_RGB_MODE(value) (ISI_CFG2_RGB_MODE_Msk & ((value) << ISI_CFG2_RGB_MODE_Pos))
|
||||
#define ISI_CFG2_GRAYSCALE_Pos _U_(13) /**< (ISI_CFG2) Grayscale Mode Format Enable Position */
|
||||
#define ISI_CFG2_GRAYSCALE_Msk (_U_(0x1) << ISI_CFG2_GRAYSCALE_Pos) /**< (ISI_CFG2) Grayscale Mode Format Enable Mask */
|
||||
#define ISI_CFG2_GRAYSCALE(value) (ISI_CFG2_GRAYSCALE_Msk & ((value) << ISI_CFG2_GRAYSCALE_Pos))
|
||||
#define ISI_CFG2_RGB_SWAP_Pos _U_(14) /**< (ISI_CFG2) RGB Format Swap Mode Position */
|
||||
#define ISI_CFG2_RGB_SWAP_Msk (_U_(0x1) << ISI_CFG2_RGB_SWAP_Pos) /**< (ISI_CFG2) RGB Format Swap Mode Mask */
|
||||
#define ISI_CFG2_RGB_SWAP(value) (ISI_CFG2_RGB_SWAP_Msk & ((value) << ISI_CFG2_RGB_SWAP_Pos))
|
||||
#define ISI_CFG2_COL_SPACE_Pos _U_(15) /**< (ISI_CFG2) Color Space for the Image Data Position */
|
||||
#define ISI_CFG2_COL_SPACE_Msk (_U_(0x1) << ISI_CFG2_COL_SPACE_Pos) /**< (ISI_CFG2) Color Space for the Image Data Mask */
|
||||
#define ISI_CFG2_COL_SPACE(value) (ISI_CFG2_COL_SPACE_Msk & ((value) << ISI_CFG2_COL_SPACE_Pos))
|
||||
#define ISI_CFG2_IM_HSIZE_Pos _U_(16) /**< (ISI_CFG2) Horizontal Size of the Image Sensor [0..2047] Position */
|
||||
#define ISI_CFG2_IM_HSIZE_Msk (_U_(0x7FF) << ISI_CFG2_IM_HSIZE_Pos) /**< (ISI_CFG2) Horizontal Size of the Image Sensor [0..2047] Mask */
|
||||
#define ISI_CFG2_IM_HSIZE(value) (ISI_CFG2_IM_HSIZE_Msk & ((value) << ISI_CFG2_IM_HSIZE_Pos))
|
||||
#define ISI_CFG2_YCC_SWAP_Pos _U_(28) /**< (ISI_CFG2) YCrCb Format Swap Mode Position */
|
||||
#define ISI_CFG2_YCC_SWAP_Msk (_U_(0x3) << ISI_CFG2_YCC_SWAP_Pos) /**< (ISI_CFG2) YCrCb Format Swap Mode Mask */
|
||||
#define ISI_CFG2_YCC_SWAP(value) (ISI_CFG2_YCC_SWAP_Msk & ((value) << ISI_CFG2_YCC_SWAP_Pos))
|
||||
#define ISI_CFG2_YCC_SWAP_DEFAULT_Val _U_(0x0) /**< (ISI_CFG2) Byte 0 Cb(i)Byte 1 Y(i)Byte 2 Cr(i)Byte 3 Y(i+1) */
|
||||
#define ISI_CFG2_YCC_SWAP_MODE1_Val _U_(0x1) /**< (ISI_CFG2) Byte 0 Cr(i)Byte 1 Y(i)Byte 2 Cb(i)Byte 3 Y(i+1) */
|
||||
#define ISI_CFG2_YCC_SWAP_MODE2_Val _U_(0x2) /**< (ISI_CFG2) Byte 0 Y(i)Byte 1 Cb(i)Byte 2 Y(i+1)Byte 3 Cr(i) */
|
||||
#define ISI_CFG2_YCC_SWAP_MODE3_Val _U_(0x3) /**< (ISI_CFG2) Byte 0 Y(i)Byte 1 Cr(i)Byte 2 Y(i+1)Byte 3 Cb(i) */
|
||||
#define ISI_CFG2_YCC_SWAP_DEFAULT (ISI_CFG2_YCC_SWAP_DEFAULT_Val << ISI_CFG2_YCC_SWAP_Pos) /**< (ISI_CFG2) Byte 0 Cb(i)Byte 1 Y(i)Byte 2 Cr(i)Byte 3 Y(i+1) Position */
|
||||
#define ISI_CFG2_YCC_SWAP_MODE1 (ISI_CFG2_YCC_SWAP_MODE1_Val << ISI_CFG2_YCC_SWAP_Pos) /**< (ISI_CFG2) Byte 0 Cr(i)Byte 1 Y(i)Byte 2 Cb(i)Byte 3 Y(i+1) Position */
|
||||
#define ISI_CFG2_YCC_SWAP_MODE2 (ISI_CFG2_YCC_SWAP_MODE2_Val << ISI_CFG2_YCC_SWAP_Pos) /**< (ISI_CFG2) Byte 0 Y(i)Byte 1 Cb(i)Byte 2 Y(i+1)Byte 3 Cr(i) Position */
|
||||
#define ISI_CFG2_YCC_SWAP_MODE3 (ISI_CFG2_YCC_SWAP_MODE3_Val << ISI_CFG2_YCC_SWAP_Pos) /**< (ISI_CFG2) Byte 0 Y(i)Byte 1 Cr(i)Byte 2 Y(i+1)Byte 3 Cb(i) Position */
|
||||
#define ISI_CFG2_RGB_CFG_Pos _U_(30) /**< (ISI_CFG2) RGB Pixel Mapping Configuration Position */
|
||||
#define ISI_CFG2_RGB_CFG_Msk (_U_(0x3) << ISI_CFG2_RGB_CFG_Pos) /**< (ISI_CFG2) RGB Pixel Mapping Configuration Mask */
|
||||
#define ISI_CFG2_RGB_CFG(value) (ISI_CFG2_RGB_CFG_Msk & ((value) << ISI_CFG2_RGB_CFG_Pos))
|
||||
#define ISI_CFG2_RGB_CFG_DEFAULT_Val _U_(0x0) /**< (ISI_CFG2) Byte 0 R/G(MSB)Byte 1 G(LSB)/BByte 2 R/G(MSB)Byte 3 G(LSB)/B */
|
||||
#define ISI_CFG2_RGB_CFG_MODE1_Val _U_(0x1) /**< (ISI_CFG2) Byte 0 B/G(MSB)Byte 1 G(LSB)/RByte 2 B/G(MSB)Byte 3 G(LSB)/R */
|
||||
#define ISI_CFG2_RGB_CFG_MODE2_Val _U_(0x2) /**< (ISI_CFG2) Byte 0 G(LSB)/RByte 1 B/G(MSB)Byte 2 G(LSB)/RByte 3 B/G(MSB) */
|
||||
#define ISI_CFG2_RGB_CFG_MODE3_Val _U_(0x3) /**< (ISI_CFG2) Byte 0 G(LSB)/BByte 1 R/G(MSB)Byte 2 G(LSB)/BByte 3 R/G(MSB) */
|
||||
#define ISI_CFG2_RGB_CFG_DEFAULT (ISI_CFG2_RGB_CFG_DEFAULT_Val << ISI_CFG2_RGB_CFG_Pos) /**< (ISI_CFG2) Byte 0 R/G(MSB)Byte 1 G(LSB)/BByte 2 R/G(MSB)Byte 3 G(LSB)/B Position */
|
||||
#define ISI_CFG2_RGB_CFG_MODE1 (ISI_CFG2_RGB_CFG_MODE1_Val << ISI_CFG2_RGB_CFG_Pos) /**< (ISI_CFG2) Byte 0 B/G(MSB)Byte 1 G(LSB)/RByte 2 B/G(MSB)Byte 3 G(LSB)/R Position */
|
||||
#define ISI_CFG2_RGB_CFG_MODE2 (ISI_CFG2_RGB_CFG_MODE2_Val << ISI_CFG2_RGB_CFG_Pos) /**< (ISI_CFG2) Byte 0 G(LSB)/RByte 1 B/G(MSB)Byte 2 G(LSB)/RByte 3 B/G(MSB) Position */
|
||||
#define ISI_CFG2_RGB_CFG_MODE3 (ISI_CFG2_RGB_CFG_MODE3_Val << ISI_CFG2_RGB_CFG_Pos) /**< (ISI_CFG2) Byte 0 G(LSB)/BByte 1 R/G(MSB)Byte 2 G(LSB)/BByte 3 R/G(MSB) Position */
|
||||
#define ISI_CFG2_Msk _U_(0xF7FFFFFF) /**< (ISI_CFG2) Register Mask */
|
||||
|
||||
|
||||
/* -------- ISI_PSIZE : (ISI Offset: 0x08) (R/W 32) ISI Preview Size Register -------- */
|
||||
#define ISI_PSIZE_PREV_VSIZE_Pos _U_(0) /**< (ISI_PSIZE) Vertical Size for the Preview Path Position */
|
||||
#define ISI_PSIZE_PREV_VSIZE_Msk (_U_(0x3FF) << ISI_PSIZE_PREV_VSIZE_Pos) /**< (ISI_PSIZE) Vertical Size for the Preview Path Mask */
|
||||
#define ISI_PSIZE_PREV_VSIZE(value) (ISI_PSIZE_PREV_VSIZE_Msk & ((value) << ISI_PSIZE_PREV_VSIZE_Pos))
|
||||
#define ISI_PSIZE_PREV_HSIZE_Pos _U_(16) /**< (ISI_PSIZE) Horizontal Size for the Preview Path Position */
|
||||
#define ISI_PSIZE_PREV_HSIZE_Msk (_U_(0x3FF) << ISI_PSIZE_PREV_HSIZE_Pos) /**< (ISI_PSIZE) Horizontal Size for the Preview Path Mask */
|
||||
#define ISI_PSIZE_PREV_HSIZE(value) (ISI_PSIZE_PREV_HSIZE_Msk & ((value) << ISI_PSIZE_PREV_HSIZE_Pos))
|
||||
#define ISI_PSIZE_Msk _U_(0x03FF03FF) /**< (ISI_PSIZE) Register Mask */
|
||||
|
||||
|
||||
/* -------- ISI_PDECF : (ISI Offset: 0x0C) (R/W 32) ISI Preview Decimation Factor Register -------- */
|
||||
#define ISI_PDECF_DEC_FACTOR_Pos _U_(0) /**< (ISI_PDECF) Decimation Factor Position */
|
||||
#define ISI_PDECF_DEC_FACTOR_Msk (_U_(0xFF) << ISI_PDECF_DEC_FACTOR_Pos) /**< (ISI_PDECF) Decimation Factor Mask */
|
||||
#define ISI_PDECF_DEC_FACTOR(value) (ISI_PDECF_DEC_FACTOR_Msk & ((value) << ISI_PDECF_DEC_FACTOR_Pos))
|
||||
#define ISI_PDECF_Msk _U_(0x000000FF) /**< (ISI_PDECF) Register Mask */
|
||||
|
||||
|
||||
/* -------- ISI_Y2R_SET0 : (ISI Offset: 0x10) (R/W 32) ISI Color Space Conversion YCrCb To RGB Set 0 Register -------- */
|
||||
#define ISI_Y2R_SET0_C0_Pos _U_(0) /**< (ISI_Y2R_SET0) Color Space Conversion Matrix Coefficient C0 Position */
|
||||
#define ISI_Y2R_SET0_C0_Msk (_U_(0xFF) << ISI_Y2R_SET0_C0_Pos) /**< (ISI_Y2R_SET0) Color Space Conversion Matrix Coefficient C0 Mask */
|
||||
#define ISI_Y2R_SET0_C0(value) (ISI_Y2R_SET0_C0_Msk & ((value) << ISI_Y2R_SET0_C0_Pos))
|
||||
#define ISI_Y2R_SET0_C1_Pos _U_(8) /**< (ISI_Y2R_SET0) Color Space Conversion Matrix Coefficient C1 Position */
|
||||
#define ISI_Y2R_SET0_C1_Msk (_U_(0xFF) << ISI_Y2R_SET0_C1_Pos) /**< (ISI_Y2R_SET0) Color Space Conversion Matrix Coefficient C1 Mask */
|
||||
#define ISI_Y2R_SET0_C1(value) (ISI_Y2R_SET0_C1_Msk & ((value) << ISI_Y2R_SET0_C1_Pos))
|
||||
#define ISI_Y2R_SET0_C2_Pos _U_(16) /**< (ISI_Y2R_SET0) Color Space Conversion Matrix Coefficient C2 Position */
|
||||
#define ISI_Y2R_SET0_C2_Msk (_U_(0xFF) << ISI_Y2R_SET0_C2_Pos) /**< (ISI_Y2R_SET0) Color Space Conversion Matrix Coefficient C2 Mask */
|
||||
#define ISI_Y2R_SET0_C2(value) (ISI_Y2R_SET0_C2_Msk & ((value) << ISI_Y2R_SET0_C2_Pos))
|
||||
#define ISI_Y2R_SET0_C3_Pos _U_(24) /**< (ISI_Y2R_SET0) Color Space Conversion Matrix Coefficient C3 Position */
|
||||
#define ISI_Y2R_SET0_C3_Msk (_U_(0xFF) << ISI_Y2R_SET0_C3_Pos) /**< (ISI_Y2R_SET0) Color Space Conversion Matrix Coefficient C3 Mask */
|
||||
#define ISI_Y2R_SET0_C3(value) (ISI_Y2R_SET0_C3_Msk & ((value) << ISI_Y2R_SET0_C3_Pos))
|
||||
#define ISI_Y2R_SET0_Msk _U_(0xFFFFFFFF) /**< (ISI_Y2R_SET0) Register Mask */
|
||||
|
||||
|
||||
/* -------- ISI_Y2R_SET1 : (ISI Offset: 0x14) (R/W 32) ISI Color Space Conversion YCrCb To RGB Set 1 Register -------- */
|
||||
#define ISI_Y2R_SET1_C4_Pos _U_(0) /**< (ISI_Y2R_SET1) Color Space Conversion Matrix Coefficient C4 Position */
|
||||
#define ISI_Y2R_SET1_C4_Msk (_U_(0x1FF) << ISI_Y2R_SET1_C4_Pos) /**< (ISI_Y2R_SET1) Color Space Conversion Matrix Coefficient C4 Mask */
|
||||
#define ISI_Y2R_SET1_C4(value) (ISI_Y2R_SET1_C4_Msk & ((value) << ISI_Y2R_SET1_C4_Pos))
|
||||
#define ISI_Y2R_SET1_Yoff_Pos _U_(12) /**< (ISI_Y2R_SET1) Color Space Conversion Luminance Default Offset Position */
|
||||
#define ISI_Y2R_SET1_Yoff_Msk (_U_(0x1) << ISI_Y2R_SET1_Yoff_Pos) /**< (ISI_Y2R_SET1) Color Space Conversion Luminance Default Offset Mask */
|
||||
#define ISI_Y2R_SET1_Yoff(value) (ISI_Y2R_SET1_Yoff_Msk & ((value) << ISI_Y2R_SET1_Yoff_Pos))
|
||||
#define ISI_Y2R_SET1_Croff_Pos _U_(13) /**< (ISI_Y2R_SET1) Color Space Conversion Red Chrominance Default Offset Position */
|
||||
#define ISI_Y2R_SET1_Croff_Msk (_U_(0x1) << ISI_Y2R_SET1_Croff_Pos) /**< (ISI_Y2R_SET1) Color Space Conversion Red Chrominance Default Offset Mask */
|
||||
#define ISI_Y2R_SET1_Croff(value) (ISI_Y2R_SET1_Croff_Msk & ((value) << ISI_Y2R_SET1_Croff_Pos))
|
||||
#define ISI_Y2R_SET1_Cboff_Pos _U_(14) /**< (ISI_Y2R_SET1) Color Space Conversion Blue Chrominance Default Offset Position */
|
||||
#define ISI_Y2R_SET1_Cboff_Msk (_U_(0x1) << ISI_Y2R_SET1_Cboff_Pos) /**< (ISI_Y2R_SET1) Color Space Conversion Blue Chrominance Default Offset Mask */
|
||||
#define ISI_Y2R_SET1_Cboff(value) (ISI_Y2R_SET1_Cboff_Msk & ((value) << ISI_Y2R_SET1_Cboff_Pos))
|
||||
#define ISI_Y2R_SET1_Msk _U_(0x000071FF) /**< (ISI_Y2R_SET1) Register Mask */
|
||||
|
||||
|
||||
/* -------- ISI_R2Y_SET0 : (ISI Offset: 0x18) (R/W 32) ISI Color Space Conversion RGB To YCrCb Set 0 Register -------- */
|
||||
#define ISI_R2Y_SET0_C0_Pos _U_(0) /**< (ISI_R2Y_SET0) Color Space Conversion Matrix Coefficient C0 Position */
|
||||
#define ISI_R2Y_SET0_C0_Msk (_U_(0x7F) << ISI_R2Y_SET0_C0_Pos) /**< (ISI_R2Y_SET0) Color Space Conversion Matrix Coefficient C0 Mask */
|
||||
#define ISI_R2Y_SET0_C0(value) (ISI_R2Y_SET0_C0_Msk & ((value) << ISI_R2Y_SET0_C0_Pos))
|
||||
#define ISI_R2Y_SET0_C1_Pos _U_(8) /**< (ISI_R2Y_SET0) Color Space Conversion Matrix Coefficient C1 Position */
|
||||
#define ISI_R2Y_SET0_C1_Msk (_U_(0x7F) << ISI_R2Y_SET0_C1_Pos) /**< (ISI_R2Y_SET0) Color Space Conversion Matrix Coefficient C1 Mask */
|
||||
#define ISI_R2Y_SET0_C1(value) (ISI_R2Y_SET0_C1_Msk & ((value) << ISI_R2Y_SET0_C1_Pos))
|
||||
#define ISI_R2Y_SET0_C2_Pos _U_(16) /**< (ISI_R2Y_SET0) Color Space Conversion Matrix Coefficient C2 Position */
|
||||
#define ISI_R2Y_SET0_C2_Msk (_U_(0x7F) << ISI_R2Y_SET0_C2_Pos) /**< (ISI_R2Y_SET0) Color Space Conversion Matrix Coefficient C2 Mask */
|
||||
#define ISI_R2Y_SET0_C2(value) (ISI_R2Y_SET0_C2_Msk & ((value) << ISI_R2Y_SET0_C2_Pos))
|
||||
#define ISI_R2Y_SET0_Roff_Pos _U_(24) /**< (ISI_R2Y_SET0) Color Space Conversion Red Component Offset Position */
|
||||
#define ISI_R2Y_SET0_Roff_Msk (_U_(0x1) << ISI_R2Y_SET0_Roff_Pos) /**< (ISI_R2Y_SET0) Color Space Conversion Red Component Offset Mask */
|
||||
#define ISI_R2Y_SET0_Roff(value) (ISI_R2Y_SET0_Roff_Msk & ((value) << ISI_R2Y_SET0_Roff_Pos))
|
||||
#define ISI_R2Y_SET0_Msk _U_(0x017F7F7F) /**< (ISI_R2Y_SET0) Register Mask */
|
||||
|
||||
|
||||
/* -------- ISI_R2Y_SET1 : (ISI Offset: 0x1C) (R/W 32) ISI Color Space Conversion RGB To YCrCb Set 1 Register -------- */
|
||||
#define ISI_R2Y_SET1_C3_Pos _U_(0) /**< (ISI_R2Y_SET1) Color Space Conversion Matrix Coefficient C3 Position */
|
||||
#define ISI_R2Y_SET1_C3_Msk (_U_(0x7F) << ISI_R2Y_SET1_C3_Pos) /**< (ISI_R2Y_SET1) Color Space Conversion Matrix Coefficient C3 Mask */
|
||||
#define ISI_R2Y_SET1_C3(value) (ISI_R2Y_SET1_C3_Msk & ((value) << ISI_R2Y_SET1_C3_Pos))
|
||||
#define ISI_R2Y_SET1_C4_Pos _U_(8) /**< (ISI_R2Y_SET1) Color Space Conversion Matrix Coefficient C4 Position */
|
||||
#define ISI_R2Y_SET1_C4_Msk (_U_(0x7F) << ISI_R2Y_SET1_C4_Pos) /**< (ISI_R2Y_SET1) Color Space Conversion Matrix Coefficient C4 Mask */
|
||||
#define ISI_R2Y_SET1_C4(value) (ISI_R2Y_SET1_C4_Msk & ((value) << ISI_R2Y_SET1_C4_Pos))
|
||||
#define ISI_R2Y_SET1_C5_Pos _U_(16) /**< (ISI_R2Y_SET1) Color Space Conversion Matrix Coefficient C5 Position */
|
||||
#define ISI_R2Y_SET1_C5_Msk (_U_(0x7F) << ISI_R2Y_SET1_C5_Pos) /**< (ISI_R2Y_SET1) Color Space Conversion Matrix Coefficient C5 Mask */
|
||||
#define ISI_R2Y_SET1_C5(value) (ISI_R2Y_SET1_C5_Msk & ((value) << ISI_R2Y_SET1_C5_Pos))
|
||||
#define ISI_R2Y_SET1_Goff_Pos _U_(24) /**< (ISI_R2Y_SET1) Color Space Conversion Green Component Offset Position */
|
||||
#define ISI_R2Y_SET1_Goff_Msk (_U_(0x1) << ISI_R2Y_SET1_Goff_Pos) /**< (ISI_R2Y_SET1) Color Space Conversion Green Component Offset Mask */
|
||||
#define ISI_R2Y_SET1_Goff(value) (ISI_R2Y_SET1_Goff_Msk & ((value) << ISI_R2Y_SET1_Goff_Pos))
|
||||
#define ISI_R2Y_SET1_Msk _U_(0x017F7F7F) /**< (ISI_R2Y_SET1) Register Mask */
|
||||
|
||||
|
||||
/* -------- ISI_R2Y_SET2 : (ISI Offset: 0x20) (R/W 32) ISI Color Space Conversion RGB To YCrCb Set 2 Register -------- */
|
||||
#define ISI_R2Y_SET2_C6_Pos _U_(0) /**< (ISI_R2Y_SET2) Color Space Conversion Matrix Coefficient C6 Position */
|
||||
#define ISI_R2Y_SET2_C6_Msk (_U_(0x7F) << ISI_R2Y_SET2_C6_Pos) /**< (ISI_R2Y_SET2) Color Space Conversion Matrix Coefficient C6 Mask */
|
||||
#define ISI_R2Y_SET2_C6(value) (ISI_R2Y_SET2_C6_Msk & ((value) << ISI_R2Y_SET2_C6_Pos))
|
||||
#define ISI_R2Y_SET2_C7_Pos _U_(8) /**< (ISI_R2Y_SET2) Color Space Conversion Matrix Coefficient C7 Position */
|
||||
#define ISI_R2Y_SET2_C7_Msk (_U_(0x7F) << ISI_R2Y_SET2_C7_Pos) /**< (ISI_R2Y_SET2) Color Space Conversion Matrix Coefficient C7 Mask */
|
||||
#define ISI_R2Y_SET2_C7(value) (ISI_R2Y_SET2_C7_Msk & ((value) << ISI_R2Y_SET2_C7_Pos))
|
||||
#define ISI_R2Y_SET2_C8_Pos _U_(16) /**< (ISI_R2Y_SET2) Color Space Conversion Matrix Coefficient C8 Position */
|
||||
#define ISI_R2Y_SET2_C8_Msk (_U_(0x7F) << ISI_R2Y_SET2_C8_Pos) /**< (ISI_R2Y_SET2) Color Space Conversion Matrix Coefficient C8 Mask */
|
||||
#define ISI_R2Y_SET2_C8(value) (ISI_R2Y_SET2_C8_Msk & ((value) << ISI_R2Y_SET2_C8_Pos))
|
||||
#define ISI_R2Y_SET2_Boff_Pos _U_(24) /**< (ISI_R2Y_SET2) Color Space Conversion Blue Component Offset Position */
|
||||
#define ISI_R2Y_SET2_Boff_Msk (_U_(0x1) << ISI_R2Y_SET2_Boff_Pos) /**< (ISI_R2Y_SET2) Color Space Conversion Blue Component Offset Mask */
|
||||
#define ISI_R2Y_SET2_Boff(value) (ISI_R2Y_SET2_Boff_Msk & ((value) << ISI_R2Y_SET2_Boff_Pos))
|
||||
#define ISI_R2Y_SET2_Msk _U_(0x017F7F7F) /**< (ISI_R2Y_SET2) Register Mask */
|
||||
|
||||
|
||||
/* -------- ISI_CR : (ISI Offset: 0x24) ( /W 32) ISI Control Register -------- */
|
||||
#define ISI_CR_ISI_EN_Pos _U_(0) /**< (ISI_CR) ISI Module Enable Request Position */
|
||||
#define ISI_CR_ISI_EN_Msk (_U_(0x1) << ISI_CR_ISI_EN_Pos) /**< (ISI_CR) ISI Module Enable Request Mask */
|
||||
#define ISI_CR_ISI_EN(value) (ISI_CR_ISI_EN_Msk & ((value) << ISI_CR_ISI_EN_Pos))
|
||||
#define ISI_CR_ISI_DIS_Pos _U_(1) /**< (ISI_CR) ISI Module Disable Request Position */
|
||||
#define ISI_CR_ISI_DIS_Msk (_U_(0x1) << ISI_CR_ISI_DIS_Pos) /**< (ISI_CR) ISI Module Disable Request Mask */
|
||||
#define ISI_CR_ISI_DIS(value) (ISI_CR_ISI_DIS_Msk & ((value) << ISI_CR_ISI_DIS_Pos))
|
||||
#define ISI_CR_ISI_SRST_Pos _U_(2) /**< (ISI_CR) ISI Software Reset Request Position */
|
||||
#define ISI_CR_ISI_SRST_Msk (_U_(0x1) << ISI_CR_ISI_SRST_Pos) /**< (ISI_CR) ISI Software Reset Request Mask */
|
||||
#define ISI_CR_ISI_SRST(value) (ISI_CR_ISI_SRST_Msk & ((value) << ISI_CR_ISI_SRST_Pos))
|
||||
#define ISI_CR_ISI_CDC_Pos _U_(8) /**< (ISI_CR) ISI Codec Request Position */
|
||||
#define ISI_CR_ISI_CDC_Msk (_U_(0x1) << ISI_CR_ISI_CDC_Pos) /**< (ISI_CR) ISI Codec Request Mask */
|
||||
#define ISI_CR_ISI_CDC(value) (ISI_CR_ISI_CDC_Msk & ((value) << ISI_CR_ISI_CDC_Pos))
|
||||
#define ISI_CR_Msk _U_(0x00000107) /**< (ISI_CR) Register Mask */
|
||||
|
||||
|
||||
/* -------- ISI_SR : (ISI Offset: 0x28) ( R/ 32) ISI Status Register -------- */
|
||||
#define ISI_SR_ENABLE_Pos _U_(0) /**< (ISI_SR) Module Enable Position */
|
||||
#define ISI_SR_ENABLE_Msk (_U_(0x1) << ISI_SR_ENABLE_Pos) /**< (ISI_SR) Module Enable Mask */
|
||||
#define ISI_SR_ENABLE(value) (ISI_SR_ENABLE_Msk & ((value) << ISI_SR_ENABLE_Pos))
|
||||
#define ISI_SR_DIS_DONE_Pos _U_(1) /**< (ISI_SR) Module Disable Request has Terminated (cleared on read) Position */
|
||||
#define ISI_SR_DIS_DONE_Msk (_U_(0x1) << ISI_SR_DIS_DONE_Pos) /**< (ISI_SR) Module Disable Request has Terminated (cleared on read) Mask */
|
||||
#define ISI_SR_DIS_DONE(value) (ISI_SR_DIS_DONE_Msk & ((value) << ISI_SR_DIS_DONE_Pos))
|
||||
#define ISI_SR_SRST_Pos _U_(2) /**< (ISI_SR) Module Software Reset Request has Terminated (cleared on read) Position */
|
||||
#define ISI_SR_SRST_Msk (_U_(0x1) << ISI_SR_SRST_Pos) /**< (ISI_SR) Module Software Reset Request has Terminated (cleared on read) Mask */
|
||||
#define ISI_SR_SRST(value) (ISI_SR_SRST_Msk & ((value) << ISI_SR_SRST_Pos))
|
||||
#define ISI_SR_CDC_PND_Pos _U_(8) /**< (ISI_SR) Pending Codec Request Position */
|
||||
#define ISI_SR_CDC_PND_Msk (_U_(0x1) << ISI_SR_CDC_PND_Pos) /**< (ISI_SR) Pending Codec Request Mask */
|
||||
#define ISI_SR_CDC_PND(value) (ISI_SR_CDC_PND_Msk & ((value) << ISI_SR_CDC_PND_Pos))
|
||||
#define ISI_SR_VSYNC_Pos _U_(10) /**< (ISI_SR) Vertical Synchronization (cleared on read) Position */
|
||||
#define ISI_SR_VSYNC_Msk (_U_(0x1) << ISI_SR_VSYNC_Pos) /**< (ISI_SR) Vertical Synchronization (cleared on read) Mask */
|
||||
#define ISI_SR_VSYNC(value) (ISI_SR_VSYNC_Msk & ((value) << ISI_SR_VSYNC_Pos))
|
||||
#define ISI_SR_PXFR_DONE_Pos _U_(16) /**< (ISI_SR) Preview DMA Transfer has Terminated (cleared on read) Position */
|
||||
#define ISI_SR_PXFR_DONE_Msk (_U_(0x1) << ISI_SR_PXFR_DONE_Pos) /**< (ISI_SR) Preview DMA Transfer has Terminated (cleared on read) Mask */
|
||||
#define ISI_SR_PXFR_DONE(value) (ISI_SR_PXFR_DONE_Msk & ((value) << ISI_SR_PXFR_DONE_Pos))
|
||||
#define ISI_SR_CXFR_DONE_Pos _U_(17) /**< (ISI_SR) Codec DMA Transfer has Terminated (cleared on read) Position */
|
||||
#define ISI_SR_CXFR_DONE_Msk (_U_(0x1) << ISI_SR_CXFR_DONE_Pos) /**< (ISI_SR) Codec DMA Transfer has Terminated (cleared on read) Mask */
|
||||
#define ISI_SR_CXFR_DONE(value) (ISI_SR_CXFR_DONE_Msk & ((value) << ISI_SR_CXFR_DONE_Pos))
|
||||
#define ISI_SR_SIP_Pos _U_(19) /**< (ISI_SR) Synchronization in Progress Position */
|
||||
#define ISI_SR_SIP_Msk (_U_(0x1) << ISI_SR_SIP_Pos) /**< (ISI_SR) Synchronization in Progress Mask */
|
||||
#define ISI_SR_SIP(value) (ISI_SR_SIP_Msk & ((value) << ISI_SR_SIP_Pos))
|
||||
#define ISI_SR_P_OVR_Pos _U_(24) /**< (ISI_SR) Preview Datapath Overflow (cleared on read) Position */
|
||||
#define ISI_SR_P_OVR_Msk (_U_(0x1) << ISI_SR_P_OVR_Pos) /**< (ISI_SR) Preview Datapath Overflow (cleared on read) Mask */
|
||||
#define ISI_SR_P_OVR(value) (ISI_SR_P_OVR_Msk & ((value) << ISI_SR_P_OVR_Pos))
|
||||
#define ISI_SR_C_OVR_Pos _U_(25) /**< (ISI_SR) Codec Datapath Overflow (cleared on read) Position */
|
||||
#define ISI_SR_C_OVR_Msk (_U_(0x1) << ISI_SR_C_OVR_Pos) /**< (ISI_SR) Codec Datapath Overflow (cleared on read) Mask */
|
||||
#define ISI_SR_C_OVR(value) (ISI_SR_C_OVR_Msk & ((value) << ISI_SR_C_OVR_Pos))
|
||||
#define ISI_SR_CRC_ERR_Pos _U_(26) /**< (ISI_SR) CRC Synchronization Error (cleared on read) Position */
|
||||
#define ISI_SR_CRC_ERR_Msk (_U_(0x1) << ISI_SR_CRC_ERR_Pos) /**< (ISI_SR) CRC Synchronization Error (cleared on read) Mask */
|
||||
#define ISI_SR_CRC_ERR(value) (ISI_SR_CRC_ERR_Msk & ((value) << ISI_SR_CRC_ERR_Pos))
|
||||
#define ISI_SR_FR_OVR_Pos _U_(27) /**< (ISI_SR) Frame Rate Overrun (cleared on read) Position */
|
||||
#define ISI_SR_FR_OVR_Msk (_U_(0x1) << ISI_SR_FR_OVR_Pos) /**< (ISI_SR) Frame Rate Overrun (cleared on read) Mask */
|
||||
#define ISI_SR_FR_OVR(value) (ISI_SR_FR_OVR_Msk & ((value) << ISI_SR_FR_OVR_Pos))
|
||||
#define ISI_SR_Msk _U_(0x0F0B0507) /**< (ISI_SR) Register Mask */
|
||||
|
||||
|
||||
/* -------- ISI_IER : (ISI Offset: 0x2C) ( /W 32) ISI Interrupt Enable Register -------- */
|
||||
#define ISI_IER_DIS_DONE_Pos _U_(1) /**< (ISI_IER) Disable Done Interrupt Enable Position */
|
||||
#define ISI_IER_DIS_DONE_Msk (_U_(0x1) << ISI_IER_DIS_DONE_Pos) /**< (ISI_IER) Disable Done Interrupt Enable Mask */
|
||||
#define ISI_IER_DIS_DONE(value) (ISI_IER_DIS_DONE_Msk & ((value) << ISI_IER_DIS_DONE_Pos))
|
||||
#define ISI_IER_SRST_Pos _U_(2) /**< (ISI_IER) Software Reset Interrupt Enable Position */
|
||||
#define ISI_IER_SRST_Msk (_U_(0x1) << ISI_IER_SRST_Pos) /**< (ISI_IER) Software Reset Interrupt Enable Mask */
|
||||
#define ISI_IER_SRST(value) (ISI_IER_SRST_Msk & ((value) << ISI_IER_SRST_Pos))
|
||||
#define ISI_IER_VSYNC_Pos _U_(10) /**< (ISI_IER) Vertical Synchronization Interrupt Enable Position */
|
||||
#define ISI_IER_VSYNC_Msk (_U_(0x1) << ISI_IER_VSYNC_Pos) /**< (ISI_IER) Vertical Synchronization Interrupt Enable Mask */
|
||||
#define ISI_IER_VSYNC(value) (ISI_IER_VSYNC_Msk & ((value) << ISI_IER_VSYNC_Pos))
|
||||
#define ISI_IER_PXFR_DONE_Pos _U_(16) /**< (ISI_IER) Preview DMA Transfer Done Interrupt Enable Position */
|
||||
#define ISI_IER_PXFR_DONE_Msk (_U_(0x1) << ISI_IER_PXFR_DONE_Pos) /**< (ISI_IER) Preview DMA Transfer Done Interrupt Enable Mask */
|
||||
#define ISI_IER_PXFR_DONE(value) (ISI_IER_PXFR_DONE_Msk & ((value) << ISI_IER_PXFR_DONE_Pos))
|
||||
#define ISI_IER_CXFR_DONE_Pos _U_(17) /**< (ISI_IER) Codec DMA Transfer Done Interrupt Enable Position */
|
||||
#define ISI_IER_CXFR_DONE_Msk (_U_(0x1) << ISI_IER_CXFR_DONE_Pos) /**< (ISI_IER) Codec DMA Transfer Done Interrupt Enable Mask */
|
||||
#define ISI_IER_CXFR_DONE(value) (ISI_IER_CXFR_DONE_Msk & ((value) << ISI_IER_CXFR_DONE_Pos))
|
||||
#define ISI_IER_P_OVR_Pos _U_(24) /**< (ISI_IER) Preview Datapath Overflow Interrupt Enable Position */
|
||||
#define ISI_IER_P_OVR_Msk (_U_(0x1) << ISI_IER_P_OVR_Pos) /**< (ISI_IER) Preview Datapath Overflow Interrupt Enable Mask */
|
||||
#define ISI_IER_P_OVR(value) (ISI_IER_P_OVR_Msk & ((value) << ISI_IER_P_OVR_Pos))
|
||||
#define ISI_IER_C_OVR_Pos _U_(25) /**< (ISI_IER) Codec Datapath Overflow Interrupt Enable Position */
|
||||
#define ISI_IER_C_OVR_Msk (_U_(0x1) << ISI_IER_C_OVR_Pos) /**< (ISI_IER) Codec Datapath Overflow Interrupt Enable Mask */
|
||||
#define ISI_IER_C_OVR(value) (ISI_IER_C_OVR_Msk & ((value) << ISI_IER_C_OVR_Pos))
|
||||
#define ISI_IER_CRC_ERR_Pos _U_(26) /**< (ISI_IER) Embedded Synchronization CRC Error Interrupt Enable Position */
|
||||
#define ISI_IER_CRC_ERR_Msk (_U_(0x1) << ISI_IER_CRC_ERR_Pos) /**< (ISI_IER) Embedded Synchronization CRC Error Interrupt Enable Mask */
|
||||
#define ISI_IER_CRC_ERR(value) (ISI_IER_CRC_ERR_Msk & ((value) << ISI_IER_CRC_ERR_Pos))
|
||||
#define ISI_IER_FR_OVR_Pos _U_(27) /**< (ISI_IER) Frame Rate Overflow Interrupt Enable Position */
|
||||
#define ISI_IER_FR_OVR_Msk (_U_(0x1) << ISI_IER_FR_OVR_Pos) /**< (ISI_IER) Frame Rate Overflow Interrupt Enable Mask */
|
||||
#define ISI_IER_FR_OVR(value) (ISI_IER_FR_OVR_Msk & ((value) << ISI_IER_FR_OVR_Pos))
|
||||
#define ISI_IER_Msk _U_(0x0F030406) /**< (ISI_IER) Register Mask */
|
||||
|
||||
|
||||
/* -------- ISI_IDR : (ISI Offset: 0x30) ( /W 32) ISI Interrupt Disable Register -------- */
|
||||
#define ISI_IDR_DIS_DONE_Pos _U_(1) /**< (ISI_IDR) Disable Done Interrupt Disable Position */
|
||||
#define ISI_IDR_DIS_DONE_Msk (_U_(0x1) << ISI_IDR_DIS_DONE_Pos) /**< (ISI_IDR) Disable Done Interrupt Disable Mask */
|
||||
#define ISI_IDR_DIS_DONE(value) (ISI_IDR_DIS_DONE_Msk & ((value) << ISI_IDR_DIS_DONE_Pos))
|
||||
#define ISI_IDR_SRST_Pos _U_(2) /**< (ISI_IDR) Software Reset Interrupt Disable Position */
|
||||
#define ISI_IDR_SRST_Msk (_U_(0x1) << ISI_IDR_SRST_Pos) /**< (ISI_IDR) Software Reset Interrupt Disable Mask */
|
||||
#define ISI_IDR_SRST(value) (ISI_IDR_SRST_Msk & ((value) << ISI_IDR_SRST_Pos))
|
||||
#define ISI_IDR_VSYNC_Pos _U_(10) /**< (ISI_IDR) Vertical Synchronization Interrupt Disable Position */
|
||||
#define ISI_IDR_VSYNC_Msk (_U_(0x1) << ISI_IDR_VSYNC_Pos) /**< (ISI_IDR) Vertical Synchronization Interrupt Disable Mask */
|
||||
#define ISI_IDR_VSYNC(value) (ISI_IDR_VSYNC_Msk & ((value) << ISI_IDR_VSYNC_Pos))
|
||||
#define ISI_IDR_PXFR_DONE_Pos _U_(16) /**< (ISI_IDR) Preview DMA Transfer Done Interrupt Disable Position */
|
||||
#define ISI_IDR_PXFR_DONE_Msk (_U_(0x1) << ISI_IDR_PXFR_DONE_Pos) /**< (ISI_IDR) Preview DMA Transfer Done Interrupt Disable Mask */
|
||||
#define ISI_IDR_PXFR_DONE(value) (ISI_IDR_PXFR_DONE_Msk & ((value) << ISI_IDR_PXFR_DONE_Pos))
|
||||
#define ISI_IDR_CXFR_DONE_Pos _U_(17) /**< (ISI_IDR) Codec DMA Transfer Done Interrupt Disable Position */
|
||||
#define ISI_IDR_CXFR_DONE_Msk (_U_(0x1) << ISI_IDR_CXFR_DONE_Pos) /**< (ISI_IDR) Codec DMA Transfer Done Interrupt Disable Mask */
|
||||
#define ISI_IDR_CXFR_DONE(value) (ISI_IDR_CXFR_DONE_Msk & ((value) << ISI_IDR_CXFR_DONE_Pos))
|
||||
#define ISI_IDR_P_OVR_Pos _U_(24) /**< (ISI_IDR) Preview Datapath Overflow Interrupt Disable Position */
|
||||
#define ISI_IDR_P_OVR_Msk (_U_(0x1) << ISI_IDR_P_OVR_Pos) /**< (ISI_IDR) Preview Datapath Overflow Interrupt Disable Mask */
|
||||
#define ISI_IDR_P_OVR(value) (ISI_IDR_P_OVR_Msk & ((value) << ISI_IDR_P_OVR_Pos))
|
||||
#define ISI_IDR_C_OVR_Pos _U_(25) /**< (ISI_IDR) Codec Datapath Overflow Interrupt Disable Position */
|
||||
#define ISI_IDR_C_OVR_Msk (_U_(0x1) << ISI_IDR_C_OVR_Pos) /**< (ISI_IDR) Codec Datapath Overflow Interrupt Disable Mask */
|
||||
#define ISI_IDR_C_OVR(value) (ISI_IDR_C_OVR_Msk & ((value) << ISI_IDR_C_OVR_Pos))
|
||||
#define ISI_IDR_CRC_ERR_Pos _U_(26) /**< (ISI_IDR) Embedded Synchronization CRC Error Interrupt Disable Position */
|
||||
#define ISI_IDR_CRC_ERR_Msk (_U_(0x1) << ISI_IDR_CRC_ERR_Pos) /**< (ISI_IDR) Embedded Synchronization CRC Error Interrupt Disable Mask */
|
||||
#define ISI_IDR_CRC_ERR(value) (ISI_IDR_CRC_ERR_Msk & ((value) << ISI_IDR_CRC_ERR_Pos))
|
||||
#define ISI_IDR_FR_OVR_Pos _U_(27) /**< (ISI_IDR) Frame Rate Overflow Interrupt Disable Position */
|
||||
#define ISI_IDR_FR_OVR_Msk (_U_(0x1) << ISI_IDR_FR_OVR_Pos) /**< (ISI_IDR) Frame Rate Overflow Interrupt Disable Mask */
|
||||
#define ISI_IDR_FR_OVR(value) (ISI_IDR_FR_OVR_Msk & ((value) << ISI_IDR_FR_OVR_Pos))
|
||||
#define ISI_IDR_Msk _U_(0x0F030406) /**< (ISI_IDR) Register Mask */
|
||||
|
||||
|
||||
/* -------- ISI_IMR : (ISI Offset: 0x34) ( R/ 32) ISI Interrupt Mask Register -------- */
|
||||
#define ISI_IMR_DIS_DONE_Pos _U_(1) /**< (ISI_IMR) Module Disable Operation Completed Position */
|
||||
#define ISI_IMR_DIS_DONE_Msk (_U_(0x1) << ISI_IMR_DIS_DONE_Pos) /**< (ISI_IMR) Module Disable Operation Completed Mask */
|
||||
#define ISI_IMR_DIS_DONE(value) (ISI_IMR_DIS_DONE_Msk & ((value) << ISI_IMR_DIS_DONE_Pos))
|
||||
#define ISI_IMR_SRST_Pos _U_(2) /**< (ISI_IMR) Software Reset Completed Position */
|
||||
#define ISI_IMR_SRST_Msk (_U_(0x1) << ISI_IMR_SRST_Pos) /**< (ISI_IMR) Software Reset Completed Mask */
|
||||
#define ISI_IMR_SRST(value) (ISI_IMR_SRST_Msk & ((value) << ISI_IMR_SRST_Pos))
|
||||
#define ISI_IMR_VSYNC_Pos _U_(10) /**< (ISI_IMR) Vertical Synchronization Position */
|
||||
#define ISI_IMR_VSYNC_Msk (_U_(0x1) << ISI_IMR_VSYNC_Pos) /**< (ISI_IMR) Vertical Synchronization Mask */
|
||||
#define ISI_IMR_VSYNC(value) (ISI_IMR_VSYNC_Msk & ((value) << ISI_IMR_VSYNC_Pos))
|
||||
#define ISI_IMR_PXFR_DONE_Pos _U_(16) /**< (ISI_IMR) Preview DMA Transfer Completed Position */
|
||||
#define ISI_IMR_PXFR_DONE_Msk (_U_(0x1) << ISI_IMR_PXFR_DONE_Pos) /**< (ISI_IMR) Preview DMA Transfer Completed Mask */
|
||||
#define ISI_IMR_PXFR_DONE(value) (ISI_IMR_PXFR_DONE_Msk & ((value) << ISI_IMR_PXFR_DONE_Pos))
|
||||
#define ISI_IMR_CXFR_DONE_Pos _U_(17) /**< (ISI_IMR) Codec DMA Transfer Completed Position */
|
||||
#define ISI_IMR_CXFR_DONE_Msk (_U_(0x1) << ISI_IMR_CXFR_DONE_Pos) /**< (ISI_IMR) Codec DMA Transfer Completed Mask */
|
||||
#define ISI_IMR_CXFR_DONE(value) (ISI_IMR_CXFR_DONE_Msk & ((value) << ISI_IMR_CXFR_DONE_Pos))
|
||||
#define ISI_IMR_P_OVR_Pos _U_(24) /**< (ISI_IMR) Preview FIFO Overflow Position */
|
||||
#define ISI_IMR_P_OVR_Msk (_U_(0x1) << ISI_IMR_P_OVR_Pos) /**< (ISI_IMR) Preview FIFO Overflow Mask */
|
||||
#define ISI_IMR_P_OVR(value) (ISI_IMR_P_OVR_Msk & ((value) << ISI_IMR_P_OVR_Pos))
|
||||
#define ISI_IMR_C_OVR_Pos _U_(25) /**< (ISI_IMR) Codec FIFO Overflow Position */
|
||||
#define ISI_IMR_C_OVR_Msk (_U_(0x1) << ISI_IMR_C_OVR_Pos) /**< (ISI_IMR) Codec FIFO Overflow Mask */
|
||||
#define ISI_IMR_C_OVR(value) (ISI_IMR_C_OVR_Msk & ((value) << ISI_IMR_C_OVR_Pos))
|
||||
#define ISI_IMR_CRC_ERR_Pos _U_(26) /**< (ISI_IMR) CRC Synchronization Error Position */
|
||||
#define ISI_IMR_CRC_ERR_Msk (_U_(0x1) << ISI_IMR_CRC_ERR_Pos) /**< (ISI_IMR) CRC Synchronization Error Mask */
|
||||
#define ISI_IMR_CRC_ERR(value) (ISI_IMR_CRC_ERR_Msk & ((value) << ISI_IMR_CRC_ERR_Pos))
|
||||
#define ISI_IMR_FR_OVR_Pos _U_(27) /**< (ISI_IMR) Frame Rate Overrun Position */
|
||||
#define ISI_IMR_FR_OVR_Msk (_U_(0x1) << ISI_IMR_FR_OVR_Pos) /**< (ISI_IMR) Frame Rate Overrun Mask */
|
||||
#define ISI_IMR_FR_OVR(value) (ISI_IMR_FR_OVR_Msk & ((value) << ISI_IMR_FR_OVR_Pos))
|
||||
#define ISI_IMR_Msk _U_(0x0F030406) /**< (ISI_IMR) Register Mask */
|
||||
|
||||
|
||||
/* -------- ISI_DMA_CHER : (ISI Offset: 0x38) ( /W 32) DMA Channel Enable Register -------- */
|
||||
#define ISI_DMA_CHER_P_CH_EN_Pos _U_(0) /**< (ISI_DMA_CHER) Preview Channel Enable Position */
|
||||
#define ISI_DMA_CHER_P_CH_EN_Msk (_U_(0x1) << ISI_DMA_CHER_P_CH_EN_Pos) /**< (ISI_DMA_CHER) Preview Channel Enable Mask */
|
||||
#define ISI_DMA_CHER_P_CH_EN(value) (ISI_DMA_CHER_P_CH_EN_Msk & ((value) << ISI_DMA_CHER_P_CH_EN_Pos))
|
||||
#define ISI_DMA_CHER_C_CH_EN_Pos _U_(1) /**< (ISI_DMA_CHER) Codec Channel Enable Position */
|
||||
#define ISI_DMA_CHER_C_CH_EN_Msk (_U_(0x1) << ISI_DMA_CHER_C_CH_EN_Pos) /**< (ISI_DMA_CHER) Codec Channel Enable Mask */
|
||||
#define ISI_DMA_CHER_C_CH_EN(value) (ISI_DMA_CHER_C_CH_EN_Msk & ((value) << ISI_DMA_CHER_C_CH_EN_Pos))
|
||||
#define ISI_DMA_CHER_Msk _U_(0x00000003) /**< (ISI_DMA_CHER) Register Mask */
|
||||
|
||||
|
||||
/* -------- ISI_DMA_CHDR : (ISI Offset: 0x3C) ( /W 32) DMA Channel Disable Register -------- */
|
||||
#define ISI_DMA_CHDR_P_CH_DIS_Pos _U_(0) /**< (ISI_DMA_CHDR) Preview Channel Disable Request Position */
|
||||
#define ISI_DMA_CHDR_P_CH_DIS_Msk (_U_(0x1) << ISI_DMA_CHDR_P_CH_DIS_Pos) /**< (ISI_DMA_CHDR) Preview Channel Disable Request Mask */
|
||||
#define ISI_DMA_CHDR_P_CH_DIS(value) (ISI_DMA_CHDR_P_CH_DIS_Msk & ((value) << ISI_DMA_CHDR_P_CH_DIS_Pos))
|
||||
#define ISI_DMA_CHDR_C_CH_DIS_Pos _U_(1) /**< (ISI_DMA_CHDR) Codec Channel Disable Request Position */
|
||||
#define ISI_DMA_CHDR_C_CH_DIS_Msk (_U_(0x1) << ISI_DMA_CHDR_C_CH_DIS_Pos) /**< (ISI_DMA_CHDR) Codec Channel Disable Request Mask */
|
||||
#define ISI_DMA_CHDR_C_CH_DIS(value) (ISI_DMA_CHDR_C_CH_DIS_Msk & ((value) << ISI_DMA_CHDR_C_CH_DIS_Pos))
|
||||
#define ISI_DMA_CHDR_Msk _U_(0x00000003) /**< (ISI_DMA_CHDR) Register Mask */
|
||||
|
||||
|
||||
/* -------- ISI_DMA_CHSR : (ISI Offset: 0x40) ( R/ 32) DMA Channel Status Register -------- */
|
||||
#define ISI_DMA_CHSR_P_CH_S_Pos _U_(0) /**< (ISI_DMA_CHSR) Preview DMA Channel Status Position */
|
||||
#define ISI_DMA_CHSR_P_CH_S_Msk (_U_(0x1) << ISI_DMA_CHSR_P_CH_S_Pos) /**< (ISI_DMA_CHSR) Preview DMA Channel Status Mask */
|
||||
#define ISI_DMA_CHSR_P_CH_S(value) (ISI_DMA_CHSR_P_CH_S_Msk & ((value) << ISI_DMA_CHSR_P_CH_S_Pos))
|
||||
#define ISI_DMA_CHSR_C_CH_S_Pos _U_(1) /**< (ISI_DMA_CHSR) Code DMA Channel Status Position */
|
||||
#define ISI_DMA_CHSR_C_CH_S_Msk (_U_(0x1) << ISI_DMA_CHSR_C_CH_S_Pos) /**< (ISI_DMA_CHSR) Code DMA Channel Status Mask */
|
||||
#define ISI_DMA_CHSR_C_CH_S(value) (ISI_DMA_CHSR_C_CH_S_Msk & ((value) << ISI_DMA_CHSR_C_CH_S_Pos))
|
||||
#define ISI_DMA_CHSR_Msk _U_(0x00000003) /**< (ISI_DMA_CHSR) Register Mask */
|
||||
|
||||
|
||||
/* -------- ISI_DMA_P_ADDR : (ISI Offset: 0x44) (R/W 32) DMA Preview Base Address Register -------- */
|
||||
#define ISI_DMA_P_ADDR_P_ADDR_Pos _U_(2) /**< (ISI_DMA_P_ADDR) Preview Image Base Address Position */
|
||||
#define ISI_DMA_P_ADDR_P_ADDR_Msk (_U_(0x3FFFFFFF) << ISI_DMA_P_ADDR_P_ADDR_Pos) /**< (ISI_DMA_P_ADDR) Preview Image Base Address Mask */
|
||||
#define ISI_DMA_P_ADDR_P_ADDR(value) (ISI_DMA_P_ADDR_P_ADDR_Msk & ((value) << ISI_DMA_P_ADDR_P_ADDR_Pos))
|
||||
#define ISI_DMA_P_ADDR_Msk _U_(0xFFFFFFFC) /**< (ISI_DMA_P_ADDR) Register Mask */
|
||||
|
||||
|
||||
/* -------- ISI_DMA_P_CTRL : (ISI Offset: 0x48) (R/W 32) DMA Preview Control Register -------- */
|
||||
#define ISI_DMA_P_CTRL_P_FETCH_Pos _U_(0) /**< (ISI_DMA_P_CTRL) Descriptor Fetch Control Bit Position */
|
||||
#define ISI_DMA_P_CTRL_P_FETCH_Msk (_U_(0x1) << ISI_DMA_P_CTRL_P_FETCH_Pos) /**< (ISI_DMA_P_CTRL) Descriptor Fetch Control Bit Mask */
|
||||
#define ISI_DMA_P_CTRL_P_FETCH(value) (ISI_DMA_P_CTRL_P_FETCH_Msk & ((value) << ISI_DMA_P_CTRL_P_FETCH_Pos))
|
||||
#define ISI_DMA_P_CTRL_P_WB_Pos _U_(1) /**< (ISI_DMA_P_CTRL) Descriptor Writeback Control Bit Position */
|
||||
#define ISI_DMA_P_CTRL_P_WB_Msk (_U_(0x1) << ISI_DMA_P_CTRL_P_WB_Pos) /**< (ISI_DMA_P_CTRL) Descriptor Writeback Control Bit Mask */
|
||||
#define ISI_DMA_P_CTRL_P_WB(value) (ISI_DMA_P_CTRL_P_WB_Msk & ((value) << ISI_DMA_P_CTRL_P_WB_Pos))
|
||||
#define ISI_DMA_P_CTRL_P_IEN_Pos _U_(2) /**< (ISI_DMA_P_CTRL) Transfer Done Flag Control Position */
|
||||
#define ISI_DMA_P_CTRL_P_IEN_Msk (_U_(0x1) << ISI_DMA_P_CTRL_P_IEN_Pos) /**< (ISI_DMA_P_CTRL) Transfer Done Flag Control Mask */
|
||||
#define ISI_DMA_P_CTRL_P_IEN(value) (ISI_DMA_P_CTRL_P_IEN_Msk & ((value) << ISI_DMA_P_CTRL_P_IEN_Pos))
|
||||
#define ISI_DMA_P_CTRL_P_DONE_Pos _U_(3) /**< (ISI_DMA_P_CTRL) Preview Transfer Done Position */
|
||||
#define ISI_DMA_P_CTRL_P_DONE_Msk (_U_(0x1) << ISI_DMA_P_CTRL_P_DONE_Pos) /**< (ISI_DMA_P_CTRL) Preview Transfer Done Mask */
|
||||
#define ISI_DMA_P_CTRL_P_DONE(value) (ISI_DMA_P_CTRL_P_DONE_Msk & ((value) << ISI_DMA_P_CTRL_P_DONE_Pos))
|
||||
#define ISI_DMA_P_CTRL_Msk _U_(0x0000000F) /**< (ISI_DMA_P_CTRL) Register Mask */
|
||||
|
||||
|
||||
/* -------- ISI_DMA_P_DSCR : (ISI Offset: 0x4C) (R/W 32) DMA Preview Descriptor Address Register -------- */
|
||||
#define ISI_DMA_P_DSCR_P_DSCR_Pos _U_(2) /**< (ISI_DMA_P_DSCR) Preview Descriptor Base Address Position */
|
||||
#define ISI_DMA_P_DSCR_P_DSCR_Msk (_U_(0x3FFFFFFF) << ISI_DMA_P_DSCR_P_DSCR_Pos) /**< (ISI_DMA_P_DSCR) Preview Descriptor Base Address Mask */
|
||||
#define ISI_DMA_P_DSCR_P_DSCR(value) (ISI_DMA_P_DSCR_P_DSCR_Msk & ((value) << ISI_DMA_P_DSCR_P_DSCR_Pos))
|
||||
#define ISI_DMA_P_DSCR_Msk _U_(0xFFFFFFFC) /**< (ISI_DMA_P_DSCR) Register Mask */
|
||||
|
||||
|
||||
/* -------- ISI_DMA_C_ADDR : (ISI Offset: 0x50) (R/W 32) DMA Codec Base Address Register -------- */
|
||||
#define ISI_DMA_C_ADDR_C_ADDR_Pos _U_(2) /**< (ISI_DMA_C_ADDR) Codec Image Base Address Position */
|
||||
#define ISI_DMA_C_ADDR_C_ADDR_Msk (_U_(0x3FFFFFFF) << ISI_DMA_C_ADDR_C_ADDR_Pos) /**< (ISI_DMA_C_ADDR) Codec Image Base Address Mask */
|
||||
#define ISI_DMA_C_ADDR_C_ADDR(value) (ISI_DMA_C_ADDR_C_ADDR_Msk & ((value) << ISI_DMA_C_ADDR_C_ADDR_Pos))
|
||||
#define ISI_DMA_C_ADDR_Msk _U_(0xFFFFFFFC) /**< (ISI_DMA_C_ADDR) Register Mask */
|
||||
|
||||
|
||||
/* -------- ISI_DMA_C_CTRL : (ISI Offset: 0x54) (R/W 32) DMA Codec Control Register -------- */
|
||||
#define ISI_DMA_C_CTRL_C_FETCH_Pos _U_(0) /**< (ISI_DMA_C_CTRL) Descriptor Fetch Control Bit Position */
|
||||
#define ISI_DMA_C_CTRL_C_FETCH_Msk (_U_(0x1) << ISI_DMA_C_CTRL_C_FETCH_Pos) /**< (ISI_DMA_C_CTRL) Descriptor Fetch Control Bit Mask */
|
||||
#define ISI_DMA_C_CTRL_C_FETCH(value) (ISI_DMA_C_CTRL_C_FETCH_Msk & ((value) << ISI_DMA_C_CTRL_C_FETCH_Pos))
|
||||
#define ISI_DMA_C_CTRL_C_WB_Pos _U_(1) /**< (ISI_DMA_C_CTRL) Descriptor Writeback Control Bit Position */
|
||||
#define ISI_DMA_C_CTRL_C_WB_Msk (_U_(0x1) << ISI_DMA_C_CTRL_C_WB_Pos) /**< (ISI_DMA_C_CTRL) Descriptor Writeback Control Bit Mask */
|
||||
#define ISI_DMA_C_CTRL_C_WB(value) (ISI_DMA_C_CTRL_C_WB_Msk & ((value) << ISI_DMA_C_CTRL_C_WB_Pos))
|
||||
#define ISI_DMA_C_CTRL_C_IEN_Pos _U_(2) /**< (ISI_DMA_C_CTRL) Transfer Done Flag Control Position */
|
||||
#define ISI_DMA_C_CTRL_C_IEN_Msk (_U_(0x1) << ISI_DMA_C_CTRL_C_IEN_Pos) /**< (ISI_DMA_C_CTRL) Transfer Done Flag Control Mask */
|
||||
#define ISI_DMA_C_CTRL_C_IEN(value) (ISI_DMA_C_CTRL_C_IEN_Msk & ((value) << ISI_DMA_C_CTRL_C_IEN_Pos))
|
||||
#define ISI_DMA_C_CTRL_C_DONE_Pos _U_(3) /**< (ISI_DMA_C_CTRL) Codec Transfer Done Position */
|
||||
#define ISI_DMA_C_CTRL_C_DONE_Msk (_U_(0x1) << ISI_DMA_C_CTRL_C_DONE_Pos) /**< (ISI_DMA_C_CTRL) Codec Transfer Done Mask */
|
||||
#define ISI_DMA_C_CTRL_C_DONE(value) (ISI_DMA_C_CTRL_C_DONE_Msk & ((value) << ISI_DMA_C_CTRL_C_DONE_Pos))
|
||||
#define ISI_DMA_C_CTRL_Msk _U_(0x0000000F) /**< (ISI_DMA_C_CTRL) Register Mask */
|
||||
|
||||
|
||||
/* -------- ISI_DMA_C_DSCR : (ISI Offset: 0x58) (R/W 32) DMA Codec Descriptor Address Register -------- */
|
||||
#define ISI_DMA_C_DSCR_C_DSCR_Pos _U_(2) /**< (ISI_DMA_C_DSCR) Codec Descriptor Base Address Position */
|
||||
#define ISI_DMA_C_DSCR_C_DSCR_Msk (_U_(0x3FFFFFFF) << ISI_DMA_C_DSCR_C_DSCR_Pos) /**< (ISI_DMA_C_DSCR) Codec Descriptor Base Address Mask */
|
||||
#define ISI_DMA_C_DSCR_C_DSCR(value) (ISI_DMA_C_DSCR_C_DSCR_Msk & ((value) << ISI_DMA_C_DSCR_C_DSCR_Pos))
|
||||
#define ISI_DMA_C_DSCR_Msk _U_(0xFFFFFFFC) /**< (ISI_DMA_C_DSCR) Register Mask */
|
||||
|
||||
|
||||
/* -------- ISI_WPMR : (ISI Offset: 0xE4) (R/W 32) Write Protection Mode Register -------- */
|
||||
#define ISI_WPMR_WPEN_Pos _U_(0) /**< (ISI_WPMR) Write Protection Enable Position */
|
||||
#define ISI_WPMR_WPEN_Msk (_U_(0x1) << ISI_WPMR_WPEN_Pos) /**< (ISI_WPMR) Write Protection Enable Mask */
|
||||
#define ISI_WPMR_WPEN(value) (ISI_WPMR_WPEN_Msk & ((value) << ISI_WPMR_WPEN_Pos))
|
||||
#define ISI_WPMR_WPKEY_Pos _U_(8) /**< (ISI_WPMR) Write Protection Key Password Position */
|
||||
#define ISI_WPMR_WPKEY_Msk (_U_(0xFFFFFF) << ISI_WPMR_WPKEY_Pos) /**< (ISI_WPMR) Write Protection Key Password Mask */
|
||||
#define ISI_WPMR_WPKEY(value) (ISI_WPMR_WPKEY_Msk & ((value) << ISI_WPMR_WPKEY_Pos))
|
||||
#define ISI_WPMR_WPKEY_PASSWD_Val _U_(0x495349) /**< (ISI_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. */
|
||||
#define ISI_WPMR_WPKEY_PASSWD (ISI_WPMR_WPKEY_PASSWD_Val << ISI_WPMR_WPKEY_Pos) /**< (ISI_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. Position */
|
||||
#define ISI_WPMR_Msk _U_(0xFFFFFF01) /**< (ISI_WPMR) Register Mask */
|
||||
|
||||
|
||||
/* -------- ISI_WPSR : (ISI Offset: 0xE8) ( R/ 32) Write Protection Status Register -------- */
|
||||
#define ISI_WPSR_WPVS_Pos _U_(0) /**< (ISI_WPSR) Write Protection Violation Status Position */
|
||||
#define ISI_WPSR_WPVS_Msk (_U_(0x1) << ISI_WPSR_WPVS_Pos) /**< (ISI_WPSR) Write Protection Violation Status Mask */
|
||||
#define ISI_WPSR_WPVS(value) (ISI_WPSR_WPVS_Msk & ((value) << ISI_WPSR_WPVS_Pos))
|
||||
#define ISI_WPSR_WPVSRC_Pos _U_(8) /**< (ISI_WPSR) Write Protection Violation Source Position */
|
||||
#define ISI_WPSR_WPVSRC_Msk (_U_(0xFFFF) << ISI_WPSR_WPVSRC_Pos) /**< (ISI_WPSR) Write Protection Violation Source Mask */
|
||||
#define ISI_WPSR_WPVSRC(value) (ISI_WPSR_WPVSRC_Msk & ((value) << ISI_WPSR_WPVSRC_Pos))
|
||||
#define ISI_WPSR_Msk _U_(0x00FFFF01) /**< (ISI_WPSR) Register Mask */
|
||||
|
||||
|
||||
/** \brief ISI register offsets definitions */
|
||||
#define ISI_CFG1_REG_OFST (0x00) /**< (ISI_CFG1) ISI Configuration 1 Register Offset */
|
||||
#define ISI_CFG2_REG_OFST (0x04) /**< (ISI_CFG2) ISI Configuration 2 Register Offset */
|
||||
#define ISI_PSIZE_REG_OFST (0x08) /**< (ISI_PSIZE) ISI Preview Size Register Offset */
|
||||
#define ISI_PDECF_REG_OFST (0x0C) /**< (ISI_PDECF) ISI Preview Decimation Factor Register Offset */
|
||||
#define ISI_Y2R_SET0_REG_OFST (0x10) /**< (ISI_Y2R_SET0) ISI Color Space Conversion YCrCb To RGB Set 0 Register Offset */
|
||||
#define ISI_Y2R_SET1_REG_OFST (0x14) /**< (ISI_Y2R_SET1) ISI Color Space Conversion YCrCb To RGB Set 1 Register Offset */
|
||||
#define ISI_R2Y_SET0_REG_OFST (0x18) /**< (ISI_R2Y_SET0) ISI Color Space Conversion RGB To YCrCb Set 0 Register Offset */
|
||||
#define ISI_R2Y_SET1_REG_OFST (0x1C) /**< (ISI_R2Y_SET1) ISI Color Space Conversion RGB To YCrCb Set 1 Register Offset */
|
||||
#define ISI_R2Y_SET2_REG_OFST (0x20) /**< (ISI_R2Y_SET2) ISI Color Space Conversion RGB To YCrCb Set 2 Register Offset */
|
||||
#define ISI_CR_REG_OFST (0x24) /**< (ISI_CR) ISI Control Register Offset */
|
||||
#define ISI_SR_REG_OFST (0x28) /**< (ISI_SR) ISI Status Register Offset */
|
||||
#define ISI_IER_REG_OFST (0x2C) /**< (ISI_IER) ISI Interrupt Enable Register Offset */
|
||||
#define ISI_IDR_REG_OFST (0x30) /**< (ISI_IDR) ISI Interrupt Disable Register Offset */
|
||||
#define ISI_IMR_REG_OFST (0x34) /**< (ISI_IMR) ISI Interrupt Mask Register Offset */
|
||||
#define ISI_DMA_CHER_REG_OFST (0x38) /**< (ISI_DMA_CHER) DMA Channel Enable Register Offset */
|
||||
#define ISI_DMA_CHDR_REG_OFST (0x3C) /**< (ISI_DMA_CHDR) DMA Channel Disable Register Offset */
|
||||
#define ISI_DMA_CHSR_REG_OFST (0x40) /**< (ISI_DMA_CHSR) DMA Channel Status Register Offset */
|
||||
#define ISI_DMA_P_ADDR_REG_OFST (0x44) /**< (ISI_DMA_P_ADDR) DMA Preview Base Address Register Offset */
|
||||
#define ISI_DMA_P_CTRL_REG_OFST (0x48) /**< (ISI_DMA_P_CTRL) DMA Preview Control Register Offset */
|
||||
#define ISI_DMA_P_DSCR_REG_OFST (0x4C) /**< (ISI_DMA_P_DSCR) DMA Preview Descriptor Address Register Offset */
|
||||
#define ISI_DMA_C_ADDR_REG_OFST (0x50) /**< (ISI_DMA_C_ADDR) DMA Codec Base Address Register Offset */
|
||||
#define ISI_DMA_C_CTRL_REG_OFST (0x54) /**< (ISI_DMA_C_CTRL) DMA Codec Control Register Offset */
|
||||
#define ISI_DMA_C_DSCR_REG_OFST (0x58) /**< (ISI_DMA_C_DSCR) DMA Codec Descriptor Address Register Offset */
|
||||
#define ISI_WPMR_REG_OFST (0xE4) /**< (ISI_WPMR) Write Protection Mode Register Offset */
|
||||
#define ISI_WPSR_REG_OFST (0xE8) /**< (ISI_WPSR) Write Protection Status Register Offset */
|
||||
|
||||
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
/** \brief ISI register API structure */
|
||||
typedef struct
|
||||
{
|
||||
__IO uint32_t ISI_CFG1; /**< Offset: 0x00 (R/W 32) ISI Configuration 1 Register */
|
||||
__IO uint32_t ISI_CFG2; /**< Offset: 0x04 (R/W 32) ISI Configuration 2 Register */
|
||||
__IO uint32_t ISI_PSIZE; /**< Offset: 0x08 (R/W 32) ISI Preview Size Register */
|
||||
__IO uint32_t ISI_PDECF; /**< Offset: 0x0C (R/W 32) ISI Preview Decimation Factor Register */
|
||||
__IO uint32_t ISI_Y2R_SET0; /**< Offset: 0x10 (R/W 32) ISI Color Space Conversion YCrCb To RGB Set 0 Register */
|
||||
__IO uint32_t ISI_Y2R_SET1; /**< Offset: 0x14 (R/W 32) ISI Color Space Conversion YCrCb To RGB Set 1 Register */
|
||||
__IO uint32_t ISI_R2Y_SET0; /**< Offset: 0x18 (R/W 32) ISI Color Space Conversion RGB To YCrCb Set 0 Register */
|
||||
__IO uint32_t ISI_R2Y_SET1; /**< Offset: 0x1C (R/W 32) ISI Color Space Conversion RGB To YCrCb Set 1 Register */
|
||||
__IO uint32_t ISI_R2Y_SET2; /**< Offset: 0x20 (R/W 32) ISI Color Space Conversion RGB To YCrCb Set 2 Register */
|
||||
__O uint32_t ISI_CR; /**< Offset: 0x24 ( /W 32) ISI Control Register */
|
||||
__I uint32_t ISI_SR; /**< Offset: 0x28 (R/ 32) ISI Status Register */
|
||||
__O uint32_t ISI_IER; /**< Offset: 0x2C ( /W 32) ISI Interrupt Enable Register */
|
||||
__O uint32_t ISI_IDR; /**< Offset: 0x30 ( /W 32) ISI Interrupt Disable Register */
|
||||
__I uint32_t ISI_IMR; /**< Offset: 0x34 (R/ 32) ISI Interrupt Mask Register */
|
||||
__O uint32_t ISI_DMA_CHER; /**< Offset: 0x38 ( /W 32) DMA Channel Enable Register */
|
||||
__O uint32_t ISI_DMA_CHDR; /**< Offset: 0x3C ( /W 32) DMA Channel Disable Register */
|
||||
__I uint32_t ISI_DMA_CHSR; /**< Offset: 0x40 (R/ 32) DMA Channel Status Register */
|
||||
__IO uint32_t ISI_DMA_P_ADDR; /**< Offset: 0x44 (R/W 32) DMA Preview Base Address Register */
|
||||
__IO uint32_t ISI_DMA_P_CTRL; /**< Offset: 0x48 (R/W 32) DMA Preview Control Register */
|
||||
__IO uint32_t ISI_DMA_P_DSCR; /**< Offset: 0x4C (R/W 32) DMA Preview Descriptor Address Register */
|
||||
__IO uint32_t ISI_DMA_C_ADDR; /**< Offset: 0x50 (R/W 32) DMA Codec Base Address Register */
|
||||
__IO uint32_t ISI_DMA_C_CTRL; /**< Offset: 0x54 (R/W 32) DMA Codec Control Register */
|
||||
__IO uint32_t ISI_DMA_C_DSCR; /**< Offset: 0x58 (R/W 32) DMA Codec Descriptor Address Register */
|
||||
__I uint8_t Reserved1[0x88];
|
||||
__IO uint32_t ISI_WPMR; /**< Offset: 0xE4 (R/W 32) Write Protection Mode Register */
|
||||
__I uint32_t ISI_WPSR; /**< Offset: 0xE8 (R/ 32) Write Protection Status Register */
|
||||
} isi_registers_t;
|
||||
|
||||
|
||||
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
#endif /* _SAME70_ISI_COMPONENT_H_ */
|
||||
@ -0,0 +1,274 @@
|
||||
/**
|
||||
* \brief Component description for MATRIX
|
||||
*
|
||||
* Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries.
|
||||
*
|
||||
* Subject to your compliance with these terms, you may use Microchip software and any derivatives
|
||||
* exclusively with Microchip products. It is your responsibility to comply with third party license
|
||||
* terms applicable to your use of third party software (including open source software) that may
|
||||
* accompany Microchip software.
|
||||
*
|
||||
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY,
|
||||
* APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND
|
||||
* FITNESS FOR A PARTICULAR PURPOSE.
|
||||
*
|
||||
* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
|
||||
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF
|
||||
* MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
|
||||
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT
|
||||
* EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
|
||||
*
|
||||
*/
|
||||
|
||||
/* file generated from device description version 2017-08-25T14:00:00Z */
|
||||
#ifndef _SAME70_MATRIX_COMPONENT_H_
|
||||
#define _SAME70_MATRIX_COMPONENT_H_
|
||||
|
||||
/* ************************************************************************** */
|
||||
/* SOFTWARE API DEFINITION FOR MATRIX */
|
||||
/* ************************************************************************** */
|
||||
|
||||
/* -------- MATRIX_PRAS : (MATRIX Offset: 0x00) (R/W 32) Priority Register A for Slave 0 -------- */
|
||||
#define MATRIX_PRAS_M0PR_Pos _U_(0) /**< (MATRIX_PRAS) Master 0 Priority Position */
|
||||
#define MATRIX_PRAS_M0PR_Msk (_U_(0x3) << MATRIX_PRAS_M0PR_Pos) /**< (MATRIX_PRAS) Master 0 Priority Mask */
|
||||
#define MATRIX_PRAS_M0PR(value) (MATRIX_PRAS_M0PR_Msk & ((value) << MATRIX_PRAS_M0PR_Pos))
|
||||
#define MATRIX_PRAS_M1PR_Pos _U_(4) /**< (MATRIX_PRAS) Master 1 Priority Position */
|
||||
#define MATRIX_PRAS_M1PR_Msk (_U_(0x3) << MATRIX_PRAS_M1PR_Pos) /**< (MATRIX_PRAS) Master 1 Priority Mask */
|
||||
#define MATRIX_PRAS_M1PR(value) (MATRIX_PRAS_M1PR_Msk & ((value) << MATRIX_PRAS_M1PR_Pos))
|
||||
#define MATRIX_PRAS_M2PR_Pos _U_(8) /**< (MATRIX_PRAS) Master 2 Priority Position */
|
||||
#define MATRIX_PRAS_M2PR_Msk (_U_(0x3) << MATRIX_PRAS_M2PR_Pos) /**< (MATRIX_PRAS) Master 2 Priority Mask */
|
||||
#define MATRIX_PRAS_M2PR(value) (MATRIX_PRAS_M2PR_Msk & ((value) << MATRIX_PRAS_M2PR_Pos))
|
||||
#define MATRIX_PRAS_M3PR_Pos _U_(12) /**< (MATRIX_PRAS) Master 3 Priority Position */
|
||||
#define MATRIX_PRAS_M3PR_Msk (_U_(0x3) << MATRIX_PRAS_M3PR_Pos) /**< (MATRIX_PRAS) Master 3 Priority Mask */
|
||||
#define MATRIX_PRAS_M3PR(value) (MATRIX_PRAS_M3PR_Msk & ((value) << MATRIX_PRAS_M3PR_Pos))
|
||||
#define MATRIX_PRAS_M4PR_Pos _U_(16) /**< (MATRIX_PRAS) Master 4 Priority Position */
|
||||
#define MATRIX_PRAS_M4PR_Msk (_U_(0x3) << MATRIX_PRAS_M4PR_Pos) /**< (MATRIX_PRAS) Master 4 Priority Mask */
|
||||
#define MATRIX_PRAS_M4PR(value) (MATRIX_PRAS_M4PR_Msk & ((value) << MATRIX_PRAS_M4PR_Pos))
|
||||
#define MATRIX_PRAS_M5PR_Pos _U_(20) /**< (MATRIX_PRAS) Master 5 Priority Position */
|
||||
#define MATRIX_PRAS_M5PR_Msk (_U_(0x3) << MATRIX_PRAS_M5PR_Pos) /**< (MATRIX_PRAS) Master 5 Priority Mask */
|
||||
#define MATRIX_PRAS_M5PR(value) (MATRIX_PRAS_M5PR_Msk & ((value) << MATRIX_PRAS_M5PR_Pos))
|
||||
#define MATRIX_PRAS_M6PR_Pos _U_(24) /**< (MATRIX_PRAS) Master 6 Priority Position */
|
||||
#define MATRIX_PRAS_M6PR_Msk (_U_(0x3) << MATRIX_PRAS_M6PR_Pos) /**< (MATRIX_PRAS) Master 6 Priority Mask */
|
||||
#define MATRIX_PRAS_M6PR(value) (MATRIX_PRAS_M6PR_Msk & ((value) << MATRIX_PRAS_M6PR_Pos))
|
||||
#define MATRIX_PRAS_Msk _U_(0x03333333) /**< (MATRIX_PRAS) Register Mask */
|
||||
|
||||
|
||||
/* -------- MATRIX_PRBS : (MATRIX Offset: 0x04) (R/W 32) Priority Register B for Slave 0 -------- */
|
||||
#define MATRIX_PRBS_M8PR_Pos _U_(0) /**< (MATRIX_PRBS) Master 8 Priority Position */
|
||||
#define MATRIX_PRBS_M8PR_Msk (_U_(0x3) << MATRIX_PRBS_M8PR_Pos) /**< (MATRIX_PRBS) Master 8 Priority Mask */
|
||||
#define MATRIX_PRBS_M8PR(value) (MATRIX_PRBS_M8PR_Msk & ((value) << MATRIX_PRBS_M8PR_Pos))
|
||||
#define MATRIX_PRBS_M9PR_Pos _U_(4) /**< (MATRIX_PRBS) Master 9 Priority Position */
|
||||
#define MATRIX_PRBS_M9PR_Msk (_U_(0x3) << MATRIX_PRBS_M9PR_Pos) /**< (MATRIX_PRBS) Master 9 Priority Mask */
|
||||
#define MATRIX_PRBS_M9PR(value) (MATRIX_PRBS_M9PR_Msk & ((value) << MATRIX_PRBS_M9PR_Pos))
|
||||
#define MATRIX_PRBS_M10PR_Pos _U_(8) /**< (MATRIX_PRBS) Master 10 Priority Position */
|
||||
#define MATRIX_PRBS_M10PR_Msk (_U_(0x3) << MATRIX_PRBS_M10PR_Pos) /**< (MATRIX_PRBS) Master 10 Priority Mask */
|
||||
#define MATRIX_PRBS_M10PR(value) (MATRIX_PRBS_M10PR_Msk & ((value) << MATRIX_PRBS_M10PR_Pos))
|
||||
#define MATRIX_PRBS_M11PR_Pos _U_(12) /**< (MATRIX_PRBS) Master 11 Priority Position */
|
||||
#define MATRIX_PRBS_M11PR_Msk (_U_(0x3) << MATRIX_PRBS_M11PR_Pos) /**< (MATRIX_PRBS) Master 11 Priority Mask */
|
||||
#define MATRIX_PRBS_M11PR(value) (MATRIX_PRBS_M11PR_Msk & ((value) << MATRIX_PRBS_M11PR_Pos))
|
||||
#define MATRIX_PRBS_Msk _U_(0x00003333) /**< (MATRIX_PRBS) Register Mask */
|
||||
|
||||
|
||||
/* -------- MATRIX_MCFG : (MATRIX Offset: 0x00) (R/W 32) Master Configuration Register 0 -------- */
|
||||
#define MATRIX_MCFG_ULBT_Pos _U_(0) /**< (MATRIX_MCFG) Undefined Length Burst Type Position */
|
||||
#define MATRIX_MCFG_ULBT_Msk (_U_(0x7) << MATRIX_MCFG_ULBT_Pos) /**< (MATRIX_MCFG) Undefined Length Burst Type Mask */
|
||||
#define MATRIX_MCFG_ULBT(value) (MATRIX_MCFG_ULBT_Msk & ((value) << MATRIX_MCFG_ULBT_Pos))
|
||||
#define MATRIX_MCFG_ULBT_UNLTD_LENGTH_Val _U_(0x0) /**< (MATRIX_MCFG) Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1-Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave. */
|
||||
#define MATRIX_MCFG_ULBT_SINGLE_ACCESS_Val _U_(0x1) /**< (MATRIX_MCFG) Single Access-The undefined length burst is treated as a succession of single accesses, allowing re-arbitration at each beat of the INCR burst or bursts sequence. */
|
||||
#define MATRIX_MCFG_ULBT_4BEAT_BURST_Val _U_(0x2) /**< (MATRIX_MCFG) 4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing re-arbitration every 4 beats. */
|
||||
#define MATRIX_MCFG_ULBT_8BEAT_BURST_Val _U_(0x3) /**< (MATRIX_MCFG) 8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing re-arbitration every 8 beats. */
|
||||
#define MATRIX_MCFG_ULBT_16BEAT_BURST_Val _U_(0x4) /**< (MATRIX_MCFG) 16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing re-arbitration every 16 beats. */
|
||||
#define MATRIX_MCFG_ULBT_32BEAT_BURST_Val _U_(0x5) /**< (MATRIX_MCFG) 32-beat Burst -The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing re-arbitration every 32 beats. */
|
||||
#define MATRIX_MCFG_ULBT_64BEAT_BURST_Val _U_(0x6) /**< (MATRIX_MCFG) 64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing re-arbitration every 64 beats. */
|
||||
#define MATRIX_MCFG_ULBT_128BEAT_BURST_Val _U_(0x7) /**< (MATRIX_MCFG) 128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing re-arbitration every 128 beats. */
|
||||
#define MATRIX_MCFG_ULBT_UNLTD_LENGTH (MATRIX_MCFG_ULBT_UNLTD_LENGTH_Val << MATRIX_MCFG_ULBT_Pos) /**< (MATRIX_MCFG) Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1-Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave. Position */
|
||||
#define MATRIX_MCFG_ULBT_SINGLE_ACCESS (MATRIX_MCFG_ULBT_SINGLE_ACCESS_Val << MATRIX_MCFG_ULBT_Pos) /**< (MATRIX_MCFG) Single Access-The undefined length burst is treated as a succession of single accesses, allowing re-arbitration at each beat of the INCR burst or bursts sequence. Position */
|
||||
#define MATRIX_MCFG_ULBT_4BEAT_BURST (MATRIX_MCFG_ULBT_4BEAT_BURST_Val << MATRIX_MCFG_ULBT_Pos) /**< (MATRIX_MCFG) 4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing re-arbitration every 4 beats. Position */
|
||||
#define MATRIX_MCFG_ULBT_8BEAT_BURST (MATRIX_MCFG_ULBT_8BEAT_BURST_Val << MATRIX_MCFG_ULBT_Pos) /**< (MATRIX_MCFG) 8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing re-arbitration every 8 beats. Position */
|
||||
#define MATRIX_MCFG_ULBT_16BEAT_BURST (MATRIX_MCFG_ULBT_16BEAT_BURST_Val << MATRIX_MCFG_ULBT_Pos) /**< (MATRIX_MCFG) 16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing re-arbitration every 16 beats. Position */
|
||||
#define MATRIX_MCFG_ULBT_32BEAT_BURST (MATRIX_MCFG_ULBT_32BEAT_BURST_Val << MATRIX_MCFG_ULBT_Pos) /**< (MATRIX_MCFG) 32-beat Burst -The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing re-arbitration every 32 beats. Position */
|
||||
#define MATRIX_MCFG_ULBT_64BEAT_BURST (MATRIX_MCFG_ULBT_64BEAT_BURST_Val << MATRIX_MCFG_ULBT_Pos) /**< (MATRIX_MCFG) 64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing re-arbitration every 64 beats. Position */
|
||||
#define MATRIX_MCFG_ULBT_128BEAT_BURST (MATRIX_MCFG_ULBT_128BEAT_BURST_Val << MATRIX_MCFG_ULBT_Pos) /**< (MATRIX_MCFG) 128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing re-arbitration every 128 beats. Position */
|
||||
#define MATRIX_MCFG_Msk _U_(0x00000007) /**< (MATRIX_MCFG) Register Mask */
|
||||
|
||||
|
||||
/* -------- MATRIX_SCFG : (MATRIX Offset: 0x40) (R/W 32) Slave Configuration Register 0 -------- */
|
||||
#define MATRIX_SCFG_SLOT_CYCLE_Pos _U_(0) /**< (MATRIX_SCFG) Maximum Bus Grant Duration for Masters Position */
|
||||
#define MATRIX_SCFG_SLOT_CYCLE_Msk (_U_(0x1FF) << MATRIX_SCFG_SLOT_CYCLE_Pos) /**< (MATRIX_SCFG) Maximum Bus Grant Duration for Masters Mask */
|
||||
#define MATRIX_SCFG_SLOT_CYCLE(value) (MATRIX_SCFG_SLOT_CYCLE_Msk & ((value) << MATRIX_SCFG_SLOT_CYCLE_Pos))
|
||||
#define MATRIX_SCFG_DEFMSTR_TYPE_Pos _U_(16) /**< (MATRIX_SCFG) Default Master Type Position */
|
||||
#define MATRIX_SCFG_DEFMSTR_TYPE_Msk (_U_(0x3) << MATRIX_SCFG_DEFMSTR_TYPE_Pos) /**< (MATRIX_SCFG) Default Master Type Mask */
|
||||
#define MATRIX_SCFG_DEFMSTR_TYPE(value) (MATRIX_SCFG_DEFMSTR_TYPE_Msk & ((value) << MATRIX_SCFG_DEFMSTR_TYPE_Pos))
|
||||
#define MATRIX_SCFG_DEFMSTR_TYPE_NONE_Val _U_(0x0) /**< (MATRIX_SCFG) No Default Master-At the end of the current slave access, if no other master request is pending, the slave is disconnected from all masters.This results in a one clock cycle latency for the first access of a burst transfer or for a single access. */
|
||||
#define MATRIX_SCFG_DEFMSTR_TYPE_LAST_Val _U_(0x1) /**< (MATRIX_SCFG) Last Default Master-At the end of the current slave access, if no other master request is pending, the slave stays connected to the last master having accessed it.This results in not having one clock cycle latency when the last master tries to access the slave again. */
|
||||
#define MATRIX_SCFG_DEFMSTR_TYPE_FIXED_Val _U_(0x2) /**< (MATRIX_SCFG) Fixed Default Master-At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number that has been written in the FIXED_DEFMSTR field.This results in not having one clock cycle latency when the fixed master tries to access the slave again. */
|
||||
#define MATRIX_SCFG_DEFMSTR_TYPE_NONE (MATRIX_SCFG_DEFMSTR_TYPE_NONE_Val << MATRIX_SCFG_DEFMSTR_TYPE_Pos) /**< (MATRIX_SCFG) No Default Master-At the end of the current slave access, if no other master request is pending, the slave is disconnected from all masters.This results in a one clock cycle latency for the first access of a burst transfer or for a single access. Position */
|
||||
#define MATRIX_SCFG_DEFMSTR_TYPE_LAST (MATRIX_SCFG_DEFMSTR_TYPE_LAST_Val << MATRIX_SCFG_DEFMSTR_TYPE_Pos) /**< (MATRIX_SCFG) Last Default Master-At the end of the current slave access, if no other master request is pending, the slave stays connected to the last master having accessed it.This results in not having one clock cycle latency when the last master tries to access the slave again. Position */
|
||||
#define MATRIX_SCFG_DEFMSTR_TYPE_FIXED (MATRIX_SCFG_DEFMSTR_TYPE_FIXED_Val << MATRIX_SCFG_DEFMSTR_TYPE_Pos) /**< (MATRIX_SCFG) Fixed Default Master-At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number that has been written in the FIXED_DEFMSTR field.This results in not having one clock cycle latency when the fixed master tries to access the slave again. Position */
|
||||
#define MATRIX_SCFG_FIXED_DEFMSTR_Pos _U_(18) /**< (MATRIX_SCFG) Fixed Default Master Position */
|
||||
#define MATRIX_SCFG_FIXED_DEFMSTR_Msk (_U_(0xF) << MATRIX_SCFG_FIXED_DEFMSTR_Pos) /**< (MATRIX_SCFG) Fixed Default Master Mask */
|
||||
#define MATRIX_SCFG_FIXED_DEFMSTR(value) (MATRIX_SCFG_FIXED_DEFMSTR_Msk & ((value) << MATRIX_SCFG_FIXED_DEFMSTR_Pos))
|
||||
#define MATRIX_SCFG_Msk _U_(0x003F01FF) /**< (MATRIX_SCFG) Register Mask */
|
||||
|
||||
|
||||
/* -------- MATRIX_MRCR : (MATRIX Offset: 0x100) (R/W 32) Master Remap Control Register -------- */
|
||||
#define MATRIX_MRCR_RCB0_Pos _U_(0) /**< (MATRIX_MRCR) Remap Command Bit for Master 0 Position */
|
||||
#define MATRIX_MRCR_RCB0_Msk (_U_(0x1) << MATRIX_MRCR_RCB0_Pos) /**< (MATRIX_MRCR) Remap Command Bit for Master 0 Mask */
|
||||
#define MATRIX_MRCR_RCB0(value) (MATRIX_MRCR_RCB0_Msk & ((value) << MATRIX_MRCR_RCB0_Pos))
|
||||
#define MATRIX_MRCR_RCB1_Pos _U_(1) /**< (MATRIX_MRCR) Remap Command Bit for Master 1 Position */
|
||||
#define MATRIX_MRCR_RCB1_Msk (_U_(0x1) << MATRIX_MRCR_RCB1_Pos) /**< (MATRIX_MRCR) Remap Command Bit for Master 1 Mask */
|
||||
#define MATRIX_MRCR_RCB1(value) (MATRIX_MRCR_RCB1_Msk & ((value) << MATRIX_MRCR_RCB1_Pos))
|
||||
#define MATRIX_MRCR_RCB2_Pos _U_(2) /**< (MATRIX_MRCR) Remap Command Bit for Master 2 Position */
|
||||
#define MATRIX_MRCR_RCB2_Msk (_U_(0x1) << MATRIX_MRCR_RCB2_Pos) /**< (MATRIX_MRCR) Remap Command Bit for Master 2 Mask */
|
||||
#define MATRIX_MRCR_RCB2(value) (MATRIX_MRCR_RCB2_Msk & ((value) << MATRIX_MRCR_RCB2_Pos))
|
||||
#define MATRIX_MRCR_RCB3_Pos _U_(3) /**< (MATRIX_MRCR) Remap Command Bit for Master 3 Position */
|
||||
#define MATRIX_MRCR_RCB3_Msk (_U_(0x1) << MATRIX_MRCR_RCB3_Pos) /**< (MATRIX_MRCR) Remap Command Bit for Master 3 Mask */
|
||||
#define MATRIX_MRCR_RCB3(value) (MATRIX_MRCR_RCB3_Msk & ((value) << MATRIX_MRCR_RCB3_Pos))
|
||||
#define MATRIX_MRCR_RCB4_Pos _U_(4) /**< (MATRIX_MRCR) Remap Command Bit for Master 4 Position */
|
||||
#define MATRIX_MRCR_RCB4_Msk (_U_(0x1) << MATRIX_MRCR_RCB4_Pos) /**< (MATRIX_MRCR) Remap Command Bit for Master 4 Mask */
|
||||
#define MATRIX_MRCR_RCB4(value) (MATRIX_MRCR_RCB4_Msk & ((value) << MATRIX_MRCR_RCB4_Pos))
|
||||
#define MATRIX_MRCR_RCB5_Pos _U_(5) /**< (MATRIX_MRCR) Remap Command Bit for Master 5 Position */
|
||||
#define MATRIX_MRCR_RCB5_Msk (_U_(0x1) << MATRIX_MRCR_RCB5_Pos) /**< (MATRIX_MRCR) Remap Command Bit for Master 5 Mask */
|
||||
#define MATRIX_MRCR_RCB5(value) (MATRIX_MRCR_RCB5_Msk & ((value) << MATRIX_MRCR_RCB5_Pos))
|
||||
#define MATRIX_MRCR_RCB6_Pos _U_(6) /**< (MATRIX_MRCR) Remap Command Bit for Master 6 Position */
|
||||
#define MATRIX_MRCR_RCB6_Msk (_U_(0x1) << MATRIX_MRCR_RCB6_Pos) /**< (MATRIX_MRCR) Remap Command Bit for Master 6 Mask */
|
||||
#define MATRIX_MRCR_RCB6(value) (MATRIX_MRCR_RCB6_Msk & ((value) << MATRIX_MRCR_RCB6_Pos))
|
||||
#define MATRIX_MRCR_RCB8_Pos _U_(8) /**< (MATRIX_MRCR) Remap Command Bit for Master 8 Position */
|
||||
#define MATRIX_MRCR_RCB8_Msk (_U_(0x1) << MATRIX_MRCR_RCB8_Pos) /**< (MATRIX_MRCR) Remap Command Bit for Master 8 Mask */
|
||||
#define MATRIX_MRCR_RCB8(value) (MATRIX_MRCR_RCB8_Msk & ((value) << MATRIX_MRCR_RCB8_Pos))
|
||||
#define MATRIX_MRCR_RCB9_Pos _U_(9) /**< (MATRIX_MRCR) Remap Command Bit for Master 9 Position */
|
||||
#define MATRIX_MRCR_RCB9_Msk (_U_(0x1) << MATRIX_MRCR_RCB9_Pos) /**< (MATRIX_MRCR) Remap Command Bit for Master 9 Mask */
|
||||
#define MATRIX_MRCR_RCB9(value) (MATRIX_MRCR_RCB9_Msk & ((value) << MATRIX_MRCR_RCB9_Pos))
|
||||
#define MATRIX_MRCR_RCB10_Pos _U_(10) /**< (MATRIX_MRCR) Remap Command Bit for Master 10 Position */
|
||||
#define MATRIX_MRCR_RCB10_Msk (_U_(0x1) << MATRIX_MRCR_RCB10_Pos) /**< (MATRIX_MRCR) Remap Command Bit for Master 10 Mask */
|
||||
#define MATRIX_MRCR_RCB10(value) (MATRIX_MRCR_RCB10_Msk & ((value) << MATRIX_MRCR_RCB10_Pos))
|
||||
#define MATRIX_MRCR_RCB11_Pos _U_(11) /**< (MATRIX_MRCR) Remap Command Bit for Master 11 Position */
|
||||
#define MATRIX_MRCR_RCB11_Msk (_U_(0x1) << MATRIX_MRCR_RCB11_Pos) /**< (MATRIX_MRCR) Remap Command Bit for Master 11 Mask */
|
||||
#define MATRIX_MRCR_RCB11(value) (MATRIX_MRCR_RCB11_Msk & ((value) << MATRIX_MRCR_RCB11_Pos))
|
||||
#define MATRIX_MRCR_Msk _U_(0x00000F7F) /**< (MATRIX_MRCR) Register Mask */
|
||||
|
||||
#define MATRIX_MRCR_RCB_Pos _U_(0) /**< (MATRIX_MRCR Position) Remap Command Bit for Master xx */
|
||||
#define MATRIX_MRCR_RCB_Msk (_U_(0x7FF) << MATRIX_MRCR_RCB_Pos) /**< (MATRIX_MRCR Mask) RCB */
|
||||
#define MATRIX_MRCR_RCB(value) (MATRIX_MRCR_RCB_Msk & ((value) << MATRIX_MRCR_RCB_Pos))
|
||||
|
||||
/* -------- CCFG_CAN0 : (MATRIX Offset: 0x110) (R/W 32) CAN0 Configuration Register -------- */
|
||||
#define CCFG_CAN0_CAN0DMABA_Pos _U_(16) /**< (CCFG_CAN0) CAN0 DMA Base Address Position */
|
||||
#define CCFG_CAN0_CAN0DMABA_Msk (_U_(0xFFFF) << CCFG_CAN0_CAN0DMABA_Pos) /**< (CCFG_CAN0) CAN0 DMA Base Address Mask */
|
||||
#define CCFG_CAN0_CAN0DMABA(value) (CCFG_CAN0_CAN0DMABA_Msk & ((value) << CCFG_CAN0_CAN0DMABA_Pos))
|
||||
#define CCFG_CAN0_Msk _U_(0xFFFF0000) /**< (CCFG_CAN0) Register Mask */
|
||||
|
||||
|
||||
/* -------- CCFG_SYSIO : (MATRIX Offset: 0x114) (R/W 32) System I/O and CAN1 Configuration Register -------- */
|
||||
#define CCFG_SYSIO_SYSIO4_Pos _U_(4) /**< (CCFG_SYSIO) PB4 or TDI Assignment Position */
|
||||
#define CCFG_SYSIO_SYSIO4_Msk (_U_(0x1) << CCFG_SYSIO_SYSIO4_Pos) /**< (CCFG_SYSIO) PB4 or TDI Assignment Mask */
|
||||
#define CCFG_SYSIO_SYSIO4(value) (CCFG_SYSIO_SYSIO4_Msk & ((value) << CCFG_SYSIO_SYSIO4_Pos))
|
||||
#define CCFG_SYSIO_SYSIO5_Pos _U_(5) /**< (CCFG_SYSIO) PB5 or TDO/TRACESWO Assignment Position */
|
||||
#define CCFG_SYSIO_SYSIO5_Msk (_U_(0x1) << CCFG_SYSIO_SYSIO5_Pos) /**< (CCFG_SYSIO) PB5 or TDO/TRACESWO Assignment Mask */
|
||||
#define CCFG_SYSIO_SYSIO5(value) (CCFG_SYSIO_SYSIO5_Msk & ((value) << CCFG_SYSIO_SYSIO5_Pos))
|
||||
#define CCFG_SYSIO_SYSIO6_Pos _U_(6) /**< (CCFG_SYSIO) PB6 or TMS/SWDIO Assignment Position */
|
||||
#define CCFG_SYSIO_SYSIO6_Msk (_U_(0x1) << CCFG_SYSIO_SYSIO6_Pos) /**< (CCFG_SYSIO) PB6 or TMS/SWDIO Assignment Mask */
|
||||
#define CCFG_SYSIO_SYSIO6(value) (CCFG_SYSIO_SYSIO6_Msk & ((value) << CCFG_SYSIO_SYSIO6_Pos))
|
||||
#define CCFG_SYSIO_SYSIO7_Pos _U_(7) /**< (CCFG_SYSIO) PB7 or TCK/SWCLK Assignment Position */
|
||||
#define CCFG_SYSIO_SYSIO7_Msk (_U_(0x1) << CCFG_SYSIO_SYSIO7_Pos) /**< (CCFG_SYSIO) PB7 or TCK/SWCLK Assignment Mask */
|
||||
#define CCFG_SYSIO_SYSIO7(value) (CCFG_SYSIO_SYSIO7_Msk & ((value) << CCFG_SYSIO_SYSIO7_Pos))
|
||||
#define CCFG_SYSIO_SYSIO12_Pos _U_(12) /**< (CCFG_SYSIO) PB12 or ERASE Assignment Position */
|
||||
#define CCFG_SYSIO_SYSIO12_Msk (_U_(0x1) << CCFG_SYSIO_SYSIO12_Pos) /**< (CCFG_SYSIO) PB12 or ERASE Assignment Mask */
|
||||
#define CCFG_SYSIO_SYSIO12(value) (CCFG_SYSIO_SYSIO12_Msk & ((value) << CCFG_SYSIO_SYSIO12_Pos))
|
||||
#define CCFG_SYSIO_CAN1DMABA_Pos _U_(16) /**< (CCFG_SYSIO) CAN1 DMA Base Address Position */
|
||||
#define CCFG_SYSIO_CAN1DMABA_Msk (_U_(0xFFFF) << CCFG_SYSIO_CAN1DMABA_Pos) /**< (CCFG_SYSIO) CAN1 DMA Base Address Mask */
|
||||
#define CCFG_SYSIO_CAN1DMABA(value) (CCFG_SYSIO_CAN1DMABA_Msk & ((value) << CCFG_SYSIO_CAN1DMABA_Pos))
|
||||
#define CCFG_SYSIO_Msk _U_(0xFFFF10F0) /**< (CCFG_SYSIO) Register Mask */
|
||||
|
||||
#define CCFG_SYSIO_SYSIO_Pos _U_(4) /**< (CCFG_SYSIO Position) PB4 or TDI Assignment */
|
||||
#define CCFG_SYSIO_SYSIO_Msk (_U_(0x1F) << CCFG_SYSIO_SYSIO_Pos) /**< (CCFG_SYSIO Mask) SYSIO */
|
||||
#define CCFG_SYSIO_SYSIO(value) (CCFG_SYSIO_SYSIO_Msk & ((value) << CCFG_SYSIO_SYSIO_Pos))
|
||||
|
||||
/* -------- CCFG_SMCNFCS : (MATRIX Offset: 0x124) (R/W 32) SMC NAND Flash Chip Select Configuration Register -------- */
|
||||
#define CCFG_SMCNFCS_SMC_NFCS0_Pos _U_(0) /**< (CCFG_SMCNFCS) SMC NAND Flash Chip Select 0 Assignment Position */
|
||||
#define CCFG_SMCNFCS_SMC_NFCS0_Msk (_U_(0x1) << CCFG_SMCNFCS_SMC_NFCS0_Pos) /**< (CCFG_SMCNFCS) SMC NAND Flash Chip Select 0 Assignment Mask */
|
||||
#define CCFG_SMCNFCS_SMC_NFCS0(value) (CCFG_SMCNFCS_SMC_NFCS0_Msk & ((value) << CCFG_SMCNFCS_SMC_NFCS0_Pos))
|
||||
#define CCFG_SMCNFCS_SMC_NFCS1_Pos _U_(1) /**< (CCFG_SMCNFCS) SMC NAND Flash Chip Select 1 Assignment Position */
|
||||
#define CCFG_SMCNFCS_SMC_NFCS1_Msk (_U_(0x1) << CCFG_SMCNFCS_SMC_NFCS1_Pos) /**< (CCFG_SMCNFCS) SMC NAND Flash Chip Select 1 Assignment Mask */
|
||||
#define CCFG_SMCNFCS_SMC_NFCS1(value) (CCFG_SMCNFCS_SMC_NFCS1_Msk & ((value) << CCFG_SMCNFCS_SMC_NFCS1_Pos))
|
||||
#define CCFG_SMCNFCS_SMC_NFCS2_Pos _U_(2) /**< (CCFG_SMCNFCS) SMC NAND Flash Chip Select 2 Assignment Position */
|
||||
#define CCFG_SMCNFCS_SMC_NFCS2_Msk (_U_(0x1) << CCFG_SMCNFCS_SMC_NFCS2_Pos) /**< (CCFG_SMCNFCS) SMC NAND Flash Chip Select 2 Assignment Mask */
|
||||
#define CCFG_SMCNFCS_SMC_NFCS2(value) (CCFG_SMCNFCS_SMC_NFCS2_Msk & ((value) << CCFG_SMCNFCS_SMC_NFCS2_Pos))
|
||||
#define CCFG_SMCNFCS_SMC_NFCS3_Pos _U_(3) /**< (CCFG_SMCNFCS) SMC NAND Flash Chip Select 3 Assignment Position */
|
||||
#define CCFG_SMCNFCS_SMC_NFCS3_Msk (_U_(0x1) << CCFG_SMCNFCS_SMC_NFCS3_Pos) /**< (CCFG_SMCNFCS) SMC NAND Flash Chip Select 3 Assignment Mask */
|
||||
#define CCFG_SMCNFCS_SMC_NFCS3(value) (CCFG_SMCNFCS_SMC_NFCS3_Msk & ((value) << CCFG_SMCNFCS_SMC_NFCS3_Pos))
|
||||
#define CCFG_SMCNFCS_SDRAMEN_Pos _U_(4) /**< (CCFG_SMCNFCS) SDRAM Enable Position */
|
||||
#define CCFG_SMCNFCS_SDRAMEN_Msk (_U_(0x1) << CCFG_SMCNFCS_SDRAMEN_Pos) /**< (CCFG_SMCNFCS) SDRAM Enable Mask */
|
||||
#define CCFG_SMCNFCS_SDRAMEN(value) (CCFG_SMCNFCS_SDRAMEN_Msk & ((value) << CCFG_SMCNFCS_SDRAMEN_Pos))
|
||||
#define CCFG_SMCNFCS_Msk _U_(0x0000001F) /**< (CCFG_SMCNFCS) Register Mask */
|
||||
|
||||
#define CCFG_SMCNFCS_SMC_NFCS_Pos _U_(0) /**< (CCFG_SMCNFCS Position) SMC NAND Flash Chip Select x Assignment */
|
||||
#define CCFG_SMCNFCS_SMC_NFCS_Msk (_U_(0xF) << CCFG_SMCNFCS_SMC_NFCS_Pos) /**< (CCFG_SMCNFCS Mask) SMC_NFCS */
|
||||
#define CCFG_SMCNFCS_SMC_NFCS(value) (CCFG_SMCNFCS_SMC_NFCS_Msk & ((value) << CCFG_SMCNFCS_SMC_NFCS_Pos))
|
||||
|
||||
/* -------- MATRIX_WPMR : (MATRIX Offset: 0x1E4) (R/W 32) Write Protection Mode Register -------- */
|
||||
#define MATRIX_WPMR_WPEN_Pos _U_(0) /**< (MATRIX_WPMR) Write Protection Enable Position */
|
||||
#define MATRIX_WPMR_WPEN_Msk (_U_(0x1) << MATRIX_WPMR_WPEN_Pos) /**< (MATRIX_WPMR) Write Protection Enable Mask */
|
||||
#define MATRIX_WPMR_WPEN(value) (MATRIX_WPMR_WPEN_Msk & ((value) << MATRIX_WPMR_WPEN_Pos))
|
||||
#define MATRIX_WPMR_WPKEY_Pos _U_(8) /**< (MATRIX_WPMR) Write Protection Key Position */
|
||||
#define MATRIX_WPMR_WPKEY_Msk (_U_(0xFFFFFF) << MATRIX_WPMR_WPKEY_Pos) /**< (MATRIX_WPMR) Write Protection Key Mask */
|
||||
#define MATRIX_WPMR_WPKEY(value) (MATRIX_WPMR_WPKEY_Msk & ((value) << MATRIX_WPMR_WPKEY_Pos))
|
||||
#define MATRIX_WPMR_WPKEY_PASSWD_Val _U_(0x4D4154) /**< (MATRIX_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. */
|
||||
#define MATRIX_WPMR_WPKEY_PASSWD (MATRIX_WPMR_WPKEY_PASSWD_Val << MATRIX_WPMR_WPKEY_Pos) /**< (MATRIX_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. Position */
|
||||
#define MATRIX_WPMR_Msk _U_(0xFFFFFF01) /**< (MATRIX_WPMR) Register Mask */
|
||||
|
||||
|
||||
/* -------- MATRIX_WPSR : (MATRIX Offset: 0x1E8) ( R/ 32) Write Protection Status Register -------- */
|
||||
#define MATRIX_WPSR_WPVS_Pos _U_(0) /**< (MATRIX_WPSR) Write Protection Violation Status Position */
|
||||
#define MATRIX_WPSR_WPVS_Msk (_U_(0x1) << MATRIX_WPSR_WPVS_Pos) /**< (MATRIX_WPSR) Write Protection Violation Status Mask */
|
||||
#define MATRIX_WPSR_WPVS(value) (MATRIX_WPSR_WPVS_Msk & ((value) << MATRIX_WPSR_WPVS_Pos))
|
||||
#define MATRIX_WPSR_WPVSRC_Pos _U_(8) /**< (MATRIX_WPSR) Write Protection Violation Source Position */
|
||||
#define MATRIX_WPSR_WPVSRC_Msk (_U_(0xFFFF) << MATRIX_WPSR_WPVSRC_Pos) /**< (MATRIX_WPSR) Write Protection Violation Source Mask */
|
||||
#define MATRIX_WPSR_WPVSRC(value) (MATRIX_WPSR_WPVSRC_Msk & ((value) << MATRIX_WPSR_WPVSRC_Pos))
|
||||
#define MATRIX_WPSR_Msk _U_(0x00FFFF01) /**< (MATRIX_WPSR) Register Mask */
|
||||
|
||||
|
||||
/** \brief MATRIX register offsets definitions */
|
||||
#define MATRIX_PRAS_REG_OFST (0x00) /**< (MATRIX_PRAS) Priority Register A for Slave 0 Offset */
|
||||
#define MATRIX_PRBS_REG_OFST (0x04) /**< (MATRIX_PRBS) Priority Register B for Slave 0 Offset */
|
||||
#define MATRIX_MCFG_REG_OFST (0x00) /**< (MATRIX_MCFG) Master Configuration Register 0 Offset */
|
||||
#define MATRIX_SCFG_REG_OFST (0x40) /**< (MATRIX_SCFG) Slave Configuration Register 0 Offset */
|
||||
#define MATRIX_MRCR_REG_OFST (0x100) /**< (MATRIX_MRCR) Master Remap Control Register Offset */
|
||||
#define CCFG_CAN0_REG_OFST (0x110) /**< (CCFG_CAN0) CAN0 Configuration Register Offset */
|
||||
#define CCFG_SYSIO_REG_OFST (0x114) /**< (CCFG_SYSIO) System I/O and CAN1 Configuration Register Offset */
|
||||
#define CCFG_SMCNFCS_REG_OFST (0x124) /**< (CCFG_SMCNFCS) SMC NAND Flash Chip Select Configuration Register Offset */
|
||||
#define MATRIX_WPMR_REG_OFST (0x1E4) /**< (MATRIX_WPMR) Write Protection Mode Register Offset */
|
||||
#define MATRIX_WPSR_REG_OFST (0x1E8) /**< (MATRIX_WPSR) Write Protection Status Register Offset */
|
||||
|
||||
#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
/** \brief MATRIX_PR register API structure */
|
||||
typedef struct
|
||||
{
|
||||
__IO uint32_t MATRIX_PRAS; /**< Offset: 0x00 (R/W 32) Priority Register A for Slave 0 */
|
||||
__IO uint32_t MATRIX_PRBS; /**< Offset: 0x04 (R/W 32) Priority Register B for Slave 0 */
|
||||
} matrix_pr_registers_t;
|
||||
|
||||
#define MATRIX_PR_NUMBER _U_(9)
|
||||
|
||||
/** \brief MATRIX register API structure */
|
||||
typedef struct
|
||||
{
|
||||
__IO uint32_t MATRIX_MCFG[12]; /**< Offset: 0x00 (R/W 32) Master Configuration Register 0 */
|
||||
__I uint8_t Reserved1[0x10];
|
||||
__IO uint32_t MATRIX_SCFG[9]; /**< Offset: 0x40 (R/W 32) Slave Configuration Register 0 */
|
||||
__I uint8_t Reserved2[0x1C];
|
||||
matrix_pr_registers_t MATRIX_PR[MATRIX_PR_NUMBER]; /**< Offset: 0x80 Priority Register A for Slave 0 */
|
||||
__I uint8_t Reserved3[0x38];
|
||||
__IO uint32_t MATRIX_MRCR; /**< Offset: 0x100 (R/W 32) Master Remap Control Register */
|
||||
__I uint8_t Reserved4[0x0C];
|
||||
__IO uint32_t CCFG_CAN0; /**< Offset: 0x110 (R/W 32) CAN0 Configuration Register */
|
||||
__IO uint32_t CCFG_SYSIO; /**< Offset: 0x114 (R/W 32) System I/O and CAN1 Configuration Register */
|
||||
__I uint8_t Reserved5[0x0C];
|
||||
__IO uint32_t CCFG_SMCNFCS; /**< Offset: 0x124 (R/W 32) SMC NAND Flash Chip Select Configuration Register */
|
||||
__I uint8_t Reserved6[0xBC];
|
||||
__IO uint32_t MATRIX_WPMR; /**< Offset: 0x1E4 (R/W 32) Write Protection Mode Register */
|
||||
__I uint32_t MATRIX_WPSR; /**< Offset: 0x1E8 (R/ 32) Write Protection Status Register */
|
||||
} matrix_registers_t;
|
||||
|
||||
|
||||
#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
#endif /* _SAME70_MATRIX_COMPONENT_H_ */
|
||||
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Reference in New Issue