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121 lines
9.7 KiB
C
121 lines
9.7 KiB
C
/**
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* \brief Component description for RAMECC
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*
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* Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries.
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*
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* Subject to your compliance with these terms, you may use Microchip software and any derivatives
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* exclusively with Microchip products. It is your responsibility to comply with third party license
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* terms applicable to your use of third party software (including open source software) that may
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* accompany Microchip software.
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*
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* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY,
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* APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND
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* FITNESS FOR A PARTICULAR PURPOSE.
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*
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* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
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* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF
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* MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
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* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT
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* EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
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*
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*/
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/* file generated from device description version 2020-03-12T17:27:04Z */
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#ifndef _SAME54_RAMECC_COMPONENT_H_
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#define _SAME54_RAMECC_COMPONENT_H_
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/* ************************************************************************** */
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/* SOFTWARE API DEFINITION FOR RAMECC */
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/* ************************************************************************** */
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/* -------- RAMECC_INTENCLR : (RAMECC Offset: 0x00) (R/W 8) Interrupt Enable Clear -------- */
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#define RAMECC_INTENCLR_RESETVALUE _U_(0x00) /**< (RAMECC_INTENCLR) Interrupt Enable Clear Reset Value */
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#define RAMECC_INTENCLR_SINGLEE_Pos _U_(0) /**< (RAMECC_INTENCLR) Single Bit ECC Error Interrupt Enable Clear Position */
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#define RAMECC_INTENCLR_SINGLEE_Msk (_U_(0x1) << RAMECC_INTENCLR_SINGLEE_Pos) /**< (RAMECC_INTENCLR) Single Bit ECC Error Interrupt Enable Clear Mask */
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#define RAMECC_INTENCLR_SINGLEE(value) (RAMECC_INTENCLR_SINGLEE_Msk & ((value) << RAMECC_INTENCLR_SINGLEE_Pos))
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#define RAMECC_INTENCLR_DUALE_Pos _U_(1) /**< (RAMECC_INTENCLR) Dual Bit ECC Error Interrupt Enable Clear Position */
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#define RAMECC_INTENCLR_DUALE_Msk (_U_(0x1) << RAMECC_INTENCLR_DUALE_Pos) /**< (RAMECC_INTENCLR) Dual Bit ECC Error Interrupt Enable Clear Mask */
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#define RAMECC_INTENCLR_DUALE(value) (RAMECC_INTENCLR_DUALE_Msk & ((value) << RAMECC_INTENCLR_DUALE_Pos))
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#define RAMECC_INTENCLR_Msk _U_(0x03) /**< (RAMECC_INTENCLR) Register Mask */
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/* -------- RAMECC_INTENSET : (RAMECC Offset: 0x01) (R/W 8) Interrupt Enable Set -------- */
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#define RAMECC_INTENSET_RESETVALUE _U_(0x00) /**< (RAMECC_INTENSET) Interrupt Enable Set Reset Value */
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#define RAMECC_INTENSET_SINGLEE_Pos _U_(0) /**< (RAMECC_INTENSET) Single Bit ECC Error Interrupt Enable Set Position */
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#define RAMECC_INTENSET_SINGLEE_Msk (_U_(0x1) << RAMECC_INTENSET_SINGLEE_Pos) /**< (RAMECC_INTENSET) Single Bit ECC Error Interrupt Enable Set Mask */
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#define RAMECC_INTENSET_SINGLEE(value) (RAMECC_INTENSET_SINGLEE_Msk & ((value) << RAMECC_INTENSET_SINGLEE_Pos))
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#define RAMECC_INTENSET_DUALE_Pos _U_(1) /**< (RAMECC_INTENSET) Dual Bit ECC Error Interrupt Enable Set Position */
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#define RAMECC_INTENSET_DUALE_Msk (_U_(0x1) << RAMECC_INTENSET_DUALE_Pos) /**< (RAMECC_INTENSET) Dual Bit ECC Error Interrupt Enable Set Mask */
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#define RAMECC_INTENSET_DUALE(value) (RAMECC_INTENSET_DUALE_Msk & ((value) << RAMECC_INTENSET_DUALE_Pos))
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#define RAMECC_INTENSET_Msk _U_(0x03) /**< (RAMECC_INTENSET) Register Mask */
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/* -------- RAMECC_INTFLAG : (RAMECC Offset: 0x02) (R/W 8) Interrupt Flag -------- */
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#define RAMECC_INTFLAG_RESETVALUE _U_(0x00) /**< (RAMECC_INTFLAG) Interrupt Flag Reset Value */
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#define RAMECC_INTFLAG_SINGLEE_Pos _U_(0) /**< (RAMECC_INTFLAG) Single Bit ECC Error Interrupt Position */
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#define RAMECC_INTFLAG_SINGLEE_Msk (_U_(0x1) << RAMECC_INTFLAG_SINGLEE_Pos) /**< (RAMECC_INTFLAG) Single Bit ECC Error Interrupt Mask */
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#define RAMECC_INTFLAG_SINGLEE(value) (RAMECC_INTFLAG_SINGLEE_Msk & ((value) << RAMECC_INTFLAG_SINGLEE_Pos))
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#define RAMECC_INTFLAG_DUALE_Pos _U_(1) /**< (RAMECC_INTFLAG) Dual Bit ECC Error Interrupt Position */
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#define RAMECC_INTFLAG_DUALE_Msk (_U_(0x1) << RAMECC_INTFLAG_DUALE_Pos) /**< (RAMECC_INTFLAG) Dual Bit ECC Error Interrupt Mask */
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#define RAMECC_INTFLAG_DUALE(value) (RAMECC_INTFLAG_DUALE_Msk & ((value) << RAMECC_INTFLAG_DUALE_Pos))
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#define RAMECC_INTFLAG_Msk _U_(0x03) /**< (RAMECC_INTFLAG) Register Mask */
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/* -------- RAMECC_STATUS : (RAMECC Offset: 0x03) ( R/ 8) Status -------- */
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#define RAMECC_STATUS_RESETVALUE _U_(0x00) /**< (RAMECC_STATUS) Status Reset Value */
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#define RAMECC_STATUS_ECCDIS_Pos _U_(0) /**< (RAMECC_STATUS) ECC Disable Position */
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#define RAMECC_STATUS_ECCDIS_Msk (_U_(0x1) << RAMECC_STATUS_ECCDIS_Pos) /**< (RAMECC_STATUS) ECC Disable Mask */
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#define RAMECC_STATUS_ECCDIS(value) (RAMECC_STATUS_ECCDIS_Msk & ((value) << RAMECC_STATUS_ECCDIS_Pos))
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#define RAMECC_STATUS_Msk _U_(0x01) /**< (RAMECC_STATUS) Register Mask */
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/* -------- RAMECC_ERRADDR : (RAMECC Offset: 0x04) ( R/ 32) Error Address -------- */
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#define RAMECC_ERRADDR_RESETVALUE _U_(0x00) /**< (RAMECC_ERRADDR) Error Address Reset Value */
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#define RAMECC_ERRADDR_ERRADDR_Pos _U_(0) /**< (RAMECC_ERRADDR) Error Address Position */
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#define RAMECC_ERRADDR_ERRADDR_Msk (_U_(0x1FFFF) << RAMECC_ERRADDR_ERRADDR_Pos) /**< (RAMECC_ERRADDR) Error Address Mask */
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#define RAMECC_ERRADDR_ERRADDR(value) (RAMECC_ERRADDR_ERRADDR_Msk & ((value) << RAMECC_ERRADDR_ERRADDR_Pos))
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#define RAMECC_ERRADDR_Msk _U_(0x0001FFFF) /**< (RAMECC_ERRADDR) Register Mask */
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/* -------- RAMECC_DBGCTRL : (RAMECC Offset: 0x0F) (R/W 8) Debug Control -------- */
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#define RAMECC_DBGCTRL_RESETVALUE _U_(0x00) /**< (RAMECC_DBGCTRL) Debug Control Reset Value */
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#define RAMECC_DBGCTRL_ECCDIS_Pos _U_(0) /**< (RAMECC_DBGCTRL) ECC Disable Position */
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#define RAMECC_DBGCTRL_ECCDIS_Msk (_U_(0x1) << RAMECC_DBGCTRL_ECCDIS_Pos) /**< (RAMECC_DBGCTRL) ECC Disable Mask */
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#define RAMECC_DBGCTRL_ECCDIS(value) (RAMECC_DBGCTRL_ECCDIS_Msk & ((value) << RAMECC_DBGCTRL_ECCDIS_Pos))
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#define RAMECC_DBGCTRL_ECCELOG_Pos _U_(1) /**< (RAMECC_DBGCTRL) ECC Error Log Position */
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#define RAMECC_DBGCTRL_ECCELOG_Msk (_U_(0x1) << RAMECC_DBGCTRL_ECCELOG_Pos) /**< (RAMECC_DBGCTRL) ECC Error Log Mask */
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#define RAMECC_DBGCTRL_ECCELOG(value) (RAMECC_DBGCTRL_ECCELOG_Msk & ((value) << RAMECC_DBGCTRL_ECCELOG_Pos))
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#define RAMECC_DBGCTRL_Msk _U_(0x03) /**< (RAMECC_DBGCTRL) Register Mask */
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/** \brief RAMECC register offsets definitions */
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#define RAMECC_INTENCLR_REG_OFST (0x00) /**< (RAMECC_INTENCLR) Interrupt Enable Clear Offset */
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#define RAMECC_INTENSET_REG_OFST (0x01) /**< (RAMECC_INTENSET) Interrupt Enable Set Offset */
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#define RAMECC_INTFLAG_REG_OFST (0x02) /**< (RAMECC_INTFLAG) Interrupt Flag Offset */
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#define RAMECC_STATUS_REG_OFST (0x03) /**< (RAMECC_STATUS) Status Offset */
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#define RAMECC_ERRADDR_REG_OFST (0x04) /**< (RAMECC_ERRADDR) Error Address Offset */
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#define RAMECC_DBGCTRL_REG_OFST (0x0F) /**< (RAMECC_DBGCTRL) Debug Control Offset */
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#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
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/** \brief RAMECC register API structure */
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typedef struct
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{ /* RAM ECC */
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__IO uint8_t RAMECC_INTENCLR; /**< Offset: 0x00 (R/W 8) Interrupt Enable Clear */
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__IO uint8_t RAMECC_INTENSET; /**< Offset: 0x01 (R/W 8) Interrupt Enable Set */
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__IO uint8_t RAMECC_INTFLAG; /**< Offset: 0x02 (R/W 8) Interrupt Flag */
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__I uint8_t RAMECC_STATUS; /**< Offset: 0x03 (R/ 8) Status */
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__I uint32_t RAMECC_ERRADDR; /**< Offset: 0x04 (R/ 32) Error Address */
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__I uint8_t Reserved1[0x07];
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__IO uint8_t RAMECC_DBGCTRL; /**< Offset: 0x0F (R/W 8) Debug Control */
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} ramecc_registers_t;
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#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
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#endif /* _SAME54_RAMECC_COMPONENT_H_ */
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