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277 lines
27 KiB
C
277 lines
27 KiB
C
/**
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* \brief Component description for AES
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*
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* Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries.
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*
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* Subject to your compliance with these terms, you may use Microchip software and any derivatives
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* exclusively with Microchip products. It is your responsibility to comply with third party license
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* terms applicable to your use of third party software (including open source software) that may
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* accompany Microchip software.
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*
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* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY,
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* APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND
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* FITNESS FOR A PARTICULAR PURPOSE.
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*
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* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
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* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF
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* MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
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* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT
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* EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
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*
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*/
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/* file generated from device description version 2020-03-12T17:27:04Z */
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#ifndef _SAME54_AES_COMPONENT_H_
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#define _SAME54_AES_COMPONENT_H_
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/* ************************************************************************** */
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/* SOFTWARE API DEFINITION FOR AES */
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/* ************************************************************************** */
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/* -------- AES_CTRLA : (AES Offset: 0x00) (R/W 32) Control A -------- */
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#define AES_CTRLA_RESETVALUE _U_(0x00) /**< (AES_CTRLA) Control A Reset Value */
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#define AES_CTRLA_SWRST_Pos _U_(0) /**< (AES_CTRLA) Software Reset Position */
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#define AES_CTRLA_SWRST_Msk (_U_(0x1) << AES_CTRLA_SWRST_Pos) /**< (AES_CTRLA) Software Reset Mask */
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#define AES_CTRLA_SWRST(value) (AES_CTRLA_SWRST_Msk & ((value) << AES_CTRLA_SWRST_Pos))
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#define AES_CTRLA_ENABLE_Pos _U_(1) /**< (AES_CTRLA) Enable Position */
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#define AES_CTRLA_ENABLE_Msk (_U_(0x1) << AES_CTRLA_ENABLE_Pos) /**< (AES_CTRLA) Enable Mask */
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#define AES_CTRLA_ENABLE(value) (AES_CTRLA_ENABLE_Msk & ((value) << AES_CTRLA_ENABLE_Pos))
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#define AES_CTRLA_AESMODE_Pos _U_(2) /**< (AES_CTRLA) AES Modes of operation Position */
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#define AES_CTRLA_AESMODE_Msk (_U_(0x7) << AES_CTRLA_AESMODE_Pos) /**< (AES_CTRLA) AES Modes of operation Mask */
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#define AES_CTRLA_AESMODE(value) (AES_CTRLA_AESMODE_Msk & ((value) << AES_CTRLA_AESMODE_Pos))
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#define AES_CTRLA_AESMODE_ECB_Val _U_(0x0) /**< (AES_CTRLA) Electronic code book mode */
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#define AES_CTRLA_AESMODE_CBC_Val _U_(0x1) /**< (AES_CTRLA) Cipher block chaining mode */
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#define AES_CTRLA_AESMODE_OFB_Val _U_(0x2) /**< (AES_CTRLA) Output feedback mode */
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#define AES_CTRLA_AESMODE_CFB_Val _U_(0x3) /**< (AES_CTRLA) Cipher feedback mode */
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#define AES_CTRLA_AESMODE_COUNTER_Val _U_(0x4) /**< (AES_CTRLA) Counter mode */
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#define AES_CTRLA_AESMODE_CCM_Val _U_(0x5) /**< (AES_CTRLA) CCM mode */
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#define AES_CTRLA_AESMODE_GCM_Val _U_(0x6) /**< (AES_CTRLA) Galois counter mode */
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#define AES_CTRLA_AESMODE_ECB (AES_CTRLA_AESMODE_ECB_Val << AES_CTRLA_AESMODE_Pos) /**< (AES_CTRLA) Electronic code book mode Position */
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#define AES_CTRLA_AESMODE_CBC (AES_CTRLA_AESMODE_CBC_Val << AES_CTRLA_AESMODE_Pos) /**< (AES_CTRLA) Cipher block chaining mode Position */
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#define AES_CTRLA_AESMODE_OFB (AES_CTRLA_AESMODE_OFB_Val << AES_CTRLA_AESMODE_Pos) /**< (AES_CTRLA) Output feedback mode Position */
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#define AES_CTRLA_AESMODE_CFB (AES_CTRLA_AESMODE_CFB_Val << AES_CTRLA_AESMODE_Pos) /**< (AES_CTRLA) Cipher feedback mode Position */
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#define AES_CTRLA_AESMODE_COUNTER (AES_CTRLA_AESMODE_COUNTER_Val << AES_CTRLA_AESMODE_Pos) /**< (AES_CTRLA) Counter mode Position */
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#define AES_CTRLA_AESMODE_CCM (AES_CTRLA_AESMODE_CCM_Val << AES_CTRLA_AESMODE_Pos) /**< (AES_CTRLA) CCM mode Position */
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#define AES_CTRLA_AESMODE_GCM (AES_CTRLA_AESMODE_GCM_Val << AES_CTRLA_AESMODE_Pos) /**< (AES_CTRLA) Galois counter mode Position */
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#define AES_CTRLA_CFBS_Pos _U_(5) /**< (AES_CTRLA) Cipher Feedback Block Size Position */
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#define AES_CTRLA_CFBS_Msk (_U_(0x7) << AES_CTRLA_CFBS_Pos) /**< (AES_CTRLA) Cipher Feedback Block Size Mask */
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#define AES_CTRLA_CFBS(value) (AES_CTRLA_CFBS_Msk & ((value) << AES_CTRLA_CFBS_Pos))
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#define AES_CTRLA_CFBS_128BIT_Val _U_(0x0) /**< (AES_CTRLA) 128-bit Input data block for Encryption/Decryption in Cipher Feedback mode */
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#define AES_CTRLA_CFBS_64BIT_Val _U_(0x1) /**< (AES_CTRLA) 64-bit Input data block for Encryption/Decryption in Cipher Feedback mode */
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#define AES_CTRLA_CFBS_32BIT_Val _U_(0x2) /**< (AES_CTRLA) 32-bit Input data block for Encryption/Decryption in Cipher Feedback mode */
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#define AES_CTRLA_CFBS_16BIT_Val _U_(0x3) /**< (AES_CTRLA) 16-bit Input data block for Encryption/Decryption in Cipher Feedback mode */
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#define AES_CTRLA_CFBS_8BIT_Val _U_(0x4) /**< (AES_CTRLA) 8-bit Input data block for Encryption/Decryption in Cipher Feedback mode */
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#define AES_CTRLA_CFBS_128BIT (AES_CTRLA_CFBS_128BIT_Val << AES_CTRLA_CFBS_Pos) /**< (AES_CTRLA) 128-bit Input data block for Encryption/Decryption in Cipher Feedback mode Position */
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#define AES_CTRLA_CFBS_64BIT (AES_CTRLA_CFBS_64BIT_Val << AES_CTRLA_CFBS_Pos) /**< (AES_CTRLA) 64-bit Input data block for Encryption/Decryption in Cipher Feedback mode Position */
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#define AES_CTRLA_CFBS_32BIT (AES_CTRLA_CFBS_32BIT_Val << AES_CTRLA_CFBS_Pos) /**< (AES_CTRLA) 32-bit Input data block for Encryption/Decryption in Cipher Feedback mode Position */
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#define AES_CTRLA_CFBS_16BIT (AES_CTRLA_CFBS_16BIT_Val << AES_CTRLA_CFBS_Pos) /**< (AES_CTRLA) 16-bit Input data block for Encryption/Decryption in Cipher Feedback mode Position */
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#define AES_CTRLA_CFBS_8BIT (AES_CTRLA_CFBS_8BIT_Val << AES_CTRLA_CFBS_Pos) /**< (AES_CTRLA) 8-bit Input data block for Encryption/Decryption in Cipher Feedback mode Position */
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#define AES_CTRLA_KEYSIZE_Pos _U_(8) /**< (AES_CTRLA) Encryption Key Size Position */
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#define AES_CTRLA_KEYSIZE_Msk (_U_(0x3) << AES_CTRLA_KEYSIZE_Pos) /**< (AES_CTRLA) Encryption Key Size Mask */
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#define AES_CTRLA_KEYSIZE(value) (AES_CTRLA_KEYSIZE_Msk & ((value) << AES_CTRLA_KEYSIZE_Pos))
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#define AES_CTRLA_KEYSIZE_128BIT_Val _U_(0x0) /**< (AES_CTRLA) 128-bit Key for Encryption / Decryption */
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#define AES_CTRLA_KEYSIZE_192BIT_Val _U_(0x1) /**< (AES_CTRLA) 192-bit Key for Encryption / Decryption */
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#define AES_CTRLA_KEYSIZE_256BIT_Val _U_(0x2) /**< (AES_CTRLA) 256-bit Key for Encryption / Decryption */
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#define AES_CTRLA_KEYSIZE_128BIT (AES_CTRLA_KEYSIZE_128BIT_Val << AES_CTRLA_KEYSIZE_Pos) /**< (AES_CTRLA) 128-bit Key for Encryption / Decryption Position */
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#define AES_CTRLA_KEYSIZE_192BIT (AES_CTRLA_KEYSIZE_192BIT_Val << AES_CTRLA_KEYSIZE_Pos) /**< (AES_CTRLA) 192-bit Key for Encryption / Decryption Position */
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#define AES_CTRLA_KEYSIZE_256BIT (AES_CTRLA_KEYSIZE_256BIT_Val << AES_CTRLA_KEYSIZE_Pos) /**< (AES_CTRLA) 256-bit Key for Encryption / Decryption Position */
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#define AES_CTRLA_CIPHER_Pos _U_(10) /**< (AES_CTRLA) Cipher Mode Position */
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#define AES_CTRLA_CIPHER_Msk (_U_(0x1) << AES_CTRLA_CIPHER_Pos) /**< (AES_CTRLA) Cipher Mode Mask */
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#define AES_CTRLA_CIPHER(value) (AES_CTRLA_CIPHER_Msk & ((value) << AES_CTRLA_CIPHER_Pos))
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#define AES_CTRLA_CIPHER_DEC_Val _U_(0x0) /**< (AES_CTRLA) Decryption */
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#define AES_CTRLA_CIPHER_ENC_Val _U_(0x1) /**< (AES_CTRLA) Encryption */
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#define AES_CTRLA_CIPHER_DEC (AES_CTRLA_CIPHER_DEC_Val << AES_CTRLA_CIPHER_Pos) /**< (AES_CTRLA) Decryption Position */
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#define AES_CTRLA_CIPHER_ENC (AES_CTRLA_CIPHER_ENC_Val << AES_CTRLA_CIPHER_Pos) /**< (AES_CTRLA) Encryption Position */
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#define AES_CTRLA_STARTMODE_Pos _U_(11) /**< (AES_CTRLA) Start Mode Select Position */
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#define AES_CTRLA_STARTMODE_Msk (_U_(0x1) << AES_CTRLA_STARTMODE_Pos) /**< (AES_CTRLA) Start Mode Select Mask */
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#define AES_CTRLA_STARTMODE(value) (AES_CTRLA_STARTMODE_Msk & ((value) << AES_CTRLA_STARTMODE_Pos))
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#define AES_CTRLA_STARTMODE_MANUAL_Val _U_(0x0) /**< (AES_CTRLA) Start Encryption / Decryption in Manual mode */
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#define AES_CTRLA_STARTMODE_AUTO_Val _U_(0x1) /**< (AES_CTRLA) Start Encryption / Decryption in Auto mode */
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#define AES_CTRLA_STARTMODE_MANUAL (AES_CTRLA_STARTMODE_MANUAL_Val << AES_CTRLA_STARTMODE_Pos) /**< (AES_CTRLA) Start Encryption / Decryption in Manual mode Position */
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#define AES_CTRLA_STARTMODE_AUTO (AES_CTRLA_STARTMODE_AUTO_Val << AES_CTRLA_STARTMODE_Pos) /**< (AES_CTRLA) Start Encryption / Decryption in Auto mode Position */
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#define AES_CTRLA_LOD_Pos _U_(12) /**< (AES_CTRLA) Last Output Data Mode Position */
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#define AES_CTRLA_LOD_Msk (_U_(0x1) << AES_CTRLA_LOD_Pos) /**< (AES_CTRLA) Last Output Data Mode Mask */
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#define AES_CTRLA_LOD(value) (AES_CTRLA_LOD_Msk & ((value) << AES_CTRLA_LOD_Pos))
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#define AES_CTRLA_LOD_NONE_Val _U_(0x0) /**< (AES_CTRLA) No effect */
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#define AES_CTRLA_LOD_LAST_Val _U_(0x1) /**< (AES_CTRLA) Start encryption in Last Output Data mode */
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#define AES_CTRLA_LOD_NONE (AES_CTRLA_LOD_NONE_Val << AES_CTRLA_LOD_Pos) /**< (AES_CTRLA) No effect Position */
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#define AES_CTRLA_LOD_LAST (AES_CTRLA_LOD_LAST_Val << AES_CTRLA_LOD_Pos) /**< (AES_CTRLA) Start encryption in Last Output Data mode Position */
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#define AES_CTRLA_KEYGEN_Pos _U_(13) /**< (AES_CTRLA) Last Key Generation Position */
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#define AES_CTRLA_KEYGEN_Msk (_U_(0x1) << AES_CTRLA_KEYGEN_Pos) /**< (AES_CTRLA) Last Key Generation Mask */
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#define AES_CTRLA_KEYGEN(value) (AES_CTRLA_KEYGEN_Msk & ((value) << AES_CTRLA_KEYGEN_Pos))
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#define AES_CTRLA_KEYGEN_NONE_Val _U_(0x0) /**< (AES_CTRLA) No effect */
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#define AES_CTRLA_KEYGEN_LAST_Val _U_(0x1) /**< (AES_CTRLA) Start Computation of the last NK words of the expanded key */
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#define AES_CTRLA_KEYGEN_NONE (AES_CTRLA_KEYGEN_NONE_Val << AES_CTRLA_KEYGEN_Pos) /**< (AES_CTRLA) No effect Position */
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#define AES_CTRLA_KEYGEN_LAST (AES_CTRLA_KEYGEN_LAST_Val << AES_CTRLA_KEYGEN_Pos) /**< (AES_CTRLA) Start Computation of the last NK words of the expanded key Position */
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#define AES_CTRLA_XORKEY_Pos _U_(14) /**< (AES_CTRLA) XOR Key Operation Position */
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#define AES_CTRLA_XORKEY_Msk (_U_(0x1) << AES_CTRLA_XORKEY_Pos) /**< (AES_CTRLA) XOR Key Operation Mask */
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#define AES_CTRLA_XORKEY(value) (AES_CTRLA_XORKEY_Msk & ((value) << AES_CTRLA_XORKEY_Pos))
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#define AES_CTRLA_XORKEY_NONE_Val _U_(0x0) /**< (AES_CTRLA) No effect */
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#define AES_CTRLA_XORKEY_XOR_Val _U_(0x1) /**< (AES_CTRLA) The user keyword gets XORed with the previous keyword register content. */
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#define AES_CTRLA_XORKEY_NONE (AES_CTRLA_XORKEY_NONE_Val << AES_CTRLA_XORKEY_Pos) /**< (AES_CTRLA) No effect Position */
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#define AES_CTRLA_XORKEY_XOR (AES_CTRLA_XORKEY_XOR_Val << AES_CTRLA_XORKEY_Pos) /**< (AES_CTRLA) The user keyword gets XORed with the previous keyword register content. Position */
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#define AES_CTRLA_CTYPE_Pos _U_(16) /**< (AES_CTRLA) Counter Measure Type Position */
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#define AES_CTRLA_CTYPE_Msk (_U_(0xF) << AES_CTRLA_CTYPE_Pos) /**< (AES_CTRLA) Counter Measure Type Mask */
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#define AES_CTRLA_CTYPE(value) (AES_CTRLA_CTYPE_Msk & ((value) << AES_CTRLA_CTYPE_Pos))
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#define AES_CTRLA_Msk _U_(0x000F7FFF) /**< (AES_CTRLA) Register Mask */
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/* -------- AES_CTRLB : (AES Offset: 0x04) (R/W 8) Control B -------- */
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#define AES_CTRLB_RESETVALUE _U_(0x00) /**< (AES_CTRLB) Control B Reset Value */
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#define AES_CTRLB_START_Pos _U_(0) /**< (AES_CTRLB) Start Encryption/Decryption Position */
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#define AES_CTRLB_START_Msk (_U_(0x1) << AES_CTRLB_START_Pos) /**< (AES_CTRLB) Start Encryption/Decryption Mask */
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#define AES_CTRLB_START(value) (AES_CTRLB_START_Msk & ((value) << AES_CTRLB_START_Pos))
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#define AES_CTRLB_NEWMSG_Pos _U_(1) /**< (AES_CTRLB) New message Position */
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#define AES_CTRLB_NEWMSG_Msk (_U_(0x1) << AES_CTRLB_NEWMSG_Pos) /**< (AES_CTRLB) New message Mask */
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#define AES_CTRLB_NEWMSG(value) (AES_CTRLB_NEWMSG_Msk & ((value) << AES_CTRLB_NEWMSG_Pos))
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#define AES_CTRLB_EOM_Pos _U_(2) /**< (AES_CTRLB) End of message Position */
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#define AES_CTRLB_EOM_Msk (_U_(0x1) << AES_CTRLB_EOM_Pos) /**< (AES_CTRLB) End of message Mask */
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#define AES_CTRLB_EOM(value) (AES_CTRLB_EOM_Msk & ((value) << AES_CTRLB_EOM_Pos))
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#define AES_CTRLB_GFMUL_Pos _U_(3) /**< (AES_CTRLB) GF Multiplication Position */
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#define AES_CTRLB_GFMUL_Msk (_U_(0x1) << AES_CTRLB_GFMUL_Pos) /**< (AES_CTRLB) GF Multiplication Mask */
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#define AES_CTRLB_GFMUL(value) (AES_CTRLB_GFMUL_Msk & ((value) << AES_CTRLB_GFMUL_Pos))
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#define AES_CTRLB_Msk _U_(0x0F) /**< (AES_CTRLB) Register Mask */
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/* -------- AES_INTENCLR : (AES Offset: 0x05) (R/W 8) Interrupt Enable Clear -------- */
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#define AES_INTENCLR_RESETVALUE _U_(0x00) /**< (AES_INTENCLR) Interrupt Enable Clear Reset Value */
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#define AES_INTENCLR_ENCCMP_Pos _U_(0) /**< (AES_INTENCLR) Encryption Complete Interrupt Enable Position */
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#define AES_INTENCLR_ENCCMP_Msk (_U_(0x1) << AES_INTENCLR_ENCCMP_Pos) /**< (AES_INTENCLR) Encryption Complete Interrupt Enable Mask */
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#define AES_INTENCLR_ENCCMP(value) (AES_INTENCLR_ENCCMP_Msk & ((value) << AES_INTENCLR_ENCCMP_Pos))
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#define AES_INTENCLR_GFMCMP_Pos _U_(1) /**< (AES_INTENCLR) GF Multiplication Complete Interrupt Enable Position */
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#define AES_INTENCLR_GFMCMP_Msk (_U_(0x1) << AES_INTENCLR_GFMCMP_Pos) /**< (AES_INTENCLR) GF Multiplication Complete Interrupt Enable Mask */
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#define AES_INTENCLR_GFMCMP(value) (AES_INTENCLR_GFMCMP_Msk & ((value) << AES_INTENCLR_GFMCMP_Pos))
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#define AES_INTENCLR_Msk _U_(0x03) /**< (AES_INTENCLR) Register Mask */
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/* -------- AES_INTENSET : (AES Offset: 0x06) (R/W 8) Interrupt Enable Set -------- */
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#define AES_INTENSET_RESETVALUE _U_(0x00) /**< (AES_INTENSET) Interrupt Enable Set Reset Value */
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#define AES_INTENSET_ENCCMP_Pos _U_(0) /**< (AES_INTENSET) Encryption Complete Interrupt Enable Position */
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#define AES_INTENSET_ENCCMP_Msk (_U_(0x1) << AES_INTENSET_ENCCMP_Pos) /**< (AES_INTENSET) Encryption Complete Interrupt Enable Mask */
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#define AES_INTENSET_ENCCMP(value) (AES_INTENSET_ENCCMP_Msk & ((value) << AES_INTENSET_ENCCMP_Pos))
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#define AES_INTENSET_GFMCMP_Pos _U_(1) /**< (AES_INTENSET) GF Multiplication Complete Interrupt Enable Position */
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#define AES_INTENSET_GFMCMP_Msk (_U_(0x1) << AES_INTENSET_GFMCMP_Pos) /**< (AES_INTENSET) GF Multiplication Complete Interrupt Enable Mask */
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#define AES_INTENSET_GFMCMP(value) (AES_INTENSET_GFMCMP_Msk & ((value) << AES_INTENSET_GFMCMP_Pos))
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#define AES_INTENSET_Msk _U_(0x03) /**< (AES_INTENSET) Register Mask */
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/* -------- AES_INTFLAG : (AES Offset: 0x07) (R/W 8) Interrupt Flag Status -------- */
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#define AES_INTFLAG_RESETVALUE _U_(0x00) /**< (AES_INTFLAG) Interrupt Flag Status Reset Value */
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#define AES_INTFLAG_ENCCMP_Pos _U_(0) /**< (AES_INTFLAG) Encryption Complete Position */
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#define AES_INTFLAG_ENCCMP_Msk (_U_(0x1) << AES_INTFLAG_ENCCMP_Pos) /**< (AES_INTFLAG) Encryption Complete Mask */
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#define AES_INTFLAG_ENCCMP(value) (AES_INTFLAG_ENCCMP_Msk & ((value) << AES_INTFLAG_ENCCMP_Pos))
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#define AES_INTFLAG_GFMCMP_Pos _U_(1) /**< (AES_INTFLAG) GF Multiplication Complete Position */
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#define AES_INTFLAG_GFMCMP_Msk (_U_(0x1) << AES_INTFLAG_GFMCMP_Pos) /**< (AES_INTFLAG) GF Multiplication Complete Mask */
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#define AES_INTFLAG_GFMCMP(value) (AES_INTFLAG_GFMCMP_Msk & ((value) << AES_INTFLAG_GFMCMP_Pos))
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#define AES_INTFLAG_Msk _U_(0x03) /**< (AES_INTFLAG) Register Mask */
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/* -------- AES_DATABUFPTR : (AES Offset: 0x08) (R/W 8) Data buffer pointer -------- */
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#define AES_DATABUFPTR_RESETVALUE _U_(0x00) /**< (AES_DATABUFPTR) Data buffer pointer Reset Value */
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#define AES_DATABUFPTR_INDATAPTR_Pos _U_(0) /**< (AES_DATABUFPTR) Input Data Pointer Position */
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#define AES_DATABUFPTR_INDATAPTR_Msk (_U_(0x3) << AES_DATABUFPTR_INDATAPTR_Pos) /**< (AES_DATABUFPTR) Input Data Pointer Mask */
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#define AES_DATABUFPTR_INDATAPTR(value) (AES_DATABUFPTR_INDATAPTR_Msk & ((value) << AES_DATABUFPTR_INDATAPTR_Pos))
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#define AES_DATABUFPTR_Msk _U_(0x03) /**< (AES_DATABUFPTR) Register Mask */
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/* -------- AES_DBGCTRL : (AES Offset: 0x09) (R/W 8) Debug control -------- */
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#define AES_DBGCTRL_RESETVALUE _U_(0x00) /**< (AES_DBGCTRL) Debug control Reset Value */
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#define AES_DBGCTRL_DBGRUN_Pos _U_(0) /**< (AES_DBGCTRL) Debug Run Position */
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#define AES_DBGCTRL_DBGRUN_Msk (_U_(0x1) << AES_DBGCTRL_DBGRUN_Pos) /**< (AES_DBGCTRL) Debug Run Mask */
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#define AES_DBGCTRL_DBGRUN(value) (AES_DBGCTRL_DBGRUN_Msk & ((value) << AES_DBGCTRL_DBGRUN_Pos))
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#define AES_DBGCTRL_Msk _U_(0x01) /**< (AES_DBGCTRL) Register Mask */
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/* -------- AES_KEYWORD : (AES Offset: 0x0C) ( /W 32) Keyword n -------- */
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#define AES_KEYWORD_RESETVALUE _U_(0x00) /**< (AES_KEYWORD) Keyword n Reset Value */
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#define AES_KEYWORD_Msk _U_(0x00000000) /**< (AES_KEYWORD) Register Mask */
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/* -------- AES_INDATA : (AES Offset: 0x38) (R/W 32) Indata -------- */
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#define AES_INDATA_RESETVALUE _U_(0x00) /**< (AES_INDATA) Indata Reset Value */
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#define AES_INDATA_Msk _U_(0x00000000) /**< (AES_INDATA) Register Mask */
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/* -------- AES_INTVECTV : (AES Offset: 0x3C) ( /W 32) Initialisation Vector n -------- */
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#define AES_INTVECTV_RESETVALUE _U_(0x00) /**< (AES_INTVECTV) Initialisation Vector n Reset Value */
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#define AES_INTVECTV_Msk _U_(0x00000000) /**< (AES_INTVECTV) Register Mask */
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/* -------- AES_HASHKEY : (AES Offset: 0x5C) (R/W 32) Hash key n -------- */
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#define AES_HASHKEY_RESETVALUE _U_(0x00) /**< (AES_HASHKEY) Hash key n Reset Value */
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#define AES_HASHKEY_Msk _U_(0x00000000) /**< (AES_HASHKEY) Register Mask */
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/* -------- AES_GHASH : (AES Offset: 0x6C) (R/W 32) Galois Hash n -------- */
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#define AES_GHASH_RESETVALUE _U_(0x00) /**< (AES_GHASH) Galois Hash n Reset Value */
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#define AES_GHASH_Msk _U_(0x00000000) /**< (AES_GHASH) Register Mask */
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/* -------- AES_CIPLEN : (AES Offset: 0x80) (R/W 32) Cipher Length -------- */
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#define AES_CIPLEN_RESETVALUE _U_(0x00) /**< (AES_CIPLEN) Cipher Length Reset Value */
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#define AES_CIPLEN_Msk _U_(0x00000000) /**< (AES_CIPLEN) Register Mask */
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/* -------- AES_RANDSEED : (AES Offset: 0x84) (R/W 32) Random Seed -------- */
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#define AES_RANDSEED_RESETVALUE _U_(0x00) /**< (AES_RANDSEED) Random Seed Reset Value */
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#define AES_RANDSEED_Msk _U_(0x00000000) /**< (AES_RANDSEED) Register Mask */
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/** \brief AES register offsets definitions */
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#define AES_CTRLA_REG_OFST (0x00) /**< (AES_CTRLA) Control A Offset */
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#define AES_CTRLB_REG_OFST (0x04) /**< (AES_CTRLB) Control B Offset */
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#define AES_INTENCLR_REG_OFST (0x05) /**< (AES_INTENCLR) Interrupt Enable Clear Offset */
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#define AES_INTENSET_REG_OFST (0x06) /**< (AES_INTENSET) Interrupt Enable Set Offset */
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#define AES_INTFLAG_REG_OFST (0x07) /**< (AES_INTFLAG) Interrupt Flag Status Offset */
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#define AES_DATABUFPTR_REG_OFST (0x08) /**< (AES_DATABUFPTR) Data buffer pointer Offset */
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#define AES_DBGCTRL_REG_OFST (0x09) /**< (AES_DBGCTRL) Debug control Offset */
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#define AES_KEYWORD_REG_OFST (0x0C) /**< (AES_KEYWORD) Keyword n Offset */
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#define AES_INDATA_REG_OFST (0x38) /**< (AES_INDATA) Indata Offset */
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#define AES_INTVECTV_REG_OFST (0x3C) /**< (AES_INTVECTV) Initialisation Vector n Offset */
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#define AES_HASHKEY_REG_OFST (0x5C) /**< (AES_HASHKEY) Hash key n Offset */
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#define AES_GHASH_REG_OFST (0x6C) /**< (AES_GHASH) Galois Hash n Offset */
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#define AES_CIPLEN_REG_OFST (0x80) /**< (AES_CIPLEN) Cipher Length Offset */
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#define AES_RANDSEED_REG_OFST (0x84) /**< (AES_RANDSEED) Random Seed Offset */
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#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
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/** \brief AES register API structure */
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typedef struct
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{ /* Advanced Encryption Standard */
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__IO uint32_t AES_CTRLA; /**< Offset: 0x00 (R/W 32) Control A */
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__IO uint8_t AES_CTRLB; /**< Offset: 0x04 (R/W 8) Control B */
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__IO uint8_t AES_INTENCLR; /**< Offset: 0x05 (R/W 8) Interrupt Enable Clear */
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__IO uint8_t AES_INTENSET; /**< Offset: 0x06 (R/W 8) Interrupt Enable Set */
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__IO uint8_t AES_INTFLAG; /**< Offset: 0x07 (R/W 8) Interrupt Flag Status */
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__IO uint8_t AES_DATABUFPTR; /**< Offset: 0x08 (R/W 8) Data buffer pointer */
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__IO uint8_t AES_DBGCTRL; /**< Offset: 0x09 (R/W 8) Debug control */
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__I uint8_t Reserved1[0x02];
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__O uint32_t AES_KEYWORD[8]; /**< Offset: 0x0C ( /W 32) Keyword n */
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__I uint8_t Reserved2[0x0C];
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__IO uint32_t AES_INDATA; /**< Offset: 0x38 (R/W 32) Indata */
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__O uint32_t AES_INTVECTV[4]; /**< Offset: 0x3C ( /W 32) Initialisation Vector n */
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__I uint8_t Reserved3[0x10];
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__IO uint32_t AES_HASHKEY[4]; /**< Offset: 0x5C (R/W 32) Hash key n */
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__IO uint32_t AES_GHASH[4]; /**< Offset: 0x6C (R/W 32) Galois Hash n */
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__I uint8_t Reserved4[0x04];
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__IO uint32_t AES_CIPLEN; /**< Offset: 0x80 (R/W 32) Cipher Length */
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__IO uint32_t AES_RANDSEED; /**< Offset: 0x84 (R/W 32) Random Seed */
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} aes_registers_t;
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#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
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#endif /* _SAME54_AES_COMPONENT_H_ */
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